diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h index 9c3295068b..ddff7eb30e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h @@ -8,17 +8,15 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCX N1xNxxx Reference Manual -** Version: rev. 1.0, 2022-10-01 -** Build: b230203 +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 2.0, 2023-02-01 +** Build: b240510 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN947_cm33_core0 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP -** All rights reserved. -** +** Copyright 2016-2024 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,26 +24,28 @@ ** ** Revisions: ** - rev. 1.0 (2022-10-01) -** Initial version based on SPEC1.14 +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN947_cm33_core0.h - * @version 1.0 - * @date 2022-10-01 + * @version 2.0 + * @date 2023-02-01 * @brief CMSIS Peripheral Access Layer for MCXN947_cm33_core0 * * CMSIS Peripheral Access Layer for MCXN947_cm33_core0 */ -#ifndef _MCXN947_CM33_CORE0_H_ -#define _MCXN947_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(MCXN947_CM33_CORE0_H_) +#define MCXN947_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -203,14 +203,14 @@ typedef enum IRQn { FLEXPWM1_SUBMODULE1_IRQn = 121, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE2_IRQn = 122, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE3_IRQn = 123, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ - ENC0_COMPARE_IRQn = 124, /**< ENC0_Compare interrupt */ - ENC0_HOME_IRQn = 125, /**< ENC0_Home interrupt */ - ENC0_WDG_SAB_IRQn = 126, /**< ENC0_WDG_IRQ/SAB interrupt */ - ENC0_IDX_IRQn = 127, /**< ENC0_IDX interrupt */ - ENC1_COMPARE_IRQn = 128, /**< ENC1_Compare interrupt */ - ENC1_HOME_IRQn = 129, /**< ENC1_Home interrupt */ - ENC1_WDG_SAB_IRQn = 130, /**< ENC1_WDG_IRQ/SAB interrupt */ - ENC1_IDX_IRQn = 131, /**< ENC1_IDX interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ + QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ + QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ + QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ ELS_ERR_IRQn = 134, /**< ELS error interrupt */ @@ -229,8 +229,8 @@ typedef enum IRQn { WUU_IRQn = 147, /**< Wake Up Unit interrupt */ PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ ETB0_IRQn = 149, /**< ETB counter expires interrupt */ - SM3_IRQn = 150, /**< Secure Generic Interface (SGI) SAFO interrupt */ - TRNG0_IRQn = 151, /**< True Random Number Generator interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ @@ -276,6 +276,262 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestMuxFlexSpi0Rx = 1U, /**< FlexSPI0 Receive event */ + kDma1RequestMuxFlexSpi0Rx = 1U, /**< FlexSPI0 Receive event */ + kDma0RequestMuxFlexSpi0Tx = 2U, /**< FlexSPI0 Transmit event */ + kDma1RequestMuxFlexSpi0Tx = 2U, /**< FlexSPI0 Transmit event */ + kDma0RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma1RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma0RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma1RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma0RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma1RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma0RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma1RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma0RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma1RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma1RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma1RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma1RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma1RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma1RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma1RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma1RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma1RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma1RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma1RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma0RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma1RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma0RequestMuxSct0Dma0 = 19U, /**< SCT0 DMA0 */ + kDma1RequestMuxSct0Dma0 = 19U, /**< SCT0 DMA0 */ + kDma0RequestMuxSct0Dma1 = 20U, /**< SCT0 DMA1 */ + kDma1RequestMuxSct0Dma1 = 20U, /**< SCT0 DMA1 */ + kDma0RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma1RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma0RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma1RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma0RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma1RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma0RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma0RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ + kDma1RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ + kDma0RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ + kDma1RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ + kDma0RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ + kDma1RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ + kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma1RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma0RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ + kDma1RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ + kDma0RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma1RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma0RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma1RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma0RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma1RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma0RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma1RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma0RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma1RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma0RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma1RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma0RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma1RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma0RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma1RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma0RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma1RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma0RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma1RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma0RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma1RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma0RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma1RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma0RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma1RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma0RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma1RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma0RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma0RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma1RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma0RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma1RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma0RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma1RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma0RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma1RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma0RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma1RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma0RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma1RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma0RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma1RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma0RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma1RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma0RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma1RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma0RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma1RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma0RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma1RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma0RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma1RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma0RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma1RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma0RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma1RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma0RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma1RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma0RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma1RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma0RequestMuxLpFlexcomm8Rx = 85U, /**< LP_FLEXCOMM8 Receive request */ + kDma1RequestMuxLpFlexcomm8Rx = 85U, /**< LP_FLEXCOMM8 Receive request */ + kDma0RequestMuxLpFlexcomm8Tx = 86U, /**< LP_FLEXCOMM8 Transmit request */ + kDma1RequestMuxLpFlexcomm8Tx = 86U, /**< LP_FLEXCOMM8 Transmit request */ + kDma0RequestMuxLpFlexcomm9Rx = 87U, /**< LP_FLEXCOMM9 Receive request */ + kDma1RequestMuxLpFlexcomm9Rx = 87U, /**< LP_FLEXCOMM9 Receive request */ + kDma0RequestMuxLpFlexcomm9Tx = 88U, /**< LP_FLEXCOMM9 Transmit request */ + kDma1RequestMuxLpFlexcomm9Tx = 88U, /**< LP_FLEXCOMM9 Transmit request */ + kDma0RequestMuxEmvSim0Rx = 91U, /**< EMVSIM0 Receive request */ + kDma1RequestMuxEmvSim0Rx = 91U, /**< EMVSIM0 Receive request */ + kDma0RequestMuxEmvSim0Tx = 92U, /**< EMVSIM0 Transmit request */ + kDma1RequestMuxEmvSim0Tx = 92U, /**< EMVSIM0 Transmit request */ + kDma0RequestMuxEmvSim1Rx = 93U, /**< EMVSIM1 Receive request */ + kDma1RequestMuxEmvSim1Rx = 93U, /**< EMVSIM1 Receive request */ + kDma0RequestMuxEmvSim1Tx = 94U, /**< EMVSIM1 Transmit request */ + kDma1RequestMuxEmvSim1Tx = 94U, /**< EMVSIM1 Transmit request */ + kDma0RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma1RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma1RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma0RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma1RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma0RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma1RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma0RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma1RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma0RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma1RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma0RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma0RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ + kDma1RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ + kDma0RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ + kDma1RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ + kDma0RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ + kDma1RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ + kDma0RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ + kDma1RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ + kDma0RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ + kDma1RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ + kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma1RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma0RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma1RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma1RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma0RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma1RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma1RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma0RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma1RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma1RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma0RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma1RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma1RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma0RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma0RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ + kDma1RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ + kDma0RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ + kDma1RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ +} dma_request_source_t; + +/* @} */ + /*! * @addtogroup eim_memory_channel * @{ @@ -323,7 +579,7 @@ typedef enum _eim_memory_channel typedef enum _eim_error_injection_channel_enable { - kEIM_MemoryChannelRAMXEnable = +0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ + kEIM_MemoryChannelRAMXEnable = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ kEIM_MemoryChannelRAMAEnable = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable */ kEIM_MemoryChannelRAMBEnable = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */ kEIM_MemoryChannelRAMCEnable = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */ @@ -1280,7 +1536,7 @@ typedef struct { /*! TSRC - Trigger Source * 0b00..Trigger source 0 * 0b01..Trigger source 1 - * 0b10-0b10..Corresponding trigger source initiated this conversion. + * 0b10..Trigger source 2 * 0b11..Trigger source 3 */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) @@ -2691,16 +2947,6 @@ typedef struct { */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) -#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_MASK (0x3000U) -#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_SHIFT (12U) -/*! SPI_FILTER - GPIO0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_MASK) - #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) /*! PINT0 - PINT0 @@ -6912,7 +7158,7 @@ typedef struct { #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x3000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (12U) -/*! SEC_CPU1_INT_MASK0_LOCK - SSEC_CPU1_INT_MASK0 Lock +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU1_INT_MASK0 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK0 cannot be written * 0b10..SEC_GPIO_MASK0 can be written @@ -6922,7 +7168,7 @@ typedef struct { #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (14U) -/*! SEC_CPU1_INT_MASK1_LOCK - SEC_GPIO_MASK1 Lock +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU1_INT_MASK1 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK1 cannot be written * 0b10..SEC_GPIO_MASK1 can be written @@ -7377,8 +7623,8 @@ typedef struct { #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) /*! DISABLE_STRICT_MODE - Disable Strict Mode * 0b00..Reserved - * 0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level. - * 0b10..Master strict mode is disabled and can access memories and peripherals at same level only + * 0b01..Master can access memories and peripherals at the same level or below that level. + * 0b10..Master can access memories and peripherals at same level only * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) @@ -7795,6 +8041,22 @@ typedef struct { */ #define CACHE64_CTRL_CCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK) +#define CACHE64_CTRL_CCR_FRCWT_MASK (0x4U) +#define CACHE64_CTRL_CCR_FRCWT_SHIFT (2U) +/*! FRCWT - Force Write Through Mode + * 0b0..Does not force + * 0b1..Force + */ +#define CACHE64_CTRL_CCR_FRCWT(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCWT_SHIFT)) & CACHE64_CTRL_CCR_FRCWT_MASK) + +#define CACHE64_CTRL_CCR_FRCNOALLC_MASK (0x8U) +#define CACHE64_CTRL_CCR_FRCNOALLC_SHIFT (3U) +/*! FRCNOALLC - Forces No Allocation On Cache Misses + * 0b0..Allocation on cache misses + * 0b1..Forces no allocation on cache misses (FRCWT must be asserted) + */ +#define CACHE64_CTRL_CCR_FRCNOALLC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCNOALLC_SHIFT)) & CACHE64_CTRL_CCR_FRCNOALLC_MASK) + #define CACHE64_CTRL_CCR_INVW0_MASK (0x1000000U) #define CACHE64_CTRL_CCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 @@ -7979,7 +8241,7 @@ typedef struct { /** Array initializer of CACHE64_CTRL peripheral base pointers */ #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } #endif -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** CACHE64_CTRL physical memory base address */ #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u} /** CACHE64_CTRL physical memory size */ @@ -8131,26 +8393,26 @@ typedef struct { /** CAN - Register Layout Typedef */ typedef struct { - __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ - __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ - __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; - __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ - __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ - __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ - __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ uint8_t RESERVED_1[4]; - __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ uint8_t RESERVED_2[4]; - __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ - __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ - __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ uint8_t RESERVED_3[8]; - __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ - __IO uint32_t RXFGMASK; /**< Legacy Rx FIFO Global Mask Register, offset: 0x48 */ - __I uint32_t RXFIR; /**< Legacy Rx FIFO Information Register, offset: 0x4C */ - __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ uint8_t RESERVED_4[44]; union { /* offset: 0x80 */ struct { /* offset: 0x80, array step: 0x10 */ @@ -8181,38 +8443,38 @@ typedef struct { } MB[32]; }; uint8_t RESERVED_5[1536]; - __IO uint32_t RXIMR[32]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_6[512]; - __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1 Register, offset: 0xB00 */ - __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2 Register, offset: 0xB04 */ - __IO uint32_t WU_MTC; /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */ - __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */ - __IO uint32_t FLT_DLC; /**< Pretended Networking DLC Filter Register, offset: 0xB10 */ - __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */ - __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */ - __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */ - __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register, offset: 0xB20 */ - __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */ + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ uint8_t RESERVED_7[24]; struct { /* offset: 0xB40, array step: 0x10 */ - __I uint32_t CS; /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */ - __I uint32_t ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */ - __I uint32_t D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */ - __I uint32_t D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ } WMB[4]; uint8_t RESERVED_8[112]; __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ - __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ - __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ - __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ - __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ - __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ - __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */ - __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ uint8_t RESERVED_9[9192]; - __IO uint32_t ERFFEL[32]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ + __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ } CAN_Type; /* ---------------------------------------------------------------------------- @@ -8224,12 +8486,12 @@ typedef struct { * @{ */ -/*! @name MCR - Module Configuration Register */ +/*! @name MCR - Module Configuration */ /*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) -/*! MAXMB - Number Of The Last Message Buffer */ +/*! MAXMB - Number of the Last Message Buffer */ #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) @@ -8244,159 +8506,158 @@ typedef struct { #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) -/*! FDEN - CAN FD operation enable - * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. - * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. +/*! FDEN - CAN FD Operation Enable + * 0b1..Enable + * 0b0..Disable */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable - * 0b0..Abort disabled. - * 0b1..Abort enabled. + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable - * 0b0..Local Priority disabled. - * 0b1..Local Priority enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_PNET_EN_MASK (0x4000U) #define CAN_MCR_PNET_EN_SHIFT (14U) /*! PNET_EN - Pretended Networking Enable - * 0b0..Pretended Networking mode is disabled. - * 0b1..Pretended Networking mode is enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable - * 0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO disabled. - * 0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) -/*! IRMQ - Individual Rx Masking And Queue Enable - * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy - * applications, the reading of C/S word locks the MB even if it is EMPTY. - * 0b1..Individual Rx masking and queue feature are enabled. +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) -/*! SRXDIS - Self Reception Disable - * 0b0..Self-reception enabled. - * 0b1..Self-reception disabled. +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) -/*! WAKSRC - Wake Up Source - * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. - * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge - * 0b0..FlexCAN is not in a low-power mode. - * 0b1..FlexCAN is in a low-power mode. + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable - * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. - * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) -/*! SLFWAK - Self Wake Up - * 0b0..FlexCAN Self Wake Up feature is disabled. - * 0b1..FlexCAN Self Wake Up feature is enabled. +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge - * 0b0..FlexCAN not in Freeze mode, prescaler running. - * 0b1..FlexCAN in Freeze mode, prescaler stopped. + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset - * 0b0..No reset request. - * 0b1..Resets the registers affected by soft reset. + * 0b0..No reset + * 0b1..Soft reset affects reset registers */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) -/*! WAKMSK - Wake Up Interrupt Mask - * 0b0..Wake Up interrupt is disabled. - * 0b1..Wake Up interrupt is enabled. +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready - * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. - * 0b1..FlexCAN module is either in Disable mode, Stop mode, or Freeze mode. + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN - * 0b0..No Freeze mode request. - * 0b1..Enters Freeze mode if the FRZ bit is asserted. + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) -/*! RFEN - Legacy Rx FIFO Enable - * 0b0..Legacy Rx FIFO not enabled. - * 0b1..Legacy Rx FIFO enabled. +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable - * 0b0..Not enabled to enter Freeze mode. - * 0b1..Enabled to enter Freeze mode. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable - * 0b0..Enable the FlexCAN module. - * 0b1..Disable the FlexCAN module. + * 0b0..Enable + * 0b1..Disable */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ -/*! @name CTRL1 - Control 1 Register */ +/*! @name CTRL1 - Control 1 */ /*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) @@ -8423,65 +8684,65 @@ typedef struct { #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync - * 0b0..Timer sync feature disabled - * 0b1..Timer sync feature enabled + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery - * 0b0..Automatic recovering from Bus Off state enabled. - * 0b1..Automatic recovering from Bus Off state disabled. + * 0b0..Enabled + * 0b1..Disabled */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling - * 0b0..Just one sample is used to determine the bit value. + * 0b0..One sample is used to determine the bit value. * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two - * preceding samples; a majority rule is used. + * preceding samples. A majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) -/*! RWRNMSK - Rx Warning Interrupt Mask - * 0b0..Rx Warning interrupt disabled. - * 0b1..Rx Warning interrupt enabled. +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) -/*! TWRNMSK - Tx Warning Interrupt Mask - * 0b0..Tx Warning interrupt disabled. - * 0b1..Tx Warning interrupt enabled. +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) -/*! LPB - Loop Back Mode - * 0b0..Loop Back disabled. - * 0b1..Loop Back enabled. +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask - * 0b0..Error interrupt disabled. - * 0b1..Error interrupt enabled. + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask - * 0b0..Bus Off interrupt disabled. - * 0b1..Bus Off interrupt enabled. + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) @@ -8506,7 +8767,7 @@ typedef struct { #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @} */ -/*! @name TIMER - Free Running Timer */ +/*! @name TIMER - Free-Running Timer */ /*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) @@ -8515,30 +8776,30 @@ typedef struct { #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @} */ -/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @name RXMGMASK - RX Message Buffers Global Mask */ /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) -/*! MG - Rx Mailboxes Global Mask Bits */ +/*! MG - Global Mask for RX Message Buffers */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ -/*! @name RX14MASK - Rx 14 Mask Register */ +/*! @name RX14MASK - Receive 14 Mask */ /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) -/*! RX14M - Rx Buffer 14 Mask Bits */ +/*! RX14M - RX Buffer 14 Mask Bits */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ -/*! @name RX15MASK - Rx 15 Mask Register */ +/*! @name RX15MASK - Receive 15 Mask */ /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) -/*! RX15M - Rx Buffer 15 Mask Bits */ +/*! RX15M - RX Buffer 15 Mask Bits */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ @@ -8557,37 +8818,37 @@ typedef struct { #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) -/*! TXERRCNT_FAST - Transmit Error Counter for fast bits */ +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) -/*! RXERRCNT_FAST - Receive Error Counter for fast bits */ +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) /*! @} */ -/*! @name ESR1 - Error and Status 1 Register */ +/*! @name ESR1 - Error and Status 1 */ /*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) -/*! WAKINT - Wake-Up Interrupt +/*! WAKINT - Wake-up Interrupt Flag * 0b0..No such occurrence. - * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) -/*! ERRINT - Error Interrupt +/*! ERRINT - Error Interrupt Flag * 0b0..No such occurrence. - * 0b1..Indicates setting of any error bit in the Error and Status register. + * 0b1..Indicates setting of any error flag in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) -/*! BOFFINT - Bus Off Interrupt +/*! BOFFINT - Bus Off Interrupt Flag * 0b0..No such occurrence. * 0b1..FlexCAN module entered Bus Off state. */ @@ -8595,9 +8856,9 @@ typedef struct { #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) -/*! RX - FlexCAN In Reception - * 0b0..FlexCAN is not receiving a message. - * 0b1..FlexCAN is receiving a message. +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) @@ -8613,22 +8874,22 @@ typedef struct { #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission - * 0b0..FlexCAN is not transmitting a message. - * 0b1..FlexCAN is transmitting a message. + * 0b0..Not transmitting + * 0b1..Transmitting */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) -/*! IDLE - IDLE - * 0b0..No such occurrence. - * 0b1..CAN bus is now IDLE. +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) -/*! RXWRN - Rx Error Warning +/*! RXWRN - RX Error Warning Flag * 0b0..No such occurrence. * 0b1..RXERRCNT is greater than or equal to 96. */ @@ -8636,47 +8897,47 @@ typedef struct { #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) -/*! TXWRN - TX Error Warning +/*! TXWRN - TX Error Warning Flag * 0b0..No such occurrence. - * 0b1..TXERRCNT is greater than or equal to 96. + * 0b1..TXERRCNT is 96 or greater. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) -/*! STFERR - Stuffing Error - * 0b0..No such occurrence. - * 0b1..A stuffing error occurred since last read of this register. +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) -/*! FRMERR - Form Error - * 0b0..No such occurrence. - * 0b1..A Form Error occurred since last read of this register. +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) -/*! CRCERR - Cyclic Redundancy Check Error - * 0b0..No such occurrence. - * 0b1..A CRC error occurred since last read of this register. +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) -/*! ACKERR - Acknowledge Error - * 0b0..No such occurrence. - * 0b1..An ACK error occurred since last read of this register. +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) -/*! BIT0ERR - Bit0 Error +/*! BIT0ERR - Bit0 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ @@ -8684,7 +8945,7 @@ typedef struct { #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) -/*! BIT1ERR - Bit1 Error +/*! BIT1ERR - Bit1 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ @@ -8692,55 +8953,55 @@ typedef struct { #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) -/*! RWRNINT - Rx Warning Interrupt Flag - * 0b0..No such occurrence. - * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) -/*! TWRNINT - Tx Warning Interrupt Flag - * 0b0..No such occurrence. - * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) -/*! SYNCH - CAN Synchronization Status - * 0b0..FlexCAN is not synchronized to the CAN bus. - * 0b1..FlexCAN is synchronized to the CAN bus. +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) -/*! BOFFDONEINT - Bus Off Done Interrupt - * 0b0..No such occurrence. +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) -/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set +/*! ERRINT_FAST - Fast Error Interrupt Flag * 0b0..No such occurrence. - * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) -/*! ERROVR - Error Overrun - * 0b0..Overrun has not occurred. - * 0b1..Overrun has occurred. +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) -/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set +/*! STFERR_FAST - Fast Stuffing Error Flag * 0b0..No such occurrence. * 0b1..A stuffing error occurred since last read of this register. */ @@ -8748,7 +9009,7 @@ typedef struct { #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) -/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set +/*! FRMERR_FAST - Fast Form Error Flag * 0b0..No such occurrence. * 0b1..A form error occurred since last read of this register. */ @@ -8756,7 +9017,7 @@ typedef struct { #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) -/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ @@ -8764,22 +9025,22 @@ typedef struct { #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) -/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set +/*! BIT0ERR_FAST - Fast Bit0 Error Flag * 0b0..No such occurrence. - * 0b1..At least one bit sent as dominant is received as recessive. + * 0b1..At least one bit transmitted as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) -/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set +/*! BIT1ERR_FAST - Fast Bit1 Error Flag * 0b0..No such occurrence. - * 0b1..At least one bit sent as recessive is received as dominant. + * 0b1..At least one bit transmitted as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) /*! @} */ -/*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @name IMASK1 - Interrupt Masks 1 */ /*! @{ */ #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) @@ -8788,44 +9049,43 @@ typedef struct { #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) /*! @} */ -/*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @name IFLAG1 - Interrupt Flags 1 */ /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) -/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit - * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. - * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) -/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */ +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) -/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Legacy Rx FIFO - * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when MCR[RFEN]=1 - * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when - * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) -/*! BUF6I - Buffer MB6 Interrupt Or Legacy Rx FIFO Warning - * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO almost full when MCR[RFEN]=1 - * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO almost full when MCR[RFEN]=1 +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) -/*! BUF7I - Buffer MB7 Interrupt Or Legacy Rx FIFO Overflow - * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO overflow when MCR[RFEN]=1 - * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO overflow when MCR[RFEN]=1 +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) @@ -8835,119 +9095,118 @@ typedef struct { #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ -/*! @name CTRL2 - Control 2 Register */ +/*! @name CTRL2 - Control 2 */ /*! @{ */ #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) /*! EDFLTDIS - Edge Filter Disable - * 0b0..Edge filter is enabled - * 0b1..Edge filter is disabled + * 0b0..Enabled + * 0b1..Disabled */ #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable - * 0b0..FlexCAN operates using the non-ISO CAN FD protocol. - * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1:2015). + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_BTE_MASK (0x2000U) #define CAN_CTRL2_BTE_SHIFT (13U) -/*! BTE - Bit Timing Expansion enable - * 0b0..CAN Bit timing expansion is disabled. - * 0b1..CAN bit timing expansion is enabled. +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) #define CAN_CTRL2_PREXCEN_MASK (0x4000U) #define CAN_CTRL2_PREXCEN_SHIFT (14U) /*! PREXCEN - Protocol Exception Enable - * 0b0..Protocol exception is disabled. - * 0b1..Protocol exception is enabled. + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) -/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes - * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. - * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within - * the incoming frame. Mask bits do apply. +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing - * 0b0..Remote response frame is generated. - * 0b1..Remote request frame is stored. + * 0b0..Generated + * 0b1..Stored */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) -/*! MRP - Mailboxes Reception Priority - * 0b0..Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on mailboxes. - * 0b1..Matching starts from mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO. +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) -/*! TASD - Tx Arbitration Start Delay */ +/*! TASD - Transmission Arbitration Start Delay */ #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) -/*! RFFN - Number Of Legacy Rx FIFO Filters */ +/*! RFFN - Number of Legacy Receive FIFO Filters */ #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask - * 0b0..Bus off done interrupt disabled. - * 0b1..Bus off done interrupt enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) -/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames - * 0b0..ERRINT_FAST error interrupt disabled. - * 0b1..ERRINT_FAST error interrupt enabled. +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) /*! @} */ -/*! @name ESR2 - Error and Status 2 Register */ +/*! @name ESR2 - Error and Status 2 */ /*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) -/*! IMB - Inactive Mailbox - * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. - * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status - * 0b0..Contents of IMB and LPTM are invalid. - * 0b1..Contents of IMB and LPTM are valid. + * 0b0..Invalid + * 0b1..Valid */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) -/*! LPTM - Lowest Priority Tx Mailbox */ +/*! LPTM - Lowest Priority TX Message Buffer */ #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @} */ -/*! @name CRCR - CRC Register */ +/*! @name CRCR - Cyclic Redundancy Check */ /*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) @@ -8957,20 +9216,20 @@ typedef struct { #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) -/*! MBCRC - CRC Mailbox */ +/*! MBCRC - CRC Message Buffer */ #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @} */ -/*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register */ +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) -/*! FGM - Legacy Rx FIFO Global Mask Bits */ +/*! FGM - Legacy RX FIFO Global Mask Bits */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ -/*! @name RXFIR - Legacy Rx FIFO Information Register */ +/*! @name RXFIR - Legacy RX FIFO Information */ /*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) @@ -8979,7 +9238,7 @@ typedef struct { #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @} */ -/*! @name CBT - CAN Bit Timing Register */ +/*! @name CBT - CAN Bit Timing */ /*! @{ */ #define CAN_CBT_EPSEG2_MASK (0x1FU) @@ -9010,8 +9269,8 @@ typedef struct { #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable - * 0b0..Extended bit time definitions disabled. - * 0b1..Extended bit time definitions enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ @@ -9526,7 +9785,7 @@ typedef struct { /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (32U) -/*! @name RXIMR - Rx Individual Mask Registers */ +/*! @name RXIMR - Receive Individual Mask */ /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) @@ -9538,7 +9797,7 @@ typedef struct { /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (32U) -/*! @name CTRL1_PN - Pretended Networking Control 1 Register */ +/*! @name CTRL1_PN - Pretended Networking Control 1 */ /*! @{ */ #define CAN_CTRL1_PN_FCS_MASK (0x3U) @@ -9554,52 +9813,50 @@ typedef struct { #define CAN_CTRL1_PN_IDFS_MASK (0xCU) #define CAN_CTRL1_PN_IDFS_SHIFT (2U) /*! IDFS - ID Filtering Selection - * 0b00..Match upon ID contents against an exact target value - * 0b01..Match upon an ID value greater than or equal to a specified target value - * 0b10..Match upon an ID value smaller than or equal to a specified target value - * 0b11..Match upon an ID value inside a range, greater than or equal to a specified lower limit, and smaller - * than or equal to a specified upper limit + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive */ #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) #define CAN_CTRL1_PN_PLFS_MASK (0x30U) #define CAN_CTRL1_PN_PLFS_SHIFT (4U) /*! PLFS - Payload Filtering Selection - * 0b00..Match upon a payload contents against an exact target value - * 0b01..Match upon a payload value greater than or equal to a specified target value - * 0b10..Match upon a payload value smaller than or equal to a specified target value - * 0b11..Match upon a payload value inside a range, greater than or equal to a specified lower limit, and smaller - * than or equal to a specified upper limit + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive */ #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) #define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) #define CAN_CTRL1_PN_NMATCH_SHIFT (8U) /*! NMATCH - Number of Messages Matching the Same Filtering Criteria - * 0b00000001..Received message must match the predefined filtering criteria for ID and/or PL once before generating a wakeup event. - * 0b00000010..Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wakeup event. - * 0b11111111..Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wakeup event. + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times */ #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) #define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) #define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) -/*! WUMF_MSK - Wake Up by Match Flag Mask Bit - * 0b0..Wakeup match event is disabled - * 0b1..Wakeup match event is enabled +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) #define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) #define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) -/*! WTOF_MSK - Wake Up by Timeout Flag Mask Bit - * 0b0..Timeout wakeup event is disabled - * 0b1..Timeout wakeup event is enabled +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) /*! @} */ -/*! @name CTRL2_PN - Pretended Networking Control 2 Register */ +/*! @name CTRL2_PN - Pretended Networking Control 2 */ /*! @{ */ #define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) @@ -9608,32 +9865,32 @@ typedef struct { #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) /*! @} */ -/*! @name WU_MTC - Pretended Networking Wake Up Match Register */ +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ /*! @{ */ #define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) #define CAN_WU_MTC_MCOUNTER_SHIFT (8U) -/*! MCOUNTER - Number of Matches when in Pretended Networking */ +/*! MCOUNTER - Number of Matches in Pretended Networking */ #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) #define CAN_WU_MTC_WUMF_MASK (0x10000U) #define CAN_WU_MTC_WUMF_SHIFT (16U) -/*! WUMF - Wake Up by Match Flag Bit - * 0b0..No wakeup by match event detected - * 0b1..Wakeup by match event detected +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected */ #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) #define CAN_WU_MTC_WTOF_MASK (0x20000U) #define CAN_WU_MTC_WTOF_SHIFT (17U) -/*! WTOF - Wake Up by Timeout Flag Bit - * 0b0..No wakeup by timeout event detected - * 0b1..Wakeup by timeout event detected +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected */ #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) /*! @} */ -/*! @name FLT_ID1 - Pretended Networking ID Filter 1 Register */ +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ /*! @{ */ #define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) @@ -9652,13 +9909,13 @@ typedef struct { #define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) #define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) /*! FLT_IDE - ID Extended Filter - * 0b0..Accept standard frame format - * 0b1..Accept extended frame format + * 0b0..Standard + * 0b1..Extended */ #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) /*! @} */ -/*! @name FLT_DLC - Pretended Networking DLC Filter Register */ +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ /*! @{ */ #define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) @@ -9672,144 +9929,128 @@ typedef struct { #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) /*! @} */ -/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 Register */ +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ /*! @{ */ #define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) #define CAN_PL1_LO_Data_byte_3_SHIFT (0U) -/*! Data_byte_3 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 3. */ +/*! Data_byte_3 - Data byte 3 */ #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) #define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) #define CAN_PL1_LO_Data_byte_2_SHIFT (8U) -/*! Data_byte_2 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2. */ +/*! Data_byte_2 - Data byte 2 */ #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) #define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) #define CAN_PL1_LO_Data_byte_1_SHIFT (16U) -/*! Data_byte_1 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 1. */ +/*! Data_byte_1 - Data byte 1 */ #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) #define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) #define CAN_PL1_LO_Data_byte_0_SHIFT (24U) -/*! Data_byte_0 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 0. */ +/*! Data_byte_0 - Data byte 0 */ #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) /*! @} */ -/*! @name PL1_HI - Pretended Networking Payload High Filter 1 Register */ +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ /*! @{ */ #define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) #define CAN_PL1_HI_Data_byte_7_SHIFT (0U) -/*! Data_byte_7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 7. */ +/*! Data_byte_7 - Data byte 7 */ #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) #define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) #define CAN_PL1_HI_Data_byte_6_SHIFT (8U) -/*! Data_byte_6 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 6. */ +/*! Data_byte_6 - Data byte 6 */ #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) #define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) #define CAN_PL1_HI_Data_byte_5_SHIFT (16U) -/*! Data_byte_5 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 5. */ +/*! Data_byte_5 - Data byte 5 */ #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) #define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) #define CAN_PL1_HI_Data_byte_4_SHIFT (24U) -/*! Data_byte_4 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 4. */ +/*! Data_byte_4 - Data byte 4 */ #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) /*! @} */ -/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 Register / ID Mask Register */ +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ /*! @{ */ #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) -/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering */ +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) -/*! RTR_MSK - Remote Transmission Request Mask Bit - * 0b0..The corresponding bit in the filter is "don't care" - * 0b1..The corresponding bit in the filter is checked +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. */ #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) -/*! IDE_MSK - ID Extended Mask Bit - * 0b0..The corresponding bit in the filter is "don't care" - * 0b1..The corresponding bit in the filter is checked +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. */ #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) /*! @} */ -/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register */ +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ /*! @{ */ #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) -/*! Data_byte_3 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 3. - */ +/*! Data_byte_3 - Data Byte 3 */ #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) -/*! Data_byte_2 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 2. - */ +/*! Data_byte_2 - Data Byte 2 */ #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) -/*! Data_byte_1 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 1. - */ +/*! Data_byte_1 - Data Byte 1 */ #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) -/*! Data_byte_0 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 0. - */ +/*! Data_byte_0 - Data Byte 0 */ #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) /*! @} */ -/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */ +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ /*! @{ */ #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) -/*! Data_byte_7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 7. - */ +/*! Data_byte_7 - Data Byte 7 */ #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) -/*! Data_byte_6 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 6. - */ +/*! Data_byte_6 - Data Byte 6 */ #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) -/*! Data_byte_5 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 5. - */ +/*! Data_byte_5 - Data Byte 5 */ #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) -/*! Data_byte_4 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 4. - */ +/*! Data_byte_4 - Data Byte 4 */ #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) /*! @} */ -/*! @name WMB_CS - Wake Up Message Buffer register for C/S */ +/*! @name WMB_CS - Wake-Up Message Buffer */ /*! @{ */ #define CAN_WMB_CS_DLC_MASK (0xF0000U) @@ -9819,89 +10060,92 @@ typedef struct { #define CAN_WMB_CS_RTR_MASK (0x100000U) #define CAN_WMB_CS_RTR_SHIFT (20U) -/*! RTR - Remote Transmission Request Bit - * 0b0..Frame is data one (not remote) - * 0b1..Frame is a remote one +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote */ #define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) #define CAN_WMB_CS_IDE_MASK (0x200000U) #define CAN_WMB_CS_IDE_SHIFT (21U) /*! IDE - ID Extended Bit - * 0b0..Frame format is standard - * 0b1..Frame format is extended + * 0b0..Standard + * 0b1..Extended */ #define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) #define CAN_WMB_CS_SRR_MASK (0x400000U) #define CAN_WMB_CS_SRR_SHIFT (22U) -/*! SRR - Substitute Remote Request */ +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ #define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) /*! @} */ /* The count of CAN_WMB_CS */ #define CAN_WMB_CS_COUNT (4U) -/*! @name WMB_ID - Wake Up Message Buffer Register for ID */ +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ /*! @{ */ #define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) #define CAN_WMB_ID_ID_SHIFT (0U) -/*! ID - Received ID under Pretended Networking mode */ +/*! ID - Received ID in Pretended Networking Mode */ #define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) /*! @} */ /* The count of CAN_WMB_ID */ #define CAN_WMB_ID_COUNT (4U) -/*! @name WMB_D03 - Wake Up Message Buffer Register for Data 0-3 */ +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ /*! @{ */ #define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) #define CAN_WMB_D03_Data_byte_3_SHIFT (0U) -/*! Data_byte_3 - Received payload corresponding to the data byte 3 under Pretended Networking mode */ +/*! Data_byte_3 - Data Byte 3 */ #define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) #define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) #define CAN_WMB_D03_Data_byte_2_SHIFT (8U) -/*! Data_byte_2 - Received payload corresponding to the data byte 2 under Pretended Networking mode */ +/*! Data_byte_2 - Data Byte 2 */ #define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) #define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) #define CAN_WMB_D03_Data_byte_1_SHIFT (16U) -/*! Data_byte_1 - Received payload corresponding to the data byte 1 under Pretended Networking mode */ +/*! Data_byte_1 - Data Byte 1 */ #define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) #define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) #define CAN_WMB_D03_Data_byte_0_SHIFT (24U) -/*! Data_byte_0 - Received payload corresponding to the data byte 0 under Pretended Networking mode */ +/*! Data_byte_0 - Data Byte 0 */ #define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) /*! @} */ /* The count of CAN_WMB_D03 */ #define CAN_WMB_D03_COUNT (4U) -/*! @name WMB_D47 - Wake Up Message Buffer Register Data 4-7 */ +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ /*! @{ */ #define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) #define CAN_WMB_D47_Data_byte_7_SHIFT (0U) -/*! Data_byte_7 - Received payload corresponding to the data byte 7 under Pretended Networking mode */ +/*! Data_byte_7 - Data Byte 7 */ #define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) #define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) #define CAN_WMB_D47_Data_byte_6_SHIFT (8U) -/*! Data_byte_6 - Received payload corresponding to the data byte 6 under Pretended Networking mode */ +/*! Data_byte_6 - Data Byte 6 */ #define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) #define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) #define CAN_WMB_D47_Data_byte_5_SHIFT (16U) -/*! Data_byte_5 - Received payload corresponding to the data byte 5 under Pretended Networking mode */ +/*! Data_byte_5 - Data Byte 5 */ #define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) #define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) #define CAN_WMB_D47_Data_byte_4_SHIFT (24U) -/*! Data_byte_4 - Received payload corresponding to the data byte 4 under Pretended Networking mode */ +/*! Data_byte_4 - Data Byte 4 */ #define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) /*! @} */ @@ -9941,7 +10185,7 @@ typedef struct { #define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) /*! @} */ -/*! @name EDCBT - Enhanced Data Phase CAN bit Timing */ +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ /*! @{ */ #define CAN_EDCBT_DTSEG1_MASK (0x1FU) @@ -9971,8 +10215,8 @@ typedef struct { #define CAN_ETDC_ETDCFAIL_MASK (0x8000U) #define CAN_ETDC_ETDCFAIL_SHIFT (15U) /*! ETDCFAIL - Transceiver Delay Compensation Fail - * 0b0..Measured loop delay is in range. - * 0b1..Measured loop delay is out of range. + * 0b0..In range + * 0b1..Out of range */ #define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) @@ -9984,21 +10228,21 @@ typedef struct { #define CAN_ETDC_TDMDIS_MASK (0x40000000U) #define CAN_ETDC_TDMDIS_SHIFT (30U) /*! TDMDIS - Transceiver Delay Measurement Disable - * 0b0..TDC measurement is enabled - * 0b1..TDC measurement is disabled + * 0b0..Enable + * 0b1..Disable */ #define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) #define CAN_ETDC_ETDCEN_MASK (0x80000000U) #define CAN_ETDC_ETDCEN_SHIFT (31U) /*! ETDCEN - Transceiver Delay Compensation Enable - * 0b0..TDC is disabled - * 0b1..TDC is enabled + * 0b0..Disable + * 0b1..Enable */ #define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) /*! @} */ -/*! @name FDCTRL - CAN FD Control Register */ +/*! @name FDCTRL - CAN FD Control */ /*! @{ */ #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) @@ -10014,39 +10258,39 @@ typedef struct { #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail - * 0b0..Measured loop delay is in range. - * 0b1..Measured loop delay is out of range. + * 0b0..In range + * 0b1..Out of range */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable - * 0b0..TDC is disabled - * 0b1..TDC is enabled + * 0b0..Disable + * 0b1..Enable */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 - * 0b00..Selects 8 bytes per message buffer. - * 0b01..Selects 16 bytes per message buffer. - * 0b10..Selects 32 bytes per message buffer. - * 0b11..Selects 64 bytes per message buffer. + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable - * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. - * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. + * 0b0..Disable + * 0b1..Enable */ #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) /*! @} */ -/*! @name FDCBT - CAN FD Bit Timing Register */ +/*! @name FDCBT - CAN FD Bit Timing */ /*! @{ */ #define CAN_FDCBT_FPSEG2_MASK (0x7U) @@ -10075,7 +10319,7 @@ typedef struct { #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) /*! @} */ -/*! @name FDCRC - CAN FD CRC Register */ +/*! @name FDCRC - CAN FD CRC */ /*! @{ */ #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) @@ -10085,21 +10329,21 @@ typedef struct { #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) -/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC */ +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /*! @} */ -/*! @name ERFCR - Enhanced Rx FIFO Control Register */ +/*! @name ERFCR - Enhanced RX FIFO Control */ /*! @{ */ #define CAN_ERFCR_ERFWM_MASK (0x1FU) #define CAN_ERFCR_ERFWM_SHIFT (0U) -/*! ERFWM - Enhanced Rx FIFO Watermark */ +/*! ERFWM - Enhanced RX FIFO Watermark */ #define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) #define CAN_ERFCR_NFE_MASK (0x3F00U) #define CAN_ERFCR_NFE_SHIFT (8U) -/*! NFE - Number of Enhanced Rx FIFO Filter Elements */ +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ #define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) #define CAN_ERFCR_NEXIF_MASK (0x7F0000U) @@ -10114,115 +10358,115 @@ typedef struct { #define CAN_ERFCR_ERFEN_MASK (0x80000000U) #define CAN_ERFCR_ERFEN_SHIFT (31U) -/*! ERFEN - Enhanced Rx FIFO enable - * 0b0..Enhanced Rx FIFO is disabled - * 0b1..Enhanced Rx FIFO is enabled +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) /*! @} */ -/*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */ +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ /*! @{ */ #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) #define CAN_ERFIER_ERFDAIE_SHIFT (28U) -/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable - * 0b0..Enhanced Rx FIFO Data Available interrupt is disabled - * 0b1..Enhanced Rx FIFO Data Available interrupt is enabled +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) #define CAN_ERFIER_ERFWMIIE_SHIFT (29U) -/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable - * 0b0..Enhanced Rx FIFO Watermark interrupt is disabled - * 0b1..Enhanced Rx FIFO Watermark interrupt is enabled +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) #define CAN_ERFIER_ERFOVFIE_SHIFT (30U) -/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable - * 0b0..Enhanced Rx FIFO Overflow is disabled - * 0b1..Enhanced Rx FIFO Overflow is enabled +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) #define CAN_ERFIER_ERFUFWIE_SHIFT (31U) -/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable - * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled - * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) /*! @} */ -/*! @name ERFSR - Enhanced Rx FIFO Status Register */ +/*! @name ERFSR - Enhanced RX FIFO Status */ /*! @{ */ #define CAN_ERFSR_ERFEL_MASK (0x3FU) #define CAN_ERFSR_ERFEL_SHIFT (0U) -/*! ERFEL - Enhanced Rx FIFO Elements */ +/*! ERFEL - Enhanced RX FIFO Elements */ #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) #define CAN_ERFSR_ERFF_MASK (0x10000U) #define CAN_ERFSR_ERFF_SHIFT (16U) -/*! ERFF - Enhanced Rx FIFO full - * 0b0..Enhanced Rx FIFO is not full - * 0b1..Enhanced Rx FIFO is full +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full */ #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) #define CAN_ERFSR_ERFE_MASK (0x20000U) #define CAN_ERFSR_ERFE_SHIFT (17U) -/*! ERFE - Enhanced Rx FIFO empty - * 0b0..Enhanced Rx FIFO is not empty - * 0b1..Enhanced Rx FIFO is empty +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty */ #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) #define CAN_ERFSR_ERFCLR_MASK (0x8000000U) #define CAN_ERFSR_ERFCLR_SHIFT (27U) -/*! ERFCLR - Enhanced Rx FIFO Clear +/*! ERFCLR - Enhanced RX FIFO Clear * 0b0..No effect - * 0b1..Clear Enhanced Rx FIFO content + * 0b1..Clear enhanced RX FIFO content */ #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) #define CAN_ERFSR_ERFDA_MASK (0x10000000U) #define CAN_ERFSR_ERFDA_SHIFT (28U) -/*! ERFDA - Enhanced Rx FIFO Data Available +/*! ERFDA - Enhanced RX FIFO Data Available Flag * 0b0..No such occurrence - * 0b1..There is at least one message stored in Enhanced Rx FIFO + * 0b1..At least one message stored in Enhanced RX FIFO */ #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) #define CAN_ERFSR_ERFWMI_SHIFT (29U) -/*! ERFWMI - Enhanced Rx FIFO Watermark Indication +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag * 0b0..No such occurrence - * 0b1..The number of messages in FIFO is greater than the watermark + * 0b1..Number of messages in FIFO is greater than the watermark */ #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) #define CAN_ERFSR_ERFOVF_MASK (0x40000000U) #define CAN_ERFSR_ERFOVF_SHIFT (30U) -/*! ERFOVF - Enhanced Rx FIFO Overflow +/*! ERFOVF - Enhanced RX FIFO Overflow Flag * 0b0..No such occurrence - * 0b1..Enhanced Rx FIFO overflow + * 0b1..Overflow */ #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) #define CAN_ERFSR_ERFUFW_MASK (0x80000000U) #define CAN_ERFSR_ERFUFW_SHIFT (31U) -/*! ERFUFW - Enhanced Rx FIFO Underflow +/*! ERFUFW - Enhanced RX FIFO Underflow Flag * 0b0..No such occurrence - * 0b1..Enhanced Rx FIFO underflow + * 0b1..Underflow */ #define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) /*! @} */ -/*! @name ERFFEL - Enhanced Rx FIFO Filter Element */ +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ /*! @{ */ #define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) @@ -10736,7 +10980,7 @@ typedef struct { uint8_t RESERVED_6[12]; __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ uint8_t RESERVED_7[28]; - __IO uint32_t BSR; /**< BootROM Status, offset: 0x100 */ + __IO uint32_t BSR; /**< BootROM Status Register, offset: 0x100 */ uint8_t RESERVED_8[8]; __IO uint32_t BLR; /**< BootROM Lock Register, offset: 0x10C */ __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ @@ -10779,6 +11023,7 @@ typedef struct { #define CMC_CKCTRL_CKMODE_SHIFT (0U) /*! CKMODE - Clocking Mode * 0b0000..No clock gating + * 0b0001..Core clock is gated * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. */ #define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) @@ -10799,6 +11044,7 @@ typedef struct { #define CMC_CKSTAT_CKMODE_SHIFT (0U) /*! CKMODE - Low Power Status * 0b0000..Core clock not gated + * 0b0001..Core clock was gated * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode * *.. */ @@ -11479,10 +11725,261 @@ typedef struct { /*! @name SRAMDIS - SRAM Disable */ /*! @{ */ -#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) -#define CMC_SRAMDIS_DIS_SHIFT (0U) -/*! DIS - SRAM Disable */ -#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) +#define CMC_SRAMDIS_DIS0_MASK (0x1U) +#define CMC_SRAMDIS_DIS0_SHIFT (0U) +/*! DIS0 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK) + +#define CMC_SRAMDIS_DIS1_MASK (0x2U) +#define CMC_SRAMDIS_DIS1_SHIFT (1U) +/*! DIS1 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK) + +#define CMC_SRAMDIS_DIS2_MASK (0x4U) +#define CMC_SRAMDIS_DIS2_SHIFT (2U) +/*! DIS2 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK) + +#define CMC_SRAMDIS_DIS3_MASK (0x8U) +#define CMC_SRAMDIS_DIS3_SHIFT (3U) +/*! DIS3 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK) + +#define CMC_SRAMDIS_DIS4_MASK (0x10U) +#define CMC_SRAMDIS_DIS4_SHIFT (4U) +/*! DIS4 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK) + +#define CMC_SRAMDIS_DIS5_MASK (0x20U) +#define CMC_SRAMDIS_DIS5_SHIFT (5U) +/*! DIS5 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK) + +#define CMC_SRAMDIS_DIS6_MASK (0x40U) +#define CMC_SRAMDIS_DIS6_SHIFT (6U) +/*! DIS6 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK) + +#define CMC_SRAMDIS_DIS7_MASK (0x80U) +#define CMC_SRAMDIS_DIS7_SHIFT (7U) +/*! DIS7 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK) + +#define CMC_SRAMDIS_DIS8_MASK (0x100U) +#define CMC_SRAMDIS_DIS8_SHIFT (8U) +/*! DIS8 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK) + +#define CMC_SRAMDIS_DIS9_MASK (0x200U) +#define CMC_SRAMDIS_DIS9_SHIFT (9U) +/*! DIS9 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK) + +#define CMC_SRAMDIS_DIS10_MASK (0x400U) +#define CMC_SRAMDIS_DIS10_SHIFT (10U) +/*! DIS10 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK) + +#define CMC_SRAMDIS_DIS11_MASK (0x800U) +#define CMC_SRAMDIS_DIS11_SHIFT (11U) +/*! DIS11 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK) + +#define CMC_SRAMDIS_DIS12_MASK (0x1000U) +#define CMC_SRAMDIS_DIS12_SHIFT (12U) +/*! DIS12 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK) + +#define CMC_SRAMDIS_DIS13_MASK (0x2000U) +#define CMC_SRAMDIS_DIS13_SHIFT (13U) +/*! DIS13 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK) + +#define CMC_SRAMDIS_DIS14_MASK (0x4000U) +#define CMC_SRAMDIS_DIS14_SHIFT (14U) +/*! DIS14 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK) + +#define CMC_SRAMDIS_DIS15_MASK (0x8000U) +#define CMC_SRAMDIS_DIS15_SHIFT (15U) +/*! DIS15 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK) + +#define CMC_SRAMDIS_DIS16_MASK (0x10000U) +#define CMC_SRAMDIS_DIS16_SHIFT (16U) +/*! DIS16 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK) + +#define CMC_SRAMDIS_DIS17_MASK (0x20000U) +#define CMC_SRAMDIS_DIS17_SHIFT (17U) +/*! DIS17 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK) + +#define CMC_SRAMDIS_DIS18_MASK (0x40000U) +#define CMC_SRAMDIS_DIS18_SHIFT (18U) +/*! DIS18 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK) + +#define CMC_SRAMDIS_DIS19_MASK (0x80000U) +#define CMC_SRAMDIS_DIS19_SHIFT (19U) +/*! DIS19 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK) + +#define CMC_SRAMDIS_DIS20_MASK (0x100000U) +#define CMC_SRAMDIS_DIS20_SHIFT (20U) +/*! DIS20 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK) + +#define CMC_SRAMDIS_DIS21_MASK (0x200000U) +#define CMC_SRAMDIS_DIS21_SHIFT (21U) +/*! DIS21 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK) + +#define CMC_SRAMDIS_DIS22_MASK (0x400000U) +#define CMC_SRAMDIS_DIS22_SHIFT (22U) +/*! DIS22 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK) + +#define CMC_SRAMDIS_DIS23_MASK (0x800000U) +#define CMC_SRAMDIS_DIS23_SHIFT (23U) +/*! DIS23 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK) + +#define CMC_SRAMDIS_DIS24_MASK (0x1000000U) +#define CMC_SRAMDIS_DIS24_SHIFT (24U) +/*! DIS24 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK) + +#define CMC_SRAMDIS_DIS25_MASK (0x2000000U) +#define CMC_SRAMDIS_DIS25_SHIFT (25U) +/*! DIS25 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK) + +#define CMC_SRAMDIS_DIS26_MASK (0x4000000U) +#define CMC_SRAMDIS_DIS26_SHIFT (26U) +/*! DIS26 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK) + +#define CMC_SRAMDIS_DIS27_MASK (0x8000000U) +#define CMC_SRAMDIS_DIS27_SHIFT (27U) +/*! DIS27 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK) + +#define CMC_SRAMDIS_DIS28_MASK (0x10000000U) +#define CMC_SRAMDIS_DIS28_SHIFT (28U) +/*! DIS28 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK) + +#define CMC_SRAMDIS_DIS29_MASK (0x20000000U) +#define CMC_SRAMDIS_DIS29_SHIFT (29U) +/*! DIS29 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK) + +#define CMC_SRAMDIS_DIS30_MASK (0x40000000U) +#define CMC_SRAMDIS_DIS30_SHIFT (30U) +/*! DIS30 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK) + +#define CMC_SRAMDIS_DIS31_MASK (0x80000000U) +#define CMC_SRAMDIS_DIS31_SHIFT (31U) +/*! DIS31 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK) /*! @} */ /* The count of CMC_SRAMDIS */ @@ -11491,10 +11988,261 @@ typedef struct { /*! @name SRAMRET - SRAM Retention */ /*! @{ */ -#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) -#define CMC_SRAMRET_RET_SHIFT (0U) -/*! RET - SRAM Retention */ -#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) +#define CMC_SRAMRET_RET0_MASK (0x1U) +#define CMC_SRAMRET_RET0_SHIFT (0U) +/*! RET0 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK) + +#define CMC_SRAMRET_RET1_MASK (0x2U) +#define CMC_SRAMRET_RET1_SHIFT (1U) +/*! RET1 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK) + +#define CMC_SRAMRET_RET2_MASK (0x4U) +#define CMC_SRAMRET_RET2_SHIFT (2U) +/*! RET2 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK) + +#define CMC_SRAMRET_RET3_MASK (0x8U) +#define CMC_SRAMRET_RET3_SHIFT (3U) +/*! RET3 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK) + +#define CMC_SRAMRET_RET4_MASK (0x10U) +#define CMC_SRAMRET_RET4_SHIFT (4U) +/*! RET4 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK) + +#define CMC_SRAMRET_RET5_MASK (0x20U) +#define CMC_SRAMRET_RET5_SHIFT (5U) +/*! RET5 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK) + +#define CMC_SRAMRET_RET6_MASK (0x40U) +#define CMC_SRAMRET_RET6_SHIFT (6U) +/*! RET6 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK) + +#define CMC_SRAMRET_RET7_MASK (0x80U) +#define CMC_SRAMRET_RET7_SHIFT (7U) +/*! RET7 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK) + +#define CMC_SRAMRET_RET8_MASK (0x100U) +#define CMC_SRAMRET_RET8_SHIFT (8U) +/*! RET8 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK) + +#define CMC_SRAMRET_RET9_MASK (0x200U) +#define CMC_SRAMRET_RET9_SHIFT (9U) +/*! RET9 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK) + +#define CMC_SRAMRET_RET10_MASK (0x400U) +#define CMC_SRAMRET_RET10_SHIFT (10U) +/*! RET10 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK) + +#define CMC_SRAMRET_RET11_MASK (0x800U) +#define CMC_SRAMRET_RET11_SHIFT (11U) +/*! RET11 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK) + +#define CMC_SRAMRET_RET12_MASK (0x1000U) +#define CMC_SRAMRET_RET12_SHIFT (12U) +/*! RET12 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK) + +#define CMC_SRAMRET_RET13_MASK (0x2000U) +#define CMC_SRAMRET_RET13_SHIFT (13U) +/*! RET13 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK) + +#define CMC_SRAMRET_RET14_MASK (0x4000U) +#define CMC_SRAMRET_RET14_SHIFT (14U) +/*! RET14 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK) + +#define CMC_SRAMRET_RET15_MASK (0x8000U) +#define CMC_SRAMRET_RET15_SHIFT (15U) +/*! RET15 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK) + +#define CMC_SRAMRET_RET16_MASK (0x10000U) +#define CMC_SRAMRET_RET16_SHIFT (16U) +/*! RET16 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK) + +#define CMC_SRAMRET_RET17_MASK (0x20000U) +#define CMC_SRAMRET_RET17_SHIFT (17U) +/*! RET17 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK) + +#define CMC_SRAMRET_RET18_MASK (0x40000U) +#define CMC_SRAMRET_RET18_SHIFT (18U) +/*! RET18 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK) + +#define CMC_SRAMRET_RET19_MASK (0x80000U) +#define CMC_SRAMRET_RET19_SHIFT (19U) +/*! RET19 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK) + +#define CMC_SRAMRET_RET20_MASK (0x100000U) +#define CMC_SRAMRET_RET20_SHIFT (20U) +/*! RET20 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK) + +#define CMC_SRAMRET_RET21_MASK (0x200000U) +#define CMC_SRAMRET_RET21_SHIFT (21U) +/*! RET21 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK) + +#define CMC_SRAMRET_RET22_MASK (0x400000U) +#define CMC_SRAMRET_RET22_SHIFT (22U) +/*! RET22 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK) + +#define CMC_SRAMRET_RET23_MASK (0x800000U) +#define CMC_SRAMRET_RET23_SHIFT (23U) +/*! RET23 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK) + +#define CMC_SRAMRET_RET24_MASK (0x1000000U) +#define CMC_SRAMRET_RET24_SHIFT (24U) +/*! RET24 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK) + +#define CMC_SRAMRET_RET25_MASK (0x2000000U) +#define CMC_SRAMRET_RET25_SHIFT (25U) +/*! RET25 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK) + +#define CMC_SRAMRET_RET26_MASK (0x4000000U) +#define CMC_SRAMRET_RET26_SHIFT (26U) +/*! RET26 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK) + +#define CMC_SRAMRET_RET27_MASK (0x8000000U) +#define CMC_SRAMRET_RET27_SHIFT (27U) +/*! RET27 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK) + +#define CMC_SRAMRET_RET28_MASK (0x10000000U) +#define CMC_SRAMRET_RET28_SHIFT (28U) +/*! RET28 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK) + +#define CMC_SRAMRET_RET29_MASK (0x20000000U) +#define CMC_SRAMRET_RET29_SHIFT (29U) +/*! RET29 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK) + +#define CMC_SRAMRET_RET30_MASK (0x40000000U) +#define CMC_SRAMRET_RET30_SHIFT (30U) +/*! RET30 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK) + +#define CMC_SRAMRET_RET31_MASK (0x80000000U) +#define CMC_SRAMRET_RET31_SHIFT (31U) +/*! RET31 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK) /*! @} */ /* The count of CMC_SRAMRET */ @@ -11518,17 +12266,9 @@ typedef struct { * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) */ #define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) - -#define CMC_FLASHCR_FLASHWAKE_MASK (0x4U) -#define CMC_FLASHCR_FLASHWAKE_SHIFT (2U) -/*! FLASHWAKE - Flash Wake - * 0b0..No effect - * 0b1..Flash memory is not disabled during flash memory accesses - */ -#define CMC_FLASHCR_FLASHWAKE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK) /*! @} */ -/*! @name BSR - BootROM Status */ +/*! @name BSR - BootROM Status Register */ /*! @{ */ #define CMC_BSR_STAT_MASK (0xFFFFFFFFU) @@ -11607,13 +12347,16 @@ typedef struct { /** Array initializer of CMC peripheral base pointers */ #define CMC_BASE_PTRS { CMC0 } #endif -/* Backward compatibility */ -#define CMC_SRIE_WDOG0_MASK CMC_SRIE_WWDT0_MASK -#define CMC_SRIE_WDOG1_MASK CMC_SRIE_WWDT1_MASK -#define CMC_SRIF_WDOG0_MASK CMC_SRIF_WWDT0_MASK -#define CMC_SRIF_WDOG1_MASK CMC_SRIF_WWDT1_MASK -#define CMC_SRS_WDOG0_MASK CMC_SRS_WWDT0_MASK -#define CMC_SRS_WDOG1_MASK CMC_SRS_WWDT1_MASK +/* Backward compatibility for CMC */ +#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) +#define CMC_SRAMDIS_DIS_SHIFT (0U) +/*! DIS - SRAM Disable */ +#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) + +#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) +#define CMC_SRAMRET_RET_SHIFT (0U) +/*! RET - SRAM Retention */ +#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) /*! @@ -11643,7 +12386,7 @@ typedef struct { __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ } ACCESS16BIT; - __IO uint32_t DATA; /**< CRC Data, offset: 0x0 */ + __IO uint32_t DATA; /**< Data, offset: 0x0 */ }; union { /* offset: 0x4 */ struct { /* offset: 0x4 */ @@ -11656,14 +12399,14 @@ typedef struct { __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ } GPOLY_ACCESS16BIT; - __IO uint32_t GPOLY; /**< CRC Polynomial, offset: 0x4 */ + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ }; union { /* offset: 0x8 */ struct { /* offset: 0x8 */ uint8_t RESERVED_0[3]; __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ } CTRL_ACCESS8BIT; - __IO uint32_t CTRL; /**< CRC Control, offset: 0x8 */ + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ }; } CRC_Type; @@ -11724,27 +12467,27 @@ typedef struct { #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) /*! @} */ -/*! @name DATA - CRC Data */ +/*! @name DATA - Data */ /*! @{ */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) -/*! LL - CRC Low Lower Byte */ +/*! LL - Lower Part of Low Byte */ #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) #define CRC_DATA_LU_MASK (0xFF00U) #define CRC_DATA_LU_SHIFT (8U) -/*! LU - CRC Low Upper Byte */ +/*! LU - Upper Part of Low Byte */ #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) #define CRC_DATA_HL_MASK (0xFF0000U) #define CRC_DATA_HL_SHIFT (16U) -/*! HL - CRC High Lower Byte */ +/*! HL - Lower Part of High Byte */ #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) -/*! HU - CRC High Upper Byte */ +/*! HU - Upper Part of High Byte */ #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) /*! @} */ @@ -11796,17 +12539,17 @@ typedef struct { #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) /*! @} */ -/*! @name GPOLY - CRC Polynomial */ +/*! @name GPOLY - Polynomial */ /*! @{ */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) -/*! LOW - Low Polynomial Half-Word */ +/*! LOW - Low Half-Word */ #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) -/*! HIGH - High Polynomial Half-Word */ +/*! HIGH - High Half-Word */ #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) /*! @} */ @@ -11816,8 +12559,8 @@ typedef struct { #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) /*! TCRC - TCRC - * 0b0..16-bit - * 0b1..32-bit + * 0b0..16 bits + * 0b1..32 bits */ #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) @@ -11832,8 +12575,8 @@ typedef struct { #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) /*! FXOR - Complement Read of CRC Data Register - * 0b0..No XOR on reading - * 0b1..Inverts or complements the read value of the CRC Data + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. */ #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) @@ -11841,31 +12584,31 @@ typedef struct { #define CRC_CTRLHU_TOTR_SHIFT (4U) /*! TOTR - Transpose Type for Read * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) -/*! TOT - Transpose Type for Writes +/*! TOT - Transpose Type for Write * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) /*! @} */ -/*! @name CTRL - CRC Control */ +/*! @name CTRL - Control */ /*! @{ */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) /*! TCRC - TCRC - * 0b0..16-bit - * 0b1..32-bit + * 0b0..16 bits + * 0b1..32 bits */ #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) @@ -11880,8 +12623,8 @@ typedef struct { #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) /*! FXOR - Complement Read of CRC Data Register - * 0b0..No XOR on reading - * 0b1..Inverts or complements the read value of the CRC Data + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. */ #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) @@ -11889,19 +12632,19 @@ typedef struct { #define CRC_CTRL_TOTR_SHIFT (28U) /*! TOTR - Transpose Type for Read * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) -/*! TOT - Transpose Type for Writes +/*! TOT - Transpose Type for Write * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) /*! @} */ @@ -15936,651 +16679,6 @@ typedef struct { */ /* end of group EMVSIM_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- ENC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer - * @{ - */ - -/** ENC - Register Layout Typedef */ -typedef struct { - __IO uint16_t CTRL; /**< Control, offset: 0x0 */ - __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ - __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ - __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ - __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ - __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ - __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ - __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ - __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ - __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ - __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ - __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ - __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ - __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ - __IO uint16_t TST; /**< Test, offset: 0x1C */ - __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ - __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ - __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ - __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ - __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ - __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ - __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ - __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ - __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ - __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ - __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ -} ENC_Type; - -/* ---------------------------------------------------------------------------- - -- ENC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Register_Masks ENC Register Masks - * @{ - */ - -/*! @name CTRL - Control */ -/*! @{ */ - -#define ENC_CTRL_CMPIE_MASK (0x1U) -#define ENC_CTRL_CMPIE_SHIFT (0U) -/*! CMPIE - Compare Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) - -#define ENC_CTRL_CMPIRQ_MASK (0x2U) -#define ENC_CTRL_CMPIRQ_SHIFT (1U) -/*! CMPIRQ - Compare Interrupt Request - * 0b0..No match has occurred - * 0b1..COMP match has occurred - */ -#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) - -#define ENC_CTRL_WDE_MASK (0x4U) -#define ENC_CTRL_WDE_SHIFT (2U) -/*! WDE - Watchdog Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) - -#define ENC_CTRL_DIE_MASK (0x8U) -#define ENC_CTRL_DIE_SHIFT (3U) -/*! DIE - Watchdog Timeout Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) - -#define ENC_CTRL_DIRQ_MASK (0x10U) -#define ENC_CTRL_DIRQ_SHIFT (4U) -/*! DIRQ - Watchdog Timeout Interrupt Request - * 0b0..Not occurred - * 0b1..Occurred - */ -#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) - -#define ENC_CTRL_XNE_MASK (0x20U) -#define ENC_CTRL_XNE_SHIFT (5U) -/*! XNE - Select Positive and Negative Edge of INDEX and PRESET Pulse - * 0b0..Use positive edge - * 0b1..Use negative edge - */ -#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) - -#define ENC_CTRL_XIP_MASK (0x40U) -#define ENC_CTRL_XIP_SHIFT (6U) -/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS - * 0b0..Does not initialize - * 0b1..Initializes - */ -#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) - -#define ENC_CTRL_XIE_MASK (0x80U) -#define ENC_CTRL_XIE_SHIFT (7U) -/*! XIE - INDEX Pulse Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) - -#define ENC_CTRL_XIRQ_MASK (0x100U) -#define ENC_CTRL_XIRQ_SHIFT (8U) -/*! XIRQ - INDEX Pulse Interrupt Request - * 0b0..Not occurred - * 0b1..Occurred - */ -#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) - -#define ENC_CTRL_PH1_MASK (0x200U) -#define ENC_CTRL_PH1_SHIFT (9U) -/*! PH1 - Enable Signal Phase Count Mode - * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. - * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. - * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; - * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. - */ -#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) - -#define ENC_CTRL_REV_MASK (0x400U) -#define ENC_CTRL_REV_SHIFT (10U) -/*! REV - Enable Reverse Direction Counting - * 0b0..Counts normally - * 0b1..Counts in the reverse direction - */ -#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) - -#define ENC_CTRL_SWIP_MASK (0x800U) -#define ENC_CTRL_SWIP_SHIFT (11U) -/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS - * 0b0..No action - * 0b1..Initialize position counter - */ -#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) - -#define ENC_CTRL_HNE_MASK (0x1000U) -#define ENC_CTRL_HNE_SHIFT (12U) -/*! HNE - Use Negative Edge of HOME Input - * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS - * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS - */ -#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) - -#define ENC_CTRL_HIP_MASK (0x2000U) -#define ENC_CTRL_HIP_SHIFT (13U) -/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS - * 0b0..No action - * 0b1..HOME signal initializes the position counter - */ -#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) - -#define ENC_CTRL_HIE_MASK (0x4000U) -#define ENC_CTRL_HIE_SHIFT (14U) -/*! HIE - HOME Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) - -#define ENC_CTRL_HIRQ_MASK (0x8000U) -#define ENC_CTRL_HIRQ_SHIFT (15U) -/*! HIRQ - HOME Signal Transition Interrupt Request - * 0b0..Not occurred - * 0b1..Occurred - */ -#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) -/*! @} */ - -/*! @name FILT - Input Filter */ -/*! @{ */ - -#define ENC_FILT_FILT_PER_MASK (0xFFU) -#define ENC_FILT_FILT_PER_SHIFT (0U) -/*! FILT_PER - Input Filter Sample Period */ -#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) - -#define ENC_FILT_FILT_CNT_MASK (0x700U) -#define ENC_FILT_FILT_CNT_SHIFT (8U) -/*! FILT_CNT - Input Filter Sample Count */ -#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) - -#define ENC_FILT_FILT_PRSC_MASK (0xE000U) -#define ENC_FILT_FILT_PRSC_SHIFT (13U) -/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ -#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK) -/*! @} */ - -/*! @name WTR - Watchdog Timeout */ -/*! @{ */ - -#define ENC_WTR_WDOG_MASK (0xFFFFU) -#define ENC_WTR_WDOG_SHIFT (0U) -/*! WDOG - WDOG */ -#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) -/*! @} */ - -/*! @name POSD - Position Difference Counter */ -/*! @{ */ - -#define ENC_POSD_POSD_MASK (0xFFFFU) -#define ENC_POSD_POSD_SHIFT (0U) -/*! POSD - POSD */ -#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) -/*! @} */ - -/*! @name POSDH - Position Difference Hold */ -/*! @{ */ - -#define ENC_POSDH_POSDH_MASK (0xFFFFU) -#define ENC_POSDH_POSDH_SHIFT (0U) -/*! POSDH - POSDH */ -#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) -/*! @} */ - -/*! @name REV - Revolution Counter */ -/*! @{ */ - -#define ENC_REV_REV_MASK (0xFFFFU) -#define ENC_REV_REV_SHIFT (0U) -/*! REV - REV */ -#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) -/*! @} */ - -/*! @name REVH - Revolution Hold */ -/*! @{ */ - -#define ENC_REVH_REVH_MASK (0xFFFFU) -#define ENC_REVH_REVH_SHIFT (0U) -/*! REVH - REVH */ -#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) -/*! @} */ - -/*! @name UPOS - Upper Position Counter */ -/*! @{ */ - -#define ENC_UPOS_POS_MASK (0xFFFFU) -#define ENC_UPOS_POS_SHIFT (0U) -/*! POS - POS */ -#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) -/*! @} */ - -/*! @name LPOS - Lower Position Counter */ -/*! @{ */ - -#define ENC_LPOS_POS_MASK (0xFFFFU) -#define ENC_LPOS_POS_SHIFT (0U) -/*! POS - POS */ -#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) -/*! @} */ - -/*! @name UPOSH - Upper Position Hold */ -/*! @{ */ - -#define ENC_UPOSH_POSH_MASK (0xFFFFU) -#define ENC_UPOSH_POSH_SHIFT (0U) -/*! POSH - POSH */ -#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) -/*! @} */ - -/*! @name LPOSH - Lower Position Hold */ -/*! @{ */ - -#define ENC_LPOSH_POSH_MASK (0xFFFFU) -#define ENC_LPOSH_POSH_SHIFT (0U) -/*! POSH - POSH */ -#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) -/*! @} */ - -/*! @name UINIT - Upper Initialization */ -/*! @{ */ - -#define ENC_UINIT_INIT_MASK (0xFFFFU) -#define ENC_UINIT_INIT_SHIFT (0U) -/*! INIT - INIT */ -#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) -/*! @} */ - -/*! @name LINIT - Lower Initialization */ -/*! @{ */ - -#define ENC_LINIT_INIT_MASK (0xFFFFU) -#define ENC_LINIT_INIT_SHIFT (0U) -/*! INIT - INIT */ -#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) -/*! @} */ - -/*! @name IMR - Input Monitor */ -/*! @{ */ - -#define ENC_IMR_HOME_MASK (0x1U) -#define ENC_IMR_HOME_SHIFT (0U) -/*! HOME - HOME */ -#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) - -#define ENC_IMR_INDEX_MASK (0x2U) -#define ENC_IMR_INDEX_SHIFT (1U) -/*! INDEX - INDEX */ -#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) - -#define ENC_IMR_PHB_MASK (0x4U) -#define ENC_IMR_PHB_SHIFT (2U) -/*! PHB - PHB */ -#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) - -#define ENC_IMR_PHA_MASK (0x8U) -#define ENC_IMR_PHA_SHIFT (3U) -/*! PHA - PHA */ -#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) - -#define ENC_IMR_FHOM_MASK (0x10U) -#define ENC_IMR_FHOM_SHIFT (4U) -/*! FHOM - FHOM */ -#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) - -#define ENC_IMR_FIND_MASK (0x20U) -#define ENC_IMR_FIND_SHIFT (5U) -/*! FIND - FIND */ -#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) - -#define ENC_IMR_FPHB_MASK (0x40U) -#define ENC_IMR_FPHB_SHIFT (6U) -/*! FPHB - FPHB */ -#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) - -#define ENC_IMR_FPHA_MASK (0x80U) -#define ENC_IMR_FPHA_SHIFT (7U) -/*! FPHA - FPHA */ -#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) -/*! @} */ - -/*! @name TST - Test */ -/*! @{ */ - -#define ENC_TST_TEST_COUNT_MASK (0xFFU) -#define ENC_TST_TEST_COUNT_SHIFT (0U) -/*! TEST_COUNT - TEST_COUNT */ -#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) - -#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) -#define ENC_TST_TEST_PERIOD_SHIFT (8U) -/*! TEST_PERIOD - TEST_PERIOD */ -#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) - -#define ENC_TST_QDN_MASK (0x2000U) -#define ENC_TST_QDN_SHIFT (13U) -/*! QDN - Quadrature Decoder Negative Signal - * 0b0..Positive quadrature decoder signal - * 0b1..Negative quadrature decoder signal - */ -#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) - -#define ENC_TST_TCE_MASK (0x4000U) -#define ENC_TST_TCE_SHIFT (14U) -/*! TCE - Test Counter Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) - -#define ENC_TST_TEN_MASK (0x8000U) -#define ENC_TST_TEN_SHIFT (15U) -/*! TEN - Test Mode Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) -/*! @} */ - -/*! @name CTRL2 - Control 2 */ -/*! @{ */ - -#define ENC_CTRL2_UPDHLD_MASK (0x1U) -#define ENC_CTRL2_UPDHLD_SHIFT (0U) -/*! UPDHLD - Update Hold Registers - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) - -#define ENC_CTRL2_UPDPOS_MASK (0x2U) -#define ENC_CTRL2_UPDPOS_SHIFT (1U) -/*! UPDPOS - Update Position Registers - * 0b0..No action - * 0b1..Clear - */ -#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) - -#define ENC_CTRL2_MOD_MASK (0x4U) -#define ENC_CTRL2_MOD_SHIFT (2U) -/*! MOD - Enable Modulo Counting - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) - -#define ENC_CTRL2_DIR_MASK (0x8U) -#define ENC_CTRL2_DIR_SHIFT (3U) -/*! DIR - Count Direction Flag - * 0b0..Down direction - * 0b1..Up direction - */ -#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) - -#define ENC_CTRL2_RUIE_MASK (0x10U) -#define ENC_CTRL2_RUIE_SHIFT (4U) -/*! RUIE - Roll-under Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) - -#define ENC_CTRL2_RUIRQ_MASK (0x20U) -#define ENC_CTRL2_RUIRQ_SHIFT (5U) -/*! RUIRQ - Roll-under Interrupt Request - * 0b0..No roll-under has occurred - * 0b1..Roll-under has occurred - */ -#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) - -#define ENC_CTRL2_ROIE_MASK (0x40U) -#define ENC_CTRL2_ROIE_SHIFT (6U) -/*! ROIE - Roll-over Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) - -#define ENC_CTRL2_ROIRQ_MASK (0x80U) -#define ENC_CTRL2_ROIRQ_SHIFT (7U) -/*! ROIRQ - Roll-over Interrupt Request - * 0b0..Did not occur - * 0b1..Occurred - */ -#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) - -#define ENC_CTRL2_REVMOD_MASK (0x100U) -#define ENC_CTRL2_REVMOD_SHIFT (8U) -/*! REVMOD - Revolution Counter Modulus Enable - * 0b0..Use INDEX pulse - * 0b1..Use modulus counting roll-over or roll-under - */ -#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) - -#define ENC_CTRL2_OUTCTL_MASK (0x200U) -#define ENC_CTRL2_OUTCTL_SHIFT (9U) -/*! OUTCTL - Output Control - * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) - * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read - */ -#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) - -#define ENC_CTRL2_SABIE_MASK (0x400U) -#define ENC_CTRL2_SABIE_SHIFT (10U) -/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) - -#define ENC_CTRL2_SABIRQ_MASK (0x800U) -#define ENC_CTRL2_SABIRQ_SHIFT (11U) -/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request - * 0b0..No simultaneous change has occurred - * 0b1..A simultaneous change has occurred - */ -#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) - -#define ENC_CTRL2_INITPOS_MASK (0x1000U) -#define ENC_CTRL2_INITPOS_SHIFT (12U) -/*! INITPOS - Initialize Position Registers - * 0b0..Don't initialize position counter - * 0b1..Initialize position counter - */ -#define ENC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_INITPOS_SHIFT)) & ENC_CTRL2_INITPOS_MASK) -/*! @} */ - -/*! @name UMOD - Upper Modulus */ -/*! @{ */ - -#define ENC_UMOD_MOD_MASK (0xFFFFU) -#define ENC_UMOD_MOD_SHIFT (0U) -/*! MOD - MOD */ -#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) -/*! @} */ - -/*! @name LMOD - Lower Modulus */ -/*! @{ */ - -#define ENC_LMOD_MOD_MASK (0xFFFFU) -#define ENC_LMOD_MOD_SHIFT (0U) -/*! MOD - MOD */ -#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) -/*! @} */ - -/*! @name UCOMP - Upper Position Compare */ -/*! @{ */ - -#define ENC_UCOMP_COMP_MASK (0xFFFFU) -#define ENC_UCOMP_COMP_SHIFT (0U) -/*! COMP - COMP */ -#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) -/*! @} */ - -/*! @name LCOMP - Lower Position Compare */ -/*! @{ */ - -#define ENC_LCOMP_COMP_MASK (0xFFFFU) -#define ENC_LCOMP_COMP_SHIFT (0U) -/*! COMP - COMP */ -#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) -/*! @} */ - -/*! @name LASTEDGE - Last Edge Time */ -/*! @{ */ - -#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) -#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U) -/*! LASTEDGE - Last Edge Time Counter */ -#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK) -/*! @} */ - -/*! @name LASTEDGEH - Last Edge Time Hold */ -/*! @{ */ - -#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) -#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U) -/*! LASTEDGEH - Last Edge Time Hold */ -#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK) -/*! @} */ - -/*! @name POSDPER - Position Difference Period Counter */ -/*! @{ */ - -#define ENC_POSDPER_POSDPER_MASK (0xFFFFU) -#define ENC_POSDPER_POSDPER_SHIFT (0U) -/*! POSDPER - Position difference period */ -#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK) -/*! @} */ - -/*! @name POSDPERBFR - Position Difference Period Buffer */ -/*! @{ */ - -#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) -#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U) -/*! POSDPERBFR - Position difference period buffer */ -#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK) -/*! @} */ - -/*! @name POSDPERH - Position Difference Period Hold */ -/*! @{ */ - -#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU) -#define ENC_POSDPERH_POSDPERH_SHIFT (0U) -/*! POSDPERH - Position difference period hold */ -#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK) -/*! @} */ - -/*! @name CTRL3 - Control 3 */ -/*! @{ */ - -#define ENC_CTRL3_PMEN_MASK (0x1U) -#define ENC_CTRL3_PMEN_SHIFT (0U) -/*! PMEN - Period Measurement Function Enable - * 0b0..Not used - * 0b1..Used - */ -#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK) - -#define ENC_CTRL3_PRSC_MASK (0xF0U) -#define ENC_CTRL3_PRSC_SHIFT (4U) -/*! PRSC - Prescaler */ -#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ENC_Register_Masks */ - - -/* ENC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral ENC0 base address */ - #define ENC0_BASE (0x500CF000u) - /** Peripheral ENC0 base address */ - #define ENC0_BASE_NS (0x400CF000u) - /** Peripheral ENC0 base pointer */ - #define ENC0 ((ENC_Type *)ENC0_BASE) - /** Peripheral ENC0 base pointer */ - #define ENC0_NS ((ENC_Type *)ENC0_BASE_NS) - /** Peripheral ENC1 base address */ - #define ENC1_BASE (0x500D1000u) - /** Peripheral ENC1 base address */ - #define ENC1_BASE_NS (0x400D1000u) - /** Peripheral ENC1 base pointer */ - #define ENC1 ((ENC_Type *)ENC1_BASE) - /** Peripheral ENC1 base pointer */ - #define ENC1_NS ((ENC_Type *)ENC1_BASE_NS) - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS { ENC0, ENC1 } - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS_NS { ENC0_BASE_NS, ENC1_BASE_NS } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS_NS { ENC0_NS, ENC1_NS } -#else - /** Peripheral ENC0 base address */ - #define ENC0_BASE (0x400CF000u) - /** Peripheral ENC0 base pointer */ - #define ENC0 ((ENC_Type *)ENC0_BASE) - /** Peripheral ENC1 base address */ - #define ENC1_BASE (0x400D1000u) - /** Peripheral ENC1 base pointer */ - #define ENC1 ((ENC_Type *)ENC1_BASE) - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS { ENC0, ENC1 } -#endif -/** Interrupt vectors for the ENC peripheral type */ -#define ENC_COMPARE_IRQS { ENC0_COMPARE_IRQn, ENC1_COMPARE_IRQn } -#define ENC_HOME_IRQS { ENC0_HOME_IRQn, ENC1_HOME_IRQn } -#define ENC_WDOG_IRQS { ENC0_WDG_SAB_IRQn, ENC1_WDG_SAB_IRQn } -#define ENC_INDEX_IRQS { ENC0_IDX_IRQn, ENC1_IDX_IRQn } - -/*! - * @} - */ /* end of group ENC_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -16703,7 +16801,7 @@ typedef struct { __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 1 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */ __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 1 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_CONTROL2; /**< Channeli Receive Control..DMA Channel 1 Receive Control, array offset: 0x1130, array step: 0x80 */ - __IO uint32_t DMA_CHX_INT_EN; /**< The Channeli Interrupt Enable register enables the interrupts reported by the Status register...Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ + __IO uint32_t DMA_CHX_INT_EN; /**< Channeli Interrupt Enable..Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 1 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 1 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ uint8_t RESERVED_3[4]; @@ -18732,8 +18830,8 @@ typedef struct { #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control - * 0b0..Timestamp Digital or Binary Rollover Control is disabled - * 0b1..Timestamp Digital or Binary Rollover Control is enabled + * 0b0..Timestamp Digital Rollover Control is disabled and Binary Rollover Control is enabled + * 0b1..Timestamp Digital Rollover Control is enabled and Binary Rollover Control is disabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) @@ -19920,7 +20018,7 @@ typedef struct { /* The count of ENET_DMA_CH_DMA_CHX_RX_CONTROL2 */ #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_COUNT (2U) -/*! @name DMA_CH_DMA_CHX_INT_EN - The Channeli Interrupt Enable register enables the interrupts reported by the Status register...Channel 1 Interrupt Enable */ +/*! @name DMA_CH_DMA_CHX_INT_EN - Channeli Interrupt Enable..Channel 1 Interrupt Enable */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) @@ -21677,66 +21775,66 @@ typedef struct { /** FLEXIO - Register Layout Typedef */ typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CTRL; /**< FLEXIO Control Register, offset: 0x8 */ - __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ - __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ - __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ - __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ - __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ uint8_t RESERVED_3[4]; - __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ uint8_t RESERVED_4[4]; - __IO uint32_t TRGSTAT; /**< Trigger Status Register, offset: 0x48 */ - __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable Register, offset: 0x4C */ - __IO uint32_t PINSTAT; /**< Pin Status Register, offset: 0x50 */ - __IO uint32_t PINIEN; /**< Pin Interrupt Enable Register, offset: 0x54 */ - __IO uint32_t PINREN; /**< Pin Rising Edge Enable Register, offset: 0x58 */ - __IO uint32_t PINFEN; /**< Pin Falling Edge Enable Register, offset: 0x5C */ - __IO uint32_t PINOUTD; /**< Pin Output Data Register, offset: 0x60 */ - __IO uint32_t PINOUTE; /**< Pin Output Enable Register, offset: 0x64 */ - __O uint32_t PINOUTDIS; /**< Pin Output Disable Register, offset: 0x68 */ - __O uint32_t PINOUTCLR; /**< Pin Output Clear Register, offset: 0x6C */ - __O uint32_t PINOUTSET; /**< Pin Output Set Register, offset: 0x70 */ - __O uint32_t PINOUTTOG; /**< Pin Output Toggle Register, offset: 0x74 */ + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ uint8_t RESERVED_5[8]; - __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_6[96]; - __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_7[224]; - __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_8[96]; - __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_9[96]; - __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_10[96]; - __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_11[96]; - __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_12[96]; - __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_13[96]; - __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ uint8_t RESERVED_14[352]; - __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ uint8_t RESERVED_15[96]; - __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Halfword Swapped Register, array offset: 0x700, array step: 0x4 */ + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ uint8_t RESERVED_16[96]; - __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ uint8_t RESERVED_17[96]; - __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */ + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_18[96]; - __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */ + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_19[96]; - __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer N Halfword Byte Swapped Register, array offset: 0x900, array step: 0x4 */ + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ } FLEXIO_Type; /* ---------------------------------------------------------------------------- @@ -21748,16 +21846,16 @@ typedef struct { * @{ */ -/*! @name VERID - Version ID Register */ +/*! @name VERID - Version ID */ /*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented. - * 0b0000000000000001..Supports state, logic, and parallel modes. - * 0b0000000000000010..Supports pin control registers. - * 0b0000000000000011..Supports state, logic, and parallel modes, plus pin control registers. + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) @@ -21772,7 +21870,7 @@ typedef struct { #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) /*! @} */ -/*! @name PARAM - Parameter Register */ +/*! @name PARAM - Parameter */ /*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) @@ -21796,51 +21894,51 @@ typedef struct { #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) /*! @} */ -/*! @name CTRL - FLEXIO Control Register */ +/*! @name CTRL - FLEXIO Control */ /*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FLEXIO Enable - * 0b0..FLEXIO module is disabled. - * 0b1..FLEXIO module is enabled. + * 0b0..Disable + * 0b1..Enable */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset - * 0b0..Software reset is disabled - * 0b1..Software reset is enabled. All FLEXIO registers except the Control Register are reset. + * 0b0..Disabled + * 0b1..Enabled */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access - * 0b0..Configures for normal register accesses to FLEXIO - * 0b1..Configures for fast register accesses to FLEXIO + * 0b0..Normal + * 0b1..Fast */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable - * 0b0..FLEXIO is disabled in Debug modes. - * 0b1..FLEXIO is enabled in Debug modes. + * 0b0..Disable + * 0b1..Enable */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable - * 0b0..FLEXIO enabled in Doze modes. - * 0b1..FLEXIO disabled in Doze modes. + * 0b0..Enable + * 0b1..Disable */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) /*! @} */ -/*! @name PIN - Pin State Register */ +/*! @name PIN - Pin State */ /*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) @@ -21849,30 +21947,45 @@ typedef struct { #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /*! @} */ -/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @name SHIFTSTAT - Shifter Status */ /*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) -/*! SSF - Shifter Status Flag */ +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ -/*! @name SHIFTERR - Shifter Error Register */ +/*! @name SHIFTERR - Shifter Error */ /*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) -/*! SEF - Shifter Error Flags */ +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ -/*! @name TIMSTAT - Timer Status Register */ +/*! @name TIMSTAT - Timer Status Flag */ /*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) -/*! TSF - Timer Status Flags */ +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ @@ -21894,7 +22007,7 @@ typedef struct { #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) /*! @} */ -/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @name TIMIEN - Timer Interrupt Enable */ /*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) @@ -21921,7 +22034,7 @@ typedef struct { #define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) /*! @} */ -/*! @name SHIFTSTATE - Shifter State Register */ +/*! @name SHIFTSTATE - Shifter State */ /*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) @@ -21930,16 +22043,21 @@ typedef struct { #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) /*! @} */ -/*! @name TRGSTAT - Trigger Status Register */ +/*! @name TRGSTAT - Trigger Status */ /*! @{ */ #define FLEXIO_TRGSTAT_ETSF_MASK (0xFFU) #define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) -/*! ETSF - External Trigger Status Flags */ +/*! ETSF - External Trigger Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) /*! @} */ -/*! @name TRIGIEN - External Trigger Interrupt Enable Register */ +/*! @name TRIGIEN - External Trigger Interrupt Enable */ /*! @{ */ #define FLEXIO_TRIGIEN_TRIE_MASK (0xFFU) @@ -21948,16 +22066,21 @@ typedef struct { #define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) /*! @} */ -/*! @name PINSTAT - Pin Status Register */ +/*! @name PINSTAT - Pin Status */ /*! @{ */ #define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) #define FLEXIO_PINSTAT_PSF_SHIFT (0U) -/*! PSF - Pin Status Flags */ +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + */ #define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) /*! @} */ -/*! @name PINIEN - Pin Interrupt Enable Register */ +/*! @name PINIEN - Pin Interrupt Enable */ /*! @{ */ #define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) @@ -21966,7 +22089,7 @@ typedef struct { #define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) /*! @} */ -/*! @name PINREN - Pin Rising Edge Enable Register */ +/*! @name PINREN - Pin Rising Edge Enable */ /*! @{ */ #define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) @@ -21975,7 +22098,7 @@ typedef struct { #define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) /*! @} */ -/*! @name PINFEN - Pin Falling Edge Enable Register */ +/*! @name PINFEN - Pin Falling Edge Enable */ /*! @{ */ #define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) @@ -21984,7 +22107,7 @@ typedef struct { #define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) /*! @} */ -/*! @name PINOUTD - Pin Output Data Register */ +/*! @name PINOUTD - Pin Output Data */ /*! @{ */ #define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) @@ -21993,7 +22116,7 @@ typedef struct { #define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) /*! @} */ -/*! @name PINOUTE - Pin Output Enable Register */ +/*! @name PINOUTE - Pin Output Enable */ /*! @{ */ #define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) @@ -22002,7 +22125,7 @@ typedef struct { #define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) /*! @} */ -/*! @name PINOUTDIS - Pin Output Disable Register */ +/*! @name PINOUTDIS - Pin Output Disable */ /*! @{ */ #define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) @@ -22011,7 +22134,7 @@ typedef struct { #define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) /*! @} */ -/*! @name PINOUTCLR - Pin Output Clear Register */ +/*! @name PINOUTCLR - Pin Output Clear */ /*! @{ */ #define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) @@ -22020,7 +22143,7 @@ typedef struct { #define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) /*! @} */ -/*! @name PINOUTSET - Pin Output Set Register */ +/*! @name PINOUTSET - Pin Output Set */ /*! @{ */ #define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) @@ -22029,7 +22152,7 @@ typedef struct { #define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) /*! @} */ -/*! @name PINOUTTOG - Pin Output Toggle Register */ +/*! @name PINOUTTOG - Pin Output Toggle */ /*! @{ */ #define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) @@ -22038,28 +22161,28 @@ typedef struct { #define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) /*! @} */ -/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @name SHIFTCTL - Shifter Control */ /*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode - * 0b000..Disabled. - * 0b001..Receive mode. Captures the current shifter content into the SHIFTBUF on expiration of the timer. - * 0b010..Transmit mode. Load SHIFTBUF contents into the shifter on expiration of the timer. - * 0b011..Reserved. - * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the timer. - * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. - * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. - * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic lookup table. + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low + * 0b0..Active high + * 0b1..Active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) @@ -22081,8 +22204,8 @@ typedef struct { #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity - * 0b0..Shift on posedge of shift clock - * 0b1..Shift on negedge of shift clock + * 0b0..Positive edge + * 0b1..Negative edge */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) @@ -22095,31 +22218,33 @@ typedef struct { /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (8U) -/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @name SHIFTCFG - Shifter Configuration */ /*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) -/*! SSTART - Shifter Start Bit - * 0b00..Start bit disabled for transmitter/receiver/match store. Transmitter loads data on enable. - * 0b01..Start bit disabled for transmitter/receiver/match store. Transmitter loads data on first shift. - * 0b10..Transmitter outputs start bit value 0 before loading data on first shift. If start bit is not 0, receiver/match store sets error flag. - * 0b11..Transmitter outputs start bit value 1 before loading data on first shift. If start bit is not 1, receiver/match store sets error flag. +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) -/*! SSTOP - Shifter Stop bit - * 0b00..Stop bit disabled for transmitter/receiver/match store - * 0b01..Stop bit disabled for transmitter/receiver/match store. When timer is in stop condition, receiver/match - * store stores receive data on the configured shift edge. - * 0b10..Transmitter outputs stop bit value 0 on store. If stop bit is not 0, receiver/match store sets error - * flag. When timer is in stop condition, receiver/match stores also store receive data on the configured shift - * edge. - * 0b11..Transmitter outputs stop bit value 1 on store. If stop bit is not 1, receiver/match store sets error - * flag. When timer is in stop condition, receiver/match store also stores receive data on the configured shift - * edge. +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) @@ -22127,23 +22252,23 @@ typedef struct { #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source * 0b0..Pin - * 0b1..Shifter N+1 Output + * 0b1..Shifter n+1 output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) #define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) /*! LATST - Late Store - * 0b0..Shift register stores the pre-shift register state. - * 0b1..Shift register stores the post-shift register state. + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state */ #define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) #define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) #define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) /*! SSIZE - Shifter Size - * 0b0..Shift register is 32-bit. - * 0b1..Shift register is 24-bit. + * 0b0..32-bit + * 0b1..24-bit */ #define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) @@ -22156,7 +22281,7 @@ typedef struct { /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (8U) -/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @name SHIFTBUF - Shifter Buffer */ /*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) @@ -22168,7 +22293,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (8U) -/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) @@ -22180,7 +22305,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (8U) -/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) @@ -22192,7 +22317,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (8U) -/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) @@ -22204,44 +22329,44 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (8U) -/*! @name TIMCTL - Timer Control N Register */ +/*! @name TIMCTL - Timer Control */ /*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode - * 0b000..Timer disabled. - * 0b001..Dual 8-bit counters baud mode. - * 0b010..Dual 8-bit counters PWM high mode. - * 0b011..Single 16-bit counter mode. - * 0b100..Single 16-bit counter disable mode. - * 0b101..Dual 8-bit counters word mode. - * 0b110..Dual 8-bit counters PWM low mode. - * 0b111..Single 16-bit input capture mode. + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) #define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) /*! ONETIM - Timer One Time Operation - * 0b0..The timer enable event is generated as normal. - * 0b1..The timer enable event is blocked unless timer status flag is clear. + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear */ #define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) #define FLEXIO_TIMCTL_PININS_MASK (0x40U) #define FLEXIO_TIMCTL_PININS_SHIFT (6U) /*! PININS - Timer Pin Input Select - * 0b0..Timer pin input and output are selected by PINSEL. - * 0b1..Timer pin input is selected by PINSEL+1. Timer pin output remains selected by PINSEL. + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL */ #define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low + * 0b0..Active high + * 0b1..Active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) @@ -22263,16 +22388,16 @@ typedef struct { #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source - * 0b0..External trigger selected - * 0b1..Internal trigger selected + * 0b0..External + * 0b1..Internal */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity - * 0b0..Trigger active high - * 0b1..Trigger active low + * 0b0..Active high + * 0b1..Active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) @@ -22285,24 +22410,24 @@ typedef struct { /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (8U) -/*! @name TIMCFG - Timer Configuration N Register */ +/*! @name TIMCFG - Timer Configuration */ /*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) -/*! TSTART - Timer Start Bit - * 0b0..Start bit disabled - * 0b1..Start bit enabled +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) -/*! TSTOP - Timer Stop Bit - * 0b00..Stop bit disabled - * 0b01..Stop bit is enabled on timer compare - * 0b10..Stop bit is enabled on timer disable - * 0b11..Stop bit is enabled on timer compare and timer disable +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) @@ -22310,13 +22435,13 @@ typedef struct { #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable * 0b000..Timer always enabled - * 0b001..Timer enabled on Timer N-1 enable - * 0b010..Timer enabled on Trigger high - * 0b011..Timer enabled on Trigger high and Pin high - * 0b100..Timer enabled on Pin rising edge - * 0b101..Timer enabled on Pin rising edge and Trigger high - * 0b110..Timer enabled on Trigger rising edge - * 0b111..Timer enabled on Trigger rising or falling edge + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) @@ -22324,9 +22449,9 @@ typedef struct { #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable * 0b000..Timer never disabled - * 0b001..Timer disabled on Timer N-1 disable - * 0b010..Timer disabled on timer compare (upper 8-bits match and decrement) - * 0b011..Timer disabled on timer compare (upper 8-bits match and decrement) and trigger low + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low * 0b100..Timer disabled on pin rising or falling edge * 0b101..Timer disabled on pin rising or falling edge provided trigger is high * 0b110..Timer disabled on trigger falling edge @@ -22337,7 +22462,7 @@ typedef struct { #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset - * 0b000..Timer never reset + * 0b000..Never reset timer * 0b001..Timer reset on timer output high. * 0b010..Timer reset on timer pin equal to timer output * 0b011..Timer reset on timer trigger equal to timer output @@ -22351,24 +22476,24 @@ typedef struct { #define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement - * 0b000..Decrement counter on FLEXIO clock. Shift clock equals timer output. - * 0b001..Decrement counter on trigger input (both edges). Shift clock equals timer output. - * 0b010..Decrement counter on pin input (both edges). Shift clock equals pin input. - * 0b011..Decrement counter on trigger input (both edges). Shift clock equals trigger input. - * 0b100..Decrement counter on FLEXIO clock divided by 16. Shift clock equals timer output. - * 0b101..Decrement counter on FLEXIO clock divided by 256. Shift clock equals timer output. - * 0b110..Decrement counter on pin input (rising edge). Shift clock equals pin input. - * 0b111..Decrement counter on trigger input (rising edge). Shift clock equals trigger input. + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output - * 0b00..Timer output is logic one when enabled and is not affected by timer reset - * 0b01..Timer output is logic zero when enabled and is not affected by timer reset - * 0b10..Timer output is logic one when enabled and on timer reset - * 0b11..Timer output is logic zero when enabled and on timer reset + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) /*! @} */ @@ -22376,7 +22501,7 @@ typedef struct { /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (8U) -/*! @name TIMCMP - Timer Compare N Register */ +/*! @name TIMCMP - Timer Compare */ /*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) @@ -22388,7 +22513,7 @@ typedef struct { /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (8U) -/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) @@ -22400,7 +22525,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (8U) -/*! @name SHIFTBUFHWS - Shifter Buffer N Halfword Swapped Register */ +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) @@ -22412,7 +22537,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (8U) -/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) @@ -22424,7 +22549,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (8U) -/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */ +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) @@ -22436,7 +22561,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFOES */ #define FLEXIO_SHIFTBUFOES_COUNT (8U) -/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */ +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) @@ -22448,7 +22573,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFEOS */ #define FLEXIO_SHIFTBUFEOS_COUNT (8U) -/*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */ +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) @@ -22805,8 +22930,11 @@ typedef struct { #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK (0x800000U) #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT (23U) /*! RX_CLK_SRC_DIFF - Sample Clock Source Different - * 0b0..Use MCR0[RXCLKSRC] for Port A and Port B. - * 0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. + * 0b0..Use MCR0[RXCLKSRC] for Port A and Port B. MCR2[RXCLKSRC_B] is ignored and MCR0[RXCLKSRC] selects the + * Sample Clock source for Flash Reading of both ports A and B. + * 0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. MCR0[RXCLKSRC] selects the Sample Clock + * source for Flash Reading of port A (A_SCLK) and MCR2[RXCLKSRC_B] selects the Sample Clock source for Flash + * Reading of port B (B_SCLK). */ #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT)) & FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK) @@ -22902,6 +23030,11 @@ typedef struct { * 0b11..256 bytes */ #define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) + +#define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xE0000000U) +#define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (29U) +/*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */ +#define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ @@ -23555,7 +23688,7 @@ typedef struct { #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) -/*! SLVDLYTARGET - Target Delay Line For Target */ +/*! SLVDLYTARGET - Target Delay Line */ #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) @@ -23570,6 +23703,11 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Target Clock Delay Line Override Value */ #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) + +#define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) +#define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) +/*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */ +#define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ /* The count of FLEXSPI_DLLCR */ @@ -24652,14 +24790,32 @@ typedef struct { #endif /** Interrupt vectors for the FLEXSPI peripheral type */ #define FLEXSPI_IRQS { FLEXSPI0_IRQn } -#if (__ARM_FEATURE_CMSE & 0x2) -/** FlexSPI0 AMBA address */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA address */ +/** FlexSPI0 AMBA end address */ +#define FlexSPI0_AMBA_END (0x1FFFFFFFu) +/** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE_NS (0x08000000U) +/** FlexSPI0 AMBA end address */ +#define FlexSPI0_AMBA_END_NS (0x0FFFFFFFU) +/* FlexSPI0 alias1 base address. */ +#define FlexSPI0_ALIAS1_BASE (0x80000000U) +/* FlexSPI0 alias1 base NS address. */ +#define FlexSPI0_ALIAS1_BASE_NS (0x90000000U) +/* FlexSPI0 alias2 base address. */ +#define FlexSPI0_ALIAS2_BASE (0xA0000000U) +/* FlexSPI0 alias2 base NS address. */ +#define FlexSPI0_ALIAS2_BASE_NS (0xB0000000U) #else -/** FlexSPI0 AMBA address */ +/** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE (0x08000000U) +/** FlexSPI0 AMBA end address */ +#define FlexSPI0_AMBA_END (0x0FFFFFFFU) +/* FlexSPI0 alias1 base address. */ +#define FlexSPI0_ALIAS1_BASE (0x80000000U) +/* FlexSPI0 alias2 base address. */ +#define FlexSPI0_ALIAS2_BASE (0xA0000000U) #endif @@ -27886,9 +28042,9 @@ typedef struct { /* FMUTEST - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FMU0TEST base address */ - #define FMU0TEST_BASE (0x5004E000u) + #define FMU0TEST_BASE (0x50043000u) /** Peripheral FMU0TEST base address */ - #define FMU0TEST_BASE_NS (0x4004E000u) + #define FMU0TEST_BASE_NS (0x40043000u) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) /** Peripheral FMU0TEST base pointer */ @@ -27903,7 +28059,7 @@ typedef struct { #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } #else /** Peripheral FMU0TEST base address */ - #define FMU0TEST_BASE (0x4004E000u) + #define FMU0TEST_BASE (0x40043000u) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) /** Array initializer of FMUTEST peripheral base addresses */ @@ -28218,15 +28374,30 @@ typedef struct { /*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */ #define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) +#define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) +#define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) +/*! field_3_0 - GDET configuration 0 Field 3_0 */ +#define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) + #define GDET_GDET_CONF_0_SBZ_MASK (0x10U) #define GDET_GDET_CONF_0_SBZ_SHIFT (4U) /*! SBZ - Should Be Left to Zero */ #define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) +#define GDET_GDET_CONF_0_SBZ_MASK (0x10U) +#define GDET_GDET_CONF_0_SBZ_SHIFT (4U) +/*! sbz - Should be left to zero */ +#define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) + #define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) #define GDET_GDET_CONF_0_RFU_SHIFT (5U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) + +#define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) +#define GDET_GDET_CONF_0_RFU_SHIFT (5U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) /*! @} */ /*! @name GDET_CONF_1 - GDET Configuration 1 Register */ @@ -28237,50 +28408,100 @@ typedef struct { /*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */ #define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) +#define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) +#define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) +/*! field_1_0 - GDET configuration 1 Field 1_0 */ +#define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) + #define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) #define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) /*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */ #define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) +#define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) +#define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) +/*! field_3_2 - GDET configuration 1 Field 3_2 */ +#define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) + #define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) #define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) /*! SBZ1 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) +#define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) +#define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) +/*! sbz1 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) + #define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) #define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) /*! SBZ2 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) +#define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) +#define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) +/*! sbz2 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) + #define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) #define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) /*! SBZ3 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) +#define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) +#define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) +/*! sbz3 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) + #define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) #define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) /*! FIELD_7 - GDET Configuration 1 Field 7 */ #define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) +#define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) +#define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) +/*! field_7 - GDET configuration 1 Field 7 */ +#define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) + #define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) #define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) /*! FIELD_8 - GDET Configuration 1 Field 8 */ #define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) +#define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) +#define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) +/*! field_8 - GDET configuration 1 Field 8 */ +#define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) + #define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) #define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) /*! SBZ4 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) +#define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) +#define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) +/*! sbz4 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) + #define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) #define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) /*! SBZ5 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) +#define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) +#define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) +/*! sbz5 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) + #define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) #define GDET_GDET_CONF_1_RFU_SHIFT (11U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) + +#define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) +#define GDET_GDET_CONF_1_RFU_SHIFT (11U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) /*! @} */ /*! @name GDET_ENABLE1 - GDET Enable Register */ @@ -28291,10 +28512,20 @@ typedef struct { /*! EN1 - If set, the detector will be clock gated */ #define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) +#define GDET_GDET_ENABLE1_EN1_MASK (0x1U) +#define GDET_GDET_ENABLE1_EN1_SHIFT (0U) +/*! en1 - If set, the detector will be clock gated */ +#define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) + #define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_ENABLE1_RFU_SHIFT (1U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) + +#define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_ENABLE1_RFU_SHIFT (1U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) /*! @} */ /*! @name GDET_CONF_2 - GDET Configuration 2 Register */ @@ -28305,30 +28536,60 @@ typedef struct { /*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */ #define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) +#define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) +/*! field_6_0 - GDET configuration 2 Field 6_0 */ +#define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) + #define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) #define GDET_GDET_CONF_2_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) +#define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) +#define GDET_GDET_CONF_2_RFU1_SHIFT (7U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) + #define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) #define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) /*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */ #define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) +#define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) +#define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) +/*! field_21_16 - GDET configuration 2 Field 21_16 */ +#define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) + #define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) #define GDET_GDET_CONF_2_RFU2_SHIFT (22U) /*! RFU2 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) +#define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) +#define GDET_GDET_CONF_2_RFU2_SHIFT (22U) +/*! rfu2 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) + #define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) #define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) /*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */ #define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) +#define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) +#define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) +/*! field_29_24 - GDET configuration 2 Field 29_24 */ +#define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) + #define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) #define GDET_GDET_CONF_2_RFU3_SHIFT (30U) /*! RFU3 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) + +#define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) +#define GDET_GDET_CONF_2_RFU3_SHIFT (30U) +/*! rfu3 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) /*! @} */ /*! @name GDET_CONF_3 - GDET Configuration 3 Register */ @@ -28339,10 +28600,20 @@ typedef struct { /*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */ #define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) +#define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) +/*! field_6_0 - GDET configuration 3 Field 6_0 */ +#define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) + #define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_3_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) + +#define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_3_RFU1_SHIFT (7U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) /*! @} */ /*! @name GDET_CONF_4 - GDET Configuration 4 Register */ @@ -28353,10 +28624,20 @@ typedef struct { /*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */ #define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) +#define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) +/*! field_6_0 - GDET configuration 4 Field 6_0 */ +#define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) + #define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_4_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) + +#define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_4_RFU1_SHIFT (7U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) /*! @} */ /*! @name GDET_CONF_5 - GDET Configuration 5 Register */ @@ -28367,15 +28648,30 @@ typedef struct { /*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */ #define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) +#define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) +#define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) +/*! field_5_0 - GDET configuration 5 Field 5_0 */ +#define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) + #define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) #define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) /*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */ #define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) +#define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) +#define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) +/*! field_11_6 - GDET configuration 5 Field 11_6 */ +#define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) + #define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) #define GDET_GDET_CONF_5_RFU1_SHIFT (12U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) + +#define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) +#define GDET_GDET_CONF_5_RFU1_SHIFT (12U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) /*! @} */ /*! @name GDET_RESET - GDET Reset Register */ @@ -28386,15 +28682,30 @@ typedef struct { /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) +#define GDET_GDET_RESET_RFU1_MASK (0x7U) +#define GDET_GDET_RESET_RFU1_SHIFT (0U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) + #define GDET_GDET_RESET_SFT_RST_MASK (0x8U) #define GDET_GDET_RESET_SFT_RST_SHIFT (3U) /*! SFT_RST - Soft Reset for the Core Reset */ #define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) +#define GDET_GDET_RESET_SFT_RST_MASK (0x8U) +#define GDET_GDET_RESET_SFT_RST_SHIFT (3U) +/*! sft_rst - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 */ +#define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) + #define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) #define GDET_GDET_RESET_RFU2_SHIFT (4U) /*! RFU2 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) + +#define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) +#define GDET_GDET_RESET_RFU2_SHIFT (4U) +/*! rfu2 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) /*! @} */ /*! @name GDET_TEST - GDET Test Register */ @@ -28405,10 +28716,20 @@ typedef struct { /*! SBZ - Should Be Left to Zero */ #define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) +#define GDET_GDET_TEST_SBZ_MASK (0x1U) +#define GDET_GDET_TEST_SBZ_SHIFT (0U) +/*! sbz - Should be left to zero */ +#define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) + #define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_TEST_RFU_SHIFT (1U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) + +#define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_TEST_RFU_SHIFT (1U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) /*! @} */ /*! @name GDET_DLY_CTRL - GDET Delay Control Register */ @@ -28419,15 +28740,30 @@ typedef struct { /*! VOL_SEL - GDET Delay Control of the Voltage Mode */ #define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) +#define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) +#define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) +/*! vol_sel - GDET delay control of the voltage mode. Used to select the trim code appropiate to the voltage mode. */ +#define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) + #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) /*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */ #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) +/*! sw_vol_ctrl - Select the control of the trim code to the delay line via HW port (0) or SW SFR (1) */ +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) + #define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) #define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) + +#define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) +#define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) /*! @} */ @@ -28497,25 +28833,25 @@ typedef struct { __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t LOCK; /**< Lock, offset: 0xC */ - __IO uint32_t PCNS; /**< Pin Control Non-Secure, offset: 0x10 */ - __IO uint32_t ICNS; /**< Interrupt Control Non-Secure, offset: 0x14 */ - __IO uint32_t PCNP; /**< Pin Control Non-Privilege, offset: 0x18 */ - __IO uint32_t ICNP; /**< Interrupt Control Non-Privilege, offset: 0x1C */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ uint8_t RESERVED_1[32]; - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x40 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x44 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x48 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0x4C */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x50 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x54 */ - __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x58 */ + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ uint8_t RESERVED_2[4]; - __IO uint8_t PDR[32]; /**< Pin Data Register a, array offset: 0x60, array step: 0x1 */ - __IO uint32_t ICR[32]; /**< Interrupt Control Register 0..Interrupt Control Register 31, array offset: 0x80, array step: 0x4 */ - __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x100 */ - __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x104 */ + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ uint8_t RESERVED_3[24]; - __IO uint32_t ISFR[2]; /**< Interrupt Status Flag Register, array offset: 0x120, array step: 0x4 */ + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -28533,8 +28869,8 @@ typedef struct { #define GPIO_VERID_FEATURE_MASK (0xFFFFU) #define GPIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number - * 0b0000000000000000..Basic implementation. - * 0b0000000000000001..Protection registers implemented. + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented */ #define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) @@ -28564,2760 +28900,2424 @@ typedef struct { #define GPIO_LOCK_PCNS_MASK (0x1U) #define GPIO_LOCK_PCNS_SHIFT (0U) /*! PCNS - Lock PCNS - * 0b0..PCNS register is writable by software in Secure-Privilege state. - * 0b1..PCNS register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK) #define GPIO_LOCK_ICNS_MASK (0x2U) #define GPIO_LOCK_ICNS_SHIFT (1U) /*! ICNS - Lock ICNS - * 0b0..ICNS register is writable by software in Secure-Privilege state. - * 0b1..ICNS register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK) #define GPIO_LOCK_PCNP_MASK (0x4U) #define GPIO_LOCK_PCNP_SHIFT (2U) /*! PCNP - Lock PCNP - * 0b0..PCNP register is writable by software in Secure-Privilege state. - * 0b1..PCNP register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK) #define GPIO_LOCK_ICNP_MASK (0x8U) #define GPIO_LOCK_ICNP_SHIFT (3U) /*! ICNP - Lock ICNP - * 0b0..ICNP register is writable by software in Secure-Privilege state. - * 0b1..ICNP register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK) /*! @} */ -/*! @name PCNS - Pin Control Non-Secure */ +/*! @name PCNS - Pin Control Nonsecure */ /*! @{ */ #define GPIO_PCNS_NSE0_MASK (0x1U) #define GPIO_PCNS_NSE0_SHIFT (0U) -/*! NSE0 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK) #define GPIO_PCNS_NSE1_MASK (0x2U) #define GPIO_PCNS_NSE1_SHIFT (1U) -/*! NSE1 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK) #define GPIO_PCNS_NSE2_MASK (0x4U) #define GPIO_PCNS_NSE2_SHIFT (2U) -/*! NSE2 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK) #define GPIO_PCNS_NSE3_MASK (0x8U) #define GPIO_PCNS_NSE3_SHIFT (3U) -/*! NSE3 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK) #define GPIO_PCNS_NSE4_MASK (0x10U) #define GPIO_PCNS_NSE4_SHIFT (4U) -/*! NSE4 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK) #define GPIO_PCNS_NSE5_MASK (0x20U) #define GPIO_PCNS_NSE5_SHIFT (5U) -/*! NSE5 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK) #define GPIO_PCNS_NSE6_MASK (0x40U) #define GPIO_PCNS_NSE6_SHIFT (6U) -/*! NSE6 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK) #define GPIO_PCNS_NSE7_MASK (0x80U) #define GPIO_PCNS_NSE7_SHIFT (7U) -/*! NSE7 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK) #define GPIO_PCNS_NSE8_MASK (0x100U) #define GPIO_PCNS_NSE8_SHIFT (8U) -/*! NSE8 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK) #define GPIO_PCNS_NSE9_MASK (0x200U) #define GPIO_PCNS_NSE9_SHIFT (9U) -/*! NSE9 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK) #define GPIO_PCNS_NSE10_MASK (0x400U) #define GPIO_PCNS_NSE10_SHIFT (10U) -/*! NSE10 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK) #define GPIO_PCNS_NSE11_MASK (0x800U) #define GPIO_PCNS_NSE11_SHIFT (11U) -/*! NSE11 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK) #define GPIO_PCNS_NSE12_MASK (0x1000U) #define GPIO_PCNS_NSE12_SHIFT (12U) -/*! NSE12 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK) #define GPIO_PCNS_NSE13_MASK (0x2000U) #define GPIO_PCNS_NSE13_SHIFT (13U) -/*! NSE13 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK) #define GPIO_PCNS_NSE14_MASK (0x4000U) #define GPIO_PCNS_NSE14_SHIFT (14U) -/*! NSE14 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK) #define GPIO_PCNS_NSE15_MASK (0x8000U) #define GPIO_PCNS_NSE15_SHIFT (15U) -/*! NSE15 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK) #define GPIO_PCNS_NSE16_MASK (0x10000U) #define GPIO_PCNS_NSE16_SHIFT (16U) -/*! NSE16 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK) #define GPIO_PCNS_NSE17_MASK (0x20000U) #define GPIO_PCNS_NSE17_SHIFT (17U) -/*! NSE17 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK) #define GPIO_PCNS_NSE18_MASK (0x40000U) #define GPIO_PCNS_NSE18_SHIFT (18U) -/*! NSE18 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK) #define GPIO_PCNS_NSE19_MASK (0x80000U) #define GPIO_PCNS_NSE19_SHIFT (19U) -/*! NSE19 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK) #define GPIO_PCNS_NSE20_MASK (0x100000U) #define GPIO_PCNS_NSE20_SHIFT (20U) -/*! NSE20 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK) #define GPIO_PCNS_NSE21_MASK (0x200000U) #define GPIO_PCNS_NSE21_SHIFT (21U) -/*! NSE21 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK) #define GPIO_PCNS_NSE22_MASK (0x400000U) #define GPIO_PCNS_NSE22_SHIFT (22U) -/*! NSE22 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK) #define GPIO_PCNS_NSE23_MASK (0x800000U) #define GPIO_PCNS_NSE23_SHIFT (23U) -/*! NSE23 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK) #define GPIO_PCNS_NSE24_MASK (0x1000000U) #define GPIO_PCNS_NSE24_SHIFT (24U) -/*! NSE24 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK) #define GPIO_PCNS_NSE25_MASK (0x2000000U) #define GPIO_PCNS_NSE25_SHIFT (25U) -/*! NSE25 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK) #define GPIO_PCNS_NSE26_MASK (0x4000000U) #define GPIO_PCNS_NSE26_SHIFT (26U) -/*! NSE26 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK) #define GPIO_PCNS_NSE27_MASK (0x8000000U) #define GPIO_PCNS_NSE27_SHIFT (27U) -/*! NSE27 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK) #define GPIO_PCNS_NSE28_MASK (0x10000000U) #define GPIO_PCNS_NSE28_SHIFT (28U) -/*! NSE28 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK) #define GPIO_PCNS_NSE29_MASK (0x20000000U) #define GPIO_PCNS_NSE29_SHIFT (29U) -/*! NSE29 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK) #define GPIO_PCNS_NSE30_MASK (0x40000000U) #define GPIO_PCNS_NSE30_SHIFT (30U) -/*! NSE30 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK) #define GPIO_PCNS_NSE31_MASK (0x80000000U) #define GPIO_PCNS_NSE31_SHIFT (31U) -/*! NSE31 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK) /*! @} */ -/*! @name ICNS - Interrupt Control Non-Secure */ +/*! @name ICNS - Interrupt Control Nonsecure */ /*! @{ */ #define GPIO_ICNS_NSE0_MASK (0x1U) #define GPIO_ICNS_NSE0_SHIFT (0U) -/*! NSE0 - Non-Secure Enable - * 0b0..The interrupt, output trigger or DMA request is configured for Secure access. Only software in Secure - * state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a - * pin that is already configured to use the corresponding interrupt, output trigger or DMA request. - * 0b1..The interrupt, output trigger or DMA request is configured for Non-Secure access. Only software in - * Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or - * reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK) #define GPIO_ICNS_NSE1_MASK (0x2U) #define GPIO_ICNS_NSE1_SHIFT (1U) -/*! NSE1 - Non-Secure Enable - * 0b0..The interrupt, output trigger or DMA request is configured for Secure access. Only software in Secure - * state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a - * pin that is already configured to use the corresponding interrupt, output trigger or DMA request. - * 0b1..The interrupt, output trigger or DMA request is configured for Non-Secure access. Only software in - * Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or - * reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK) /*! @} */ -/*! @name PCNP - Pin Control Non-Privilege */ +/*! @name PCNP - Pin Control Nonprivilege */ /*! @{ */ #define GPIO_PCNP_NPE0_MASK (0x1U) #define GPIO_PCNP_NPE0_SHIFT (0U) -/*! NPE0 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK) #define GPIO_PCNP_NPE1_MASK (0x2U) #define GPIO_PCNP_NPE1_SHIFT (1U) -/*! NPE1 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK) #define GPIO_PCNP_NPE2_MASK (0x4U) #define GPIO_PCNP_NPE2_SHIFT (2U) -/*! NPE2 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK) #define GPIO_PCNP_NPE3_MASK (0x8U) #define GPIO_PCNP_NPE3_SHIFT (3U) -/*! NPE3 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK) #define GPIO_PCNP_NPE4_MASK (0x10U) #define GPIO_PCNP_NPE4_SHIFT (4U) -/*! NPE4 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK) #define GPIO_PCNP_NPE5_MASK (0x20U) #define GPIO_PCNP_NPE5_SHIFT (5U) -/*! NPE5 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK) #define GPIO_PCNP_NPE6_MASK (0x40U) #define GPIO_PCNP_NPE6_SHIFT (6U) -/*! NPE6 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK) #define GPIO_PCNP_NPE7_MASK (0x80U) #define GPIO_PCNP_NPE7_SHIFT (7U) -/*! NPE7 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK) #define GPIO_PCNP_NPE8_MASK (0x100U) #define GPIO_PCNP_NPE8_SHIFT (8U) -/*! NPE8 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK) #define GPIO_PCNP_NPE9_MASK (0x200U) #define GPIO_PCNP_NPE9_SHIFT (9U) -/*! NPE9 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK) #define GPIO_PCNP_NPE10_MASK (0x400U) #define GPIO_PCNP_NPE10_SHIFT (10U) -/*! NPE10 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK) #define GPIO_PCNP_NPE11_MASK (0x800U) #define GPIO_PCNP_NPE11_SHIFT (11U) -/*! NPE11 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK) #define GPIO_PCNP_NPE12_MASK (0x1000U) #define GPIO_PCNP_NPE12_SHIFT (12U) -/*! NPE12 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK) #define GPIO_PCNP_NPE13_MASK (0x2000U) #define GPIO_PCNP_NPE13_SHIFT (13U) -/*! NPE13 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK) #define GPIO_PCNP_NPE14_MASK (0x4000U) #define GPIO_PCNP_NPE14_SHIFT (14U) -/*! NPE14 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK) #define GPIO_PCNP_NPE15_MASK (0x8000U) #define GPIO_PCNP_NPE15_SHIFT (15U) -/*! NPE15 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK) #define GPIO_PCNP_NPE16_MASK (0x10000U) #define GPIO_PCNP_NPE16_SHIFT (16U) -/*! NPE16 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK) #define GPIO_PCNP_NPE17_MASK (0x20000U) #define GPIO_PCNP_NPE17_SHIFT (17U) -/*! NPE17 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK) #define GPIO_PCNP_NPE18_MASK (0x40000U) #define GPIO_PCNP_NPE18_SHIFT (18U) -/*! NPE18 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK) #define GPIO_PCNP_NPE19_MASK (0x80000U) #define GPIO_PCNP_NPE19_SHIFT (19U) -/*! NPE19 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK) #define GPIO_PCNP_NPE20_MASK (0x100000U) #define GPIO_PCNP_NPE20_SHIFT (20U) -/*! NPE20 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK) #define GPIO_PCNP_NPE21_MASK (0x200000U) #define GPIO_PCNP_NPE21_SHIFT (21U) -/*! NPE21 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK) #define GPIO_PCNP_NPE22_MASK (0x400000U) #define GPIO_PCNP_NPE22_SHIFT (22U) -/*! NPE22 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK) #define GPIO_PCNP_NPE23_MASK (0x800000U) #define GPIO_PCNP_NPE23_SHIFT (23U) -/*! NPE23 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK) #define GPIO_PCNP_NPE24_MASK (0x1000000U) #define GPIO_PCNP_NPE24_SHIFT (24U) -/*! NPE24 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK) #define GPIO_PCNP_NPE25_MASK (0x2000000U) #define GPIO_PCNP_NPE25_SHIFT (25U) -/*! NPE25 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK) #define GPIO_PCNP_NPE26_MASK (0x4000000U) #define GPIO_PCNP_NPE26_SHIFT (26U) -/*! NPE26 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK) #define GPIO_PCNP_NPE27_MASK (0x8000000U) #define GPIO_PCNP_NPE27_SHIFT (27U) -/*! NPE27 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK) #define GPIO_PCNP_NPE28_MASK (0x10000000U) #define GPIO_PCNP_NPE28_SHIFT (28U) -/*! NPE28 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK) #define GPIO_PCNP_NPE29_MASK (0x20000000U) #define GPIO_PCNP_NPE29_SHIFT (29U) -/*! NPE29 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK) #define GPIO_PCNP_NPE30_MASK (0x40000000U) #define GPIO_PCNP_NPE30_SHIFT (30U) -/*! NPE30 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK) #define GPIO_PCNP_NPE31_MASK (0x80000000U) #define GPIO_PCNP_NPE31_SHIFT (31U) -/*! NPE31 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK) /*! @} */ -/*! @name ICNP - Interrupt Control Non-Privilege */ +/*! @name ICNP - Interrupt Control Nonprivilege */ /*! @{ */ #define GPIO_ICNP_NPE0_MASK (0x1U) #define GPIO_ICNP_NPE0_SHIFT (0U) -/*! NPE0 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use - * the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to - * use the corresponding interrupt/trigger output/DMA request. - * 0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can - * configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is - * already configured to use the corresponding interrupt/trigger output/DMA request. +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK) #define GPIO_ICNP_NPE1_MASK (0x2U) #define GPIO_ICNP_NPE1_SHIFT (1U) -/*! NPE1 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use - * the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to - * use the corresponding interrupt/trigger output/DMA request. - * 0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can - * configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is - * already configured to use the corresponding interrupt/trigger output/DMA request. +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK) /*! @} */ -/*! @name PDOR - Port Data Output Register */ +/*! @name PDOR - Port Data Output */ /*! @{ */ #define GPIO_PDOR_PDO0_MASK (0x1U) #define GPIO_PDOR_PDO0_SHIFT (0U) /*! PDO0 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) #define GPIO_PDOR_PDO1_MASK (0x2U) #define GPIO_PDOR_PDO1_SHIFT (1U) /*! PDO1 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) #define GPIO_PDOR_PDO2_MASK (0x4U) #define GPIO_PDOR_PDO2_SHIFT (2U) /*! PDO2 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) #define GPIO_PDOR_PDO3_MASK (0x8U) #define GPIO_PDOR_PDO3_SHIFT (3U) /*! PDO3 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) #define GPIO_PDOR_PDO4_MASK (0x10U) #define GPIO_PDOR_PDO4_SHIFT (4U) /*! PDO4 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) #define GPIO_PDOR_PDO5_MASK (0x20U) #define GPIO_PDOR_PDO5_SHIFT (5U) /*! PDO5 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) #define GPIO_PDOR_PDO6_MASK (0x40U) #define GPIO_PDOR_PDO6_SHIFT (6U) /*! PDO6 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) #define GPIO_PDOR_PDO7_MASK (0x80U) #define GPIO_PDOR_PDO7_SHIFT (7U) /*! PDO7 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) #define GPIO_PDOR_PDO8_MASK (0x100U) #define GPIO_PDOR_PDO8_SHIFT (8U) /*! PDO8 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) #define GPIO_PDOR_PDO9_MASK (0x200U) #define GPIO_PDOR_PDO9_SHIFT (9U) /*! PDO9 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) #define GPIO_PDOR_PDO10_MASK (0x400U) #define GPIO_PDOR_PDO10_SHIFT (10U) /*! PDO10 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) #define GPIO_PDOR_PDO11_MASK (0x800U) #define GPIO_PDOR_PDO11_SHIFT (11U) /*! PDO11 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) #define GPIO_PDOR_PDO12_MASK (0x1000U) #define GPIO_PDOR_PDO12_SHIFT (12U) /*! PDO12 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) #define GPIO_PDOR_PDO13_MASK (0x2000U) #define GPIO_PDOR_PDO13_SHIFT (13U) /*! PDO13 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) #define GPIO_PDOR_PDO14_MASK (0x4000U) #define GPIO_PDOR_PDO14_SHIFT (14U) /*! PDO14 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) #define GPIO_PDOR_PDO15_MASK (0x8000U) #define GPIO_PDOR_PDO15_SHIFT (15U) /*! PDO15 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) #define GPIO_PDOR_PDO16_MASK (0x10000U) #define GPIO_PDOR_PDO16_SHIFT (16U) /*! PDO16 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) #define GPIO_PDOR_PDO17_MASK (0x20000U) #define GPIO_PDOR_PDO17_SHIFT (17U) /*! PDO17 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) #define GPIO_PDOR_PDO18_MASK (0x40000U) #define GPIO_PDOR_PDO18_SHIFT (18U) /*! PDO18 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) #define GPIO_PDOR_PDO19_MASK (0x80000U) #define GPIO_PDOR_PDO19_SHIFT (19U) /*! PDO19 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) #define GPIO_PDOR_PDO20_MASK (0x100000U) #define GPIO_PDOR_PDO20_SHIFT (20U) /*! PDO20 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) #define GPIO_PDOR_PDO21_MASK (0x200000U) #define GPIO_PDOR_PDO21_SHIFT (21U) /*! PDO21 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) #define GPIO_PDOR_PDO22_MASK (0x400000U) #define GPIO_PDOR_PDO22_SHIFT (22U) /*! PDO22 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) #define GPIO_PDOR_PDO23_MASK (0x800000U) #define GPIO_PDOR_PDO23_SHIFT (23U) /*! PDO23 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) #define GPIO_PDOR_PDO24_MASK (0x1000000U) #define GPIO_PDOR_PDO24_SHIFT (24U) /*! PDO24 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) #define GPIO_PDOR_PDO25_MASK (0x2000000U) #define GPIO_PDOR_PDO25_SHIFT (25U) /*! PDO25 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) #define GPIO_PDOR_PDO26_MASK (0x4000000U) #define GPIO_PDOR_PDO26_SHIFT (26U) /*! PDO26 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) #define GPIO_PDOR_PDO27_MASK (0x8000000U) #define GPIO_PDOR_PDO27_SHIFT (27U) /*! PDO27 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) #define GPIO_PDOR_PDO28_MASK (0x10000000U) #define GPIO_PDOR_PDO28_SHIFT (28U) /*! PDO28 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) #define GPIO_PDOR_PDO29_MASK (0x20000000U) #define GPIO_PDOR_PDO29_SHIFT (29U) /*! PDO29 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) #define GPIO_PDOR_PDO30_MASK (0x40000000U) #define GPIO_PDOR_PDO30_SHIFT (30U) /*! PDO30 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) #define GPIO_PDOR_PDO31_MASK (0x80000000U) #define GPIO_PDOR_PDO31_SHIFT (31U) /*! PDO31 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) /*! @} */ -/*! @name PSOR - Port Set Output Register */ +/*! @name PSOR - Port Set Output */ /*! @{ */ #define GPIO_PSOR_PTSO0_MASK (0x1U) #define GPIO_PSOR_PTSO0_SHIFT (0U) /*! PTSO0 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) #define GPIO_PSOR_PTSO1_MASK (0x2U) #define GPIO_PSOR_PTSO1_SHIFT (1U) /*! PTSO1 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) #define GPIO_PSOR_PTSO2_MASK (0x4U) #define GPIO_PSOR_PTSO2_SHIFT (2U) /*! PTSO2 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) #define GPIO_PSOR_PTSO3_MASK (0x8U) #define GPIO_PSOR_PTSO3_SHIFT (3U) /*! PTSO3 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) #define GPIO_PSOR_PTSO4_MASK (0x10U) #define GPIO_PSOR_PTSO4_SHIFT (4U) /*! PTSO4 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) #define GPIO_PSOR_PTSO5_MASK (0x20U) #define GPIO_PSOR_PTSO5_SHIFT (5U) /*! PTSO5 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) #define GPIO_PSOR_PTSO6_MASK (0x40U) #define GPIO_PSOR_PTSO6_SHIFT (6U) /*! PTSO6 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) #define GPIO_PSOR_PTSO7_MASK (0x80U) #define GPIO_PSOR_PTSO7_SHIFT (7U) /*! PTSO7 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) #define GPIO_PSOR_PTSO8_MASK (0x100U) #define GPIO_PSOR_PTSO8_SHIFT (8U) /*! PTSO8 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) #define GPIO_PSOR_PTSO9_MASK (0x200U) #define GPIO_PSOR_PTSO9_SHIFT (9U) /*! PTSO9 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) #define GPIO_PSOR_PTSO10_MASK (0x400U) #define GPIO_PSOR_PTSO10_SHIFT (10U) /*! PTSO10 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) #define GPIO_PSOR_PTSO11_MASK (0x800U) #define GPIO_PSOR_PTSO11_SHIFT (11U) /*! PTSO11 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) #define GPIO_PSOR_PTSO12_MASK (0x1000U) #define GPIO_PSOR_PTSO12_SHIFT (12U) /*! PTSO12 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) #define GPIO_PSOR_PTSO13_MASK (0x2000U) #define GPIO_PSOR_PTSO13_SHIFT (13U) /*! PTSO13 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) #define GPIO_PSOR_PTSO14_MASK (0x4000U) #define GPIO_PSOR_PTSO14_SHIFT (14U) /*! PTSO14 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) #define GPIO_PSOR_PTSO15_MASK (0x8000U) #define GPIO_PSOR_PTSO15_SHIFT (15U) /*! PTSO15 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) #define GPIO_PSOR_PTSO16_MASK (0x10000U) #define GPIO_PSOR_PTSO16_SHIFT (16U) /*! PTSO16 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) #define GPIO_PSOR_PTSO17_MASK (0x20000U) #define GPIO_PSOR_PTSO17_SHIFT (17U) /*! PTSO17 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) #define GPIO_PSOR_PTSO18_MASK (0x40000U) #define GPIO_PSOR_PTSO18_SHIFT (18U) /*! PTSO18 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) #define GPIO_PSOR_PTSO19_MASK (0x80000U) #define GPIO_PSOR_PTSO19_SHIFT (19U) /*! PTSO19 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) #define GPIO_PSOR_PTSO20_MASK (0x100000U) #define GPIO_PSOR_PTSO20_SHIFT (20U) /*! PTSO20 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) #define GPIO_PSOR_PTSO21_MASK (0x200000U) #define GPIO_PSOR_PTSO21_SHIFT (21U) /*! PTSO21 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) #define GPIO_PSOR_PTSO22_MASK (0x400000U) #define GPIO_PSOR_PTSO22_SHIFT (22U) /*! PTSO22 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) #define GPIO_PSOR_PTSO23_MASK (0x800000U) #define GPIO_PSOR_PTSO23_SHIFT (23U) /*! PTSO23 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) #define GPIO_PSOR_PTSO24_MASK (0x1000000U) #define GPIO_PSOR_PTSO24_SHIFT (24U) /*! PTSO24 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) #define GPIO_PSOR_PTSO25_MASK (0x2000000U) #define GPIO_PSOR_PTSO25_SHIFT (25U) /*! PTSO25 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) #define GPIO_PSOR_PTSO26_MASK (0x4000000U) #define GPIO_PSOR_PTSO26_SHIFT (26U) /*! PTSO26 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) #define GPIO_PSOR_PTSO27_MASK (0x8000000U) #define GPIO_PSOR_PTSO27_SHIFT (27U) /*! PTSO27 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) #define GPIO_PSOR_PTSO28_MASK (0x10000000U) #define GPIO_PSOR_PTSO28_SHIFT (28U) /*! PTSO28 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) #define GPIO_PSOR_PTSO29_MASK (0x20000000U) #define GPIO_PSOR_PTSO29_SHIFT (29U) /*! PTSO29 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) #define GPIO_PSOR_PTSO30_MASK (0x40000000U) #define GPIO_PSOR_PTSO30_SHIFT (30U) /*! PTSO30 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) #define GPIO_PSOR_PTSO31_MASK (0x80000000U) #define GPIO_PSOR_PTSO31_SHIFT (31U) /*! PTSO31 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) /*! @} */ -/*! @name PCOR - Port Clear Output Register */ +/*! @name PCOR - Port Clear Output */ /*! @{ */ #define GPIO_PCOR_PTCO0_MASK (0x1U) #define GPIO_PCOR_PTCO0_SHIFT (0U) /*! PTCO0 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) #define GPIO_PCOR_PTCO1_MASK (0x2U) #define GPIO_PCOR_PTCO1_SHIFT (1U) /*! PTCO1 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) #define GPIO_PCOR_PTCO2_MASK (0x4U) #define GPIO_PCOR_PTCO2_SHIFT (2U) /*! PTCO2 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) #define GPIO_PCOR_PTCO3_MASK (0x8U) #define GPIO_PCOR_PTCO3_SHIFT (3U) /*! PTCO3 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) #define GPIO_PCOR_PTCO4_MASK (0x10U) #define GPIO_PCOR_PTCO4_SHIFT (4U) /*! PTCO4 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) #define GPIO_PCOR_PTCO5_MASK (0x20U) #define GPIO_PCOR_PTCO5_SHIFT (5U) /*! PTCO5 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) #define GPIO_PCOR_PTCO6_MASK (0x40U) #define GPIO_PCOR_PTCO6_SHIFT (6U) /*! PTCO6 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) #define GPIO_PCOR_PTCO7_MASK (0x80U) #define GPIO_PCOR_PTCO7_SHIFT (7U) /*! PTCO7 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) #define GPIO_PCOR_PTCO8_MASK (0x100U) #define GPIO_PCOR_PTCO8_SHIFT (8U) /*! PTCO8 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) #define GPIO_PCOR_PTCO9_MASK (0x200U) #define GPIO_PCOR_PTCO9_SHIFT (9U) /*! PTCO9 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) #define GPIO_PCOR_PTCO10_MASK (0x400U) #define GPIO_PCOR_PTCO10_SHIFT (10U) /*! PTCO10 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) #define GPIO_PCOR_PTCO11_MASK (0x800U) #define GPIO_PCOR_PTCO11_SHIFT (11U) /*! PTCO11 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) #define GPIO_PCOR_PTCO12_MASK (0x1000U) #define GPIO_PCOR_PTCO12_SHIFT (12U) /*! PTCO12 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) #define GPIO_PCOR_PTCO13_MASK (0x2000U) #define GPIO_PCOR_PTCO13_SHIFT (13U) /*! PTCO13 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) #define GPIO_PCOR_PTCO14_MASK (0x4000U) #define GPIO_PCOR_PTCO14_SHIFT (14U) /*! PTCO14 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) #define GPIO_PCOR_PTCO15_MASK (0x8000U) #define GPIO_PCOR_PTCO15_SHIFT (15U) /*! PTCO15 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) #define GPIO_PCOR_PTCO16_MASK (0x10000U) #define GPIO_PCOR_PTCO16_SHIFT (16U) /*! PTCO16 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) #define GPIO_PCOR_PTCO17_MASK (0x20000U) #define GPIO_PCOR_PTCO17_SHIFT (17U) /*! PTCO17 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) #define GPIO_PCOR_PTCO18_MASK (0x40000U) #define GPIO_PCOR_PTCO18_SHIFT (18U) /*! PTCO18 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) #define GPIO_PCOR_PTCO19_MASK (0x80000U) #define GPIO_PCOR_PTCO19_SHIFT (19U) /*! PTCO19 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) #define GPIO_PCOR_PTCO20_MASK (0x100000U) #define GPIO_PCOR_PTCO20_SHIFT (20U) /*! PTCO20 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) #define GPIO_PCOR_PTCO21_MASK (0x200000U) #define GPIO_PCOR_PTCO21_SHIFT (21U) /*! PTCO21 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) #define GPIO_PCOR_PTCO22_MASK (0x400000U) #define GPIO_PCOR_PTCO22_SHIFT (22U) /*! PTCO22 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) #define GPIO_PCOR_PTCO23_MASK (0x800000U) #define GPIO_PCOR_PTCO23_SHIFT (23U) /*! PTCO23 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) #define GPIO_PCOR_PTCO24_MASK (0x1000000U) #define GPIO_PCOR_PTCO24_SHIFT (24U) /*! PTCO24 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) #define GPIO_PCOR_PTCO25_MASK (0x2000000U) #define GPIO_PCOR_PTCO25_SHIFT (25U) /*! PTCO25 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) #define GPIO_PCOR_PTCO26_MASK (0x4000000U) #define GPIO_PCOR_PTCO26_SHIFT (26U) /*! PTCO26 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) #define GPIO_PCOR_PTCO27_MASK (0x8000000U) #define GPIO_PCOR_PTCO27_SHIFT (27U) /*! PTCO27 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) #define GPIO_PCOR_PTCO28_MASK (0x10000000U) #define GPIO_PCOR_PTCO28_SHIFT (28U) /*! PTCO28 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) #define GPIO_PCOR_PTCO29_MASK (0x20000000U) #define GPIO_PCOR_PTCO29_SHIFT (29U) /*! PTCO29 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) #define GPIO_PCOR_PTCO30_MASK (0x40000000U) #define GPIO_PCOR_PTCO30_SHIFT (30U) /*! PTCO30 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) #define GPIO_PCOR_PTCO31_MASK (0x80000000U) #define GPIO_PCOR_PTCO31_SHIFT (31U) /*! PTCO31 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) /*! @} */ -/*! @name PTOR - Port Toggle Output Register */ +/*! @name PTOR - Port Toggle Output */ /*! @{ */ #define GPIO_PTOR_PTTO0_MASK (0x1U) #define GPIO_PTOR_PTTO0_SHIFT (0U) /*! PTTO0 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) #define GPIO_PTOR_PTTO1_MASK (0x2U) #define GPIO_PTOR_PTTO1_SHIFT (1U) /*! PTTO1 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) #define GPIO_PTOR_PTTO2_MASK (0x4U) #define GPIO_PTOR_PTTO2_SHIFT (2U) /*! PTTO2 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) #define GPIO_PTOR_PTTO3_MASK (0x8U) #define GPIO_PTOR_PTTO3_SHIFT (3U) /*! PTTO3 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) #define GPIO_PTOR_PTTO4_MASK (0x10U) #define GPIO_PTOR_PTTO4_SHIFT (4U) /*! PTTO4 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) #define GPIO_PTOR_PTTO5_MASK (0x20U) #define GPIO_PTOR_PTTO5_SHIFT (5U) /*! PTTO5 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) #define GPIO_PTOR_PTTO6_MASK (0x40U) #define GPIO_PTOR_PTTO6_SHIFT (6U) /*! PTTO6 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) #define GPIO_PTOR_PTTO7_MASK (0x80U) #define GPIO_PTOR_PTTO7_SHIFT (7U) /*! PTTO7 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) #define GPIO_PTOR_PTTO8_MASK (0x100U) #define GPIO_PTOR_PTTO8_SHIFT (8U) /*! PTTO8 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) #define GPIO_PTOR_PTTO9_MASK (0x200U) #define GPIO_PTOR_PTTO9_SHIFT (9U) /*! PTTO9 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) #define GPIO_PTOR_PTTO10_MASK (0x400U) #define GPIO_PTOR_PTTO10_SHIFT (10U) /*! PTTO10 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) #define GPIO_PTOR_PTTO11_MASK (0x800U) #define GPIO_PTOR_PTTO11_SHIFT (11U) /*! PTTO11 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) #define GPIO_PTOR_PTTO12_MASK (0x1000U) #define GPIO_PTOR_PTTO12_SHIFT (12U) /*! PTTO12 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) #define GPIO_PTOR_PTTO13_MASK (0x2000U) #define GPIO_PTOR_PTTO13_SHIFT (13U) /*! PTTO13 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) #define GPIO_PTOR_PTTO14_MASK (0x4000U) #define GPIO_PTOR_PTTO14_SHIFT (14U) /*! PTTO14 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) #define GPIO_PTOR_PTTO15_MASK (0x8000U) #define GPIO_PTOR_PTTO15_SHIFT (15U) /*! PTTO15 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) #define GPIO_PTOR_PTTO16_MASK (0x10000U) #define GPIO_PTOR_PTTO16_SHIFT (16U) /*! PTTO16 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) #define GPIO_PTOR_PTTO17_MASK (0x20000U) #define GPIO_PTOR_PTTO17_SHIFT (17U) /*! PTTO17 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) #define GPIO_PTOR_PTTO18_MASK (0x40000U) #define GPIO_PTOR_PTTO18_SHIFT (18U) /*! PTTO18 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) #define GPIO_PTOR_PTTO19_MASK (0x80000U) #define GPIO_PTOR_PTTO19_SHIFT (19U) /*! PTTO19 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) #define GPIO_PTOR_PTTO20_MASK (0x100000U) #define GPIO_PTOR_PTTO20_SHIFT (20U) /*! PTTO20 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) #define GPIO_PTOR_PTTO21_MASK (0x200000U) #define GPIO_PTOR_PTTO21_SHIFT (21U) /*! PTTO21 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) #define GPIO_PTOR_PTTO22_MASK (0x400000U) #define GPIO_PTOR_PTTO22_SHIFT (22U) /*! PTTO22 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) #define GPIO_PTOR_PTTO23_MASK (0x800000U) #define GPIO_PTOR_PTTO23_SHIFT (23U) /*! PTTO23 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) #define GPIO_PTOR_PTTO24_MASK (0x1000000U) #define GPIO_PTOR_PTTO24_SHIFT (24U) /*! PTTO24 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) #define GPIO_PTOR_PTTO25_MASK (0x2000000U) #define GPIO_PTOR_PTTO25_SHIFT (25U) /*! PTTO25 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) #define GPIO_PTOR_PTTO26_MASK (0x4000000U) #define GPIO_PTOR_PTTO26_SHIFT (26U) /*! PTTO26 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) #define GPIO_PTOR_PTTO27_MASK (0x8000000U) #define GPIO_PTOR_PTTO27_SHIFT (27U) /*! PTTO27 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) #define GPIO_PTOR_PTTO28_MASK (0x10000000U) #define GPIO_PTOR_PTTO28_SHIFT (28U) /*! PTTO28 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) #define GPIO_PTOR_PTTO29_MASK (0x20000000U) #define GPIO_PTOR_PTTO29_SHIFT (29U) /*! PTTO29 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) #define GPIO_PTOR_PTTO30_MASK (0x40000000U) #define GPIO_PTOR_PTTO30_SHIFT (30U) /*! PTTO30 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) #define GPIO_PTOR_PTTO31_MASK (0x80000000U) #define GPIO_PTOR_PTTO31_SHIFT (31U) /*! PTTO31 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) /*! @} */ -/*! @name PDIR - Port Data Input Register */ +/*! @name PDIR - Port Data Input */ /*! @{ */ #define GPIO_PDIR_PDI0_MASK (0x1U) #define GPIO_PDIR_PDI0_SHIFT (0U) /*! PDI0 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) #define GPIO_PDIR_PDI1_MASK (0x2U) #define GPIO_PDIR_PDI1_SHIFT (1U) /*! PDI1 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) #define GPIO_PDIR_PDI2_MASK (0x4U) #define GPIO_PDIR_PDI2_SHIFT (2U) /*! PDI2 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) #define GPIO_PDIR_PDI3_MASK (0x8U) #define GPIO_PDIR_PDI3_SHIFT (3U) /*! PDI3 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) #define GPIO_PDIR_PDI4_MASK (0x10U) #define GPIO_PDIR_PDI4_SHIFT (4U) /*! PDI4 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) #define GPIO_PDIR_PDI5_MASK (0x20U) #define GPIO_PDIR_PDI5_SHIFT (5U) /*! PDI5 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) #define GPIO_PDIR_PDI6_MASK (0x40U) #define GPIO_PDIR_PDI6_SHIFT (6U) /*! PDI6 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) #define GPIO_PDIR_PDI7_MASK (0x80U) #define GPIO_PDIR_PDI7_SHIFT (7U) /*! PDI7 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) #define GPIO_PDIR_PDI8_MASK (0x100U) #define GPIO_PDIR_PDI8_SHIFT (8U) /*! PDI8 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) #define GPIO_PDIR_PDI9_MASK (0x200U) #define GPIO_PDIR_PDI9_SHIFT (9U) /*! PDI9 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) #define GPIO_PDIR_PDI10_MASK (0x400U) #define GPIO_PDIR_PDI10_SHIFT (10U) /*! PDI10 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) #define GPIO_PDIR_PDI11_MASK (0x800U) #define GPIO_PDIR_PDI11_SHIFT (11U) /*! PDI11 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) #define GPIO_PDIR_PDI12_MASK (0x1000U) #define GPIO_PDIR_PDI12_SHIFT (12U) /*! PDI12 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) #define GPIO_PDIR_PDI13_MASK (0x2000U) #define GPIO_PDIR_PDI13_SHIFT (13U) /*! PDI13 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) #define GPIO_PDIR_PDI14_MASK (0x4000U) #define GPIO_PDIR_PDI14_SHIFT (14U) /*! PDI14 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) #define GPIO_PDIR_PDI15_MASK (0x8000U) #define GPIO_PDIR_PDI15_SHIFT (15U) /*! PDI15 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) #define GPIO_PDIR_PDI16_MASK (0x10000U) #define GPIO_PDIR_PDI16_SHIFT (16U) /*! PDI16 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) #define GPIO_PDIR_PDI17_MASK (0x20000U) #define GPIO_PDIR_PDI17_SHIFT (17U) /*! PDI17 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) #define GPIO_PDIR_PDI18_MASK (0x40000U) #define GPIO_PDIR_PDI18_SHIFT (18U) /*! PDI18 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) #define GPIO_PDIR_PDI19_MASK (0x80000U) #define GPIO_PDIR_PDI19_SHIFT (19U) /*! PDI19 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) #define GPIO_PDIR_PDI20_MASK (0x100000U) #define GPIO_PDIR_PDI20_SHIFT (20U) /*! PDI20 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) #define GPIO_PDIR_PDI21_MASK (0x200000U) #define GPIO_PDIR_PDI21_SHIFT (21U) /*! PDI21 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) #define GPIO_PDIR_PDI22_MASK (0x400000U) #define GPIO_PDIR_PDI22_SHIFT (22U) /*! PDI22 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) #define GPIO_PDIR_PDI23_MASK (0x800000U) #define GPIO_PDIR_PDI23_SHIFT (23U) /*! PDI23 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) #define GPIO_PDIR_PDI24_MASK (0x1000000U) #define GPIO_PDIR_PDI24_SHIFT (24U) /*! PDI24 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) #define GPIO_PDIR_PDI25_MASK (0x2000000U) #define GPIO_PDIR_PDI25_SHIFT (25U) /*! PDI25 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) #define GPIO_PDIR_PDI26_MASK (0x4000000U) #define GPIO_PDIR_PDI26_SHIFT (26U) /*! PDI26 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) #define GPIO_PDIR_PDI27_MASK (0x8000000U) #define GPIO_PDIR_PDI27_SHIFT (27U) /*! PDI27 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) #define GPIO_PDIR_PDI28_MASK (0x10000000U) #define GPIO_PDIR_PDI28_SHIFT (28U) /*! PDI28 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) #define GPIO_PDIR_PDI29_MASK (0x20000000U) #define GPIO_PDIR_PDI29_SHIFT (29U) /*! PDI29 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) #define GPIO_PDIR_PDI30_MASK (0x40000000U) #define GPIO_PDIR_PDI30_SHIFT (30U) /*! PDI30 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) #define GPIO_PDIR_PDI31_MASK (0x80000000U) #define GPIO_PDIR_PDI31_SHIFT (31U) /*! PDI31 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) /*! @} */ -/*! @name PDDR - Port Data Direction Register */ +/*! @name PDDR - Port Data Direction */ /*! @{ */ #define GPIO_PDDR_PDD0_MASK (0x1U) #define GPIO_PDDR_PDD0_SHIFT (0U) /*! PDD0 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) #define GPIO_PDDR_PDD1_MASK (0x2U) #define GPIO_PDDR_PDD1_SHIFT (1U) /*! PDD1 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) #define GPIO_PDDR_PDD2_MASK (0x4U) #define GPIO_PDDR_PDD2_SHIFT (2U) /*! PDD2 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) #define GPIO_PDDR_PDD3_MASK (0x8U) #define GPIO_PDDR_PDD3_SHIFT (3U) /*! PDD3 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) #define GPIO_PDDR_PDD4_MASK (0x10U) #define GPIO_PDDR_PDD4_SHIFT (4U) /*! PDD4 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) #define GPIO_PDDR_PDD5_MASK (0x20U) #define GPIO_PDDR_PDD5_SHIFT (5U) /*! PDD5 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) #define GPIO_PDDR_PDD6_MASK (0x40U) #define GPIO_PDDR_PDD6_SHIFT (6U) /*! PDD6 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) #define GPIO_PDDR_PDD7_MASK (0x80U) #define GPIO_PDDR_PDD7_SHIFT (7U) /*! PDD7 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) #define GPIO_PDDR_PDD8_MASK (0x100U) #define GPIO_PDDR_PDD8_SHIFT (8U) /*! PDD8 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) #define GPIO_PDDR_PDD9_MASK (0x200U) #define GPIO_PDDR_PDD9_SHIFT (9U) /*! PDD9 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) #define GPIO_PDDR_PDD10_MASK (0x400U) #define GPIO_PDDR_PDD10_SHIFT (10U) /*! PDD10 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) #define GPIO_PDDR_PDD11_MASK (0x800U) #define GPIO_PDDR_PDD11_SHIFT (11U) /*! PDD11 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) #define GPIO_PDDR_PDD12_MASK (0x1000U) #define GPIO_PDDR_PDD12_SHIFT (12U) /*! PDD12 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) #define GPIO_PDDR_PDD13_MASK (0x2000U) #define GPIO_PDDR_PDD13_SHIFT (13U) /*! PDD13 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) #define GPIO_PDDR_PDD14_MASK (0x4000U) #define GPIO_PDDR_PDD14_SHIFT (14U) /*! PDD14 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) #define GPIO_PDDR_PDD15_MASK (0x8000U) #define GPIO_PDDR_PDD15_SHIFT (15U) /*! PDD15 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) #define GPIO_PDDR_PDD16_MASK (0x10000U) #define GPIO_PDDR_PDD16_SHIFT (16U) /*! PDD16 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) #define GPIO_PDDR_PDD17_MASK (0x20000U) #define GPIO_PDDR_PDD17_SHIFT (17U) /*! PDD17 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) #define GPIO_PDDR_PDD18_MASK (0x40000U) #define GPIO_PDDR_PDD18_SHIFT (18U) /*! PDD18 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) #define GPIO_PDDR_PDD19_MASK (0x80000U) #define GPIO_PDDR_PDD19_SHIFT (19U) /*! PDD19 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) #define GPIO_PDDR_PDD20_MASK (0x100000U) #define GPIO_PDDR_PDD20_SHIFT (20U) /*! PDD20 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) #define GPIO_PDDR_PDD21_MASK (0x200000U) #define GPIO_PDDR_PDD21_SHIFT (21U) /*! PDD21 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) #define GPIO_PDDR_PDD22_MASK (0x400000U) #define GPIO_PDDR_PDD22_SHIFT (22U) /*! PDD22 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) #define GPIO_PDDR_PDD23_MASK (0x800000U) #define GPIO_PDDR_PDD23_SHIFT (23U) /*! PDD23 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) #define GPIO_PDDR_PDD24_MASK (0x1000000U) #define GPIO_PDDR_PDD24_SHIFT (24U) /*! PDD24 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) #define GPIO_PDDR_PDD25_MASK (0x2000000U) #define GPIO_PDDR_PDD25_SHIFT (25U) /*! PDD25 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) #define GPIO_PDDR_PDD26_MASK (0x4000000U) #define GPIO_PDDR_PDD26_SHIFT (26U) /*! PDD26 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) #define GPIO_PDDR_PDD27_MASK (0x8000000U) #define GPIO_PDDR_PDD27_SHIFT (27U) /*! PDD27 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) #define GPIO_PDDR_PDD28_MASK (0x10000000U) #define GPIO_PDDR_PDD28_SHIFT (28U) /*! PDD28 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) #define GPIO_PDDR_PDD29_MASK (0x20000000U) #define GPIO_PDDR_PDD29_SHIFT (29U) /*! PDD29 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) #define GPIO_PDDR_PDD30_MASK (0x40000000U) #define GPIO_PDDR_PDD30_SHIFT (30U) /*! PDD30 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) #define GPIO_PDDR_PDD31_MASK (0x80000000U) #define GPIO_PDDR_PDD31_SHIFT (31U) /*! PDD31 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) /*! @} */ -/*! @name PIDR - Port Input Disable Register */ +/*! @name PIDR - Port Input Disable */ /*! @{ */ #define GPIO_PIDR_PID0_MASK (0x1U) #define GPIO_PIDR_PID0_SHIFT (0U) /*! PID0 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) #define GPIO_PIDR_PID1_MASK (0x2U) #define GPIO_PIDR_PID1_SHIFT (1U) /*! PID1 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) #define GPIO_PIDR_PID2_MASK (0x4U) #define GPIO_PIDR_PID2_SHIFT (2U) /*! PID2 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) #define GPIO_PIDR_PID3_MASK (0x8U) #define GPIO_PIDR_PID3_SHIFT (3U) /*! PID3 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) #define GPIO_PIDR_PID4_MASK (0x10U) #define GPIO_PIDR_PID4_SHIFT (4U) /*! PID4 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) #define GPIO_PIDR_PID5_MASK (0x20U) #define GPIO_PIDR_PID5_SHIFT (5U) /*! PID5 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) #define GPIO_PIDR_PID6_MASK (0x40U) #define GPIO_PIDR_PID6_SHIFT (6U) /*! PID6 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) #define GPIO_PIDR_PID7_MASK (0x80U) #define GPIO_PIDR_PID7_SHIFT (7U) /*! PID7 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) #define GPIO_PIDR_PID8_MASK (0x100U) #define GPIO_PIDR_PID8_SHIFT (8U) /*! PID8 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) #define GPIO_PIDR_PID9_MASK (0x200U) #define GPIO_PIDR_PID9_SHIFT (9U) /*! PID9 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) #define GPIO_PIDR_PID10_MASK (0x400U) #define GPIO_PIDR_PID10_SHIFT (10U) /*! PID10 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) #define GPIO_PIDR_PID11_MASK (0x800U) #define GPIO_PIDR_PID11_SHIFT (11U) /*! PID11 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) #define GPIO_PIDR_PID12_MASK (0x1000U) #define GPIO_PIDR_PID12_SHIFT (12U) /*! PID12 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) #define GPIO_PIDR_PID13_MASK (0x2000U) #define GPIO_PIDR_PID13_SHIFT (13U) /*! PID13 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) #define GPIO_PIDR_PID14_MASK (0x4000U) #define GPIO_PIDR_PID14_SHIFT (14U) /*! PID14 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) #define GPIO_PIDR_PID15_MASK (0x8000U) #define GPIO_PIDR_PID15_SHIFT (15U) /*! PID15 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) #define GPIO_PIDR_PID16_MASK (0x10000U) #define GPIO_PIDR_PID16_SHIFT (16U) /*! PID16 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) #define GPIO_PIDR_PID17_MASK (0x20000U) #define GPIO_PIDR_PID17_SHIFT (17U) /*! PID17 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) #define GPIO_PIDR_PID18_MASK (0x40000U) #define GPIO_PIDR_PID18_SHIFT (18U) /*! PID18 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) #define GPIO_PIDR_PID19_MASK (0x80000U) #define GPIO_PIDR_PID19_SHIFT (19U) /*! PID19 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) #define GPIO_PIDR_PID20_MASK (0x100000U) #define GPIO_PIDR_PID20_SHIFT (20U) /*! PID20 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) #define GPIO_PIDR_PID21_MASK (0x200000U) #define GPIO_PIDR_PID21_SHIFT (21U) /*! PID21 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) #define GPIO_PIDR_PID22_MASK (0x400000U) #define GPIO_PIDR_PID22_SHIFT (22U) /*! PID22 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) #define GPIO_PIDR_PID23_MASK (0x800000U) #define GPIO_PIDR_PID23_SHIFT (23U) /*! PID23 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) #define GPIO_PIDR_PID24_MASK (0x1000000U) #define GPIO_PIDR_PID24_SHIFT (24U) /*! PID24 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) #define GPIO_PIDR_PID25_MASK (0x2000000U) #define GPIO_PIDR_PID25_SHIFT (25U) /*! PID25 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) #define GPIO_PIDR_PID26_MASK (0x4000000U) #define GPIO_PIDR_PID26_SHIFT (26U) /*! PID26 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) #define GPIO_PIDR_PID27_MASK (0x8000000U) #define GPIO_PIDR_PID27_SHIFT (27U) /*! PID27 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) #define GPIO_PIDR_PID28_MASK (0x10000000U) #define GPIO_PIDR_PID28_SHIFT (28U) /*! PID28 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) #define GPIO_PIDR_PID29_MASK (0x20000000U) #define GPIO_PIDR_PID29_SHIFT (29U) /*! PID29 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) #define GPIO_PIDR_PID30_MASK (0x40000000U) #define GPIO_PIDR_PID30_SHIFT (30U) /*! PID30 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) #define GPIO_PIDR_PID31_MASK (0x80000000U) #define GPIO_PIDR_PID31_SHIFT (31U) /*! PID31 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) /*! @} */ -/*! @name PDR - Pin Data Register a */ +/*! @name PDR - Pin Data */ /*! @{ */ #define GPIO_PDR_PD_MASK (0x1U) #define GPIO_PDR_PD_SHIFT (0U) -/*! PD - Pin Data (input and output) - * 0b0..Pin logic level is logic zero or not configured for use by digital function. - * 0b1..Pin logic level is logic one. +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one */ #define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) /*! @} */ @@ -31325,57 +31325,56 @@ typedef struct { /* The count of GPIO_PDR */ #define GPIO_PDR_COUNT (32U) -/*! @name ICR - Interrupt Control Register 0..Interrupt Control Register 31 */ +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ /*! @{ */ #define GPIO_ICR_IRQC_MASK (0xF0000U) #define GPIO_ICR_IRQC_SHIFT (16U) /*! IRQC - Interrupt Configuration - * 0b0000..Interrupt Status Flag (ISF) is disabled. - * 0b0001..ISF flag and DMA request on rising edge. - * 0b0010..ISF flag and DMA request on falling edge. - * 0b0011..ISF flag and DMA request on either edge. - * 0b0100..Reserved. - * 0b0101..ISF flag sets on rising edge. - * 0b0110..ISF flag sets on falling edge. - * 0b0111..ISF flag sets on either edge. - * 0b1000..ISF flag and Interrupt when logic 0. - * 0b1001..ISF flag and Interrupt on rising-edge. - * 0b1010..ISF flag and Interrupt on falling-edge. - * 0b1011..ISF flag and Interrupt on either edge. - * 0b1100..ISF flag and Interrupt when logic 1. - * 0b1101..Enable active high trigger output, ISF flag on rising edge. Pin state is ORed with other enabled - * triggers to generate the output trigger, for use by other peripherals. - * 0b1110..Enable active low trigger output, ISF flag on falling edge. Pin state is inverted and ORed with other - * enabled triggers to generate the output trigger, for use by other peripherals. - * 0b1111..Reserved. + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved */ #define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) #define GPIO_ICR_IRQS_MASK (0x100000U) #define GPIO_ICR_IRQS_SHIFT (20U) /*! IRQS - Interrupt Select - * 0b0..Interrupt/trigger output/DMA request 0. - * 0b1..Interrupt/trigger output/DMA request 1. + * 0b0..Interrupt, trigger output, or DMA request 0 + * 0b1..Interrupt, trigger output, or DMA request 1 */ #define GPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK) #define GPIO_ICR_LK_MASK (0x800000U) #define GPIO_ICR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Interrupt configuration by ICR[23:0] is not locked and can be updated. - * 0b1..Interrupt configuration by ICR[23:0] is locked and cannot be updated until next system reset. +/*! LK - Lock + * 0b0..Lock + * 0b1..Do not lock */ #define GPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK) #define GPIO_ICR_ISF_MASK (0x1000000U) #define GPIO_ICR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag - * 0b0..Configured interrupt is not detected. - * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the - * corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the - * flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive - * interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) /*! @} */ @@ -31383,134 +31382,134 @@ typedef struct { /* The count of GPIO_ICR */ #define GPIO_ICR_COUNT (32U) -/*! @name GICLR - Global Interrupt Control Low Register */ +/*! @name GICLR - Global Interrupt Control Low */ /*! @{ */ #define GPIO_GICLR_GIWE0_MASK (0x1U) #define GPIO_GICLR_GIWE0_SHIFT (0U) /*! GIWE0 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) #define GPIO_GICLR_GIWE1_MASK (0x2U) #define GPIO_GICLR_GIWE1_SHIFT (1U) /*! GIWE1 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) #define GPIO_GICLR_GIWE2_MASK (0x4U) #define GPIO_GICLR_GIWE2_SHIFT (2U) /*! GIWE2 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) #define GPIO_GICLR_GIWE3_MASK (0x8U) #define GPIO_GICLR_GIWE3_SHIFT (3U) /*! GIWE3 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) #define GPIO_GICLR_GIWE4_MASK (0x10U) #define GPIO_GICLR_GIWE4_SHIFT (4U) /*! GIWE4 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) #define GPIO_GICLR_GIWE5_MASK (0x20U) #define GPIO_GICLR_GIWE5_SHIFT (5U) /*! GIWE5 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) #define GPIO_GICLR_GIWE6_MASK (0x40U) #define GPIO_GICLR_GIWE6_SHIFT (6U) /*! GIWE6 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) #define GPIO_GICLR_GIWE7_MASK (0x80U) #define GPIO_GICLR_GIWE7_SHIFT (7U) /*! GIWE7 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) #define GPIO_GICLR_GIWE8_MASK (0x100U) #define GPIO_GICLR_GIWE8_SHIFT (8U) /*! GIWE8 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) #define GPIO_GICLR_GIWE9_MASK (0x200U) #define GPIO_GICLR_GIWE9_SHIFT (9U) /*! GIWE9 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) #define GPIO_GICLR_GIWE10_MASK (0x400U) #define GPIO_GICLR_GIWE10_SHIFT (10U) /*! GIWE10 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) #define GPIO_GICLR_GIWE11_MASK (0x800U) #define GPIO_GICLR_GIWE11_SHIFT (11U) /*! GIWE11 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) #define GPIO_GICLR_GIWE12_MASK (0x1000U) #define GPIO_GICLR_GIWE12_SHIFT (12U) /*! GIWE12 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) #define GPIO_GICLR_GIWE13_MASK (0x2000U) #define GPIO_GICLR_GIWE13_SHIFT (13U) /*! GIWE13 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) #define GPIO_GICLR_GIWE14_MASK (0x4000U) #define GPIO_GICLR_GIWE14_SHIFT (14U) /*! GIWE14 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) #define GPIO_GICLR_GIWE15_MASK (0x8000U) #define GPIO_GICLR_GIWE15_SHIFT (15U) /*! GIWE15 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) @@ -31520,134 +31519,134 @@ typedef struct { #define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) /*! @} */ -/*! @name GICHR - Global Interrupt Control High Register */ +/*! @name GICHR - Global Interrupt Control High */ /*! @{ */ #define GPIO_GICHR_GIWE16_MASK (0x1U) #define GPIO_GICHR_GIWE16_SHIFT (0U) /*! GIWE16 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) #define GPIO_GICHR_GIWE17_MASK (0x2U) #define GPIO_GICHR_GIWE17_SHIFT (1U) /*! GIWE17 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) #define GPIO_GICHR_GIWE18_MASK (0x4U) #define GPIO_GICHR_GIWE18_SHIFT (2U) /*! GIWE18 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) #define GPIO_GICHR_GIWE19_MASK (0x8U) #define GPIO_GICHR_GIWE19_SHIFT (3U) /*! GIWE19 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) #define GPIO_GICHR_GIWE20_MASK (0x10U) #define GPIO_GICHR_GIWE20_SHIFT (4U) /*! GIWE20 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) #define GPIO_GICHR_GIWE21_MASK (0x20U) #define GPIO_GICHR_GIWE21_SHIFT (5U) /*! GIWE21 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) #define GPIO_GICHR_GIWE22_MASK (0x40U) #define GPIO_GICHR_GIWE22_SHIFT (6U) /*! GIWE22 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) #define GPIO_GICHR_GIWE23_MASK (0x80U) #define GPIO_GICHR_GIWE23_SHIFT (7U) /*! GIWE23 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) #define GPIO_GICHR_GIWE24_MASK (0x100U) #define GPIO_GICHR_GIWE24_SHIFT (8U) /*! GIWE24 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) #define GPIO_GICHR_GIWE25_MASK (0x200U) #define GPIO_GICHR_GIWE25_SHIFT (9U) /*! GIWE25 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) #define GPIO_GICHR_GIWE26_MASK (0x400U) #define GPIO_GICHR_GIWE26_SHIFT (10U) /*! GIWE26 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) #define GPIO_GICHR_GIWE27_MASK (0x800U) #define GPIO_GICHR_GIWE27_SHIFT (11U) /*! GIWE27 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) #define GPIO_GICHR_GIWE28_MASK (0x1000U) #define GPIO_GICHR_GIWE28_SHIFT (12U) /*! GIWE28 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) #define GPIO_GICHR_GIWE29_MASK (0x2000U) #define GPIO_GICHR_GIWE29_SHIFT (13U) /*! GIWE29 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) #define GPIO_GICHR_GIWE30_MASK (0x4000U) #define GPIO_GICHR_GIWE30_SHIFT (14U) /*! GIWE30 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) #define GPIO_GICHR_GIWE31_MASK (0x8000U) #define GPIO_GICHR_GIWE31_SHIFT (15U) /*! GIWE31 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) @@ -31657,390 +31656,326 @@ typedef struct { #define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) /*! @} */ -/*! @name ISFR - Interrupt Status Flag Register */ +/*! @name ISFR - Interrupt Status Flag */ /*! @{ */ #define GPIO_ISFR_ISF0_MASK (0x1U) #define GPIO_ISFR_ISF0_SHIFT (0U) /*! ISF0 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) #define GPIO_ISFR_ISF1_MASK (0x2U) #define GPIO_ISFR_ISF1_SHIFT (1U) /*! ISF1 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) #define GPIO_ISFR_ISF2_MASK (0x4U) #define GPIO_ISFR_ISF2_SHIFT (2U) /*! ISF2 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) #define GPIO_ISFR_ISF3_MASK (0x8U) #define GPIO_ISFR_ISF3_SHIFT (3U) /*! ISF3 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) #define GPIO_ISFR_ISF4_MASK (0x10U) #define GPIO_ISFR_ISF4_SHIFT (4U) /*! ISF4 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) #define GPIO_ISFR_ISF5_MASK (0x20U) #define GPIO_ISFR_ISF5_SHIFT (5U) /*! ISF5 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) #define GPIO_ISFR_ISF6_MASK (0x40U) #define GPIO_ISFR_ISF6_SHIFT (6U) /*! ISF6 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) #define GPIO_ISFR_ISF7_MASK (0x80U) #define GPIO_ISFR_ISF7_SHIFT (7U) /*! ISF7 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) #define GPIO_ISFR_ISF8_MASK (0x100U) #define GPIO_ISFR_ISF8_SHIFT (8U) /*! ISF8 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) #define GPIO_ISFR_ISF9_MASK (0x200U) #define GPIO_ISFR_ISF9_SHIFT (9U) /*! ISF9 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) #define GPIO_ISFR_ISF10_MASK (0x400U) #define GPIO_ISFR_ISF10_SHIFT (10U) /*! ISF10 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) #define GPIO_ISFR_ISF11_MASK (0x800U) #define GPIO_ISFR_ISF11_SHIFT (11U) /*! ISF11 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) #define GPIO_ISFR_ISF12_MASK (0x1000U) #define GPIO_ISFR_ISF12_SHIFT (12U) /*! ISF12 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) #define GPIO_ISFR_ISF13_MASK (0x2000U) #define GPIO_ISFR_ISF13_SHIFT (13U) /*! ISF13 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) #define GPIO_ISFR_ISF14_MASK (0x4000U) #define GPIO_ISFR_ISF14_SHIFT (14U) /*! ISF14 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) #define GPIO_ISFR_ISF15_MASK (0x8000U) #define GPIO_ISFR_ISF15_SHIFT (15U) /*! ISF15 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) #define GPIO_ISFR_ISF16_MASK (0x10000U) #define GPIO_ISFR_ISF16_SHIFT (16U) /*! ISF16 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) #define GPIO_ISFR_ISF17_MASK (0x20000U) #define GPIO_ISFR_ISF17_SHIFT (17U) /*! ISF17 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) #define GPIO_ISFR_ISF18_MASK (0x40000U) #define GPIO_ISFR_ISF18_SHIFT (18U) /*! ISF18 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) #define GPIO_ISFR_ISF19_MASK (0x80000U) #define GPIO_ISFR_ISF19_SHIFT (19U) /*! ISF19 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) #define GPIO_ISFR_ISF20_MASK (0x100000U) #define GPIO_ISFR_ISF20_SHIFT (20U) /*! ISF20 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) #define GPIO_ISFR_ISF21_MASK (0x200000U) #define GPIO_ISFR_ISF21_SHIFT (21U) /*! ISF21 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) #define GPIO_ISFR_ISF22_MASK (0x400000U) #define GPIO_ISFR_ISF22_SHIFT (22U) /*! ISF22 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) #define GPIO_ISFR_ISF23_MASK (0x800000U) #define GPIO_ISFR_ISF23_SHIFT (23U) /*! ISF23 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) #define GPIO_ISFR_ISF24_MASK (0x1000000U) #define GPIO_ISFR_ISF24_SHIFT (24U) /*! ISF24 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) #define GPIO_ISFR_ISF25_MASK (0x2000000U) #define GPIO_ISFR_ISF25_SHIFT (25U) /*! ISF25 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) #define GPIO_ISFR_ISF26_MASK (0x4000000U) #define GPIO_ISFR_ISF26_SHIFT (26U) /*! ISF26 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) #define GPIO_ISFR_ISF27_MASK (0x8000000U) #define GPIO_ISFR_ISF27_SHIFT (27U) /*! ISF27 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) #define GPIO_ISFR_ISF28_MASK (0x10000000U) #define GPIO_ISFR_ISF28_SHIFT (28U) /*! ISF28 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) #define GPIO_ISFR_ISF29_MASK (0x20000000U) #define GPIO_ISFR_ISF29_SHIFT (29U) /*! ISF29 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) #define GPIO_ISFR_ISF30_MASK (0x40000000U) #define GPIO_ISFR_ISF30_SHIFT (30U) /*! ISF30 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) #define GPIO_ISFR_ISF31_MASK (0x80000000U) #define GPIO_ISFR_ISF31_SHIFT (31U) /*! ISF31 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) /*! @} */ @@ -32153,13 +32088,17 @@ typedef struct { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO0_ALIAS1_BASE, GPIO1_BASE, GPIO1_ALIAS1_BASE, GPIO2_BASE, GPIO2_ALIAS1_BASE, GPIO3_BASE, GPIO3_ALIAS1_BASE, GPIO4_BASE, GPIO4_ALIAS1_BASE, GPIO5_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } + #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO0_ALIAS1_NS, GPIO1_NS, GPIO1_ALIAS1_NS, GPIO2_NS, GPIO2_ALIAS1_NS, GPIO3_NS, GPIO3_ALIAS1_NS, GPIO4_NS, GPIO4_ALIAS1_NS, GPIO5_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } + #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) @@ -32210,24 +32149,11 @@ typedef struct { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS \ - { \ - GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE \ - } -#define GPIO_ALIAS1_BASE_ADDRS \ - { \ - GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, \ - GPIO5_ALIAS1_BASE \ - } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS \ - { \ - GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 \ - } -#define GPIO_ALIAS1_BASE_PTRS \ - { \ - GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 \ - } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn} @@ -32333,7 +32259,7 @@ typedef struct { #define HPDAC_GCR_FIFOEN_MASK (0x8U) #define HPDAC_GCR_FIFOEN_SHIFT (3U) /*! FIFOEN - FIFO Enable - * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to goes to buffer then goes to conversion. + * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. */ #define HPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_FIFOEN_SHIFT)) & HPDAC_GCR_FIFOEN_MASK) @@ -32675,7 +32601,7 @@ typedef struct { #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard feature set. + * 0b0000000000000000..Standard feature set */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) @@ -32695,7 +32621,7 @@ typedef struct { #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) -/*! DATALINE - Number of Datalinks */ +/*! DATALINE - Number of Data Lines */ #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) #define I2S_PARAM_FIFO_MASK (0xF00U) @@ -32715,96 +32641,102 @@ typedef struct { #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables the DMA warning. - * 0b1..Enables the DMA warning. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag - * 0b0..Transmit FIFO watermark has not been reached. - * 0b1..Transmit FIFO watermark has been reached. + * 0b0..Watermark not reached + * 0b1..Watermark reached */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag - * 0b0..No enabled transmit FIFO is empty. - * 0b1..Enabled transmit FIFO is empty. + * 0b0..Not empty + * 0b1..Empty */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag - * 0b0..Transmit underrun not detected. - * 0b1..Transmit underrun detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) @@ -32819,40 +32751,40 @@ typedef struct { #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. + * 0b0..No effect + * 0b1..FIFO reset */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable - * 0b0..Transmit bit clock is disabled. - * 0b1..Transmit bit clock is enabled. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable - * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. - * 0b1..Transmitter is enabled in Debug mode. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable - * 0b0..Transmitter disabled in Stop mode. - * 0b1..Transmitter enabled in Stop mode. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable - * 0b0..Transmitter is disabled. - * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ @@ -32863,10 +32795,10 @@ typedef struct { #define I2S_TCR1_TFW_MASK (0x7U) #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark - * 0b000..1 FIFO word - * 0b001..2 FIFO words - * 0b010-0b110..(TFW +1) FIFO words - * 0b111..8 FIFO words + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(TFW +1) + * 0b111..8 */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ @@ -32882,50 +32814,50 @@ typedef struct { #define I2S_TCR2_BYP_MASK (0x800000U) #define I2S_TCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass - * 0b0..Internal bit clock is generated from bit clock divider. - * 0b1..Internal bit clock is divide-by-one of the audio master clock. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity - * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + * 0b0..Active high + * 0b1..Active low */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) @@ -32965,48 +32897,48 @@ typedef struct { #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction - * 0b0..Frame sync is generated externally in Slave mode. - * 0b1..Frame sync is generated internally in Master mode. + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. + * 0b0..Active high + * 0b1..Active low */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is 0. +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First - * 0b0..LSB is transmitted first. - * 0b1..MSB is transmitted first. + * 0b0..LSB + * 0b1..MSB */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode - * 0b0..TDM mode, transmit data pins are 3-stated when slots are masked or channels are disabled. - * 0b1..Output mode, transmit data pins are never 3-stated and output zero when slots are masked or channels are disabled. + * 0b0..TDM mode + * 0b1..Output mode */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) @@ -33017,34 +32949,34 @@ typedef struct { #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) -/*! FRSZ - Frame size */ +/*! FRSZ - Frame Size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled. + * 0b00..Disable FIFO packing * 0b01..Reserved - * 0b10..8-bit FIFO packing is enabled. - * 0b11..16-bit FIFO packing is enabled. + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode - * 0b00..FIFO Combine mode disabled. - * 0b01..FIFO Combine mode enabled on FIFO reads (from transmit shift registers). - * 0b10..FIFO Combine mode enabled on FIFO writes (by software). - * 0b11..FIFO Combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, SAI continues from the start of the next frame after the FIFO error flag has been cleared. - * 0b1..On FIFO error, SAI continues from the same word that caused the FIFO error to become 1 after the FIFO warning flag returns to 0. + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ @@ -33055,29 +32987,29 @@ typedef struct { #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted - * 0b00000..Bit index is 0. - * 0b00001-0b11110..Bit index is FBT value. - * 0b11111..Bit index is 31. + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width - * 0b00111..8 bits per word - * 0b01000..9 bits per word - * 0b01001-0b11110..(W0W value + 1) bits per word - * 0b11111..32 bits per word + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width - * 0b00111..8 bits per word - * 0b01000..9 bits per word - * 0b01001-0b11110..(WNW value + 1) bits per word - * 0b11111..32 bits per word + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 */ #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ @@ -33087,7 +33019,7 @@ typedef struct { #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) -/*! TDR - Transmit Data Register */ +/*! TDR - Transmit Data */ #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ @@ -33111,7 +33043,7 @@ typedef struct { #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer * 0b0..No effect - * 0b1..FIFO Combine mode is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + * 0b1..Next FIFO to be written */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) /*! @} */ @@ -33125,8 +33057,8 @@ typedef struct { #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are 3-stated or drive zero when masked. + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ @@ -33137,144 +33069,150 @@ typedef struct { #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables DMA warnings. - * 0b1..Enables DMA warnings. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag - * 0b0..Receive FIFO watermark not reached. - * 0b1..Receive FIFO watermark has been reached. + * 0b0..Watermark not reached + * 0b1..Watermark reached */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag - * 0b0..No enabled receive FIFO is full. - * 0b1..Enabled receive FIFO is full. + * 0b0..Not full + * 0b1..Full */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag - * 0b0..Receive overflow not detected. - * 0b1..Receive overflow detected. + * 0b0..No error + * 0b1..Receive overflow detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset - * 0b0..No effect. - * 0b1..Software reset. + * 0b0..No effect + * 0b1..Software reset */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. + * 0b0..No effect + * 0b1..Reset */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable - * 0b0..Receive bit clock is disabled. - * 0b1..Receive bit clock is enabled. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable - * 0b0..Receiver is disabled in Debug mode, after completing the current frame. - * 0b1..Receiver is enabled in Debug mode. + * 0b0..Disable after completing the current frame + * 0b1..Enable */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable - * 0b0..Receiver disabled in Stop mode. - * 0b1..Receiver enabled in Stop mode. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable - * 0b0..Receiver is disabled. - * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ @@ -33285,10 +33223,10 @@ typedef struct { #define I2S_RCR1_RFW_MASK (0x7U) #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark - * 0b000..1 FIFO word - * 0b001..2 FIFO words - * 0b010-0b110..(RFW value + 1) FIFO words - * 0b111..8 FIFO words + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(RFW value + 1) + * 0b111..8 */ #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ @@ -33304,50 +33242,50 @@ typedef struct { #define I2S_RCR2_BYP_MASK (0x800000U) #define I2S_RCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass - * 0b0..Internal bit clock is generated from bit clock divider. - * 0b1..Internal bit clock is divide-by-one of the audio master clock. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity - * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + * 0b0..Active high + * 0b1..Active low */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) @@ -33392,88 +33330,88 @@ typedef struct { #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction - * 0b0..Frame Sync is generated externally in Slave mode. - * 0b1..Frame Sync is generated internally in Master mode. + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. + * 0b0..Active high + * 0b1..Active low */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is 0. +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First - * 0b0..LSB is received first. - * 0b1..MSB is received first. + * 0b0..LSB + * 0b1..MSB */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width - * 0b00000..1 bit-clock cycle - * 0b00001..2 bit-clock cycle - * 0b00010-0b11110..(SYWD value + 1) bit-clock cycle - * 0b11111..32 bit-clock cycle + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size - * 0b00000..1 word per frame - * 0b00001..2 words per frame - * 0b00010-0b11110..(FRSZ value + 1) words per frame - * 0b11111..32 words per frame + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled + * 0b00..Disable * 0b01..Reserved - * 0b10..8-bit FIFO packing is enabled - * 0b11..16-bit FIFO packing is enabled + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode - * 0b00..FIFO Combine mode disabled. - * 0b01..FIFO Combine mode enabled on FIFO writes (from receive shift registers). - * 0b10..FIFO Combine mode enabled on FIFO reads (by software). - * 0b11..FIFO Combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, SAI continues from the start of the next frame after the FIFO error flag returns to 0. - * 0b1..On FIFO error, SAI continues from the same word that caused the FIFO error to become 1 after the FIFO warning flag returns to 0. + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ @@ -33484,29 +33422,29 @@ typedef struct { #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted - * 0b00000..Bit index is 0. - * 0b00001-0b11110..Bit index is FBT value. - * 0b11111..Bit index is 31. + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width - * 0b00000..1 bit per word - * 0b00001..2 bits per word - * 0b00010-0b11110..(W0W value + 1) bits per word - * 0b11111..32 bits per word + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width - * 0b00111..8 bits per word - * 0b01000..9 bits per word - * 0b01001-0b11110..(WNW value + 1) bits per word - * 0b11111..32 bits per word + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 */ #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ @@ -33516,7 +33454,7 @@ typedef struct { #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) -/*! RDR - Receive Data Register */ +/*! RDR - Receive Data */ #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ @@ -33533,9 +33471,9 @@ typedef struct { #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) -/*! RCP - Receive Channel Pointer - * 0b0..No effect. - * 0b1..FIFO Combine mode is enabled for FIFO reads and this FIFO will be read on the next FIFO read. +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) @@ -33554,8 +33492,8 @@ typedef struct { #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @} */ @@ -33571,26 +33509,26 @@ typedef struct { #define I2S_MCR_DIVEN_MASK (0x800000U) #define I2S_MCR_DIVEN_SHIFT (23U) /*! DIVEN - MCLK Post Divide Enable - * 0b0..Output on MCLK signal pin is the audio master clock. - * 0b1..Output on MCLK signal pin is a post-divided version of audio master clock. + * 0b0..Disable + * 0b1..Enable */ #define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) #define I2S_MCR_MSEL_MASK (0x3000000U) #define I2S_MCR_MSEL_SHIFT (24U) /*! MSEL - MCLK Select - * 0b00..Master Clock (MCLK) 1 option selected. + * 0b00..Controller clock (MCLK) option 1 * 0b01..Reserved - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 */ #define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) /*! MOE - MCLK Output Enable - * 0b0..MCLK signal pin is an input. - * 0b1..MCLK signal pin is an output. + * 0b0..Input + * 0b1..Output */ #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) /*! @} */ @@ -33674,13 +33612,13 @@ typedef struct { __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ - __O uint32_t SWDATAH; /**< Target Write Data Half-word, offset: 0x38 */ - __O uint32_t SWDATAHE; /**< Target Write Data Half-word End, offset: 0x3C */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ uint8_t RESERVED_1[4]; __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ uint8_t RESERVED_2[8]; - __IO uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ uint8_t RESERVED_3[4]; __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ @@ -33709,7 +33647,7 @@ typedef struct { __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ uint8_t RESERVED_6[4]; __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ - __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1(to bus), offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ union { /* offset: 0xD0 */ __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ @@ -33717,7 +33655,7 @@ typedef struct { __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ union { /* offset: 0xD8 */ __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ - __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ }; __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ @@ -33757,15 +33695,15 @@ typedef struct { #define I3C_MCONFIG_DISTO_MASK (0x8U) #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout - * 0b1..Timeout disabled, if timeout is configured - * 0b0..Timeout enabled + * 0b1..Disabled, if configured + * 0b0..Enabled */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) #define I3C_MCONFIG_HKEEP_MASK (0x30U) #define I3C_MCONFIG_HKEEP_SHIFT (4U) /*! HKEEP - High-Keeper - * 0b00..NONE + * 0b00..None * 0b01..WIRED_IN * 0b10..PASSIVE_SDA * 0b11..PASSIVE_ON_SDA_SCL @@ -33775,9 +33713,8 @@ typedef struct { #define I3C_MCONFIG_ODSTOP_MASK (0x40U) #define I3C_MCONFIG_ODSTOP_SHIFT (6U) /*! ODSTOP - Open Drain Stop - * 0b1..Enable open-drain stop. STOP is emitted at open-drain speeds even for I3C messages. In legacy devices, - * this feature can ensure that the legacy devices see the STOP. - * 0b0..Disable open-drain stop. ODSTOP must be disabled when sending an HDR exit pattern. + * 0b1..Enable + * 0b0..Disable */ #define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) @@ -33799,10 +33736,8 @@ typedef struct { #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) #define I3C_MCONFIG_ODHPP_SHIFT (24U) /*! ODHPP - Open Drain High Push-Pull - * 0b1..ODHPP enabled. Open-Drain High SCL half-lock period is one PPBAUD count for I3C messages. This setting is - * faster (and works for I3C devices). Any legacy I2C devices on the bus will not see the SCL High at all - * (less than the spike filter period). - * 0b0..ODHPP disabled. Open-Drain SCL High half-clock period is the same as the Open-Drain Low SCL half-period. + * 0b1..Enable + * 0b0..Disable */ #define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) @@ -33823,59 +33758,55 @@ typedef struct { #define I3C_SCONFIG_SLVENA_MASK (0x1U) #define I3C_SCONFIG_SLVENA_SHIFT (0U) /*! SLVENA - Target Enable - * 0b1..Target can operate on the I2C or I3C bus - * 0b0..Target ignores the I2C or I3C bus + * 0b1..Enable + * 0b0..Disable */ #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) #define I3C_SCONFIG_NACK_MASK (0x2U) #define I3C_SCONFIG_NACK_SHIFT (1U) /*! NACK - Not Acknowledge - * 0b1..Always NACK enable. The target rejects all requests to it, except for a Common Command Code (CCC) - * broadcast. NACK = 1 should be used with caution, because the controller may decide that the target is missing, if - * NACK is overused. - * 0b0..Always NACK disable + * 0b1..Always enable NACK mode (works normally) + * 0b0..Always disable NACK mode */ #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) #define I3C_SCONFIG_MATCHSS_MASK (0x4U) #define I3C_SCONFIG_MATCHSS_SHIFT (2U) -/*! MATCHSS - Match START or STOP - * 0b1..Match START or STOP enable. START and STOP sticky SSTATUS bits only become 1 when SSTATUS[MATCHED] is 1. - * This setting allows START and STOP to be used to detect the end of a message to/from this target. - * 0b0..Match START or STOP disable +/*! MATCHSS - Match Start or Stop + * 0b1..Enable + * 0b0..Disable */ #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) #define I3C_SCONFIG_S0IGNORE_MASK (0x8U) #define I3C_SCONFIG_S0IGNORE_SHIFT (3U) -/*! S0IGNORE - Ignore TE0/TE1 Errors - * 0b1..Ignore TE0/TE1 errors. Target does not detect TE0 or TE1 errors, so it does not lock up waiting on an - * Exit Pattern. This setting should only be used when the bus does not use HDR mode. - * 0b0..Do not ignore TE0/TE1 errors +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b1..Ignore TE0 or TE1 errors + * 0b0..Do not ignore TE0 or TE1 errors */ #define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) #define I3C_SCONFIG_DDROK_MASK (0x10U) #define I3C_SCONFIG_DDROK_SHIFT (4U) /*! DDROK - Double Data Rate OK - * 0b1..Allow HDR-DDR messaging. - * 0b0..Do not allow HDR-DDR messaging. + * 0b1..Allow HDR-DDR messaging + * 0b0..Do not allow HDR-DDR messaging */ #define I3C_SCONFIG_DDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK) #define I3C_SCONFIG_IDRAND_MASK (0x100U) #define I3C_SCONFIG_IDRAND_SHIFT (8U) /*! IDRAND - ID random - * 0b1..SIDPARTNO[PARTNO] is a random value. - * 0b0..SIDPARTNO[PARTNO] is a part number and an instance. + * 0b1..Random value + * 0b0..Part number and an instance */ #define I3C_SCONFIG_IDRAND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK) #define I3C_SCONFIG_OFFLINE_MASK (0x200U) #define I3C_SCONFIG_OFFLINE_SHIFT (9U) /*! OFFLINE - Offline - * 0b1..Enables wait to ensure the bus is not in HDR mode. + * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) @@ -33896,57 +33827,56 @@ typedef struct { #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) -/*! STNOTSTOP - Status Not Stop - * 0b1..The bus is busy (has activity). - * 0b0..I3C module is in a STOP condition. +/*! STNOTSTOP - Status not Stop + * 0b1..Busy + * 0b0..In STOP condition */ #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) #define I3C_SSTATUS_STMSG_MASK (0x2U) #define I3C_SSTATUS_STMSG_SHIFT (1U) -/*! STMSG - Status message - * 0b1..This bus target is listening to the bus traffic or responding. - * 0b0..Bus target not listening or responding. +/*! STMSG - Status Message + * 0b1..Busy + * 0b0..Idle */ #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) #define I3C_SSTATUS_STCCCH_MASK (0x4U) #define I3C_SSTATUS_STCCCH_SHIFT (2U) /*! STCCCH - Status Common Command Code Handler - * 0b1..A CCC message is being handled automatically. - * 0b0..No CCC message is being handled. + * 0b1..Handled automatically + * 0b0..No CCC message handled */ #define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) #define I3C_SSTATUS_STREQRD_MASK (0x8U) #define I3C_SSTATUS_STREQRD_SHIFT (3U) /*! STREQRD - Status Request Read - * 0b1..The REQ in process is an SDR read from this target, or an In-Band Interrupt (IBI) is being pushed out. - * 0b0..REQ in process is not an SDR read from this target. + * 0b1..SDR read from this target or an IBI is being pushed out + * 0b0..Not an SDR read */ #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) #define I3C_SSTATUS_STREQWR_MASK (0x10U) #define I3C_SSTATUS_STREQWR_SHIFT (4U) /*! STREQWR - Status Request Write - * 0b1..REQ in process is SDR write data from the controller to this bus target (or all I3C targets), but not in ENTDAA mode. - * 0b0..REQ in process is not SDR write data from the controller. + * 0b1..SDR write data from the controller, but not in ENTDAA mode + * 0b0..Not an SDR write */ #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) #define I3C_SSTATUS_STDAA_MASK (0x20U) #define I3C_SSTATUS_STDAA_SHIFT (5U) /*! STDAA - Status Dynamic Address Assignment - * 0b1..I3C bus is in Enter Dynamic Address Assignment (ENTDAA) mode, regardless of whether this bus target has a Dynamic Address or not. - * 0b0..Not in ENTDAA mode. + * 0b1..In ENTDAA mode + * 0b0..Not in ENTDAA mode */ #define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) #define I3C_SSTATUS_STHDR_MASK (0x40U) #define I3C_SSTATUS_STHDR_SHIFT (6U) /*! STHDR - Status High Data Rate - * 0b1..The I3C bus is in HDR-DDR mode , regardless of whether HDR mode is supported by this module or not, and - * regardless of whether the message is to this module or to some other module. + * 0b1..I3C bus in HDR-DDR mode * 0b0..I3C bus not in HDR-DDR mode */ #define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) @@ -33954,38 +33884,44 @@ typedef struct { #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) /*! START - Start - * 0b1..A START or repeated START was seen after the START bit was last cleared. - * 0b0..No START seen. + * 0b1..Detected + * 0b0..Not detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) #define I3C_SSTATUS_MATCHED_MASK (0x200U) #define I3C_SSTATUS_MATCHED_SHIFT (9U) /*! MATCHED - Matched - * 0b1..An incoming header matched the I3C Dynamic or I2C Static address of this device (if any) since the bus was last cleared. - * 0b0..No header matched. + * 0b1..Header matched + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) #define I3C_SSTATUS_STOP_MASK (0x400U) #define I3C_SSTATUS_STOP_SHIFT (10U) /*! STOP - Stop - * 0b1..Stopped state detected. A STOP state was present on the bus since the bus was last cleared. - * 0b0..No STOP detected. + * 0b1..Stopped state detected + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) #define I3C_SSTATUS_RX_PEND_MASK (0x800U) #define I3C_SSTATUS_RX_PEND_SHIFT (11U) /*! RX_PEND - Received Message Pending - * 0b1..Received message is pending. - * 0b0..No received message is pending. + * 0b1..Received message pending + * 0b0..No received message pending */ #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - Transmit Buffer Is Not Full +/*! TXNOTFULL - Transmit Buffer Not Full * 0b1..Transmit buffer not full * 0b0..Transmit buffer full */ @@ -33994,16 +33930,20 @@ typedef struct { #define I3C_SSTATUS_DACHG_MASK (0x2000U) #define I3C_SSTATUS_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change - * 0b1..DA change detected. The target DA has been assigned, re-assigned, or reset (lost) and is now in the state of being valid or none. - * 0b0..No DA change detected. + * 0b1..DA change detected + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) #define I3C_SSTATUS_CCC_MASK (0x4000U) #define I3C_SSTATUS_CCC_SHIFT (14U) /*! CCC - Common Command Code - * 0b1..CCC received. - * 0b0..No CCC received. + * 0b1..CCC received + * 0b0..CCC not received + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) @@ -34015,78 +33955,84 @@ typedef struct { #define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) #define I3C_SSTATUS_HDRMATCH_SHIFT (16U) /*! HDRMATCH - High Data Rate Command Match - * 0b1..HDR command matched the I3C Dynamic Address of this device. - * 0b0..HDR command did not match. + * 0b1..Matched the I3C dynamic address + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) #define I3C_SSTATUS_CHANDLED_MASK (0x20000U) #define I3C_SSTATUS_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code Handled - * 0b1..CCC handling in progress. - * 0b0..CCC handling not in progress. + * 0b1..CCC handling in progress + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) #define I3C_SSTATUS_EVENT_MASK (0x40000U) #define I3C_SSTATUS_EVENT_SHIFT (18U) /*! EVENT - Event - * 0b1..An IBI, CR, or HJ has occurred. - * 0b0..No event has occurred. + * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) #define I3C_SSTATUS_EVDET_MASK (0x300000U) #define I3C_SSTATUS_EVDET_SHIFT (20U) /*! EVDET - Event Details - * 0b00..NONE - * 0b01..NO_REQUEST - * 0b10..NACKED - * 0b11..ACKED + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) */ #define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) #define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) #define I3C_SSTATUS_IBIDIS_SHIFT (24U) -/*! IBIDIS - In-Band Interrupts Are Disabled - * 0b1..In-Band Interrupts disabled - * 0b0..In-Band Interrupts not disabled +/*! IBIDIS - In-Band Interrupts Disable + * 0b1..Disabled + * 0b0..Enabled */ #define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) #define I3C_SSTATUS_MRDIS_MASK (0x2000000U) #define I3C_SSTATUS_MRDIS_SHIFT (25U) -/*! MRDIS - Controller Requests Are Disabled - * 0b1..Controller Requests disabled - * 0b0..Controller Requests not disabled +/*! MRDIS - Controller Requests Disable + * 0b1..Disabled + * 0b0..Enabled */ #define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) #define I3C_SSTATUS_HJDIS_MASK (0x8000000U) #define I3C_SSTATUS_HJDIS_SHIFT (27U) /*! HJDIS - Hot-Join Disabled - * 0b1..Hot-Join disabled - * 0b0..Hot-Join not disabled + * 0b1..Disabled + * 0b0..Enabled */ #define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) #define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) #define I3C_SSTATUS_ACTSTATE_SHIFT (28U) /*! ACTSTATE - Activity State from Common Command Codes (CCC) - * 0b00..NO_LATENCY - * 0b01..LATENCY_1MS - * 0b10..LATENCY_100MS - * 0b11..LATENCY_10S + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) */ #define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) #define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) #define I3C_SSTATUS_TIMECTRL_SHIFT (30U) /*! TIMECTRL - Time Control - * 0b00..NO_TIME_CONTROL - * 0b01..SYNC_MODE - * 0b10..ASYNC_MODE - * 0b11..BOTHSYNCASYNC + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) */ #define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) /*! @} */ @@ -34107,8 +34053,8 @@ typedef struct { #define I3C_SCTRL_EXTDATA_MASK (0x8U) #define I3C_SCTRL_EXTDATA_SHIFT (3U) /*! EXTDATA - Extended Data - * 0b1..Extended data enabled. After IBIDATA is emitted, extended data is taken from IBIEXT1 and IBIEXT2 if configured. - * 0b0..Extended data disabled. + * 0b1..Enable + * 0b0..Disable */ #define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) @@ -34139,88 +34085,88 @@ typedef struct { #define I3C_SINTSET_START_MASK (0x100U) #define I3C_SINTSET_START_SHIFT (8U) /*! START - Start Interrupt Enable - * 0b1..Enable START interrupt - * 0b0..Disable START interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) #define I3C_SINTSET_MATCHED_MASK (0x200U) #define I3C_SINTSET_MATCHED_SHIFT (9U) -/*! MATCHED - Match interrupt enable - * 0b1..Enable match interrupt - * 0b0..Disable match interrupt +/*! MATCHED - Match Interrupt Enable + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) #define I3C_SINTSET_STOP_MASK (0x400U) #define I3C_SINTSET_STOP_SHIFT (10U) /*! STOP - Stop Interrupt Enable - * 0b1..Enable STOP interrupt - * 0b0..Disable STOP interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) #define I3C_SINTSET_RXPEND_MASK (0x800U) #define I3C_SINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Interrupt Enable - * 0b1..Enable Receive interrupt - * 0b0..Disable Receive interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) #define I3C_SINTSET_TXSEND_MASK (0x1000U) #define I3C_SINTSET_TXSEND_SHIFT (12U) /*! TXSEND - Transmit Interrupt Enable - * 0b1..Enable Transmit interrupt - * 0b0..Disable Transmit interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) #define I3C_SINTSET_DACHG_MASK (0x2000U) #define I3C_SINTSET_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change Interrupt Enable - * 0b1..Enable DA Change interrupt - * 0b0..Disable DA Change interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) #define I3C_SINTSET_CCC_MASK (0x4000U) #define I3C_SINTSET_CCC_SHIFT (14U) -/*! CCC - CCC (that was not handled by I3C module) Interrupt Enable - * 0b1..Enable CCC interrupt - * 0b0..Disable CCC interrupt +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) #define I3C_SINTSET_ERRWARN_MASK (0x8000U) #define I3C_SINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning Interrupt Enable - * 0b1..Enable error or warning interrupt - * 0b0..Disable error or warning interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) #define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) #define I3C_SINTSET_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - Double Data Rate Interrupt Enable - * 0b1..Enable DDR interrupt - * 0b0..Disable DDR interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) #define I3C_SINTSET_CHANDLED_MASK (0x20000U) #define I3C_SINTSET_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code (CCC) Interrupt Enable - * 0b1..Enable CCC Handled interrupt - * 0b0..Disable CCC Handled interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) #define I3C_SINTSET_EVENT_MASK (0x40000U) #define I3C_SINTSET_EVENT_SHIFT (18U) /*! EVENT - Event Interrupt Enable - * 0b1..Enable Event interrupt - * 0b0..Disable Event interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) /*! @} */ @@ -34235,7 +34181,7 @@ typedef struct { #define I3C_SINTCLR_MATCHED_MASK (0x200U) #define I3C_SINTCLR_MATCHED_SHIFT (9U) -/*! MATCHED - MATCHED Interrupt Enable Clear */ +/*! MATCHED - Matched Interrupt Enable Clear */ #define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) #define I3C_SINTCLR_STOP_MASK (0x400U) @@ -34289,7 +34235,7 @@ typedef struct { #define I3C_SINTMASKED_START_MASK (0x100U) #define I3C_SINTMASKED_START_SHIFT (8U) -/*! START - START interrupt mask */ +/*! START - START Interrupt Mask */ #define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) #define I3C_SINTMASKED_MATCHED_MASK (0x200U) @@ -34351,6 +34297,8 @@ typedef struct { /*! ORUN - Overrun Error * 0b1..Overrun error * 0b0..No overrun error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) @@ -34359,14 +34307,18 @@ typedef struct { /*! URUN - Underrun Error * 0b1..Underrun error * 0b0..No underrun error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) -/*! URUNNACK - Underrun and Not Acknowledged (NACKED) Error - * 0b1..Underrun and not acknowledged error - * 0b0..No underrun and not acknowledged error +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error + * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) @@ -34375,6 +34327,8 @@ typedef struct { /*! TERM - Terminated Error * 0b1..Terminated error * 0b0..No terminated error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) @@ -34383,54 +34337,68 @@ typedef struct { /*! INVSTART - Invalid Start Error * 0b1..Invalid start error * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) #define I3C_SERRWARN_SPAR_MASK (0x100U) #define I3C_SERRWARN_SPAR_SHIFT (8U) /*! SPAR - SDR Parity Error - * 0b1..SDR Parity error - * 0b0..No SDR Parity error + * 0b1..SDR parity error + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) #define I3C_SERRWARN_HPAR_MASK (0x200U) #define I3C_SERRWARN_HPAR_SHIFT (9U) /*! HPAR - HDR Parity Error - * 0b1..HDR Parity error - * 0b0..No HDR Parity error + * 0b1..HDR parity error + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) #define I3C_SERRWARN_HCRC_MASK (0x400U) #define I3C_SERRWARN_HCRC_SHIFT (10U) /*! HCRC - HDR-DDR CRC Error - * 0b1..HDR-DDR CRC error - * 0b0..No HDR-DDR CRC error + * 0b1..HDR-DDR CRC error occurred + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) #define I3C_SERRWARN_S0S1_MASK (0x800U) #define I3C_SERRWARN_S0S1_SHIFT (11U) /*! S0S1 - TE0 or TE1 Error - * 0b1..TE0 or TE1 error - * 0b0..No TE0 or TE1 error + * 0b1..TE0 or TE1 error occurred + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) -/*! OREAD - Over-read Error +/*! OREAD - Over-Read Error * 0b1..Over-read error - * 0b0..No Over-read error + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) -/*! OWRITE - Over-write Error +/*! OWRITE - Over-Write Error * 0b1..Overwrite error - * 0b0..No Overwrite error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ @@ -34440,9 +34408,9 @@ typedef struct { #define I3C_SDMACTRL_DMAFB_MASK (0x3U) #define I3C_SDMACTRL_DMAFB_SHIFT (0U) -/*! DMAFB - DMA Read (From-bus) Trigger +/*! DMAFB - DMA Read (From-Bus) Trigger * 0b00..DMA not used - * 0b01..DMA is enabled for one frame + * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ @@ -34450,9 +34418,9 @@ typedef struct { #define I3C_SDMACTRL_DMATB_MASK (0xCU) #define I3C_SDMACTRL_DMATB_SHIFT (2U) -/*! DMATB - DMA Write (To-bus) Trigger +/*! DMATB - DMA Write (To-Bus) Trigger * 0b00..DMA not used - * 0b01..DMA enabled for one frame (ended by DMA or terminated) + * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ @@ -34462,7 +34430,7 @@ typedef struct { #define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) /*! DMAWIDTH - Width of DMA Operations * 0b00, 0b01..Byte - * 0b10..Half word (16 bits) + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) * 0b11.. */ #define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) @@ -34473,19 +34441,19 @@ typedef struct { #define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) -/*! FLUSHTB - Flush the To-bus Buffer or FIFO */ +/*! FLUSHTB - Flush To-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) #define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) -/*! FLUSHFB - Flush the From-bus Buffer or FIFO */ +/*! FLUSHFB - Flush From-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) #define I3C_SDATACTRL_UNLOCK_MASK (0x8U) #define I3C_SDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock - * 0b0..RXTRIG and TXTRIG fields cannot be changed on a write. - * 0b1..RXTRIG and TXTRIG fields can be changed on a write. + * 0b0..Cannot be changed + * 0b1..Can be changed */ #define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) @@ -34495,7 +34463,7 @@ typedef struct { * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less - * 0b11..Default. Trigger when 1 less than full or less + * 0b11..Default (trigger when 1 less than full or less) */ #define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) @@ -34521,7 +34489,7 @@ typedef struct { #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_SDATACTRL_TXFULL_SHIFT (30U) -/*! TXFULL - Transmit Is Full +/*! TXFULL - Transmit is Full * 0b1..Full * 0b0..Not full */ @@ -34529,7 +34497,7 @@ typedef struct { #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) -/*! RXEMPTY - Receive Is Empty +/*! RXEMPTY - Receive is Empty * 0b1..Empty * 0b0..Not empty */ @@ -34547,16 +34515,16 @@ typedef struct { #define I3C_SWDATAB_END_MASK (0x100U) #define I3C_SWDATAB_END_SHIFT (8U) /*! END - End - * 0b1..End. This bit marks the last byte of the message. - * 0b0..Not the end. There are more bytes in the message. + * 0b1..End + * 0b0..Not the end */ #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) #define I3C_SWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End Also - * 0b1..End. This bit marks the last byte of the message. - * 0b0..Not the end. There are more bytes in the message. + * 0b1..End + * 0b0..Not the end */ #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) /*! @} */ @@ -34570,7 +34538,7 @@ typedef struct { #define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) /*! @} */ -/*! @name SWDATAH - Target Write Data Half-word */ +/*! @name SWDATAH - Target Write Data Halfword */ /*! @{ */ #define I3C_SWDATAH_DATA0_MASK (0xFFU) @@ -34585,14 +34553,14 @@ typedef struct { #define I3C_SWDATAH_END_MASK (0x10000U) #define I3C_SWDATAH_END_SHIFT (16U) -/*! END - End of message - * 0b1..End. This bit marks the last byte of the message. - * 0b0..Not the end. There are more bytes in the message. +/*! END - End of Message + * 0b1..End + * 0b0..Not the end */ #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) /*! @} */ -/*! @name SWDATAHE - Target Write Data Half-word End */ +/*! @name SWDATAHE - Target Write Data Halfword End */ /*! @{ */ #define I3C_SWDATAHE_DATA0_MASK (0xFFU) @@ -34620,12 +34588,12 @@ typedef struct { #define I3C_SRDATAH_LSB_MASK (0xFFU) #define I3C_SRDATAH_LSB_SHIFT (0U) -/*! LSB - The first byte read from the target */ +/*! LSB - Low Byte */ #define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) #define I3C_SRDATAH_MSB_MASK (0xFF00U) #define I3C_SRDATAH_MSB_SHIFT (8U) -/*! MSB - The second byte read from the target */ +/*! MSB - High Byte */ #define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) /*! @} */ @@ -34636,11 +34604,6 @@ typedef struct { #define I3C_SWDATAB1_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) - -#define I3C_SWDATAB1_IGNORED_MASK (0xFFFFFF00U) -#define I3C_SWDATAB1_IGNORED_SHIFT (8U) -/*! IGNORED - Ignored field */ -#define I3C_SWDATAB1_IGNORED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_IGNORED_SHIFT)) & I3C_SWDATAB1_IGNORED_MASK) /*! @} */ /*! @name SCAPABILITIES2 - Target Capabilities 2 */ @@ -34654,66 +34617,66 @@ typedef struct { #define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) #define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) /*! I2C10B - I2C 10-bit Address - * 0b0..Does not support 10-bit I2C address - * 0b1..Supports 10-bit I2C address + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) #define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) #define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) /*! I2CRST - I2C Software Reset - * 0b0..Does not support I2C software reset - * 0b1..Supports I2C software reset + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) #define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) /*! I2CDEVID - I2C Device ID - * 0b0..Does not support I2C device ID - * 0b1..Supports I2C device ID + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) #define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) #define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) /*! IBIEXT - In-Band Interrupt EXTDATA - * 0b0..Does not support IBIEXT - * 0b1..Supports IBIEXT + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) #define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) #define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) /*! IBIXREG - In-Band Interrupt Extended Register - * 0b0..Does not support extended registers for IBIs - * 0b1..Supports extended registers for IBIs + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) #define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) #define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) /*! SLVRST - Target Reset - * 0b0..Does not support Target Reset - * 0b1..Supports Target Reset + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) #define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) #define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) /*! GROUP - Group - * 0b00..Does not supports v1.1 Group addressing - * 0b01..Supports one group - * 0b10..Supports two groups - * 0b11..Supports three groups + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported */ #define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) #define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) #define I3C_SCAPABILITIES2_AASA_SHIFT (21U) -/*! AASA - Supports SETAASA - * 0b1..Supports SETAASA - * 0b0..Does not support SETAASA +/*! AASA - SETAASA + * 0b1..SETAASA supported + * 0b0..SETAASA not supported */ #define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) @@ -34750,11 +34713,11 @@ typedef struct { #define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) #define I3C_SCAPABILITIES_IDREG_SHIFT (2U) /*! IDREG - ID Register - * 0b0000..All ID register features below are disabled. - * 0bxxx1..ID Instance is a register, and is used if there is no PARTNO register. - * 0bxx1x..An ID Random field is available. - * 0bx1xx..A Device Characteristic Register (DCR) is available. - * 0b1xxx..A Bus Characteristics Register (BCR) is available. + * 0b0000..All ID register features disabled + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + * 0bxx1x..An ID Random field is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0b1xxx..A Bus Characteristics Register (BCR) is available */ #define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) @@ -34762,7 +34725,7 @@ typedef struct { #define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) /*! HDRSUPP - High Data Rate Support * 0b00..No HDR modes supported - * 0b01..Double Data Rate mode supported + * 0b01..DDR mode supported * *.. */ #define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) @@ -34788,30 +34751,30 @@ typedef struct { #define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) /*! CCCHANDLE - Common Command Codes Handling - * 0b0000..All handling features below are disabled. - * 0bxxx1..The block (I3C module) manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items. - * 0bxx1x..The block manages maximum read and write lengths, and max data speed. - * 0bx1xx..GETSTATUS CCC returns SCTRL[PENDINT] and SCTRL[ACTSTATE] values. - * 0b1xxx..GETSTATUS CCC returns SCTRL[VENDINFO] value. + * 0b0000..All handling features disabled + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] */ #define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) #define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events - * 0b00000..Application cannot generate IBI, CR, or HJ. - * 0bxxxx1..Application can generate an IBI. - * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register. - * 0bxx1xx..Application can generate a Controller Request for a secondary controller. - * 0bx1xxx..Application can generate a Hot-Join event. - * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing. + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0bxxxx1..Application can generate an IBI + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bx1xxx..Application can generate a Hot-Join event + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing */ #define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) #define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) #define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) /*! TIMECTRL - Time Control - * 0b0..No time control enabled + * 0b0..No time control supported * 0b1..At least one time-control type supported */ #define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) @@ -34819,7 +34782,7 @@ typedef struct { #define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) #define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) /*! EXTFIFO - External FIFO - * 0b000..No external FIFO is available + * 0b000..No external FIFO available * 0b001..Standard available or free external FIFO * 0b010..Request track external FIFO * *.. @@ -34869,8 +34832,8 @@ typedef struct { #define I3C_SDYNADDR_DAVALID_MASK (0x1U) #define I3C_SDYNADDR_DAVALID_SHIFT (0U) /*! DAVALID - Dynamic Address Valid - * 0b0..DANOTASSIGNED: a Dynamic Address is not assigned - * 0b1..DAASSIGNED: a Dynamic Address is assigned + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned */ #define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) @@ -34886,7 +34849,7 @@ typedef struct { #define I3C_SDYNADDR_SA10B_MASK (0xE000U) #define I3C_SDYNADDR_SA10B_SHIFT (13U) -/*! SA10B - 10bit Static Address */ +/*! SA10B - 10-Bit Static Address */ #define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) #define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) @@ -34914,7 +34877,7 @@ typedef struct { #define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) #define I3C_SIDPARTNO_PARTNO_SHIFT (0U) -/*! PARTNO - Part number */ +/*! PARTNO - Part Number */ #define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) /*! @} */ @@ -35043,9 +35006,9 @@ typedef struct { #define I3C_MSTATUS_STATE_MASK (0x7U) #define I3C_MSTATUS_STATE_SHIFT (0U) -/*! STATE - State Of The Controller - * 0b000..IDLE - * 0b001..SLVREQ +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) * 0b010..MSGSDR * 0b011..NORMACT * 0b100..MSGDDR @@ -35058,7 +35021,7 @@ typedef struct { #define I3C_MSTATUS_BETWEEN_MASK (0x10U) #define I3C_MSTATUS_BETWEEN_SHIFT (4U) /*! BETWEEN - Between - * 0b0..Inactive + * 0b0..Inactive (for other cases) * 0b1..Active */ #define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) @@ -35074,10 +35037,10 @@ typedef struct { #define I3C_MSTATUS_IBITYPE_MASK (0xC0U) #define I3C_MSTATUS_IBITYPE_SHIFT (6U) /*! IBITYPE - In-Band Interrupt (IBI) Type - * 0b00..NONE - * 0b01..In-Band Interrupt - * 0b10..Controller Request - * 0b11..Hot-Join + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ */ #define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) @@ -35086,6 +35049,8 @@ typedef struct { /*! SLVSTART - Target Start * 0b1..Target requesting START * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) @@ -35094,6 +35059,8 @@ typedef struct { /*! MCTRLDONE - Controller Control Done * 0b1..Done * 0b0..Not done + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) @@ -35102,6 +35069,8 @@ typedef struct { /*! COMPLETE - Complete * 0b1..Complete * 0b0..Not complete + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) @@ -35126,12 +35095,14 @@ typedef struct { /*! IBIWON - In-Band Interrupt (IBI) Won * 0b1..IBI arbitration won * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) #define I3C_MSTATUS_ERRWARN_SHIFT (15U) -/*! ERRWARN - Error Or Warning +/*! ERRWARN - Error or Warning * 0b1..Error or warning * 0b0..No error or warning */ @@ -35139,9 +35110,11 @@ typedef struct { #define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) #define I3C_MSTATUS_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - Module Is Now Controller - * 0b1..Module has become controller - * 0b0..Module has not become controller +/*! NOWMASTER - Module is now Controller + * 0b1..Controller + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) @@ -35181,9 +35154,9 @@ typedef struct { #define I3C_MIBIRULES_MSB0_MASK (0x40000000U) #define I3C_MIBIRULES_MSB0_SHIFT (30U) -/*! MSB0 - Most Significant Address Bit Is 0 - * 0b1..For all I3C dynamic addresses, MSB is 0. - * 0b0..MSB is not 0. +/*! MSB0 - Most Significant Address Bit is 0 + * 0b1..MSB is 0 + * 0b0..MSB is not 0 */ #define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) @@ -35225,12 +35198,12 @@ typedef struct { #define I3C_MINTSET_RXPEND_MASK (0x800U) #define I3C_MINTSET_RXPEND_SHIFT (11U) -/*! RXPEND - Rx Pending Interrupt Enable */ +/*! RXPEND - Receive Pending Interrupt Enable */ #define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable * 0b1..Enable * 0b0..Disable */ @@ -35238,7 +35211,7 @@ typedef struct { #define I3C_MINTSET_IBIWON_MASK (0x2000U) #define I3C_MINTSET_IBIWON_SHIFT (13U) -/*! IBIWON - In-Band Interrupt (IBI) Won Interrupt Enable +/*! IBIWON - IBI Won Interrupt Enable * 0b1..Enable * 0b0..Disable */ @@ -35254,7 +35227,7 @@ typedef struct { #define I3C_MINTSET_NOWMASTER_MASK (0x80000U) #define I3C_MINTSET_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - Now Controller (now this I3C module is a controller) Interrupt Enable +/*! NOWMASTER - Now Controller Interrupt Enable * 0b1..Enable * 0b0..Disable */ @@ -35267,64 +35240,80 @@ typedef struct { #define I3C_MINTCLR_SLVSTART_MASK (0x100U) #define I3C_MINTCLR_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) #define I3C_MINTCLR_COMPLETE_MASK (0x400U) #define I3C_MINTCLR_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) #define I3C_MINTCLR_RXPEND_MASK (0x800U) #define I3C_MINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) #define I3C_MINTCLR_IBIWON_MASK (0x2000U) #define I3C_MINTCLR_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) #define I3C_MINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) #define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) #define I3C_MINTCLR_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) /*! @} */ @@ -35335,24 +35324,24 @@ typedef struct { #define I3C_MINTMASKED_SLVSTART_MASK (0x100U) #define I3C_MINTMASKED_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) @@ -35364,32 +35353,32 @@ typedef struct { #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) #define I3C_MINTMASKED_IBIWON_MASK (0x2000U) #define I3C_MINTMASKED_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) #define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) #define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) /*! @} */ @@ -35397,19 +35386,13 @@ typedef struct { /*! @name MERRWARN - Controller Errors and Warnings */ /*! @{ */ -#define I3C_MERRWARN_URUN_MASK (0x2U) -#define I3C_MERRWARN_URUN_SHIFT (1U) -/*! URUN - Underrun error - * 0b1..Error - * 0b0..No error - */ -#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) - #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) /*! NACK - Not Acknowledge Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) @@ -35418,22 +35401,18 @@ typedef struct { /*! WRABT - Write Abort Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) -#define I3C_MERRWARN_TERM_MASK (0x10U) -#define I3C_MERRWARN_TERM_SHIFT (4U) -/*! TERM - Terminate Error - * 0b1..Error - * 0b0..No error - */ -#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) - #define I3C_MERRWARN_HPAR_MASK (0x200U) #define I3C_MERRWARN_HPAR_SHIFT (9U) /*! HPAR - High Data Rate Parity * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) @@ -35442,22 +35421,28 @@ typedef struct { /*! HCRC - High Data Rate CRC Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) -/*! OREAD - Over-read Error +/*! OREAD - Overread Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) -/*! OWRITE - Over-write Error +/*! OWRITE - Overwrite Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) @@ -35466,6 +35451,8 @@ typedef struct { /*! MSGERR - Message Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) @@ -35474,6 +35461,8 @@ typedef struct { /*! INVREQ - Invalid Request Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) @@ -35482,6 +35471,8 @@ typedef struct { /*! TIMEOUT - Timeout Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ @@ -35491,8 +35482,8 @@ typedef struct { #define I3C_MDMACTRL_DMAFB_MASK (0x3U) #define I3C_MDMACTRL_DMAFB_SHIFT (0U) -/*! DMAFB - DMA From Bus - * 0b00..DMA is not used +/*! DMAFB - DMA from Bus + * 0b00..DMA not used * 0b01..Enable DMA for one frame * 0b10..Enable DMA until DMA is turned off * 0b11.. @@ -35501,9 +35492,9 @@ typedef struct { #define I3C_MDMACTRL_DMATB_MASK (0xCU) #define I3C_MDMACTRL_DMATB_SHIFT (2U) -/*! DMATB - DMA To Bus - * 0b00..DMA is not used - * 0b01..Enable DMA for one frame (ended by DMA or Terminated) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) * 0b10..Enable DMA until DMA is turned off * 0b11.. */ @@ -35524,7 +35515,7 @@ typedef struct { #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) -/*! FLUSHTB - Flush To-bus Buffer or FIFO +/*! FLUSHTB - Flush To-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ @@ -35532,7 +35523,7 @@ typedef struct { #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) -/*! FLUSHFB - Flush From-bus Buffer or FIFO +/*! FLUSHFB - Flush From-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ @@ -35541,8 +35532,8 @@ typedef struct { #define I3C_MDATACTRL_UNLOCK_MASK (0x8U) #define I3C_MDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock - * 0b0..Locked. RXTRIG and TXTRIG fields cannot be changed on a write. - * 0b1..Unlocked. RXTRIG and TXTRIG fields can be changed on a write. + * 0b0..Locked + * 0b1..Unlocked */ #define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) @@ -35552,7 +35543,7 @@ typedef struct { * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less - * 0b11..Default. Trigger when 1 less than full or less + * 0b11..Trigger when 1 less than full or less (default) */ #define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) @@ -35578,17 +35569,17 @@ typedef struct { #define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_MDATACTRL_TXFULL_SHIFT (30U) -/*! TXFULL - Transmit Is Full - * 0b0..Transmit FIFO or buffer is not yet full. - * 0b1..Transmit FIFO or buffer is full. +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full */ #define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) #define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) -/*! RXEMPTY - Receive Is Empty - * 0b0..Receive FIFO or buffer is not yet empty. - * 0b1..Receive FIFO or buffer is empty. +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty */ #define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) /*! @} */ @@ -35604,16 +35595,16 @@ typedef struct { #define I3C_MWDATAB_END_MASK (0x100U) #define I3C_MWDATAB_END_SHIFT (8U) /*! END - End of Message - * 0b0..Not the end. More bytes are assumed to be in the message. - * 0b1..End. The END bit marks the last byte of the message. + * 0b0..Not the end + * 0b1..End */ #define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) #define I3C_MWDATAB_END_ALSO_MASK (0x10000U) #define I3C_MWDATAB_END_ALSO_SHIFT (16U) -/*! END_ALSO - End of Message Also - * 0b0..Not the end. More bytes are assumed to be in the message. - * 0b1..End. The END bit marks the last byte of the message. +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End */ #define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) /*! @} */ @@ -35642,9 +35633,9 @@ typedef struct { #define I3C_MWDATAH_END_MASK (0x10000U) #define I3C_MWDATAH_END_SHIFT (16U) -/*! END - End of message - * 0b0..Not the end. More bytes are assumed to be in the message. - * 0b1..End. The END bit marks the last byte of the message. +/*! END - End of Message + * 0b0..Not the end + * 0b1..End */ #define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) /*! @} */ @@ -35677,16 +35668,16 @@ typedef struct { #define I3C_MRDATAH_LSB_MASK (0xFFU) #define I3C_MRDATAH_LSB_SHIFT (0U) -/*! LSB - LSB */ +/*! LSB - Low Byte */ #define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) #define I3C_MRDATAH_MSB_MASK (0xFF00U) #define I3C_MRDATAH_MSB_SHIFT (8U) -/*! MSB - MSB */ +/*! MSB - High Byte */ #define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) /*! @} */ -/*! @name MWDATAB1 - Controller Write Byte Data 1(to bus) */ +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ /*! @{ */ #define I3C_MWDATAB1_VALUE_MASK (0xFFU) @@ -35714,8 +35705,8 @@ typedef struct { #define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) #define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) /*! END - End of SDR Message - * 0b0..Not the end. SDR message ends waiting for a new SDR message (issues a repeated START for a new message). - * 0b1..End. SDR message ends at the STOP. + * 0b0..Not the end + * 0b1..End */ #define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) @@ -35760,7 +35751,7 @@ typedef struct { #define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) /*! @} */ -/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR mode Control 2 */ +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ /*! @{ */ #define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) @@ -35770,9 +35761,9 @@ typedef struct { #define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) -/*! END - End of message - * 0b1..End. DDR message ends on HDR Exit. - * 0b0..Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message). +/*! END - End of Message + * 0b1..End + * 0b0..Not the end */ #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) /*! @} */ @@ -35800,7 +35791,7 @@ typedef struct { #define I3C_MDYNADDR_DAVALID_MASK (0x1U) #define I3C_MDYNADDR_DAVALID_SHIFT (0U) -/*! DAVALID - Dynamic address valid +/*! DAVALID - Dynamic Address Valid * 0b1..Valid DA assigned * 0b0..No valid DA assigned */ @@ -35808,7 +35799,7 @@ typedef struct { #define I3C_MDYNADDR_DADDR_MASK (0xFEU) #define I3C_MDYNADDR_DADDR_SHIFT (1U) -/*! DADDR - Dynamic address */ +/*! DADDR - Dynamic Address */ #define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) /*! @} */ @@ -35818,8 +35809,8 @@ typedef struct { #define I3C_SMAPCTRL0_ENA_MASK (0x1U) #define I3C_SMAPCTRL0_ENA_SHIFT (0U) /*! ENA - Enable Primary Dynamic Address - * 0b0..Disable - * 0b1..Enable + * 0b0..Disabled + * 0b1..Enabled */ #define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) @@ -35831,12 +35822,11 @@ typedef struct { #define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) #define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) /*! CAUSE - Cause - * 0b000..No information. This value occurs when not configured to write DA. + * 0b000..No information (this value occurs when not configured to write DA) * 0b001..Set using ENTDAA * 0b010..Set using SETDASA, SETAASA, or SETNEWDA * 0b011..Cleared using RSTDAA - * 0b100..Auto MAP change happened last. The change may have changed this DA as well (for example, ENTDAA, and - * SETAASA), but at least one MAP entry automatically changed after. + * 0b100..Auto MAP change happened last * *.. */ #define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) @@ -35857,17 +35847,17 @@ typedef struct { #define I3C_IBIEXT1_EXT1_MASK (0xFF00U) #define I3C_IBIEXT1_EXT1_SHIFT (8U) -/*! EXT1 - Extra byte 1 */ +/*! EXT1 - Extra Byte 1 */ #define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) #define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) #define I3C_IBIEXT1_EXT2_SHIFT (16U) -/*! EXT2 - Extra byte 2 */ +/*! EXT2 - Extra Byte 2 */ #define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) #define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) #define I3C_IBIEXT1_EXT3_SHIFT (24U) -/*! EXT3 - Extra byte 3 */ +/*! EXT3 - Extra Byte 3 */ #define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) /*! @} */ @@ -35876,22 +35866,22 @@ typedef struct { #define I3C_IBIEXT2_EXT4_MASK (0xFFU) #define I3C_IBIEXT2_EXT4_SHIFT (0U) -/*! EXT4 - Extra byte 4 */ +/*! EXT4 - Extra Byte 4 */ #define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) #define I3C_IBIEXT2_EXT5_MASK (0xFF00U) #define I3C_IBIEXT2_EXT5_SHIFT (8U) -/*! EXT5 - Extra byte 5 */ +/*! EXT5 - Extra Byte 5 */ #define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) #define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) #define I3C_IBIEXT2_EXT6_SHIFT (16U) -/*! EXT6 - Extra byte 6 */ +/*! EXT6 - Extra Byte 6 */ #define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) #define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) #define I3C_IBIEXT2_EXT7_SHIFT (24U) -/*! EXT7 - Extra byte 7 */ +/*! EXT7 - Extra Byte 7 */ #define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) /*! @} */ @@ -35974,19 +35964,19 @@ typedef struct { __IO uint32_t CTIMER0CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */ __IO uint32_t CTIMER0CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */ __IO uint32_t CTIMER0CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */ - __IO uint32_t TIMER0TRIG; /**< Trigger Register for TIMER, offset: 0x30 */ + __IO uint32_t TIMER0TRIG; /**< Trigger Register for CTIMER, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CTIMER1CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */ __IO uint32_t CTIMER1CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */ __IO uint32_t CTIMER1CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */ __IO uint32_t CTIMER1CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */ - __IO uint32_t TIMER1TRIG; /**< Trigger Register for TIMER, offset: 0x50 */ + __IO uint32_t TIMER1TRIG; /**< Trigger Register for CTIMER, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t CTIMER2CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */ __IO uint32_t CTIMER2CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */ __IO uint32_t CTIMER2CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */ __IO uint32_t CTIMER2CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */ - __IO uint32_t TIMER2TRIG; /**< Trigger Register for TIMER, offset: 0x70 */ + __IO uint32_t TIMER2TRIG; /**< Trigger Register for CTIMER, offset: 0x70 */ uint8_t RESERVED_2[44]; __IO uint32_t SMARTDMAARCHB_INMUX[8]; /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */ __IO uint32_t PINTSEL[8]; /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */ @@ -35998,13 +35988,13 @@ typedef struct { __IO uint32_t CTIMER3CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */ __IO uint32_t CTIMER3CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */ __IO uint32_t CTIMER3CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */ - __IO uint32_t TIMER3TRIG; /**< Trigger Register for TIMER, offset: 0x1B0 */ + __IO uint32_t TIMER3TRIG; /**< Trigger Register for CTIMER, offset: 0x1B0 */ uint8_t RESERVED_5[12]; __IO uint32_t CTIMER4CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */ __IO uint32_t CTIMER4CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */ __IO uint32_t CTIMER4CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */ __IO uint32_t CTIMER4CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */ - __IO uint32_t TIMER4TRIG; /**< Trigger Register for TIMER, offset: 0x1D0 */ + __IO uint32_t TIMER4TRIG; /**< Trigger Register for CTIMER, offset: 0x1D0 */ uint8_t RESERVED_6[140]; __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ uint8_t RESERVED_7[28]; @@ -36018,101 +36008,62 @@ typedef struct { uint8_t RESERVED_11[28]; __IO uint32_t DAC2_TRIG; /**< DAC2 Trigger Inputs, offset: 0x340 */ uint8_t RESERVED_12[28]; - __IO uint32_t ENC0_TRIG; /**< ENC0 Trigger Input Connections, offset: 0x360 */ - __IO uint32_t ENC0_HOME; /**< ENC0 Input Connections, offset: 0x364 */ - __IO uint32_t ENC0_INDEX; /**< ENC0 Input Connections, offset: 0x368 */ - __IO uint32_t ENC0_PHASEB; /**< ENC0 Input Connections, offset: 0x36C */ - __IO uint32_t ENC0_PHASEA; /**< ENC0 Input Connections, offset: 0x370 */ - uint8_t RESERVED_13[12]; - __IO uint32_t ENC1_TRIG; /**< ENC1 Trigger Input Connections, offset: 0x380 */ - __IO uint32_t ENC1_HOME; /**< ENC1 Input Connections, offset: 0x384 */ - __IO uint32_t ENC1_INDEX; /**< ENC1 Input Connections, offset: 0x388 */ - __IO uint32_t ENC1_PHASEB; /**< ENC1 Input Connections, offset: 0x38C */ - __IO uint32_t ENC1_PHASEA; /**< ENC1 Input Connections, offset: 0x390 */ - uint8_t RESERVED_14[12]; + struct { /* offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_TRIG; /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_HOME; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */ + __IO uint32_t QDC_INDEX; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */ + __IO uint32_t QDC_PHASEB; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */ + __IO uint32_t QDC_PHASEA; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */ + uint8_t RESERVED_0[12]; + } QDCN[2]; __IO uint32_t FLEXPWM0_SM_EXTSYNC[4]; /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */ __IO uint32_t FLEXPWM0_SM_EXTA[4]; /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */ __IO uint32_t FLEXPWM0_EXTFORCE; /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */ __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */ - uint8_t RESERVED_15[12]; + uint8_t RESERVED_13[12]; __IO uint32_t FLEXPWM1_SM_EXTSYNC[4]; /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */ - __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input Trigger Connections, array offset: 0x3F0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */ __IO uint32_t FLEXPWM1_EXTFORCE; /**< PWM1 External Force Trigger Connections, offset: 0x400 */ __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */ - uint8_t RESERVED_16[12]; + uint8_t RESERVED_14[12]; __IO uint32_t PWM0_EXT_CLK; /**< PWM0 External Clock Trigger, offset: 0x420 */ __IO uint32_t PWM1_EXT_CLK; /**< PWM1 External Clock Trigger, offset: 0x424 */ - uint8_t RESERVED_17[24]; - __IO uint32_t EVTG_TRIG0; /**< EVTG Trigger Input Connections 0, offset: 0x440 */ - __IO uint32_t EVTG_TRIG1; /**< EVTG Trigger Input Connections 1, offset: 0x444 */ - __IO uint32_t EVTG_TRIG2; /**< EVTG Trigger Input Connections 2, offset: 0x448 */ - __IO uint32_t EVTG_TRIG3; /**< EVTG Trigger Input Connections 3, offset: 0x44C */ - __IO uint32_t EVTG_TRIG4; /**< EVTG Trigger Input Connections 4, offset: 0x450 */ - __IO uint32_t EVTG_TRIG5; /**< EVTG Trigger Input Connections 5, offset: 0x454 */ - __IO uint32_t EVTG_TRIG6; /**< EVTG Trigger Input Connections 6, offset: 0x458 */ - __IO uint32_t EVTG_TRIG7; /**< EVTG Trigger Input Connections 7, offset: 0x45C */ - __IO uint32_t EVTG_TRIG8; /**< EVTG Trigger Input Connections 8, offset: 0x460 */ - __IO uint32_t EVTG_TRIG9; /**< EVTG Trigger Input Connections 9, offset: 0x464 */ - __IO uint32_t EVTG_TRIG10; /**< EVTG Trigger Input Connections 10, offset: 0x468 */ - __IO uint32_t EVTG_TRIG11; /**< EVTG Trigger Input Connections 11, offset: 0x46C */ - __IO uint32_t EVTG_TRIG12; /**< EVTG Trigger Input Connections 12, offset: 0x470 */ - __IO uint32_t EVTG_TRIG13; /**< EVTG Trigger Input Connections 13, offset: 0x474 */ - __IO uint32_t EVTG_TRIG14; /**< EVTG Trigger Input Connections 14, offset: 0x478 */ - __IO uint32_t EVTG_TRIG15; /**< EVTG Trigger Input Connections 15, offset: 0x47C */ + uint8_t RESERVED_15[24]; + __IO uint32_t EVTG_TRIG[16]; /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */ __IO uint32_t USBFS_TRIG; /**< USB-FS Trigger Input Connections, offset: 0x480 */ - uint8_t RESERVED_18[28]; + uint8_t RESERVED_16[28]; __IO uint32_t TSI_TRIG; /**< TSI Trigger Input Connections, offset: 0x4A0 */ - uint8_t RESERVED_19[28]; - __IO uint32_t EXT_TRIG0; /**< EXT Trigger Connections 0, offset: 0x4C0 */ - __IO uint32_t EXT_TRIG1; /**< EXT Trigger Connections 1, offset: 0x4C4 */ - __IO uint32_t EXT_TRIG2; /**< EXT Trigger Connections 2, offset: 0x4C8 */ - __IO uint32_t EXT_TRIG3; /**< EXT Trigger Connections 3, offset: 0x4CC */ - __IO uint32_t EXT_TRIG4; /**< EXT Trigger Connections 4, offset: 0x4D0 */ - __IO uint32_t EXT_TRIG5; /**< EXT Trigger Connections 5, offset: 0x4D4 */ - __IO uint32_t EXT_TRIG6; /**< EXT Trigger Connections 6, offset: 0x4D8 */ - __IO uint32_t EXT_TRIG7; /**< EXT Trigger Connections 7, offset: 0x4DC */ + uint8_t RESERVED_17[28]; + __IO uint32_t EXT_TRIG[8]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ __IO uint32_t CMP1_TRIG; /**< CMP1 Input Connections, offset: 0x4E0 */ - uint8_t RESERVED_20[28]; + uint8_t RESERVED_18[28]; __IO uint32_t CMP2_TRIG; /**< CMP2 Input Connections, offset: 0x500 */ - uint8_t RESERVED_21[28]; - __IO uint32_t SINC_FILTER_CH0; /**< SINC Filter Channel0 Trigger Input Connections, offset: 0x520 */ - __IO uint32_t SINC_FILTER_CH1; /**< SINC Filter Channel1 Trigger Input Connections, offset: 0x524 */ - __IO uint32_t SINC_FILTER_CH2; /**< SINC Filter Channel2 Trigger Input Connections, offset: 0x528 */ - __IO uint32_t SINC_FILTER_CH3; /**< SINC Filter Channel3 Trigger Input Connections, offset: 0x52C */ - __IO uint32_t SINC_FILTER_CH4; /**< SINC Filter Channel4 Trigger Input Connections, offset: 0x530 */ - uint8_t RESERVED_22[76]; - __IO uint32_t OPAMP0_TRIG; /**< OPAMP0 Trigger Input Connections, offset: 0x580 */ - __IO uint32_t OPAMP1_TRIG; /**< OPAMP1 Trigger Input Connections, offset: 0x584 */ - __IO uint32_t OPAMP2_TRIG; /**< OPAMP2 Trigger Input Connections, offset: 0x588 */ - uint8_t RESERVED_23[20]; + uint8_t RESERVED_19[28]; + __IO uint32_t SINC_FILTER_CH[5]; /**< SINC Filter Channel Trigger Input Connections, array offset: 0x520, array step: 0x4 */ + uint8_t RESERVED_20[76]; + __IO uint32_t OPAMP_TRIG[3]; /**< OPAMP Trigger Input Connections, array offset: 0x580, array step: 0x4 */ + uint8_t RESERVED_21[20]; __IO uint32_t FLEXCOMM0_TRIG; /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */ - uint8_t RESERVED_24[28]; + uint8_t RESERVED_22[28]; __IO uint32_t FLEXCOMM1_TRIG; /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */ - uint8_t RESERVED_25[28]; + uint8_t RESERVED_23[28]; __IO uint32_t FLEXCOMM2_TRIG; /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */ - uint8_t RESERVED_26[28]; + uint8_t RESERVED_24[28]; __IO uint32_t FLEXCOMM3_TRIG; /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */ - uint8_t RESERVED_27[28]; + uint8_t RESERVED_25[28]; __IO uint32_t FLEXCOMM4_TRIG; /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */ - uint8_t RESERVED_28[28]; + uint8_t RESERVED_26[28]; __IO uint32_t FLEXCOMM5_TRIG; /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */ - uint8_t RESERVED_29[28]; + uint8_t RESERVED_27[28]; __IO uint32_t FLEXCOMM6_TRIG; /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */ - uint8_t RESERVED_30[28]; + uint8_t RESERVED_28[28]; __IO uint32_t FLEXCOMM7_TRIG; /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */ - uint8_t RESERVED_31[28]; + uint8_t RESERVED_29[28]; __IO uint32_t FLEXCOMM8_TRIG; /**< LP_FLEXCOMM8 Trigger Input Connections, offset: 0x6A0 */ - uint8_t RESERVED_32[28]; + uint8_t RESERVED_30[28]; __IO uint32_t FLEXCOMM9_TRIG; /**< LP_FLEXCOMM9 Trigger Input Connections, offset: 0x6C0 */ - uint8_t RESERVED_33[28]; - __IO uint32_t FLEXIO_TRIG0; /**< FlexIO Trigger Input Connections 0, offset: 0x6E0 */ - __IO uint32_t FLEXIO_TRIG1; /**< FlexIO Trigger Input Connections 1, offset: 0x6E4 */ - __IO uint32_t FLEXIO_TRIG2; /**< FlexIO Trigger Input Connections 2, offset: 0x6E8 */ - __IO uint32_t FLEXIO_TRIG3; /**< FlexIO Trigger Input Connections 3, offset: 0x6EC */ - __IO uint32_t FLEXIO_TRIG4; /**< FlexIO Trigger Input Connections 4, offset: 0x6F0 */ - __IO uint32_t FLEXIO_TRIG5; /**< FlexIO Trigger Input Connections 5, offset: 0x6F4 */ - __IO uint32_t FLEXIO_TRIG6; /**< FlexIO Trigger Input Connections 6, offset: 0x6F8 */ - __IO uint32_t FLEXIO_TRIG7; /**< FlexIO Trigger Input Connections 7, offset: 0x6FC */ + uint8_t RESERVED_31[28]; + __IO uint32_t FLEXIO_TRIG[8]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ __IO uint32_t DMA0_REQ_ENABLE0; /**< DMA0 Request Enable0, offset: 0x700 */ __O uint32_t DMA0_REQ_ENABLE0_SET; /**< DMA0 Request Enable0, offset: 0x704 */ __O uint32_t DMA0_REQ_ENABLE0_CLR; /**< DMA0 Request Enable0, offset: 0x708 */ @@ -36128,7 +36079,7 @@ typedef struct { __IO uint32_t DMA0_REQ_ENABLE3; /**< DMA0 Request Enable3, offset: 0x730 */ __O uint32_t DMA0_REQ_ENABLE3_SET; /**< DMA0 Request Enable3, offset: 0x734 */ __O uint32_t DMA0_REQ_ENABLE3_CLR; /**< DMA0 Request Enable3, offset: 0x738 */ - uint8_t RESERVED_34[68]; + uint8_t RESERVED_32[68]; __IO uint32_t DMA1_REQ_ENABLE0; /**< DMA1 Request Enable0, offset: 0x780 */ __O uint32_t DMA1_REQ_ENABLE0_SET; /**< DMA1 Request Enable0, offset: 0x784 */ __O uint32_t DMA1_REQ_ENABLE0_CLR; /**< DMA1 Request Enable0, offset: 0x788 */ @@ -36183,7 +36134,7 @@ typedef struct { * 0b0010011..SINC Filter CH2 Conversion Complete input is selected * 0b0010100..SINC Filter CH3 Conversion Complete input is selected * 0b0010101..SINC Filter CH4 Conversion Complete input is selected - * 0b0010110..ARM_TXEV (CM33 event output) input is selected + * 0b0010110..Reserved * 0b0010111..DEBUG_HALTED input is selected * 0b0011000..ADC1_IRQ input is selected * 0b0011001..ADC0_tcomp[0] input is selected @@ -36197,16 +36148,16 @@ typedef struct { * 0b0100001..CMP0_OUT input is selected * 0b0100010..CMP1_OUT input is selected * 0b0100011..CMP2_OUT input is selected - * 0b0100100..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0100101..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100110..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100111..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0101000..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0101001..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0101010..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0101100..ENC0_CMP/POS_MATCH input is selected - * 0b0101101..ENC1_CMP/POS_MATCH input is selected + * 0b0100100..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0100101..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100111..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0101000..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0101100..QDC0_CMP/POS_MATCH input is selected + * 0b0101101..QDC1_CMP/POS_MATCH input is selected * 0b0101110..EVTG_OUT0A input is selected * 0b0101111..EVTG_OUT0B input is selected * 0b0110000..EVTG_OUT1A input is selected @@ -36215,10 +36166,10 @@ typedef struct { * 0b0110011..EVTG_OUT2B input is selected * 0b0110100..EVTG_OUT3A input is selected * 0b0110101..EVTG_OUT3B input is selected - * 0b0110110..FC3_P0 (SDO, RXD, SDA) input is selected - * 0b0110111..FC3_P1 (SCK, TXD, SCL)) input is selected - * 0b0111000..FC3_P2 (SDI, RTS, SCLS, TXD) input is selected - * 0b0111001..FC3_P3 (PCS[0], CTS, SDAS, RXD) input is selected + * 0b0110110..FC3_P0 (SDO, SDA) input is selected + * 0b0110111..FC3_P1 (SCK, TXD, SCL) input is selected + * 0b0111000..FC3_P2 (RTS, SCLS, TXD) input is selected + * 0b0111001..FC3_P3 (PCS[0], CTS, SDAS) input is selected * 0b0111010..Reserved * 0b0111011..Reserved * 0b0111100..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected @@ -36251,7 +36202,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36275,23 +36226,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36315,8 +36266,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK) @@ -36327,7 +36278,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36351,23 +36302,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36391,8 +36342,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK) @@ -36403,7 +36354,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36427,23 +36378,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36467,8 +36418,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK) @@ -36479,7 +36430,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36503,23 +36454,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36543,19 +36494,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK) /*! @} */ -/*! @name TIMER0TRIG - Trigger Register for TIMER */ +/*! @name TIMER0TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36579,23 +36530,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36619,8 +36570,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) @@ -36631,7 +36582,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36655,23 +36606,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36695,8 +36646,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK) @@ -36707,7 +36658,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36731,23 +36682,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36771,8 +36722,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK) @@ -36783,7 +36734,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36807,23 +36758,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36847,8 +36798,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK) @@ -36859,7 +36810,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36883,23 +36834,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36923,19 +36874,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK) /*! @} */ -/*! @name TIMER1TRIG - Trigger Register for TIMER */ +/*! @name TIMER1TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36959,23 +36910,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36999,8 +36950,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) @@ -37011,7 +36962,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37035,23 +36986,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37075,8 +37026,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK) @@ -37087,7 +37038,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37111,23 +37062,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37151,8 +37102,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK) @@ -37163,7 +37114,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37187,23 +37138,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37227,8 +37178,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK) @@ -37239,7 +37190,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37263,23 +37214,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37303,19 +37254,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK) /*! @} */ -/*! @name TIMER2TRIG - Trigger Register for TIMER */ +/*! @name TIMER2TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37339,23 +37290,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37379,8 +37330,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) @@ -37392,7 +37343,7 @@ typedef struct { #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU) #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U) /*! INP - Input number select to SmartDMA ARCHB input - * 0b0000000..GPIO P0_0 input is selected + * 0b0000000..FlexIO interrupt is selected as input * 0b0000001..GPIO P0_1 input is selected * 0b0000010..GPIO P0_2 input is selected * 0b0000011..GPIO P0_3 input is selected @@ -37424,7 +37375,7 @@ typedef struct { * 0b0011101..WWDT0 WDT0_IRQ input is selected * 0b0011110..ADC0 ADC0_IRQ input is selected * 0b0011111..CMP0_IRQ input is selected - * 0b0100000..LPSPI LSPI_HS_IRQ input is selected + * 0b0100000..Reserved * 0b0100001..LP_FLEXCOMM7_IRQ input is selected * 0b0100010..LP_FLEXCOMM6_IRQ input is selected * 0b0100011..LP_FLEXCOMM5_IRQ input is selected @@ -37435,10 +37386,12 @@ typedef struct { * 0b0101000..LP_FLEXCOMM0_IRQ input is selected * 0b0101001..DMA0_IRQ input is selected * 0b0101010..DMA1_IRQ input is selected - * 0b0101011..SYS_IRQ input is selected + * 0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure + * violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR + * operation. input is selected * 0b0101100..RTC_COMBO_IRQ input is selected * 0b0101101..ARM_TXEV input is selected - * 0b0101110..PINT GPIO_INT_BMATCH input is selected + * 0b0101110..PINT0 GPIO_INT_BMATCH input is selected * 0b0101111..Reserved * 0b0110000..Reserved * 0b0110001..CMP0_OUT input is selected @@ -37451,8 +37404,8 @@ typedef struct { * 0b0111000..DAC1_IRQ/DAC2_IRQ input is selected * 0b0111001..PWM0_IRQ input is selected * 0b0111010..PWM1_IRQ input is selected - * 0b0111011..ENC0_IRQ input is selected - * 0b0111100..ENC1_IRQ input is selected + * 0b0111011..QDC0_IRQ input is selected + * 0b0111100..QDC1_IRQ input is selected * 0b0111101..EVTG_OUT0A input is selected * 0b0111110..EVTG_OUT1A input is selected * 0b0111111..Reserved @@ -37555,7 +37508,7 @@ typedef struct { #define INPUTMUX_FREQMEAS_REF_INP_MASK (0x3FU) #define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) -/*! INP - Clock source number (binary value) for frequency measure function target clock. +/*! INP - Clock source number (binary value) for frequency measure function reference clock. * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected * 0b000001..FRO_12M input is selected * 0b000010..FRO_144M input is selected @@ -37597,7 +37550,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37621,23 +37574,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37661,8 +37614,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK) @@ -37673,7 +37626,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37697,23 +37650,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37737,8 +37690,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK) @@ -37749,7 +37702,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37773,23 +37726,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37813,8 +37766,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK) @@ -37825,7 +37778,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37849,23 +37802,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37889,19 +37842,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK) /*! @} */ -/*! @name TIMER3TRIG - Trigger Register for TIMER */ +/*! @name TIMER3TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37925,23 +37878,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37965,8 +37918,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) @@ -37977,7 +37930,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38001,23 +37954,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38041,8 +37994,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK) @@ -38053,7 +38006,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38077,23 +38030,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38117,8 +38070,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK) @@ -38129,7 +38082,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38153,23 +38106,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38193,8 +38146,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK) @@ -38205,7 +38158,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38229,23 +38182,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38269,19 +38222,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK) /*! @} */ -/*! @name TIMER4TRIG - Trigger Register for TIMER */ +/*! @name TIMER4TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38305,23 +38258,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38345,8 +38298,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) @@ -38369,22 +38322,22 @@ typedef struct { * 0b001000..CTIMER0_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC1_tcomp[0] input is selected * 0b001111..Reserved * 0b010000..Reserved - * 0b010001..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b010010..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b010011..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b010100..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b010101..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b010110..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b010111..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b011000..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b011001..ENC0_CMP/POS_MATCH input is selected - * 0b011010..ENC1_CMP/POS_MATCH input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected @@ -38421,7 +38374,7 @@ typedef struct { * 0b00001000..CTIMER3_MAT3 input is selected * 0b00001001..CTIMER4_MAT3 input is selected * 0b00001010..DCDC_Burst_Done_Trig input is selected - * 0b00001011..ARM_TXEV input is selected + * 0b00001011..Reserved * 0b00001100..PINT GPIO_INT_BMAT input is selected * 0b00001101..ADC0_tcomp[0] input is selected * 0b00001110..ADC0_tcomp[1] input is selected @@ -38434,24 +38387,24 @@ typedef struct { * 0b00010101..CMP0_OUT input is selected * 0b00010110..CMP1_OUT input is selected * 0b00010111..CMP2_OUT input is selected - * 0b00011000..PWM0_A0_TRIG0 input is selected - * 0b00011001..PWM0_A0_TRIG1 input is selected - * 0b00011010..PWM0_A1_TRIG0 input is selected - * 0b00011011..PWM0_A1_TRIG1 input is selected - * 0b00011100..PWM0_A2_TRIG0 input is selected - * 0b00011101..PWM0_A2_TRIG1 input is selected - * 0b00011110..PWM0_A3_TRIG0 input is selected - * 0b00011111..PWM0_A3_TRIG1 input is selected - * 0b00100000..PWM1_A0_TRIG0 input is selected - * 0b00100001..PWM1_A0_TRIG1 input is selected - * 0b00100010..PWM1_A1_TRIG0 input is selected - * 0b00100011..PWM1_A1_TRIG1 input is selected - * 0b00100100..PWM1_A2_TRIG0 input is selected - * 0b00100101..PWM1_A2_TRIG1 input is selected - * 0b00100110..PWM1_A3_TRIG0 input is selected - * 0b00100111..PWM1_A3_TRIG1 input is selected - * 0b00101000..ENC0_CMP/POS_MATCH input is selected - * 0b00101001..ENC1_CMP/POS_MATCH input is selected + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected * 0b00101010..EVTG_OUT0A input is selected * 0b00101011..EVTG_OUT0B input is selected * 0b00101100..EVTG_OUT1A input is selected @@ -38489,7 +38442,7 @@ typedef struct { #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU) #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - ADC0 trigger inputs +/*! TRIGIN - ADC1 trigger inputs * 0b00000000..PINT PIN_INT0 input is selected * 0b00000001..PINT PIN_INT2 input is selected * 0b00000010..SCT0 SCT_OUT4 input is selected @@ -38501,7 +38454,7 @@ typedef struct { * 0b00001000..CTIMER3_MAT2 input is selected * 0b00001001..CTIMER4_MAT1 input is selected * 0b00001010..DCDC_Burst_Done_Trig input is selected - * 0b00001011..ARM_TXEV input is selected + * 0b00001011..Reserved * 0b00001100..PINT GPIO_INT_BMAT input is selected * 0b00001101..ADC0_tcomp[0] input is selected * 0b00001110..ADC0_tcomp[1] input is selected @@ -38514,24 +38467,24 @@ typedef struct { * 0b00010101..CMP0_OUT input is selected * 0b00010110..CMP1_OUT input is selected * 0b00010111..CMP2_OUT input is selected - * 0b00011000..PWM0_A0_TRIG0 input is selected - * 0b00011001..PWM0_A0_TRIG1 input is selected - * 0b00011010..PWM0_A1_TRIG0 input is selected - * 0b00011011..PWM0_A1_TRIG1 input is selected - * 0b00011100..PWM0_A2_TRIG0 input is selected - * 0b00011101..PWM0_A2_TRIG1 input is selected - * 0b00011110..PWM0_A3_TRIG0 input is selected - * 0b00011111..PWM0_A3_TRIG1 input is selected - * 0b00100000..PWM1_A0_TRIG0 input is selected - * 0b00100001..PWM1_A0_TRIG1 input is selected - * 0b00100010..PWM1_A1_TRIG0 input is selected - * 0b00100011..PWM1_A1_TRIG1 input is selected - * 0b00100100..PWM1_A2_TRIG0 input is selected - * 0b00100101..PWM1_A2_TRIG1 input is selected - * 0b00100110..PWM1_A3_TRIG0 input is selected - * 0b00100111..PWM1_A3_TRIG1 input is selected - * 0b00101000..ENC0_CMP/POS_MATCH input is selected - * 0b00101001..ENC1_CMP/POS_MATCH input is selected + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected * 0b00101010..EVTG_OUT0A input is selected * 0b00101011..EVTG_OUT0B input is selected * 0b00101100..EVTG_OUT1A input is selected @@ -38581,7 +38534,7 @@ typedef struct { * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC1_tcomp[0] input is selected @@ -38624,7 +38577,7 @@ typedef struct { * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER3_MAT1 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[1] input is selected * 0b001110..ADC1_tcomp[1] input is selected @@ -38667,7 +38620,7 @@ typedef struct { * 0b001000..CTIMER2_MAT2 input is selected * 0b001001..CTIMER3_MAT2 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[2] input is selected * 0b001110..ADC1_tcomp[2] input is selected @@ -38693,12 +38646,12 @@ typedef struct { #define INPUTMUX_DAC2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK) /*! @} */ -/*! @name ENC0_TRIG - ENC0 Trigger Input Connections */ +/*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_TRIG_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38723,16 +38676,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38753,15 +38706,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_TRIG_INP_SHIFT)) & INPUTMUX_ENC0_TRIG_INP_MASK) +#define INPUTMUX_QDCN_QDC_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK) /*! @} */ -/*! @name ENC0_HOME - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_TRIG */ +#define INPUTMUX_QDCN_QDC_TRIG_COUNT (2U) + +/*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_HOME_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_HOME_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_HOME_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT (0U) +/*! INP - QDC1 HOME input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected @@ -38786,16 +38742,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38816,15 +38772,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_HOME_INP_SHIFT)) & INPUTMUX_ENC0_HOME_INP_MASK) +#define INPUTMUX_QDCN_QDC_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK) /*! @} */ -/*! @name ENC0_INDEX - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_HOME */ +#define INPUTMUX_QDCN_QDC_HOME_COUNT (2U) + +/*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_INDEX_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_INDEX_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_INDEX_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 INDEX input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38849,16 +38808,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38879,15 +38838,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_INDEX_INP_SHIFT)) & INPUTMUX_ENC0_INDEX_INP_MASK) +#define INPUTMUX_QDCN_QDC_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK) /*! @} */ -/*! @name ENC0_PHASEB - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_INDEX */ +#define INPUTMUX_QDCN_QDC_INDEX_COUNT (2U) + +/*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_PHASEB_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_PHASEB_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 PHASEB input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38912,16 +38874,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38942,15 +38904,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEB_INP_SHIFT)) & INPUTMUX_ENC0_PHASEB_INP_MASK) +#define INPUTMUX_QDCN_QDC_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK) /*! @} */ -/*! @name ENC0_PHASEA - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_PHASEB */ +#define INPUTMUX_QDCN_QDC_PHASEB_COUNT (2U) + +/*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_PHASEA_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_PHASEA_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT (0U) +/*! INP - QDC1 PHASEA input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38975,16 +38940,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39005,330 +38970,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEA_INP_SHIFT)) & INPUTMUX_ENC0_PHASEA_INP_MASK) +#define INPUTMUX_QDCN_QDC_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK) /*! @} */ -/*! @name ENC1_TRIG - ENC1 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_TRIG_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_TRIG_INP_SHIFT)) & INPUTMUX_ENC1_TRIG_INP_MASK) -/*! @} */ - -/*! @name ENC1_HOME - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_HOME_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_HOME_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_HOME_INP_SHIFT)) & INPUTMUX_ENC1_HOME_INP_MASK) -/*! @} */ - -/*! @name ENC1_INDEX - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_INDEX_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_INDEX_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_INDEX_INP_SHIFT)) & INPUTMUX_ENC1_INDEX_INP_MASK) -/*! @} */ - -/*! @name ENC1_PHASEB - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_PHASEB_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_PHASEB_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEB_INP_SHIFT)) & INPUTMUX_ENC1_PHASEB_INP_MASK) -/*! @} */ - -/*! @name ENC1_PHASEA - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_PHASEA_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_PHASEA_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEA_INP_SHIFT)) & INPUTMUX_ENC1_PHASEA_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_QDCN_QDC_PHASEA */ +#define INPUTMUX_QDCN_QDC_PHASEA_COUNT (2U) /*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTSYNC input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39353,16 +39006,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39403,7 +39056,7 @@ typedef struct { #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTA input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39428,16 +39081,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39478,7 +39131,7 @@ typedef struct { #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTFORCE input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39503,16 +39156,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39550,7 +39203,7 @@ typedef struct { #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - FAULT input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39575,16 +39228,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39625,7 +39278,7 @@ typedef struct { #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTSYNC input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39650,16 +39303,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39695,12 +39348,12 @@ typedef struct { /* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */ #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U) -/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input Trigger Connections */ +/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTA input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39725,16 +39378,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39775,7 +39428,7 @@ typedef struct { #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 +/*! TRIGIN - EXTFORCE input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39800,16 +39453,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39847,7 +39500,7 @@ typedef struct { #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 +/*! TRIGIN - FAULT input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39872,16 +39525,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39922,7 +39575,7 @@ typedef struct { #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U) #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM +/*! TRIGIN - EXT_CLK input connections for PWM0 * 0b000..FRO16K input is selected * 0b001..OSC_32k input is selected * 0b010..EVTG_OUT0A input is selected @@ -39939,7 +39592,7 @@ typedef struct { #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM +/*! TRIGIN - EXT_CLK input connections for PWM1 * 0b0000..FRO16K input is selected * 0b0001..OSC_32k input is selected * 0b0010..EVTG_OUT0A input is selected @@ -39951,11 +39604,11 @@ typedef struct { #define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) /*! @} */ -/*! @name EVTG_TRIG0 - EVTG Trigger Input Connections 0 */ +/*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_EVTG_TRIG0_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG0_INP_SHIFT (0U) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT (0U) /*! INP - EVTG trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected @@ -39984,24 +39637,24 @@ typedef struct { * 0b011000..CMP0_OUT input is selected * 0b011001..CMP1_OUT input is selected * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected + * 0b011011..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100111..PWM1_SM2_MUX_TRIG0 input is selected + * 0b101000..PWM1_SM2_MUX_TRIG1 input is selected + * 0b101001..PWM1_SM3_MUX_TRIG0 input is selected + * 0b101010..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101011..QDC0_CMP/POS_MATCH input is selected + * 0b101100..QDC1_CMP/POS_MATCH input is selected * 0b101101..TRIG_IN0 input is selected * 0b101110..TRIG_IN1 input is selected * 0b101111..TRIG_IN2 input is selected @@ -40017,1043 +39670,11 @@ typedef struct { * 0b111001..Reserved * *.. */ -#define INPUTMUX_EVTG_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG0_INP_SHIFT)) & INPUTMUX_EVTG_TRIG0_INP_MASK) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK) /*! @} */ -/*! @name EVTG_TRIG1 - EVTG Trigger Input Connections 1 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG1_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG1_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG1_INP_SHIFT)) & INPUTMUX_EVTG_TRIG1_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG2 - EVTG Trigger Input Connections 2 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG2_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG2_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG2_INP_SHIFT)) & INPUTMUX_EVTG_TRIG2_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG3 - EVTG Trigger Input Connections 3 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG3_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG3_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG3_INP_SHIFT)) & INPUTMUX_EVTG_TRIG3_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG4 - EVTG Trigger Input Connections 4 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG4_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG4_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..GPIO_INT_BMATCH input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG4_INP_SHIFT)) & INPUTMUX_EVTG_TRIG4_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG5 - EVTG Trigger Input Connections 5 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG5_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG5_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG5_INP_SHIFT)) & INPUTMUX_EVTG_TRIG5_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG6 - EVTG Trigger Input Connections 6 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG6_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG6_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG6_INP_SHIFT)) & INPUTMUX_EVTG_TRIG6_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG7 - EVTG Trigger Input Connections 7 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG7_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG7_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG7_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG7_INP_SHIFT)) & INPUTMUX_EVTG_TRIG7_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG8 - EVTG Trigger Input Connections 8 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG8_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG8_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG8_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG8_INP_SHIFT)) & INPUTMUX_EVTG_TRIG8_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG9 - EVTG Trigger Input Connections 9 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG9_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG9_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG9_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG9_INP_SHIFT)) & INPUTMUX_EVTG_TRIG9_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG10 - EVTG Trigger Input Connections 10 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG10_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG10_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG10_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG10_INP_SHIFT)) & INPUTMUX_EVTG_TRIG10_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG11 - EVTG Trigger Input Connections 11 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG11_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG11_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG11_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG11_INP_SHIFT)) & INPUTMUX_EVTG_TRIG11_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG12 - EVTG Trigger Input Connections 12 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG12_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG12_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG12_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG12_INP_SHIFT)) & INPUTMUX_EVTG_TRIG12_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG13 - EVTG Trigger Input Connections 13 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG13_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG13_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG13_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG13_INP_SHIFT)) & INPUTMUX_EVTG_TRIG13_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG14 - EVTG Trigger Input Connections 14 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG14_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG14_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG14_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG14_INP_SHIFT)) & INPUTMUX_EVTG_TRIG14_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG15 - EVTG Trigger Input Connections 15 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG15_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG15_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG15_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG15_INP_SHIFT)) & INPUTMUX_EVTG_TRIG15_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT (16U) /*! @name USBFS_TRIG - USB-FS Trigger Input Connections */ /*! @{ */ @@ -41089,28 +39710,28 @@ typedef struct { #define INPUTMUX_TSI_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TSI_TRIG_INP_SHIFT)) & INPUTMUX_TSI_TRIG_INP_MASK) /*! @} */ -/*! @name EXT_TRIG0 - EXT Trigger Connections 0 */ +/*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */ /*! @{ */ -#define INPUTMUX_EXT_TRIG0_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG0_INP_SHIFT (0U) -/*! INP - EXT trigger input connections +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) +/*! INP - TRIG_OUTa pin input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected * 0b000010..ADC0_IRQ input is selected * 0b000011..ADC1_IRQ input is selected * 0b000100..ADC0_tcomp[0] input is selected * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected + * 0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b001110..QDC0_CMP/POS_MATCH input is selected + * 0b001111..QDC1_CMP/POS_MATCH input is selected * 0b010000..EVTG_OUT0A input is selected * 0b010001..EVTG_OUT0B input is selected * 0b010010..EVTG_OUT1A input is selected @@ -41129,437 +39750,27 @@ typedef struct { * 0b011111..SCT Out3 input is selected * 0b100000..SCT Out4 input is selected * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected + * 0b100010..LP_FLEXCOMM0 trigger output 3 input is selected + * 0b100011..LP_FLEXCOMM1 trigger output 3 input is selected + * 0b100100..LP_FLEXCOMM2 trigger output 3 input is selected + * 0b100101..LP_FLEXCOMM3 trigger output 3 input is selected + * 0b100110..LP_FLEXCOMM4 trigger output 3 input is selected + * 0b100111..LP_FLEXCOMM5 trigger output 3 input is selected + * 0b101000..LP_FLEXCOMM6 trigger output 3 input is selected + * 0b101001..LP_FLEXCOMM7 trigger output 3 input is selected + * 0b101010..LP_FLEXCOMM8 trigger output 3 input is selected + * 0b101011..LP_FLEXCOMM9 trigger output 3 input is selected * 0b101100..CMP0_OUT input is selected * 0b101101..CMP1_OUT input is selected * 0b101110..CMP2_OUT input is selected * 0b101111..ENET_PPS_OUT_0 input is selected * *.. */ -#define INPUTMUX_EXT_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG0_INP_SHIFT)) & INPUTMUX_EXT_TRIG0_INP_MASK) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) /*! @} */ -/*! @name EXT_TRIG1 - EXT Trigger Connections 1 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG1_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG1_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG1_INP_SHIFT)) & INPUTMUX_EXT_TRIG1_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG2 - EXT Trigger Connections 2 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG2_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG2_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG2_INP_SHIFT)) & INPUTMUX_EXT_TRIG2_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG3 - EXT Trigger Connections 3 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG3_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG3_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG3_INP_SHIFT)) & INPUTMUX_EXT_TRIG3_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG4 - EXT Trigger Connections 4 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG4_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG4_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG4_INP_SHIFT)) & INPUTMUX_EXT_TRIG4_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG5 - EXT Trigger Connections 5 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG5_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG5_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG5_INP_SHIFT)) & INPUTMUX_EXT_TRIG5_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG6 - EXT Trigger Connections 6 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG6_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG6_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG6_INP_SHIFT)) & INPUTMUX_EXT_TRIG6_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG7 - EXT Trigger Connections 7 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG7_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG7_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG7_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG7_INP_SHIFT)) & INPUTMUX_EXT_TRIG7_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) /*! @name CMP1_TRIG - CMP1 Input Connections */ /*! @{ */ @@ -41578,22 +39789,22 @@ typedef struct { * 0b001000..CTIMER3_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[1] input is selected * 0b001110..ADC1_tcomp[1] input is selected * 0b001111..Reserved * 0b010000..Reserved - * 0b010001..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b010010..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b010011..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b010100..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b010101..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b010110..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b010111..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b011000..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b011001..ENC0_CMP/POS_MATCH input is selected - * 0b011010..ENC1_CMP/POS_MATCH input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected @@ -41630,22 +39841,22 @@ typedef struct { * 0b001000..CTIMER3_MAT2 input is selected * 0b001001..CTIMER4_MAT2 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[2] input is selected * 0b001110..ADC1_tcomp[2] input is selected * 0b001111..Reserved * 0b010000..Reserved - * 0b010001..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b010010..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b010011..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b010100..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b010101..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b010110..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b010111..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b011000..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b011001..ENC0_CMP/POS_MATCH input is selected - * 0b011010..ENC1_CMP/POS_MATCH input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected @@ -41665,11 +39876,11 @@ typedef struct { #define INPUTMUX_CMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK) /*! @} */ -/*! @name SINC_FILTER_CH0 - SINC Filter Channel0 Trigger Input Connections */ +/*! @name SINC_FILTER_CHN_SINC_FILTER_CH - SINC Filter Channel Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_SINC_FILTER_CH0_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH0_INP_SHIFT (0U) +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK (0x3FU) +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT (0U) /*! INP - SINC FILTER trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected @@ -41682,7 +39893,7 @@ typedef struct { * 0b001000..CTIMER3_MAT3 input is selected * 0b001001..CTIMER4_MAT3 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected @@ -41695,24 +39906,24 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101000..QDC0_CMP/POS_MATCH input is selected + * 0b101001..QDC1_CMP/POS_MATCH input is selected * 0b101010..EVTG_OUT0A input is selected * 0b101011..EVTG_OUT0B input is selected * 0b101100..EVTG_OUT1A input is selected @@ -41730,286 +39941,17 @@ typedef struct { * 0b111000..WUU input is selected * *.. */ -#define INPUTMUX_SINC_FILTER_CH0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH0_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH0_INP_MASK) +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK) /*! @} */ -/*! @name SINC_FILTER_CH1 - SINC Filter Channel1 Trigger Input Connections */ +/* The count of INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH */ +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_COUNT (5U) + +/*! @name OPAMPN_TRIG_OPAMP_TRIG - OPAMP Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_SINC_FILTER_CH1_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH1_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH1_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH1_INP_MASK) -/*! @} */ - -/*! @name SINC_FILTER_CH2 - SINC Filter Channel2 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_SINC_FILTER_CH2_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH2_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH2_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH2_INP_MASK) -/*! @} */ - -/*! @name SINC_FILTER_CH3 - SINC Filter Channel3 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_SINC_FILTER_CH3_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH3_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH3_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH3_INP_MASK) -/*! @} */ - -/*! @name SINC_FILTER_CH4 - SINC Filter Channel4 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_SINC_FILTER_CH4_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH4_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH4_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH4_INP_MASK) -/*! @} */ - -/*! @name OPAMP0_TRIG - OPAMP0 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_OPAMP0_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_OPAMP0_TRIG_INP_SHIFT (0U) +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT (0U) /*! INP - OPAMP trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected @@ -42034,22 +39976,22 @@ typedef struct { * 0b010100..ADC1_tcomp[1] input is selected * 0b010101..ADC1_tcomp[2] input is selected * 0b010110..ADC1_tcomp[3] input is selected - * 0b010111..PWM0_A0_TRIG0 input is selected - * 0b011000..PWM0_A0_TRIG1 input is selected - * 0b011001..PWM0_A1_TRIG0 input is selected - * 0b011010..PWM0_A1_TRIG1 input is selected - * 0b011011..PWM0_A2_TRIG0 input is selected - * 0b011100..PWM0_A2_TRIG1 input is selected - * 0b011101..PWM0_A3_TRIG0 input is selected - * 0b011110..PWM0_A3_TRIG1 input is selected - * 0b011111..PWM1_A0_TRIG0 input is selected - * 0b100000..PWM1_A0_TRIG1 input is selected - * 0b100001..PWM1_A1_TRIG0 input is selected - * 0b100010..PWM1_A1_TRIG1 input is selected - * 0b100011..PWM1_A2_TRIG0 input is selected - * 0b100100..PWM1_A2_TRIG1 input is selected - * 0b100101..PWM1_A3_TRIG0 input is selected - * 0b100110..PWM1_A3_TRIG1 input is selected + * 0b010111..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011001..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011011..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011111..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100000..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100001..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100010..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM2_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM2_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM3_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM3_MUX_TRIG1 input is selected * 0b100111..EVTG_OUT0A input is selected * 0b101000..EVTG_OUT0B input is selected * 0b101001..EVTG_OUT1A input is selected @@ -42068,147 +40010,18 @@ typedef struct { * 0b110110..FlexIO CH7 input is selected * *.. */ -#define INPUTMUX_OPAMP0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP0_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP0_TRIG_INP_MASK) +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT)) & INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK) /*! @} */ -/*! @name OPAMP1_TRIG - OPAMP1 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_OPAMP1_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_OPAMP1_TRIG_INP_SHIFT (0U) -/*! INP - OPAMP trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..PINT PIN_INT2 input is selected - * 0b000011..PINT PIN_INT3 input is selected - * 0b000100..SCT_OUT4 input is selected - * 0b000101..SCT_OUT5 input is selected - * 0b000110..SCT_OUT6 input is selected - * 0b000111..SCT_OUT7 input is selected - * 0b001000..SCT_OUT8 input is selected - * 0b001001..CTIMER0_MAT3 input is selected - * 0b001010..CTIMER1_MAT3 input is selected - * 0b001011..CTIMER2_MAT3 input is selected - * 0b001100..CTIMER3_MAT3 input is selected - * 0b001101..CTIMER4_MAT3 input is selected - * 0b001110..PINT GPIO_INT_BMAT input is selected - * 0b001111..ADC0_tcomp[0] input is selected - * 0b010000..ADC0_tcomp[1] input is selected - * 0b010001..ADC0_tcomp[2] input is selected - * 0b010010..ADC0_tcomp[3] input is selected - * 0b010011..ADC1_tcomp[0] input is selected - * 0b010100..ADC1_tcomp[1] input is selected - * 0b010101..ADC1_tcomp[2] input is selected - * 0b010110..ADC1_tcomp[3] input is selected - * 0b010111..PWM0_A0_TRIG0 input is selected - * 0b011000..PWM0_A0_TRIG1 input is selected - * 0b011001..PWM0_A1_TRIG0 input is selected - * 0b011010..PWM0_A1_TRIG1 input is selected - * 0b011011..PWM0_A2_TRIG0 input is selected - * 0b011100..PWM0_A2_TRIG1 input is selected - * 0b011101..PWM0_A3_TRIG0 input is selected - * 0b011110..PWM0_A3_TRIG1 input is selected - * 0b011111..PWM1_A0_TRIG0 input is selected - * 0b100000..PWM1_A0_TRIG1 input is selected - * 0b100001..PWM1_A1_TRIG0 input is selected - * 0b100010..PWM1_A1_TRIG1 input is selected - * 0b100011..PWM1_A2_TRIG0 input is selected - * 0b100100..PWM1_A2_TRIG1 input is selected - * 0b100101..PWM1_A3_TRIG0 input is selected - * 0b100110..PWM1_A3_TRIG1 input is selected - * 0b100111..EVTG_OUT0A input is selected - * 0b101000..EVTG_OUT0B input is selected - * 0b101001..EVTG_OUT1A input is selected - * 0b101010..EVTG_OUT1B input is selected - * 0b101011..EVTG_OUT2A input is selected - * 0b101100..EVTG_OUT2B input is selected - * 0b101101..EVTG_OUT3A input is selected - * 0b101110..EVTG_OUT3B input is selected - * 0b101111..TRIG_IN0 input is selected - * 0b110000..TRIG_IN1 input is selected - * 0b110001..TRIG_IN2 input is selected - * 0b110010..TRIG_IN3 input is selected - * 0b110011..FlexIO CH4 input is selected - * 0b110100..FlexIO CH5 input is selected - * 0b110101..FlexIO CH6 input is selected - * 0b110110..FlexIO CH7 input is selected - * *.. - */ -#define INPUTMUX_OPAMP1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP1_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP1_TRIG_INP_MASK) -/*! @} */ - -/*! @name OPAMP2_TRIG - OPAMP2 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_OPAMP2_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_OPAMP2_TRIG_INP_SHIFT (0U) -/*! INP - OPAMP trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..PINT PIN_INT2 input is selected - * 0b000011..PINT PIN_INT3 input is selected - * 0b000100..SCT_OUT4 input is selected - * 0b000101..SCT_OUT5 input is selected - * 0b000110..SCT_OUT6 input is selected - * 0b000111..SCT_OUT7 input is selected - * 0b001000..SCT_OUT8 input is selected - * 0b001001..CTIMER0_MAT3 input is selected - * 0b001010..CTIMER1_MAT3 input is selected - * 0b001011..CTIMER2_MAT3 input is selected - * 0b001100..CTIMER3_MAT3 input is selected - * 0b001101..CTIMER4_MAT3 input is selected - * 0b001110..PINT GPIO_INT_BMAT input is selected - * 0b001111..ADC0_tcomp[0] input is selected - * 0b010000..ADC0_tcomp[1] input is selected - * 0b010001..ADC0_tcomp[2] input is selected - * 0b010010..ADC0_tcomp[3] input is selected - * 0b010011..ADC1_tcomp[0] input is selected - * 0b010100..ADC1_tcomp[1] input is selected - * 0b010101..ADC1_tcomp[2] input is selected - * 0b010110..ADC1_tcomp[3] input is selected - * 0b010111..PWM0_A0_TRIG0 input is selected - * 0b011000..PWM0_A0_TRIG1 input is selected - * 0b011001..PWM0_A1_TRIG0 input is selected - * 0b011010..PWM0_A1_TRIG1 input is selected - * 0b011011..PWM0_A2_TRIG0 input is selected - * 0b011100..PWM0_A2_TRIG1 input is selected - * 0b011101..PWM0_A3_TRIG0 input is selected - * 0b011110..PWM0_A3_TRIG1 input is selected - * 0b011111..PWM1_A0_TRIG0 input is selected - * 0b100000..PWM1_A0_TRIG1 input is selected - * 0b100001..PWM1_A1_TRIG0 input is selected - * 0b100010..PWM1_A1_TRIG1 input is selected - * 0b100011..PWM1_A2_TRIG0 input is selected - * 0b100100..PWM1_A2_TRIG1 input is selected - * 0b100101..PWM1_A3_TRIG0 input is selected - * 0b100110..PWM1_A3_TRIG1 input is selected - * 0b100111..EVTG_OUT0A input is selected - * 0b101000..EVTG_OUT0B input is selected - * 0b101001..EVTG_OUT1A input is selected - * 0b101010..EVTG_OUT1B input is selected - * 0b101011..EVTG_OUT2A input is selected - * 0b101100..EVTG_OUT2B input is selected - * 0b101101..EVTG_OUT3A input is selected - * 0b101110..EVTG_OUT3B input is selected - * 0b101111..TRIG_IN0 input is selected - * 0b110000..TRIG_IN1 input is selected - * 0b110001..TRIG_IN2 input is selected - * 0b110010..TRIG_IN3 input is selected - * 0b110011..FlexIO CH4 input is selected - * 0b110100..FlexIO CH5 input is selected - * 0b110101..FlexIO CH6 input is selected - * 0b110110..FlexIO CH7 input is selected - * *.. - */ -#define INPUTMUX_OPAMP2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP2_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP2_TRIG_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG */ +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_COUNT (3U) /*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM0 trigger input connections +/*! INP - LP_FLEXCOMM0 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT6 input is selected @@ -42222,7 +40035,7 @@ typedef struct { * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42262,7 +40075,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM1 trigger input connections +/*! INP - LP_FLEXCOMM1 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT6 input is selected @@ -42276,7 +40089,7 @@ typedef struct { * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42316,7 +40129,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM2 trigger input connections +/*! INP - LP_FLEXCOMM2 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT6 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42330,7 +40143,7 @@ typedef struct { * 0b001010..CTIMER4_MAT1 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42370,7 +40183,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM3 trigger input connections +/*! INP - LP_FLEXCOMM3 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42384,7 +40197,7 @@ typedef struct { * 0b001010..CTIMER4_MAT1 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42424,7 +40237,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM4 trigger input connections +/*! INP - LP_FLEXCOMM4 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42438,7 +40251,7 @@ typedef struct { * 0b001010..CTIMER4_MAT2 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42478,7 +40291,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM5 trigger input connections +/*! INP - LP_FLEXCOMM5 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42492,7 +40305,7 @@ typedef struct { * 0b001010..CTIMER4_MAT2 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42532,7 +40345,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM6 trigger input connections +/*! INP - LP_FLEXCOMM6 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42546,7 +40359,7 @@ typedef struct { * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42586,7 +40399,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM7 trigger input connections +/*! INP - LP_FLEXCOMM7 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42600,7 +40413,7 @@ typedef struct { * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42640,7 +40453,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM8_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM8_TRIG_INP_SHIFT (0U) -/*! INP - Flexcomm8 trigger input connections +/*! INP - LP_FLEXCOMM8 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42654,7 +40467,7 @@ typedef struct { * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42694,7 +40507,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM9_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT (0U) -/*! INP - Flexcomm9 trigger input connections +/*! INP - LP_FLEXCOMM9 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42708,7 +40521,7 @@ typedef struct { * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42743,11 +40556,11 @@ typedef struct { #define INPUTMUX_FLEXCOMM9_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM9_TRIG_INP_MASK) /*! @} */ -/*! @name FLEXIO_TRIG0 - FlexIO Trigger Input Connections 0 */ +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_FLEXIO_TRIG0_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG0_INP_SHIFT (0U) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) /*! INP - Input number for FlexIO0. * 0b0000000..PINT PIN_INT4 input is selected * 0b0000001..PINT PIN_INT5 input is selected @@ -42765,7 +40578,7 @@ typedef struct { * 0b0001101..T4_MAT1 input is selected * 0b0001110..LPTMR0 input is selected * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected + * 0b0010000..Reserved * 0b0010001..PINT GPIO_INT_BMAT input is selected * 0b0010010..ADC0_tcomp[0] input is selected * 0b0010011..ADC0_tcomp[1] input is selected @@ -42778,22 +40591,22 @@ typedef struct { * 0b0011010..CMP0_OUT input is selected * 0b0011011..CMP1_OUT input is selected * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected + * 0b0011101..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100011..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100100..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100110..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100111..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0101000..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101100..PWM1_SM3_MUX_TRIG1 input is selected * 0b0101101..EVTG_OUT0A input is selected * 0b0101110..EVTG_OUT0B input is selected * 0b0101111..EVTG_OUT1A input is selected @@ -42828,624 +40641,11 @@ typedef struct { * 0b1001100..WUU input is selected * *.. */ -#define INPUTMUX_FLEXIO_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG0_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG0_INP_MASK) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) /*! @} */ -/*! @name FLEXIO_TRIG1 - FlexIO Trigger Input Connections 1 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG1_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG1_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG1_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG1_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG2 - FlexIO Trigger Input Connections 2 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG2_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG2_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG2_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG2_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG3 - FlexIO Trigger Input Connections 3 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG3_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG3_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG3_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG3_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG4 - FlexIO Trigger Input Connections 4 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG4_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG4_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG4_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG4_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG5 - FlexIO Trigger Input Connections 5 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG5_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG5_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG5_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG5_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG6 - FlexIO Trigger Input Connections 6 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG6_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG6_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG6_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG6_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG7 - FlexIO Trigger Input Connections 7 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG7_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG7_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG7_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG7_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG7_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (8U) /*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */ /*! @{ */ @@ -43468,7 +40668,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U) -/*! REQ3_EN0 - This register is used to enable and disable INT0 request. +/*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request. * 0b0..Disable * 0b1..Enable */ @@ -43476,7 +40676,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U) -/*! REQ4_EN0 - This register is used to enable and disable INT1 request. +/*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request. * 0b0..Disable * 0b1..Enable */ @@ -43484,7 +40684,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U) -/*! REQ5_EN0 - This register is used to enable and disable INT2 request. +/*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request. * 0b0..Disable * 0b1..Enable */ @@ -43492,7 +40692,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U) -/*! REQ6_EN0 - This register is used to enable and disable INT3 request. +/*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request. * 0b0..Disable * 0b1..Enable */ @@ -43500,7 +40700,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U) -/*! REQ7_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43508,7 +40708,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U) -/*! REQ8_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43516,7 +40716,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U) -/*! REQ9_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43524,7 +40724,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U) -/*! REQ10_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43532,7 +40732,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U) -/*! REQ11_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43540,7 +40740,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U) -/*! REQ12_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43548,7 +40748,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U) -/*! REQ13_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43556,7 +40756,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U) -/*! REQ14_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43564,7 +40764,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U) -/*! REQ15_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43572,7 +40772,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U) -/*! REQ16_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43580,7 +40780,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U) -/*! REQ17_EN0 - This register is used to enable and disable wake up event request. +/*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request. * 0b0..Disable * 0b1..Enable */ @@ -43588,7 +40788,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U) -/*! REQ18_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43596,7 +40796,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_SHIFT (19U) -/*! REQ19_EN0 - This register is used to enable and disable DMA0 request. +/*! REQ19_EN0 - This register is used to enable and disable SCT0 DMA0 request. * 0b0..Disable * 0b1..Enable */ @@ -43604,7 +40804,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_SHIFT (20U) -/*! REQ20_EN0 - This register is used to enable and disable DMA1 request. +/*! REQ20_EN0 - This register is used to enable and disable SCT0 DMA1 request. * 0b0..Disable * 0b1..Enable */ @@ -43612,7 +40812,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U) -/*! REQ21_EN0 - This register is used to enable and disable FIFO A request. +/*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -43620,7 +40820,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U) -/*! REQ22_EN0 - This register is used to enable and disable FIFO B request. +/*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -43628,7 +40828,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U) -/*! REQ23_EN0 - This register is used to enable and disable FIFO A request. +/*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -43636,7 +40836,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U) -/*! REQ24_EN0 - This register is used to enable and disable FIFO B request. +/*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -43644,7 +40844,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_SHIFT (25U) -/*! REQ25_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ25_EN0 - This register is used to enable and disable DAC0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43652,7 +40852,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_SHIFT (26U) -/*! REQ26_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ26_EN0 - This register is used to enable and disable DAC1 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43660,7 +40860,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_SHIFT (27U) -/*! REQ27_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ27_EN0 - This register is used to enable and disable DAC2 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43668,7 +40868,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U) -/*! REQ28_EN0 - This register is used to enable and disable DMA_request. +/*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -43676,7 +40876,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U) -/*! REQ29_EN0 - This register is used to enable and disable DMA_request. +/*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -43684,7 +40884,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_SHIFT (30U) -/*! REQ30_EN0 - This register is used to enable and disable DMA_request. +/*! REQ30_EN0 - This register is used to enable and disable CMP2 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -43692,7 +40892,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U) -/*! REQ31_EN0 - This register is used to enable and disable OUT0A request. +/*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request. * 0b0..Disable * 0b1..Enable */ @@ -44181,7 +41381,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U) -/*! REQ32_EN0 - This register is used to enable and disable OUT0B request. +/*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request. * 0b0..Disable * 0b1..Enable */ @@ -44189,7 +41389,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U) -/*! REQ33_EN0 - This register is used to enable and disable OUT1A request. +/*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request. * 0b0..Disable * 0b1..Enable */ @@ -44197,7 +41397,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U) -/*! REQ34_EN0 - This register is used to enable and disable OUT1B request. +/*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request. * 0b0..Disable * 0b1..Enable */ @@ -44205,7 +41405,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U) -/*! REQ35_EN0 - This register is used to enable and disable OUT2A request. +/*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request. * 0b0..Disable * 0b1..Enable */ @@ -44213,7 +41413,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U) -/*! REQ36_EN0 - This register is used to enable and disable OUT2B request. +/*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request. * 0b0..Disable * 0b1..Enable */ @@ -44221,7 +41421,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U) -/*! REQ37_EN0 - This register is used to enable and disable OUT3A request. +/*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request. * 0b0..Disable * 0b1..Enable */ @@ -44229,7 +41429,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U) -/*! REQ38_EN0 - This register is used to enable and disable OUT3B request. +/*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request. * 0b0..Disable * 0b1..Enable */ @@ -44237,7 +41437,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U) -/*! REQ39_EN0 - This register is used to enable and disable Req_capt0 request. +/*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -44245,7 +41445,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U) -/*! REQ40_EN0 - This register is used to enable and disable Req_capt1 request. +/*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -44253,7 +41453,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U) -/*! REQ41_EN0 - This register is used to enable and disable Req_capt2 request. +/*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -44261,7 +41461,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U) -/*! REQ42_EN0 - This register is used to enable and disable Req_capt3 request. +/*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -44269,7 +41469,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U) -/*! REQ43_EN0 - This register is used to enable and disable Req_val0 request. +/*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -44277,7 +41477,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U) -/*! REQ44_EN0 - This register is used to enable and disable Req_val1 request. +/*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -44285,7 +41485,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U) -/*! REQ45_EN0 - This register is used to enable and disable Req_val2 request. +/*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -44293,7 +41493,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U) -/*! REQ46_EN0 - This register is used to enable and disable Req_val3 request. +/*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -44301,7 +41501,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U) -/*! REQ47_EN0 - This register is used to enable and disable Req_capt0 request. +/*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -44309,7 +41509,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U) -/*! REQ48_EN0 - This register is used to enable and disable Req_capt1 request. +/*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -44317,7 +41517,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U) -/*! REQ49_EN0 - This register is used to enable and disable Req_capt2 request. +/*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -44325,7 +41525,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U) -/*! REQ50_EN0 - This register is used to enable and disable Req_capt3 request. +/*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -44333,7 +41533,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U) -/*! REQ51_EN0 - This register is used to enable and disable Req_val0 request. +/*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -44341,7 +41541,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U) -/*! REQ52_EN0 - This register is used to enable and disable Req_val1 request. +/*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -44349,7 +41549,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U) -/*! REQ53_EN0 - This register is used to enable and disable Req_val2 request. +/*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -44357,7 +41557,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U) -/*! REQ54_EN0 - This register is used to enable and disable Req_val3 request. +/*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -44365,7 +41565,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U) -/*! REQ57_EN0 - This register is used to enable and disable counter match event request. +/*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -44373,7 +41573,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U) -/*! REQ58_EN0 - This register is used to enable and disable counter match event request. +/*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -44381,7 +41581,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U) -/*! REQ59_EN0 - This register is used to enable and disable DMA request. +/*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44389,7 +41589,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U) -/*! REQ60_EN0 - This register is used to enable and disable DMA request. +/*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44397,7 +41597,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U) -/*! REQ61_EN0 - This register is used to enable and disable shift register 0 request. +/*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44405,7 +41605,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U) -/*! REQ62_EN0 - This register is used to enable and disable shift register 1 request. +/*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44413,7 +41613,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U) -/*! REQ63_EN0 - This register is used to enable and disable shift register 2 request. +/*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44538,16 +41738,6 @@ typedef struct { /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_MASK (0x800000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_SHIFT (23U) -/*! REQ55_EN0 - Writing a 1 to REQ55_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_SHIFT (24U) -/*! REQ56_EN0 - Writing a 1 to REQ56_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ @@ -44702,16 +41892,6 @@ typedef struct { /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_MASK (0x800000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_SHIFT (23U) -/*! REQ55_EN0 - Writing a 1 to REQ55_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_SHIFT (24U) -/*! REQ56_EN0 - Writing a 1 to REQ56_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ @@ -44866,16 +42046,6 @@ typedef struct { /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_MASK (0x800000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_SHIFT (23U) -/*! REQ55_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_SHIFT (24U) -/*! REQ56_EN0 - Writing a 1 to REQ56_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ @@ -44917,7 +42087,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U) -/*! REQ64_EN0 - This register is used to enable and disable shift register 3 request. +/*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request. * 0b0..Disable * 0b1..Enable */ @@ -44925,7 +42095,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U) -/*! REQ65_EN0 - This register is used to enable and disable shift register 4 request. +/*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request. * 0b0..Disable * 0b1..Enable */ @@ -44933,7 +42103,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U) -/*! REQ66_EN0 - This register is used to enable and disable shift register 5 request. +/*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request. * 0b0..Disable * 0b1..Enable */ @@ -44941,7 +42111,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U) -/*! REQ67_EN0 - This register is used to enable and disable shift register 6 request. +/*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request. * 0b0..Disable * 0b1..Enable */ @@ -44949,7 +42119,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U) -/*! REQ68_EN0 - This register is used to enable and disable shift register 7 request. +/*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request. * 0b0..Disable * 0b1..Enable */ @@ -44957,7 +42127,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U) -/*! REQ69_EN0 - This register is used to enable and disable receive request. +/*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -44965,7 +42135,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U) -/*! REQ70_EN0 - This register is used to enable and disable transmit request. +/*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -44973,7 +42143,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U) -/*! REQ71_EN0 - This register is used to enable and disable receive request. +/*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -44981,7 +42151,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U) -/*! REQ72_EN0 - This register is used to enable and disable transmit request. +/*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -44989,7 +42159,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U) -/*! REQ73_EN0 - This register is used to enable and disable receive request. +/*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request. * 0b0..Disable * 0b1..Enable */ @@ -44997,7 +42167,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U) -/*! REQ74_EN0 - This register is used to enable and disable transmit request. +/*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45005,7 +42175,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U) -/*! REQ75_EN0 - This register is used to enable and disable receive request. +/*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45013,7 +42183,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U) -/*! REQ76_EN0 - This register is used to enable and disable transmit request. +/*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45021,7 +42191,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U) -/*! REQ77_EN0 - This register is used to enable and disable receive request. +/*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45029,7 +42199,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U) -/*! REQ78_EN0 - This register is used to enable and disable transmit request. +/*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45037,7 +42207,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U) -/*! REQ79_EN0 - This register is used to enable and disable receive request. +/*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45045,7 +42215,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U) -/*! REQ80_EN0 - This register is used to enable and disable transmit request. +/*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45053,7 +42223,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U) -/*! REQ81_EN0 - This register is used to enable and disable receive request. +/*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45061,7 +42231,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U) -/*! REQ82_EN0 - This register is used to enable and disable transmit request. +/*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45069,7 +42239,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U) -/*! REQ83_EN0 - This register is used to enable and disable receive request. +/*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45077,7 +42247,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U) -/*! REQ84_EN0 - This register is used to enable and disable transmit request. +/*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45085,7 +42255,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_SHIFT (21U) -/*! REQ85_EN0 - This register is used to enable and disable receive request. +/*! REQ85_EN0 - This register is used to enable and disable LP_FLEXCOMM8 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45093,7 +42263,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_SHIFT (22U) -/*! REQ86_EN0 - This register is used to enable and disable transmit request. +/*! REQ86_EN0 - This register is used to enable and disable LP_FLEXCOMM8 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45101,7 +42271,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_SHIFT (23U) -/*! REQ87_EN0 - This register is used to enable and disable receive request. +/*! REQ87_EN0 - This register is used to enable and disable LP_FLEXCOMM9 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45109,31 +42279,15 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT (24U) -/*! REQ88_EN0 - This register is used to enable and disable transmit request. +/*! REQ88_EN0 - This register is used to enable and disable LP_FLEXCOMM9 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - This register is used to enable and disable channel 0 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - This register is used to enable and disable channel 1 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_SHIFT (27U) -/*! REQ91_EN0 - This register is used to enable and disable receive request. +/*! REQ91_EN0 - This register is used to enable and disable EMVSIM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45141,7 +42295,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_SHIFT (28U) -/*! REQ92_EN0 - This register is used to enable and disable transmit request. +/*! REQ92_EN0 - This register is used to enable and disable EMVSIM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45149,7 +42303,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_SHIFT (29U) -/*! REQ93_EN0 - This register is used to enable and disable receive request. +/*! REQ93_EN0 - This register is used to enable and disable EMVSIM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45157,7 +42311,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_SHIFT (30U) -/*! REQ94_EN0 - This register is used to enable and disable transmit request. +/*! REQ94_EN0 - This register is used to enable and disable EMVSIM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45165,7 +42319,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U) -/*! REQ95_EN0 - This register is used to enable and disable receive request. +/*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45300,16 +42454,6 @@ typedef struct { /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - Writing a 1 to REQ89_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - Writing a 1 to REQ90_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ @@ -45464,16 +42608,6 @@ typedef struct { /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - Writing a 1 to REQ89_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - Writing a 1 to REQ90_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ @@ -45628,16 +42762,6 @@ typedef struct { /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - Writing a 1 to REQ89_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - Writing a 1 to REQ90_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ @@ -45669,7 +42793,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U) -/*! REQ96_EN0 - This register is used to enable and disable transmit request. +/*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45677,7 +42801,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U) -/*! REQ97_EN0 - This register is used to enable and disable shift register 4 request. +/*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45685,7 +42809,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U) -/*! REQ98_EN0 - This register is used to enable and disable transmit request. +/*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45693,7 +42817,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U) -/*! REQ99_EN0 - This register is used to enable and disable shift register 6 request. +/*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45701,7 +42825,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U) -/*! REQ100_EN0 - This register is used to enable and disable transmit request. +/*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45709,7 +42833,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U) -/*! REQ101_EN0 - This register is used to enable and disable receive request. +/*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45717,7 +42841,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U) -/*! REQ102_EN0 - This register is used to enable and disable transmit request. +/*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45725,7 +42849,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_SHIFT (7U) -/*! REQ103_EN0 - This register is used to enable and disable ipd_req_sinc[0] or ipd_req_alt [0] request. +/*! REQ103_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request. * 0b0..Disable * 0b1..Enable */ @@ -45733,7 +42857,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_SHIFT (8U) -/*! REQ104_EN0 - This register is used to enable and disable ipd_req_sinc[1] or ipd_req_alt [1] request. +/*! REQ104_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request. * 0b0..Disable * 0b1..Enable */ @@ -45741,7 +42865,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_SHIFT (9U) -/*! REQ105_EN0 - This register is used to enable and disable ipd_req_sinc[2] or ipd_req_alt [2] request. +/*! REQ105_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request. * 0b0..Disable * 0b1..Enable */ @@ -45749,7 +42873,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_SHIFT (10U) -/*! REQ106_EN0 - This register is used to enable and disable ipd_req_sinc[3] or ipd_req_alt [3] request. +/*! REQ106_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request. * 0b0..Disable * 0b1..Enable */ @@ -45757,7 +42881,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_SHIFT (11U) -/*! REQ107_EN0 - This register is used to enable and disable ipd_req_sinc[4] or ipd_req_alt [4] request. +/*! REQ107_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request. * 0b0..Disable * 0b1..Enable */ @@ -45765,7 +42889,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U) -/*! REQ108_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45773,7 +42897,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U) -/*! REQ109_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45781,7 +42905,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U) -/*! REQ110_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45789,7 +42913,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U) -/*! REQ111_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45797,7 +42921,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U) -/*! REQ112_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45805,7 +42929,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U) -/*! REQ113_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45813,7 +42937,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U) -/*! REQ114_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45821,7 +42945,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U) -/*! REQ115_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45829,7 +42953,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U) -/*! REQ116_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45837,7 +42961,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U) -/*! REQ117_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45845,7 +42969,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U) -/*! REQ118_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45853,7 +42977,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U) -/*! REQ119_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45861,7 +42985,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_SHIFT (24U) -/*! REQ120_EN0 - This register is used to enable and disable end of scan request. +/*! REQ120_EN0 - This register is used to enable and disable TSI0 end of scan request. * 0b0..Disable * 0b1..Enable */ @@ -45869,7 +42993,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_SHIFT (25U) -/*! REQ121_EN0 - This register is used to enable and disable out of range request. +/*! REQ121_EN0 - This register is used to enable and disable TSI0 out of range request. * 0b0..Disable * 0b1..Enable */ @@ -46165,7 +43289,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U) -/*! REQ3_EN1 - This register is used to enable and disable INT0 request. +/*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request. * 0b0..Disable * 0b1..Enable */ @@ -46173,7 +43297,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U) -/*! REQ4_EN1 - This register is used to enable and disable INT1 request. +/*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request. * 0b0..Disable * 0b1..Enable */ @@ -46181,7 +43305,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U) -/*! REQ5_EN1 - This register is used to enable and disable INT2 request. +/*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request. * 0b0..Disable * 0b1..Enable */ @@ -46189,7 +43313,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U) -/*! REQ6_EN1 - This register is used to enable and disable INT3 request. +/*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request. * 0b0..Disable * 0b1..Enable */ @@ -46197,7 +43321,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U) -/*! REQ7_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46205,7 +43329,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U) -/*! REQ8_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46213,7 +43337,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U) -/*! REQ9_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46221,7 +43345,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U) -/*! REQ10_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46229,7 +43353,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U) -/*! REQ11_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46237,7 +43361,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U) -/*! REQ12_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46245,7 +43369,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U) -/*! REQ13_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46253,7 +43377,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U) -/*! REQ14_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46261,7 +43385,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U) -/*! REQ15_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46269,7 +43393,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U) -/*! REQ16_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46277,7 +43401,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U) -/*! REQ17_EN1 - This register is used to enable and disable wake up event request. +/*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request. * 0b0..Disable * 0b1..Enable */ @@ -46285,7 +43409,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U) -/*! REQ18_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46293,7 +43417,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_SHIFT (19U) -/*! REQ19_EN1 - This register is used to enable and disable DMA0 request. +/*! REQ19_EN1 - This register is used to enable and disable SCT0 DMA0 request. * 0b0..Disable * 0b1..Enable */ @@ -46301,7 +43425,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_SHIFT (20U) -/*! REQ20_EN1 - This register is used to enable and disable DMA1 request. +/*! REQ20_EN1 - This register is used to enable and disable SCT0 DMA1 request. * 0b0..Disable * 0b1..Enable */ @@ -46309,7 +43433,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U) -/*! REQ21_EN1 - This register is used to enable and disable FIFO A request. +/*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -46317,7 +43441,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U) -/*! REQ22_EN1 - This register is used to enable and disable FIFO B request. +/*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -46325,7 +43449,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U) -/*! REQ23_EN1 - This register is used to enable and disable FIFO A request. +/*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -46333,7 +43457,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U) -/*! REQ24_EN1 - This register is used to enable and disable FIFO B request. +/*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -46341,7 +43465,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_SHIFT (25U) -/*! REQ25_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ25_EN1 - This register is used to enable and disable DAC0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46349,7 +43473,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_SHIFT (26U) -/*! REQ26_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ26_EN1 - This register is used to enable and disable DAC1 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46357,7 +43481,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_SHIFT (27U) -/*! REQ27_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ27_EN1 - This register is used to enable and disable DAC2 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46365,7 +43489,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U) -/*! REQ28_EN1 - This register is used to enable and disable DMA_request. +/*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -46373,7 +43497,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U) -/*! REQ29_EN1 - This register is used to enable and disable DMA_request. +/*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -46381,7 +43505,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_SHIFT (30U) -/*! REQ30_EN1 - This register is used to enable and disable DMA_request. +/*! REQ30_EN1 - This register is used to enable and disable CMP2 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -46389,7 +43513,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U) -/*! REQ31_EN1 - This register is used to enable and disable OUT0A request. +/*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request. * 0b0..Disable * 0b1..Enable */ @@ -46878,7 +44002,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U) -/*! REQ32_EN1 - This register is used to enable and disable OUT0B request. +/*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request. * 0b0..Disable * 0b1..Enable */ @@ -46886,7 +44010,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U) -/*! REQ33_EN1 - This register is used to enable and disable OUT1A request. +/*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request. * 0b0..Disable * 0b1..Enable */ @@ -46894,7 +44018,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U) -/*! REQ34_EN1 - This register is used to enable and disable OUT1B request. +/*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request. * 0b0..Disable * 0b1..Enable */ @@ -46902,7 +44026,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U) -/*! REQ35_EN1 - This register is used to enable and disable OUT2A request. +/*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request. * 0b0..Disable * 0b1..Enable */ @@ -46910,7 +44034,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U) -/*! REQ36_EN1 - This register is used to enable and disable OUT2B request. +/*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request. * 0b0..Disable * 0b1..Enable */ @@ -46918,7 +44042,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U) -/*! REQ37_EN1 - This register is used to enable and disable OUT3A request. +/*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request. * 0b0..Disable * 0b1..Enable */ @@ -46926,7 +44050,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U) -/*! REQ38_EN1 - This register is used to enable and disable OUT3B request. +/*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request. * 0b0..Disable * 0b1..Enable */ @@ -46934,7 +44058,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U) -/*! REQ39_EN1 - This register is used to enable and disable Req_capt0 request. +/*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -46942,7 +44066,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U) -/*! REQ40_EN1 - This register is used to enable and disable Req_capt1 request. +/*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -46950,7 +44074,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U) -/*! REQ41_EN1 - This register is used to enable and disable Req_capt2 request. +/*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -46958,7 +44082,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U) -/*! REQ42_EN1 - This register is used to enable and disable Req_capt3 request. +/*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -46966,7 +44090,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U) -/*! REQ43_EN1 - This register is used to enable and disable Req_val0 request. +/*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -46974,7 +44098,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U) -/*! REQ44_EN1 - This register is used to enable and disable Req_val1 request. +/*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -46982,7 +44106,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U) -/*! REQ45_EN1 - This register is used to enable and disable Req_val2 request. +/*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -46990,7 +44114,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U) -/*! REQ46_EN1 - This register is used to enable and disable Req_val3 request. +/*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -46998,7 +44122,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U) -/*! REQ47_EN1 - This register is used to enable and disable Req_capt0 request. +/*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -47006,7 +44130,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U) -/*! REQ48_EN1 - This register is used to enable and disable Req_capt1 request. +/*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -47014,7 +44138,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U) -/*! REQ49_EN1 - This register is used to enable and disable Req_capt2 request. +/*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -47022,7 +44146,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U) -/*! REQ50_EN1 - This register is used to enable and disable Req_capt3 request. +/*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -47030,7 +44154,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U) -/*! REQ51_EN1 - This register is used to enable and disable Req_val0 request. +/*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -47038,7 +44162,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U) -/*! REQ52_EN1 - This register is used to enable and disable Req_val1 request. +/*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -47046,7 +44170,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U) -/*! REQ53_EN1 - This register is used to enable and disable Req_val2 request. +/*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -47054,7 +44178,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U) -/*! REQ54_EN1 - This register is used to enable and disable Req_val3 request. +/*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -47062,7 +44186,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U) -/*! REQ57_EN1 - This register is used to enable and disable counter match event request. +/*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -47070,7 +44194,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U) -/*! REQ58_EN1 - This register is used to enable and disable counter match event request. +/*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -47078,7 +44202,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U) -/*! REQ59_EN1 - This register is used to enable and disable DMA request. +/*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47086,7 +44210,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U) -/*! REQ60_EN1 - This register is used to enable and disable DMA request. +/*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47094,7 +44218,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U) -/*! REQ61_EN1 - This register is used to enable and disable shift register 0 request. +/*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47102,7 +44226,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U) -/*! REQ62_EN1 - This register is used to enable and disable shift register 1 request. +/*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47110,7 +44234,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U) -/*! REQ63_EN1 - This register is used to enable and disable shift register 2 request. +/*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47235,16 +44359,6 @@ typedef struct { /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_MASK (0x800000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_SHIFT (23U) -/*! REQ55_EN1 - Writing a 1 to REQ55_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_MASK (0x1000000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_SHIFT (24U) -/*! REQ56_EN1 - Writing a 1 to REQ56_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ @@ -47399,16 +44513,6 @@ typedef struct { /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_MASK (0x800000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_SHIFT (23U) -/*! REQ55_EN1 - Writing a 1 to REQ55_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_MASK (0x1000000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_SHIFT (24U) -/*! REQ56_EN1 - Writing a 1 to REQ56_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ @@ -47563,16 +44667,6 @@ typedef struct { /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_MASK (0x800000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_SHIFT (23U) -/*! REQ55_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_MASK (0x1000000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_SHIFT (24U) -/*! REQ56_EN1 - Writing a 1 to REQ56_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ @@ -47614,7 +44708,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U) -/*! REQ64_EN1 - This register is used to enable and disable shift register 3 request. +/*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47622,7 +44716,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U) -/*! REQ65_EN1 - This register is used to enable and disable shift register 4 request. +/*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47630,7 +44724,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U) -/*! REQ66_EN1 - This register is used to enable and disable shift register 5 request. +/*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47638,7 +44732,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U) -/*! REQ67_EN1 - This register is used to enable and disable shift register 6 request. +/*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47646,7 +44740,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U) -/*! REQ68_EN1 - This register is used to enable and disable shift register 7 request. +/*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47654,7 +44748,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U) -/*! REQ69_EN1 - This register is used to enable and disable receive request. +/*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47662,7 +44756,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U) -/*! REQ70_EN1 - This register is used to enable and disable transmit request. +/*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47670,7 +44764,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U) -/*! REQ71_EN1 - This register is used to enable and disable receive request. +/*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47678,7 +44772,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U) -/*! REQ72_EN1 - This register is used to enable and disable transmit request. +/*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47686,7 +44780,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U) -/*! REQ73_EN1 - This register is used to enable and disable receive request. +/*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47694,7 +44788,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U) -/*! REQ74_EN1 - This register is used to enable and disable transmit request. +/*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47702,7 +44796,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U) -/*! REQ75_EN1 - This register is used to enable and disable receive request. +/*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47710,7 +44804,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U) -/*! REQ76_EN1 - This register is used to enable and disable transmit request. +/*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47718,7 +44812,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U) -/*! REQ77_EN1 - This register is used to enable and disable receive request. +/*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47726,7 +44820,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U) -/*! REQ78_EN1 - This register is used to enable and disable transmit request. +/*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47734,7 +44828,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U) -/*! REQ79_EN1 - This register is used to enable and disable receive request. +/*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47742,7 +44836,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U) -/*! REQ80_EN1 - This register is used to enable and disable transmit request. +/*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47750,7 +44844,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U) -/*! REQ81_EN1 - This register is used to enable and disable receive request. +/*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47758,7 +44852,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U) -/*! REQ82_EN1 - This register is used to enable and disable transmit request. +/*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47766,7 +44860,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U) -/*! REQ83_EN1 - This register is used to enable and disable receive request. +/*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47774,7 +44868,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U) -/*! REQ84_EN1 - This register is used to enable and disable transmit request. +/*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47782,7 +44876,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_SHIFT (21U) -/*! REQ85_EN1 - This register is used to enable and disable receive request. +/*! REQ85_EN1 - This register is used to enable and disable LP_FLEXCOMM8 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47790,7 +44884,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_SHIFT (22U) -/*! REQ86_EN1 - This register is used to enable and disable transmit request. +/*! REQ86_EN1 - This register is used to enable and disable LP_FLEXCOMM8 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47798,7 +44892,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_SHIFT (23U) -/*! REQ87_EN1 - This register is used to enable and disable receive request. +/*! REQ87_EN1 - This register is used to enable and disable LP_FLEXCOMM9 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47806,31 +44900,15 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT (24U) -/*! REQ88_EN1 - This register is used to enable and disable transmit request. +/*! REQ88_EN1 - This register is used to enable and disable LP_FLEXCOMM9 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_MASK (0x2000000U) -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_SHIFT (25U) -/*! REQ89_EN1 - This register is used to enable and disable channel 0 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_MASK (0x4000000U) -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_SHIFT (26U) -/*! REQ90_EN1 - This register is used to enable and disable channel 1 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_SHIFT (27U) -/*! REQ91_EN1 - This register is used to enable and disable receive request. +/*! REQ91_EN1 - This register is used to enable and disable EMVSIM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47838,7 +44916,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_SHIFT (28U) -/*! REQ92_EN1 - This register is used to enable and disable transmit request. +/*! REQ92_EN1 - This register is used to enable and disable EMVSIM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47846,7 +44924,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_SHIFT (29U) -/*! REQ93_EN1 - This register is used to enable and disable receive request. +/*! REQ93_EN1 - This register is used to enable and disable EMVSIM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47854,7 +44932,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_SHIFT (30U) -/*! REQ94_EN1 - This register is used to enable and disable transmit request. +/*! REQ94_EN1 - This register is used to enable and disable EMVSIM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47862,7 +44940,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U) -/*! REQ95_EN1 - This register is used to enable and disable receive request. +/*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48366,7 +45444,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) -/*! REQ96_EN1 - This register is used to enable and disable transmit request. +/*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48374,7 +45452,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U) -/*! REQ97_EN1 - This register is used to enable and disable shift register 4 request. +/*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48382,7 +45460,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U) -/*! REQ98_EN1 - This register is used to enable and disable transmit request. +/*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48390,7 +45468,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U) -/*! REQ99_EN1 - This register is used to enable and disable shift register 6 request. +/*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48398,7 +45476,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U) -/*! REQ100_EN1 - This register is used to enable and disable transmit request. +/*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48406,7 +45484,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U) -/*! REQ101_EN1 - This register is used to enable and disable receive request. +/*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48414,7 +45492,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U) -/*! REQ102_EN1 - This register is used to enable and disable transmit request. +/*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48422,7 +45500,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_SHIFT (7U) -/*! REQ103_EN1 - This register is used to enable and disable ipd_req_sinc[0] or ipd_req_alt [0] request. +/*! REQ103_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request. * 0b0..Disable * 0b1..Enable */ @@ -48430,7 +45508,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_SHIFT (8U) -/*! REQ104_EN1 - This register is used to enable and disable ipd_req_sinc[1] or ipd_req_alt [1] request. +/*! REQ104_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request. * 0b0..Disable * 0b1..Enable */ @@ -48438,7 +45516,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_SHIFT (9U) -/*! REQ105_EN1 - This register is used to enable and disable ipd_req_sinc[2] or ipd_req_alt [2] request. +/*! REQ105_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request. * 0b0..Disable * 0b1..Enable */ @@ -48446,7 +45524,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_SHIFT (10U) -/*! REQ106_EN1 - This register is used to enable and disable ipd_req_sinc[3] or ipd_req_alt [3] request. +/*! REQ106_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request. * 0b0..Disable * 0b1..Enable */ @@ -48454,7 +45532,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_SHIFT (11U) -/*! REQ107_EN1 - This register is used to enable and disable ipd_req_sinc[4] or ipd_req_alt [4] request. +/*! REQ107_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request. * 0b0..Disable * 0b1..Enable */ @@ -48462,7 +45540,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U) -/*! REQ108_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48470,7 +45548,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U) -/*! REQ109_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48478,7 +45556,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U) -/*! REQ110_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48486,7 +45564,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U) -/*! REQ111_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48494,7 +45572,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U) -/*! REQ112_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48502,7 +45580,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U) -/*! REQ113_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48510,7 +45588,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U) -/*! REQ114_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48518,7 +45596,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U) -/*! REQ115_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48526,7 +45604,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U) -/*! REQ116_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48534,7 +45612,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U) -/*! REQ117_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48542,7 +45620,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U) -/*! REQ118_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48550,7 +45628,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U) -/*! REQ119_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48558,7 +45636,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_SHIFT (24U) -/*! REQ120_EN1 - This register is used to enable and disable end of scan request. +/*! REQ120_EN1 - This register is used to enable and disable TSI0 end of scan request. * 0b0..Disable * 0b1..Enable */ @@ -48566,7 +45644,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_SHIFT (25U) -/*! REQ121_EN1 - This register is used to enable and disable out of range request. +/*! REQ121_EN1 - This register is used to enable and disable TSI0 out of range request. * 0b0..Disable * 0b1..Enable */ @@ -49087,7 +46165,7 @@ typedef struct { #define ITRC_STATUS_IN3_STATUS_MASK (0x8U) #define ITRC_STATUS_IN3_STATUS_SHIFT (3U) -/*! IN3_STATUS - VDD_MAIN volt tamper output. +/*! IN3_STATUS - VBAT volt tamper output. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ @@ -49283,7 +46361,7 @@ typedef struct { #define ITRC_STATUS1_IN20_STATUS_MASK (0x10U) #define ITRC_STATUS1_IN20_STATUS_SHIFT (4U) -/*! IN20_STATUS - VDD_MAIN clock tamper output event occurred. +/*! IN20_STATUS - VBAT clock tamper output event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ @@ -49382,7 +46460,7 @@ typedef struct { #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U) -/*! IN3_SELn - Selects VDD_MAIN voltage tamper event as a trigger source. */ +/*! IN3_SELn - Selects VBAT voltage tamper event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U) @@ -49472,12 +46550,12 @@ typedef struct { #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U) -/*! IN19_SELn - Selects VDD_MAIN temperature tamper output event as a trigger source. */ +/*! IN19_SELn - Selects VBAT temperature tamper output event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U) -/*! IN20_SELn - Selects VDD_MAIN clock tamper output event as a trigger source. */ +/*! IN20_SELn - Selects VBAT clock tamper output event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U) @@ -49731,15 +46809,15 @@ typedef struct { #define LPCMP_CCR0_CMP_EN_MASK (0x1U) #define LPCMP_CCR0_CMP_EN_SHIFT (0U) /*! CMP_EN - Comparator Enable - * 0b0..Disables (The analog logic remains off and consumes no power.) - * 0b1..Enables + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable */ #define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) #define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) #define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) /*! CMP_STOP_EN - Comparator Deep sleep Mode Enable - * 0b0..Disable the analog comparator regardless of CMP_EN. + * 0b0..Disables the analog comparator regardless of CMP_EN. * 0b1..Allows CMP_EN to enable the analog comparator. */ #define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) @@ -49751,24 +46829,24 @@ typedef struct { #define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) #define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) /*! WINDOW_EN - Windowing Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) #define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) #define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) /*! SAMPLE_EN - Sampling Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) #define LPCMP_CCR1_DMA_EN_MASK (0x4U) #define LPCMP_CCR1_DMA_EN_SHIFT (2U) /*! DMA_EN - DMA Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) @@ -49889,10 +46967,10 @@ typedef struct { #define LPCMP_CCR2_HYSTCTR_MASK (0x30U) #define LPCMP_CCR2_HYSTCTR_SHIFT (4U) /*! HYSTCTR - Comparator Hysteresis Control - * 0b00..Level 0 - * 0b01..Level 1 - * 0b10..Level 2 - * 0b11..Level 3 + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. */ #define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) @@ -49931,24 +47009,24 @@ typedef struct { #define LPCMP_DCR_DAC_EN_MASK (0x1U) #define LPCMP_DCR_DAC_EN_SHIFT (0U) /*! DAC_EN - DAC Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) #define LPCMP_DCR_DAC_HPMD_MASK (0x2U) #define LPCMP_DCR_DAC_HPMD_SHIFT (1U) -/*! DAC_HPMD - DAC High Power Mode Select - * 0b0..Disables - * 0b1..Enables +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) #define LPCMP_DCR_VRSEL_MASK (0x100U) #define LPCMP_DCR_VRSEL_SHIFT (8U) /*! VRSEL - DAC Reference High Voltage Source Select - * 0b0..vrefh0 - * 0b1..vrefh1 + * 0b0..VREFH0 + * 0b1..VREFH1 */ #define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) @@ -50025,8 +47103,8 @@ typedef struct { #define LPCMP_RRCR0_RR_EN_MASK (0x1U) #define LPCMP_RRCR0_RR_EN_SHIFT (0U) /*! RR_EN - Round-Robin Enable - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) @@ -50040,7 +47118,7 @@ typedef struct { #define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU) #define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U) -/*! RR_EXTTRG_SEL - Select the External Trigger Source +/*! RR_EXTTRG_SEL - External Trigger Source Select * 0b0000..Select external trigger source 0 * 0b0001..Select external trigger source 1 * 0b0010..Select external trigger source 2 @@ -50139,64 +47217,64 @@ typedef struct { #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) #define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) /*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) #define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) #define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) /*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) #define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) #define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) /*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) #define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) #define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) /*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) #define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) #define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) /*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) #define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) #define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) /*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) #define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) #define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) /*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) #define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) #define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) /*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) @@ -50273,7 +47351,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH0F_MASK (0x1U) #define LPCMP_RRSR_RR_CH0F_SHIFT (0U) /*! RR_CH0F - Channel 0 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) @@ -50281,7 +47359,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH1F_MASK (0x2U) #define LPCMP_RRSR_RR_CH1F_SHIFT (1U) /*! RR_CH1F - Channel 1 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) @@ -50289,7 +47367,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH2F_MASK (0x4U) #define LPCMP_RRSR_RR_CH2F_SHIFT (2U) /*! RR_CH2F - Channel 2 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) @@ -50297,7 +47375,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH3F_MASK (0x8U) #define LPCMP_RRSR_RR_CH3F_SHIFT (3U) /*! RR_CH3F - Channel 3 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) @@ -50305,7 +47383,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH4F_MASK (0x10U) #define LPCMP_RRSR_RR_CH4F_SHIFT (4U) /*! RR_CH4F - Channel 4 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) @@ -50313,7 +47391,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH5F_MASK (0x20U) #define LPCMP_RRSR_RR_CH5F_SHIFT (5U) /*! RR_CH5F - Channel 5 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) @@ -50321,7 +47399,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH6F_MASK (0x40U) #define LPCMP_RRSR_RR_CH6F_SHIFT (6U) /*! RR_CH6F - Channel 6 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) @@ -50329,7 +47407,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH7F_MASK (0x80U) #define LPCMP_RRSR_RR_CH7F_SHIFT (7U) /*! RR_CH7F - Channel 7 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) @@ -50512,9 +47590,9 @@ typedef struct { #define LPDAC_GCR_DACRFS_MASK (0x6U) #define LPDAC_GCR_DACRFS_SHIFT (1U) /*! DACRFS - DAC Reference Select - * 0b00..Selects VREFH0 as the reference voltage - * 0b01..Selects VREFH1 as the reference voltage - * 0b10..Selects VREFH2 as the reference voltage + * 0b00..Selects VREFH0 as the reference voltage. + * 0b01..Selects VREFH1 as the reference voltage. + * 0b10..Selects VREFH2 as the reference voltage. * 0b11..Reserved. */ #define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) @@ -50522,7 +47600,7 @@ typedef struct { #define LPDAC_GCR_FIFOEN_MASK (0x8U) #define LPDAC_GCR_FIFOEN_SHIFT (3U) /*! FIFOEN - FIFO Enable - * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to goes to buffer then goes to conversion. + * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. */ #define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) @@ -50891,7 +47969,7 @@ typedef struct { uint8_t RESERVED_7[148]; __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ - __IO uint32_t SIER; /**< Target interrupt enable, offset: 0x118 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ @@ -50963,32 +48041,32 @@ typedef struct { #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Controller Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset - * 0b0..Not reset + * 0b0..No effect * 0b1..Reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) -/*! DOZEN - Doze mode enable - * 0b0..Controller is enabled in doze mode - * 0b1..Controller is disabled in doze mode +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable - * 0b0..Controller is disabled in debug mode - * 0b1..Controller is enabled in debug mode + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) @@ -50996,7 +48074,7 @@ typedef struct { #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect - * 0b1..Transmit FIFO is reset + * 0b1..Reset transmit FIFO */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) @@ -51004,7 +48082,7 @@ typedef struct { #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect - * 0b1..Receive FIFO is reset + * 0b1..Reset receive FIFO */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ @@ -51015,80 +48093,96 @@ typedef struct { #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag - * 0b0..Transmit data is not requested - * 0b1..Transmit data is requested + * 0b0..Transmit data not requested + * 0b1..Transmit data requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag - * 0b0..Receive data is not ready - * 0b1..Receive data is ready + * 0b0..Receive data not ready + * 0b1..Receive data ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag - * 0b0..Controller has not generated a STOP or Repeated START condition - * 0b1..Controller has generated a STOP or Repeated START condition + * 0b0..No Stop or repeated Start generated + * 0b1..Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) -/*! SDF - STOP Detect Flag - * 0b0..Controller has not generated a STOP condition - * 0b1..Controller has generated a STOP condition +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b1..Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag - * 0b0..Unexpected NACK was not detected - * 0b1..Unexpected NACK was detected + * 0b0..No unexpected NACK detected + * 0b1..Unexpected NACK detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag - * 0b0..Controller has not lost arbitration - * 0b1..Controller has lost arbitration + * 0b0..Controller did not lose arbitration + * 0b1..Controller lost arbitration + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag - * 0b0..No error - * 0b1..Controller sending or receiving data without a START condition + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag - * 0b0..Pin low timeout has not occurred or is disabled - * 0b1..Pin low timeout has occurred + * 0b0..Pin low timeout did not occur + * 0b1..Pin low timeout occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag - * 0b0..Have not received matching data - * 0b1..Have received matching data + * 0b0..Matching data not received + * 0b1..Matching data received + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_STF_MASK (0x8000U) #define LPI2C_MSR_STF_SHIFT (15U) -/*! STF - START Flag - * 0b0..START condition not detected. - * 0b1..START condition detected. +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b1..Start condition detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) @@ -51115,80 +48209,80 @@ typedef struct { #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) -/*! SDIE - STOP Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) #define LPI2C_MIER_STIE_MASK (0x8000U) #define LPI2C_MIER_STIE_SHIFT (15U) -/*! STIE - START Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) /*! @} */ @@ -51199,16 +48293,16 @@ typedef struct { #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ @@ -51218,15 +48312,15 @@ typedef struct { #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) -/*! HREN - Host request enable - * 0b0..Host request input is disabled - * 0b1..Host request input is enabled +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host request polarity +/*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ @@ -51234,7 +48328,7 @@ typedef struct { #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host request select +/*! HRSEL - Host Request Select * 0b0..Host request input is pin HREQ * 0b1..Host request input is input trigger */ @@ -51242,7 +48336,7 @@ typedef struct { #define LPI2C_MCFGR0_HRDIR_MASK (0x8U) #define LPI2C_MCFGR0_HRDIR_SHIFT (3U) -/*! HRDIR - Host request direction +/*! HRDIR - Host Request Direction * 0b0..HREQ pin is input (for LPI2C controller) * 0b1..HREQ pin is output (for LPI2C target) */ @@ -51250,17 +48344,17 @@ typedef struct { #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) -/*! CIRFIFO - Circular FIFO enable - * 0b0..Circular FIFO is disabled - * 0b1..Circular FIFO is enabled +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) -/*! RDMO - Receive data match only +/*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO - * 0b1..Received data is discarded unless the Data Match Flag (MSR[DMF]) is 1. + * 0b1..Received data is discarded unless MSR[DMF] is set */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) @@ -51276,7 +48370,7 @@ typedef struct { #define LPI2C_MCFGR0_ABORT_SHIFT (17U) /*! ABORT - Abort Transfer * 0b0..Normal transfer - * 0b1..Abort existing transfer and do not start new transfer + * 0b1..Abort existing transfer and do not start a new one */ #define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) /*! @} */ @@ -51300,9 +48394,9 @@ typedef struct { #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) -/*! AUTOSTOP - Automatic STOP Generation +/*! AUTOSTOP - Automatic Stop Generation * 0b0..No effect - * 0b1..STOP condition is automatically generated when the transmit FIFO is empty and the LPI2C controller is busy + * 0b1..Stop automatically generated */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) @@ -51310,34 +48404,31 @@ typedef struct { #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - Ignore NACK * 0b0..No effect - * 0b1..LPI2C controller treats a received NACK as if it (NACK) was an ACK and the NACK Detect Flag is never written 1. + * 0b1..Treat a received NACK as an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration - * 0b0..MSR[PLTF] becomes 1 if SCL is low for longer than the configured timeout. - * 0b1..MSR[PLTF] becomes 1 if either SCL or SDA is low for longer than the configured timeout. + * 0b0..SCL + * 0b1..SCL or SDA */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) #define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) -/*! STOPCFG - STOP Configuration - * 0b0..MSR[SDF] asserts on any STOP condition generated by LPI2C controller. - * 0b1..MSR[SDF] asserts on last STOP condition before LPI2C controller is idle (that is, the transmit FIFO is - * empty at the time of the STOP condition). +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition */ #define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) #define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) #define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) -/*! STARTCFG - START Configuration - * 0b0..MSR[STF] asserts on START condition provided both I2C bus and LPI2C controller are idle (that is, any - * non-repeated START condition initiated by any other controller on the bus but not the LPI2C controller). - * 0b1..MSR[STF] asserts on START condition provided I2C bus is idle (that is, any non-repeated START condition - * initiated by any controller on the bus including the LPI2C controller). +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle */ #define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) @@ -51346,12 +48437,12 @@ typedef struct { /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved - * 0b010..Match is enabled (first data word equals MDMR[MATCH0] OR MDMR[MATCH1]) - * 0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) - * 0b100..Match is enabled (first data word equals MDMR[MATCH0] AND second data word equals MDMR[MATCH1) - * 0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) - * 0b110..Match is enabled (first data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) - * 0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) @@ -51359,11 +48450,11 @@ typedef struct { #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..Two-pin open drain mode - * 0b001..Two-pin output only mode (ultra-fast mode) + * 0b001..Two-pin output only mode (Ultra-Fast mode) * 0b010..Two-pin push-pull mode * 0b011..Four-pin push-pull mode - * 0b100..Two-pin open drain mode with separate LPI2C target - * 0b101..Two-pin output only mode (ultra-fast mode) with separate LPI2C target + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target * 0b110..Two-pin push-pull mode with separate LPI2C target * 0b111..Four-pin push-pull mode (inverted outputs) */ @@ -51394,7 +48485,7 @@ typedef struct { #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) -/*! PINLOW - Pin low timeout */ +/*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ @@ -51499,14 +48590,14 @@ typedef struct { #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data - * 0b000..Transmit DATA[7:0] + * 0b000..Transmit the value in DATA[7:0] * 0b001..Receive (DATA[7:0] + 1) bytes - * 0b010..Generate STOP condition + * 0b010..Generate Stop condition on I2C bus * 0b011..Receive and discard (DATA[7:0] + 1) bytes - * 0b100..Generate (repeated) START and transmit address in DATA[7:0] - * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. - * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode - * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode. This transfer expects a NACK to be returned. + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ @@ -51522,8 +48613,8 @@ typedef struct { #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty - * 0b0..Receive FIFO is not empty - * 0b1..Receive FIFO is empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ @@ -51539,8 +48630,8 @@ typedef struct { #define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty - * 0b0..Receive FIFO is not empty - * 0b1..Receive FIFO is empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) /*! @} */ @@ -51551,40 +48642,40 @@ typedef struct { #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Target Enable - * 0b0..I2C Target mode is disabled - * 0b1..I2C Target mode is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) -/*! RST - Software reset - * 0b0..Target mode logic is not reset - * 0b1..Target mode logic is reset +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) -/*! FILTEN - Filter enable - * 0b0..Disable digital filter and output delay counter for target mode - * 0b1..Enable digital filter and output delay counter for target mode +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) -/*! FILTDZ - Filter doze enable - * 0b0..Filter remains enabled in Doze mode - * 0b1..Filter is disabled in Doze mode +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) -/*! RTF - Reset transmit FIFO +/*! RTF - Reset Transmit FIFO * 0b0..No effect - * 0b1..Transmit Data Register is now empty. + * 0b1..STDR is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) @@ -51592,7 +48683,7 @@ typedef struct { #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect - * 0b1..Receive Data Register is now empty. + * 0b1..SRDR is now empty */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ @@ -51602,7 +48693,7 @@ typedef struct { #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) -/*! TDF - Transmit data flag +/*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ @@ -51610,63 +48701,71 @@ typedef struct { #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) -/*! RDF - Receive data flag - * 0b0..Receive data is not ready - * 0b1..Receive data is ready +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) -/*! AVF - Address valid flag - * 0b0..Address Status Register is not valid - * 0b1..Address Status Register is valid +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) -/*! TAF - Transmit ACK flag - * 0b0..Transmit ACK/NACK is not required - * 0b1..Transmit ACK/NACK is required +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) -/*! RSF - Repeated start flag - * 0b0..Target has not detected a Repeated START condition - * 0b1..Target has detected a Repeated START condition +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b1..Repeated Start detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) -/*! SDF - STOP detect flag - * 0b0..Target has not detected a STOP condition - * 0b1..Target has detected a STOP condition +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b1..Stop detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) -/*! BEF - Bit error flag - * 0b0..Target has not detected a bit error - * 0b1..Target has detected a bit error +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b1..Bit error occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) -/*! FEF - FIFO error flag - * 0b0..FIFO underflow or overflow was not detected - * 0b1..FIFO underflow or overflow was detected +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) -/*! AM0F - Address match 0 flag +/*! AM0F - Address Match 0 Flag * 0b0..ADDR0 matching address not received * 0b1..ADDR0 matching address received */ @@ -51674,31 +48773,31 @@ typedef struct { #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) -/*! AM1F - Address match 1 flag - * 0b0..ADDR1 or ADDR0/ADDR1 range matching address not received - * 0b1..ADDR1 or ADDR0/ADDR1 range matching address received +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) -/*! GCF - General call flag - * 0b0..Target has not detected the General Call Address or the General Call Address is disabled - * 0b1..Target has detected the General Call Address +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) -/*! SARF - SMBus alert response flag - * 0b0..SMBus alert response is disabled or not detected - * 0b1..SMBus alert response is enabled and detected +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) -/*! SBF - Target busy flag +/*! SBF - Target Busy Flag * 0b0..Idle * 0b1..Busy */ @@ -51706,99 +48805,99 @@ typedef struct { #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) -/*! BBF - Bus busy flag +/*! BBF - Bus Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ -/*! @name SIER - Target interrupt enable */ +/*! @name SIER - Target Interrupt Enable */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) -/*! TDIE - Transmit data interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) -/*! RDIE - Receive data interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) -/*! AVIE - Address valid interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) -/*! TAIE - Transmit ACK interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) -/*! RSIE - Repeated start interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) -/*! SDIE - STOP detect interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) -/*! BEIE - Bit error interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) -/*! FEIE - FIFO error interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) -/*! AM0IE - Address match 0 interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1IE_MASK (0x2000U) #define LPI2C_SIER_AM1IE_SHIFT (13U) -/*! AM1IE - Address match 1 interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) -/*! GCIE - General call interrupt enable +/*! GCIE - General Call Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ @@ -51806,9 +48905,9 @@ typedef struct { #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) -/*! SARIE - SMBus alert response interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ @@ -51818,41 +48917,41 @@ typedef struct { #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) -/*! TDDE - Transmit data DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) -/*! RDDE - Receive data DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) -/*! AVDE - Address valid DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) #define LPI2C_SDER_RSDE_MASK (0x100U) #define LPI2C_SDER_RSDE_SHIFT (8U) -/*! RSDE - Repeated start DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) #define LPI2C_SDER_SDDE_MASK (0x200U) #define LPI2C_SDER_SDDE_SHIFT (9U) -/*! SDDE - Stop detect DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) /*! @} */ @@ -51863,14 +48962,14 @@ typedef struct { #define LPI2C_SCFGR0_RDREQ_MASK (0x1U) #define LPI2C_SCFGR0_RDREQ_SHIFT (0U) /*! RDREQ - Read Request - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) #define LPI2C_SCFGR0_RDACK_MASK (0x2U) #define LPI2C_SCFGR0_RDACK_SHIFT (1U) -/*! RDACK - Read Acknowledge +/*! RDACK - Read Acknowledge Flag * 0b0..Read Request not acknowledged * 0b1..Read Request acknowledged */ @@ -51882,89 +48981,87 @@ typedef struct { #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) -/*! ADRSTALL - Address SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) -/*! RXSTALL - RX SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) -/*! TXDSTALL - Transmit data SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) -/*! ACKSTALL - ACK SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_RXNACK_MASK (0x10U) #define LPI2C_SCFGR1_RXNACK_SHIFT (4U) /*! RXNACK - Receive NACK - * 0b0..ACK/NACK always written 1 by TXNACK - * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK/NACK is written 1 by TXNACK. + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] */ #define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) -/*! GCEN - General call enable - * 0b0..General Call address is disabled - * 0b1..General Call address is enabled +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) -/*! SAEN - SMBus alert enable - * 0b0..Disables match on SMBus Alert - * 0b1..Enables match on SMBus Alert +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) -/*! TXCFG - Transmit flag configuration - * 0b0..MSR[TDF] becomes 1 only during a target-transmit transfer when the Transmit Data register is empty - * 0b1..MSR[TDF] becomes 1 whenever the Transmit Data register is empty +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration - * 0b0..Reading the Receive Data register returns received data and writes 0 to the Receive Data flag. - * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is 1, returns the Address Status - * register and writes 0 to SSR[AVF]. Reading the Receive Data register when SSR[AVF] is 0, returns received - * data and writes 0 to the Receive Data flag (MSR[RDF]). + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK - * 0b0..Target ends transfer when NACK is detected - * 0b1..Target does not end transfer when NACK detected + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) -/*! HSMEN - High-speed mode enable +/*! HSMEN - HS Mode Enable * 0b0..Disable * 0b1..Enable */ @@ -51972,39 +49069,39 @@ typedef struct { #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) -/*! ADDRCFG - Address configuration +/*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit) * 0b001..Address match 0 (10-bit) - * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) - * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) - * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) - * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) - * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) - * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) #define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) #define LPI2C_SCFGR1_RXALL_SHIFT (24U) -/*! RXALL - Receive all - * 0b0..Receive all disabled - * 0b1..Receive all enabled +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) #define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) #define LPI2C_SCFGR1_RSCFG_SHIFT (25U) -/*! RSCFG - Repeated start configuration - * 0b0..Any repeated START condition following an address match - * 0b1..Any repeated START condition +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition */ #define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) #define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) #define LPI2C_SCFGR1_SDCFG_SHIFT (26U) /*! SDCFG - Stop Detect Configuration - * 0b0..Any STOP condition following an address match - * 0b1..Any STOP condition + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition */ #define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) /*! @} */ @@ -52014,22 +49111,22 @@ typedef struct { #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) -/*! CLKHOLD - Clock hold time */ +/*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) -/*! DATAVD - Data valid delay */ +/*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) -/*! FILTSCL - Glitch filter SCL */ +/*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) -/*! FILTSDA - Glitch filter SDA */ +/*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ @@ -52038,12 +49135,12 @@ typedef struct { #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) -/*! ADDR0 - Address 0 value */ +/*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) -/*! ADDR1 - Address 1 value */ +/*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ @@ -52057,9 +49154,9 @@ typedef struct { #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) -/*! ANV - Address not valid - * 0b0..Received Address (RADDR) is valid - * 0b1..Received Address (RADDR) is not valid +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ @@ -52070,8 +49167,8 @@ typedef struct { #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK - * 0b0..Write a Transmit ACK for each received word - * 0b1..Write a Transmit NACK for each received word + * 0b0..Transmit ACK + * 0b1..Transmit NACK */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ @@ -52081,7 +49178,7 @@ typedef struct { #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) -/*! DATA - Transmit data */ +/*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ @@ -52090,27 +49187,27 @@ typedef struct { #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) -/*! DATA - Receive data */ +/*! DATA - Received Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RADDR_MASK (0x700U) #define LPI2C_SRDR_RADDR_SHIFT (8U) -/*! RADDR - Received address */ +/*! RADDR - Received Address */ #define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - Receive empty - * 0b0..The Receive Data Register is not empty - * 0b1..The Receive Data Register is empty +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) -/*! SOF - Start of frame - * 0b0..Not the first data word since a (repeated) START or STOP condition - * 0b1..Is the first data word since a (repeated) START or STOP condition +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ @@ -52120,27 +49217,27 @@ typedef struct { #define LPI2C_SRDROR_DATA_MASK (0xFFU) #define LPI2C_SRDROR_DATA_SHIFT (0U) -/*! DATA - Receive data */ +/*! DATA - Receive Data */ #define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) #define LPI2C_SRDROR_RADDR_MASK (0x700U) #define LPI2C_SRDROR_RADDR_SHIFT (8U) -/*! RADDR - Received address */ +/*! RADDR - Received Address */ #define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) #define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - Receive empty - * 0b0..The Receive Data Register is not empty - * 0b1..The Receive Data Register is empty +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) #define LPI2C_SRDROR_SOF_MASK (0x8000U) #define LPI2C_SRDROR_SOF_SHIFT (15U) -/*! SOF - Start of frame - * 0b0..Is not the first data word since a (repeated) START or STOP condition - * 0b1..Is the first data word since a (repeated) START or STOP condition +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First */ #define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) /*! @} */ @@ -52481,7 +49578,7 @@ typedef struct { #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested - * 0b1..Transmit data is requested + * 0b1..Transmit data requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) @@ -52489,7 +49586,7 @@ typedef struct { #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data not ready - * 0b1..Receive data is ready + * 0b1..Receive data ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) @@ -52498,6 +49595,8 @@ typedef struct { /*! WCF - Word Complete Flag * 0b0..Not complete * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) @@ -52506,6 +49605,8 @@ typedef struct { /*! FCF - Frame Complete Flag * 0b0..Not complete * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) @@ -52514,6 +49615,8 @@ typedef struct { /*! TCF - Transfer Complete Flag * 0b0..Not complete * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) @@ -52522,6 +49625,8 @@ typedef struct { /*! TEF - Transmit Error Flag * 0b0..No underrun * 0b1..Underrun + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) @@ -52530,6 +49635,8 @@ typedef struct { /*! REF - Receive Error Flag * 0b0..No overflow * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) @@ -52538,6 +49645,8 @@ typedef struct { /*! DMF - Data Match Flag * 0b0..No match * 0b1..Match + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) @@ -52743,7 +49852,10 @@ typedef struct { #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) -/*! PCSPOL - Peripheral Chip Select Polarity */ +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) @@ -52763,26 +49875,26 @@ typedef struct { #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration - * 0b00..SIN is used for input data; SOUT is used for output data. - * 0b01..SIN is used for both input and output data. Only half-duplex serial transfers are supported. - * 0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are supported. - * 0b11..SOUT is used for input data; SIN is used for output data. + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration - * 0b0..Output data retains last value. - * 0b1..Output data is 3-stated. + * 0b0..Retain last value + * 0b1..3-stated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration - * 0b0..PCS[3:2] are configured for chip select function - * 0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ @@ -52844,7 +49956,7 @@ typedef struct { #define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) #define LPSPI_CCR1_PCSPCS_SHIFT (16U) -/*! PCSPCS - PCS to PCS delay */ +/*! PCSPCS - PCS to PCS Delay */ #define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) #define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) @@ -52911,7 +50023,7 @@ typedef struct { #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer - * 0b1..Receive data is masked + * 0b1..Mask receive data */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) @@ -52926,24 +50038,24 @@ typedef struct { #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer - * 0b0..Continuous transfer is disabled - * 0b1..Continuous transfer is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable byte swap + * 0b1..Enable byte swap */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First - * 0b0..Data is transferred MSB first - * 0b1..Data is transferred LSB first + * 0b0..MSB first + * 0b1..LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) @@ -53002,7 +50114,7 @@ typedef struct { #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) -/*! SOF - Start Of Frame +/*! SOF - Start of Frame * 0b0..Subsequent data word * 0b1..First data word */ @@ -53230,7 +50342,7 @@ typedef struct { /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ - __IO uint32_t PSR; /**< Prescale and Glitch Filter, offset: 0x4 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ __IO uint32_t CMR; /**< Compare, offset: 0x8 */ __IO uint32_t CNR; /**< Counter, offset: 0xC */ } LPTMR_Type; @@ -53258,15 +50370,15 @@ typedef struct { #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) /*! TMS - Timer Mode Select - * 0b0..Time Counter mode - * 0b1..Pulse Counter mode + * 0b0..Time Counter + * 0b1..Pulse Counter */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) /*! TFC - Timer Free-Running Counter - * 0b0..Reset if TCF set + * 0b0..Reset when TCF asserts * 0b1..Reset on overflow */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) @@ -53302,6 +50414,8 @@ typedef struct { /*! TCF - Timer Compare Flag * 0b0..CNR != (CMR + 1) * 0b1..CNR = (CMR + 1) + * 0b0..No effect + * 0b1..Clear the flag */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) @@ -53314,12 +50428,12 @@ typedef struct { #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) /*! @} */ -/*! @name PSR - Prescale and Glitch Filter */ +/*! @name PSR - Prescaler and Glitch Filter */ /*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) -/*! PCS - Prescaler/Glitch Filter Clock Select +/*! PCS - Prescaler and Glitch Filter Clock Select * 0b00..Clock 0 * 0b01..Clock 1 * 0b10..Clock 2 @@ -53329,31 +50443,31 @@ typedef struct { #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) -/*! PBYP - Prescaler/Glitch Filter Bypass - * 0b0..Prescaler/glitch filter enable - * 0b1..Prescaler/glitch filter bypass +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) -/*! PRESCALE - Prescale/Glitch Filter Value - * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. - * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. - * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. - * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. - * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. - * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. - * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. - * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. - * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. - * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. - * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. - * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. - * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. - * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. - * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. - * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @} */ @@ -53560,72 +50674,72 @@ typedef struct { #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable - * 0b0..Disables hardware interrupts from STAT[RXEDGIF] - * 0b1..Requests hardware interrupts when STAT[RXEDGIF] is 1 + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable - * 0b0..Disables hardware interrupts from STAT[LBKDIF] (uses polling) - * 0b1..Requests hardware interrupt when STAT[LBKDIF] is 1 + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable - * 0b0..Enables resynchronization - * 0b1..Disables resynchronization + * 0b0..Enable + * 0b1..Disable */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling - * 0b0..Receiver samples input data using the rising edge of the baud rate clock - * 0b1..Receiver samples input data using the rising and falling edges of the baud rate clock + * 0b0..Rising edge + * 0b1..Both rising and falling edges */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration - * 0b00..Address match wakeup - * 0b01..Idle match wakeup + * 0b00..Address match wake-up + * 0b01..Idle match wake-up * 0b10..Match on and match off - * 0b11..Enables RWU on data match and match on/off for the transmitter CTS input + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable - * 0b0..DMA request disabled - * 0b1..DMA request enabled + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable - * 0b0..Disables DMA request - * 0b1..Enables DMA request + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable - * 0b0..Disables DMA request - * 0b1..Enables DMA request + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) -/*! OSR - Oversampling Ratio (OSR) +/*! OSR - Oversampling Ratio * 0b00000..Results in an OSR of 16 * 0b00001..Reserved * 0b00010..Reserved @@ -53672,16 +50786,16 @@ typedef struct { #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ @@ -53692,16 +50806,16 @@ typedef struct { #define LPUART_STAT_LBKFE_MASK (0x1U) #define LPUART_STAT_LBKFE_SHIFT (0U) /*! LBKFE - LIN Break Flag Enable - * 0b0..Disables LIN break detect - * 0b1..Enables LIN break detect + * 0b0..Disable + * 0b1..Enable */ #define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) #define LPUART_STAT_AME_MASK (0x2U) #define LPUART_STAT_AME_SHIFT (1U) /*! AME - Address Mark Enable - * 0b0..Address mark in character is MSB - * 0b1..Address mark in character is the last bit before the stop bit (or parity bit when enabled) + * 0b0..Disable + * 0b1..Enable */ #define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) @@ -53726,6 +50840,8 @@ typedef struct { /*! MA2F - Match 2 Flag * 0b0..Not equal to MA2 * 0b1..Equal to MA2 + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) @@ -53734,30 +50850,38 @@ typedef struct { /*! MA1F - Match 1 Flag * 0b0..Not equal to MA1 * 0b1..Equal to MA1 + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) -/*! PF - Parity Error Flag (PF) +/*! PF - Parity Error Flag * 0b0..No parity error detected * 0b1..Parity error detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) -/*! FE - Framing Error Flag (FE) +/*! FE - Framing Error Flag * 0b0..No framing error detected (this does not guarantee that the framing is correct) * 0b1..Framing error detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) -/*! NF - Noise Flag (NF) +/*! NF - Noise Flag * 0b0..No noise detected * 0b1..Noise detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) @@ -53765,15 +50889,19 @@ typedef struct { #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun - * 0b1..Receive overrun (new LPUART data lost) + * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag - * 0b0..No idle line detected - * 0b1..Idle line detected + * 0b0..Idle line detected + * 0b1..Idle line not detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) @@ -53788,8 +50916,8 @@ typedef struct { #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag - * 0b0..Transmitter active (sending data, a preamble, or a break) - * 0b1..Transmitter idle (transmission activity complete) + * 0b0..Transmitter active + * 0b1..Transmitter idle */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) @@ -53812,8 +50940,8 @@ typedef struct { #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) @@ -53854,6 +50982,8 @@ typedef struct { /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag * 0b0..Not occurred * 0b1..Occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) @@ -53862,6 +50992,8 @@ typedef struct { /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..Not detected * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ @@ -53880,8 +51012,8 @@ typedef struct { #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) @@ -53895,17 +51027,17 @@ typedef struct { #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) -/*! WAKE - Receiver Wakeup Method Select - * 0b0..Configures CTRL[RWU] for idle-line wakeup - * 0b1..Configures CTRL[RWU] with address-mark wakeup +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit Or 8-Bit Mode Select - * 0b0..8-bit data characters - * 0b1..9-bit data characters + * 0b0..8-bit + * 0b1..9-bit */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) @@ -53919,9 +51051,9 @@ typedef struct { #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) -/*! DOZEEN - Enables LPUART in Doze mode. - * 0b0..Enables - * 0b1..Disables +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) @@ -53950,24 +51082,24 @@ typedef struct { #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select - * 0b0..8-bit to 10-bit data characters - * 0b1..7-bit data characters + * 0b0..8-bit to 10-bit + * 0b1..7-bit */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 (MA2F) Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 (MA1F) Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) @@ -53981,89 +51113,89 @@ typedef struct { #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) -/*! RWU - Receiver Wakeup Control +/*! RWU - Receiver Wake-Up Control * 0b0..Normal receiver operation - * 0b1..LPUART receiver in standby, waiting for a wakeup condition + * 0b1..LPUART receiver in standby, waiting for a wake-up condition */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable - * 0b0..Disables hardware interrupts from STAT[IDLE]; use polling - * 0b1..Enables hardware interrupts when STAT[IDLE] = 1 + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) @@ -54078,8 +51210,8 @@ typedef struct { #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode - * 0b0..TXD pin is an input in Single-Wire mode - * 0b1..TXD pin is an output in Single-Wire mode + * 0b0..Input + * 0b1..Output */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) @@ -54099,75 +51231,75 @@ typedef struct { #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) -/*! R0T0 - Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0 */ +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) -/*! R1T1 - Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1 */ +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) -/*! R2T2 - Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2 */ +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) -/*! R3T3 - Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3 */ +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) -/*! R4T4 - Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4 */ +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) -/*! R5T5 - Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5 */ +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) -/*! R6T6 - Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6 */ +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) -/*! R7T7 - Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7 */ +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) -/*! R8T8 - Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8 */ +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) -/*! R9T9 - Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9 */ +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_LINBRK_MASK (0x400U) #define LPUART_DATA_LINBRK_SHIFT (10U) /*! LINBRK - LIN Break - * 0b0..LIN break not detected or LIN break detect circuitry disabled - * 0b1..LIN break detected + * 0b0..Not detected + * 0b1..Detected */ #define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line - * 0b0..Received was not idle - * 0b1..Receiver was idle + * 0b0..Not idle + * 0b1..Idle */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty - * 0b0..Contains valid data - * 0b1..Contains invalid data and is empty + * 0b0..Valid data + * 0b1..Invalid data and empty */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) @@ -54216,32 +51348,32 @@ typedef struct { #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter CTS Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter RTS Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter RTS Polarity - * 0b0..Transmitter RTS is active low - * 0b1..Transmitter RTS is active high + * 0b0..Active low + * 0b1..Active high */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver RTS Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) @@ -54279,8 +51411,8 @@ typedef struct { #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - IR Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ @@ -54291,74 +51423,74 @@ typedef struct { #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth - * 0b000..Receive FIFO buffer depth = 1 dataword - * 0b001..Receive FIFO buffer depth = 4 datawords - * 0b010..Receive FIFO buffer depth = 8 datawords - * 0b011..Receive FIFO buffer depth = 16 datawords - * 0b100..Receive FIFO buffer depth = 32 datawords - * 0b101..Receive FIFO buffer depth = 64 datawords - * 0b110..Receive FIFO buffer depth = 128 datawords - * 0b111..Receive FIFO buffer depth = 256 datawords + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable - * 0b0..Disables; buffer depth is 1 - * 0b1..Enables; FIFO[RXFIFOSIZE] indicates the buffer depth + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth - * 0b000..Transmit FIFO buffer depth = 1 dataword - * 0b001..Transmit FIFO buffer depth = 4 datawords - * 0b010..Transmit FIFO buffer depth = 8 datawords - * 0b011..Transmit FIFO buffer depth = 16 datawords - * 0b100..Transmit FIFO buffer depth = 32 datawords - * 0b101..Transmit FIFO buffer depth = 64 datawords - * 0b110..Transmit FIFO buffer depth = 128 datawords - * 0b111..Transmit FIFO buffer depth = 256 datawords + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable - * 0b0..Disables; buffer depth is 1 - * 0b1..Enables; FIFO[TXFIFOSIZE] indicates the buffer depth + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable - * 0b000..Disables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle - * 0b001..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character - * 0b010..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters - * 0b011..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters - * 0b100..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters - * 0b101..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters - * 0b110..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters - * 0b111..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) @@ -54366,7 +51498,7 @@ typedef struct { #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO Flush * 0b0..No effect - * 0b1..All data is flushed out + * 0b1..All data flushed out */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) @@ -54374,7 +51506,7 @@ typedef struct { #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO Flush * 0b0..No effect - * 0b1..All data is flushed out + * 0b1..All data flushed out */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) @@ -54383,6 +51515,8 @@ typedef struct { /*! RXUF - Receiver FIFO Underflow Flag * 0b0..No underflow * 0b1..Underflow + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) @@ -54391,6 +51525,8 @@ typedef struct { /*! TXOF - Transmitter FIFO Overflow Flag * 0b0..No overflow * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) @@ -54450,48 +51586,48 @@ typedef struct { #define LPUART_MCR_CTS_MASK (0x1U) #define LPUART_MCR_CTS_SHIFT (0U) /*! CTS - Clear To Send - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) #define LPUART_MCR_DSR_MASK (0x2U) #define LPUART_MCR_DSR_SHIFT (1U) /*! DSR - Data Set Ready - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) #define LPUART_MCR_RIN_MASK (0x4U) #define LPUART_MCR_RIN_SHIFT (2U) /*! RIN - Ring Indicator - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) #define LPUART_MCR_DCD_MASK (0x8U) #define LPUART_MCR_DCD_SHIFT (3U) /*! DCD - Data Carrier Detect - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) #define LPUART_MCR_DTR_MASK (0x100U) #define LPUART_MCR_DTR_SHIFT (8U) /*! DTR - Data Terminal Ready - * 0b0..Default state is logic one - * 0b1..Default state is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) #define LPUART_MCR_RTS_MASK (0x200U) #define LPUART_MCR_RTS_SHIFT (9U) /*! RTS - Request To Send - * 0b0..Default state is logic one - * 0b1..Default state is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) /*! @} */ @@ -54504,6 +51640,8 @@ typedef struct { /*! DCTS - Delta Clear To Send * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) @@ -54512,6 +51650,8 @@ typedef struct { /*! DDSR - Delta Data Set Ready * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) @@ -54520,6 +51660,8 @@ typedef struct { /*! DRI - Delta Ring Indicator * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) @@ -54528,38 +51670,40 @@ typedef struct { /*! DDCD - Delta Data Carrier Detect * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) #define LPUART_MSR_CTS_MASK (0x10U) #define LPUART_MSR_CTS_SHIFT (4U) /*! CTS - Clear To Send - * 0b0..The CTS_B pin is logic one - * 0b1..The CTS_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) #define LPUART_MSR_DSR_MASK (0x20U) #define LPUART_MSR_DSR_SHIFT (5U) /*! DSR - Data Set Ready - * 0b0..The DSR_B pin is logic one - * 0b1..The DSR_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) #define LPUART_MSR_RIN_MASK (0x40U) #define LPUART_MSR_RIN_SHIFT (6U) /*! RIN - Ring Indicator - * 0b0..The RIN_B pin is logic one - * 0b1..The RIN_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) #define LPUART_MSR_DCD_MASK (0x80U) #define LPUART_MSR_DCD_SHIFT (7U) /*! DCD - Data Carrier Detect - * 0b0..The DCD_B pin is logic one - * 0b1..The DCD_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) /*! @} */ @@ -54604,16 +51748,16 @@ typedef struct { #define LPUART_HDCR_RXWRMSK_MASK (0x4U) #define LPUART_HDCR_RXWRMSK_SHIFT (2U) /*! RXWRMSK - Receive FIFO Write Mask - * 0b0..Does not mask - * 0b1..Masks + * 0b0..Do not mask + * 0b1..Mask */ #define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) #define LPUART_HDCR_RXMSK_MASK (0x8U) #define LPUART_HDCR_RXMSK_SHIFT (3U) /*! RXMSK - Receive Mask - * 0b0..Does not mask - * 0b1..Masks + * 0b0..Do not mask + * 0b1..Mask */ #define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) @@ -54647,7 +51791,12 @@ typedef struct { #define LPUART_TOSR_TOF_MASK (0xF00U) #define LPUART_TOSR_TOF_SHIFT (8U) -/*! TOF - Timeout Flag */ +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0001..Occurred + * 0b0000..No effect + * 0b0001..Clear the flag + */ #define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) /*! @} */ @@ -55146,9 +52295,9 @@ typedef struct { /** MAILBOX - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Cortex_M33 (CPU0) Interrupt..Cortex_M33 (CPU1) Interrupt, array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Cortex_M33 (CPU0) Interrupt Set..Cortex_M33 (CPU1) Interrupt Set, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Cortex_M33 (CPU0) Interrupt Clear..Cortex_M33 (CPU1) Interrupt Clear, array offset: 0x8, array step: 0x10 */ + __IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt, array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear, array offset: 0x8, array step: 0x10 */ uint8_t RESERVED_0[4]; } MBOXIRQ[2]; uint8_t RESERVED_0[216]; @@ -55164,7 +52313,7 @@ typedef struct { * @{ */ -/*! @name MBOXIRQ_IRQ - Cortex_M33 (CPU0) Interrupt..Cortex_M33 (CPU1) Interrupt */ +/*! @name MBOXIRQ_IRQ - Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) @@ -55176,7 +52325,7 @@ typedef struct { /* The count of MAILBOX_MBOXIRQ_IRQ */ #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) -/*! @name MBOXIRQ_IRQSET - Cortex_M33 (CPU0) Interrupt Set..Cortex_M33 (CPU1) Interrupt Set */ +/*! @name MBOXIRQ_IRQSET - Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) @@ -55188,7 +52337,7 @@ typedef struct { /* The count of MAILBOX_MBOXIRQ_IRQSET */ #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) -/*! @name MBOXIRQ_IRQCLR - Cortex_M33 (CPU0) Interrupt Clear..Cortex_M33 (CPU1) Interrupt Clear */ +/*! @name MBOXIRQ_IRQCLR - Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) @@ -55252,3592 +52401,6 @@ typedef struct { */ /* end of group MAILBOX_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- MBC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MBC_Peripheral_Access_Layer MBC Peripheral Access Layer - * @{ - */ - -/** MBC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4096]; - __IO uint32_t MBC0_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x1000, array step: 0x4 */ - __IO uint32_t MBC0_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, offset: 0x1010 */ - __O uint32_t MBC0_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, offset: 0x1014 */ - __O uint32_t MBC0_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, offset: 0x1018 */ - __O uint32_t MBC0_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, offset: 0x101C */ - __IO uint32_t MBC0_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x1020, array step: 0x4 */ - struct { /* offset: 0x1040, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x1040, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W1; /**< MBC Memory Block Configuration Word, array offset: 0x1044, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W2; /**< MBC Memory Block Configuration Word, array offset: 0x1048, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W3; /**< MBC Memory Block Configuration Word, array offset: 0x104C, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W4; /**< MBC Memory Block Configuration Word, array offset: 0x1050, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W5; /**< MBC Memory Block Configuration Word, array offset: 0x1054, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W6; /**< MBC Memory Block Configuration Word, array offset: 0x1058, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W7; /**< MBC Memory Block Configuration Word, array offset: 0x105C, array step: 0x18C */ - uint8_t RESERVED_0[224]; - __IO uint32_t MBC0_DOM_MEM0_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1140, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_NSE_W1; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1144, array step: 0x18C */ - uint8_t RESERVED_1[56]; - __IO uint32_t MBC0_DOM_MEM1_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x1180, array step: 0x18C */ - uint8_t RESERVED_2[28]; - __IO uint32_t MBC0_DOM_MEM1_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11A0, array step: 0x18C */ - uint8_t RESERVED_3[4]; - __IO uint32_t MBC0_DOM_MEM2_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x11A8, array step: 0x18C */ - uint8_t RESERVED_4[28]; - __IO uint32_t MBC0_DOM_MEM2_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11C8, array step: 0x18C */ - } MBC_DOM0[1]; -} MBC_Type; - -/* ---------------------------------------------------------------------------- - -- MBC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MBC_Register_Masks MBC Register Masks - * @{ - */ - -/*! @name MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG - MBC Global Configuration Register */ -/*! @{ */ - -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_MASK (0x3FFU) -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_SHIFT (0U) -/*! NBLKS - Number of blocks in this memory */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_MASK) - -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) -/*! SIZE_LOG2 - Log2 size per block */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_MASK) - -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_MASK (0xC0000000U) -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_SHIFT (30U) -/*! CLRE - Clear Error */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_MASK) -/*! @} */ - -/* The count of MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_COUNT (4U) - -/*! @name MBC0_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_INDEX_WNDX_MASK (0x3CU) -#define MBC_MBC0_NSE_BLK_INDEX_WNDX_SHIFT (2U) -/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ -#define MBC_MBC0_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_WNDX_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_WNDX_MASK) - -#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) -#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) -/*! MEM_SEL - Memory Select */ -#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_MASK) - -#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) -#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) -/*! DID_SEL0 - DID Select - * 0b0..No effect. - * 0b1..Selects NSE bits for this domain. - */ -#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_MASK) - -#define MBC_MBC0_NSE_BLK_INDEX_AI_MASK (0x80000000U) -#define MBC_MBC0_NSE_BLK_INDEX_AI_SHIFT (31U) -/*! AI - Auto Increment - * 0b0..No effect. - * 0b1..Add 1 to the WNDX field after the register write. - */ -#define MBC_MBC0_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_AI_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_AI_MASK) -/*! @} */ - -/*! @name MBC0_NSE_BLK_SET - MBC NonSecure Enable Block Set */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) -#define MBC_MBC0_NSE_BLK_SET_W1SET_SHIFT (0U) -/*! W1SET - Write-1 Set */ -#define MBC_MBC0_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_SET_W1SET_SHIFT)) & MBC_MBC0_NSE_BLK_SET_W1SET_MASK) -/*! @} */ - -/*! @name MBC0_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) -#define MBC_MBC0_NSE_BLK_CLR_W1CLR_SHIFT (0U) -/*! W1CLR - Write-1 Clear */ -#define MBC_MBC0_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_W1CLR_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_W1CLR_MASK) -/*! @} */ - -/*! @name MBC0_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) -#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) -/*! MEMSEL - Memory Select */ -#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_MASK) - -#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) -#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) -/*! DID_SEL0 - DID Select - * 0b0..No effect. - * 0b1..Clear all NSE bits for this domain. - */ -#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_MASK) -/*! @} */ - -/*! @name MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC - MBC Global Access Control */ -/*! @{ */ - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_MASK (0x1U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_SHIFT (0U) -/*! NUX - NonsecureUser Execute - * 0b0..Execute access is not allowed in Nonsecure User mode. - * 0b1..Execute access is allowed in Nonsecure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_MASK (0x2U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_SHIFT (1U) -/*! NUW - NonsecureUser Write - * 0b0..Write access is not allowed in Nonsecure User mode. - * 0b1..Write access is allowed in Nonsecure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_MASK (0x4U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_SHIFT (2U) -/*! NUR - NonsecureUser Read - * 0b0..Read access is not allowed in Nonsecure User mode. - * 0b1..Read access is allowed in Nonsecure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_MASK (0x10U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_SHIFT (4U) -/*! NPX - NonsecurePriv Execute - * 0b0..Execute access is not allowed in Nonsecure Privilege mode. - * 0b1..Execute access is allowed in Nonsecure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_MASK (0x20U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_SHIFT (5U) -/*! NPW - NonsecurePriv Write - * 0b0..Write access is not allowed in Nonsecure Privilege mode. - * 0b1..Write access is allowed in Nonsecure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_MASK (0x40U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_SHIFT (6U) -/*! NPR - NonsecurePriv Read - * 0b0..Read access is not allowed in Nonsecure Privilege mode. - * 0b1..Read access is allowed in Nonsecure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_MASK (0x100U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_SHIFT (8U) -/*! SUX - SecureUser Execute - * 0b0..Execute access is not allowed in Secure User mode. - * 0b1..Execute access is allowed in Secure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_MASK (0x200U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_SHIFT (9U) -/*! SUW - SecureUser Write - * 0b0..Write access is not allowed in Secure User mode. - * 0b1..Write access is allowed in Secure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_MASK (0x400U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_SHIFT (10U) -/*! SUR - SecureUser Read - * 0b0..Read access is not allowed in Secure User mode. - * 0b1..Read access is allowed in Secure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_MASK (0x1000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_SHIFT (12U) -/*! SPX - SecurePriv Execute - * 0b0..Execute access is not allowed in Secure Privilege mode. - * 0b1..Execute access is allowed in Secure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_MASK (0x2000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_SHIFT (13U) -/*! SPW - SecurePriv Write - * 0b0..Write access is not allowed in Secure Privilege mode. - * 0b1..Write access is allowed in Secure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_MASK (0x4000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_SHIFT (14U) -/*! SPR - SecurePriv Read - * 0b0..Read access is not allowed in Secure Privilege mode. - * 0b1..Read access is allowed in Secure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_MASK (0x80000000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_SHIFT (31U) -/*! LK - LOCK - * 0b0..This register is not locked and can be altered. - * 0b1..This register is locked and cannot be altered. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_MASK) -/*! @} */ - -/* The count of MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_COUNT (8U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_COUNT (1U) - - -/*! - * @} - */ /* end of group MBC_Register_Masks */ - - -/* MBC - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral TRDC base address */ - #define TRDC_BASE (0x500C6000u) - /** Peripheral TRDC base address */ - #define TRDC_BASE_NS (0x400C6000u) - /** Peripheral TRDC base pointer */ - #define TRDC ((MBC_Type *)TRDC_BASE) - /** Peripheral TRDC base pointer */ - #define TRDC_NS ((MBC_Type *)TRDC_BASE_NS) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { TRDC_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { TRDC } - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS_NS { TRDC_BASE_NS } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS_NS { TRDC_NS } -#else - /** Peripheral TRDC base address */ - #define TRDC_BASE (0x400C6000u) - /** Peripheral TRDC base pointer */ - #define TRDC ((MBC_Type *)TRDC_BASE) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { TRDC_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { TRDC } -#endif - -/*! - * @} - */ /* end of group MBC_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- MRT Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -58932,10 +52495,7 @@ typedef struct { #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. Writing 0 indicates no pending interrupt or no operation. - * Writing 1 indicates pending interrupt, because TIMERn has reached the end of the time - * interval. If CTRL and the global interrupt are generated. Writing 1 to this field bit clears the - * interrupt request.n in the CONTROLn also gets 1, then the interrupt for timer channel n +/*! INTFLAG - Interrupt Flag * 0b0..No pending interrupt. * 0b1..Pending interrupt. */ @@ -59233,12 +52793,12 @@ typedef struct { #define NPX_REMAP_LIM_MASK (0x1F0000U) #define NPX_REMAP_LIM_SHIFT (16U) -/*! LIM - LIM data */ +/*! LIM - LIM Remapping Address */ #define NPX_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK) #define NPX_REMAP_LIMDP_MASK (0x1F000000U) #define NPX_REMAP_LIMDP_SHIFT (24U) -/*! LIMDP - LIM_DP data */ +/*! LIMDP - LIMDP Remapping Address */ #define NPX_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK) /*! @} */ @@ -59911,10 +53471,10 @@ typedef struct { #define OPAMP_OPAMP_CTR_INTREF_MASK (0x30U) #define OPAMP_OPAMP_CTR_INTREF_SHIFT (4U) -/*! INTREF - Internal Reference Voltage Selection - * 0b00..Select VDDA/2 - * 0b01..Select VDDA_3V - * 0b10..Select VSSA_3V +/*! INTREF - Provide OPAMP rail to rail voltage selection + * 0b00..Select OPAMP input rail to rail voltage from 0 to VDD_ANA + * 0b01..Select OPAMP input rail to rail voltage from 0 to VDD_ANA-0.8V + * 0b10..Select OPAMP input rail to rail voltage from 0.8V to VDD_ANA * 0b11..Not allowed */ #define OPAMP_OPAMP_CTR_INTREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK) @@ -59954,10 +53514,10 @@ typedef struct { #define OPAMP_OPAMP_CTR_PREF_MASK (0x60000U) #define OPAMP_OPAMP_CTR_PREF_SHIFT (17U) /*! PREF - Positive Reference Voltage Selection - * 0b00..DACx_OUT - * 0b01..VDDA/2 - * 0b10..VREFO - * 0b11..520 mV + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 */ #define OPAMP_OPAMP_CTR_PREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK) @@ -59989,13 +53549,13 @@ typedef struct { #define OPAMP_OPAMP_CTR_PGAIN_SHIFT (24U) /*! PGAIN - Positive PGA Selection * 0b000..Positive input 1 (INP1) - * 0b001..Gain application 1* - * 0b010..Gain application 2* - * 0b011..Gain application 4* - * 0b100..Gain application 8* - * 0b101..Gain application 16* - * 0b110..Gain application 33* - * 0b111..Gain application 64* + * 0b001..Pgain=1 + * 0b010..Pgain=2 + * 0b011..Pgain=4 + * 0b100..Pgain=8 + * 0b101..Pgain=16 + * 0b110..Pgain=33 + * 0b111..Pgain=64 */ #define OPAMP_OPAMP_CTR_PGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK) @@ -60003,13 +53563,13 @@ typedef struct { #define OPAMP_OPAMP_CTR_NGAIN_SHIFT (28U) /*! NGAIN - Negative PGA Selection * 0b000..Buffer - * 0b001..Gain application 1* - * 0b010..Gain application 2* - * 0b011..Gain application 4* - * 0b100..Gain application 8* - * 0b101..Gain application 16* - * 0b110..Gain application 33* - * 0b111..Gain application 64* + * 0b001..Ngain=1 + * 0b010..Ngain=2 + * 0b011..Ngain=4 + * 0b100..Ngain=8 + * 0b101..Ngain=16 + * 0b110..Ngain=33 + * 0b111..Ngain=64 */ #define OPAMP_OPAMP_CTR_NGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK) /*! @} */ @@ -60850,7 +54410,10 @@ typedef struct { #define PDM_CTRL_1_DOZEN_MASK (0x40000000U) #define PDM_CTRL_1_DOZEN_SHIFT (30U) -/*! DOZEN - Doze Enable */ +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ #define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) #define PDM_CTRL_1_MDIS_MASK (0x80000000U) @@ -60867,7 +54430,12 @@ typedef struct { #define PDM_CTRL_2_CLKDIV_MASK (0xFFU) #define PDM_CTRL_2_CLKDIV_SHIFT (0U) -/*! CLKDIV - Clock Divider */ +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ #define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) #define PDM_CTRL_2_CLKDIVDIS_MASK (0x8000U) @@ -60880,7 +54448,12 @@ typedef struct { #define PDM_CTRL_2_CICOSR_MASK (0xF0000U) #define PDM_CTRL_2_CICOSR_SHIFT (16U) -/*! CICOSR - CIC Decimation Rate */ +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ #define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) #define PDM_CTRL_2_QSEL_MASK (0xE000000U) @@ -61242,12 +54815,24 @@ typedef struct { #define PDM_PARAM_NPAIR_MASK (0xFU) #define PDM_PARAM_NPAIR_SHIFT (0U) -/*! NPAIR - Number of Microphone Pairs */ +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ #define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) #define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) #define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) -/*! FIFO_PTRWID - FIFO Pointer Width */ +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ #define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) #define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) @@ -61519,112 +55104,112 @@ typedef struct { #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) /*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) #define PINT_PMSRC_SRC1_MASK (0x3800U) #define PINT_PMSRC_SRC1_SHIFT (11U) /*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) #define PINT_PMSRC_SRC2_MASK (0x1C000U) #define PINT_PMSRC_SRC2_SHIFT (14U) /*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) #define PINT_PMSRC_SRC3_MASK (0xE0000U) #define PINT_PMSRC_SRC3_SHIFT (17U) /*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) #define PINT_PMSRC_SRC4_MASK (0x700000U) #define PINT_PMSRC_SRC4_SHIFT (20U) /*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) #define PINT_PMSRC_SRC5_MASK (0x3800000U) #define PINT_PMSRC_SRC5_SHIFT (23U) /*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) #define PINT_PMSRC_SRC6_MASK (0x1C000000U) #define PINT_PMSRC_SRC6_SHIFT (26U) /*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) /*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) /*! @} */ @@ -61871,8 +55456,8 @@ typedef struct { /** PKC - Register Layout Typedef */ typedef struct { - __I uint32_t PKC_STATUS; /**< Status register, offset: 0x0 */ - __IO uint32_t PKC_CTRL; /**< Control register, offset: 0x4 */ + __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ @@ -61916,151 +55501,97 @@ typedef struct { * @{ */ -/*! @name PKC_STATUS - Status register */ +/*! @name PKC_STATUS - Status Register */ /*! @{ */ #define PKC_PKC_STATUS_ACTIV_MASK (0x1U) #define PKC_PKC_STATUS_ACTIV_SHIFT (0U) -/*! activ - PKC active: ACTIV=1 signals that a calculation is in progress or about to start. At the - * end of a calculation ACTIV is automatically reset to logic 0 in case no further GO bit is set. - * If the next PKC operation has been started by setting a GO bit during a calculation, ACTIV - * remains high. ACTIV is always '1' in case PKC_STATUS.GOANY is set. ACTIV is always '0' in case - * PKC_CTRL_RESET is set. - */ +/*! ACTIV - PKC ACTIV */ #define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) #define PKC_PKC_STATUS_CARRY_MASK (0x2U) #define PKC_PKC_STATUS_CARRY_SHIFT (1U) -/*! carry - Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case */ +/*! CARRY - Carry overflow flag */ #define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) #define PKC_PKC_STATUS_ZERO_MASK (0x4U) #define PKC_PKC_STATUS_ZERO_SHIFT (2U) -/*! zero - Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result - * of the calculation is equal zero. ZERO is updated for each PKC calculation mode, except for - * MUL1 (opcode 0x20) and MUL1_GF2 (opcode 0x24). - */ +/*! ZERO - Zero result flag */ #define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) #define PKC_PKC_STATUS_GOANY_MASK (0x8U) #define PKC_PKC_STATUS_GOANY_SHIFT (3U) -/*! goany - Combined GO status flag: GOANY is set in case either PKC_CTRL.GOD1, GOD2, GOM1, GOM2 or - * GOU is set. The 1-to-0 transition of GOANY indicates that a calculation has been started and - * that a new GO bit can be set. If GOANY is cleared also all PKC_STATUS.LOCKED bits are cleared - * to indicate that the parameter set can be updated. GOANY is always '0' in case PKC_CTRL.RESET - * is set. - */ +/*! GOANY - Combined GO status flag */ #define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) -#define PKC_PKC_STATUS_RESERVED4_MASK (0x10U) -#define PKC_PKC_STATUS_RESERVED4_SHIFT (4U) -/*! reserved4 - reserved */ -#define PKC_PKC_STATUS_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_RESERVED4_SHIFT)) & PKC_PKC_STATUS_RESERVED4_MASK) - #define PKC_PKC_STATUS_LOCKED_MASK (0x60U) #define PKC_PKC_STATUS_LOCKED_SHIFT (5U) -/*! locked - Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten. */ +/*! LOCKED - Parameter set locked */ #define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) - -#define PKC_PKC_STATUS_RESERVED31_MASK (0xFFFFFF80U) -#define PKC_PKC_STATUS_RESERVED31_SHIFT (7U) -/*! reserved31 - reserved */ -#define PKC_PKC_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_RESERVED31_SHIFT)) & PKC_PKC_STATUS_RESERVED31_MASK) /*! @} */ -/*! @name PKC_CTRL - Control register */ +/*! @name PKC_CTRL - Control Register */ /*! @{ */ #define PKC_PKC_CTRL_RESET_MASK (0x1U) #define PKC_PKC_CTRL_RESET_SHIFT (0U) -/*! reset - PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation - * cannot be started and by which any ongoing calculation process is stopped. RESET can be - * set/cleared by the CPU in order to switch between PKC reset and calculation enable. RESET=1 is the - * default state after a chip reset. - */ +/*! RESET - PKC reset control bit */ #define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) #define PKC_PKC_CTRL_STOP_MASK (0x2U) #define PKC_PKC_CTRL_STOP_SHIFT (1U) -/*! stop - Freeze PKC calculation: STOP=1 freezes all PKC activity incl. RAM accesses and reduces - * the PKC power consumption to its minimum. The difference compared to the reset of the PKC is - * that a stopped calculation can be continued when STOP is released (reset to '0') again. The - * status flags are not affected by the STOP control bit. - */ +/*! STOP - Freeze PKC calculation */ #define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) #define PKC_PKC_CTRL_GOD1_MASK (0x4U) #define PKC_PKC_CTRL_GOD1_SHIFT (2U) -/*! god1 - Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will - * start a direct / L0 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, PKC_LEN1). - */ +/*! GOD1 - Control bit to start direct operation using parameter set 1 */ #define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) #define PKC_PKC_CTRL_GOD2_MASK (0x8U) #define PKC_PKC_CTRL_GOD2_SHIFT (3U) -/*! god2 - Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will - * start a direct / L0 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2). - */ +/*! GOD2 - Control bit to start direct operation using parameter set 2 */ #define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) #define PKC_PKC_CTRL_GOM1_MASK (0x10U) #define PKC_PKC_CTRL_GOM1_SHIFT (4U) -/*! gom1 - Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC - * pattern / L1 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, PKC_LEN1). - */ +/*! GOM1 - Control bit to start MC pattern using parameter set 1 */ #define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) #define PKC_PKC_CTRL_GOM2_MASK (0x20U) #define PKC_PKC_CTRL_GOM2_SHIFT (5U) -/*! gom2 - Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC - * pattern / L1 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2). - */ +/*! GOM2 - Control bit to start MC pattern using parameter set 2 */ #define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) #define PKC_PKC_CTRL_GOU_MASK (0x40U) #define PKC_PKC_CTRL_GOU_SHIFT (6U) -/*! gou - Control bit to start pipe operation: If GOU is set PKC will start the pipe / L2 operation - * (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch Operation'. - */ +/*! GOU - Control bit to start pipe operation */ #define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) #define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) #define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) -/*! gf2conv - Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes. */ +/*! GF2CONV - Convert to GF2 calculation modes */ #define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) #define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) #define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) -/*! clrcache - Clear universal pointer cache: Invalidates the cache such that all previously fetched - * parameters are withdrawn and have to be fetched again via DMA accesses. - */ +/*! CLRCACHE - Clear universal pointer cache */ #define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) #define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) #define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) -/*! cache_en - Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer - * parameters is enabled. In case a parameter value is found in the cache (from a previous fetch) no - * DMA access is triggered. As such the amount of DMA accesses for the parameter fetch vary - * between 0 and 4. To further optimize the cache utilization not used parameters, e.g. XPTR for a - * plain addition (opcode 0x0A), could be defined equal to a used one (e.g. equal YPTR or RPTR) or - * a previously fetched parameter. - */ +/*! CACHE_EN - Enable universal pointer cache */ #define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) #define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) #define PKC_PKC_CTRL_REDMUL_SHIFT (10U) -/*! redmul - Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor. +/*! REDMUL - Reduced multiplier mode * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 - * 0b01..RFU Error Generated if selected + * 0b01..Reserved - Error Generated if selected * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 - * 0b11..RFU Error Generated if selected + * 0b11..Reserved - Error Generated if selected */ #define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) - -#define PKC_PKC_CTRL_RESERVED31_MASK (0xFFFFF000U) -#define PKC_PKC_CTRL_RESERVED31_SHIFT (12U) -/*! reserved31 - reserved */ -#define PKC_PKC_CTRL_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESERVED31_SHIFT)) & PKC_PKC_CTRL_RESERVED31_MASK) /*! @} */ /*! @name PKC_CFG - Configuration register */ @@ -62068,53 +55599,39 @@ typedef struct { #define PKC_PKC_CFG_IDLEOP_MASK (0x1U) #define PKC_PKC_CFG_IDLEOP_SHIFT (0U) -/*! idleop - Idle operation feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) #define PKC_PKC_CFG_RFU1_MASK (0x2U) #define PKC_PKC_CFG_RFU1_SHIFT (1U) -/*! rfu1 - RFU */ #define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) #define PKC_PKC_CFG_RFU2_MASK (0x4U) #define PKC_PKC_CFG_RFU2_SHIFT (2U) -/*! rfu2 - RFU */ #define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) #define PKC_PKC_CFG_CLKRND_MASK (0x8U) #define PKC_PKC_CFG_CLKRND_SHIFT (3U) -/*! clkrnd - Clock randomization feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) #define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) #define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) -/*! redmulnoise - Noise in reduced multiplier mode feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) #define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) #define PKC_PKC_CFG_RNDDLY_SHIFT (5U) -/*! rnddly - Random delay feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) #define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) #define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) -/*! sbxnoise - Noise feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) #define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) #define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) -/*! alpnoise - Noise feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) #define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) #define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) -/*! fmulnoise - Noise feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) - -#define PKC_PKC_CFG_RESERVED31_MASK (0xFFFFF800U) -#define PKC_PKC_CFG_RESERVED31_SHIFT (11U) -/*! reserved31 - reserved */ -#define PKC_PKC_CFG_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RESERVED31_SHIFT)) & PKC_PKC_CFG_RESERVED31_MASK) /*! @} */ /*! @name PKC_MODE1 - Mode register, parameter set 1 */ @@ -62122,13 +55639,8 @@ typedef struct { #define PKC_PKC_MODE1_MODE_MASK (0xFFU) #define PKC_PKC_MODE1_MODE_SHIFT (0U) -/*! mode - Calculation Mode / MC Start address: */ +/*! MODE - Calculation Mode / MC Start address */ #define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) - -#define PKC_PKC_MODE1_RESERVED31_MASK (0xFFFFFF00U) -#define PKC_PKC_MODE1_RESERVED31_SHIFT (8U) -/*! reserved31 - reserved */ -#define PKC_PKC_MODE1_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_RESERVED31_SHIFT)) & PKC_PKC_MODE1_RESERVED31_MASK) /*! @} */ /*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ @@ -62136,18 +55648,12 @@ typedef struct { #define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) #define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) -/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) #define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) #define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) -/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) /*! @} */ @@ -62156,15 +55662,12 @@ typedef struct { #define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) #define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) -/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: */ +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ #define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) #define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) #define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) -/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ #define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) /*! @} */ @@ -62173,19 +55676,12 @@ typedef struct { #define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) #define PKC_PKC_LEN1_LEN_SHIFT (0U) -/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length - * of Y, Z and R depend furthermore on the selected calculation mode. - */ +/*! LEN - Operand length */ #define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) #define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) #define PKC_PKC_LEN1_MCLEN_SHIFT (16U) -/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that - * can be used in L1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC patterns - * Modular Multiplication (MC start address 0x00), Plain Multiplication (0x13), Plain - * Multiplication with Addition (0x1D) and Modular Reduction (0x33) MCLEN defines the length of the X operand - * in bytes. - */ +/*! MCLEN - Loop counter for microcode pattern */ #define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) /*! @} */ @@ -62194,13 +55690,8 @@ typedef struct { #define PKC_PKC_MODE2_MODE_MASK (0xFFU) #define PKC_PKC_MODE2_MODE_SHIFT (0U) -/*! mode - Calculation Mode / MC Start address: */ +/*! MODE - Calculation Mode / MC Start address */ #define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) - -#define PKC_PKC_MODE2_RESERVED31_MASK (0xFFFFFF00U) -#define PKC_PKC_MODE2_RESERVED31_SHIFT (8U) -/*! reserved31 - reserved */ -#define PKC_PKC_MODE2_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_RESERVED31_SHIFT)) & PKC_PKC_MODE2_RESERVED31_MASK) /*! @} */ /*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ @@ -62208,35 +55699,26 @@ typedef struct { #define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) #define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) -/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) #define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) #define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) -/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) /*! @} */ /*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ /*! @{ */ -#define PKC_PKC_ZRPTR2_ZPTR_MASK (0xFFFFU) -#define PKC_PKC_ZRPTR2_ZPTR_SHIFT (0U) -/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: */ -#define PKC_PKC_ZRPTR2_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPTR_SHIFT)) & PKC_PKC_ZRPTR2_ZPTR_MASK) +#define PKC_PKC_ZRPTR2_ZPT_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_ZPT_SHIFT (0U) +/*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR2_ZPT(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK) #define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) #define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) -/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ #define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) /*! @} */ @@ -62245,17 +55727,12 @@ typedef struct { #define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) #define PKC_PKC_LEN2_LEN_SHIFT (0U) -/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length - * of Y, Z and R depend furthermore on the selected calculation mode. - */ +/*! LEN - Operand length */ #define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) #define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) #define PKC_PKC_LEN2_MCLEN_SHIFT (16U) -/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that - * can be used in L1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC patterns - * Modular Multiplication (MC start address 0x00) - */ +/*! MCLEN - Loop counter for microcode pattern */ #define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) /*! @} */ @@ -62264,11 +55741,7 @@ typedef struct { #define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) #define PKC_PKC_UPTR_PTR_SHIFT (0U) -/*! ptr - Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting - * a universal pointer PKC calculation (L2) via PKC_CTRL.GOU. The pointer address needs to be - * valid and the memory space the pointer addresses needs to be enabled for PKC access by the - * system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). - */ +/*! PTR - Pointer to start address of PKC FUP program */ #define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) /*! @} */ @@ -62277,11 +55750,7 @@ typedef struct { #define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) #define PKC_PKC_UPTRT_PTR_SHIFT (0U) -/*! ptr - Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a - * universal pointer PKC calculation (L2) via PKC_CTRL.GOU. The pointer address needs to be - * valid and the memory space the pointer addresses needs to be enabled for PKC access by the system. - * Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). - */ +/*! PTR - Pointer to start address of PKC FUP table */ #define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) /*! @} */ @@ -62290,16 +55759,8 @@ typedef struct { #define PKC_PKC_ULEN_LEN_MASK (0xFFU) #define PKC_PKC_ULEN_LEN_SHIFT (0U) -/*! len - Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries - * shall be processed for one L2 calculation started via PKC_CTRL.GOU. The FUP program entries - * include L0 calculations, L1 calculations and CRC entries for FUP program integrity protection. - */ +/*! LEN - Length of universal pointer calculation */ #define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) - -#define PKC_PKC_ULEN_RESERVED31_MASK (0xFFFFFF00U) -#define PKC_PKC_ULEN_RESERVED31_SHIFT (8U) -/*! reserved31 - reserved */ -#define PKC_PKC_ULEN_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_RESERVED31_SHIFT)) & PKC_PKC_ULEN_RESERVED31_MASK) /*! @} */ /*! @name PKC_MCDATA - MC pattern data interface */ @@ -62307,10 +55768,7 @@ typedef struct { #define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) #define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) -/*! mcdata - Microcode read/write data: This IP version does not support flexible MC patterns (only - * hard coded ones). Any read or write access to PKC_MCDATA triggers a security alarm - * (PKC_ACCESS_ERR.CTRL is set). - */ +/*! MCDATA - Microcode read/write data */ #define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) /*! @} */ @@ -62319,67 +55777,54 @@ typedef struct { #define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) #define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) -/*! mulsize - native multiplier size and operand granularity +/*! MULSIZE * 0b01..32-bit multiplier * 0b10..64-bit multiplier * 0b11..128-bit multiplier + * 0b10..128-bit multiplier + * 0b01..64-bit multiplier */ #define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) #define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) #define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) -/*! mcavail - MC feature (L1 calculation) is available */ #define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) #define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) #define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) -/*! upavail - UP feature (L2 calculation) is available */ #define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) #define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) #define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) -/*! upcacheavail - UP cache is available */ #define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) #define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) #define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) -/*! gf2avail - GF2 calculation modes are available */ #define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) #define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) #define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) -/*! paramnum - Number of parameter sets for real calculation */ #define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) #define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) #define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) -/*! sbx0avail - SBX0 operation is available */ #define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) #define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) #define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) -/*! sbx1avail - SBX1 operation is available */ #define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) #define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) #define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) -/*! sbx2avail - SBX2 operation is available */ #define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) #define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) #define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) -/*! sbx3avail - SBX3 operation is available */ #define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) #define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) #define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) -/*! mcreconf_size - Size of reconfigurable MC table in bytes */ #define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) - -#define PKC_PKC_VERSION_RESERVED31_MASK (0xFFF00000U) -#define PKC_PKC_VERSION_RESERVED31_SHIFT (20U) -/*! reserved31 - reserved */ -#define PKC_PKC_VERSION_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_RESERVED31_SHIFT)) & PKC_PKC_VERSION_RESERVED31_MASK) /*! @} */ /*! @name PKC_SOFT_RST - Software reset */ @@ -62387,15 +55832,7 @@ typedef struct { #define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) #define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) -/*! soft_rst - Write 1 to reset module (0 has no effect). All running and pending PKC calculation - * are stopped. All PKC SFRs are reset except PKC_ACCESS_ERR. - */ #define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) - -#define PKC_PKC_SOFT_RST_RESERVED31_MASK (0xFFFFFFFEU) -#define PKC_PKC_SOFT_RST_RESERVED31_SHIFT (1U) -/*! reserved31 - reserved */ -#define PKC_PKC_SOFT_RST_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_RESERVED31_SHIFT)) & PKC_PKC_SOFT_RST_RESERVED31_MASK) /*! @} */ /*! @name PKC_ACCESS_ERR - Access Error */ @@ -62403,68 +55840,38 @@ typedef struct { #define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) #define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) -/*! apb_notav - APB Error: address not available */ +/*! APB_NOTAV - APB Error */ #define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) #define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) #define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) -/*! apb_wrgmd - APB Error: Wrong access mode */ +/*! APB_WRGMD - APB Error */ #define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) -#define PKC_PKC_ACCESS_ERR_RESERVED3_MASK (0xCU) -#define PKC_PKC_ACCESS_ERR_RESERVED3_SHIFT (2U) -/*! reserved3 - reserved for future erors on APB I/F */ -#define PKC_PKC_ACCESS_ERR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED3_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED3_MASK) - #define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) #define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) -/*! apb_master - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV) */ #define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) -#define PKC_PKC_ACCESS_ERR_RESERVED9_MASK (0x300U) -#define PKC_PKC_ACCESS_ERR_RESERVED9_SHIFT (8U) -/*! reserved9 - reserved for future erors on AHB I/F L2 Only */ -#define PKC_PKC_ACCESS_ERR_RESERVED9(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED9_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED9_MASK) - #define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) #define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) -/*! ahb - AHB Error: invalid AHB access L2 Only */ +/*! AHB - AHB Error */ #define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) -#define PKC_PKC_ACCESS_ERR_RESERVED15_MASK (0xF800U) -#define PKC_PKC_ACCESS_ERR_RESERVED15_SHIFT (11U) -/*! reserved15 - reserved for future erors on AHB I/F L2 Only */ -#define PKC_PKC_ACCESS_ERR_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED15_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED15_MASK) - #define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) #define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) -/*! pkcc - Error in PKC coprocessor kernel */ #define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) #define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) #define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) -/*! fdet - Error due to error detection circuitry */ #define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) #define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) #define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) -/*! ctrl - Error in PKC software control */ #define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) #define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) #define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) -/*! ucrc - Error in L2 CRC check */ #define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) - -#define PKC_PKC_ACCESS_ERR_RESERVED20_MASK (0x100000U) -#define PKC_PKC_ACCESS_ERR_RESERVED20_SHIFT (20U) -/*! reserved20 - reserved */ -#define PKC_PKC_ACCESS_ERR_RESERVED20(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED20_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED20_MASK) - -#define PKC_PKC_ACCESS_ERR_RESERVED31_MASK (0xFFE00000U) -#define PKC_PKC_ACCESS_ERR_RESERVED31_SHIFT (21U) -/*! reserved31 - reserved for more block errors */ -#define PKC_PKC_ACCESS_ERR_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED31_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED31_MASK) /*! @} */ /*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ @@ -62472,13 +55879,7 @@ typedef struct { #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) -/*! err_clr - Write 1 to reset PKC_ACCESS_ERR SFR. */ #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) - -#define PKC_PKC_ACCESS_ERR_CLR_RESERVED31_MASK (0xFFFFFFFEU) -#define PKC_PKC_ACCESS_ERR_CLR_RESERVED31_SHIFT (1U) -/*! reserved31 - reserved */ -#define PKC_PKC_ACCESS_ERR_CLR_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_RESERVED31_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ @@ -62486,18 +55887,7 @@ typedef struct { #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) -/*! en_pdone - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=0). */ #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) - -#define PKC_PKC_INT_CLR_ENABLE_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_CLR_ENABLE_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_CLR_ENABLE_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_RESERVED1_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_RESERVED1_MASK) - -#define PKC_PKC_INT_CLR_ENABLE_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_CLR_ENABLE_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_CLR_ENABLE_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_RESERVED31_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ @@ -62505,18 +55895,7 @@ typedef struct { #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) -/*! en_pdone - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=1). */ #define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) - -#define PKC_PKC_INT_SET_ENABLE_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_SET_ENABLE_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_SET_ENABLE_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_RESERVED1_SHIFT)) & PKC_PKC_INT_SET_ENABLE_RESERVED1_MASK) - -#define PKC_PKC_INT_SET_ENABLE_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_SET_ENABLE_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_SET_ENABLE_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_RESERVED31_SHIFT)) & PKC_PKC_INT_SET_ENABLE_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_STATUS - Interrupt status */ @@ -62524,22 +55903,8 @@ typedef struct { #define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) -/*! int_pdone - End-of-computation status flag: INT_PDONE is set after EACH single PKC L0 or L1 - * calculation. In case of a universal pointer calculation (L2) INT_PDONE is set at the end of the - * pipe calculation when PKC_ULEN has been decremented to zero and the final PKC calculation has - * completed. - */ +/*! INT_PDONE - End-of-computation status flag */ #define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) - -#define PKC_PKC_INT_STATUS_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_STATUS_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_STATUS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_RESERVED1_SHIFT)) & PKC_PKC_INT_STATUS_RESERVED1_MASK) - -#define PKC_PKC_INT_STATUS_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_STATUS_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_RESERVED31_SHIFT)) & PKC_PKC_INT_STATUS_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_ENABLE - Interrupt enable */ @@ -62547,20 +55912,8 @@ typedef struct { #define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) -/*! en_pdone - PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time - * PKC_INT_STATUS.INT_PDONE is set. Otherwise the interrupt generation is suppressed. - */ +/*! EN_PDONE - PDONE interrupt enable flag */ #define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) - -#define PKC_PKC_INT_ENABLE_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_ENABLE_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_ENABLE_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_RESERVED1_SHIFT)) & PKC_PKC_INT_ENABLE_RESERVED1_MASK) - -#define PKC_PKC_INT_ENABLE_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_ENABLE_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_ENABLE_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_RESERVED31_SHIFT)) & PKC_PKC_INT_ENABLE_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ @@ -62568,18 +55921,7 @@ typedef struct { #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) -/*! int_pdone - Write to clear End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=0). */ #define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) - -#define PKC_PKC_INT_CLR_STATUS_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_CLR_STATUS_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_CLR_STATUS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_RESERVED1_SHIFT)) & PKC_PKC_INT_CLR_STATUS_RESERVED1_MASK) - -#define PKC_PKC_INT_CLR_STATUS_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_CLR_STATUS_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_CLR_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_RESERVED31_SHIFT)) & PKC_PKC_INT_CLR_STATUS_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_SET_STATUS - Interrupt status set */ @@ -62587,20 +55929,7 @@ typedef struct { #define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) -/*! int_pdone - Write to set End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=1) to trigger - * a PKC interrupt via software, e.g. for debug purposes. - */ #define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) - -#define PKC_PKC_INT_SET_STATUS_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_SET_STATUS_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_SET_STATUS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_RESERVED1_SHIFT)) & PKC_PKC_INT_SET_STATUS_RESERVED1_MASK) - -#define PKC_PKC_INT_SET_STATUS_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_SET_STATUS_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_SET_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_RESERVED31_SHIFT)) & PKC_PKC_INT_SET_STATUS_RESERVED31_MASK) /*! @} */ /*! @name PKC_MODULE_ID - Module ID */ @@ -62608,22 +55937,18 @@ typedef struct { #define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) #define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) -/*! size - Address space of the IP */ #define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) #define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) #define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! minor_rev - Minor revision */ #define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) #define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) #define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! major_rev - Major revision */ #define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) #define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) #define PKC_PKC_MODULE_ID_ID_SHIFT (16U) -/*! id - Module ID */ #define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) /*! @} */ @@ -62923,7 +56248,7 @@ typedef struct { __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ uint8_t RESERVED_4[24]; - __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 23, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ + __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ } PORT_Type; /* ---------------------------------------------------------------------------- @@ -63317,14 +56642,6 @@ typedef struct { */ #define PORT_EDFR_EDF8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK) -#define PORT_EDFR_Reserved8_MASK (0x100U) -#define PORT_EDFR_Reserved8_SHIFT (8U) -/*! Reserved8 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved8_SHIFT)) & PORT_EDFR_Reserved8_MASK) - #define PORT_EDFR_EDF9_MASK (0x200U) #define PORT_EDFR_EDF9_SHIFT (9U) /*! EDF9 - EFT Detect Flag @@ -63333,14 +56650,6 @@ typedef struct { */ #define PORT_EDFR_EDF9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK) -#define PORT_EDFR_Reserved9_MASK (0x200U) -#define PORT_EDFR_Reserved9_SHIFT (9U) -/*! Reserved9 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved9_SHIFT)) & PORT_EDFR_Reserved9_MASK) - #define PORT_EDFR_EDF10_MASK (0x400U) #define PORT_EDFR_EDF10_SHIFT (10U) /*! EDF10 - EFT Detect Flag @@ -63349,14 +56658,6 @@ typedef struct { */ #define PORT_EDFR_EDF10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK) -#define PORT_EDFR_Reserved10_MASK (0x400U) -#define PORT_EDFR_Reserved10_SHIFT (10U) -/*! Reserved10 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved10_SHIFT)) & PORT_EDFR_Reserved10_MASK) - #define PORT_EDFR_EDF11_MASK (0x800U) #define PORT_EDFR_EDF11_SHIFT (11U) /*! EDF11 - EFT Detect Flag @@ -63365,14 +56666,6 @@ typedef struct { */ #define PORT_EDFR_EDF11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK) -#define PORT_EDFR_Reserved11_MASK (0x800U) -#define PORT_EDFR_Reserved11_SHIFT (11U) -/*! Reserved11 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved11_SHIFT)) & PORT_EDFR_Reserved11_MASK) - #define PORT_EDFR_EDF12_MASK (0x1000U) #define PORT_EDFR_EDF12_SHIFT (12U) /*! EDF12 - EFT Detect Flag @@ -63381,14 +56674,6 @@ typedef struct { */ #define PORT_EDFR_EDF12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK) -#define PORT_EDFR_Reserved12_MASK (0x1000U) -#define PORT_EDFR_Reserved12_SHIFT (12U) -/*! Reserved12 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved12_SHIFT)) & PORT_EDFR_Reserved12_MASK) - #define PORT_EDFR_EDF13_MASK (0x2000U) #define PORT_EDFR_EDF13_SHIFT (13U) /*! EDF13 - EFT Detect Flag @@ -63397,14 +56682,6 @@ typedef struct { */ #define PORT_EDFR_EDF13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK) -#define PORT_EDFR_Reserved13_MASK (0x2000U) -#define PORT_EDFR_Reserved13_SHIFT (13U) -/*! Reserved13 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved13_SHIFT)) & PORT_EDFR_Reserved13_MASK) - #define PORT_EDFR_EDF14_MASK (0x4000U) #define PORT_EDFR_EDF14_SHIFT (14U) /*! EDF14 - EFT Detect Flag @@ -63413,14 +56690,6 @@ typedef struct { */ #define PORT_EDFR_EDF14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK) -#define PORT_EDFR_Reserved14_MASK (0x4000U) -#define PORT_EDFR_Reserved14_SHIFT (14U) -/*! Reserved14 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved14_SHIFT)) & PORT_EDFR_Reserved14_MASK) - #define PORT_EDFR_EDF15_MASK (0x8000U) #define PORT_EDFR_EDF15_SHIFT (15U) /*! EDF15 - EFT Detect Flag @@ -63429,14 +56698,6 @@ typedef struct { */ #define PORT_EDFR_EDF15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK) -#define PORT_EDFR_Reserved15_MASK (0x8000U) -#define PORT_EDFR_Reserved15_SHIFT (15U) -/*! Reserved15 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved15_SHIFT)) & PORT_EDFR_Reserved15_MASK) - #define PORT_EDFR_EDF16_MASK (0x10000U) #define PORT_EDFR_EDF16_SHIFT (16U) /*! EDF16 - EFT Detect Flag @@ -63445,14 +56706,6 @@ typedef struct { */ #define PORT_EDFR_EDF16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK) -#define PORT_EDFR_Reserved16_MASK (0x10000U) -#define PORT_EDFR_Reserved16_SHIFT (16U) -/*! Reserved16 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved16_SHIFT)) & PORT_EDFR_Reserved16_MASK) - #define PORT_EDFR_EDF17_MASK (0x20000U) #define PORT_EDFR_EDF17_SHIFT (17U) /*! EDF17 - EFT Detect Flag @@ -63461,14 +56714,6 @@ typedef struct { */ #define PORT_EDFR_EDF17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK) -#define PORT_EDFR_Reserved17_MASK (0x20000U) -#define PORT_EDFR_Reserved17_SHIFT (17U) -/*! Reserved17 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved17_SHIFT)) & PORT_EDFR_Reserved17_MASK) - #define PORT_EDFR_EDF18_MASK (0x40000U) #define PORT_EDFR_EDF18_SHIFT (18U) /*! EDF18 - EFT Detect Flag @@ -63477,14 +56722,6 @@ typedef struct { */ #define PORT_EDFR_EDF18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK) -#define PORT_EDFR_Reserved18_MASK (0x40000U) -#define PORT_EDFR_Reserved18_SHIFT (18U) -/*! Reserved18 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved18_SHIFT)) & PORT_EDFR_Reserved18_MASK) - #define PORT_EDFR_EDF19_MASK (0x80000U) #define PORT_EDFR_EDF19_SHIFT (19U) /*! EDF19 - EFT Detect Flag @@ -63493,14 +56730,6 @@ typedef struct { */ #define PORT_EDFR_EDF19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK) -#define PORT_EDFR_Reserved19_MASK (0x80000U) -#define PORT_EDFR_Reserved19_SHIFT (19U) -/*! Reserved19 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved19_SHIFT)) & PORT_EDFR_Reserved19_MASK) - #define PORT_EDFR_EDF20_MASK (0x100000U) #define PORT_EDFR_EDF20_SHIFT (20U) /*! EDF20 - EFT Detect Flag @@ -63509,14 +56738,6 @@ typedef struct { */ #define PORT_EDFR_EDF20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK) -#define PORT_EDFR_Reserved20_MASK (0x100000U) -#define PORT_EDFR_Reserved20_SHIFT (20U) -/*! Reserved20 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved20_SHIFT)) & PORT_EDFR_Reserved20_MASK) - #define PORT_EDFR_EDF21_MASK (0x200000U) #define PORT_EDFR_EDF21_SHIFT (21U) /*! EDF21 - EFT Detect Flag @@ -63525,14 +56746,6 @@ typedef struct { */ #define PORT_EDFR_EDF21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK) -#define PORT_EDFR_Reserved21_MASK (0x200000U) -#define PORT_EDFR_Reserved21_SHIFT (21U) -/*! Reserved21 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved21_SHIFT)) & PORT_EDFR_Reserved21_MASK) - #define PORT_EDFR_EDF22_MASK (0x400000U) #define PORT_EDFR_EDF22_SHIFT (22U) /*! EDF22 - EFT Detect Flag @@ -63541,14 +56754,6 @@ typedef struct { */ #define PORT_EDFR_EDF22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK) -#define PORT_EDFR_Reserved22_MASK (0x400000U) -#define PORT_EDFR_Reserved22_SHIFT (22U) -/*! Reserved22 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved22_SHIFT)) & PORT_EDFR_Reserved22_MASK) - #define PORT_EDFR_EDF23_MASK (0x800000U) #define PORT_EDFR_EDF23_SHIFT (23U) /*! EDF23 - EFT Detect Flag @@ -63557,14 +56762,6 @@ typedef struct { */ #define PORT_EDFR_EDF23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK) -#define PORT_EDFR_Reserved23_MASK (0x800000U) -#define PORT_EDFR_Reserved23_SHIFT (23U) -/*! Reserved23 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved23_SHIFT)) & PORT_EDFR_Reserved23_MASK) - #define PORT_EDFR_EDF24_MASK (0x1000000U) #define PORT_EDFR_EDF24_SHIFT (24U) /*! EDF24 - EFT Detect Flag @@ -63573,14 +56770,6 @@ typedef struct { */ #define PORT_EDFR_EDF24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK) -#define PORT_EDFR_Reserved24_MASK (0x1000000U) -#define PORT_EDFR_Reserved24_SHIFT (24U) -/*! Reserved24 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved24_SHIFT)) & PORT_EDFR_Reserved24_MASK) - #define PORT_EDFR_EDF25_MASK (0x2000000U) #define PORT_EDFR_EDF25_SHIFT (25U) /*! EDF25 - EFT Detect Flag @@ -63589,14 +56778,6 @@ typedef struct { */ #define PORT_EDFR_EDF25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK) -#define PORT_EDFR_Reserved25_MASK (0x2000000U) -#define PORT_EDFR_Reserved25_SHIFT (25U) -/*! Reserved25 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved25_SHIFT)) & PORT_EDFR_Reserved25_MASK) - #define PORT_EDFR_EDF26_MASK (0x4000000U) #define PORT_EDFR_EDF26_SHIFT (26U) /*! EDF26 - EFT Detect Flag @@ -63605,14 +56786,6 @@ typedef struct { */ #define PORT_EDFR_EDF26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK) -#define PORT_EDFR_Reserved26_MASK (0x4000000U) -#define PORT_EDFR_Reserved26_SHIFT (26U) -/*! Reserved26 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved26_SHIFT)) & PORT_EDFR_Reserved26_MASK) - #define PORT_EDFR_EDF27_MASK (0x8000000U) #define PORT_EDFR_EDF27_SHIFT (27U) /*! EDF27 - EFT Detect Flag @@ -63621,14 +56794,6 @@ typedef struct { */ #define PORT_EDFR_EDF27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK) -#define PORT_EDFR_Reserved27_MASK (0x8000000U) -#define PORT_EDFR_Reserved27_SHIFT (27U) -/*! Reserved27 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved27_SHIFT)) & PORT_EDFR_Reserved27_MASK) - #define PORT_EDFR_EDF28_MASK (0x10000000U) #define PORT_EDFR_EDF28_SHIFT (28U) /*! EDF28 - EFT Detect Flag @@ -63637,14 +56802,6 @@ typedef struct { */ #define PORT_EDFR_EDF28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK) -#define PORT_EDFR_Reserved28_MASK (0x10000000U) -#define PORT_EDFR_Reserved28_SHIFT (28U) -/*! Reserved28 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved28_SHIFT)) & PORT_EDFR_Reserved28_MASK) - #define PORT_EDFR_EDF29_MASK (0x20000000U) #define PORT_EDFR_EDF29_SHIFT (29U) /*! EDF29 - EFT Detect Flag @@ -63653,14 +56810,6 @@ typedef struct { */ #define PORT_EDFR_EDF29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK) -#define PORT_EDFR_Reserved29_MASK (0x20000000U) -#define PORT_EDFR_Reserved29_SHIFT (29U) -/*! Reserved29 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved29_SHIFT)) & PORT_EDFR_Reserved29_MASK) - #define PORT_EDFR_EDF30_MASK (0x40000000U) #define PORT_EDFR_EDF30_SHIFT (30U) /*! EDF30 - EFT Detect Flag @@ -63669,14 +56818,6 @@ typedef struct { */ #define PORT_EDFR_EDF30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK) -#define PORT_EDFR_Reserved30_MASK (0x40000000U) -#define PORT_EDFR_Reserved30_SHIFT (30U) -/*! Reserved30 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved30_SHIFT)) & PORT_EDFR_Reserved30_MASK) - #define PORT_EDFR_EDF31_MASK (0x80000000U) #define PORT_EDFR_EDF31_SHIFT (31U) /*! EDF31 - EFT Detect Flag @@ -63684,14 +56825,6 @@ typedef struct { * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK) - -#define PORT_EDFR_Reserved31_MASK (0x80000000U) -#define PORT_EDFR_Reserved31_SHIFT (31U) -/*! Reserved31 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved31_SHIFT)) & PORT_EDFR_Reserved31_MASK) /*! @} */ /*! @name EDIER - EFT Detect Interrupt Enable */ @@ -63769,14 +56902,6 @@ typedef struct { */ #define PORT_EDIER_EDIE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK) -#define PORT_EDIER_Reserved8_MASK (0x100U) -#define PORT_EDIER_Reserved8_SHIFT (8U) -/*! Reserved8 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved8_SHIFT)) & PORT_EDIER_Reserved8_MASK) - #define PORT_EDIER_EDIE9_MASK (0x200U) #define PORT_EDIER_EDIE9_SHIFT (9U) /*! EDIE9 - EFT Detect Interrupt Enable @@ -63785,14 +56910,6 @@ typedef struct { */ #define PORT_EDIER_EDIE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK) -#define PORT_EDIER_Reserved9_MASK (0x200U) -#define PORT_EDIER_Reserved9_SHIFT (9U) -/*! Reserved9 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved9_SHIFT)) & PORT_EDIER_Reserved9_MASK) - #define PORT_EDIER_EDIE10_MASK (0x400U) #define PORT_EDIER_EDIE10_SHIFT (10U) /*! EDIE10 - EFT Detect Interrupt Enable @@ -63801,14 +56918,6 @@ typedef struct { */ #define PORT_EDIER_EDIE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK) -#define PORT_EDIER_Reserved10_MASK (0x400U) -#define PORT_EDIER_Reserved10_SHIFT (10U) -/*! Reserved10 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved10_SHIFT)) & PORT_EDIER_Reserved10_MASK) - #define PORT_EDIER_EDIE11_MASK (0x800U) #define PORT_EDIER_EDIE11_SHIFT (11U) /*! EDIE11 - EFT Detect Interrupt Enable @@ -63817,14 +56926,6 @@ typedef struct { */ #define PORT_EDIER_EDIE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK) -#define PORT_EDIER_Reserved11_MASK (0x800U) -#define PORT_EDIER_Reserved11_SHIFT (11U) -/*! Reserved11 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved11_SHIFT)) & PORT_EDIER_Reserved11_MASK) - #define PORT_EDIER_EDIE12_MASK (0x1000U) #define PORT_EDIER_EDIE12_SHIFT (12U) /*! EDIE12 - EFT Detect Interrupt Enable @@ -63833,14 +56934,6 @@ typedef struct { */ #define PORT_EDIER_EDIE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK) -#define PORT_EDIER_Reserved12_MASK (0x1000U) -#define PORT_EDIER_Reserved12_SHIFT (12U) -/*! Reserved12 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved12_SHIFT)) & PORT_EDIER_Reserved12_MASK) - #define PORT_EDIER_EDIE13_MASK (0x2000U) #define PORT_EDIER_EDIE13_SHIFT (13U) /*! EDIE13 - EFT Detect Interrupt Enable @@ -63849,14 +56942,6 @@ typedef struct { */ #define PORT_EDIER_EDIE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK) -#define PORT_EDIER_Reserved13_MASK (0x2000U) -#define PORT_EDIER_Reserved13_SHIFT (13U) -/*! Reserved13 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved13_SHIFT)) & PORT_EDIER_Reserved13_MASK) - #define PORT_EDIER_EDIE14_MASK (0x4000U) #define PORT_EDIER_EDIE14_SHIFT (14U) /*! EDIE14 - EFT Detect Interrupt Enable @@ -63865,14 +56950,6 @@ typedef struct { */ #define PORT_EDIER_EDIE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK) -#define PORT_EDIER_Reserved14_MASK (0x4000U) -#define PORT_EDIER_Reserved14_SHIFT (14U) -/*! Reserved14 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved14_SHIFT)) & PORT_EDIER_Reserved14_MASK) - #define PORT_EDIER_EDIE15_MASK (0x8000U) #define PORT_EDIER_EDIE15_SHIFT (15U) /*! EDIE15 - EFT Detect Interrupt Enable @@ -63881,14 +56958,6 @@ typedef struct { */ #define PORT_EDIER_EDIE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK) -#define PORT_EDIER_Reserved15_MASK (0x8000U) -#define PORT_EDIER_Reserved15_SHIFT (15U) -/*! Reserved15 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved15_SHIFT)) & PORT_EDIER_Reserved15_MASK) - #define PORT_EDIER_EDIE16_MASK (0x10000U) #define PORT_EDIER_EDIE16_SHIFT (16U) /*! EDIE16 - EFT Detect Interrupt Enable @@ -63897,14 +56966,6 @@ typedef struct { */ #define PORT_EDIER_EDIE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK) -#define PORT_EDIER_Reserved16_MASK (0x10000U) -#define PORT_EDIER_Reserved16_SHIFT (16U) -/*! Reserved16 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved16_SHIFT)) & PORT_EDIER_Reserved16_MASK) - #define PORT_EDIER_EDIE17_MASK (0x20000U) #define PORT_EDIER_EDIE17_SHIFT (17U) /*! EDIE17 - EFT Detect Interrupt Enable @@ -63913,14 +56974,6 @@ typedef struct { */ #define PORT_EDIER_EDIE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK) -#define PORT_EDIER_Reserved17_MASK (0x20000U) -#define PORT_EDIER_Reserved17_SHIFT (17U) -/*! Reserved17 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved17_SHIFT)) & PORT_EDIER_Reserved17_MASK) - #define PORT_EDIER_EDIE18_MASK (0x40000U) #define PORT_EDIER_EDIE18_SHIFT (18U) /*! EDIE18 - EFT Detect Interrupt Enable @@ -63929,14 +56982,6 @@ typedef struct { */ #define PORT_EDIER_EDIE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK) -#define PORT_EDIER_Reserved18_MASK (0x40000U) -#define PORT_EDIER_Reserved18_SHIFT (18U) -/*! Reserved18 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved18_SHIFT)) & PORT_EDIER_Reserved18_MASK) - #define PORT_EDIER_EDIE19_MASK (0x80000U) #define PORT_EDIER_EDIE19_SHIFT (19U) /*! EDIE19 - EFT Detect Interrupt Enable @@ -63945,14 +56990,6 @@ typedef struct { */ #define PORT_EDIER_EDIE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK) -#define PORT_EDIER_Reserved19_MASK (0x80000U) -#define PORT_EDIER_Reserved19_SHIFT (19U) -/*! Reserved19 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved19_SHIFT)) & PORT_EDIER_Reserved19_MASK) - #define PORT_EDIER_EDIE20_MASK (0x100000U) #define PORT_EDIER_EDIE20_SHIFT (20U) /*! EDIE20 - EFT Detect Interrupt Enable @@ -63961,14 +56998,6 @@ typedef struct { */ #define PORT_EDIER_EDIE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK) -#define PORT_EDIER_Reserved20_MASK (0x100000U) -#define PORT_EDIER_Reserved20_SHIFT (20U) -/*! Reserved20 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved20_SHIFT)) & PORT_EDIER_Reserved20_MASK) - #define PORT_EDIER_EDIE21_MASK (0x200000U) #define PORT_EDIER_EDIE21_SHIFT (21U) /*! EDIE21 - EFT Detect Interrupt Enable @@ -63977,14 +57006,6 @@ typedef struct { */ #define PORT_EDIER_EDIE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK) -#define PORT_EDIER_Reserved21_MASK (0x200000U) -#define PORT_EDIER_Reserved21_SHIFT (21U) -/*! Reserved21 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved21_SHIFT)) & PORT_EDIER_Reserved21_MASK) - #define PORT_EDIER_EDIE22_MASK (0x400000U) #define PORT_EDIER_EDIE22_SHIFT (22U) /*! EDIE22 - EFT Detect Interrupt Enable @@ -63993,14 +57014,6 @@ typedef struct { */ #define PORT_EDIER_EDIE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK) -#define PORT_EDIER_Reserved22_MASK (0x400000U) -#define PORT_EDIER_Reserved22_SHIFT (22U) -/*! Reserved22 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved22_SHIFT)) & PORT_EDIER_Reserved22_MASK) - #define PORT_EDIER_EDIE23_MASK (0x800000U) #define PORT_EDIER_EDIE23_SHIFT (23U) /*! EDIE23 - EFT Detect Interrupt Enable @@ -64009,14 +57022,6 @@ typedef struct { */ #define PORT_EDIER_EDIE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK) -#define PORT_EDIER_Reserved23_MASK (0x800000U) -#define PORT_EDIER_Reserved23_SHIFT (23U) -/*! Reserved23 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved23_SHIFT)) & PORT_EDIER_Reserved23_MASK) - #define PORT_EDIER_EDIE24_MASK (0x1000000U) #define PORT_EDIER_EDIE24_SHIFT (24U) /*! EDIE24 - EFT Detect Interrupt Enable @@ -64025,14 +57030,6 @@ typedef struct { */ #define PORT_EDIER_EDIE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK) -#define PORT_EDIER_Reserved24_MASK (0x1000000U) -#define PORT_EDIER_Reserved24_SHIFT (24U) -/*! Reserved24 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved24_SHIFT)) & PORT_EDIER_Reserved24_MASK) - #define PORT_EDIER_EDIE25_MASK (0x2000000U) #define PORT_EDIER_EDIE25_SHIFT (25U) /*! EDIE25 - EFT Detect Interrupt Enable @@ -64041,14 +57038,6 @@ typedef struct { */ #define PORT_EDIER_EDIE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK) -#define PORT_EDIER_Reserved25_MASK (0x2000000U) -#define PORT_EDIER_Reserved25_SHIFT (25U) -/*! Reserved25 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved25_SHIFT)) & PORT_EDIER_Reserved25_MASK) - #define PORT_EDIER_EDIE26_MASK (0x4000000U) #define PORT_EDIER_EDIE26_SHIFT (26U) /*! EDIE26 - EFT Detect Interrupt Enable @@ -64057,14 +57046,6 @@ typedef struct { */ #define PORT_EDIER_EDIE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK) -#define PORT_EDIER_Reserved26_MASK (0x4000000U) -#define PORT_EDIER_Reserved26_SHIFT (26U) -/*! Reserved26 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved26_SHIFT)) & PORT_EDIER_Reserved26_MASK) - #define PORT_EDIER_EDIE27_MASK (0x8000000U) #define PORT_EDIER_EDIE27_SHIFT (27U) /*! EDIE27 - EFT Detect Interrupt Enable @@ -64073,14 +57054,6 @@ typedef struct { */ #define PORT_EDIER_EDIE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK) -#define PORT_EDIER_Reserved27_MASK (0x8000000U) -#define PORT_EDIER_Reserved27_SHIFT (27U) -/*! Reserved27 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved27_SHIFT)) & PORT_EDIER_Reserved27_MASK) - #define PORT_EDIER_EDIE28_MASK (0x10000000U) #define PORT_EDIER_EDIE28_SHIFT (28U) /*! EDIE28 - EFT Detect Interrupt Enable @@ -64089,14 +57062,6 @@ typedef struct { */ #define PORT_EDIER_EDIE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK) -#define PORT_EDIER_Reserved28_MASK (0x10000000U) -#define PORT_EDIER_Reserved28_SHIFT (28U) -/*! Reserved28 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved28_SHIFT)) & PORT_EDIER_Reserved28_MASK) - #define PORT_EDIER_EDIE29_MASK (0x20000000U) #define PORT_EDIER_EDIE29_SHIFT (29U) /*! EDIE29 - EFT Detect Interrupt Enable @@ -64105,14 +57070,6 @@ typedef struct { */ #define PORT_EDIER_EDIE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK) -#define PORT_EDIER_Reserved29_MASK (0x20000000U) -#define PORT_EDIER_Reserved29_SHIFT (29U) -/*! Reserved29 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved29_SHIFT)) & PORT_EDIER_Reserved29_MASK) - #define PORT_EDIER_EDIE30_MASK (0x40000000U) #define PORT_EDIER_EDIE30_SHIFT (30U) /*! EDIE30 - EFT Detect Interrupt Enable @@ -64121,14 +57078,6 @@ typedef struct { */ #define PORT_EDIER_EDIE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK) -#define PORT_EDIER_Reserved30_MASK (0x40000000U) -#define PORT_EDIER_Reserved30_SHIFT (30U) -/*! Reserved30 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved30_SHIFT)) & PORT_EDIER_Reserved30_MASK) - #define PORT_EDIER_EDIE31_MASK (0x80000000U) #define PORT_EDIER_EDIE31_SHIFT (31U) /*! EDIE31 - EFT Detect Interrupt Enable @@ -64136,14 +57085,6 @@ typedef struct { * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK) - -#define PORT_EDIER_Reserved31_MASK (0x80000000U) -#define PORT_EDIER_Reserved31_SHIFT (31U) -/*! Reserved31 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved31_SHIFT)) & PORT_EDIER_Reserved31_MASK) /*! @} */ /*! @name EDCR - EFT Detect Clear */ @@ -64194,7 +57135,7 @@ typedef struct { #define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) /*! @} */ -/*! @name PCR - Pin Control 0..Pin Control 23 */ +/*! @name PCR - Pin Control 0..Pin Control 31 */ /*! @{ */ #define PORT_PCR_PS_MASK (0x1U) @@ -64253,7 +57194,7 @@ typedef struct { */ #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) -#define PORT_PCR_MUX_MASK (0xF00U) +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define PORT_PCR_MUX_SHIFT (8U) /*! MUX - Pin Multiplex Control * 0b0000..Alternative 0 (GPIO) @@ -64271,7 +57212,7 @@ typedef struct { * 0b1100..Alternative 12 (chip-specific) * 0b1101..Alternative 13 (chip-specific) */ -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define PORT_PCR_IBE_MASK (0x1000U) #define PORT_PCR_IBE_SHIFT (12U) @@ -64416,20 +57357,20 @@ typedef struct { __IO uint32_t OUTFORMAT; /**< Output Format, offset: 0x4 */ __IO uint32_t TMPBASE; /**< Temporary Base, offset: 0x8 */ __IO uint32_t TMPFORMAT; /**< Temporary Format, offset: 0xC */ - __IO uint32_t INABASE; /**< Input A base, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Input B base, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + __IO uint32_t INABASE; /**< Input A Base, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A Format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Input B Base, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B Format, offset: 0x1C */ uint8_t RESERVED_0[224]; __IO uint32_t CONTROL; /**< Control, offset: 0x100 */ __IO uint32_t LENGTH; /**< Length, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Coprocessor Pre-scale, offset: 0x108 */ + __IO uint32_t CPPRE; /**< Coprocessor Prescale, offset: 0x108 */ __IO uint32_t MISC; /**< Miscellaneous, offset: 0x10C */ __IO uint32_t CURSORY; /**< Cursory, offset: 0x110 */ uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< CORDIC input X, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< CORDIC input Y, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< CORDIC input Z, offset: 0x188 */ + __IO uint32_t CORDIC_X; /**< CORDIC Input X, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< CORDIC Input Y, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< CORDIC Input Z, offset: 0x188 */ __IO uint32_t ERRSTAT; /**< Error Status, offset: 0x18C */ __IO uint32_t INTREN; /**< Interrupt Enable, offset: 0x190 */ __IO uint32_t EVENTEN; /**< Event Enable, offset: 0x194 */ @@ -64453,7 +57394,7 @@ typedef struct { #define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -/*! OUTBASE - Base address for the output region */ +/*! OUTBASE - Output Region Base Address */ #define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) /*! @} */ @@ -64462,25 +57403,27 @@ typedef struct { #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -/*! OUT_FORMATINT - Output internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! OUT_FORMATINT - Output Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -/*! OUT_FORMATEXT - Output external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! OUT_FORMATEXT - Output External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -/*! OUT_SCALER - Output scaler value */ +/*! OUT_SCALER - 8-bit Scaling Value for Result Data */ #define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) /*! @} */ @@ -64489,7 +57432,7 @@ typedef struct { #define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -/*! TMPBASE - Base address for the temporary region */ +/*! TMPBASE - Base Address for the Temporary Region */ #define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) /*! @} */ @@ -64498,97 +57441,103 @@ typedef struct { #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -/*! TMP_FORMATINT - Temporary internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! TMP_FORMATINT - Temporary Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -/*! TMP_FORMATEXT - Temporary external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! TMP_FORMATEXT - Temporary External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -/*! TMP_SCALER - Temporary scaler value */ +/*! TMP_SCALER - Scaling Value for Temporary Data. */ #define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) /*! @} */ -/*! @name INABASE - Input A base */ +/*! @name INABASE - Input A Base */ /*! @{ */ #define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INABASE_INABASE_SHIFT (0U) -/*! INABASE - Input A base */ +/*! INABASE - Input A Base */ #define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) /*! @} */ -/*! @name INAFORMAT - Input A format */ +/*! @name INAFORMAT - Input A Format */ /*! @{ */ #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -/*! INA_FORMATINT - Input A internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INA_FORMATINT - Input A Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -/*! INA_FORMATEXT - Input A external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INA_FORMATEXT - Input A External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) #define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -/*! INA_SCALER - Input A scaler value */ +/*! INA_SCALER - Input A Scaler Value */ #define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) /*! @} */ -/*! @name INBBASE - Input B base */ +/*! @name INBBASE - Input B Base */ /*! @{ */ #define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -/*! INBBASE - Input B base */ +/*! INBBASE - Input B Base */ #define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) /*! @} */ -/*! @name INBFORMAT - Input B format */ +/*! @name INBFORMAT - Input B Format */ /*! @{ */ #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -/*! INB_FORMATINT - Input B internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INB_FORMATINT - Input B Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -/*! INB_FORMATEXT - Input B external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INB_FORMATEXT - Input B External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) #define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -/*! INB_SCALER - Input B scaler value */ +/*! INB_SCALER - Input B Scaler */ #define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) /*! @} */ @@ -64597,18 +57546,25 @@ typedef struct { #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -/*! DECODE_OPCODE - Decode opcode */ +/*! DECODE_OPCODE - Decode Opcode */ #define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -/*! DECODE_MACHINE - Decode machine */ +/*! DECODE_MACHINE - Decode Machine + * 0b0000..Coprocessor + * 0b0001..Matrix engine + * 0b0010..Transform engine + * 0b0011..Filter engine + * 0b0101..CORDIC engine + * 0b0100, 0b0110-0b1111.. + */ #define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) #define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) #define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -/*! INST_BUSY - Instruction busy - * 0b1..busy +/*! INST_BUSY - Instruction Busy + * 0b1..Busy * 0b0..Not busy */ #define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) @@ -64623,17 +57579,17 @@ typedef struct { #define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) /*! @} */ -/*! @name CPPRE - Coprocessor Pre-scale */ +/*! @name CPPRE - Coprocessor Prescale */ /*! @{ */ #define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -/*! CPPRE_IN - Input */ +/*! CPPRE_IN - Prescaling Input */ #define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) #define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -/*! CPPRE_OUT - Output */ +/*! CPPRE_OUT - Postscaling Output */ #define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) #define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) @@ -64658,7 +57614,7 @@ typedef struct { #define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) #define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -/*! INST_MISC - For matrix operations used for scaling factor */ +/*! INST_MISC - Scaling Factor */ #define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) /*! @} */ @@ -64668,36 +57624,36 @@ typedef struct { #define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) #define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) /*! CURSORY - Cursory Mode - * 0b0..Disable cursory mode - * 0b1..Enable cursory Mode + * 0b0..Disable cursory mode, full floating-point accuracy (24-bit mantissa + 2 bits before rounding). + * 0b1..Enable cursory Mode, 16-bit mantissa (bottom bits are zeroed for inputs and outputs of MACs). */ #define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) /*! @} */ -/*! @name CORDIC_X - CORDIC input X */ +/*! @name CORDIC_X - CORDIC Input X */ /*! @{ */ #define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -/*! CORDIC_X - CORDIC input x */ +/*! CORDIC_X - CORDIC Input X */ #define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) /*! @} */ -/*! @name CORDIC_Y - CORDIC input Y */ +/*! @name CORDIC_Y - CORDIC Input Y */ /*! @{ */ #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -/*! CORDIC_Y - CORDIC input y */ +/*! CORDIC_Y - CORDIC Input Y */ #define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) /*! @} */ -/*! @name CORDIC_Z - CORDIC input Z */ +/*! @name CORDIC_Z - CORDIC Input Z */ /*! @{ */ #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -/*! CORDIC_Z - CORDIC input z */ +/*! CORDIC_Z - CORDIC Input Z */ #define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) /*! @} */ @@ -64706,25 +57662,25 @@ typedef struct { #define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -/*! OVERFLOW - Floating point overflow +/*! OVERFLOW - Floating-point Overflow * 0b0..No error - * 0b1..Error on floating point overflow + * 0b1..Error on floating-point overflow */ #define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) #define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) #define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -/*! NAN - Floating Point NaN +/*! NAN - Floating-Point Not-a-Number (NaN) * 0b0..No error - * 0b1..Error on Floating Point NaN + * 0b1..Error on floating-point NaN */ #define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -/*! FIXEDOVERFLOW - Fixed point overflow +/*! FIXEDOVERFLOW - Fixed-point Overflow * 0b0..No error - * 0b1..Error on fixed point overflow + * 0b1..Error on fixed-point overflow */ #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) @@ -64738,7 +57694,7 @@ typedef struct { #define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -/*! BUSERROR - Bus error +/*! BUSERROR - Bus Error * 0b0..No error * 0b1..Error on bus */ @@ -64750,7 +57706,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -/*! INTR_OFLOW - Interrupt floating point overflow +/*! INTR_OFLOW - Interrupt Floating-point Overflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64758,7 +57714,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) #define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -/*! INTR_NAN - Interrupt floating point NaN +/*! INTR_NAN - Interrupt Floating-point NaN * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64766,7 +57722,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) #define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -/*! INTR_FIXED - Interrupt on fixed-point overflow +/*! INTR_FIXED - Interrupt on Fixed-point Overflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64774,7 +57730,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -/*! INTR_UFLOW - Interrupt on subnormal truncation +/*! INTR_UFLOW - Interrupt on Underflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64782,7 +57738,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) #define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -/*! INTR_BERR - Interrupt on AHBM bus error +/*! INTR_BERR - Interrupt on AHBM Bus Error * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64790,7 +57746,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) #define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -/*! INTR_COMP - Interrupt on instruction completion +/*! INTR_COMP - Interrupt on Instruction Completion * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64802,7 +57758,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -/*! EVENT_OFLOW - Event trigger on floating point overflow +/*! EVENT_OFLOW - Event Trigger on Floating-point Overflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64810,7 +57766,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -/*! EVENT_NAN - Event trigger on floating point NaN +/*! EVENT_NAN - Event Trigger on Floating-Point NaN * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64818,7 +57774,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -/*! EVENT_FIXED - Event trigger on fixed-point overflow +/*! EVENT_FIXED - Event Trigger on Fixed-point Overflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64826,7 +57782,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -/*! EVENT_UFLOW - Event trigger on subnormal truncation +/*! EVENT_UFLOW - Event Trigger on Underflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64834,7 +57790,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -/*! EVENT_BERR - Event trigger on AHBM bus error +/*! EVENT_BERR - Event Trigger on AHBM Bus Error * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64842,7 +57798,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -/*! EVENT_COMP - Event trigger on instruction completion +/*! EVENT_COMP - Event Trigger on Instruction Completion * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64919,6 +57875,8 @@ typedef struct { /** Array initializer of POWERQUAD peripheral base pointers */ #define POWERQUAD_BASE_PTRS { POWERQUAD } #endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } /*! * @} @@ -64962,7 +57920,10 @@ typedef struct { __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ - uint8_t RESERVED_7[512]; + __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ + __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ + __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ + uint8_t RESERVED_7[500]; __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ uint8_t RESERVED_8[208]; @@ -65157,8 +58118,8 @@ typedef struct { #define PUF_AR_ALLOW_STOP_MASK (0x20U) #define PUF_AR_ALLOW_STOP_SHIFT (5U) /*! ALLOW_STOP - Stop operation - * 0b1..Indicates that the Stop operation is allowed * 0b0..Indicates that the Stop operation is not allowed + * 0b1..Indicates that the Stop operation is allowed */ #define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) @@ -65484,22 +58445,136 @@ typedef struct { #define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) /*! @} */ +/*! @name CONFIG - PUF command blocking configuration */ +/*! @{ */ + +#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) +#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) +/*! DIS_PUF_ENROLL - Disable PUF enroll command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) + +#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) +#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) +/*! DIS_PUF_START - Disable PUF start command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) + +#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) +#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) +/*! DIS_PUF_STOP - Disable PUF stop command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) + +#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) +#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) +/*! DIS_PUF_GET_KEY - Disable PUF get key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) +/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) +/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) +/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) +/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) + +#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) +#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) +/*! DIS_PUF_TEST - Disable PUF test command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) +/*! @} */ + +/*! @name SEC_LOCK - Security level lock */ +/*! @{ */ + +#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) +#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) +/*! SEC_LEVEL - Security Level + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) +/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) +#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Pattern */ +#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name APP_CTX_MASK - Application defined context mask */ +/*! @{ */ + +#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) +#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) +/*! APP_CTX_MASK - Application defined context */ +#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) +/*! @} */ + /*! @name SRAM_CFG - SRAM Configuration */ /*! @{ */ #define PUF_SRAM_CFG_ENABLE_MASK (0x1U) #define PUF_SRAM_CFG_ENABLE_SHIFT (0U) /*! ENABLE - PUF SRAM Controller activation + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) #define PUF_SRAM_CFG_CKGATING_MASK (0x4U) #define PUF_SRAM_CFG_CKGATING_SHIFT (2U) /*! CKGATING - PUF SRAM Clock Gating control + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) /*! @} */ @@ -65561,16 +58636,16 @@ typedef struct { #define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) #define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) /*! READY - READY Interrupt Enable + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) /*! SRAM_APB_ERR - APB_ERR Interrupt Enable + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) /*! @} */ @@ -65685,222 +58760,6 @@ typedef struct { */ /* end of group PUF_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- PUF_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_CTRL_Peripheral_Access_Layer PUF_CTRL Peripheral Access Layer - * @{ - */ - -/** PUF_CTRL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[256]; - __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ - __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ - __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ -} PUF_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- PUF_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_CTRL_Register_Masks PUF_CTRL Register Masks - * @{ - */ - -/*! @name CONFIG - PUF command blocking configuration */ -/*! @{ */ - -#define PUF_CTRL_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) -#define PUF_CTRL_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) -/*! DIS_PUF_ENROLL - Disable PUF enroll command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_ENROLL_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_START_MASK (0x4U) -#define PUF_CTRL_CONFIG_DIS_PUF_START_SHIFT (2U) -/*! DIS_PUF_START - Disable PUF start command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_START_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_STOP_MASK (0x20U) -#define PUF_CTRL_CONFIG_DIS_PUF_STOP_SHIFT (5U) -/*! DIS_PUF_STOP - Disable PUF stop command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_STOP_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) -#define PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) -/*! DIS_PUF_GET_KEY - Disable PUF get key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) -#define PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) -/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) -/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) -#define PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) -/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) -/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) -#define PUF_CTRL_CONFIG_DIS_PUF_TEST_SHIFT (31U) -/*! DIS_PUF_TEST - Disable PUF test command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_TEST_MASK) -/*! @} */ - -/*! @name SEC_LOCK - Security level lock */ -/*! @{ */ - -#define PUF_CTRL_SEC_LOCK_SEC_LEVEL_MASK (0x3U) -#define PUF_CTRL_SEC_LOCK_SEC_LEVEL_SHIFT (0U) -/*! SEC_LEVEL - Security Level - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define PUF_CTRL_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_CTRL_SEC_LOCK_SEC_LEVEL_MASK) - -#define PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) -#define PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) -/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level - * 0b00..Secure and privileged Master - * 0b01..Secure and non-privileged Master - * 0b10..Non-secure and privileged Master - * 0b11..Non-secure and non-privileged Master - */ -#define PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) - -#define PUF_CTRL_SEC_LOCK_PATTERN_MASK (0xFFF0U) -#define PUF_CTRL_SEC_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Pattern */ -#define PUF_CTRL_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SEC_LOCK_PATTERN_SHIFT)) & PUF_CTRL_SEC_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name APP_CTX_MASK - Application defined context mask */ -/*! @{ */ - -#define PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) -#define PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) -/*! APP_CTX_MASK - Application defined context */ -#define PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_CTRL_Register_Masks */ - - -/* PUF_CTRL - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral PUF_CTRL base address */ - #define PUF_CTRL_BASE (0x5002C000u) - /** Peripheral PUF_CTRL base address */ - #define PUF_CTRL_BASE_NS (0x4002C000u) - /** Peripheral PUF_CTRL base pointer */ - #define PUF_CTRL ((PUF_CTRL_Type *)PUF_CTRL_BASE) - /** Peripheral PUF_CTRL base pointer */ - #define PUF_CTRL_NS ((PUF_CTRL_Type *)PUF_CTRL_BASE_NS) - /** Peripheral PUF_CTRL_ALIAS1 base address */ - #define PUF_CTRL_ALIAS1_BASE (0x5002D000u) - /** Peripheral PUF_CTRL_ALIAS1 base address */ - #define PUF_CTRL_ALIAS1_BASE_NS (0x4002D000u) - /** Peripheral PUF_CTRL_ALIAS1 base pointer */ - #define PUF_CTRL_ALIAS1 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS1_BASE) - /** Peripheral PUF_CTRL_ALIAS1 base pointer */ - #define PUF_CTRL_ALIAS1_NS ((PUF_CTRL_Type *)PUF_CTRL_ALIAS1_BASE_NS) - /** Peripheral PUF_CTRL_ALIAS2 base address */ - #define PUF_CTRL_ALIAS2_BASE (0x5002E000u) - /** Peripheral PUF_CTRL_ALIAS2 base address */ - #define PUF_CTRL_ALIAS2_BASE_NS (0x4002E000u) - /** Peripheral PUF_CTRL_ALIAS2 base pointer */ - #define PUF_CTRL_ALIAS2 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS2_BASE) - /** Peripheral PUF_CTRL_ALIAS2 base pointer */ - #define PUF_CTRL_ALIAS2_NS ((PUF_CTRL_Type *)PUF_CTRL_ALIAS2_BASE_NS) - /** Peripheral PUF_CTRL_ALIAS3 base address */ - #define PUF_CTRL_ALIAS3_BASE (0x5002F000u) - /** Peripheral PUF_CTRL_ALIAS3 base address */ - #define PUF_CTRL_ALIAS3_BASE_NS (0x4002F000u) - /** Peripheral PUF_CTRL_ALIAS3 base pointer */ - #define PUF_CTRL_ALIAS3 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS3_BASE) - /** Peripheral PUF_CTRL_ALIAS3 base pointer */ - #define PUF_CTRL_ALIAS3_NS ((PUF_CTRL_Type *)PUF_CTRL_ALIAS3_BASE_NS) - /** Array initializer of PUF_CTRL peripheral base addresses */ - #define PUF_CTRL_BASE_ADDRS { PUF_CTRL_BASE, PUF_CTRL_ALIAS1_BASE, PUF_CTRL_ALIAS2_BASE, PUF_CTRL_ALIAS3_BASE } - /** Array initializer of PUF_CTRL peripheral base pointers */ - #define PUF_CTRL_BASE_PTRS { PUF_CTRL, PUF_CTRL_ALIAS1, PUF_CTRL_ALIAS2, PUF_CTRL_ALIAS3 } - /** Array initializer of PUF_CTRL peripheral base addresses */ - #define PUF_CTRL_BASE_ADDRS_NS { PUF_CTRL_BASE_NS, PUF_CTRL_ALIAS1_BASE_NS, PUF_CTRL_ALIAS2_BASE_NS, PUF_CTRL_ALIAS3_BASE_NS } - /** Array initializer of PUF_CTRL peripheral base pointers */ - #define PUF_CTRL_BASE_PTRS_NS { PUF_CTRL_NS, PUF_CTRL_ALIAS1_NS, PUF_CTRL_ALIAS2_NS, PUF_CTRL_ALIAS3_NS } -#else - /** Peripheral PUF_CTRL base address */ - #define PUF_CTRL_BASE (0x4002C000u) - /** Peripheral PUF_CTRL base pointer */ - #define PUF_CTRL ((PUF_CTRL_Type *)PUF_CTRL_BASE) - /** Peripheral PUF_CTRL_ALIAS1 base address */ - #define PUF_CTRL_ALIAS1_BASE (0x4002D000u) - /** Peripheral PUF_CTRL_ALIAS1 base pointer */ - #define PUF_CTRL_ALIAS1 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS1_BASE) - /** Peripheral PUF_CTRL_ALIAS2 base address */ - #define PUF_CTRL_ALIAS2_BASE (0x4002E000u) - /** Peripheral PUF_CTRL_ALIAS2 base pointer */ - #define PUF_CTRL_ALIAS2 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS2_BASE) - /** Peripheral PUF_CTRL_ALIAS3 base address */ - #define PUF_CTRL_ALIAS3_BASE (0x4002F000u) - /** Peripheral PUF_CTRL_ALIAS3 base pointer */ - #define PUF_CTRL_ALIAS3 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS3_BASE) - /** Array initializer of PUF_CTRL peripheral base addresses */ - #define PUF_CTRL_BASE_ADDRS { PUF_CTRL_BASE, PUF_CTRL_ALIAS1_BASE, PUF_CTRL_ALIAS2_BASE, PUF_CTRL_ALIAS3_BASE } - /** Array initializer of PUF_CTRL peripheral base pointers */ - #define PUF_CTRL_BASE_PTRS { PUF_CTRL, PUF_CTRL_ALIAS1, PUF_CTRL_ALIAS2, PUF_CTRL_ALIAS3 } -#endif - -/*! - * @} - */ /* end of group PUF_CTRL_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -67197,12 +60056,12 @@ typedef struct { #define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) -/*! CAPTA_FILT_PER - Fault Filter Period */ +/*! CAPTA_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) #define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) -/*! CAPTA_FILT_CNT - Fault Filter Count */ +/*! CAPTA_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) /*! @} */ @@ -67214,12 +60073,12 @@ typedef struct { #define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) -/*! CAPTB_FILT_PER - Fault Filter Period */ +/*! CAPTB_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) #define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) -/*! CAPTB_FILT_CNT - Fault Filter Count */ +/*! CAPTB_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) /*! @} */ @@ -67231,12 +60090,12 @@ typedef struct { #define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) -/*! CAPTX_FILT_PER - Fault Filter Period */ +/*! CAPTX_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) #define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) -/*! CAPTX_FILT_CNT - Fault Filter Count */ +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) /*! @} */ @@ -67248,26 +60107,17 @@ typedef struct { #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) -/*! PWMX_EN - PWM_X Output Enables - * 0b0000..PWM_X output disabled. - * 0b0001..PWM_X output enabled. - */ +/*! PWMX_EN - PWM_X Output Enables */ #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) #define PWM_OUTEN_PWMB_EN_MASK (0xF0U) #define PWM_OUTEN_PWMB_EN_SHIFT (4U) -/*! PWMB_EN - PWM_B Output Enables - * 0b0000..PWM_B output disabled. - * 0b0001..PWM_B output enabled. - */ +/*! PWMB_EN - PWM_B Output Enables */ #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) -/*! PWMA_EN - PWM_A Output Enables - * 0b0000..PWM_A output disabled. - * 0b0001..PWM_A output enabled. - */ +/*! PWMA_EN - PWM_A Output Enables */ #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) /*! @} */ @@ -67276,34 +60126,22 @@ typedef struct { #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) -/*! MASKX - PWM_X Masks - * 0b0000..PWM_X output normal. - * 0b0001..PWM_X output masked. - */ +/*! MASKX - PWM_X Masks */ #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) #define PWM_MASK_MASKB_MASK (0xF0U) #define PWM_MASK_MASKB_SHIFT (4U) -/*! MASKB - PWM_B Masks - * 0b0000..PWM_B output normal. - * 0b0001..PWM_B output masked. - */ +/*! MASKB - PWM_B Masks */ #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) #define PWM_MASK_MASKA_MASK (0xF00U) #define PWM_MASK_MASKA_SHIFT (8U) -/*! MASKA - PWM_A Masks - * 0b0000..PWM_A output normal. - * 0b0001..PWM_A output masked. - */ +/*! MASKA - PWM_A Masks */ #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) #define PWM_MASK_UPDATE_MASK_MASK (0xF000U) #define PWM_MASK_UPDATE_MASK_SHIFT (12U) -/*! UPDATE_MASK - Update Mask Bits Immediately - * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. - * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. - */ +/*! UPDATE_MASK - Update Mask Bits Immediately */ #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) /*! @} */ @@ -67384,7 +60222,7 @@ typedef struct { * 0b00..Generated SM0PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. - * 0b11..PWM0_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) @@ -67404,7 +60242,7 @@ typedef struct { * 0b00..Generated SM1PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. - * 0b11..PWM1_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) @@ -67424,7 +60262,7 @@ typedef struct { * 0b00..Generated SM2PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. - * 0b11..PWM2_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) @@ -67444,7 +60282,7 @@ typedef struct { * 0b00..Generated SM3PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. - * 0b11..PWM3_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) @@ -67495,18 +60333,6 @@ typedef struct { /*! @name MCTRL2 - Master Control 2 Register */ /*! @{ */ -#define PWM_MCTRL2_MONPLL_MASK (0x3U) -#define PWM_MCTRL2_MONPLL_SHIFT (0U) -/*! MONPLL - Monitor PLL State - * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. - * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. - * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock - * will be controlled by software. These bits are write protected until the next reset. - * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL - * encounters problems. These bits are write protected until the next reset. - */ -#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) - #define PWM_MCTRL2_WRPROT_MASK (0xCU) #define PWM_MCTRL2_WRPROT_SHIFT (2U) /*! WRPROT - Write protect @@ -67716,6 +60542,651 @@ typedef struct { */ /* end of group PWM_Peripheral_Access_Layer */ +/* ---------------------------------------------------------------------------- + -- QDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer + * @{ + */ + +/** QDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ + __IO uint16_t TST; /**< Test, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ +} QDC_Type; + +/* ---------------------------------------------------------------------------- + -- QDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Register_Masks QDC Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define QDC_CTRL_CMPIE_MASK (0x1U) +#define QDC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK) + +#define QDC_CTRL_CMPIRQ_MASK (0x2U) +#define QDC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK) + +#define QDC_CTRL_WDE_MASK (0x4U) +#define QDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK) + +#define QDC_CTRL_DIE_MASK (0x8U) +#define QDC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK) + +#define QDC_CTRL_DIRQ_MASK (0x10U) +#define QDC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK) + +#define QDC_CTRL_XNE_MASK (0x20U) +#define QDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive and Negative Edge of INDEX Pulse + * 0b0..Use positive edge + * 0b1..Use negative edge + */ +#define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK) + +#define QDC_CTRL_XIP_MASK (0x40U) +#define QDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..Does not initialize + * 0b1..Initializes + */ +#define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK) + +#define QDC_CTRL_XIE_MASK (0x80U) +#define QDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK) + +#define QDC_CTRL_XIRQ_MASK (0x100U) +#define QDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK) + +#define QDC_CTRL_PH1_MASK (0x200U) +#define QDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. + * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; + * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. + */ +#define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK) + +#define QDC_CTRL_REV_MASK (0x400U) +#define QDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Counts normally + * 0b1..Counts in the reverse direction + */ +#define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK) + +#define QDC_CTRL_SWIP_MASK (0x800U) +#define QDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK) + +#define QDC_CTRL_HNE_MASK (0x1000U) +#define QDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK) + +#define QDC_CTRL_HIP_MASK (0x2000U) +#define QDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK) + +#define QDC_CTRL_HIE_MASK (0x4000U) +#define QDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK) + +#define QDC_CTRL_HIRQ_MASK (0x8000U) +#define QDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter */ +/*! @{ */ + +#define QDC_FILT_FILT_PER_MASK (0xFFU) +#define QDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK) + +#define QDC_FILT_FILT_CNT_MASK (0x700U) +#define QDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK) + +#define QDC_FILT_FILT_PRSC_MASK (0xE000U) +#define QDC_FILT_FILT_PRSC_SHIFT (13U) +/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ +#define QDC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout */ +/*! @{ */ + +#define QDC_WTR_WDOG_MASK (0xFFFFU) +#define QDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter */ +/*! @{ */ + +#define QDC_POSD_POSD_MASK (0xFFFFU) +#define QDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold */ +/*! @{ */ + +#define QDC_POSDH_POSDH_MASK (0xFFFFU) +#define QDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter */ +/*! @{ */ + +#define QDC_REV_REV_MASK (0xFFFFU) +#define QDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold */ +/*! @{ */ + +#define QDC_REVH_REVH_MASK (0xFFFFU) +#define QDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter */ +/*! @{ */ + +#define QDC_UPOS_POS_MASK (0xFFFFU) +#define QDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter */ +/*! @{ */ + +#define QDC_LPOS_POS_MASK (0xFFFFU) +#define QDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold */ +/*! @{ */ + +#define QDC_UPOSH_POSH_MASK (0xFFFFU) +#define QDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold */ +/*! @{ */ + +#define QDC_LPOSH_POSH_MASK (0xFFFFU) +#define QDC_LPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization */ +/*! @{ */ + +#define QDC_UINIT_INIT_MASK (0xFFFFU) +#define QDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization */ +/*! @{ */ + +#define QDC_LINIT_INIT_MASK (0xFFFFU) +#define QDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor */ +/*! @{ */ + +#define QDC_IMR_HOME_MASK (0x1U) +#define QDC_IMR_HOME_SHIFT (0U) +/*! HOME - HOME */ +#define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK) + +#define QDC_IMR_INDEX_MASK (0x2U) +#define QDC_IMR_INDEX_SHIFT (1U) +/*! INDEX - INDEX */ +#define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK) + +#define QDC_IMR_PHB_MASK (0x4U) +#define QDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK) + +#define QDC_IMR_PHA_MASK (0x8U) +#define QDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK) + +#define QDC_IMR_FHOM_MASK (0x10U) +#define QDC_IMR_FHOM_SHIFT (4U) +/*! FHOM - FHOM */ +#define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK) + +#define QDC_IMR_FIND_MASK (0x20U) +#define QDC_IMR_FIND_SHIFT (5U) +/*! FIND - FIND */ +#define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK) + +#define QDC_IMR_FPHB_MASK (0x40U) +#define QDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - FPHB */ +#define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK) + +#define QDC_IMR_FPHA_MASK (0x80U) +#define QDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - FPHA */ +#define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test */ +/*! @{ */ + +#define QDC_TST_TEST_COUNT_MASK (0xFFU) +#define QDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK) + +#define QDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define QDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK) + +#define QDC_TST_QDN_MASK (0x2000U) +#define QDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Positive quadrature decoder signal + * 0b1..Negative quadrature decoder signal + */ +#define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK) + +#define QDC_TST_TCE_MASK (0x4000U) +#define QDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK) + +#define QDC_TST_TEN_MASK (0x8000U) +#define QDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define QDC_CTRL2_UPDHLD_MASK (0x1U) +#define QDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK) + +#define QDC_CTRL2_UPDPOS_MASK (0x2U) +#define QDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action + * 0b1..Clear + */ +#define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK) + +#define QDC_CTRL2_MOD_MASK (0x4U) +#define QDC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK) + +#define QDC_CTRL2_DIR_MASK (0x8U) +#define QDC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Down direction + * 0b1..Up direction + */ +#define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK) + +#define QDC_CTRL2_RUIE_MASK (0x10U) +#define QDC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK) + +#define QDC_CTRL2_RUIRQ_MASK (0x20U) +#define QDC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK) + +#define QDC_CTRL2_ROIE_MASK (0x40U) +#define QDC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK) + +#define QDC_CTRL2_ROIRQ_MASK (0x80U) +#define QDC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..Did not occur + * 0b1..Occurred + */ +#define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK) + +#define QDC_CTRL2_REVMOD_MASK (0x100U) +#define QDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse + * 0b1..Use modulus counting roll-over or roll-under + */ +#define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK) + +#define QDC_CTRL2_OUTCTL_MASK (0x200U) +#define QDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + */ +#define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK) + +#define QDC_CTRL2_SABIE_MASK (0x400U) +#define QDC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK) + +#define QDC_CTRL2_SABIRQ_MASK (0x800U) +#define QDC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change has occurred + * 0b1..A simultaneous change has occurred + */ +#define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK) + +#define QDC_CTRL2_INITPOS_MASK (0x1000U) +#define QDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initialize Position Registers + * 0b0..Don't initialize position counter + * 0b1..Initialize position counter + */ +#define QDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus */ +/*! @{ */ + +#define QDC_UMOD_MOD_MASK (0xFFFFU) +#define QDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus */ +/*! @{ */ + +#define QDC_LMOD_MOD_MASK (0xFFFFU) +#define QDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare */ +/*! @{ */ + +#define QDC_UCOMP_COMP_MASK (0xFFFFU) +#define QDC_UCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare */ +/*! @{ */ + +#define QDC_LCOMP_COMP_MASK (0xFFFFU) +#define QDC_LCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time */ +/*! @{ */ + +#define QDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define QDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define QDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold */ +/*! @{ */ + +#define QDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define QDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define QDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter */ +/*! @{ */ + +#define QDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define QDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define QDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer */ +/*! @{ */ + +#define QDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define QDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define QDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold */ +/*! @{ */ + +#define QDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define QDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define QDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 */ +/*! @{ */ + +#define QDC_CTRL3_PMEN_MASK (0x1U) +#define QDC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period Measurement Function Enable + * 0b0..Not used + * 0b1..Used + */ +#define QDC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK) + +#define QDC_CTRL3_PRSC_MASK (0xF0U) +#define QDC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler */ +#define QDC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group QDC_Register_Masks */ + + +/* QDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x500D1000u) + /** Peripheral QDC1 base address */ + #define QDC1_BASE_NS (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Peripheral QDC1 base pointer */ + #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } + +/*! + * @} + */ /* end of group QDC_Peripheral_Access_Layer */ + + /* ---------------------------------------------------------------------------- -- RTC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -68312,8 +61783,8 @@ typedef struct { #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) /*! SUB_SECOND_CNT_EN - Subsecond Counter Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) /*! @} */ @@ -68333,32 +61804,32 @@ typedef struct { #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) /*! WAKE_FLAG - Wake Timer Status Flag - * 0b0..Wake timer has not timed out. - * 0b1..Wake timer has timed out. + * 0b0..Not timed out + * 0b1..Timed out */ #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) /*! CLR_WAKE_TIMER - Clear Wake Timer - * 0b0..No effect. - * 0b1..Clears the wake timer counter and halts operation until a new count value is loaded. + * 0b0..No effect + * 0b1..Clear the wake timer counter */ #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) /*! OSC_DIV_ENA - OSC Divide Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) #define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) #define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) /*! INTR_EN - Enable Interrupt - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) /*! @} */ @@ -68428,37 +61899,37 @@ typedef struct { /** S50 - Register Layout Typedef */ typedef struct { - __I uint32_t STATUS; /**< Status Register, offset: 0x0 */ - __IO uint32_t CTRL; /**< Control Register, offset: 0x4 */ - __IO uint32_t CMDCFG0; /**< Command Configuration Register, offset: 0x8 */ - __IO uint32_t CFG; /**< Configuration Register, offset: 0xC */ - __IO uint32_t KIDX0; /**< Keystore Index 0 Register, offset: 0x10 */ - __IO uint32_t KIDX1; /**< Keystore Index 1 Register, offset: 0x14 */ - __IO uint32_t KPROPIN; /**< Key Properties Request Register, offset: 0x18 */ + __I uint32_t ELS_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t ELS_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t ELS_CMDCFG0; /**< Command Configuration, offset: 0x8 */ + __IO uint32_t ELS_CFG; /**< Configuration Register, offset: 0xC */ + __IO uint32_t ELS_KIDX0; /**< Keystore Index 0, offset: 0x10 */ + __IO uint32_t ELS_KIDX1; /**< Keystore Index 1, offset: 0x14 */ + __IO uint32_t ELS_KPROPIN; /**< Key Properties Request, offset: 0x18 */ uint8_t RESERVED_0[4]; - __IO uint32_t DMA_SRC0; /**< DMA Source 0 Register, offset: 0x20 */ - __IO uint32_t DMA_SRC0_LEN; /**< DMA Source 0 Length Register, offset: 0x24 */ - __IO uint32_t DMA_SRC1; /**< DMA Source 1 Register, offset: 0x28 */ + __IO uint32_t ELS_DMA_SRC0; /**< DMA Source 0, offset: 0x20 */ + __IO uint32_t ELS_DMA_SRC0_LEN; /**< DMA Source 0 Length, offset: 0x24 */ + __IO uint32_t ELS_DMA_SRC1; /**< DMA Source 1, offset: 0x28 */ uint8_t RESERVED_1[4]; - __IO uint32_t DMA_SRC2; /**< DMA Source 2 Register, offset: 0x30 */ - __IO uint32_t DMA_SRC2_LEN; /**< DMA Source 2 Length Register, offset: 0x34 */ - __IO uint32_t DMA_RES0; /**< DMA Result 0 Register, offset: 0x38 */ - __IO uint32_t DMA_RES0_LEN; /**< DMA Result 0 Size Register, offset: 0x3C */ - __IO uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x40 */ - __O uint32_t INT_STATUS_CLR; /**< Interrupt Status Clear Register, offset: 0x44 */ - __O uint32_t INT_STATUS_SET; /**< Interrupt Status Set Register, offset: 0x48 */ - __I uint32_t ERR_STATUS; /**< Error Status Register, offset: 0x4C */ - __O uint32_t ERR_STATUS_CLR; /**< Error Status Clear Register, offset: 0x50 */ - __I uint32_t VERSION; /**< Version Register, offset: 0x54 */ + __IO uint32_t ELS_DMA_SRC2; /**< DMA Source 2, offset: 0x30 */ + __IO uint32_t ELS_DMA_SRC2_LEN; /**< DMA Source 2 Length, offset: 0x34 */ + __IO uint32_t ELS_DMA_RES0; /**< DMA Result 0, offset: 0x38 */ + __IO uint32_t ELS_DMA_RES0_LEN; /**< DMA Result 0 Length, offset: 0x3C */ + __IO uint32_t ELS_INT_ENABLE; /**< Interrupt Enable, offset: 0x40 */ + __O uint32_t ELS_INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0x44 */ + __O uint32_t ELS_INT_STATUS_SET; /**< Interrupt Status Set, offset: 0x48 */ + __I uint32_t ELS_ERR_STATUS; /**< Error Status, offset: 0x4C */ + __O uint32_t ELS_ERR_STATUS_CLR; /**< Error Status Clear, offset: 0x50 */ + __I uint32_t ELS_VERSION; /**< Version Register, offset: 0x54 */ uint8_t RESERVED_2[4]; - __I uint32_t PRNG_DATOUT; /**< PRNG SW Read Out Register, offset: 0x5C */ - __IO uint32_t CMDCRC_CTRL; /**< CRC Configuration Register, offset: 0x60 */ - __I uint32_t CMDCRC; /**< Command CRC Value Register, offset: 0x64 */ - __IO uint32_t SESSION_ID; /**< Session ID Register, offset: 0x68 */ + __I uint32_t ELS_PRNG_DATOUT; /**< PRNG SW Read Out, offset: 0x5C */ + __IO uint32_t ELS_CMDCRC_CTRL; /**< CRC Configuration, offset: 0x60 */ + __I uint32_t ELS_CMDCRC; /**< Command CRC Value, offset: 0x64 */ + __IO uint32_t ELS_SESSION_ID; /**< Session ID, offset: 0x68 */ uint8_t RESERVED_3[4]; - __I uint32_t DMA_FIN_ADDR; /**< Final DMA Address Register, offset: 0x70 */ - __IO uint32_t MASTER_ID; /**< Master ID Register, offset: 0x74 */ - __IO uint32_t KIDX2; /**< Keystore Index 2 Register, offset: 0x78 */ + __I uint32_t ELS_DMA_FIN_ADDR; /**< Final DMA Address, offset: 0x70 */ + __IO uint32_t ELS_MASTER_ID; /**< Master ID, offset: 0x74 */ + __IO uint32_t ELS_KIDX2; /**< Keystore Index 2, offset: 0x78 */ uint8_t RESERVED_4[212]; __I uint32_t ELS_KS0; /**< Status Register, offset: 0x150 */ __I uint32_t ELS_KS1; /**< Status Register, offset: 0x154 */ @@ -68491,383 +61962,423 @@ typedef struct { * @{ */ -/*! @name STATUS - Status Register */ +/*! @name ELS_STATUS - Status Register */ /*! @{ */ -#define S50_STATUS_ELS_BUSY_MASK (0x1U) -#define S50_STATUS_ELS_BUSY_SHIFT (0U) +#define S50_ELS_STATUS_ELS_BUSY_MASK (0x1U) +#define S50_ELS_STATUS_ELS_BUSY_SHIFT (0U) /*! ELS_BUSY * 0b1..Crypto sequence executing * 0b0..Crypto sequence not executing */ -#define S50_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_BUSY_SHIFT)) & S50_STATUS_ELS_BUSY_MASK) +#define S50_ELS_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK) -#define S50_STATUS_ELS_IRQ_MASK (0x2U) -#define S50_STATUS_ELS_IRQ_SHIFT (1U) +#define S50_ELS_STATUS_ELS_IRQ_MASK (0x2U) +#define S50_ELS_STATUS_ELS_IRQ_SHIFT (1U) /*! ELS_IRQ * 0b1..Active interrupt * 0b0..No active interrupt */ -#define S50_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_IRQ_SHIFT)) & S50_STATUS_ELS_IRQ_MASK) +#define S50_ELS_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK) -#define S50_STATUS_ELS_ERR_MASK (0x4U) -#define S50_STATUS_ELS_ERR_SHIFT (2U) +#define S50_ELS_STATUS_ELS_ERR_MASK (0x4U) +#define S50_ELS_STATUS_ELS_ERR_SHIFT (2U) /*! ELS_ERR * 0b1..Internal error detected * 0b0..Internal error not detected */ -#define S50_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_ERR_SHIFT)) & S50_STATUS_ELS_ERR_MASK) +#define S50_ELS_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK) -#define S50_STATUS_PRNG_RDY_MASK (0x8U) -#define S50_STATUS_PRNG_RDY_SHIFT (3U) +#define S50_ELS_STATUS_PRNG_RDY_MASK (0x8U) +#define S50_ELS_STATUS_PRNG_RDY_SHIFT (3U) /*! PRNG_RDY * 0b0..Internal PRNG not ready * 0b1..Internal PRNG ready */ -#define S50_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_PRNG_RDY_SHIFT)) & S50_STATUS_PRNG_RDY_MASK) +#define S50_ELS_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK) -#define S50_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) -#define S50_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) /*! ECDSA_VFY_STATUS * 0b11..Invalid, Error * 0b00..No verify run * 0b01..Signature verify failed * 0b10..Signature verify passed */ -#define S50_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_STATUS_ECDSA_VFY_STATUS_MASK) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK) -#define S50_STATUS_PPROT_MASK (0xC0U) -#define S50_STATUS_PPROT_SHIFT (6U) +#define S50_ELS_STATUS_PPROT_MASK (0xC0U) +#define S50_ELS_STATUS_PPROT_SHIFT (6U) /*! PPROT * 0b10..Non-secure, non-privileged * 0b11..Non-secure, privileged * 0b00..Secure, non-privileged * 0b01..Secure, privileged */ -#define S50_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_PPROT_SHIFT)) & S50_STATUS_PPROT_MASK) +#define S50_ELS_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK) -#define S50_STATUS_DRBG_ENT_LVL_MASK (0x300U) -#define S50_STATUS_DRBG_ENT_LVL_SHIFT (8U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_MASK (0x300U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT (8U) /*! DRBG_ENT_LVL * 0b10..HIGH, DRBG generates random numbers of high quality entropy * 0b01..LOW, DRBG generates random numbers of low quality entropy * 0b00..NONE * 0b11..RFU, Reserved for Future Use */ -#define S50_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_STATUS_DRBG_ENT_LVL_MASK) +#define S50_ELS_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK) -#define S50_STATUS_DTRNG_BUSY_MASK (0x400U) -#define S50_STATUS_DTRNG_BUSY_SHIFT (10U) +#define S50_ELS_STATUS_DTRNG_BUSY_MASK (0x400U) +#define S50_ELS_STATUS_DTRNG_BUSY_SHIFT (10U) /*! DTRNG_BUSY * 0b1..Gathering entropy * 0b0..Not gathering entropy */ -#define S50_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_DTRNG_BUSY_SHIFT)) & S50_STATUS_DTRNG_BUSY_MASK) +#define S50_ELS_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK) -#define S50_STATUS_ELS_LOCKED_MASK (0x10000U) -#define S50_STATUS_ELS_LOCKED_SHIFT (16U) +#define S50_ELS_STATUS_ELS_LOCKED_MASK (0x10000U) +#define S50_ELS_STATUS_ELS_LOCKED_SHIFT (16U) /*! ELS_LOCKED * 0b1..Locked by master * 0b0..Not locked by master */ -#define S50_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_LOCKED_SHIFT)) & S50_STATUS_ELS_LOCKED_MASK) +#define S50_ELS_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK) /*! @} */ -/*! @name CTRL - Control Register */ +/*! @name ELS_CTRL - Control Register */ /*! @{ */ -#define S50_CTRL_ELS_EN_MASK (0x1U) -#define S50_CTRL_ELS_EN_SHIFT (0U) +#define S50_ELS_CTRL_ELS_EN_MASK (0x1U) +#define S50_ELS_CTRL_ELS_EN_SHIFT (0U) /*! ELS_EN * 0b0..Disabled * 0b1..Enabled */ -#define S50_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_EN_SHIFT)) & S50_CTRL_ELS_EN_MASK) +#define S50_ELS_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK) -#define S50_CTRL_ELS_START_MASK (0x2U) -#define S50_CTRL_ELS_START_SHIFT (1U) -#define S50_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_START_SHIFT)) & S50_CTRL_ELS_START_MASK) +#define S50_ELS_CTRL_ELS_START_MASK (0x2U) +#define S50_ELS_CTRL_ELS_START_SHIFT (1U) +#define S50_ELS_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK) -#define S50_CTRL_ELS_RESET_MASK (0x4U) -#define S50_CTRL_ELS_RESET_SHIFT (2U) -#define S50_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_RESET_SHIFT)) & S50_CTRL_ELS_RESET_MASK) +#define S50_ELS_CTRL_ELS_RESET_MASK (0x4U) +#define S50_ELS_CTRL_ELS_RESET_SHIFT (2U) +#define S50_ELS_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK) -#define S50_CTRL_ELS_CMD_MASK (0xF8U) -#define S50_CTRL_ELS_CMD_SHIFT (3U) +#define S50_ELS_CTRL_ELS_CMD_MASK (0xF8U) +#define S50_ELS_CTRL_ELS_CMD_SHIFT (3U) /*! ELS_CMD - ELS Command ID */ -#define S50_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_CMD_SHIFT)) & S50_CTRL_ELS_CMD_MASK) +#define S50_ELS_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK) -#define S50_CTRL_BYTE_ORDER_MASK (0x100U) -#define S50_CTRL_BYTE_ORDER_SHIFT (8U) +#define S50_ELS_CTRL_BYTE_ORDER_MASK (0x100U) +#define S50_ELS_CTRL_BYTE_ORDER_SHIFT (8U) /*! BYTE_ORDER * 0b1..Big endian * 0b0..Little endian */ -#define S50_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_BYTE_ORDER_SHIFT)) & S50_CTRL_BYTE_ORDER_MASK) +#define S50_ELS_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK) /*! @} */ -/*! @name CMDCFG0 - Command Configuration Register */ +/*! @name ELS_CMDCFG0 - Command Configuration */ /*! @{ */ -#define S50_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) -#define S50_CMDCFG0_CMDCFG0_SHIFT (0U) -#define S50_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCFG0_CMDCFG0_SHIFT)) & S50_CMDCFG0_CMDCFG0_MASK) +#define S50_ELS_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCFG0_CMDCFG0_SHIFT (0U) +#define S50_ELS_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK) /*! @} */ -/*! @name CFG - Configuration Register */ +/*! @name ELS_CFG - Configuration Register */ /*! @{ */ -#define S50_CFG_ADCTRL_MASK (0x3FF0000U) -#define S50_CFG_ADCTRL_SHIFT (16U) -#define S50_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_CFG_ADCTRL_SHIFT)) & S50_CFG_ADCTRL_MASK) +#define S50_ELS_CFG_ADCTRL_MASK (0x3FF0000U) +#define S50_ELS_CFG_ADCTRL_SHIFT (16U) +#define S50_ELS_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK) /*! @} */ -/*! @name KIDX0 - Keystore Index 0 Register */ +/*! @name ELS_KIDX0 - Keystore Index 0 */ /*! @{ */ -#define S50_KIDX0_KIDX0_MASK (0x1FU) -#define S50_KIDX0_KIDX0_SHIFT (0U) -#define S50_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_KIDX0_KIDX0_SHIFT)) & S50_KIDX0_KIDX0_MASK) +#define S50_ELS_KIDX0_KIDX0_MASK (0x1FU) +#define S50_ELS_KIDX0_KIDX0_SHIFT (0U) +#define S50_ELS_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK) /*! @} */ -/*! @name KIDX1 - Keystore Index 1 Register */ +/*! @name ELS_KIDX1 - Keystore Index 1 */ /*! @{ */ -#define S50_KIDX1_KIDX1_MASK (0x1FU) -#define S50_KIDX1_KIDX1_SHIFT (0U) -#define S50_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_KIDX1_KIDX1_SHIFT)) & S50_KIDX1_KIDX1_MASK) +#define S50_ELS_KIDX1_KIDX1_MASK (0x1FU) +#define S50_ELS_KIDX1_KIDX1_SHIFT (0U) +#define S50_ELS_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK) /*! @} */ -/*! @name KPROPIN - Key Properties Request Register */ +/*! @name ELS_KPROPIN - Key Properties Request */ /*! @{ */ -#define S50_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) -#define S50_KPROPIN_KPROPIN_SHIFT (0U) -#define S50_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_KPROPIN_KPROPIN_SHIFT)) & S50_KPROPIN_KPROPIN_MASK) +#define S50_ELS_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) +#define S50_ELS_KPROPIN_KPROPIN_SHIFT (0U) +#define S50_ELS_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK) /*! @} */ -/*! @name DMA_SRC0 - DMA Source 0 Register */ +/*! @name ELS_DMA_SRC0 - DMA Source 0 */ /*! @{ */ -#define S50_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC0_ADDR_SRC0_SHIFT (0U) -#define S50_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_DMA_SRC0_ADDR_SRC0_MASK) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT (0U) +#define S50_ELS_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK) /*! @} */ -/*! @name DMA_SRC0_LEN - DMA Source 0 Length Register */ +/*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */ /*! @{ */ -#define S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) -#define S50_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) /*! @} */ -/*! @name DMA_SRC1 - DMA Source 1 Register */ +/*! @name ELS_DMA_SRC1 - DMA Source 1 */ /*! @{ */ -#define S50_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC1_ADDR_SRC1_SHIFT (0U) -#define S50_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_DMA_SRC1_ADDR_SRC1_MASK) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT (0U) +#define S50_ELS_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK) /*! @} */ -/*! @name DMA_SRC2 - DMA Source 2 Register */ +/*! @name ELS_DMA_SRC2 - DMA Source 2 */ /*! @{ */ -#define S50_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC2_ADDR_SRC2_SHIFT (0U) -#define S50_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_DMA_SRC2_ADDR_SRC2_MASK) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT (0U) +#define S50_ELS_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK) /*! @} */ -/*! @name DMA_SRC2_LEN - DMA Source 2 Length Register */ +/*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */ /*! @{ */ -#define S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) -#define S50_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) /*! @} */ -/*! @name DMA_RES0 - DMA Result 0 Register */ +/*! @name ELS_DMA_RES0 - DMA Result 0 */ /*! @{ */ -#define S50_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) -#define S50_DMA_RES0_ADDR_RES0_SHIFT (0U) -#define S50_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_RES0_ADDR_RES0_SHIFT)) & S50_DMA_RES0_ADDR_RES0_MASK) +#define S50_ELS_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT (0U) +#define S50_ELS_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK) /*! @} */ -/*! @name DMA_RES0_LEN - DMA Result 0 Size Register */ +/*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */ /*! @{ */ -#define S50_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) -#define S50_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) -#define S50_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) /*! @} */ -/*! @name INT_ENABLE - Interrupt Enable Register */ +/*! @name ELS_INT_ENABLE - Interrupt Enable */ /*! @{ */ -#define S50_INT_ENABLE_INT_EN_MASK (0x1U) -#define S50_INT_ENABLE_INT_EN_SHIFT (0U) -#define S50_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_INT_ENABLE_INT_EN_SHIFT)) & S50_INT_ENABLE_INT_EN_MASK) +#define S50_ELS_INT_ENABLE_INT_EN_MASK (0x1U) +#define S50_ELS_INT_ENABLE_INT_EN_SHIFT (0U) +/*! INT_EN + * 0b0..Disables + * 0b1..Enables + */ +#define S50_ELS_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK) /*! @} */ -/*! @name INT_STATUS_CLR - Interrupt Status Clear Register */ +/*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */ /*! @{ */ -#define S50_INT_STATUS_CLR_INT_CLR_MASK (0x1U) -#define S50_INT_STATUS_CLR_INT_CLR_SHIFT (0U) -#define S50_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_INT_STATUS_CLR_INT_CLR_MASK) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK (0x1U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT (0U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK) /*! @} */ -/*! @name INT_STATUS_SET - Interrupt Status Set Register */ +/*! @name ELS_INT_STATUS_SET - Interrupt Status Set */ /*! @{ */ -#define S50_INT_STATUS_SET_INT_SET_MASK (0x1U) -#define S50_INT_STATUS_SET_INT_SET_SHIFT (0U) -#define S50_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_INT_STATUS_SET_INT_SET_SHIFT)) & S50_INT_STATUS_SET_INT_SET_MASK) +#define S50_ELS_INT_STATUS_SET_INT_SET_MASK (0x1U) +#define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT (0U) +#define S50_ELS_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK) /*! @} */ -/*! @name ERR_STATUS - Error Status Register */ +/*! @name ELS_ERR_STATUS - Error Status */ /*! @{ */ -#define S50_ERR_STATUS_BUS_ERR_MASK (0x1U) -#define S50_ERR_STATUS_BUS_ERR_SHIFT (0U) -#define S50_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ERR_STATUS_BUS_ERR_MASK) +#define S50_ELS_ERR_STATUS_BUS_ERR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT (0U) +/*! BUS_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK) -#define S50_ERR_STATUS_OPN_ERR_MASK (0x2U) -#define S50_ERR_STATUS_OPN_ERR_SHIFT (1U) -#define S50_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ERR_STATUS_OPN_ERR_MASK) +#define S50_ELS_ERR_STATUS_OPN_ERR_MASK (0x2U) +#define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT (1U) +/*! OPN_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK) -#define S50_ERR_STATUS_ALG_ERR_MASK (0x4U) -#define S50_ERR_STATUS_ALG_ERR_SHIFT (2U) -#define S50_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ERR_STATUS_ALG_ERR_MASK) +#define S50_ELS_ERR_STATUS_ALG_ERR_MASK (0x4U) +#define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT (2U) +/*! ALG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK) -#define S50_ERR_STATUS_ITG_ERR_MASK (0x8U) -#define S50_ERR_STATUS_ITG_ERR_SHIFT (3U) -#define S50_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ERR_STATUS_ITG_ERR_MASK) +#define S50_ELS_ERR_STATUS_ITG_ERR_MASK (0x8U) +#define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT (3U) +/*! ITG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK) -#define S50_ERR_STATUS_FLT_ERR_MASK (0x10U) -#define S50_ERR_STATUS_FLT_ERR_SHIFT (4U) -#define S50_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ERR_STATUS_FLT_ERR_MASK) +#define S50_ELS_ERR_STATUS_FLT_ERR_MASK (0x10U) +#define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT (4U) +/*! FLT_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK) -#define S50_ERR_STATUS_PRNG_ERR_MASK (0x20U) -#define S50_ERR_STATUS_PRNG_ERR_SHIFT (5U) -#define S50_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ERR_STATUS_PRNG_ERR_MASK) +#define S50_ELS_ERR_STATUS_PRNG_ERR_MASK (0x20U) +#define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT (5U) +/*! PRNG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK) -#define S50_ERR_STATUS_ERR_LVL_MASK (0xC0U) -#define S50_ERR_STATUS_ERR_LVL_SHIFT (6U) -#define S50_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ERR_STATUS_ERR_LVL_MASK) +#define S50_ELS_ERR_STATUS_ERR_LVL_MASK (0xC0U) +#define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT (6U) +#define S50_ELS_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK) -#define S50_ERR_STATUS_DTRNG_ERR_MASK (0x100U) -#define S50_ERR_STATUS_DTRNG_ERR_SHIFT (8U) -#define S50_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ERR_STATUS_DTRNG_ERR_MASK) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK (0x100U) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT (8U) +/*! DTRNG_ERR + * 0b0..No error + * 0b1..TRNG error occurred + */ +#define S50_ELS_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK) /*! @} */ -/*! @name ERR_STATUS_CLR - Error Status Clear Register */ +/*! @name ELS_ERR_STATUS_CLR - Error Status Clear */ /*! @{ */ -#define S50_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) -#define S50_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) /*! ERR_CLR - * 0b1..Clears ELS error status bits + * 0b1..Clears ELS error state * 0b0..Exits ELS error state */ -#define S50_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ERR_STATUS_CLR_ERR_CLR_MASK) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK) /*! @} */ -/*! @name VERSION - Version Register */ +/*! @name ELS_VERSION - Version Register */ /*! @{ */ -#define S50_VERSION_Z_MASK (0xFU) -#define S50_VERSION_Z_SHIFT (0U) -#define S50_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_Z_SHIFT)) & S50_VERSION_Z_MASK) +#define S50_ELS_VERSION_Z_MASK (0xFU) +#define S50_ELS_VERSION_Z_SHIFT (0U) +#define S50_ELS_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK) -#define S50_VERSION_Y2_MASK (0xF0U) -#define S50_VERSION_Y2_SHIFT (4U) -#define S50_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_Y2_SHIFT)) & S50_VERSION_Y2_MASK) +#define S50_ELS_VERSION_Y2_MASK (0xF0U) +#define S50_ELS_VERSION_Y2_SHIFT (4U) +#define S50_ELS_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK) -#define S50_VERSION_Y1_MASK (0xF00U) -#define S50_VERSION_Y1_SHIFT (8U) -#define S50_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_Y1_SHIFT)) & S50_VERSION_Y1_MASK) +#define S50_ELS_VERSION_Y1_MASK (0xF00U) +#define S50_ELS_VERSION_Y1_SHIFT (8U) +#define S50_ELS_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK) -#define S50_VERSION_X_MASK (0xF000U) -#define S50_VERSION_X_SHIFT (12U) -#define S50_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_X_SHIFT)) & S50_VERSION_X_MASK) +#define S50_ELS_VERSION_X_MASK (0xF000U) +#define S50_ELS_VERSION_X_SHIFT (12U) +#define S50_ELS_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK) -#define S50_VERSION_SW_Z_MASK (0xF0000U) -#define S50_VERSION_SW_Z_SHIFT (16U) -#define S50_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_Z_SHIFT)) & S50_VERSION_SW_Z_MASK) +#define S50_ELS_VERSION_SW_Z_MASK (0xF0000U) +#define S50_ELS_VERSION_SW_Z_SHIFT (16U) +#define S50_ELS_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK) -#define S50_VERSION_SW_Y2_MASK (0xF00000U) -#define S50_VERSION_SW_Y2_SHIFT (20U) -#define S50_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_Y2_SHIFT)) & S50_VERSION_SW_Y2_MASK) +#define S50_ELS_VERSION_SW_Y2_MASK (0xF00000U) +#define S50_ELS_VERSION_SW_Y2_SHIFT (20U) +#define S50_ELS_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK) -#define S50_VERSION_SW_Y1_MASK (0xF000000U) -#define S50_VERSION_SW_Y1_SHIFT (24U) -#define S50_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_Y1_SHIFT)) & S50_VERSION_SW_Y1_MASK) +#define S50_ELS_VERSION_SW_Y1_MASK (0xF000000U) +#define S50_ELS_VERSION_SW_Y1_SHIFT (24U) +#define S50_ELS_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK) -#define S50_VERSION_SW_X_MASK (0xF0000000U) -#define S50_VERSION_SW_X_SHIFT (28U) -#define S50_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_X_SHIFT)) & S50_VERSION_SW_X_MASK) +#define S50_ELS_VERSION_SW_X_MASK (0xF0000000U) +#define S50_ELS_VERSION_SW_X_SHIFT (28U) +#define S50_ELS_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK) /*! @} */ -/*! @name PRNG_DATOUT - PRNG SW Read Out Register */ +/*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */ /*! @{ */ -#define S50_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) -#define S50_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) -#define S50_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_PRNG_DATOUT_PRNG_DATOUT_MASK) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK) /*! @} */ -/*! @name CMDCRC_CTRL - CRC Configuration Register */ +/*! @name ELS_CMDCRC_CTRL - CRC Configuration */ /*! @{ */ -#define S50_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) -#define S50_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) -#define S50_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_CMDCRC_CTRL_CMDCRC_RST_MASK) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) +/*! CMDCRC_RST + * 0b1..Resets the CRC command to its default value + * 0b0..No effect + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK) -#define S50_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) -#define S50_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) -#define S50_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_CMDCRC_CTRL_CMDCRC_EN_MASK) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) +/*! CMDCRC_EN + * 0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command. + * 0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command. + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK) /*! @} */ -/*! @name CMDCRC - Command CRC Value Register */ +/*! @name ELS_CMDCRC - Command CRC Value */ /*! @{ */ -#define S50_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) -#define S50_CMDCRC_CMDCRC_SHIFT (0U) -#define S50_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCRC_CMDCRC_SHIFT)) & S50_CMDCRC_CMDCRC_MASK) +#define S50_ELS_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCRC_CMDCRC_SHIFT (0U) +#define S50_ELS_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK) /*! @} */ -/*! @name SESSION_ID - Session ID Register */ +/*! @name ELS_SESSION_ID - Session ID */ /*! @{ */ -#define S50_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) -#define S50_SESSION_ID_SESSION_ID_SHIFT (0U) -#define S50_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_SESSION_ID_SESSION_ID_SHIFT)) & S50_SESSION_ID_SESSION_ID_MASK) +#define S50_ELS_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) +#define S50_ELS_SESSION_ID_SESSION_ID_SHIFT (0U) +#define S50_ELS_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK) /*! @} */ -/*! @name DMA_FIN_ADDR - Final DMA Address Register */ +/*! @name ELS_DMA_FIN_ADDR - Final DMA Address */ /*! @{ */ -#define S50_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) -#define S50_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) -#define S50_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) /*! @} */ -/*! @name MASTER_ID - Master ID Register */ +/*! @name ELS_MASTER_ID - Master ID */ /*! @{ */ -#define S50_MASTER_ID_MASTER_ID_MASK (0x1FU) -#define S50_MASTER_ID_MASTER_ID_SHIFT (0U) -#define S50_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_MASTER_ID_MASTER_ID_SHIFT)) & S50_MASTER_ID_MASTER_ID_MASK) +#define S50_ELS_MASTER_ID_MASTER_ID_MASK (0x1FU) +#define S50_ELS_MASTER_ID_MASTER_ID_SHIFT (0U) +#define S50_ELS_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK) /*! @} */ -/*! @name KIDX2 - Keystore Index 2 Register */ +/*! @name ELS_KIDX2 - Keystore Index 2 */ /*! @{ */ -#define S50_KIDX2_KIDX2_MASK (0x1FU) -#define S50_KIDX2_KIDX2_SHIFT (0U) -#define S50_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_KIDX2_KIDX2_SHIFT)) & S50_KIDX2_KIDX2_MASK) +#define S50_ELS_KIDX2_KIDX2_MASK (0x1FU) +#define S50_ELS_KIDX2_KIDX2_SHIFT (0U) +#define S50_ELS_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK) /*! @} */ /*! @name ELS_KS0 - Status Register */ @@ -71211,7 +64722,8 @@ typedef struct { __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ uint8_t RESERVED_4[8]; __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ - uint8_t RESERVED_5[8]; + __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ + uint8_t RESERVED_5[4]; __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ uint8_t RESERVED_6[228]; __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ @@ -71255,8 +64767,6 @@ typedef struct { __IO uint32_t UPLLCSR; /**< UPLL Control Status Register, offset: 0x700 */ uint8_t RESERVED_17[252]; __IO uint32_t LDOCSR; /**< LDO Control and Status Register, offset: 0x800 */ - uint8_t RESERVED_18[252]; - __IO uint32_t TROCSR; /**< TRO Control Status Register, offset: 0x900 */ } SCG_Type; /* ---------------------------------------------------------------------------- @@ -71335,14 +64845,6 @@ typedef struct { * 0b0..UPLL clock source is not present */ #define SCG_PARAM_UPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK) - -#define SCG_PARAM_TROCLKPRES_MASK (0x100U) -#define SCG_PARAM_TROCLKPRES_SHIFT (8U) -/*! TROCLKPRES - TRO Clock Present - * 0b1..TRO clock source is present - * 0b0..TRO clock source is not present - */ -#define SCG_PARAM_TROCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_TROCLKPRES_SHIFT)) & SCG_PARAM_TROCLKPRES_MASK) /*! @} */ /*! @name TRIM_LOCK - Trim Lock register */ @@ -71384,8 +64886,7 @@ typedef struct { * 0b0101..APLL * 0b0110..SPLL * 0b0111..UPLL - * 0b1000..TRO - * 0b1001-0b1111..Reserved + * 0b1000-0b1111..Reserved */ #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) /*! @} */ @@ -71404,8 +64905,7 @@ typedef struct { * 0b0101..APLL * 0b0110..SPLL * 0b0111..UPLL - * 0b1000..TRO - * 0b1001-0b1111..Reserved + * 0b1000-0b1111..Reserved */ #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) /*! @} */ @@ -71619,6 +65119,29 @@ typedef struct { #define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) /*! @} */ +/*! @name SIRCTRIM - SIRC Trim Register */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + /*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ /*! @{ */ @@ -71906,14 +65429,6 @@ typedef struct { */ #define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) -#define SCG_APLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) -#define SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) -/*! FRM_CLOCKSTABLE - Free running mode clock stable - * 0b0..Free running mode clockstable is disabled - * 0b1..Free running mode clockstable is enabled - */ -#define SCG_APLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_APLLCSR_FRM_CLOCKSTABLE_MASK) - #define SCG_APLLCSR_APLLCM_MASK (0x10000U) #define SCG_APLLCSR_APLLCM_SHIFT (16U) /*! APLLCM - APLL Clock Monitor @@ -72029,20 +65544,12 @@ typedef struct { */ #define SCG_APLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) -#define SCG_APLLCTRL_FRM_MASK (0x400000U) -#define SCG_APLLCTRL_FRM_SHIFT (22U) -/*! FRM - Free Running Mode Enable - * 0b0..Free running mode disabled - * 0b1..Free running mode enabled - */ -#define SCG_APLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_FRM_SHIFT)) & SCG_APLLCTRL_FRM_MASK) - #define SCG_APLLCTRL_SOURCE_MASK (0x6000000U) #define SCG_APLLCTRL_SOURCE_SHIFT (25U) /*! SOURCE - Clock Source * 0b00..SOSC * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. - * 0b10..ROSC + * 0b10..Reserved * 0b11..No clock */ #define SCG_APLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK) @@ -72074,14 +65581,6 @@ typedef struct { * 0b1..The postdivider (P) ratio change is accepted by the analog PLL */ #define SCG_APLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK) - -#define SCG_APLLSTAT_FRMDET_MASK (0x10U) -#define SCG_APLLSTAT_FRMDET_SHIFT (4U) -/*! FRMDET - Free running detector (active high) - * 0b0..Free running is not detected - * 0b1..Free running is detected - */ -#define SCG_APLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_FRMDET_SHIFT)) & SCG_APLLSTAT_FRMDET_MASK) /*! @} */ /*! @name APLLNDIV - APLL N Divider Register */ @@ -72279,14 +65778,6 @@ typedef struct { */ #define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) -#define SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) -#define SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) -/*! FRM_CLOCKSTABLE - Free running mode clock stable - * 0b0..Free running mode clockstable is disabled - * 0b1..Free running mode clockstable is enabled - */ -#define SCG_SPLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK) - #define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) #define SCG_SPLLCSR_SPLLCM_SHIFT (16U) /*! SPLLCM - SPLL Clock Monitor @@ -72402,20 +65893,12 @@ typedef struct { */ #define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) -#define SCG_SPLLCTRL_FRM_MASK (0x400000U) -#define SCG_SPLLCTRL_FRM_SHIFT (22U) -/*! FRM - Free Running Mode Enable - * 0b0..Free running mode disabled - * 0b1..Free running mode enabled - */ -#define SCG_SPLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_FRM_SHIFT)) & SCG_SPLLCTRL_FRM_MASK) - #define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) #define SCG_SPLLCTRL_SOURCE_SHIFT (25U) /*! SOURCE - Clock Source * 0b00..SOSC * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. - * 0b10..ROSC + * 0b10..Reserved * 0b11..No clock */ #define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) @@ -72447,14 +65930,6 @@ typedef struct { * 0b1..The postdivider (P) ratio change is accepted by the analog PLL */ #define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) - -#define SCG_SPLLSTAT_FRMDET_MASK (0x10U) -#define SCG_SPLLSTAT_FRMDET_SHIFT (4U) -/*! FRMDET - Free running detector (active high) - * 0b0..Free running is not detected - * 0b1..Free running is detected - */ -#define SCG_SPLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_FRMDET_SHIFT)) & SCG_SPLLSTAT_FRMDET_MASK) /*! @} */ /*! @name SPLLNDIV - SPLL N Divider Register */ @@ -72719,68 +66194,6 @@ typedef struct { #define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) /*! @} */ -/*! @name TROCSR - TRO Control Status Register */ -/*! @{ */ - -#define SCG_TROCSR_TROCM_MASK (0x10000U) -#define SCG_TROCSR_TROCM_SHIFT (16U) -/*! TROCM - TRO Clock Monitor - * 0b0..TRO Clock Monitor is disabled - * 0b1..TRO Clock Monitor is enabled - */ -#define SCG_TROCSR_TROCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCM_SHIFT)) & SCG_TROCSR_TROCM_MASK) - -#define SCG_TROCSR_TROCMRE_MASK (0x20000U) -#define SCG_TROCSR_TROCMRE_SHIFT (17U) -/*! TROCMRE - TRO Clock Monitor Reset Enable - * 0b0..Clock monitor generates an interrupt when an error is detected - * 0b1..Clock monitor generates a reset when an error is detected - */ -#define SCG_TROCSR_TROCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCMRE_SHIFT)) & SCG_TROCSR_TROCMRE_MASK) - -#define SCG_TROCSR_TRO_REFCLK_SEL_MASK (0xC0000U) -#define SCG_TROCSR_TRO_REFCLK_SEL_SHIFT (18U) -/*! TRO_REFCLK_SEL - TRO reference clock selection - * 0b00..SOSC - * 0b01..SIRC - * 0b10..FIRC (144 MHz or 48 MHz, based on RANGE selection) - * 0b11..Reserved - */ -#define SCG_TROCSR_TRO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TRO_REFCLK_SEL_SHIFT)) & SCG_TROCSR_TRO_REFCLK_SEL_MASK) - -#define SCG_TROCSR_LK_MASK (0x800000U) -#define SCG_TROCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written - * 0b1..Control Status Register cannot be written - */ -#define SCG_TROCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_LK_SHIFT)) & SCG_TROCSR_LK_MASK) - -#define SCG_TROCSR_TROVLD_MASK (0x1000000U) -#define SCG_TROCSR_TROVLD_SHIFT (24U) -/*! TROVLD - TRO Valid - * 0b0..TRO is not enabled or clock is not valid - * 0b1..TRO is enabled and output clock is valid - */ -#define SCG_TROCSR_TROVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROVLD_SHIFT)) & SCG_TROCSR_TROVLD_MASK) - -#define SCG_TROCSR_TROSEL_MASK (0x2000000U) -#define SCG_TROCSR_TROSEL_SHIFT (25U) -/*! TROSEL - TRO Selected - * 0b0..TRO is not the system clock source - * 0b1..TRO is the system clock source - */ -#define SCG_TROCSR_TROSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROSEL_SHIFT)) & SCG_TROCSR_TROSEL_MASK) - -#define SCG_TROCSR_TROERR_MASK (0x4000000U) -#define SCG_TROCSR_TROERR_SHIFT (26U) -/*! TROERR - TRO Clock Error - * 0b0..TRO clock monitor is disabled or has not detected an error - * 0b1..TRO clock monitor is enabled and detected an error - */ -#define SCG_TROCSR_TROERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROERR_SHIFT)) & SCG_TROCSR_TROERR_MASK) -/*! @} */ - /*! * @} @@ -74983,10 +68396,10 @@ typedef struct { /*! @name FRACMATREL - Fractional Match Reload */ /*! @{ */ -#define SCT_FRACMATREL_FRACMAT_L_MASK (0xFU) -#define SCT_FRACMATREL_FRACMAT_L_SHIFT (0U) -/*! FRACMAT_L - Reload Fractional Match Low */ -#define SCT_FRACMATREL_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_FRACMAT_L_SHIFT)) & SCT_FRACMATREL_FRACMAT_L_MASK) +#define SCT_FRACMATREL_RELFRAC_L_MASK (0xFU) +#define SCT_FRACMATREL_RELFRAC_L_SHIFT (0U) +/*! RELFRAC_L - Reload Fractional Match Low */ +#define SCT_FRACMATREL_RELFRAC_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_L_SHIFT)) & SCT_FRACMATREL_RELFRAC_L_MASK) #define SCT_FRACMATREL_RELFRAC_H_MASK (0xF0000U) #define SCT_FRACMATREL_RELFRAC_H_SHIFT (16U) @@ -75185,8 +68598,8 @@ typedef struct { __IO uint8_t GATE12; /**< Gate, offset: 0xF */ uint8_t RESERVED_0[50]; union { /* offset: 0x42 */ - __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ - __O uint16_t W; /**< Reset Gate Write, offset: 0x42 */ + __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ + __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ }; } SEMA42_Type; @@ -75615,21 +69028,21 @@ typedef struct { #define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) /*! @} */ -/*! @name R - Reset Gate Read */ +/*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ -#define SEMA42_R_RSTGTN_MASK (0xFFU) -#define SEMA42_R_RSTGTN_SHIFT (0U) +#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ -#define SEMA42_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_R_RSTGTN_SHIFT)) & SEMA42_R_RSTGTN_MASK) +#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) -#define SEMA42_R_RSTGMS_MASK (0xF00U) -#define SEMA42_R_RSTGMS_SHIFT (8U) +#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) +#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) /*! RSTGMS - Reset Gate Domain */ -#define SEMA42_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_R_RSTGMS_SHIFT)) & SEMA42_R_RSTGMS_MASK) +#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) -#define SEMA42_R_RSTGSM_MASK (0x3000U) -#define SEMA42_R_RSTGSM_SHIFT (12U) +#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) +#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) /*! RSTGSM - Reset Gate Finite State Machine * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write @@ -75637,21 +69050,21 @@ typedef struct { * this machine returns to the idle (waiting for first data pattern write) state. * 0b11..This state encoding is never used and therefore reserved. */ -#define SEMA42_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_R_RSTGSM_SHIFT)) & SEMA42_R_RSTGSM_MASK) +#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) /*! @} */ -/*! @name W - Reset Gate Write */ +/*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ -#define SEMA42_W_RSTGTN_MASK (0xFFU) -#define SEMA42_W_RSTGTN_SHIFT (0U) +#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ -#define SEMA42_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_W_RSTGTN_SHIFT)) & SEMA42_W_RSTGTN_MASK) +#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) -#define SEMA42_W_RSTGDP_MASK (0xFF00U) -#define SEMA42_W_RSTGDP_SHIFT (8U) +#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) +#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) /*! RSTGDP - Reset Gate Data Pattern */ -#define SEMA42_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_W_RSTGDP_SHIFT)) & SEMA42_W_RSTGDP_MASK) +#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) /*! @} */ @@ -77062,75 +70475,75 @@ typedef struct { #define SINC_SR_MCLKRDY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY2_SHIFT)) & SINC_SR_MCLKRDY2_MASK) /*! @} */ -/*! @name CHANNEL_CCR - Channel 0 Control..Channel 4 Control */ +/*! @name CCR - Channel 0 Control..Channel 4 Control */ /*! @{ */ -#define SINC_CHANNEL_CCR_CHEN_MASK (0x1U) -#define SINC_CHANNEL_CCR_CHEN_SHIFT (0U) +#define SINC_CCR_CHEN_MASK (0x1U) +#define SINC_CCR_CHEN_SHIFT (0U) /*! CHEN - Channel Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_CHEN_SHIFT)) & SINC_CHANNEL_CCR_CHEN_MASK) +#define SINC_CCR_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CHEN_SHIFT)) & SINC_CCR_CHEN_MASK) -#define SINC_CHANNEL_CCR_PFEN_MASK (0x2U) -#define SINC_CHANNEL_CCR_PFEN_SHIFT (1U) +#define SINC_CCR_PFEN_MASK (0x2U) +#define SINC_CCR_PFEN_SHIFT (1U) /*! PFEN - PF Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_PFEN_SHIFT)) & SINC_CHANNEL_CCR_PFEN_MASK) +#define SINC_CCR_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_PFEN_SHIFT)) & SINC_CCR_PFEN_MASK) -#define SINC_CHANNEL_CCR_DMAEN_MASK (0x8U) -#define SINC_CHANNEL_CCR_DMAEN_SHIFT (3U) +#define SINC_CCR_DMAEN_MASK (0x8U) +#define SINC_CCR_DMAEN_SHIFT (3U) /*! DMAEN - DMA Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_DMAEN_SHIFT)) & SINC_CHANNEL_CCR_DMAEN_MASK) +#define SINC_CCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DMAEN_SHIFT)) & SINC_CCR_DMAEN_MASK) -#define SINC_CHANNEL_CCR_SCDEN_MASK (0x100U) -#define SINC_CHANNEL_CCR_SCDEN_SHIFT (8U) +#define SINC_CCR_SCDEN_MASK (0x100U) +#define SINC_CCR_SCDEN_SHIFT (8U) /*! SCDEN - Short Circuit Detect Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_SCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_SCDEN_SHIFT)) & SINC_CHANNEL_CCR_SCDEN_MASK) +#define SINC_CCR_SCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_SCDEN_SHIFT)) & SINC_CCR_SCDEN_MASK) -#define SINC_CHANNEL_CCR_CADEN_MASK (0x200U) -#define SINC_CHANNEL_CCR_CADEN_SHIFT (9U) +#define SINC_CCR_CADEN_MASK (0x200U) +#define SINC_CCR_CADEN_SHIFT (9U) /*! CADEN - Clock Absence Detect Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_CADEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_CADEN_SHIFT)) & SINC_CHANNEL_CCR_CADEN_MASK) +#define SINC_CCR_CADEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK) -#define SINC_CHANNEL_CCR_ZCDEN_MASK (0x1000U) -#define SINC_CHANNEL_CCR_ZCDEN_SHIFT (12U) +#define SINC_CCR_ZCDEN_MASK (0x1000U) +#define SINC_CCR_ZCDEN_SHIFT (12U) /*! ZCDEN - Zero Cross Detect Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_ZCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_ZCDEN_SHIFT)) & SINC_CHANNEL_CCR_ZCDEN_MASK) +#define SINC_CCR_ZCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_ZCDEN_SHIFT)) & SINC_CCR_ZCDEN_MASK) -#define SINC_CHANNEL_CCR_LMTEN_MASK (0x2000U) -#define SINC_CHANNEL_CCR_LMTEN_SHIFT (13U) +#define SINC_CCR_LMTEN_MASK (0x2000U) +#define SINC_CCR_LMTEN_SHIFT (13U) /*! LMTEN - Limit Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_LMTEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_LMTEN_SHIFT)) & SINC_CHANNEL_CCR_LMTEN_MASK) +#define SINC_CCR_LMTEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_LMTEN_SHIFT)) & SINC_CCR_LMTEN_MASK) -#define SINC_CHANNEL_CCR_FIFOEN_MASK (0x4000U) -#define SINC_CHANNEL_CCR_FIFOEN_SHIFT (14U) +#define SINC_CCR_FIFOEN_MASK (0x4000U) +#define SINC_CCR_FIFOEN_SHIFT (14U) /*! FIFOEN - FIFO Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_FIFOEN_SHIFT)) & SINC_CHANNEL_CCR_FIFOEN_MASK) +#define SINC_CCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_FIFOEN_SHIFT)) & SINC_CCR_FIFOEN_MASK) -#define SINC_CHANNEL_CCR_DBGSEL_MASK (0xF00000U) -#define SINC_CHANNEL_CCR_DBGSEL_SHIFT (20U) +#define SINC_CCR_DBGSEL_MASK (0xF00000U) +#define SINC_CCR_DBGSEL_SHIFT (20U) /*! DBGSEL - Debug Output Selection * 0b0000..Final data from the PF (24 bits) * 0b0001..Offset data (24 bits) @@ -77144,77 +70557,77 @@ typedef struct { * 0b1010..Status of the parallel or serial data converter * *.. */ -#define SINC_CHANNEL_CCR_DBGSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_DBGSEL_SHIFT)) & SINC_CHANNEL_CCR_DBGSEL_MASK) +#define SINC_CCR_DBGSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DBGSEL_SHIFT)) & SINC_CCR_DBGSEL_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CCR */ -#define SINC_CHANNEL_CCR_COUNT (5U) +/* The count of SINC_CCR */ +#define SINC_CCR_COUNT (5U) -/*! @name CHANNEL_CDR - Channel 0 Data Rate..Channel 4 Data Rate */ +/*! @name CDR - Channel 0 Data Rate..Channel 4 Data Rate */ /*! @{ */ -#define SINC_CHANNEL_CDR_PFOSR_MASK (0x7FFU) -#define SINC_CHANNEL_CDR_PFOSR_SHIFT (0U) +#define SINC_CDR_PFOSR_MASK (0x7FFU) +#define SINC_CDR_PFOSR_SHIFT (0U) /*! PFOSR - PF OSR */ -#define SINC_CHANNEL_CDR_PFOSR(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDR_PFOSR_SHIFT)) & SINC_CHANNEL_CDR_PFOSR_MASK) +#define SINC_CDR_PFOSR(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFOSR_SHIFT)) & SINC_CDR_PFOSR_MASK) -#define SINC_CHANNEL_CDR_PFORD_MASK (0x1800U) -#define SINC_CHANNEL_CDR_PFORD_SHIFT (11U) +#define SINC_CDR_PFORD_MASK (0x1800U) +#define SINC_CDR_PFORD_SHIFT (11U) /*! PFORD - PF Order * 0b00..FastSinc * 0b01..First order * 0b10..Second order * 0b11..Third order */ -#define SINC_CHANNEL_CDR_PFORD(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDR_PFORD_SHIFT)) & SINC_CHANNEL_CDR_PFORD_MASK) +#define SINC_CDR_PFORD(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFORD_SHIFT)) & SINC_CDR_PFORD_MASK) -#define SINC_CHANNEL_CDR_PFCM_MASK (0xC000U) -#define SINC_CHANNEL_CDR_PFCM_SHIFT (14U) +#define SINC_CDR_PFCM_MASK (0xC000U) +#define SINC_CDR_PFCM_SHIFT (14U) /*! PFCM - PF Conversion Mode * 0b00..Single * 0b01..Continuous * 0b10..Always * 0b11..Fixed number */ -#define SINC_CHANNEL_CDR_PFCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDR_PFCM_SHIFT)) & SINC_CHANNEL_CDR_PFCM_MASK) +#define SINC_CDR_PFCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFCM_SHIFT)) & SINC_CDR_PFCM_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CDR */ -#define SINC_CHANNEL_CDR_COUNT (5U) +/* The count of SINC_CDR */ +#define SINC_CDR_COUNT (5U) -/*! @name CHANNEL_CCFR - Channel 0 Configuration..Channel 4 Configuration */ +/*! @name CCFR - Channel 0 Configuration..Channel 4 Configuration */ /*! @{ */ -#define SINC_CHANNEL_CCFR_PFSFT_MASK (0x1FU) -#define SINC_CHANNEL_CCFR_PFSFT_SHIFT (0U) +#define SINC_CCFR_PFSFT_MASK (0x1FU) +#define SINC_CCFR_PFSFT_SHIFT (0U) /*! PFSFT - PF Shift */ -#define SINC_CHANNEL_CCFR_PFSFT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_PFSFT_SHIFT)) & SINC_CHANNEL_CCFR_PFSFT_MASK) +#define SINC_CCFR_PFSFT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_PFSFT_SHIFT)) & SINC_CCFR_PFSFT_MASK) -#define SINC_CHANNEL_CCFR_RDFMT_MASK (0x40U) -#define SINC_CHANNEL_CCFR_RDFMT_SHIFT (6U) +#define SINC_CCFR_RDFMT_MASK (0x40U) +#define SINC_CCFR_RDFMT_SHIFT (6U) /*! RDFMT - Result Data Format * 0b0..Left justified, signed * 0b1..Left justified, unsigned */ -#define SINC_CHANNEL_CCFR_RDFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_RDFMT_SHIFT)) & SINC_CHANNEL_CCFR_RDFMT_MASK) +#define SINC_CCFR_RDFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_RDFMT_SHIFT)) & SINC_CCFR_RDFMT_MASK) -#define SINC_CHANNEL_CCFR_FIFOWMK_MASK (0x1C00U) -#define SINC_CHANNEL_CCFR_FIFOWMK_SHIFT (10U) +#define SINC_CCFR_FIFOWMK_MASK (0x1C00U) +#define SINC_CCFR_FIFOWMK_SHIFT (10U) /*! FIFOWMK - FIFO Watermark */ -#define SINC_CHANNEL_CCFR_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_FIFOWMK_SHIFT)) & SINC_CHANNEL_CCFR_FIFOWMK_MASK) +#define SINC_CCFR_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_FIFOWMK_SHIFT)) & SINC_CCFR_FIFOWMK_MASK) -#define SINC_CHANNEL_CCFR_IBFMT_MASK (0x30000U) -#define SINC_CHANNEL_CCFR_IBFMT_SHIFT (16U) +#define SINC_CCFR_IBFMT_MASK (0x30000U) +#define SINC_CCFR_IBFMT_SHIFT (16U) /*! IBFMT - Input Bit Format * 0b00..External bitstream from the MBIT[n] signal * 0b01..External Manchester code; ICESEL selects the rise or fall decoder * 0b10..Internal 16-bit parallel data from MPDATA * 0b11..Internal 32-bit serial data from MPDATA */ -#define SINC_CHANNEL_CCFR_IBFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_IBFMT_SHIFT)) & SINC_CHANNEL_CCFR_IBFMT_MASK) +#define SINC_CCFR_IBFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBFMT_SHIFT)) & SINC_CCFR_IBFMT_MASK) -#define SINC_CHANNEL_CCFR_ICSEL_MASK (0x1C0000U) -#define SINC_CHANNEL_CCFR_ICSEL_SHIFT (18U) +#define SINC_CCFR_ICSEL_MASK (0x1C0000U) +#define SINC_CCFR_ICSEL_SHIFT (18U) /*! ICSEL - Input Clock Select * 0b000..MCLK_OUT0 with internal routeback * 0b001..MCLK_OUT1 with internal routeback @@ -77223,10 +70636,10 @@ typedef struct { * 0b111..Grouped clock shared with an adjacent channel; the adjacent channel's ICSEL field determines the input clock * *.. */ -#define SINC_CHANNEL_CCFR_ICSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ICSEL_SHIFT)) & SINC_CHANNEL_CCFR_ICSEL_MASK) +#define SINC_CCFR_ICSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICSEL_SHIFT)) & SINC_CCFR_ICSEL_MASK) -#define SINC_CHANNEL_CCFR_ICESEL_MASK (0xE00000U) -#define SINC_CHANNEL_CCFR_ICESEL_SHIFT (21U) +#define SINC_CCFR_ICESEL_MASK (0xE00000U) +#define SINC_CCFR_ICESEL_SHIFT (21U) /*! ICESEL - Input Clock Edge Select * 0b001..Positive edge * 0b010..Negative edge @@ -77237,206 +70650,206 @@ typedef struct { * 0b111..Every other even negative edge * *.. */ -#define SINC_CHANNEL_CCFR_ICESEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ICESEL_SHIFT)) & SINC_CHANNEL_CCFR_ICESEL_MASK) +#define SINC_CCFR_ICESEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICESEL_SHIFT)) & SINC_CCFR_ICESEL_MASK) -#define SINC_CHANNEL_CCFR_ITSEL_MASK (0x3000000U) -#define SINC_CHANNEL_CCFR_ITSEL_SHIFT (24U) +#define SINC_CCFR_ITSEL_MASK (0x3000000U) +#define SINC_CCFR_ITSEL_SHIFT (24U) /*! ITSEL - Input Trigger Select * 0b00..Software * 0b01..Hardware trigger dedicated to the channel * 0b11..Grouped trigger shared with an adjacent channel; the adjacent channel's ITSEL field determines the trigger * *.. */ -#define SINC_CHANNEL_CCFR_ITSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ITSEL_SHIFT)) & SINC_CHANNEL_CCFR_ITSEL_MASK) +#define SINC_CCFR_ITSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITSEL_SHIFT)) & SINC_CCFR_ITSEL_MASK) -#define SINC_CHANNEL_CCFR_IBSEL_MASK (0xC000000U) -#define SINC_CHANNEL_CCFR_IBSEL_SHIFT (26U) +#define SINC_CCFR_IBSEL_MASK (0xC000000U) +#define SINC_CCFR_IBSEL_SHIFT (26U) /*! IBSEL - Input Bit Select * 0b00..External bitstream from the MBIT[n] signal * 0b01..Alternate internal bitstream from the INP[n] signal * 0b11..Grouped bitstream shared with an adjacent channel; the adjacent channel's IBSEL field determines the input * *.. */ -#define SINC_CHANNEL_CCFR_IBSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_IBSEL_SHIFT)) & SINC_CHANNEL_CCFR_IBSEL_MASK) +#define SINC_CCFR_IBSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBSEL_SHIFT)) & SINC_CCFR_IBSEL_MASK) -#define SINC_CHANNEL_CCFR_ITLVL_MASK (0x10000000U) -#define SINC_CHANNEL_CCFR_ITLVL_SHIFT (28U) +#define SINC_CCFR_ITLVL_MASK (0x10000000U) +#define SINC_CCFR_ITLVL_SHIFT (28U) /*! ITLVL - Input Trigger Level Type * 0b0..Edge * 0b1..Level */ -#define SINC_CHANNEL_CCFR_ITLVL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ITLVL_SHIFT)) & SINC_CHANNEL_CCFR_ITLVL_MASK) +#define SINC_CCFR_ITLVL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITLVL_SHIFT)) & SINC_CCFR_ITLVL_MASK) -#define SINC_CHANNEL_CCFR_ZCOP_MASK (0xC0000000U) -#define SINC_CHANNEL_CCFR_ZCOP_SHIFT (30U) +#define SINC_CCFR_ZCOP_MASK (0xC0000000U) +#define SINC_CCFR_ZCOP_SHIFT (30U) /*! ZCOP - Zero Cross Option * 0b00..Both rise and fall * 0b10..Rise * 0b01..Fall * *.. */ -#define SINC_CHANNEL_CCFR_ZCOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ZCOP_SHIFT)) & SINC_CHANNEL_CCFR_ZCOP_MASK) +#define SINC_CCFR_ZCOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ZCOP_SHIFT)) & SINC_CCFR_ZCOP_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CCFR */ -#define SINC_CHANNEL_CCFR_COUNT (5U) +/* The count of SINC_CCFR */ +#define SINC_CCFR_COUNT (5U) -/*! @name CHANNEL_CPROT - Channel 0 Protection..Channel 4 Protection */ +/*! @name CPROT - Channel 0 Protection..Channel 4 Protection */ /*! @{ */ -#define SINC_CHANNEL_CPROT_SCDLMT_MASK (0xFFU) -#define SINC_CHANNEL_CPROT_SCDLMT_SHIFT (0U) +#define SINC_CPROT_SCDLMT_MASK (0xFFU) +#define SINC_CPROT_SCDLMT_SHIFT (0U) /*! SCDLMT - SCD Limit Threshold * 0b00000000-0b00000001..Disables SCD * *..Threshold value */ -#define SINC_CHANNEL_CPROT_SCDLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDLMT_SHIFT)) & SINC_CHANNEL_CPROT_SCDLMT_MASK) +#define SINC_CPROT_SCDLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDLMT_SHIFT)) & SINC_CPROT_SCDLMT_MASK) -#define SINC_CHANNEL_CPROT_SCDCM_MASK (0x800U) -#define SINC_CHANNEL_CPROT_SCDCM_SHIFT (11U) +#define SINC_CPROT_SCDCM_MASK (0x800U) +#define SINC_CPROT_SCDCM_SHIFT (11U) /*! SCDCM - SCD Conversion Mode * 0b0..Constantly when CnCR[CHEN] = MCR[MEN] = 1 * 0b1..Only when the PF is performing a conversion */ -#define SINC_CHANNEL_CPROT_SCDCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDCM_SHIFT)) & SINC_CHANNEL_CPROT_SCDCM_MASK) +#define SINC_CPROT_SCDCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDCM_SHIFT)) & SINC_CPROT_SCDCM_MASK) -#define SINC_CHANNEL_CPROT_SCDOP_MASK (0x3000U) -#define SINC_CHANNEL_CPROT_SCDOP_SHIFT (12U) +#define SINC_CPROT_SCDOP_MASK (0x3000U) +#define SINC_CPROT_SCDOP_SHIFT (12U) /*! SCDOP - SCD Option * 0b00..Both 0 and 1 * 0b01..Only 1 * 0b10..Only 0 * 0b11.. */ -#define SINC_CHANNEL_CPROT_SCDOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDOP_SHIFT)) & SINC_CHANNEL_CPROT_SCDOP_MASK) +#define SINC_CPROT_SCDOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDOP_SHIFT)) & SINC_CPROT_SCDOP_MASK) -#define SINC_CHANNEL_CPROT_LMTOP_MASK (0xC000U) -#define SINC_CHANNEL_CPROT_LMTOP_SHIFT (14U) +#define SINC_CPROT_LMTOP_MASK (0xC000U) +#define SINC_CPROT_LMTOP_SHIFT (14U) /*! LMTOP - Limit Detection Option * 0b00..Both high and low limits * 0b01..High limit * 0b10..Low limit * 0b11..Windowed value */ -#define SINC_CHANNEL_CPROT_LMTOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_LMTOP_SHIFT)) & SINC_CHANNEL_CPROT_LMTOP_MASK) +#define SINC_CPROT_LMTOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LMTOP_SHIFT)) & SINC_CPROT_LMTOP_MASK) -#define SINC_CHANNEL_CPROT_CADLMT_MASK (0xF0000U) -#define SINC_CHANNEL_CPROT_CADLMT_SHIFT (16U) +#define SINC_CPROT_CADLMT_MASK (0xF0000U) +#define SINC_CPROT_CADLMT_SHIFT (16U) /*! CADLMT - CAD Limit Threshold * 0b0000..Disables CAD * *..Threshold value */ -#define SINC_CHANNEL_CPROT_CADLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_CADLMT_SHIFT)) & SINC_CHANNEL_CPROT_CADLMT_MASK) +#define SINC_CPROT_CADLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADLMT_SHIFT)) & SINC_CPROT_CADLMT_MASK) -#define SINC_CHANNEL_CPROT_CADBK_MASK (0x4000000U) -#define SINC_CHANNEL_CPROT_CADBK_SHIFT (26U) +#define SINC_CPROT_CADBK_MASK (0x4000000U) +#define SINC_CPROT_CADBK_SHIFT (26U) /*! CADBK - CAD Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_CADBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_CADBK_SHIFT)) & SINC_CHANNEL_CPROT_CADBK_MASK) +#define SINC_CPROT_CADBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADBK_SHIFT)) & SINC_CPROT_CADBK_MASK) -#define SINC_CHANNEL_CPROT_SCDBK_MASK (0x8000000U) -#define SINC_CHANNEL_CPROT_SCDBK_SHIFT (27U) +#define SINC_CPROT_SCDBK_MASK (0x8000000U) +#define SINC_CPROT_SCDBK_SHIFT (27U) /*! SCDBK - SCD Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_SCDBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDBK_SHIFT)) & SINC_CHANNEL_CPROT_SCDBK_MASK) +#define SINC_CPROT_SCDBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDBK_SHIFT)) & SINC_CPROT_SCDBK_MASK) -#define SINC_CHANNEL_CPROT_LLMTBK_MASK (0x20000000U) -#define SINC_CHANNEL_CPROT_LLMTBK_SHIFT (29U) +#define SINC_CPROT_LLMTBK_MASK (0x20000000U) +#define SINC_CPROT_LLMTBK_SHIFT (29U) /*! LLMTBK - Low Limit Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_LLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_LLMTBK_SHIFT)) & SINC_CHANNEL_CPROT_LLMTBK_MASK) +#define SINC_CPROT_LLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LLMTBK_SHIFT)) & SINC_CPROT_LLMTBK_MASK) -#define SINC_CHANNEL_CPROT_WLMTBK_MASK (0x40000000U) -#define SINC_CHANNEL_CPROT_WLMTBK_SHIFT (30U) +#define SINC_CPROT_WLMTBK_MASK (0x40000000U) +#define SINC_CPROT_WLMTBK_SHIFT (30U) /*! WLMTBK - Window Limit Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_WLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_WLMTBK_SHIFT)) & SINC_CHANNEL_CPROT_WLMTBK_MASK) +#define SINC_CPROT_WLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_WLMTBK_SHIFT)) & SINC_CPROT_WLMTBK_MASK) -#define SINC_CHANNEL_CPROT_HLMTBK_MASK (0x80000000U) -#define SINC_CHANNEL_CPROT_HLMTBK_SHIFT (31U) +#define SINC_CPROT_HLMTBK_MASK (0x80000000U) +#define SINC_CPROT_HLMTBK_SHIFT (31U) /*! HLMTBK - High Limit Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_HLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_HLMTBK_SHIFT)) & SINC_CHANNEL_CPROT_HLMTBK_MASK) +#define SINC_CPROT_HLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_HLMTBK_SHIFT)) & SINC_CPROT_HLMTBK_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CPROT */ -#define SINC_CHANNEL_CPROT_COUNT (5U) +/* The count of SINC_CPROT */ +#define SINC_CPROT_COUNT (5U) -/*! @name CHANNEL_CBIAS - Channel 0 Bias..Channel 4 Bias */ +/*! @name CBIAS - Channel 0 Bias..Channel 4 Bias */ /*! @{ */ -#define SINC_CHANNEL_CBIAS_BIAS_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CBIAS_BIAS_SHIFT (8U) +#define SINC_CBIAS_BIAS_MASK (0xFFFFFF00U) +#define SINC_CBIAS_BIAS_SHIFT (8U) /*! BIAS - Bias Value */ -#define SINC_CHANNEL_CBIAS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CBIAS_BIAS_SHIFT)) & SINC_CHANNEL_CBIAS_BIAS_MASK) +#define SINC_CBIAS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CBIAS_BIAS_SHIFT)) & SINC_CBIAS_BIAS_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CBIAS */ -#define SINC_CHANNEL_CBIAS_COUNT (5U) +/* The count of SINC_CBIAS */ +#define SINC_CBIAS_COUNT (5U) -/*! @name CHANNEL_CLOLMT - Channel 0 Low Limit..Channel 4 Low Limit */ +/*! @name CLOLMT - Channel 0 Low Limit..Channel 4 Low Limit */ /*! @{ */ -#define SINC_CHANNEL_CLOLMT_LOLMT_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CLOLMT_LOLMT_SHIFT (8U) +#define SINC_CLOLMT_LOLMT_MASK (0xFFFFFF00U) +#define SINC_CLOLMT_LOLMT_SHIFT (8U) /*! LOLMT - Low Limit Threshold */ -#define SINC_CHANNEL_CLOLMT_LOLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CLOLMT_LOLMT_SHIFT)) & SINC_CHANNEL_CLOLMT_LOLMT_MASK) +#define SINC_CLOLMT_LOLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CLOLMT_LOLMT_SHIFT)) & SINC_CLOLMT_LOLMT_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CLOLMT */ -#define SINC_CHANNEL_CLOLMT_COUNT (5U) +/* The count of SINC_CLOLMT */ +#define SINC_CLOLMT_COUNT (5U) -/*! @name CHANNEL_CHILMT - Channel 0 High Limit..Channel 4 High Limit */ +/*! @name CHILMT - Channel 0 High Limit..Channel 4 High Limit */ /*! @{ */ -#define SINC_CHANNEL_CHILMT_HILMT_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CHILMT_HILMT_SHIFT (8U) +#define SINC_CHILMT_HILMT_MASK (0xFFFFFF00U) +#define SINC_CHILMT_HILMT_SHIFT (8U) /*! HILMT - High Limit Threshold */ -#define SINC_CHANNEL_CHILMT_HILMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CHILMT_HILMT_SHIFT)) & SINC_CHANNEL_CHILMT_HILMT_MASK) +#define SINC_CHILMT_HILMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHILMT_HILMT_SHIFT)) & SINC_CHILMT_HILMT_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CHILMT */ -#define SINC_CHANNEL_CHILMT_COUNT (5U) +/* The count of SINC_CHILMT */ +#define SINC_CHILMT_COUNT (5U) -/*! @name CHANNEL_CRDATA - Channel 0 Result Data..Channel 4 Result Data */ +/*! @name CRDATA - Channel 0 Result Data..Channel 4 Result Data */ /*! @{ */ -#define SINC_CHANNEL_CRDATA_RDATA_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CRDATA_RDATA_SHIFT (8U) +#define SINC_CRDATA_RDATA_MASK (0xFFFFFF00U) +#define SINC_CRDATA_RDATA_SHIFT (8U) /*! RDATA - Result Data */ -#define SINC_CHANNEL_CRDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CRDATA_RDATA_SHIFT)) & SINC_CHANNEL_CRDATA_RDATA_MASK) +#define SINC_CRDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CRDATA_RDATA_SHIFT)) & SINC_CRDATA_RDATA_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CRDATA */ -#define SINC_CHANNEL_CRDATA_COUNT (5U) +/* The count of SINC_CRDATA */ +#define SINC_CRDATA_COUNT (5U) -/*! @name CHANNEL_CMPDATA - Channel 0 Multipurpose Data..Channel 4 Multipurpose Data */ +/*! @name CMPDATA - Channel 0 Multipurpose Data..Channel 4 Multipurpose Data */ /*! @{ */ -#define SINC_CHANNEL_CMPDATA_MPDATA_MASK (0xFFFFFFFFU) -#define SINC_CHANNEL_CMPDATA_MPDATA_SHIFT (0U) +#define SINC_CMPDATA_MPDATA_MASK (0xFFFFFFFFU) +#define SINC_CMPDATA_MPDATA_SHIFT (0U) /*! MPDATA - Multipurpose Data */ -#define SINC_CHANNEL_CMPDATA_MPDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CMPDATA_MPDATA_SHIFT)) & SINC_CHANNEL_CMPDATA_MPDATA_MASK) +#define SINC_CMPDATA_MPDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CMPDATA_MPDATA_SHIFT)) & SINC_CMPDATA_MPDATA_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CMPDATA */ -#define SINC_CHANNEL_CMPDATA_COUNT (5U) +/* The count of SINC_CMPDATA */ +#define SINC_CMPDATA_COUNT (5U) -/*! @name CHANNEL_CACFR - Channel 0 Advanced Configuration..Channel 4 Advanced Configuration */ +/*! @name CACFR - Channel 0 Advanced Configuration..Channel 4 Advanced Configuration */ /*! @{ */ -#define SINC_CHANNEL_CACFR_ADMASEL_MASK (0xF000U) -#define SINC_CHANNEL_CACFR_ADMASEL_SHIFT (12U) +#define SINC_CACFR_ADMASEL_MASK (0xF000U) +#define SINC_CACFR_ADMASEL_SHIFT (12U) /*! ADMASEL - Alternate DMA Source Selection * 0b0000..Alternate DMA disabled * 0b0001..PF conversion complete @@ -77451,127 +70864,127 @@ typedef struct { * 0b1010..Clock absence * 0b1011..Saturation */ -#define SINC_CHANNEL_CACFR_ADMASEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CACFR_ADMASEL_SHIFT)) & SINC_CHANNEL_CACFR_ADMASEL_MASK) +#define SINC_CACFR_ADMASEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_ADMASEL_SHIFT)) & SINC_CACFR_ADMASEL_MASK) -#define SINC_CHANNEL_CACFR_HPFA_MASK (0xF0000U) -#define SINC_CHANNEL_CACFR_HPFA_SHIFT (16U) +#define SINC_CACFR_HPFA_MASK (0xF0000U) +#define SINC_CACFR_HPFA_SHIFT (16U) /*! HPFA - HPF DC Remover Alpha Coefficient */ -#define SINC_CHANNEL_CACFR_HPFA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CACFR_HPFA_SHIFT)) & SINC_CHANNEL_CACFR_HPFA_MASK) +#define SINC_CACFR_HPFA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_HPFA_SHIFT)) & SINC_CACFR_HPFA_MASK) -#define SINC_CHANNEL_CACFR_IBDLY_MASK (0xF00000U) -#define SINC_CHANNEL_CACFR_IBDLY_SHIFT (20U) +#define SINC_CACFR_IBDLY_MASK (0xF00000U) +#define SINC_CACFR_IBDLY_SHIFT (20U) /*! IBDLY - Input Modulator Bitstream Delay * 0b0000..Disabled * *..Delay in clock cycles */ -#define SINC_CHANNEL_CACFR_IBDLY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CACFR_IBDLY_SHIFT)) & SINC_CHANNEL_CACFR_IBDLY_MASK) +#define SINC_CACFR_IBDLY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_IBDLY_SHIFT)) & SINC_CACFR_IBDLY_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CACFR */ -#define SINC_CHANNEL_CACFR_COUNT (5U) +/* The count of SINC_CACFR */ +#define SINC_CACFR_COUNT (5U) -/*! @name CHANNEL_CSR - Channel 0 Status..Channel 4 Status */ +/*! @name CSR - Channel 0 Status..Channel 4 Status */ /*! @{ */ -#define SINC_CHANNEL_CSR_FIFOAVIL_MASK (0x1FU) -#define SINC_CHANNEL_CSR_FIFOAVIL_SHIFT (0U) +#define SINC_CSR_FIFOAVIL_MASK (0x1FU) +#define SINC_CSR_FIFOAVIL_SHIFT (0U) /*! FIFOAVIL - FIFO Available Data */ -#define SINC_CHANNEL_CSR_FIFOAVIL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_FIFOAVIL_SHIFT)) & SINC_CHANNEL_CSR_FIFOAVIL_MASK) +#define SINC_CSR_FIFOAVIL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_FIFOAVIL_SHIFT)) & SINC_CSR_FIFOAVIL_MASK) -#define SINC_CHANNEL_CSR_PSRDY_MASK (0x80U) -#define SINC_CHANNEL_CSR_PSRDY_SHIFT (7U) +#define SINC_CSR_PSRDY_MASK (0x80U) +#define SINC_CSR_PSRDY_SHIFT (7U) /*! PSRDY - Parallel or Serial Data Ready * 0b0..Not ready * 0b1..Ready */ -#define SINC_CHANNEL_CSR_PSRDY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_PSRDY_SHIFT)) & SINC_CHANNEL_CSR_PSRDY_MASK) +#define SINC_CSR_PSRDY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PSRDY_SHIFT)) & SINC_CSR_PSRDY_MASK) -#define SINC_CHANNEL_CSR_PFSAT_MASK (0x100U) -#define SINC_CHANNEL_CSR_PFSAT_SHIFT (8U) +#define SINC_CSR_PFSAT_MASK (0x100U) +#define SINC_CSR_PFSAT_SHIFT (8U) /*! PFSAT - Primary CIC Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_PFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_PFSAT_SHIFT)) & SINC_CHANNEL_CSR_PFSAT_MASK) +#define SINC_CSR_PFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PFSAT_SHIFT)) & SINC_CSR_PFSAT_MASK) -#define SINC_CHANNEL_CSR_HPFSAT_MASK (0x200U) -#define SINC_CHANNEL_CSR_HPFSAT_SHIFT (9U) +#define SINC_CSR_HPFSAT_MASK (0x200U) +#define SINC_CSR_HPFSAT_SHIFT (9U) /*! HPFSAT - HPF Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_HPFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_HPFSAT_SHIFT)) & SINC_CHANNEL_CSR_HPFSAT_MASK) +#define SINC_CSR_HPFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_HPFSAT_SHIFT)) & SINC_CSR_HPFSAT_MASK) -#define SINC_CHANNEL_CSR_SFTSAT_MASK (0x400U) -#define SINC_CHANNEL_CSR_SFTSAT_SHIFT (10U) +#define SINC_CSR_SFTSAT_MASK (0x400U) +#define SINC_CSR_SFTSAT_SHIFT (10U) /*! SFTSAT - Shift Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_SFTSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_SFTSAT_SHIFT)) & SINC_CHANNEL_CSR_SFTSAT_MASK) +#define SINC_CSR_SFTSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SFTSAT_SHIFT)) & SINC_CSR_SFTSAT_MASK) -#define SINC_CHANNEL_CSR_BIASSAT_MASK (0x800U) -#define SINC_CHANNEL_CSR_BIASSAT_SHIFT (11U) +#define SINC_CSR_BIASSAT_MASK (0x800U) +#define SINC_CSR_BIASSAT_SHIFT (11U) /*! BIASSAT - Bias Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_BIASSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_BIASSAT_SHIFT)) & SINC_CHANNEL_CSR_BIASSAT_MASK) +#define SINC_CSR_BIASSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_BIASSAT_SHIFT)) & SINC_CSR_BIASSAT_MASK) -#define SINC_CHANNEL_CSR_RDRS_MASK (0x1000U) -#define SINC_CHANNEL_CSR_RDRS_SHIFT (12U) +#define SINC_CSR_RDRS_MASK (0x1000U) +#define SINC_CSR_RDRS_SHIFT (12U) /*! RDRS - Result Data Direct Read Status * 0b0..Valid * 0b1..Invalid */ -#define SINC_CHANNEL_CSR_RDRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_RDRS_SHIFT)) & SINC_CHANNEL_CSR_RDRS_MASK) +#define SINC_CSR_RDRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_RDRS_SHIFT)) & SINC_CSR_RDRS_MASK) -#define SINC_CHANNEL_CSR_SRDS_MASK (0x2000U) -#define SINC_CHANNEL_CSR_SRDS_SHIFT (13U) +#define SINC_CSR_SRDS_MASK (0x2000U) +#define SINC_CSR_SRDS_SHIFT (13U) /*! SRDS - Start Read Debug Data Sync * 0b0..Data valid * 0b1..Procedure in progress * 0b0..No effect * 0b1..Starts the procedure */ -#define SINC_CHANNEL_CSR_SRDS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_SRDS_SHIFT)) & SINC_CHANNEL_CSR_SRDS_MASK) +#define SINC_CSR_SRDS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SRDS_SHIFT)) & SINC_CSR_SRDS_MASK) -#define SINC_CHANNEL_CSR_DBGRS_MASK (0xC000U) -#define SINC_CHANNEL_CSR_DBGRS_SHIFT (14U) +#define SINC_CSR_DBGRS_MASK (0xC000U) +#define SINC_CSR_DBGRS_SHIFT (14U) /*! DBGRS - Debug Data Read Status * 0b00..Valid * 0b01-0b11..Invalid */ -#define SINC_CHANNEL_CSR_DBGRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_DBGRS_SHIFT)) & SINC_CHANNEL_CSR_DBGRS_MASK) +#define SINC_CSR_DBGRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_DBGRS_SHIFT)) & SINC_CSR_DBGRS_MASK) -#define SINC_CHANNEL_CSR_CNUM_MASK (0x7F0000U) -#define SINC_CHANNEL_CSR_CNUM_SHIFT (16U) +#define SINC_CSR_CNUM_MASK (0x7F0000U) +#define SINC_CSR_CNUM_SHIFT (16U) /*! CNUM - Number Of Conversions */ -#define SINC_CHANNEL_CSR_CNUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_CNUM_SHIFT)) & SINC_CHANNEL_CSR_CNUM_MASK) +#define SINC_CSR_CNUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_SHIFT)) & SINC_CSR_CNUM_MASK) -#define SINC_CHANNEL_CSR_CNUM_OV_MASK (0x800000U) -#define SINC_CHANNEL_CSR_CNUM_OV_SHIFT (23U) +#define SINC_CSR_CNUM_OV_MASK (0x800000U) +#define SINC_CSR_CNUM_OV_SHIFT (23U) /*! CNUM_OV - Overflow In Number Of Conversions * 0b0..No overflow * 0b1..Overflow */ -#define SINC_CHANNEL_CSR_CNUM_OV(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_CNUM_OV_SHIFT)) & SINC_CHANNEL_CSR_CNUM_OV_MASK) +#define SINC_CSR_CNUM_OV(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_OV_SHIFT)) & SINC_CSR_CNUM_OV_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CSR */ -#define SINC_CHANNEL_CSR_COUNT (5U) +/* The count of SINC_CSR */ +#define SINC_CSR_COUNT (5U) -/*! @name CHANNEL_CDBGR - Channel 0 Debug..Channel 4 Debug */ +/*! @name CDBGR - Channel 0 Debug..Channel 4 Debug */ /*! @{ */ -#define SINC_CHANNEL_CDBGR_DBGDATA_MASK (0xFFFFFFFFU) -#define SINC_CHANNEL_CDBGR_DBGDATA_SHIFT (0U) +#define SINC_CDBGR_DBGDATA_MASK (0xFFFFFFFFU) +#define SINC_CDBGR_DBGDATA_SHIFT (0U) /*! DBGDATA - Debug Data */ -#define SINC_CHANNEL_CDBGR_DBGDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDBGR_DBGDATA_SHIFT)) & SINC_CHANNEL_CDBGR_DBGDATA_MASK) +#define SINC_CDBGR_DBGDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDBGR_DBGDATA_SHIFT)) & SINC_CDBGR_DBGDATA_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CDBGR */ -#define SINC_CHANNEL_CDBGR_COUNT (5U) +/* The count of SINC_CDBGR */ +#define SINC_CDBGR_COUNT (5U) /*! @@ -77613,580 +71026,6 @@ typedef struct { */ /* end of group SINC_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- SM3 Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SM3_Peripheral_Access_Layer SM3 Peripheral Access Layer - * @{ - */ - -/** SM3 - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[512]; - __IO uint32_t DATIN0A; /**< Input Data register 0 lower-bank low, offset: 0x200 */ - __IO uint32_t DATIN0B; /**< Input Data register 0 lower-bank high, offset: 0x204 */ - __IO uint32_t DATIN0C; /**< Input Data register 0 upper-bank low, offset: 0x208 */ - __IO uint32_t DATIN0D; /**< Input Data register 0 upper-bank high, offset: 0x20C */ - __IO uint32_t DATIN1A; /**< Input Data register 1 lower-bank low, offset: 0x210 */ - __IO uint32_t DATIN1B; /**< Input Data register 1 lower-bank high, offset: 0x214 */ - __IO uint32_t DATIN1C; /**< Input Data register 1 upper-bank low, offset: 0x218 */ - __IO uint32_t DATIN1D; /**< Input Data register 1 upper-bank high, offset: 0x21C */ - uint8_t RESERVED_1[32]; - __IO uint32_t KEY0A; /**< Input Key register 0 lower-bank low, offset: 0x240 */ - __IO uint32_t KEY0B; /**< Input Key register 0 lower-bank high, offset: 0x244 */ - __IO uint32_t KEY0C; /**< Input Key register 0 upper-bank low, offset: 0x248 */ - __IO uint32_t KEY0D; /**< Input Key register 0 upper-bank high, offset: 0x24C */ - __IO uint32_t KEY1A; /**< Input Key register 1 lower-bank low, offset: 0x250 */ - __IO uint32_t KEY1B; /**< Input Key register 1 lower-bank high, offset: 0x254 */ - __IO uint32_t KEY1C; /**< Input Key register 1 upper-bank low, offset: 0x258 */ - __IO uint32_t KEY1D; /**< Input Key register 1 upper-bank high, offset: 0x25C */ - uint8_t RESERVED_2[96]; - __I uint32_t DATOUTA; /**< Output Data register lower-bank low, offset: 0x2C0 */ - __I uint32_t DATOUTB; /**< Ouput Data register lower-bank high, offset: 0x2C4 */ - __I uint32_t DATOUTC; /**< Ouput Data register upper-bank low, offset: 0x2C8 */ - __I uint32_t DATOUTD; /**< Output Data register upper-bank high, offset: 0x2CC */ - uint8_t RESERVED_3[2352]; - __I uint32_t STATUS; /**< Status Register, offset: 0xC00 */ - __IO uint32_t COUNT; /**< Calculation Counter, offset: 0xC04 */ - uint8_t RESERVED_4[248]; - __IO uint32_t CTRL; /**< SGI Control Register, offset: 0xD00 */ - __IO uint32_t CTRL2; /**< SGI Control Register 2, offset: 0xD04 */ - uint8_t RESERVED_5[12]; - __IO uint32_t SM3_CTRL; /**< SM3 Control Register, offset: 0xD14 */ - __O uint32_t SM3_FIFO; /**< SM3 FIFO Register, offset: 0xD18 */ - __I uint32_t CONFIG; /**< SGI Configuration Register, offset: 0xD1C */ - uint8_t RESERVED_6[708]; - __IO uint32_t INT_ENABLE; /**< Interrupt Enable, offset: 0xFE4 */ - __O uint32_t INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0xFE8 */ - __O uint32_t INT_STATUS_SET; /**< Interrupt Status Set, offset: 0xFEC */ -} SM3_Type; - -/* ---------------------------------------------------------------------------- - -- SM3 Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SM3_Register_Masks SM3 Register Masks - * @{ - */ - -/*! @name DATIN0A - Input Data register 0 lower-bank low */ -/*! @{ */ - -#define SM3_DATIN0A_DATIN0A_MASK (0xFFFFFFFFU) -#define SM3_DATIN0A_DATIN0A_SHIFT (0U) -/*! DATIN0A - Input Data register */ -#define SM3_DATIN0A_DATIN0A(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0A_DATIN0A_SHIFT)) & SM3_DATIN0A_DATIN0A_MASK) -/*! @} */ - -/*! @name DATIN0B - Input Data register 0 lower-bank high */ -/*! @{ */ - -#define SM3_DATIN0B_DATIN0B_MASK (0xFFFFFFFFU) -#define SM3_DATIN0B_DATIN0B_SHIFT (0U) -/*! DATIN0B - Input Data register */ -#define SM3_DATIN0B_DATIN0B(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0B_DATIN0B_SHIFT)) & SM3_DATIN0B_DATIN0B_MASK) -/*! @} */ - -/*! @name DATIN0C - Input Data register 0 upper-bank low */ -/*! @{ */ - -#define SM3_DATIN0C_DATIN0C_MASK (0xFFFFFFFFU) -#define SM3_DATIN0C_DATIN0C_SHIFT (0U) -/*! DATIN0C - Input Data register */ -#define SM3_DATIN0C_DATIN0C(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0C_DATIN0C_SHIFT)) & SM3_DATIN0C_DATIN0C_MASK) -/*! @} */ - -/*! @name DATIN0D - Input Data register 0 upper-bank high */ -/*! @{ */ - -#define SM3_DATIN0D_DATIN0D_MASK (0xFFFFFFFFU) -#define SM3_DATIN0D_DATIN0D_SHIFT (0U) -/*! DATIN0D - Input Data register */ -#define SM3_DATIN0D_DATIN0D(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0D_DATIN0D_SHIFT)) & SM3_DATIN0D_DATIN0D_MASK) -/*! @} */ - -/*! @name DATIN1A - Input Data register 1 lower-bank low */ -/*! @{ */ - -#define SM3_DATIN1A_DATIN1A_MASK (0xFFFFFFFFU) -#define SM3_DATIN1A_DATIN1A_SHIFT (0U) -/*! DATIN1A - Input Data register */ -#define SM3_DATIN1A_DATIN1A(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1A_DATIN1A_SHIFT)) & SM3_DATIN1A_DATIN1A_MASK) -/*! @} */ - -/*! @name DATIN1B - Input Data register 1 lower-bank high */ -/*! @{ */ - -#define SM3_DATIN1B_DATIN1B_MASK (0xFFFFFFFFU) -#define SM3_DATIN1B_DATIN1B_SHIFT (0U) -/*! DATIN1B - Input Data register */ -#define SM3_DATIN1B_DATIN1B(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1B_DATIN1B_SHIFT)) & SM3_DATIN1B_DATIN1B_MASK) -/*! @} */ - -/*! @name DATIN1C - Input Data register 1 upper-bank low */ -/*! @{ */ - -#define SM3_DATIN1C_DATIN1C_MASK (0xFFFFFFFFU) -#define SM3_DATIN1C_DATIN1C_SHIFT (0U) -/*! DATIN1C - Input Data register */ -#define SM3_DATIN1C_DATIN1C(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1C_DATIN1C_SHIFT)) & SM3_DATIN1C_DATIN1C_MASK) -/*! @} */ - -/*! @name DATIN1D - Input Data register 1 upper-bank high */ -/*! @{ */ - -#define SM3_DATIN1D_DATIN1D_MASK (0xFFFFFFFFU) -#define SM3_DATIN1D_DATIN1D_SHIFT (0U) -/*! DATIN1D - Input Data register */ -#define SM3_DATIN1D_DATIN1D(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1D_DATIN1D_SHIFT)) & SM3_DATIN1D_DATIN1D_MASK) -/*! @} */ - -/*! @name KEY0A - Input Key register 0 lower-bank low */ -/*! @{ */ - -#define SM3_KEY0A_KEY0A_MASK (0xFFFFFFFFU) -#define SM3_KEY0A_KEY0A_SHIFT (0U) -/*! KEY0A - Input Key register */ -#define SM3_KEY0A_KEY0A(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0A_KEY0A_SHIFT)) & SM3_KEY0A_KEY0A_MASK) -/*! @} */ - -/*! @name KEY0B - Input Key register 0 lower-bank high */ -/*! @{ */ - -#define SM3_KEY0B_KEY0B_MASK (0xFFFFFFFFU) -#define SM3_KEY0B_KEY0B_SHIFT (0U) -/*! KEY0B - Input Key register */ -#define SM3_KEY0B_KEY0B(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0B_KEY0B_SHIFT)) & SM3_KEY0B_KEY0B_MASK) -/*! @} */ - -/*! @name KEY0C - Input Key register 0 upper-bank low */ -/*! @{ */ - -#define SM3_KEY0C_KEY0C_MASK (0xFFFFFFFFU) -#define SM3_KEY0C_KEY0C_SHIFT (0U) -/*! KEY0C - Input Key register */ -#define SM3_KEY0C_KEY0C(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0C_KEY0C_SHIFT)) & SM3_KEY0C_KEY0C_MASK) -/*! @} */ - -/*! @name KEY0D - Input Key register 0 upper-bank high */ -/*! @{ */ - -#define SM3_KEY0D_KEY0D_MASK (0xFFFFFFFFU) -#define SM3_KEY0D_KEY0D_SHIFT (0U) -/*! KEY0D - Input Key register */ -#define SM3_KEY0D_KEY0D(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0D_KEY0D_SHIFT)) & SM3_KEY0D_KEY0D_MASK) -/*! @} */ - -/*! @name KEY1A - Input Key register 1 lower-bank low */ -/*! @{ */ - -#define SM3_KEY1A_KEY1A_MASK (0xFFFFFFFFU) -#define SM3_KEY1A_KEY1A_SHIFT (0U) -/*! KEY1A - Input Key register */ -#define SM3_KEY1A_KEY1A(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1A_KEY1A_SHIFT)) & SM3_KEY1A_KEY1A_MASK) -/*! @} */ - -/*! @name KEY1B - Input Key register 1 lower-bank high */ -/*! @{ */ - -#define SM3_KEY1B_KEY1B_MASK (0xFFFFFFFFU) -#define SM3_KEY1B_KEY1B_SHIFT (0U) -/*! KEY1B - Input Key register */ -#define SM3_KEY1B_KEY1B(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1B_KEY1B_SHIFT)) & SM3_KEY1B_KEY1B_MASK) -/*! @} */ - -/*! @name KEY1C - Input Key register 1 upper-bank low */ -/*! @{ */ - -#define SM3_KEY1C_KEY1C_MASK (0xFFFFFFFFU) -#define SM3_KEY1C_KEY1C_SHIFT (0U) -/*! KEY1C - Input Key register */ -#define SM3_KEY1C_KEY1C(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1C_KEY1C_SHIFT)) & SM3_KEY1C_KEY1C_MASK) -/*! @} */ - -/*! @name KEY1D - Input Key register 1 upper-bank high */ -/*! @{ */ - -#define SM3_KEY1D_KEY1D_MASK (0xFFFFFFFFU) -#define SM3_KEY1D_KEY1D_SHIFT (0U) -/*! KEY1D - Input Key register */ -#define SM3_KEY1D_KEY1D(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1D_KEY1D_SHIFT)) & SM3_KEY1D_KEY1D_MASK) -/*! @} */ - -/*! @name DATOUTA - Output Data register lower-bank low */ -/*! @{ */ - -#define SM3_DATOUTA_DATOUTA_MASK (0xFFFFFFFFU) -#define SM3_DATOUTA_DATOUTA_SHIFT (0U) -/*! DATOUTA - Output Data register */ -#define SM3_DATOUTA_DATOUTA(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTA_DATOUTA_SHIFT)) & SM3_DATOUTA_DATOUTA_MASK) -/*! @} */ - -/*! @name DATOUTB - Ouput Data register lower-bank high */ -/*! @{ */ - -#define SM3_DATOUTB_DATOUTB_MASK (0xFFFFFFFFU) -#define SM3_DATOUTB_DATOUTB_SHIFT (0U) -/*! DATOUTB - Ouput Data register */ -#define SM3_DATOUTB_DATOUTB(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTB_DATOUTB_SHIFT)) & SM3_DATOUTB_DATOUTB_MASK) -/*! @} */ - -/*! @name DATOUTC - Ouput Data register upper-bank low */ -/*! @{ */ - -#define SM3_DATOUTC_DATOUTC_MASK (0xFFFFFFFFU) -#define SM3_DATOUTC_DATOUTC_SHIFT (0U) -/*! DATOUTC - Ouput Data register */ -#define SM3_DATOUTC_DATOUTC(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTC_DATOUTC_SHIFT)) & SM3_DATOUTC_DATOUTC_MASK) -/*! @} */ - -/*! @name DATOUTD - Output Data register upper-bank high */ -/*! @{ */ - -#define SM3_DATOUTD_DOUTD_MASK (0xFFFFFFFFU) -#define SM3_DATOUTD_DOUTD_SHIFT (0U) -/*! DOUTD - Output Data register */ -#define SM3_DATOUTD_DOUTD(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTD_DOUTD_SHIFT)) & SM3_DATOUTD_DOUTD_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ - -#define SM3_STATUS_BUSY_MASK (0x1U) -#define SM3_STATUS_BUSY_SHIFT (0U) -/*! BUSY - Busy Flag */ -#define SM3_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_BUSY_SHIFT)) & SM3_STATUS_BUSY_MASK) - -#define SM3_STATUS_PRNG_RDY_MASK (0x4U) -#define SM3_STATUS_PRNG_RDY_SHIFT (2U) -/*! PRNG_RDY - PRNG Ready */ -#define SM3_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_PRNG_RDY_SHIFT)) & SM3_STATUS_PRNG_RDY_MASK) - -#define SM3_STATUS_ERROR_MASK (0x38U) -#define SM3_STATUS_ERROR_SHIFT (3U) -/*! ERROR - Error Indicator */ -#define SM3_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_ERROR_SHIFT)) & SM3_STATUS_ERROR_MASK) - -#define SM3_STATUS_SM3_BUSY_MASK (0x40U) -#define SM3_STATUS_SM3_BUSY_SHIFT (6U) -/*! SM3_BUSY - SM3 Busy Status Flag */ -#define SM3_STATUS_SM3_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_BUSY_SHIFT)) & SM3_STATUS_SM3_BUSY_MASK) - -#define SM3_STATUS_IRQ_MASK (0x80U) -#define SM3_STATUS_IRQ_SHIFT (7U) -/*! IRQ - Interrupt Status Flag */ -#define SM3_STATUS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_IRQ_SHIFT)) & SM3_STATUS_IRQ_MASK) - -#define SM3_STATUS_SM3_FIFO_FULL_MASK (0x100U) -#define SM3_STATUS_SM3_FIFO_FULL_SHIFT (8U) -/*! SM3_FIFO_FULL - SM3 FIFO Full Indicator */ -#define SM3_STATUS_SM3_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_FIFO_FULL_SHIFT)) & SM3_STATUS_SM3_FIFO_FULL_MASK) - -#define SM3_STATUS_SM3_FIFO_LEVEL_MASK (0x7E00U) -#define SM3_STATUS_SM3_FIFO_LEVEL_SHIFT (9U) -/*! SM3_FIFO_LEVEL - SM3 FIFO Level */ -#define SM3_STATUS_SM3_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_FIFO_LEVEL_SHIFT)) & SM3_STATUS_SM3_FIFO_LEVEL_MASK) - -#define SM3_STATUS_SM3_ERROR_MASK (0x8000U) -#define SM3_STATUS_SM3_ERROR_SHIFT (15U) -/*! SM3_ERROR - SM3 ERROR */ -#define SM3_STATUS_SM3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_ERROR_SHIFT)) & SM3_STATUS_SM3_ERROR_MASK) -/*! @} */ - -/*! @name COUNT - Calculation Counter */ -/*! @{ */ - -#define SM3_COUNT_COUNT_MASK (0xFFFFU) -#define SM3_COUNT_COUNT_SHIFT (0U) -/*! COUNT - Calculation Counter */ -#define SM3_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SM3_COUNT_COUNT_SHIFT)) & SM3_COUNT_COUNT_MASK) -/*! @} */ - -/*! @name CTRL - SGI Control Register */ -/*! @{ */ - -#define SM3_CTRL_START_MASK (0x1U) -#define SM3_CTRL_START_SHIFT (0U) -/*! START - Start Crypto Operation */ -#define SM3_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL_START_SHIFT)) & SM3_CTRL_START_MASK) - -#define SM3_CTRL_CRYPTO_OP_MASK (0x70U) -#define SM3_CTRL_CRYPTO_OP_SHIFT (4U) -/*! CRYPTO_OP - Crypto Operation Type */ -#define SM3_CTRL_CRYPTO_OP(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL_CRYPTO_OP_SHIFT)) & SM3_CTRL_CRYPTO_OP_MASK) - -#define SM3_CTRL_DATOUT_RES_MASK (0xC000U) -#define SM3_CTRL_DATOUT_RES_SHIFT (14U) -/*! DATOUT_RES - Kernels Data Out Options */ -#define SM3_CTRL_DATOUT_RES(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL_DATOUT_RES_SHIFT)) & SM3_CTRL_DATOUT_RES_MASK) -/*! @} */ - -/*! @name CTRL2 - SGI Control Register 2 */ -/*! @{ */ - -#define SM3_CTRL2_FLUSH_MASK (0x1U) -#define SM3_CTRL2_FLUSH_SHIFT (0U) -/*! FLUSH - Start Full SGI Flush */ -#define SM3_CTRL2_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_FLUSH_SHIFT)) & SM3_CTRL2_FLUSH_MASK) - -#define SM3_CTRL2_KEY_FLUSH_MASK (0x2U) -#define SM3_CTRL2_KEY_FLUSH_SHIFT (1U) -/*! KEY_FLUSH - Start KEY register-bank Flush */ -#define SM3_CTRL2_KEY_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_KEY_FLUSH_SHIFT)) & SM3_CTRL2_KEY_FLUSH_MASK) - -#define SM3_CTRL2_DATIN_FLUSH_MASK (0x4U) -#define SM3_CTRL2_DATIN_FLUSH_SHIFT (2U) -/*! DATIN_FLUSH - Start DATIN register-bank Flush */ -#define SM3_CTRL2_DATIN_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_DATIN_FLUSH_SHIFT)) & SM3_CTRL2_DATIN_FLUSH_MASK) - -#define SM3_CTRL2_FLUSHWR_MASK (0x20U) -#define SM3_CTRL2_FLUSHWR_SHIFT (5U) -/*! FLUSHWR - Flush Write control */ -#define SM3_CTRL2_FLUSHWR(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_FLUSHWR_SHIFT)) & SM3_CTRL2_FLUSHWR_MASK) - -#define SM3_CTRL2_BYTES_ORDER_MASK (0x400000U) -#define SM3_CTRL2_BYTES_ORDER_SHIFT (22U) -/*! BYTES_ORDER - Byte order of regbank read/write data */ -#define SM3_CTRL2_BYTES_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_BYTES_ORDER_SHIFT)) & SM3_CTRL2_BYTES_ORDER_MASK) -/*! @} */ - -/*! @name SM3_CTRL - SM3 Control Register */ -/*! @{ */ - -#define SM3_SM3_CTRL_SM3_MODE_MASK (0x2U) -#define SM3_SM3_CTRL_SM3_MODE_SHIFT (1U) -/*! SM3_MODE - SM3 mode normal or automatic */ -#define SM3_SM3_CTRL_SM3_MODE(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_MODE_SHIFT)) & SM3_SM3_CTRL_SM3_MODE_MASK) - -#define SM3_SM3_CTRL_SM3_LOW_LIM_MASK (0xF0U) -#define SM3_SM3_CTRL_SM3_LOW_LIM_SHIFT (4U) -/*! SM3_LOW_LIM - SM3 FIFO low limit */ -#define SM3_SM3_CTRL_SM3_LOW_LIM(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_LOW_LIM_SHIFT)) & SM3_SM3_CTRL_SM3_LOW_LIM_MASK) - -#define SM3_SM3_CTRL_SM3_HIGH_LIM_MASK (0xF00U) -#define SM3_SM3_CTRL_SM3_HIGH_LIM_SHIFT (8U) -/*! SM3_HIGH_LIM - SM3 FIFO high limit */ -#define SM3_SM3_CTRL_SM3_HIGH_LIM(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_HIGH_LIM_SHIFT)) & SM3_SM3_CTRL_SM3_HIGH_LIM_MASK) - -#define SM3_SM3_CTRL_SM3_COUNT_EN_MASK (0x1000U) -#define SM3_SM3_CTRL_SM3_COUNT_EN_SHIFT (12U) -/*! SM3_COUNT_EN - SM3 Calculation Counter Enable */ -#define SM3_SM3_CTRL_SM3_COUNT_EN(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_COUNT_EN_SHIFT)) & SM3_SM3_CTRL_SM3_COUNT_EN_MASK) - -#define SM3_SM3_CTRL_HASH_RELOAD_MASK (0x2000U) -#define SM3_SM3_CTRL_HASH_RELOAD_SHIFT (13U) -/*! HASH_RELOAD - SM3 HASH reload */ -#define SM3_SM3_CTRL_HASH_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_HASH_RELOAD_SHIFT)) & SM3_SM3_CTRL_HASH_RELOAD_MASK) - -#define SM3_SM3_CTRL_SM3_STOP_MASK (0x4000U) -#define SM3_SM3_CTRL_SM3_STOP_SHIFT (14U) -/*! SM3_STOP - STOP SM3 AUTO mode */ -#define SM3_SM3_CTRL_SM3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_STOP_SHIFT)) & SM3_SM3_CTRL_SM3_STOP_MASK) - -#define SM3_SM3_CTRL_NO_AUTO_INIT_MASK (0x8000U) -#define SM3_SM3_CTRL_NO_AUTO_INIT_SHIFT (15U) -/*! NO_AUTO_INIT - SM3 no automatic HASH initialisation. */ -#define SM3_SM3_CTRL_NO_AUTO_INIT(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_NO_AUTO_INIT_SHIFT)) & SM3_SM3_CTRL_NO_AUTO_INIT_MASK) - -#define SM3_SM3_CTRL_SM3_EN_MASK (0x10000U) -#define SM3_SM3_CTRL_SM3_EN_SHIFT (16U) -/*! SM3_EN - SM3 enable */ -#define SM3_SM3_CTRL_SM3_EN(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_EN_SHIFT)) & SM3_SM3_CTRL_SM3_EN_MASK) -/*! @} */ - -/*! @name SM3_FIFO - SM3 FIFO Register */ -/*! @{ */ - -#define SM3_SM3_FIFO_FIFO_MASK (0xFFFFFFFFU) -#define SM3_SM3_FIFO_FIFO_SHIFT (0U) -/*! FIFO - SM3 FIFO Register */ -#define SM3_SM3_FIFO_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_FIFO_FIFO_SHIFT)) & SM3_SM3_FIFO_FIFO_MASK) -/*! @} */ - -/*! @name CONFIG - SGI Configuration Register */ -/*! @{ */ - -#define SM3_CONFIG_ROW_MASK (0x1U) -#define SM3_CONFIG_ROW_SHIFT (0U) -/*! ROW - ROW */ -#define SM3_CONFIG_ROW(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_ROW_SHIFT)) & SM3_CONFIG_ROW_MASK) - -#define SM3_CONFIG_CHINA_MASK (0x2U) -#define SM3_CONFIG_CHINA_SHIFT (1U) -/*! CHINA - CHINA */ -#define SM3_CONFIG_CHINA(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_CHINA_SHIFT)) & SM3_CONFIG_CHINA_MASK) - -#define SM3_CONFIG_CC_MASK (0x4U) -#define SM3_CONFIG_CC_SHIFT (2U) -/*! CC - CC */ -#define SM3_CONFIG_CC(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_CC_SHIFT)) & SM3_CONFIG_CC_MASK) - -#define SM3_CONFIG_HAS_AES_MASK (0x8U) -#define SM3_CONFIG_HAS_AES_SHIFT (3U) -/*! HAS_AES - Has AES */ -#define SM3_CONFIG_HAS_AES(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_AES_SHIFT)) & SM3_CONFIG_HAS_AES_MASK) - -#define SM3_CONFIG_HAS_DES_MASK (0x10U) -#define SM3_CONFIG_HAS_DES_SHIFT (4U) -/*! HAS_DES - Has DES */ -#define SM3_CONFIG_HAS_DES(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_DES_SHIFT)) & SM3_CONFIG_HAS_DES_MASK) - -#define SM3_CONFIG_HAS_SHA_MASK (0x20U) -#define SM3_CONFIG_HAS_SHA_SHIFT (5U) -/*! HAS_SHA - Has SHA */ -#define SM3_CONFIG_HAS_SHA(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_SHA_SHIFT)) & SM3_CONFIG_HAS_SHA_MASK) - -#define SM3_CONFIG_HAS_MOVEM_MASK (0x40U) -#define SM3_CONFIG_HAS_MOVEM_SHIFT (6U) -/*! HAS_MOVEM - Has MOVEM */ -#define SM3_CONFIG_HAS_MOVEM(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_MOVEM_SHIFT)) & SM3_CONFIG_HAS_MOVEM_MASK) - -#define SM3_CONFIG_HAS_CMAC_MASK (0x80U) -#define SM3_CONFIG_HAS_CMAC_SHIFT (7U) -/*! HAS_CMAC - Has CMAC */ -#define SM3_CONFIG_HAS_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_CMAC_SHIFT)) & SM3_CONFIG_HAS_CMAC_MASK) - -#define SM3_CONFIG_HAS_GFMUL_MASK (0x100U) -#define SM3_CONFIG_HAS_GFMUL_SHIFT (8U) -/*! HAS_GFMUL - Has GFMUL */ -#define SM3_CONFIG_HAS_GFMUL(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_GFMUL_SHIFT)) & SM3_CONFIG_HAS_GFMUL_MASK) - -#define SM3_CONFIG_INTERNAL_PRNG_MASK (0x200U) -#define SM3_CONFIG_INTERNAL_PRNG_SHIFT (9U) -/*! INTERNAL_PRNG - Has internal PRNG */ -#define SM3_CONFIG_INTERNAL_PRNG(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_INTERNAL_PRNG_SHIFT)) & SM3_CONFIG_INTERNAL_PRNG_MASK) - -#define SM3_CONFIG_KEY_DIGEST_MASK (0x400U) -#define SM3_CONFIG_KEY_DIGEST_SHIFT (10U) -/*! KEY_DIGEST - Has key digest */ -#define SM3_CONFIG_KEY_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_KEY_DIGEST_SHIFT)) & SM3_CONFIG_KEY_DIGEST_MASK) - -#define SM3_CONFIG_MST_MASK (0x4000U) -#define SM3_CONFIG_MST_SHIFT (14U) -/*! MST - Has MST */ -#define SM3_CONFIG_MST(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_MST_SHIFT)) & SM3_CONFIG_MST_MASK) - -#define SM3_CONFIG_BUS_WIDTH_MASK (0x8000U) -#define SM3_CONFIG_BUS_WIDTH_SHIFT (15U) -/*! BUS_WIDTH - Bus width */ -#define SM3_CONFIG_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_BUS_WIDTH_SHIFT)) & SM3_CONFIG_BUS_WIDTH_MASK) - -#define SM3_CONFIG_NUM_DATIN_MASK (0x30000U) -#define SM3_CONFIG_NUM_DATIN_SHIFT (16U) -/*! NUM_DATIN - Number DATIN */ -#define SM3_CONFIG_NUM_DATIN(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_NUM_DATIN_SHIFT)) & SM3_CONFIG_NUM_DATIN_MASK) - -#define SM3_CONFIG_NUM_KEY_MASK (0x1C0000U) -#define SM3_CONFIG_NUM_KEY_SHIFT (18U) -/*! NUM_KEY - Number KEY */ -#define SM3_CONFIG_NUM_KEY(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_NUM_KEY_SHIFT)) & SM3_CONFIG_NUM_KEY_MASK) - -#define SM3_CONFIG_EDC_MASK (0x200000U) -#define SM3_CONFIG_EDC_SHIFT (21U) -/*! EDC - EDC enable */ -#define SM3_CONFIG_EDC(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_EDC_SHIFT)) & SM3_CONFIG_EDC_MASK) - -#define SM3_CONFIG_DUAL_SGI_MASK (0x400000U) -#define SM3_CONFIG_DUAL_SGI_SHIFT (22U) -/*! DUAL_SGI - Has dual SGI */ -#define SM3_CONFIG_DUAL_SGI(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_DUAL_SGI_SHIFT)) & SM3_CONFIG_DUAL_SGI_MASK) - -#define SM3_CONFIG_SHA_256_ONLY_MASK (0x1000000U) -#define SM3_CONFIG_SHA_256_ONLY_SHIFT (24U) -/*! SHA_256_ONLY - Has SHA 256 only */ -#define SM3_CONFIG_SHA_256_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SHA_256_ONLY_SHIFT)) & SM3_CONFIG_SHA_256_ONLY_MASK) - -#define SM3_CONFIG_SPB_SUPPORT_MASK (0x2000000U) -#define SM3_CONFIG_SPB_SUPPORT_SHIFT (25U) -/*! SPB_SUPPORT - ID_CFG_SPB_SUPPORT is set */ -#define SM3_CONFIG_SPB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SPB_SUPPORT_SHIFT)) & SM3_CONFIG_SPB_SUPPORT_MASK) - -#define SM3_CONFIG_SPB_MASKING_MASK (0x4000000U) -#define SM3_CONFIG_SPB_MASKING_SHIFT (26U) -/*! SPB_MASKING - ID_CFG_SGI_SPB_MASKING is set */ -#define SM3_CONFIG_SPB_MASKING(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SPB_MASKING_SHIFT)) & SM3_CONFIG_SPB_MASKING_MASK) - -#define SM3_CONFIG_SFR_SW_MASK_MASK (0x8000000U) -#define SM3_CONFIG_SFR_SW_MASK_SHIFT (27U) -/*! SFR_SW_MASK - ID_CFG_SGI_USE_SFR_SW_MASK is set */ -#define SM3_CONFIG_SFR_SW_MASK(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SFR_SW_MASK_SHIFT)) & SM3_CONFIG_SFR_SW_MASK_MASK) - -#define SM3_CONFIG_HAS_SM3_MASK (0x10000000U) -#define SM3_CONFIG_HAS_SM3_SHIFT (28U) -/*! HAS_SM3 - Has SM3 */ -#define SM3_CONFIG_HAS_SM3(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_SM3_SHIFT)) & SM3_CONFIG_HAS_SM3_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt Enable */ -/*! @{ */ - -#define SM3_INT_ENABLE_INT_EN_MASK (0x1U) -#define SM3_INT_ENABLE_INT_EN_SHIFT (0U) -/*! INT_EN - Interrupt enable bit */ -#define SM3_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SM3_INT_ENABLE_INT_EN_SHIFT)) & SM3_INT_ENABLE_INT_EN_MASK) -/*! @} */ - -/*! @name INT_STATUS_CLR - Interrupt Status Clear */ -/*! @{ */ - -#define SM3_INT_STATUS_CLR_INT_CLR_MASK (0x1U) -#define SM3_INT_STATUS_CLR_INT_CLR_SHIFT (0U) -/*! INT_CLR - Interrupt Status Clear */ -#define SM3_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SM3_INT_STATUS_CLR_INT_CLR_SHIFT)) & SM3_INT_STATUS_CLR_INT_CLR_MASK) -/*! @} */ - -/*! @name INT_STATUS_SET - Interrupt Status Set */ -/*! @{ */ - -#define SM3_INT_STATUS_SET_INT_SET_MASK (0x1U) -#define SM3_INT_STATUS_SET_INT_SET_SHIFT (0U) -/*! INT_SET - Set Interrupt by SW */ -#define SM3_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << SM3_INT_STATUS_SET_INT_SET_SHIFT)) & SM3_INT_STATUS_SET_INT_SET_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SM3_Register_Masks */ - - -/* SM3 - Peripheral instance base addresses */ -#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral SM3_0 base address */ - #define SM3_0_BASE (0x50031000u) - /** Peripheral SM3_0 base address */ - #define SM3_0_BASE_NS (0x40031000u) - /** Peripheral SM3_0 base pointer */ - #define SM3_0 ((SM3_Type *)SM3_0_BASE) - /** Peripheral SM3_0 base pointer */ - #define SM3_0_NS ((SM3_Type *)SM3_0_BASE_NS) - /** Array initializer of SM3 peripheral base addresses */ - #define SM3_BASE_ADDRS { SM3_0_BASE } - /** Array initializer of SM3 peripheral base pointers */ - #define SM3_BASE_PTRS { SM3_0 } - /** Array initializer of SM3 peripheral base addresses */ - #define SM3_BASE_ADDRS_NS { SM3_0_BASE_NS } - /** Array initializer of SM3 peripheral base pointers */ - #define SM3_BASE_PTRS_NS { SM3_0_NS } -#else - /** Peripheral SM3_0 base address */ - #define SM3_0_BASE (0x40031000u) - /** Peripheral SM3_0 base pointer */ - #define SM3_0 ((SM3_Type *)SM3_0_BASE) - /** Array initializer of SM3 peripheral base addresses */ - #define SM3_BASE_ADDRS { SM3_0_BASE } - /** Array initializer of SM3 peripheral base pointers */ - #define SM3_BASE_PTRS { SM3_0 } -#endif - -/*! - * @} - */ /* end of group SM3_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- SMARTDMA Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -78440,7 +71279,7 @@ typedef struct { __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ __IO uint32_t VD_IO_CFG; /**< IO Voltage Detect Configuration, offset: 0x13C */ __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ - __IO uint32_t VDD_CORE_GLITCH_DETECT_SC; /**< VDD Core Glitch Detect Status Control, offset: 0x144 */ + __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ uint8_t RESERVED_7[440]; __IO uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ uint8_t RESERVED_8[252]; @@ -78495,7 +71334,7 @@ typedef struct { #define SPC_SC_SPC_LP_REQ_MASK (0x2U) #define SPC_SC_SPC_LP_REQ_SHIFT (1U) /*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag - * 0b0..SPC is in Active mode; the ACTIVE_CFG register has control + * 0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register * 0b0..No effect * 0b1..Clear the flag @@ -78620,7 +71459,7 @@ typedef struct { * 0b00.. * 0b01..1.0 V * 0b10..1.1 V - * 0b11..SRAM configured for 1.2 V operation + * 0b11.. */ #define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) @@ -78699,9 +71538,9 @@ typedef struct { #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) -/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable - * 0b0..VDD Core Low Voltage Glitch Detect enabled - * 0b1..VDD Core Low Voltage Glitch Detect disabled +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Low Voltage Glitch Detect enabled + * 0b1..Low Voltage Glitch Detect disabled */ #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) @@ -78803,11 +71642,10 @@ typedef struct { #define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) #define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level - * 0b00..Under voltage (0.95 V) + * 0b00..Retention voltage * 0b01..Mid voltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) - * *.. */ #define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) @@ -78832,8 +71670,7 @@ typedef struct { #define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00.. - * 0b00.. + * 0b00..Retention voltage (0.7 V) * 0b01..Mid voltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) @@ -78842,7 +71679,7 @@ typedef struct { #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) -/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable * 0b0..Enable * 0b1..Disable */ @@ -78963,7 +71800,7 @@ typedef struct { #define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) #define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) -/*! COREVDD_LVDF - Core VDD Low-Voltage Detect Flag +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect @@ -78973,7 +71810,7 @@ typedef struct { #define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) #define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) -/*! SYSVDD_LVDF - System VDD Low-Voltage Detect Flag +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect @@ -79003,7 +71840,7 @@ typedef struct { #define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) #define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) -/*! SYSVDD_HVDF - System VDD HVD Flag +/*! SYSVDD_HVDF - System HVD Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect @@ -79027,7 +71864,7 @@ typedef struct { #define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) #define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) -/*! LVDRE - Core VDD LVD Reset Enable +/*! LVDRE - Core LVD Reset Enable * 0b0..Disable * 0b1..Enable */ @@ -79035,7 +71872,7 @@ typedef struct { #define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) #define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) -/*! LVDIE - Core VDD LVD Interrupt Enable +/*! LVDIE - Core LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ @@ -79071,7 +71908,7 @@ typedef struct { #define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) #define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) -/*! LVDRE - System VDD LVD Reset Enable +/*! LVDRE - System LVD Reset Enable * 0b0..Disable * 0b1..Enable */ @@ -79079,7 +71916,7 @@ typedef struct { #define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) #define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) -/*! LVDIE - System VDD LVD Interrupt Enable +/*! LVDIE - System LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ @@ -79087,7 +71924,7 @@ typedef struct { #define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) #define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) -/*! HVDRE - System VDD HVD Reset Enable +/*! HVDRE - System HVD Reset Enable * 0b0..Disable * 0b1..Enable */ @@ -79095,20 +71932,12 @@ typedef struct { #define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) #define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) -/*! HVDIE - System VDD HVD Interrupt Enable +/*! HVDIE - System HVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) -#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) -#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) -/*! LVSEL - System VDD Low-Voltage Level Select - * 0b0..Normal - * 0b1..Safe - */ -#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) - #define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) #define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) /*! LOCK - System Voltage Detect Reset Enable Lock @@ -79156,8 +71985,8 @@ typedef struct { #define SPC_VD_IO_CFG_LVSEL_MASK (0x100U) #define SPC_VD_IO_CFG_LVSEL_SHIFT (8U) /*! LVSEL - IO VDD Low-Voltage Level Select - * 0b0..Normal - * 0b1..Safe + * 0b0..High range + * 0b1..Low range */ #define SPC_VD_IO_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK) @@ -79189,52 +72018,52 @@ typedef struct { #define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) /*! @} */ -/*! @name VDD_CORE_GLITCH_DETECT_SC - VDD Core Glitch Detect Status Control */ +/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ /*! @{ */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) /*! CNT_SELECT - Counter Select * 0b00..0 * 0b01..1 * 0b10..2 * 0b11..3 */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) /*! TIMEOUT - Timeout */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK) +#define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK (0x40U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_SHIFT (6U) -/*! RE - Core VDD Glitch Detect Reset Enable +#define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) +#define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) +/*! RE - Glitch Detect Reset Enable * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK) +#define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK (0x80U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_SHIFT (7U) -/*! IE - Core VDD Glitch Detect Interrupt Enable +#define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) +#define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) +/*! IE - Glitch Detect Interrupt Enable * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK) +#define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) /*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_SHIFT (16U) -/*! LOCK - VDD Core Voltage Glitch Detect Reset Enable Lock Bit +#define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) +#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) +/*! LOCK - Glitch Detect Reset Enable Lock Bit * 0b0..Writes to RE are allowed. * 0b1..Writes to RE are ignored. */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) +#define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) /*! @} */ /*! @name CORELDO_CFG - LDO_CORE Configuration */ @@ -79528,12 +72357,14 @@ typedef struct { __O uint32_t REF_CLK_CTRL_SET; /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */ __O uint32_t REF_CLK_CTRL_CLR; /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */ __IO uint32_t GDET_CTRL[2]; /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */ - uint8_t RESERVED_40[12]; + __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection Register, offset: 0x974 */ + __IO uint32_t ELS_LOCK_CTRL; /**< ELS Lock Control, offset: 0x978 */ + __IO uint32_t ELS_LOCK_CTRL_DP; /**< ELS Lock Control DP, offset: 0x97C */ __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0x980 */ __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0x984 */ __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0x988 */ __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0x98C */ - uint8_t RESERVED_41[64]; + uint8_t RESERVED_40[64]; __I uint32_t ELS_AS_CFG0; /**< ELS AS Configuration, offset: 0x9D0 */ __I uint32_t ELS_AS_CFG1; /**< ELS AS Configuration1, offset: 0x9D4 */ __I uint32_t ELS_AS_CFG2; /**< ELS AS Configuration2, offset: 0x9D8 */ @@ -79541,21 +72372,21 @@ typedef struct { __I uint32_t ELS_AS_ST0; /**< ELS AS State Register, offset: 0x9E0 */ __I uint32_t ELS_AS_ST1; /**< ELS AS State1, offset: 0x9E4 */ __I uint32_t ELS_AS_BOOT_LOG0; /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */ - __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: N-boot library log, offset: 0x9EC */ + __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: Library log, offset: 0x9EC */ __I uint32_t ELS_AS_BOOT_LOG2; /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */ __I uint32_t ELS_AS_BOOT_LOG3; /**< Boot state captured during boot: Security log, offset: 0x9F4 */ __I uint32_t ELS_AS_FLAG0; /**< ELS AS Flag0, offset: 0x9F8 */ __I uint32_t ELS_AS_FLAG1; /**< ELS AS Flag1, offset: 0x9FC */ - uint8_t RESERVED_42[24]; + uint8_t RESERVED_41[24]; __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ - uint8_t RESERVED_43[276]; + uint8_t RESERVED_42[276]; __IO uint32_t I3C1FCLKSEL; /**< I3C1 Functional Clock Selection, offset: 0xB30 */ __IO uint32_t I3C1FCLKSTCSEL; /**< Selects the I3C1 Time Control clock, offset: 0xB34 */ __IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ __IO uint32_t I3C1FCLKSDIV; /**< I3C1 FCLK Slow clock Divider, offset: 0xB3C */ __IO uint32_t I3C1FCLKDIV; /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */ __IO uint32_t I3C1FCLKSSEL; /**< I3C1 FCLK Slow Selection, offset: 0xB44 */ - uint8_t RESERVED_44[8]; + uint8_t RESERVED_43[8]; __IO uint32_t ETB_STATUS; /**< ETB Counter Status Register, offset: 0xB50 */ __IO uint32_t ETB_COUNTER_CTRL; /**< ETB Counter Control Register, offset: 0xB54 */ __IO uint32_t ETB_COUNTER_RELOAD; /**< ETB Counter Reload Register, offset: 0xB58 */ @@ -79564,25 +72395,25 @@ typedef struct { __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */ __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ - uint8_t RESERVED_45[660]; + uint8_t RESERVED_44[660]; __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control Automatic Clock Gating, offset: 0xE04 */ - uint8_t RESERVED_46[36]; + uint8_t RESERVED_45[36]; __IO uint32_t AUTOCLKGATEOVERRIDEC; /**< Control Automatic Clock Gating C, offset: 0xE2C */ - uint8_t RESERVED_47[8]; + uint8_t RESERVED_46[8]; __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0xE38 */ __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0xE3C */ __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0xE40 */ __IO uint32_t ECC_ENABLE_CTRL; /**< RAM ECC Enable Control, offset: 0xE44 */ - uint8_t RESERVED_48[344]; + uint8_t RESERVED_47[344]; __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ - uint8_t RESERVED_49[8]; + uint8_t RESERVED_48[8]; __IO uint32_t SWD_ACCESS_CPU[2]; /**< CPU0 Software Debug Access..CPU1 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ - uint8_t RESERVED_50[4]; + uint8_t RESERVED_49[4]; __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ __IO uint32_t SWD_ACCESS_DSP; /**< DSP Software Debug Access, offset: 0xFC4 */ - uint8_t RESERVED_51[40]; + uint8_t RESERVED_50[40]; __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ @@ -79818,13 +72649,17 @@ typedef struct { #define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is not exact or not given. */ +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ #define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) #define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor. 0 = reference - * clock is provided; 1 = no reference clock is provided. +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided */ #define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) /*! @} */ @@ -80418,21 +73253,21 @@ typedef struct { */ #define SYSCON_PRESETCTRL3_COOLFLUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_COOLFLUX_RST_SHIFT)) & SYSCON_PRESETCTRL3_COOLFLUX_RST_MASK) -#define SYSCON_PRESETCTRL3_ENC0_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL3_ENC0_RST_SHIFT (4U) -/*! ENC0_RST - ENC0 reset control +#define SYSCON_PRESETCTRL3_QDC0_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT (4U) +/*! QDC0_RST - QDC0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ -#define SYSCON_PRESETCTRL3_ENC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC0_RST_MASK) +#define SYSCON_PRESETCTRL3_QDC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK) -#define SYSCON_PRESETCTRL3_ENC1_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL3_ENC1_RST_SHIFT (5U) -/*! ENC1_RST - ENC1 reset control +#define SYSCON_PRESETCTRL3_QDC1_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT (5U) +/*! QDC1_RST - QDC1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ -#define SYSCON_PRESETCTRL3_ENC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC1_RST_MASK) +#define SYSCON_PRESETCTRL3_QDC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK) #define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x40U) #define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (6U) @@ -81266,21 +74101,21 @@ typedef struct { */ #define SYSCON_AHBCLKCTRL3_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_COOLFLUX_SHIFT)) & SYSCON_AHBCLKCTRL3_COOLFLUX_MASK) -#define SYSCON_AHBCLKCTRL3_ENC0_MASK (0x10U) -#define SYSCON_AHBCLKCTRL3_ENC0_SHIFT (4U) -/*! ENC0 - Enables the clock for ENC0 +#define SYSCON_AHBCLKCTRL3_QDC0_MASK (0x10U) +#define SYSCON_AHBCLKCTRL3_QDC0_SHIFT (4U) +/*! QDC0 - Enables the clock for QDC0 * 0b1..Enables clock * 0b0..Disables clock */ -#define SYSCON_AHBCLKCTRL3_ENC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC0_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC0_MASK) +#define SYSCON_AHBCLKCTRL3_QDC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK) -#define SYSCON_AHBCLKCTRL3_ENC1_MASK (0x20U) -#define SYSCON_AHBCLKCTRL3_ENC1_SHIFT (5U) -/*! ENC1 - Enables the clock for ENC1 +#define SYSCON_AHBCLKCTRL3_QDC1_MASK (0x20U) +#define SYSCON_AHBCLKCTRL3_QDC1_SHIFT (5U) +/*! QDC1 - Enables the clock for QDC1 * 0b1..Enables clock * 0b0..Disables clock */ -#define SYSCON_AHBCLKCTRL3_ENC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC1_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC1_MASK) +#define SYSCON_AHBCLKCTRL3_QDC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK) #define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x40U) #define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (6U) @@ -81606,7 +74441,7 @@ typedef struct { * 0b001..PLL divided clock * 0b010..FRO 12 MHz clock * 0b011..fro_hf_div clock - * 0b100..CLK_1MHz clock + * 0b100..clk_1m clock * 0b101..USB PLL clock * 0b110..LP Oscillator clock * 0b111..No clock @@ -84175,6 +77010,39 @@ typedef struct { /* The count of SYSCON_GDETX_CTRL_GDET_CTRL */ #define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT (2U) +/*! @name ELS_ASSET_PROT - ELS Asset Protection Register */ +/*! @{ */ + +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U) +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U) +/*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the + * ELS module. Refer to the ELS chapter in the SRM for more details. + * 0b00..ELS asset is protected + * 0b10..ELS asset is protected + * 0b11..ELS asset is protected + * 0b01..ELS asset is not protected + */ +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL - ELS Lock Control */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - ELS Lock Control */ +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U) +/*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */ +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK) +/*! @} */ + /*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ /*! @{ */ @@ -84678,7 +77546,7 @@ typedef struct { #define SYSCON_ELS_AS_BOOT_LOG0_ISP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK) /*! @} */ -/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: N-boot library log */ +/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */ /*! @{ */ #define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK (0x3U) @@ -84745,16 +77613,6 @@ typedef struct { #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U) /*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */ #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK) - -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_MASK (0xFF0000U) -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_SHIFT (16U) -/*! ERR_CFG_FAIL_COUNT - CFPA->ERR_CFG_FAIL_COUNT[7:0] */ -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_MASK) - -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_MASK (0xFF000000U) -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_SHIFT (24U) -/*! ERR_COUNT3 - CFPA->ERR_COUNT3[7:0] */ -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_MASK) /*! @} */ /*! @name ELS_AS_FLAG0 - ELS AS Flag0 */ @@ -85032,7 +77890,7 @@ typedef struct { #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U) -/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTIMER0/1 modules. +/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ @@ -85048,7 +77906,7 @@ typedef struct { #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK (0x8U) #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT (3U) -/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTIMER0/1, and Frequency Measurement modules +/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules * 0b1..Clock is enabled * 0b0..Clock is not enabled */ @@ -85064,7 +77922,7 @@ typedef struct { #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enables clk_in clock for MICFIL, EMVSIM0/1, CAN0/1, I3C0/1, SAI0/1, SINC Filter (SINC), TSI, USBFS, SCT, uSDHC, clkout. +/*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ @@ -86049,659 +78907,1907 @@ typedef struct { /* ---------------------------------------------------------------------------- - -- TRNG Peripheral Access Layer + -- TRDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer * @{ */ -/** TRNG - Register Layout Typedef */ +/** TRDC - Register Layout Typedef */ typedef struct { - __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ - __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - union { /* offset: 0x18 */ - __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ - __I uint32_t OSC2_FRQCNT; /**< Oscillator-2 Frequency Count Register, offset: 0x18 */ - }; - union { /* offset: 0x1C */ - __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ - __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ - }; - union { /* offset: 0x20 */ - __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ - __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ - }; - union { /* offset: 0x24 */ - __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ - __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ - }; - union { /* offset: 0x28 */ - __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ - __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ - }; - union { /* offset: 0x2C */ - __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ - __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ - }; - uint8_t RESERVED_2[12]; - __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ - __I uint32_t ENT[8]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_3[64]; - __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ - __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ - __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ - __I uint32_t CSER; /**< Common Security Error Register, offset: 0xB0 */ - __O uint32_t CSCLR; /**< Common Security Clear Register, offset: 0xB4 */ - uint8_t RESERVED_4[52]; - __IO uint32_t OSC2_CTL; /**< TRNG Oscillator 2 Control Register, offset: 0xEC */ - __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ - __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ -} TRNG_Type; + struct { /* offset: 0x0, array step: 0x1CC */ + __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_0[224]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */ + } MBC_INDEX[1]; +} TRDC_Type; /* ---------------------------------------------------------------------------- - -- TRNG Register Masks + -- TRDC Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @addtogroup TRDC_Register_Masks TRDC Register Masks * @{ */ -/*! @name MCTL - Miscellaneous Control Register */ +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ /*! @{ */ -#define TRNG_MCTL_OSC_DIV_MASK (0xCU) -#define TRNG_MCTL_OSC_DIV_SHIFT (2U) -/*! OSC_DIV - Oscillator1 Divide - * 0b00..use ring oscillator with no divide - * 0b01..use ring oscillator divided-by-2 - * 0b10..use ring oscillator divided-by-4 - * 0b11..use ring oscillator divided-by-8 - */ -#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) -#define TRNG_MCTL_DIS_SLF_TST_MASK (0x10U) -#define TRNG_MCTL_DIS_SLF_TST_SHIFT (4U) -/*! DIS_SLF_TST - Disable Self-Tests */ -#define TRNG_MCTL_DIS_SLF_TST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_DIS_SLF_TST_SHIFT)) & TRNG_MCTL_DIS_SLF_TST_MASK) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) -#define TRNG_MCTL_RST_DEF_MASK (0x40U) -#define TRNG_MCTL_RST_DEF_SHIFT (6U) -/*! RST_DEF - Reset Defaults - * 0b0..No impact. - * 0b1..Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state. - */ -#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) - -#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) -#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) -/*! FCT_FAIL - Frequency Count Fail */ -#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) - -#define TRNG_MCTL_FCT_VAL_MASK (0x200U) -#define TRNG_MCTL_FCT_VAL_SHIFT (9U) -/*! FCT_VAL - Frequency Count Valid - * 0b0..Frequency Count is not valid - * 0b1..Frequency Count is valid - */ -#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) - -#define TRNG_MCTL_ENT_VAL_MASK (0x400U) -#define TRNG_MCTL_ENT_VAL_SHIFT (10U) -/*! ENT_VAL - Entropy Valid - * 0b0..Entropy is not valid - * 0b1..Entropy is valid - */ -#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) - -#define TRNG_MCTL_ERR_MASK (0x1000U) -#define TRNG_MCTL_ERR_SHIFT (12U) -/*! ERR - Error Status - * 0b0..No error - * 0b1..Error detected - */ -#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) - -#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) -#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) -/*! TSTOP_OK - TRNG is ok to stop - * 0b0..TRNG is generating entropy and is not ok to stop - * 0b1..TRNG is not generating entropy and is ok to stop - */ -#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) - -#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) -#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) -/*! LRUN_CONT - Long run count continues between entropy generations - * 0b0..The internal test's long run count is restarted for each entropy re-generation. - * 0b1..The count value (of TRNG's internal long_run test), at the start of an entropy generation will continue - * where it left off at the end of the previous entropy generation. - */ -#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) - -#define TRNG_MCTL_OSC2_FAIL_MASK (0x8000U) -#define TRNG_MCTL_OSC2_FAIL_SHIFT (15U) -/*! OSC2_FAIL - Oscillator 2 Failure - * 0b0..Oscillator 2 is running. - * 0b1..Oscillator 2 has failed (see OSC2_CTL[OSC_FAILSAFE_LMT]). - */ -#define TRNG_MCTL_OSC2_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC2_FAIL_SHIFT)) & TRNG_MCTL_OSC2_FAIL_MASK) - -#define TRNG_MCTL_PRGM_MASK (0x10000U) -#define TRNG_MCTL_PRGM_SHIFT (16U) -/*! PRGM - Program Mode - * 0b0..TRNG is in Run Mode - * 0b1..TRNG is in Program Mode - */ -#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) /*! @} */ -/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ /*! @{ */ -#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) -#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) -#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK) -#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) -#define TRNG_SCMISC_RTY_CT_SHIFT (16U) -#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK) /*! @} */ -/*! @name SDCTL - Seed Control Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ /*! @{ */ -#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) -#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) -#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) - -#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) -#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) -#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK) /*! @} */ -/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ /*! @{ */ -#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) -#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) -#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK) /*! @} */ -/*! @name OSC2_FRQCNT - Oscillator-2 Frequency Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ /*! @{ */ -#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT (0U) -#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT)) & TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) /*! @} */ -/*! @name FRQCNT - Frequency Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ /*! @{ */ -#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) -#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) /*! @} */ -/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ -#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) -#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) -#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) /*! @} */ -/*! @name SCMC - Statistical Check Monobit Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ -#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) -#define TRNG_SCMC_MONO_CT_SHIFT (0U) -#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) /*! @} */ -/*! @name SCML - Statistical Check Monobit Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ -#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) -#define TRNG_SCML_MONO_MAX_SHIFT (0U) -#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) -#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) -#define TRNG_SCML_MONO_RNG_SHIFT (16U) -#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) /*! @} */ -/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ -#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) -#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) -/*! R1_0_CT - Runs of Zero, Length 1 Count */ -#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) -#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) -#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) -/*! R1_1_CT - Runs of One, Length 1 Count */ -#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) /*! @} */ -/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ -#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) -#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) -/*! RUN1_MAX - Run Length 1 Maximum Limit */ -#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) -#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) -#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) -/*! RUN1_RNG - Run Length 1 Range */ -#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) /*! @} */ -/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ -#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) -#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) -#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) -#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) -#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) -#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) /*! @} */ -/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ -/*! @{ */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U) -#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) -#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) -#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) - -#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) -#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) -#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) -/*! @} */ - -/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ -/*! @{ */ - -#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) -#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) -#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) - -#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) -#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) -#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) -/*! @} */ - -/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ -/*! @{ */ - -#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) -#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) -#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) - -#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) -#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) -#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ - -#define TRNG_STATUS_TF1BR0_MASK (0x1U) -#define TRNG_STATUS_TF1BR0_SHIFT (0U) -/*! TF1BR0 - * 0b0..The 1-Bit Run, Sampling 0s Test has passed - * 0b1..The 1-Bit Run, Sampling 0s Test has failed - */ -#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) - -#define TRNG_STATUS_TF1BR1_MASK (0x2U) -#define TRNG_STATUS_TF1BR1_SHIFT (1U) -/*! TF1BR1 - * 0b0..The 1-Bit Run, Sampling 1s Test has passed - * 0b1..The 1-Bit Run, Sampling 1s Test has failed - */ -#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) - -#define TRNG_STATUS_TF2BR0_MASK (0x4U) -#define TRNG_STATUS_TF2BR0_SHIFT (2U) -/*! TF2BR0 - * 0b0..The 2-Bit Run, Sampling 0s Test has passed - * 0b1..The 2-Bit Run, Sampling 0s Test has failed - */ -#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) - -#define TRNG_STATUS_TF2BR1_MASK (0x8U) -#define TRNG_STATUS_TF2BR1_SHIFT (3U) -/*! TF2BR1 - * 0b0..The 2-Bit Run, Sampling 1s Test has passed - * 0b1..The 2-Bit Run, Sampling 1s Test has failed - */ -#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) - -#define TRNG_STATUS_TF3BR0_MASK (0x10U) -#define TRNG_STATUS_TF3BR0_SHIFT (4U) -/*! TF3BR0 - * 0b0..The 3-Bit Run, Sampling 0s Test has passed - * 0b1..The 3-Bit Run, Sampling 0s Test has failed - */ -#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) - -#define TRNG_STATUS_TF3BR1_MASK (0x20U) -#define TRNG_STATUS_TF3BR1_SHIFT (5U) -/*! TF3BR1 - Test Fail - * 0b0..The 3-Bit Run, Sampling 1s Test has passed - * 0b1..The 3-Bit Run, Sampling 1s Test has failed - */ -#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) - -#define TRNG_STATUS_TFLR_MASK (0x2000U) -#define TRNG_STATUS_TFLR_SHIFT (13U) -/*! TFLR - Test Fail, Long Run. - * 0b0..The Long Run Test has passed - * 0b1..The Long Run Test has failed - */ -#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) - -#define TRNG_STATUS_TFMB_MASK (0x8000U) -#define TRNG_STATUS_TFMB_SHIFT (15U) -/*! TFMB - * 0b0..The Mono Bit Test has passed - * 0b1..The Mono Bit Test has failed - */ -#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) - -#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) -#define TRNG_STATUS_RETRY_CT_SHIFT (16U) -#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) -/*! @} */ - -/*! @name ENT - Entropy Read Register */ -/*! @{ */ - -#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) -#define TRNG_ENT_ENT_SHIFT (0U) -#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) -/*! @} */ - -/* The count of TRNG_ENT */ -#define TRNG_ENT_COUNT (8U) - -/*! @name SEC_CFG - Security Configuration Register */ -/*! @{ */ - -#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) -#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) -/*! NO_PRGM - * 0b0..TRNG configuration registers can be modified. - * 0b1..TRNG configuration registers cannot be modified. - */ -#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) -/*! @} */ - -/*! @name INT_CTRL - Interrupt Control Register */ -/*! @{ */ - -#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) -#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..Clears the INT_STATUS[HW_ERR] bit. Will automatically set after writing. - * 0b1..Enables the INT_STATUS[HW_ERR] bit to be set, thereby enabling interrupt generation for the HW_ERR condition. - */ -#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) - -#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) -#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Clears the INT_STATUS[ENT_VAL] bit. Will automatically set after writing. - * 0b1..Enables the INT_STATUS[ENT_VAL] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition. - */ -#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) - -#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..Clears the INT_STATUS[FRQ_CT_FAIL] bit. Will automatically set after writing. - * 0b1..Enables the INT_STATUS[FRQ_CT_FAIL] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition. - */ -#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_MASK - Mask Register */ -/*! @{ */ - -#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) -#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..HW_ERR interrupt is disabled. - * 0b1..HW_ERR interrupt is enabled. - */ -#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) - -#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) -#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..ENT_VAL interrupt is disabled. - * 0b1..ENT_VAL interrupt is enabled. - */ -#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) - -#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..FRQ_CT_FAIL interrupt is disabled. - * 0b1..FRQ_CT_FAIL interrupt is enabled. - */ -#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ - -#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) -#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..No error. - * 0b1..Error detected. - */ -#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) - -#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) -#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Busy generating entropy. Any value read from the Entropy registers is invalid. - * 0b1..Values read from the Entropy registers are valid. - */ -#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) - -#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..No hardware nor self test frequency errors. - * 0b1..The frequency counter has detected a failure. - */ -#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name CSER - Common Security Error Register */ -/*! @{ */ - -#define TRNG_CSER_RED_FSM_MASK (0x2U) -#define TRNG_CSER_RED_FSM_SHIFT (1U) -/*! RED_FSM - Redundant FSM error/fault detected - * 0b0..No redundant FSM error/fault - * 0b1..Redundant FSM error/fault detected. - */ -#define TRNG_CSER_RED_FSM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSER_RED_FSM_SHIFT)) & TRNG_CSER_RED_FSM_MASK) -/*! @} */ - -/*! @name CSCLR - Common Security Clear Register */ -/*! @{ */ - -#define TRNG_CSCLR_RED_FSM_CLR_MASK (0x2U) -#define TRNG_CSCLR_RED_FSM_CLR_SHIFT (1U) -/*! RED_FSM_CLR - * 0b0..No effect, ignored - * 0b1..Clears the CSER[RED_FSM] bit. - */ -#define TRNG_CSCLR_RED_FSM_CLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSCLR_RED_FSM_CLR_SHIFT)) & TRNG_CSCLR_RED_FSM_CLR_MASK) -/*! @} */ - -/*! @name OSC2_CTL - TRNG Oscillator 2 Control Register */ -/*! @{ */ - -#define TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK (0x3U) -#define TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT (0U) -/*! TRNG_ENT_CTL - TRNG entropy generation control. - * 0b00..Single oscillator mode, using OSC1 (default) - * 0b01..Dual oscillator mode - * 0b10..Single oscillator mode, using OSC2 - * 0b11..Unused, (bit field cannot be written to this value) - */ -#define TRNG_OSC2_CTL_TRNG_ENT_CTL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT)) & TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK) - -#define TRNG_OSC2_CTL_OSC2_DIV_MASK (0xCU) -#define TRNG_OSC2_CTL_OSC2_DIV_SHIFT (2U) -/*! OSC2_DIV - Oscillator 2 Divide. - * 0b00..Use ring oscillator 2 with no divide - * 0b01..Use ring oscillator 2 divided-by-2 - * 0b10..Use ring oscillator 2 divided-by-4 - * 0b11..Use ring oscillator 2 divided-by-8 - */ -#define TRNG_OSC2_CTL_OSC2_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_DIV_SHIFT)) & TRNG_OSC2_CTL_OSC2_DIV_MASK) - -#define TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK (0x200U) -#define TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT (9U) -/*! OSC2_FCT_VAL - TRNG Oscillator 2 Frequency Count Valid - * 0b0..Frequency count is invalid. - * 0b1..If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT. - */ -#define TRNG_OSC2_CTL_OSC2_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT)) & TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK) - -#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK (0x3000U) -#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT (12U) -/*! OSC_FAILSAFE_LMT - Oscillator fail safe limit. - * 0b00..The limit N is 4096 (2^12) system clocks. - * 0b01..The limit N is 65536 (2^16) system clocks. (default) - * 0b10..N is 2^20 system clocks. - * 0b11..N is 2^22 system clocks (full range of the counter being used). - */ -#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK) - -#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK (0x4000U) -#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT (14U) -/*! OSC_FAILSAFE_TEST - Oscillator fail safe test. - * 0b0..No impact. - * 0b1..Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b). - */ -#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK) -/*! @} */ - -/*! @name VID1 - Version ID Register (MS) */ -/*! @{ */ - -#define TRNG_VID1_MIN_REV_MASK (0xFFU) -#define TRNG_VID1_MIN_REV_SHIFT (0U) -/*! MIN_REV - * 0b00001011..Minor revision number for TRNG. - */ -#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) - -#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) -#define TRNG_VID1_MAJ_REV_SHIFT (8U) -/*! MAJ_REV - * 0b00010100..Major revision number for TRNG. - */ -#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) - -#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) -#define TRNG_VID1_IP_ID_SHIFT (16U) -/*! IP_ID - * 0b0000000000110000..ID for TRNG. - */ -#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name VID2 - Version ID Register (LS) */ -/*! @{ */ - -#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) -#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) -/*! CONFIG_OPT - * 0b00000000..TRNG_CONFIG_OPT for TRNG. - */ -#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) - -#define TRNG_VID2_ECO_REV_MASK (0xFF00U) -#define TRNG_VID2_ECO_REV_SHIFT (8U) -/*! ECO_REV - * 0b00000000..TRNG_ECO_REV for TRNG. - */ -#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) - -#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) -#define TRNG_VID2_INTG_OPT_SHIFT (16U) -/*! INTG_OPT - * 0b00001010..INTG_OPT for TRNG. - */ -#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) - -#define TRNG_VID2_ERA_MASK (0xFF000000U) -#define TRNG_VID2_ERA_SHIFT (24U) -/*! ERA - * 0b00001011..ERA of the TRNG. - */ -#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) -/*! @} */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) /*! * @} - */ /* end of group TRNG_Register_Masks */ + */ /* end of group TRDC_Register_Masks */ -/* TRNG - Peripheral instance base addresses */ +/* TRDC - Peripheral instance base addresses */ #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) - /** Peripheral TRNG0 base address */ - #define TRNG0_BASE (0x5005A000u) - /** Peripheral TRNG0 base address */ - #define TRNG0_BASE_NS (0x4005A000u) - /** Peripheral TRNG0 base pointer */ - #define TRNG0 ((TRNG_Type *)TRNG0_BASE) - /** Peripheral TRNG0 base pointer */ - #define TRNG0_NS ((TRNG_Type *)TRNG0_BASE_NS) - /** Array initializer of TRNG peripheral base addresses */ - #define TRNG_BASE_ADDRS { TRNG0_BASE } - /** Array initializer of TRNG peripheral base pointers */ - #define TRNG_BASE_PTRS { TRNG0 } - /** Array initializer of TRNG peripheral base addresses */ - #define TRNG_BASE_ADDRS_NS { TRNG0_BASE_NS } - /** Array initializer of TRNG peripheral base pointers */ - #define TRNG_BASE_PTRS_NS { TRNG0_NS } + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } #else - /** Peripheral TRNG0 base address */ - #define TRNG0_BASE (0x4005A000u) - /** Peripheral TRNG0 base pointer */ - #define TRNG0 ((TRNG_Type *)TRNG0_BASE) - /** Array initializer of TRNG peripheral base addresses */ - #define TRNG_BASE_ADDRS { TRNG0_BASE } - /** Array initializer of TRNG peripheral base pointers */ - #define TRNG_BASE_PTRS { TRNG0 } + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } #endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + /*! * @} - */ /* end of group TRNG_Peripheral_Access_Layer */ + */ /* end of group TRDC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- @@ -89440,7 +83546,7 @@ typedef struct { /** USBHS - Register Layout Typedef */ typedef struct { - __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t ID; /**< Identification, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ @@ -89463,9 +83569,9 @@ typedef struct { uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; - __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ - __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ - __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ @@ -89482,17 +83588,17 @@ typedef struct { uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ - __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; - __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t OTGSC; /**< On-The-Go Status & Control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ - __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control 0, offset: 0x1C0 */ __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ } USBHS_Type; @@ -89505,22 +83611,22 @@ typedef struct { * @{ */ -/*! @name ID - Identification register */ +/*! @name ID - Identification */ /*! @{ */ #define USBHS_ID_ID_MASK (0x3FU) #define USBHS_ID_ID_SHIFT (0U) -/*! ID - ID */ +/*! ID - Configuration Number */ #define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK) #define USBHS_ID_NID_MASK (0x3F00U) #define USBHS_ID_NID_SHIFT (8U) -/*! NID - NID */ +/*! NID - Complement Version of ID */ #define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK) #define USBHS_ID_REVISION_MASK (0xFF0000U) #define USBHS_ID_REVISION_SHIFT (16U) -/*! REVISION - REVISION */ +/*! REVISION - Revision Number of the Controller Core */ #define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK) /*! @} */ @@ -89529,7 +83635,7 @@ typedef struct { #define USBHS_HWGENERAL_PHYW_MASK (0x30U) #define USBHS_HWGENERAL_PHYW_SHIFT (4U) -/*! PHYW - PHYW +/*! PHYW - Data width of the transceiver connected to the controller core * 0b00..8 bit wide data bus (Software non-programmable) * 0b01..16 bit wide data bus (Software non-programmable) * 0b10..Reset to 8 bit wide data bus (Software programmable) @@ -89539,7 +83645,7 @@ typedef struct { #define USBHS_HWGENERAL_PHYM_MASK (0x1C0U) #define USBHS_HWGENERAL_PHYM_SHIFT (6U) -/*! PHYM - PHYM +/*! PHYM - Transceiver Type * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI @@ -89553,9 +83659,9 @@ typedef struct { #define USBHS_HWGENERAL_SM_MASK (0x600U) #define USBHS_HWGENERAL_SM_SHIFT (9U) -/*! SM - SM - * 0b00..No Serial Engine, always use parallel signalling. - * 0b01..Serial Engine present, always use serial signalling for FS/LS. +/*! SM - Serial interface mode capability + * 0b00..No Serial Engine, always use parallel signalling + * 0b01..Serial Engine present, always use serial signalling for FS/LS * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ @@ -89567,7 +83673,7 @@ typedef struct { #define USBHS_HWHOST_HC_MASK (0x1U) #define USBHS_HWHOST_HC_SHIFT (0U) -/*! HC - HC +/*! HC - Host Capable * 0b1..Supported * 0b0..Not supported */ @@ -89575,7 +83681,7 @@ typedef struct { #define USBHS_HWHOST_NPORT_MASK (0xEU) #define USBHS_HWHOST_NPORT_SHIFT (1U) -/*! NPORT - NPORT */ +/*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */ #define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK) /*! @} */ @@ -89584,7 +83690,7 @@ typedef struct { #define USBHS_HWDEVICE_DC_MASK (0x1U) #define USBHS_HWDEVICE_DC_SHIFT (0U) -/*! DC - DC +/*! DC - Device Capable * 0b1..Supported * 0b0..Not supported */ @@ -89592,7 +83698,7 @@ typedef struct { #define USBHS_HWDEVICE_DEVEP_MASK (0x3EU) #define USBHS_HWDEVICE_DEVEP_SHIFT (1U) -/*! DEVEP - DEVEP */ +/*! DEVEP - Device Endpoint Number */ #define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK) /*! @} */ @@ -89601,12 +83707,12 @@ typedef struct { #define USBHS_HWTXBUF_TXBURST_MASK (0xFFU) #define USBHS_HWTXBUF_TXBURST_SHIFT (0U) -/*! TXBURST - TXBURST */ +/*! TXBURST - Default burst size for memory to TX buffer transfer */ #define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK) #define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U) -/*! TXCHANADD - TXCHANADD */ +/*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */ #define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK) /*! @} */ @@ -89615,12 +83721,12 @@ typedef struct { #define USBHS_HWRXBUF_RXBURST_MASK (0xFFU) #define USBHS_HWRXBUF_RXBURST_SHIFT (0U) -/*! RXBURST - RXBURST */ +/*! RXBURST - Default burst size for memory to RX buffer transfer */ #define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK) #define USBHS_HWRXBUF_RXADD_MASK (0xFF00U) #define USBHS_HWRXBUF_RXADD_SHIFT (8U) -/*! RXADD - RXADD */ +/*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */ #define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK) /*! @} */ @@ -89629,7 +83735,7 @@ typedef struct { #define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U) -/*! GPTLD - GPTLD */ +/*! GPTLD - General Purpose Timer Load Value */ #define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK) /*! @} */ @@ -89638,12 +83744,12 @@ typedef struct { #define USBHS_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -/*! GPTCNT - GPTCNT */ +/*! GPTCNT - General Purpose Timer Counter */ #define USBHS_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK) #define USBHS_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -/*! GPTMODE - GPTMODE +/*! GPTMODE - General Purpose Timer Mode * 0b0..One Shot Mode * 0b1..Repeat Mode */ @@ -89651,7 +83757,7 @@ typedef struct { #define USBHS_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USBHS_GPTIMER0CTRL_GPTRST_SHIFT (30U) -/*! GPTRST - GPTRST +/*! GPTRST - General Purpose Timer Reset * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ @@ -89659,7 +83765,7 @@ typedef struct { #define USBHS_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -/*! GPTRUN - GPTRUN +/*! GPTRUN - General Purpose Timer Run * 0b0..Stop counting * 0b1..Run */ @@ -89671,7 +83777,7 @@ typedef struct { #define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U) -/*! GPTLD - GPTLD */ +/*! GPTLD - General Purpose Timer Load Value */ #define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK) /*! @} */ @@ -89680,12 +83786,12 @@ typedef struct { #define USBHS_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -/*! GPTCNT - GPTCNT */ +/*! GPTCNT - General Purpose Timer Counter */ #define USBHS_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK) #define USBHS_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -/*! GPTMODE - GPTMODE +/*! GPTMODE - General Purpose Timer Mode * 0b0..One Shot Mode * 0b1..Repeat Mode */ @@ -89693,7 +83799,7 @@ typedef struct { #define USBHS_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USBHS_GPTIMER1CTRL_GPTRST_SHIFT (30U) -/*! GPTRST - GPTRST +/*! GPTRST - General Purpose Timer Reset * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ @@ -89701,7 +83807,7 @@ typedef struct { #define USBHS_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -/*! GPTRUN - GPTRUN +/*! GPTRUN - General Purpose Timer Run * 0b0..Stop counting * 0b1..Run */ @@ -89713,7 +83819,7 @@ typedef struct { #define USBHS_SBUSCFG_AHBBRST_MASK (0x7U) #define USBHS_SBUSCFG_AHBBRST_SHIFT (0U) -/*! AHBBRST - AHBBRST +/*! AHBBRST - AHB master interface Burst configuration * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer @@ -89731,7 +83837,9 @@ typedef struct { #define USBHS_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USBHS_CAPLENGTH_CAPLENGTH_SHIFT (0U) -/*! CAPLENGTH - CAPLENGTH */ +/*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of + * the Operational Register. Default value is '40h'. + */ #define USBHS_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ @@ -89740,7 +83848,7 @@ typedef struct { #define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USBHS_HCIVERSION_HCIVERSION_SHIFT (0U) -/*! HCIVERSION - HCIVERSION */ +/*! HCIVERSION - Host Controller Interface Version Number */ #define USBHS_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK) /*! @} */ @@ -89749,40 +83857,40 @@ typedef struct { #define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU) #define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U) -/*! N_PORTS - N_PORTS */ +/*! N_PORTS - Number of Downstream Ports */ #define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK) #define USBHS_HCSPARAMS_PPC_MASK (0x10U) #define USBHS_HCSPARAMS_PPC_SHIFT (4U) -/*! PPC - PPC */ +/*! PPC - Port Power Control */ #define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK) #define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U) #define USBHS_HCSPARAMS_N_PCC_SHIFT (8U) -/*! N_PCC - N_PCC */ +/*! N_PCC - Number of Ports per Companion Controller */ #define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK) #define USBHS_HCSPARAMS_N_CC_MASK (0xF000U) #define USBHS_HCSPARAMS_N_CC_SHIFT (12U) -/*! N_CC - N_CC - * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. - * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. +/*! N_CC - Number of Companion Controller + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported */ #define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK) #define USBHS_HCSPARAMS_PI_MASK (0x10000U) #define USBHS_HCSPARAMS_PI_SHIFT (16U) -/*! PI - PI */ +/*! PI - Port Indicators (P INDICATOR) */ #define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK) #define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USBHS_HCSPARAMS_N_PTT_SHIFT (20U) -/*! N_PTT - N_PTT */ +/*! N_PTT - Number of Ports per Transaction Translator */ #define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK) #define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U) #define USBHS_HCSPARAMS_N_TT_SHIFT (24U) -/*! N_TT - N_TT */ +/*! N_TT - Number of Transaction Translators */ #define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK) /*! @} */ @@ -89791,27 +83899,27 @@ typedef struct { #define USBHS_HCCPARAMS_ADC_MASK (0x1U) #define USBHS_HCCPARAMS_ADC_SHIFT (0U) -/*! ADC - ADC */ +/*! ADC - 64-bit Addressing Capability */ #define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK) #define USBHS_HCCPARAMS_PFL_MASK (0x2U) #define USBHS_HCCPARAMS_PFL_SHIFT (1U) -/*! PFL - PFL */ +/*! PFL - Programmable Frame List Flag */ #define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK) #define USBHS_HCCPARAMS_ASP_MASK (0x4U) #define USBHS_HCCPARAMS_ASP_SHIFT (2U) -/*! ASP - ASP */ +/*! ASP - Asynchronous Schedule Park Capability */ #define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK) #define USBHS_HCCPARAMS_IST_MASK (0xF0U) #define USBHS_HCCPARAMS_IST_SHIFT (4U) -/*! IST - IST */ +/*! IST - Isochronous Scheduling Threshold */ #define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK) #define USBHS_HCCPARAMS_EECP_MASK (0xFF00U) #define USBHS_HCCPARAMS_EECP_SHIFT (8U) -/*! EECP - EECP */ +/*! EECP - EHCI Extended Capabilities Pointer */ #define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK) /*! @} */ @@ -89820,7 +83928,7 @@ typedef struct { #define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U) -/*! DCIVERSION - DCIVERSION */ +/*! DCIVERSION - Device Controller Interface Version Number */ #define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK) /*! @} */ @@ -89829,87 +83937,90 @@ typedef struct { #define USBHS_DCCPARAMS_DEN_MASK (0x1FU) #define USBHS_DCCPARAMS_DEN_SHIFT (0U) -/*! DEN - DEN */ +/*! DEN - Device Endpoint Number */ #define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK) #define USBHS_DCCPARAMS_DC_MASK (0x80U) #define USBHS_DCCPARAMS_DC_SHIFT (7U) -/*! DC - DC */ +/*! DC - Device Capable */ #define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK) #define USBHS_DCCPARAMS_HC_MASK (0x100U) #define USBHS_DCCPARAMS_HC_SHIFT (8U) -/*! HC - HC */ +/*! HC - Host Capable */ #define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK) /*! @} */ -/*! @name USBCMD - USB Command Register */ +/*! @name USBCMD - USB Command */ /*! @{ */ #define USBHS_USBCMD_RS_MASK (0x1U) #define USBHS_USBCMD_RS_SHIFT (0U) -/*! RS - RS */ +/*! RS - Run/Stop + * 0b0..Stop + * 0b1..Run + */ #define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK) #define USBHS_USBCMD_RST_MASK (0x2U) #define USBHS_USBCMD_RST_SHIFT (1U) -/*! RST - RST */ +/*! RST - Controller Reset */ #define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK) #define USBHS_USBCMD_FS_1_MASK (0xCU) #define USBHS_USBCMD_FS_1_SHIFT (2U) -/*! FS_1 - FS_1 */ +/*! FS_1 - Frame List Size */ #define USBHS_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK) #define USBHS_USBCMD_PSE_MASK (0x10U) #define USBHS_USBCMD_PSE_SHIFT (4U) -/*! PSE - PSE +/*! PSE - Periodic Schedule Enable * 0b0..Do not process the Periodic Schedule - * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule */ #define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK) #define USBHS_USBCMD_ASE_MASK (0x20U) #define USBHS_USBCMD_ASE_SHIFT (5U) -/*! ASE - ASE - * 0b0..Do not process the Asynchronous Schedule. - * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. +/*! ASE - Asynchronous Schedule Enable + * 0b0..Do not process the Asynchronous Schedule + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule */ #define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK) #define USBHS_USBCMD_IAA_MASK (0x40U) #define USBHS_USBCMD_IAA_SHIFT (6U) -/*! IAA - IAA */ +/*! IAA - Interrupt on Async Advance Doorbell */ #define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK) #define USBHS_USBCMD_ASP_MASK (0x300U) #define USBHS_USBCMD_ASP_SHIFT (8U) -/*! ASP - ASP */ +/*! ASP - Asynchronous Schedule Park Mode Count */ #define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK) #define USBHS_USBCMD_ASPE_MASK (0x800U) #define USBHS_USBCMD_ASPE_SHIFT (11U) -/*! ASPE - ASPE */ +/*! ASPE - Asynchronous Schedule Park Mode Enable */ #define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK) #define USBHS_USBCMD_SUTW_MASK (0x2000U) #define USBHS_USBCMD_SUTW_SHIFT (13U) -/*! SUTW - SUTW */ +/*! SUTW - Setup TripWire [device mode only] */ #define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK) #define USBHS_USBCMD_ATDTW_MASK (0x4000U) #define USBHS_USBCMD_ATDTW_SHIFT (14U) -/*! ATDTW - ATDTW */ +/*! ATDTW - Add dTD TripWire[device mode only] */ #define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK) #define USBHS_USBCMD_FS_2_MASK (0x8000U) #define USBHS_USBCMD_FS_2_SHIFT (15U) -/*! FS_2 - FS_2 */ +/*! FS_2 - Frame List Size [host mode only] */ #define USBHS_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK) #define USBHS_USBCMD_ITC_MASK (0xFF0000U) #define USBHS_USBCMD_ITC_SHIFT (16U) -/*! ITC - ITC +/*! ITC - Interrupt Threshold Control * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames @@ -89922,166 +84033,166 @@ typedef struct { #define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK) /*! @} */ -/*! @name USBSTS - USB Status Register */ +/*! @name USBSTS - USB Status */ /*! @{ */ #define USBHS_USBSTS_UI_MASK (0x1U) #define USBHS_USBSTS_UI_SHIFT (0U) -/*! UI - UI */ +/*! UI - USB Interrupt (USBINT) */ #define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK) #define USBHS_USBSTS_UEI_MASK (0x2U) #define USBHS_USBSTS_UEI_SHIFT (1U) -/*! UEI - UEI */ +/*! UEI - USB Error Interrupt (USBERRINT) */ #define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK) #define USBHS_USBSTS_PCI_MASK (0x4U) #define USBHS_USBSTS_PCI_SHIFT (2U) -/*! PCI - PCI */ +/*! PCI - Port Change Detect */ #define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK) #define USBHS_USBSTS_FRI_MASK (0x8U) #define USBHS_USBSTS_FRI_SHIFT (3U) -/*! FRI - FRI */ +/*! FRI - Frame List Rollover */ #define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK) #define USBHS_USBSTS_SEI_MASK (0x10U) #define USBHS_USBSTS_SEI_SHIFT (4U) -/*! SEI - SEI */ +/*! SEI - System Error */ #define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK) #define USBHS_USBSTS_AAI_MASK (0x20U) #define USBHS_USBSTS_AAI_SHIFT (5U) -/*! AAI - AAI */ +/*! AAI - Interrupt on Async Advance */ #define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK) #define USBHS_USBSTS_URI_MASK (0x40U) #define USBHS_USBSTS_URI_SHIFT (6U) -/*! URI - URI */ +/*! URI - USB Reset Received */ #define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK) #define USBHS_USBSTS_SRI_MASK (0x80U) #define USBHS_USBSTS_SRI_SHIFT (7U) -/*! SRI - SRI */ +/*! SRI - SOF Received */ #define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK) #define USBHS_USBSTS_SLI_MASK (0x100U) #define USBHS_USBSTS_SLI_SHIFT (8U) -/*! SLI - SLI */ +/*! SLI - DCSuspend */ #define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK) #define USBHS_USBSTS_ULPII_MASK (0x400U) #define USBHS_USBSTS_ULPII_SHIFT (10U) -/*! ULPII - ULPII */ +/*! ULPII - ULPI Interrupt */ #define USBHS_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK) #define USBHS_USBSTS_HCH_MASK (0x1000U) #define USBHS_USBSTS_HCH_SHIFT (12U) -/*! HCH - HCH */ +/*! HCH - HCHaIted */ #define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK) #define USBHS_USBSTS_RCL_MASK (0x2000U) #define USBHS_USBSTS_RCL_SHIFT (13U) -/*! RCL - RCL */ +/*! RCL - Reclamation */ #define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK) #define USBHS_USBSTS_PS_MASK (0x4000U) #define USBHS_USBSTS_PS_SHIFT (14U) -/*! PS - PS */ +/*! PS - Periodic Schedule Status */ #define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK) #define USBHS_USBSTS_AS_MASK (0x8000U) #define USBHS_USBSTS_AS_SHIFT (15U) -/*! AS - AS */ +/*! AS - Asynchronous Schedule Status */ #define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK) #define USBHS_USBSTS_NAKI_MASK (0x10000U) #define USBHS_USBSTS_NAKI_SHIFT (16U) -/*! NAKI - NAKI */ +/*! NAKI - NAK Interrupt Bit */ #define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK) #define USBHS_USBSTS_TI0_MASK (0x1000000U) #define USBHS_USBSTS_TI0_SHIFT (24U) -/*! TI0 - TI0 */ +/*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */ #define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK) #define USBHS_USBSTS_TI1_MASK (0x2000000U) #define USBHS_USBSTS_TI1_SHIFT (25U) -/*! TI1 - TI1 */ +/*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */ #define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK) /*! @} */ -/*! @name USBINTR - Interrupt Enable Register */ +/*! @name USBINTR - Interrupt Enable */ /*! @{ */ #define USBHS_USBINTR_UE_MASK (0x1U) #define USBHS_USBINTR_UE_SHIFT (0U) -/*! UE - UE */ +/*! UE - USB Interrupt Enable */ #define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK) #define USBHS_USBINTR_UEE_MASK (0x2U) #define USBHS_USBINTR_UEE_SHIFT (1U) -/*! UEE - UEE */ +/*! UEE - USB Error Interrupt Enable */ #define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK) #define USBHS_USBINTR_PCE_MASK (0x4U) #define USBHS_USBINTR_PCE_SHIFT (2U) -/*! PCE - PCE */ +/*! PCE - Port Change Detect Interrupt Enable */ #define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK) #define USBHS_USBINTR_FRE_MASK (0x8U) #define USBHS_USBINTR_FRE_SHIFT (3U) -/*! FRE - FRE */ +/*! FRE - Frame List Rollover Interrupt Enable */ #define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK) #define USBHS_USBINTR_SEE_MASK (0x10U) #define USBHS_USBINTR_SEE_SHIFT (4U) -/*! SEE - SEE */ +/*! SEE - System Error Interrupt Enable */ #define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK) #define USBHS_USBINTR_AAE_MASK (0x20U) #define USBHS_USBINTR_AAE_SHIFT (5U) -/*! AAE - AAE */ +/*! AAE - Async Advance Interrupt Enable */ #define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK) #define USBHS_USBINTR_URE_MASK (0x40U) #define USBHS_USBINTR_URE_SHIFT (6U) -/*! URE - URE */ +/*! URE - USB Reset Interrupt Enable */ #define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK) #define USBHS_USBINTR_SRE_MASK (0x80U) #define USBHS_USBINTR_SRE_SHIFT (7U) -/*! SRE - SRE */ +/*! SRE - SOF Received Interrupt Enable */ #define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK) #define USBHS_USBINTR_SLE_MASK (0x100U) #define USBHS_USBINTR_SLE_SHIFT (8U) -/*! SLE - SLE */ +/*! SLE - Sleep Interrupt Enable */ #define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK) #define USBHS_USBINTR_NAKE_MASK (0x10000U) #define USBHS_USBINTR_NAKE_SHIFT (16U) -/*! NAKE - NAKE */ +/*! NAKE - NAK Interrupt Enable */ #define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK) #define USBHS_USBINTR_UAIE_MASK (0x40000U) #define USBHS_USBINTR_UAIE_SHIFT (18U) -/*! UAIE - UAIE */ +/*! UAIE - USB Host Asynchronous Interrupt Enable */ #define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK) #define USBHS_USBINTR_UPIE_MASK (0x80000U) #define USBHS_USBINTR_UPIE_SHIFT (19U) -/*! UPIE - UPIE */ +/*! UPIE - USB Host Periodic Interrupt Enable */ #define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK) #define USBHS_USBINTR_TIE0_MASK (0x1000000U) #define USBHS_USBINTR_TIE0_SHIFT (24U) -/*! TIE0 - TIE0 */ +/*! TIE0 - General Purpose Timer #0 Interrupt Enable */ #define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK) #define USBHS_USBINTR_TIE1_MASK (0x2000000U) #define USBHS_USBINTR_TIE1_SHIFT (25U) -/*! TIE1 - TIE1 */ +/*! TIE1 - General Purpose Timer #1 Interrupt Enable */ #define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK) /*! @} */ @@ -90090,7 +84201,7 @@ typedef struct { #define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USBHS_FRINDEX_FRINDEX_SHIFT (0U) -/*! FRINDEX - FRINDEX +/*! FRINDEX - Frame Index * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 @@ -90108,12 +84219,12 @@ typedef struct { #define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USBHS_DEVICEADDR_USBADRA_SHIFT (24U) -/*! USBADRA - USBADRA */ +/*! USBADRA - Device Address Advance */ #define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK) #define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USBHS_DEVICEADDR_USBADR_SHIFT (25U) -/*! USBADR - USBADR */ +/*! USBADR - Device Address */ #define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK) /*! @} */ @@ -90122,7 +84233,7 @@ typedef struct { #define USBHS_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USBHS_PERIODICLISTBASE_BASEADR_SHIFT (12U) -/*! BASEADR - BASEADR */ +/*! BASEADR - Base Address (Low) */ #define USBHS_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ @@ -90131,7 +84242,7 @@ typedef struct { #define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -/*! ASYBASE - ASYBASE */ +/*! ASYBASE - Link Pointer Low (LPL) */ #define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ @@ -90140,7 +84251,7 @@ typedef struct { #define USBHS_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USBHS_ENDPTLISTADDR_EPBASE_SHIFT (11U) -/*! EPBASE - EPBASE */ +/*! EPBASE - Endpoint List Pointer (Low) */ #define USBHS_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ @@ -90149,12 +84260,12 @@ typedef struct { #define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U) -/*! RXPBURST - RXPBURST */ +/*! RXPBURST - Programmable RX Burst Size */ #define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK) -#define USBHS_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U) #define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U) -/*! TXPBURST - TXPBURST */ +/*! TXPBURST - Programmable TX Burst Size */ #define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK) /*! @} */ @@ -90163,17 +84274,17 @@ typedef struct { #define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU) #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U) -/*! TXSCHOH - TXSCHOH */ +/*! TXSCHOH - Scheduler Overhead */ #define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK) #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -/*! TXSCHHEALTH - TXSCHHEALTH */ +/*! TXSCHHEALTH - Scheduler Health Counter */ #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK) #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -/*! TXFIFOTHRES - TXFIFOTHRES */ +/*! TXFIFOTHRES - FIFO Burst Threshold */ #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ @@ -90182,12 +84293,12 @@ typedef struct { #define USBHS_ENDPTNAK_EPRN_MASK (0xFFU) #define USBHS_ENDPTNAK_EPRN_SHIFT (0U) -/*! EPRN - EPRN */ +/*! EPRN - RX Endpoint NAK */ #define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK) #define USBHS_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USBHS_ENDPTNAK_EPTN_SHIFT (16U) -/*! EPTN - EPTN */ +/*! EPTN - TX Endpoint NAK */ #define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK) /*! @} */ @@ -90196,23 +84307,23 @@ typedef struct { #define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U) -/*! EPRNE - EPRNE */ +/*! EPRNE - RX Endpoint NAK Enable */ #define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK) #define USBHS_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U) -/*! EPTNE - EPTNE */ +/*! EPTNE - TX Endpoint NAK Enable */ #define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK) /*! @} */ -/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @name CONFIGFLAG - Configure Flag */ /*! @{ */ #define USBHS_CONFIGFLAG_CF_MASK (0x1U) #define USBHS_CONFIGFLAG_CF_SHIFT (0U) -/*! CF - CF - * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. - * 0b1..Port routing control logic default-routes all ports to this host controller. +/*! CF - Configure Flag + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller + * 0b1..Port routing control logic default-routes all ports to this host controller */ #define USBHS_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK) /*! @} */ @@ -90222,60 +84333,81 @@ typedef struct { #define USBHS_PORTSC1_CCS_MASK (0x1U) #define USBHS_PORTSC1_CCS_SHIFT (0U) -/*! CCS - CCS */ +/*! CCS - Current Connect Status + * 0b0..In Host mode: No device is present. In Device mode: Not attached + * 0b1..In Host mode: Device is present on port. In Device mode: Attached + */ #define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK) #define USBHS_PORTSC1_CSC_MASK (0x2U) #define USBHS_PORTSC1_CSC_SHIFT (1U) -/*! CSC - CSC */ +/*! CSC - Connect Status Change + * 0b0..No change + * 0b1..Change in current connect status + */ #define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK) #define USBHS_PORTSC1_PE_MASK (0x4U) #define USBHS_PORTSC1_PE_SHIFT (2U) -/*! PE - PE */ +/*! PE - Port Enabled/Disabled + * 0b0..Disable + * 0b1..Enable + */ #define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK) #define USBHS_PORTSC1_PEC_MASK (0x8U) #define USBHS_PORTSC1_PEC_SHIFT (3U) -/*! PEC - PEC */ +/*! PEC - Port Enable/Disable Change + * 0b0..No change + * 0b1..Port enabled/disabled status has changed + */ #define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK) #define USBHS_PORTSC1_OCA_MASK (0x10U) #define USBHS_PORTSC1_OCA_SHIFT (4U) -/*! OCA - OCA +/*! OCA - Over-Current Active * 0b1..This port currently has an over-current condition - * 0b0..This port does not have an over-current condition. + * 0b0..This port does not have an over-current condition */ #define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK) #define USBHS_PORTSC1_OCC_MASK (0x20U) #define USBHS_PORTSC1_OCC_SHIFT (5U) -/*! OCC - OCC */ +/*! OCC - Over-current Change */ #define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK) #define USBHS_PORTSC1_FPR_MASK (0x40U) #define USBHS_PORTSC1_FPR_SHIFT (6U) -/*! FPR - FPR */ +/*! FPR - Force Port Resume + * 0b0..No resume (K-state) detected/driven on port + * 0b1..Resume detected/driven on port + */ #define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK) #define USBHS_PORTSC1_SUSP_MASK (0x80U) #define USBHS_PORTSC1_SUSP_SHIFT (7U) -/*! SUSP - SUSP */ +/*! SUSP - Suspend + * 0b0..Port not in suspend state + * 0b1..Port in suspend state + */ #define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK) #define USBHS_PORTSC1_PR_MASK (0x100U) #define USBHS_PORTSC1_PR_SHIFT (8U) -/*! PR - PR */ +/*! PR - Port Reset + * 0b0..Port is not in reset + * 0b1..Port is in reset + */ #define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK) #define USBHS_PORTSC1_HSP_MASK (0x200U) #define USBHS_PORTSC1_HSP_SHIFT (9U) -/*! HSP - HSP */ +/*! HSP - High-Speed Port */ #define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK) #define USBHS_PORTSC1_LS_MASK (0xC00U) #define USBHS_PORTSC1_LS_SHIFT (10U) -/*! LS - LS +/*! LS - Line Status * 0b00..SE0 * 0b10..J-state * 0b01..K-state @@ -90285,17 +84417,17 @@ typedef struct { #define USBHS_PORTSC1_PP_MASK (0x1000U) #define USBHS_PORTSC1_PP_SHIFT (12U) -/*! PP - PP */ +/*! PP - Port Power */ #define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK) #define USBHS_PORTSC1_PO_MASK (0x2000U) #define USBHS_PORTSC1_PO_SHIFT (13U) -/*! PO - PO */ +/*! PO - Port Owner */ #define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK) #define USBHS_PORTSC1_PIC_MASK (0xC000U) #define USBHS_PORTSC1_PIC_SHIFT (14U) -/*! PIC - PIC +/*! PIC - Port Indicator Control * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green @@ -90305,7 +84437,7 @@ typedef struct { #define USBHS_PORTSC1_PTC_MASK (0xF0000U) #define USBHS_PORTSC1_PTC_SHIFT (16U) -/*! PTC - PTC +/*! PTC - Port Test Control * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE @@ -90320,22 +84452,22 @@ typedef struct { #define USBHS_PORTSC1_WKCN_MASK (0x100000U) #define USBHS_PORTSC1_WKCN_SHIFT (20U) -/*! WKCN - WKCN */ +/*! WKCN - Wake on Connect Enable (WKCNNT_E) */ #define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK) #define USBHS_PORTSC1_WKDC_MASK (0x200000U) #define USBHS_PORTSC1_WKDC_SHIFT (21U) -/*! WKDC - WKDC */ +/*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */ #define USBHS_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK) #define USBHS_PORTSC1_WKOC_MASK (0x400000U) #define USBHS_PORTSC1_WKOC_SHIFT (22U) -/*! WKOC - WKOC */ +/*! WKOC - Wake on Over-current Enable (WKOC_E) */ #define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK) #define USBHS_PORTSC1_PHCD_MASK (0x800000U) #define USBHS_PORTSC1_PHCD_SHIFT (23U) -/*! PHCD - PHCD +/*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD) * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ @@ -90343,7 +84475,7 @@ typedef struct { #define USBHS_PORTSC1_PFSC_MASK (0x1000000U) #define USBHS_PORTSC1_PFSC_SHIFT (24U) -/*! PFSC - PFSC +/*! PFSC - Port Force Full Speed Connect * 0b1..Forced to full speed * 0b0..Normal operation */ @@ -90351,12 +84483,12 @@ typedef struct { #define USBHS_PORTSC1_PTS_2_MASK (0x2000000U) #define USBHS_PORTSC1_PTS_2_SHIFT (25U) -/*! PTS_2 - PTS_2 */ +/*! PTS_2 - Parallel Transceiver Select */ #define USBHS_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK) #define USBHS_PORTSC1_PSPD_MASK (0xC000000U) #define USBHS_PORTSC1_PSPD_SHIFT (26U) -/*! PSPD - PSPD +/*! PSPD - Port Speed * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed @@ -90366,154 +84498,163 @@ typedef struct { #define USBHS_PORTSC1_PTW_MASK (0x10000000U) #define USBHS_PORTSC1_PTW_SHIFT (28U) -/*! PTW - PTW - * 0b0..Select the 8-bit UTMI interface [60MHz] - * 0b1..Select the 16-bit UTMI interface [30MHz] +/*! PTW - Parallel Transceiver Width - Read/Write + * 0b0..Select the 8-bit UTMI interface [60 MHz] + * 0b1..Select the 16-bit UTMI interface [30 MHz] */ #define USBHS_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK) #define USBHS_PORTSC1_STS_MASK (0x20000000U) #define USBHS_PORTSC1_STS_SHIFT (29U) -/*! STS - STS */ +/*! STS - Serial Transceiver Select + * 0b0..Parallel Interface signals is selected + * 0b1..Serial Interface Engine is selected + */ #define USBHS_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK) #define USBHS_PORTSC1_PTS_1_MASK (0xC0000000U) #define USBHS_PORTSC1_PTS_1_SHIFT (30U) -/*! PTS_1 - PTS_1 */ +/*! PTS_1 - Parallel Transceiver Select */ #define USBHS_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK) /*! @} */ -/*! @name OTGSC - On-The-Go Status & control */ +/*! @name OTGSC - On-The-Go Status & Control */ /*! @{ */ #define USBHS_OTGSC_VD_MASK (0x1U) #define USBHS_OTGSC_VD_SHIFT (0U) -/*! VD - VD */ +/*! VD - VBUS Discharge */ #define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK) #define USBHS_OTGSC_VC_MASK (0x2U) #define USBHS_OTGSC_VC_SHIFT (1U) -/*! VC - VC */ +/*! VC - VBUS Charge */ #define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK) #define USBHS_OTGSC_OT_MASK (0x8U) #define USBHS_OTGSC_OT_SHIFT (3U) -/*! OT - OT */ +/*! OT - OTG Termination */ #define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK) #define USBHS_OTGSC_DP_MASK (0x10U) #define USBHS_OTGSC_DP_SHIFT (4U) -/*! DP - DP */ +/*! DP - Data Pulsing */ #define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK) #define USBHS_OTGSC_IDPU_MASK (0x20U) #define USBHS_OTGSC_IDPU_SHIFT (5U) -/*! IDPU - IDPU */ +/*! IDPU - ID Pullup + * 0b0..Off + * 0b1..On + */ #define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK) #define USBHS_OTGSC_ID_MASK (0x100U) #define USBHS_OTGSC_ID_SHIFT (8U) -/*! ID - ID */ +/*! ID - USB ID + * 0b0..A device + * 0b1..B device + */ #define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK) #define USBHS_OTGSC_AVV_MASK (0x200U) #define USBHS_OTGSC_AVV_SHIFT (9U) -/*! AVV - AVV */ +/*! AVV - A VBus Valid */ #define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK) #define USBHS_OTGSC_ASV_MASK (0x400U) #define USBHS_OTGSC_ASV_SHIFT (10U) -/*! ASV - ASV */ +/*! ASV - A Session Valid */ #define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK) #define USBHS_OTGSC_BSV_MASK (0x800U) #define USBHS_OTGSC_BSV_SHIFT (11U) -/*! BSV - BSV */ +/*! BSV - B Session Valid */ #define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK) #define USBHS_OTGSC_BSE_MASK (0x1000U) #define USBHS_OTGSC_BSE_SHIFT (12U) -/*! BSE - BSE */ +/*! BSE - B Session End */ #define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK) #define USBHS_OTGSC_TOG_1MS_MASK (0x2000U) #define USBHS_OTGSC_TOG_1MS_SHIFT (13U) -/*! TOG_1MS - TOG_1MS */ +/*! TOG_1MS - 1 Millisecond Timer Toggle */ #define USBHS_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK) #define USBHS_OTGSC_DPS_MASK (0x4000U) #define USBHS_OTGSC_DPS_SHIFT (14U) -/*! DPS - DPS */ +/*! DPS - Data Bus Pulsing Status */ #define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK) #define USBHS_OTGSC_IDIS_MASK (0x10000U) #define USBHS_OTGSC_IDIS_SHIFT (16U) -/*! IDIS - IDIS */ +/*! IDIS - USB ID Interrupt Status */ #define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK) #define USBHS_OTGSC_AVVIS_MASK (0x20000U) #define USBHS_OTGSC_AVVIS_SHIFT (17U) -/*! AVVIS - AVVIS */ +/*! AVVIS - A VBus Valid Interrupt Status */ #define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK) #define USBHS_OTGSC_ASVIS_MASK (0x40000U) #define USBHS_OTGSC_ASVIS_SHIFT (18U) -/*! ASVIS - ASVIS */ +/*! ASVIS - A Session Valid Interrupt Status */ #define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK) #define USBHS_OTGSC_BSVIS_MASK (0x80000U) #define USBHS_OTGSC_BSVIS_SHIFT (19U) -/*! BSVIS - BSVIS */ +/*! BSVIS - B Session Valid Interrupt Status */ #define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK) #define USBHS_OTGSC_BSEIS_MASK (0x100000U) #define USBHS_OTGSC_BSEIS_SHIFT (20U) -/*! BSEIS - BSEIS */ +/*! BSEIS - B Session End Interrupt Status */ #define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK) #define USBHS_OTGSC_STATUS_1MS_MASK (0x200000U) #define USBHS_OTGSC_STATUS_1MS_SHIFT (21U) -/*! STATUS_1MS - STATUS_1MS */ +/*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */ #define USBHS_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK) #define USBHS_OTGSC_DPIS_MASK (0x400000U) #define USBHS_OTGSC_DPIS_SHIFT (22U) -/*! DPIS - DPIS */ +/*! DPIS - Data Pulse Interrupt Status */ #define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK) #define USBHS_OTGSC_IDIE_MASK (0x1000000U) #define USBHS_OTGSC_IDIE_SHIFT (24U) -/*! IDIE - IDIE */ +/*! IDIE - USB ID Interrupt Enable */ #define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK) #define USBHS_OTGSC_AVVIE_MASK (0x2000000U) #define USBHS_OTGSC_AVVIE_SHIFT (25U) -/*! AVVIE - AVVIE */ +/*! AVVIE - A VBus Valid Interrupt Enable */ #define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK) #define USBHS_OTGSC_ASVIE_MASK (0x4000000U) #define USBHS_OTGSC_ASVIE_SHIFT (26U) -/*! ASVIE - ASVIE */ +/*! ASVIE - A Session Valid Interrupt Enable */ #define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK) #define USBHS_OTGSC_BSVIE_MASK (0x8000000U) #define USBHS_OTGSC_BSVIE_SHIFT (27U) -/*! BSVIE - BSVIE */ +/*! BSVIE - B Session Valid Interrupt Enable */ #define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK) #define USBHS_OTGSC_BSEIE_MASK (0x10000000U) #define USBHS_OTGSC_BSEIE_SHIFT (28U) -/*! BSEIE - BSEIE */ +/*! BSEIE - B Session End Interrupt Enable */ #define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK) #define USBHS_OTGSC_EN_1MS_MASK (0x20000000U) #define USBHS_OTGSC_EN_1MS_SHIFT (29U) -/*! EN_1MS - EN_1MS */ +/*! EN_1MS - 1 Millisecond Timer Interrupt Enable */ #define USBHS_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK) #define USBHS_OTGSC_DPIE_MASK (0x40000000U) #define USBHS_OTGSC_DPIE_SHIFT (30U) -/*! DPIE - DPIE */ +/*! DPIE - Data Pulse Interrupt Enable */ #define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK) /*! @} */ @@ -90522,7 +84663,7 @@ typedef struct { #define USBHS_USBMODE_CM_MASK (0x3U) #define USBHS_USBMODE_CM_SHIFT (0U) -/*! CM - CM +/*! CM - Controller Mode * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] @@ -90532,15 +84673,15 @@ typedef struct { #define USBHS_USBMODE_ES_MASK (0x4U) #define USBHS_USBMODE_ES_SHIFT (2U) -/*! ES - ES - * 0b0..Little Endian [Default] +/*! ES - Endian Select + * 0b0..Little Endian * 0b1..Big Endian */ #define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK) #define USBHS_USBMODE_SLOM_MASK (0x8U) #define USBHS_USBMODE_SLOM_SHIFT (3U) -/*! SLOM - SLOM +/*! SLOM - Setup Lockout Mode * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off */ @@ -90548,7 +84689,10 @@ typedef struct { #define USBHS_USBMODE_SDIS_MASK (0x10U) #define USBHS_USBMODE_SDIS_SHIFT (4U) -/*! SDIS - SDIS */ +/*! SDIS - Stream Disable Mode + * 0b0..Inactive + * 0b1..Active + */ #define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK) /*! @} */ @@ -90557,7 +84701,7 @@ typedef struct { #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */ +/*! ENDPTSETUPSTAT - Setup Endpoint Status */ #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ @@ -90566,12 +84710,12 @@ typedef struct { #define USBHS_ENDPTPRIME_PERB_MASK (0xFFU) #define USBHS_ENDPTPRIME_PERB_SHIFT (0U) -/*! PERB - PERB */ +/*! PERB - Prime Endpoint Receive Buffer */ #define USBHS_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK) #define USBHS_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USBHS_ENDPTPRIME_PETB_SHIFT (16U) -/*! PETB - PETB */ +/*! PETB - Prime Endpoint Transmit Buffer */ #define USBHS_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK) /*! @} */ @@ -90580,12 +84724,12 @@ typedef struct { #define USBHS_ENDPTFLUSH_FERB_MASK (0xFFU) #define USBHS_ENDPTFLUSH_FERB_SHIFT (0U) -/*! FERB - FERB */ +/*! FERB - Flush Endpoint Receive Buffer */ #define USBHS_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK) #define USBHS_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USBHS_ENDPTFLUSH_FETB_SHIFT (16U) -/*! FETB - FETB */ +/*! FETB - Flush Endpoint Transmit Buffer */ #define USBHS_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK) /*! @} */ @@ -90594,12 +84738,12 @@ typedef struct { #define USBHS_ENDPTSTAT_ERBR_MASK (0xFFU) #define USBHS_ENDPTSTAT_ERBR_SHIFT (0U) -/*! ERBR - ERBR */ +/*! ERBR - Endpoint Receive Buffer Ready */ #define USBHS_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK) #define USBHS_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USBHS_ENDPTSTAT_ETBR_SHIFT (16U) -/*! ETBR - ETBR */ +/*! ETBR - Endpoint Transmit Buffer Ready */ #define USBHS_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK) /*! @} */ @@ -90608,46 +84752,62 @@ typedef struct { #define USBHS_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USBHS_ENDPTCOMPLETE_ERCE_SHIFT (0U) -/*! ERCE - ERCE */ +/*! ERCE - Endpoint Receive Complete Event */ #define USBHS_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK) #define USBHS_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USBHS_ENDPTCOMPLETE_ETCE_SHIFT (16U) -/*! ETCE - ETCE */ +/*! ETCE - Endpoint Transmit Complete Event */ #define USBHS_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ -/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @name ENDPTCTRL0 - Endpoint Control 0 */ /*! @{ */ #define USBHS_ENDPTCTRL0_RXS_MASK (0x1U) #define USBHS_ENDPTCTRL0_RXS_SHIFT (0U) -/*! RXS - RXS */ +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK) #define USBHS_ENDPTCTRL0_RXT_MASK (0xCU) #define USBHS_ENDPTCTRL0_RXT_SHIFT (2U) -/*! RXT - RXT */ +/*! RXT - RX Endpoint Type + * 0b00..Control + */ #define USBHS_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK) #define USBHS_ENDPTCTRL0_RXE_MASK (0x80U) #define USBHS_ENDPTCTRL0_RXE_SHIFT (7U) -/*! RXE - RXE */ +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK) #define USBHS_ENDPTCTRL0_TXS_MASK (0x10000U) #define USBHS_ENDPTCTRL0_TXS_SHIFT (16U) -/*! TXS - TXS */ +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK) #define USBHS_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USBHS_ENDPTCTRL0_TXT_SHIFT (18U) -/*! TXT - TXT */ +/*! TXT - TX Endpoint Type + * 0b00..Control + */ #define USBHS_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK) #define USBHS_ENDPTCTRL0_TXE_MASK (0x800000U) #define USBHS_ENDPTCTRL0_TXE_SHIFT (23U) -/*! TXE - TXE */ +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK) /*! @} */ @@ -90656,62 +84816,98 @@ typedef struct { #define USBHS_ENDPTCTRL_RXS_MASK (0x1U) #define USBHS_ENDPTCTRL_RXS_SHIFT (0U) -/*! RXS - RXS */ +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK) #define USBHS_ENDPTCTRL_RXD_MASK (0x2U) #define USBHS_ENDPTCTRL_RXD_SHIFT (1U) -/*! RXD - RXD */ +/*! RXD - RX Endpoint Data Sink + * 0b0..Dual Port Memory Buffer/DMA Engine + */ #define USBHS_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK) #define USBHS_ENDPTCTRL_RXT_MASK (0xCU) #define USBHS_ENDPTCTRL_RXT_SHIFT (2U) -/*! RXT - RXT */ +/*! RXT - RX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ #define USBHS_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK) #define USBHS_ENDPTCTRL_RXI_MASK (0x20U) #define USBHS_ENDPTCTRL_RXI_SHIFT (5U) -/*! RXI - RXI */ +/*! RXI - RX Data Toggle Inhibit + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK) #define USBHS_ENDPTCTRL_RXR_MASK (0x40U) #define USBHS_ENDPTCTRL_RXR_SHIFT (6U) -/*! RXR - RXR */ +/*! RXR - RX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ #define USBHS_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK) #define USBHS_ENDPTCTRL_RXE_MASK (0x80U) #define USBHS_ENDPTCTRL_RXE_SHIFT (7U) -/*! RXE - RXE */ +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK) #define USBHS_ENDPTCTRL_TXS_MASK (0x10000U) #define USBHS_ENDPTCTRL_TXS_SHIFT (16U) -/*! TXS - TXS */ +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK) #define USBHS_ENDPTCTRL_TXD_MASK (0x20000U) #define USBHS_ENDPTCTRL_TXD_SHIFT (17U) -/*! TXD - TXD */ +/*! TXD - TX Endpoint Data Source + * 0b0..Dual Port Memory Buffer/DMA Engine + */ #define USBHS_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK) #define USBHS_ENDPTCTRL_TXT_MASK (0xC0000U) #define USBHS_ENDPTCTRL_TXT_SHIFT (18U) -/*! TXT - TXT */ +/*! TXT - TX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ #define USBHS_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK) #define USBHS_ENDPTCTRL_TXI_MASK (0x200000U) #define USBHS_ENDPTCTRL_TXI_SHIFT (21U) -/*! TXI - TXI */ +/*! TXI - TX Data Toggle Inhibit + * 0b0..PID sequencing enabled + * 0b1..PID sequencing disabled + */ #define USBHS_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK) #define USBHS_ENDPTCTRL_TXR_MASK (0x400000U) #define USBHS_ENDPTCTRL_TXR_SHIFT (22U) -/*! TXR - TXR */ +/*! TXR - TX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ #define USBHS_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK) #define USBHS_ENDPTCTRL_TXE_MASK (0x800000U) #define USBHS_ENDPTCTRL_TXE_SHIFT (23U) -/*! TXE - TXE */ +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK) /*! @} */ @@ -91187,10 +85383,10 @@ typedef struct { /** USBNC - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL1; /**< USB OTG Control 1 Register, offset: 0x0 */ - __IO uint32_t CTRL2; /**< USB OTG Control 2 Register, offset: 0x4 */ + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ uint8_t RESERVED_0[8]; - __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control Register, offset: 0x10 */ + __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control, offset: 0x10 */ } USBNC_Type; /* ---------------------------------------------------------------------------- @@ -91202,20 +85398,20 @@ typedef struct { * @{ */ -/*! @name CTRL1 - USB OTG Control 1 Register */ +/*! @name CTRL1 - USB OTG Control 1 */ /*! @{ */ #define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) -/*! OVER_CUR_DIS - OVER_CUR_DIS - * 0b1..Disables overcurrent detection - * 0b0..Enables overcurrent detection +/*! OVER_CUR_DIS - Disable Overcurrent Detection + * 0b1..Disables + * 0b0..Enables */ #define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) -/*! OVER_CUR_POL - OVER_CUR_POL +/*! OVER_CUR_POL - Polarity of Overcurrent * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ @@ -91223,7 +85419,7 @@ typedef struct { #define USBNC_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_CTRL1_PWR_POL_SHIFT (9U) -/*! PWR_POL - PWR_POL +/*! PWR_POL - Power Polarity * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ @@ -91231,7 +85427,7 @@ typedef struct { #define USBNC_CTRL1_WIE_MASK (0x400U) #define USBNC_CTRL1_WIE_SHIFT (10U) -/*! WIE - WIE +/*! WIE - Wake-up Interrupt Enable * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ @@ -91239,15 +85435,15 @@ typedef struct { #define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) -/*! WKUP_SW_EN - WKUP_SW_EN - * 0b1..Enable - * 0b0..Disable +/*! WKUP_SW_EN - Software Wake-up Enable + * 0b1..Enables + * 0b0..Disables */ #define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) #define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_CTRL1_WKUP_SW_SHIFT (15U) -/*! WKUP_SW - WKUP_SW +/*! WKUP_SW - Software Wake-up * 0b1..Force wake-up * 0b0..Inactive */ @@ -91255,43 +85451,43 @@ typedef struct { #define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) -/*! WKUP_ID_EN - WKUP_ID_EN - * 0b1..Enable - * 0b0..Disable +/*! WKUP_ID_EN - Wake-up on ID Change Enable + * 0b1..Enables + * 0b0..Disables */ #define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) #define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) -/*! WKUP_VBUS_EN - WKUP_VBUS_EN - * 0b1..Enable - * 0b0..Disable +/*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable + * 0b1..Enables + * 0b0..Disables */ #define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) -/*! WKUP_DPDM_EN - Wake-up on DPDM change enable - * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. - * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. +/*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable + * 0b1..DPDM changes wake-up to be enabled, it is for device only + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0 */ #define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_CTRL1_WIR_MASK (0x80000000U) #define USBNC_CTRL1_WIR_SHIFT (31U) -/*! WIR - WIR - * 0b1..Wake-up Interrupt Request received - * 0b0..No wake-up interrupt request received +/*! WIR - Wake-up Interrupt Request + * 0b1..Request received + * 0b0..No request received */ #define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) /*! @} */ -/*! @name CTRL2 - USB OTG Control 2 Register */ +/*! @name CTRL2 - USB OTG Control 2 */ /*! @{ */ #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) -/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL +/*! VBUS_SOURCE_SEL - VBUS Source Select * 0b00..vbus_valid * 0b01..sess_valid * 0b10..sess_valid @@ -91308,25 +85504,25 @@ typedef struct { #define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) -/*! LOWSPEED_EN - LOWSPEED_EN +/*! LOWSPEED_EN - Low Speed Enable * 0b0..Default */ #define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) #define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) -/*! UTMI_CLK_VLD - UTMI_CLK_VLD +/*! UTMI_CLK_VLD - UTMI Clock Valid * 0b0..Default */ #define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ -/*! @name HSIC_CTRL - USB Host HSIC Control Register */ +/*! @name HSIC_CTRL - USB Host HSIC Control */ /*! @{ */ #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) -/*! HSIC_CLK_ON - HSIC_CLK_ON +/*! HSIC_CLK_ON - HSIC Clock ON * 0b1..Active * 0b0..Inactive */ @@ -91334,7 +85530,7 @@ typedef struct { #define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) -/*! HSIC_EN - HSIC_EN +/*! HSIC_EN - Host HSIC Enable * 0b1..Enabled * 0b0..Disabled */ @@ -91342,7 +85538,7 @@ typedef struct { #define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) -/*! CLK_VLD - CLK_VLD +/*! CLK_VLD - Clock Valid * 0b1..Valid * 0b0..Invalid */ @@ -91433,69 +85629,69 @@ typedef struct { /** USBPHY - Register Layout Typedef */ typedef struct { - __IO uint32_t PWD; /**< Power Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< Power Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< Power Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< Power Down Register, offset: 0xC */ - __IO uint32_t TX; /**< Tx Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< Tx Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< Tx Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< Tx Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< Rx Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< Rx Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< Rx Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< Rx Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< General Purpose Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< General Purpose Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< General Purpose Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< General Purpose Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< Status Register, offset: 0x40 */ + __IO uint32_t PWD; /**< Power Down, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< Power Down, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< Power Down, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< Power Down, offset: 0xC */ + __IO uint32_t TX; /**< TX Control, offset: 0x10 */ + __IO uint32_t TX_SET; /**< TX Control, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< TX Control, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< TX Control, offset: 0x1C */ + __IO uint32_t RX; /**< RX Control, offset: 0x20 */ + __IO uint32_t RX_SET; /**< RX Control, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< RX Control, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< RX Control, offset: 0x2C */ + __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< General Purpose Control, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< General Purpose Control, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< General Purpose Control, offset: 0x3C */ + __IO uint32_t STATUS; /**< Status, offset: 0x40 */ uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< Debug Register 0, offset: 0x5C */ + __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< Debug 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< Debug 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< Debug 0, offset: 0x5C */ uint8_t RESERVED_1[32]; - __I uint32_t VERSION; /**< Version Register, offset: 0x80 */ + __I uint32_t VERSION; /**< Version, offset: 0x80 */ uint8_t RESERVED_2[12]; - __IO uint32_t IP; /**< IP Block Register, offset: 0x90 */ - __IO uint32_t IP_SET; /**< IP Block Register, offset: 0x94 */ - __IO uint32_t IP_CLR; /**< IP Block Register, offset: 0x98 */ - __IO uint32_t IP_TOG; /**< IP Block Register, offset: 0x9C */ - __IO uint32_t PLL_SIC; /**< PLL SIC Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< PLL SIC Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< PLL SIC Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< PLL SIC Register, offset: 0xAC */ + __IO uint32_t IP; /**< IP Block, offset: 0x90 */ + __IO uint32_t IP_SET; /**< IP Block, offset: 0x94 */ + __IO uint32_t IP_CLR; /**< IP Block, offset: 0x98 */ + __IO uint32_t IP_TOG; /**< IP Block, offset: 0x9C */ + __IO uint32_t PLL_SIC; /**< PLL SIC, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< PLL SIC, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< PLL SIC, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< PLL SIC, offset: 0xAC */ uint8_t RESERVED_3[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status Register, offset: 0xD0 */ - __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status Register, offset: 0xD4 */ - __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status Register, offset: 0xD8 */ - __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status Register, offset: 0xDC */ - __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect Register, offset: 0xE0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect Register, offset: 0xE4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect Register, offset: 0xE8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect Register, offset: 0xEC */ - __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status Register, offset: 0xF0 */ - __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status Register, offset: 0xF4 */ - __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status Register, offset: 0xF8 */ - __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status Register, offset: 0xFC */ - __IO uint32_t ANACTRL; /**< Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< Analog Control Register, offset: 0x10C */ + __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */ + __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status, offset: 0xD4 */ + __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status, offset: 0xD8 */ + __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status, offset: 0xDC */ + __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status, offset: 0xF0 */ + __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status, offset: 0xF4 */ + __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status, offset: 0xF8 */ + __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status, offset: 0xFC */ + __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< Analog Control, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< Analog Control, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< Analog Control, offset: 0x10C */ uint8_t RESERVED_4[32]; - __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim Register, offset: 0x130 */ - __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim Register, offset: 0x134 */ - __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim Register, offset: 0x138 */ - __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim Register, offset: 0x13C */ - __IO uint32_t PFDA; /**< PFD Register A, offset: 0x140 */ - __IO uint32_t PFDA_SET; /**< PFD Register A, offset: 0x144 */ - __IO uint32_t PFDA_CLR; /**< PFD Register A, offset: 0x148 */ - __IO uint32_t PFDA_TOG; /**< PFD Register A, offset: 0x14C */ + __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim, offset: 0x130 */ + __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim, offset: 0x134 */ + __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim, offset: 0x138 */ + __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim, offset: 0x13C */ + __IO uint32_t PFDA; /**< PFD A, offset: 0x140 */ + __IO uint32_t PFDA_SET; /**< PFD A, offset: 0x144 */ + __IO uint32_t PFDA_CLR; /**< PFD A, offset: 0x148 */ + __IO uint32_t PFDA_TOG; /**< PFD A, offset: 0x14C */ } USBPHY_Type; /* ---------------------------------------------------------------------------- @@ -91507,576 +85703,637 @@ typedef struct { * @{ */ -/*! @name PWD - Power Down Register */ +/*! @name PWD - Power Down */ /*! @{ */ #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers - * 0b0..Provide bias to allow enable of FS Tx drivers - * 0b1..Power down FS Tx drivers and configure them to high impedance state +/*! TXPWDFS - Power Down USB FS TX Drivers + * 0b0..Provide bias to enable + * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block - * 0b0..Enable current mirror circuits for general transceiver/detector bias - * 0b1..Power down current bias mirrors +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror - * 0b0..Enable Tx V-to-I converter and current mirrors - * 0b1..Power down Tx V-to-I converter and current mirrors +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator - * 0b0..Enable the HS Rx envelope detector and Host Disconnect comparator - * 0b1..Power down the HS Rx envelope detector and Host Disconnect comparator +/*! RXPWDENV - Power Down USB HS RX Envelope Detector + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver - * 0b0..Enable the FS differential receiver - * 0b1..Power down the FS differential receiver +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver - * 0b0..Enable the HS differential receiver - * 0b1..Power down the HS differential receiver +/*! RXPWDDIFF - Power Down USB HS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator - * 0b0..Enable the PHY's receiver block except for the FS differential receiver - * 0b1..Power down the PHY's receiver block except for the FS differential receiver +/*! RXPWDRX - Power Down USBPHY Receiver Circuits + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) /*! @} */ -/*! @name PWD_SET - Power Down Register */ +/*! @name PWD_SET - Power Down */ /*! @{ */ #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers */ +/*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block */ +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror */ +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator */ +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver */ +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver */ +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator */ +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) /*! @} */ -/*! @name PWD_CLR - Power Down Register */ +/*! @name PWD_CLR - Power Down */ /*! @{ */ #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers */ +/*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block */ +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror */ +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator */ +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver */ +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver */ +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator */ +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) /*! @} */ -/*! @name PWD_TOG - Power Down Register */ +/*! @name PWD_TOG - Power Down */ /*! @{ */ #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers */ +/*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block */ +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror */ +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator */ +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver */ +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver */ +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator */ +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) /*! @} */ -/*! @name TX - Tx Control Register */ +/*! @name TX - TX Control */ /*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) #define USBPHY_TX_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) /*! @} */ -/*! @name TX_SET - Tx Control Register */ +/*! @name TX_SET - TX Control */ /*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) #define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) /*! @} */ -/*! @name TX_CLR - Tx Control Register */ +/*! @name TX_CLR - TX Control */ /*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) #define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) /*! @} */ -/*! @name TX_TOG - Tx Control Register */ +/*! @name TX_TOG - TX Control */ /*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) #define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) /*! @} */ -/*! @name RX - Rx Control Register */ +/*! @name RX - RX Control */ /*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V +/*! ENVADJ - Envelope Detector Trip Point + * 0b000..0.1000 V + * 0b001..0.1125 V + * 0b010..0.1250 V + * 0b011..0.0875 V * 0b1xx.. */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V +/*! DISCONADJ - Disconnect Detector Trip Point + * 0b000..0.56875 V + * 0b001..0.55000 V + * 0b010..0.58125 V + * 0b011..0.60000 V * 0b1xx.. */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) /*! @} */ -/*! @name RX_SET - Rx Control Register */ +/*! @name RX_SET - RX Control */ /*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point */ +/*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point */ +/*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) /*! @} */ -/*! @name RX_CLR - Rx Control Register */ +/*! @name RX_CLR - RX Control */ /*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point */ +/*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point */ +/*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) /*! @} */ -/*! @name RX_TOG - Rx Control Register */ +/*! @name RX_TOG - RX Control */ /*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point */ +/*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point */ +/*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) /*! @} */ -/*! @name CTRL - General Purpose Control Register */ +/*! @name CTRL - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt + * 0b0..Connected + * 0b1..Disconnected + */ #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection - * 0b0..Disables 200 kohm pullup resistors on USB_DP and USB_DM pins - * 0b1..Enables 200 kohm pullup resistors on USB_DP and USB_DM pins +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity + * 0b0..Plugged in + * 0b1..Unplugged + */ #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt + * 0b0..No ID change interrupt + * 0b1..ID change interrupt + */ #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector - * 0b0..Disable the PHY's internal ID pin detection circuit - * 0b1..Enable the PHY's internal ID pin detection circuit +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky + * 0b0..During the resume or reset state signaling period + * 0b1..Until you write 0 to it + */ #define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt + * 0b0..No resume interrupt + * 0b1..Resume interrupt + */ #define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value - * 0b0..False, when ID resistance to ground is less than Ra_Plug_ID, indicating Host (A) side - * 0b1..True, when ID resistance is greater than Rb_Plug_ID, indicating Device (B) side +/*! OTG_ID_VALUE - OTG ID Value + * 0b0..Host + * 0b1..Device */ #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -/*! UTMI_SUSPENDM - UTMI Suspend */ +/*! UTMI_SUSPENDM - UTMI Suspend + * 0b0..Not suspended + * 0b1..Suspended + */ #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate + * 0b0..Run clocks + * 0b1..Gate clocks + */ #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset + * 0b0..Release from reset + * 0b1..Soft-reset + */ #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) /*! @} */ -/*! @name CTRL_SET - General Purpose Control Register */ +/*! @name CTRL_SET - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */ +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector */ +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value */ +/*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) @@ -92086,126 +86343,126 @@ typedef struct { #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset */ #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) /*! @} */ -/*! @name CTRL_CLR - General Purpose Control Register */ +/*! @name CTRL_CLR - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */ +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector */ +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value */ +/*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) @@ -92215,126 +86472,126 @@ typedef struct { #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset */ #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) /*! @} */ -/*! @name CTRL_TOG - General Purpose Control Register */ +/*! @name CTRL_TOG - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */ +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector */ +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value */ +/*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) @@ -92344,57 +86601,57 @@ typedef struct { #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset */ #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) /*! @} */ -/*! @name STATUS - Status Register */ +/*! @name STATUS - Status */ /*! @{ */ #define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) #define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) -/*! OK_STATUS_3V - USB 3.3 V / 1.8 V supply status - * 0b0..One or both of the 1.8 V and 3.3 V supplies to the PHY are not powered - * 0b1..Both of the 1.8 V and 3.3 V supplies to the PHY are powered +/*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status + * 0b0..Not powered + * 0b1..Powered */ #define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - Host disconnect status - * 0b0..USB cable disconnect has not been detected at the local Host - * 0b1..USB cable disconnect has been detected at the local Host +/*! HOSTDISCONDETECT_STATUS - Host Disconnect Status + * 0b0..Not detected + * 0b1..Detected */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection. - * 0b0..No attachment to a USB Host is detected - * 0b1..Cable attachment to a USB Host is detected +/*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection + * 0b0..No attachment detected + * 0b1..Cable attachment detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -/*! OTGID_STATUS - OTG ID status - * 0b0..False, when ID resistance to ground is less than Ra_Plug_ID, indicating Host (A) side - * 0b1..True, when ID resistance is greater than Rb_Plug_ID, indicating Device (B) side +/*! OTGID_STATUS - OTG ID Status + * 0b0..Host + * 0b1..Device */ #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -/*! RESUME_STATUS - Resume status */ +/*! RESUME_STATUS - Resume Status */ #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ -/*! @name DEBUG0 - Debug Register 0 */ +/*! @name DEBUG0 - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) @@ -92404,16 +86661,22 @@ typedef struct { #define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode + * 0b00..Disconnect + * 0b01..Connect + */ #define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode + * 0b00..Disable + * 0b01..Enable + */ #define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name DEBUG0_SET - Debug Register 0 */ +/*! @name DEBUG0_SET - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) @@ -92423,16 +86686,16 @@ typedef struct { #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name DEBUG0_CLR - Debug Register 0 */ +/*! @name DEBUG0_CLR - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) @@ -92442,16 +86705,16 @@ typedef struct { #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name DEBUG0_TOG - Debug Register 0 */ +/*! @name DEBUG0_TOG - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) @@ -92461,181 +86724,181 @@ typedef struct { #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name VERSION - Version Register */ +/*! @name VERSION - Version */ /*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) -/*! STEP - STEP */ +/*! STEP - Step */ #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) #define USBPHY_VERSION_MINOR_MASK (0xFF0000U) #define USBPHY_VERSION_MINOR_SHIFT (16U) -/*! MINOR - MINOR */ +/*! MINOR - Minor */ #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) -/*! MAJOR - MAJOR */ +/*! MAJOR - Major */ #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /*! @} */ -/*! @name IP - IP Block Register */ +/*! @name IP - IP Block */ /*! @{ */ #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name IP_SET - IP Block Register */ +/*! @name IP_SET - IP Block */ /*! @{ */ #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name IP_CLR - IP Block Register */ +/*! @name IP_CLR - IP Block */ /*! @{ */ #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name IP_TOG - IP Block Register */ +/*! @name IP_TOG - IP Block */ /*! @{ */ #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name PLL_SIC - PLL SIC Register */ +/*! @name PLL_SIC - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend - * 0b0..Power up PLL without regard to state of UTMI_SUSPENDM - * 0b1..Power down PLL when in Suspend bus state +/*! MISC2_CONTROL0 - Miscellaneous Control + * 0b0..Power up PLL + * 0b1..Power down PLL */ #define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable - * 0b0..Disable PLL multi-phase 480 MHz clock outputs - * 0b1..Enable PLL multi-phase 480 MHz clock outputs +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control - * 0b0..Powers down the USB PLL - * 0b1..Allows powerup of USB PLL +/*! PLL_POWER - USB PLL Powerup Control + * 0b0..Power down + * 0b1..Allow powerup */ #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable - * 0b0..Disable PLL single phase 480 MHz clock output - * 0b1..Enable PLL single phase 480 MHz clock output +/*! PLL_ENABLE - PLL Output Clock Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) /*! PLL_BYPASS - Bypass USB PLL - * 0b0..Select PLL 480 MHz output clock for output mux - * 0b1..Select PLL input reference clock for output mux + * 0b0..480 MHz output clock + * 0b1..Input reference clock */ #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control - * 0b0..Control reference bias with PLL POWER internal state signal - * 0b1..Control reference bias with PLL_SIC[REFBIAS_PWD] +/*! REFBIAS_PWD_SEL - Reference Bias Power Control + * 0b0..PLL_POWER internal state signal + * 0b1..REFBIAS_PWD */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias - * 0b0..Enable master reference bias in direct power control mode - * 0b1..Power down master reference bias in direct power control mode +/*! REFBIAS_PWD - Power Down Reference Bias + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator - * 0b0..Disable the local regulator for the PLL - * 0b1..Enable the local regulator for the PLL +/*! PLL_REG_ENABLE - Enable PLL Regulator + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration - * 0b000..Configure for 32 MHz input clock (Divide by 15) - * 0b001..Configure for 30 MHz input clock (Divide by 16) - * 0b010..Configure for 24 MHz input clock (Divide by 20) - * 0b011..Reserved, not usable for USB operation (Divide by 22) - * 0b100..Configure for 20 MHz input clock (Divide by 24) - * 0b101..Configure for 19.2 MHz input clock (Divide by 25) - * 0b110..Configure for 16 MHz input clock (Divide by 30) - * 0b111..Configure for 12 MHz input clock (Divide by 40) May give marginal jitter results. +/*! PLL_DIV_SEL - PLL Divider Value Configuration + * 0b000..Configure for a 32 MHz input clock (divide by 15) + * 0b001..Configure for a 30 MHz input clock (divide by 16) + * 0b010..Configure for a 24 MHz input clock (divide by 20) + * 0b011..Reserved, not usable for USB operation (divide by 22) + * 0b100..Configure for a 20 MHz input clock (divide by 24) + * 0b101..Configure for a 19.2 MHz input clock (divide by 25) + * 0b110..Configure for a 16 MHz input clock (divide by 30) + * 0b111..Configure for a 12 MHz input clock (divide by 40) */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator - * 0b0..The USB PLL is not currently locked - * 0b1..The USB PLL is currently locked +/*! PLL_LOCK - USB PLL Lock Status Indicator + * 0b0..Not locked + * 0b1..Locked */ #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) /*! @} */ -/*! @name PLL_SIC_SET - PLL SIC Register */ +/*! @name PLL_SIC_SET - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend */ +/*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable */ +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control */ +/*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable */ +/*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) @@ -92645,51 +86908,51 @@ typedef struct { #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control */ +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias */ +/*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator */ +/*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration */ +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator */ +/*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) /*! @} */ -/*! @name PLL_SIC_CLR - PLL SIC Register */ +/*! @name PLL_SIC_CLR - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend */ +/*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable */ +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control */ +/*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable */ +/*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) @@ -92699,51 +86962,51 @@ typedef struct { #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control */ +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias */ +/*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator */ +/*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration */ +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator */ +/*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) /*! @} */ -/*! @name PLL_SIC_TOG - PLL SIC Register */ +/*! @name PLL_SIC_TOG - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend */ +/*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable */ +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control */ +/*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable */ +/*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) @@ -92753,41 +87016,41 @@ typedef struct { #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control */ +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias */ +/*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator */ +/*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration */ +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator */ +/*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold +/*! VBUSVALID_THRESH - VBUS Comparator Threshold * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V - * 0b100..4.4 V (Default) + * 0b100..4.4 V * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V @@ -92796,1162 +87059,1162 @@ typedef struct { #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable + * 0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND + * 0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB subsystem - * 0b1..Use the VBUS_VALID_3V comparator results for signal reported to the USB subsystem +/*! VBUSVALID_SEL - VBUS_VALID Selection + * 0b0..VBUS_VALID comparator result + * 0b1..VBUS_VALID_3V comparator result */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB subsystem - * 0b01..Use the Session Valid comparator results for signal reported to the USB subsystem - * 0b10..Use the Session Valid comparator results for signal reported to the USB subsystem +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection + * 0b00..VBUS_VALID comparator result + * 0b01..Session valid comparator result + * 0b10..Session valid comparator result * 0b11.. */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override - * 0b0..Use PHY's ID pin detector or external override for ID status +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override + * 0b0..Use ID pin detector or external override * 0b1..Allow local override of ID pin detection status */ #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY - * 0b0..Determine the reported ID pin status results using the PHY's internal detector or local override - * 0b1..Determine the reported ID pin status results using the external ID signal value +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable + * 0b0..Internal detector or local override + * 0b1..External ID signal value */ #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY - * 0b0..Determine the reported VBUS detection results using the PHY's internal comparators/detectors or local overrides - * 0b1..Determine the reported VBUS detection results using the external VBUS_VALID value +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable + * 0b0..Internal detector or local override + * 0b1..External VBUS_VALID value */ #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session Valid detector for VBUS_VALID results. The Session Valid threshold is >= 0.8V and <= 4.0V. +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection + * 0b0..VBUS_VALID comparator + * 0b1..Session valid detector */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators - * 0bxx0..Power down the VBUS_VALID comparator +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable + * 0bxx0..Disable or power down the VBUS_VALID comparator * 0bxx1..Enable the VBUS_VALID comparator - * 0bx0x..Power down the Session Valid detector - * 0bx1x..Enable the Session Valid detector - * 0b0xx..Power down VBUS_VALID_3V detector + * 0bx0x..Disable or power down the session valid detector + * 0bx1x..Enable the session valid detector + * 0b0xx..Disable or power down the VBUS_VALID_3V detector * 0b1xx..Enable the VBUS_VALID_3V detector */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor - * 0b0..VBUS discharge resistor is disabled - * 0b1..VBUS discharge resistor is enabled +/*! DISCHARGE_VBUS - VBUS Discharge Resistor + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT_SET - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT_SET - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold */ +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override */ +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override */ +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY */ +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY */ +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID */ +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators */ +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */ +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold */ +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override */ +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override */ +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY */ +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY */ +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID */ +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators */ +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */ +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold */ +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override */ +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override */ +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY */ +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY */ +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID */ +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators */ +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */ +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold +/*! SESSEND - Session End Indicator + * 0b0..Above threshold + * 0b1..Below threshold */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold +/*! BVALID - B-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold +/*! AVALID - A-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold +/*! VBUS_VALID - VBUS Voltage Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status - * 0b0..VBUS voltage is below the VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above the VBUS_VALID_3V threshold +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator */ +/*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status */ +/*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status */ +/*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status */ +/*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status */ +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator */ +/*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status */ +/*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status */ +/*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status */ +/*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status */ +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator */ +/*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status */ +/*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status */ +/*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status */ +/*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status */ +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) - * 0b0..Disables BC Secondary Detection function when controlled by this register - * 0b1..Enables BC Secondary Detection function when controlled by this register +/*! DETECT_SEC - Secondary Detection Function Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control - * 0b0..DP pullup resistor controlled only with UTMI bus signals - * 0b1..Force DP pullup resistor to be enabled +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - * 0b0..Disables CDP advertisement signaling VDM_SRC function when controlled by this register. - * 0b1..Enables CDP advertisement signaling VDM_SRC function when controlled by this register. +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) - * 0b0..Disables BC Data Contact Detect function when controlled by this register - * 0b1..Enables BC Data Contact Detect function when controlled by this register +/*! CHK_CONTACT - BC Data Contact Detect Function Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) - * 0b0..Enables BC Charger Detection function when controlled by this register - * 0b1..Disables BC Charger Detection function when controlled by this register +/*! CHK_CHRG_B - BC Charger Detection Function Enable + * 0b0..Enable + * 0b1..Disable */ #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) - * 0b0..Enables BC v1.2 functions when controlled by this register - * 0b1..Disables BC v1.2 functions when controlled by this register +/*! EN_B - Selection of BC v1.2 Function Enable + * 0b0..Enable + * 0b1..Disable */ #define USBPHY_USB1_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits - * 0b0..Bit fields in USB1_CHRG_DETECT control BC 1.2 functionality - * 0b1..Bit fields and state machines in USBHSDCD module control BC 1.2 functionality +/*! DCDSEL - DCD Selection + * 0b0..Fields in USB1_CHRG_DETECT + * 0b1..Fields and state machines in the USBHSDCD module */ #define USBPHY_USB1_CHRG_DETECT_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT_SET - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT_SET - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) */ +/*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control */ +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - */ +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) */ +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) */ +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) */ +/*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits */ +/*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT_CLR - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT_CLR - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) */ +/*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control */ +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - */ +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) */ +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) */ +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) */ +/*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits */ +/*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT_TOG - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT_TOG - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) */ +/*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control */ +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - */ +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) */ +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) */ +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) */ +/*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits */ +/*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output - * 0b0..No USB cable attachment has been detected - * 0b1..A USB cable attachment between the device and host has been detected +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output + * 0b0..Not detected + * 0b1..Detected */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output - * 0b0..Standard Downstream Port (SDP) has been detected - * 0b1..Charging Port has been detected +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output + * 0b0..SDP detected + * 0b1..Charging port detected */ #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage - * 0b0..USB_DM pin voltage is <= 0.8V - * 0b1..USB_DM pin voltage is >= 2.0V +/*! DM_STATE - DM Voltage + * 0b0..USB_DM pin voltage is <= 0.8 V + * 0b1..USB_DM pin voltage is >= 2.0 V */ #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage - * 0b0..USB_DP pin voltage is <= 0.8V - * 0b1..USB_DP pin voltage is >= 2.0V +/*! DP_STATE - DP Voltage + * 0b0..USB_DP pin voltage is <= 0.8 V + * 0b1..USB_DP pin voltage is >= 2.0 V */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output - * 0b0..Charging Downstream Port (CDP) has been detected - * 0b1..Downstream Charging Port (DCP) has been detected +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output + * 0b0..CDP detected + * 0b1..DCP detected */ #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output */ +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output */ +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage */ +/*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage */ +/*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output */ +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output */ +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output */ +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage */ +/*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage */ +/*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output */ +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output */ +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output */ +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage */ +/*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage */ +/*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output */ +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK) /*! @} */ -/*! @name ANACTRL - Analog Control Register */ +/*! @name ANACTRL - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit - * 0b0..Disable the internal low voltage detector for the USB 3.3 V and 1.8 V domain - * 0b1..Enable the internal low voltage detector for the USB 3.3 V and 1.8 V domain +/*! LVI_EN - Internal Low Voltage Detector Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control - * 0b00..USB1PFDCLK is the same frequency as the USB PLL reference clock - * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4 - * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2 - * 0b11..USB1PFDCLK is the same as the pfd_clk frequency +/*! PFD_CLK_SEL - PFD Clock Selection + * 0b00..USB1PFDCLK = USB PLL reference clock + * 0b01..USB1PFDCLK = pfd_clk / 4 + * 0b10..USB1PFDCLK frequency = pfd_clk / 2 + * 0b11..USB1PFDCLK = pfd_clk */ #define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable - * 0b0..The 15 kohm nominal pulldowns on the USB_DP and USB_DM pins are disabled for Device mode - * 0b1..The 15 kohm nominal pulldowns on the USB_DP and USB_DM pins are enabled for Device mode +/*! DEV_PULLDOWN - Device Pulldown Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name ANACTRL_SET - Analog Control Register */ +/*! @name ANACTRL_SET - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit */ +/*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control */ +/*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable */ +/*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name ANACTRL_CLR - Analog Control Register */ +/*! @name ANACTRL_CLR - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit */ +/*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control */ +/*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable */ +/*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name ANACTRL_TOG - Analog Control Register */ +/*! @name ANACTRL_TOG - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit */ +/*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control */ +/*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable */ +/*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN - Trim Register */ +/*! @name TRIM_OVERRIDE_EN - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value - * 0b0..Use the TRIM_OVERRIDE_EN register values for the PLL divider value - * 0b1..Use the PLL_SIC register values for the PLL divider value +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value + * 0b0..TRIM_OVERRIDE_EN + * 0b1..PLL_SIC */ #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim - * 0b0..Use the TRIM_OVERRIDE_EN register values for HS Tx output current trim - * 0b1..Use the Tx register values for HS Tx output current trim +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim - * 0b0..Use the TRIM_OVERRIDE_EN register values for DP resistance trim - * 0b1..Use the Tx register values for DP resistance trim +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim - * 0b0..Use the TRIM_OVERRIDE_EN register values for DM resistance trim - * 0b1..Use the Tx register values for DM resistance trim +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN_SET - Trim Register */ +/*! @name TRIM_OVERRIDE_EN_SET - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value */ +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim */ +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim */ +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim */ +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN_CLR - Trim Register */ +/*! @name TRIM_OVERRIDE_EN_CLR - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value */ +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim */ +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim */ +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim */ +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN_TOG - Trim Register */ +/*! @name TRIM_OVERRIDE_EN_TOG - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value */ +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim */ +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim */ +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim */ +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name PFDA - PFD Register A */ +/*! @name PFDA - PFD A */ /*! @{ */ #define USBPHY_PFDA_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate - * 0b0..PFD0 clock output is enabled - * 0b1..PFD0 clock output is gated (Default) +/*! PFD0_CLKGATE - PFD0 Clock Gate + * 0b0..Enable + * 0b1..Disable */ #define USBPHY_PFDA_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK) #define USBPHY_PFDA_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal + * 0b0..Not stable + * 0b1..Stable + */ #define USBPHY_PFDA_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK) /*! @} */ -/*! @name PFDA_SET - PFD Register A */ +/*! @name PFDA_SET - PFD A */ /*! @{ */ #define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate */ +/*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_SET_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK) #define USBPHY_PFDA_SET_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK) /*! @} */ -/*! @name PFDA_CLR - PFD Register A */ +/*! @name PFDA_CLR - PFD A */ /*! @{ */ #define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate */ +/*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_CLR_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK) #define USBPHY_PFDA_CLR_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK) /*! @} */ -/*! @name PFDA_TOG - PFD Register A */ +/*! @name PFDA_TOG - PFD A */ /*! @{ */ #define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate */ +/*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_TOG_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK) #define USBPHY_PFDA_TOG_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK) /*! @} */ @@ -94367,14 +88630,14 @@ typedef struct { #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level - * 0b00000111..Data 7 line signal level - * 0b00000110..Data 6 line signal level - * 0b00000101..Data 5 line signal level - * 0b00000100..Data 4 line signal level - * 0b00000011..Data 3 line signal level - * 0b00000010..Data 2 line signal level - * 0b00000001..Data 1 line signal level - * 0b00000000..Data 0 line signal level + * 0b10000000..Data 7 line signal level + * 0b01000000..Data 6 line signal level + * 0b00100000..Data 5 line signal level + * 0b00010000..Data 4 line signal level + * 0b00001000..Data 3 line signal level + * 0b00000100..Data 2 line signal level + * 0b00000010..Data 1 line signal level + * 0b00000001..Data 0 line signal level */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ @@ -94520,8 +88783,8 @@ typedef struct { #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value - * 0b1110..SDCLK x 2 30 recommend to use for SDR104 mode - * 0b1101..SDCLK x 2 29 recommend to use for other speed mode except SDR104 mode + * 0b1110..SDCLK x 2 30, recommend to use for SDR104 mode + * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except SDR104 mode * 0b0011..SDCLK x 2 19 * 0b0010..SDCLK x 2 18 * 0b0001..SDCLK x 2 33 @@ -94529,6 +88792,11 @@ typedef struct { */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) +#define USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) +/*! RST_FIFO - Reset the async FIFO */ +#define USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK) + #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ @@ -95714,15 +89982,15 @@ typedef struct { */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) -/*! TUNING_8bit_EN - Tuning 8bit enable */ -#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) - -#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) -#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) -/*! TUNING_1bit_EN - Tuning 1bit enable */ -#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) +/*! TUNING_BIT_EN - Tuning bit enable + * 0b00..Enable Tuning circuit for DATA[3:0] + * 0b01..Enable Tuning circuit for DATA[7:0] + * 0b10..Enable Tuning circuit for DATA[0] + * 0b11..Invalid + */ +#define USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) @@ -95739,6 +90007,14 @@ typedef struct { * 0b0..Disable */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) +#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) +/*! EN_32K_CLK - Select the clock source for host card detection. + * 0b0..Use the peripheral clock (ipg_clk) for card detection. + * 0b1..Use the low power clock (ipg_clk_lp) for card detection. + */ +#define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ @@ -96254,6 +90530,14 @@ typedef struct { */ #define VBAT_STATUSA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK) +#define VBAT_STATUSA_LIGHT_DET_MASK (0x400U) +#define VBAT_STATUSA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Light error not detected + * 0b1..Light error detected + */ +#define VBAT_STATUSA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK) + #define VBAT_STATUSA_SEC0_DET_MASK (0x1000U) #define VBAT_STATUSA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96387,6 +90671,14 @@ typedef struct { */ #define VBAT_IRQENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK) +#define VBAT_IRQENA_LIGHT_DET_MASK (0x400U) +#define VBAT_IRQENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK) + #define VBAT_IRQENA_SEC0_DET_MASK (0x1000U) #define VBAT_IRQENA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96520,6 +90812,14 @@ typedef struct { */ #define VBAT_WAKENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK) +#define VBAT_WAKENA_LIGHT_DET_MASK (0x400U) +#define VBAT_WAKENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK) + #define VBAT_WAKENA_SEC0_DET_MASK (0x1000U) #define VBAT_WAKENA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96613,6 +90913,14 @@ typedef struct { */ #define VBAT_TAMPERA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK) +#define VBAT_TAMPERA_LIGHT_DET_MASK (0x400U) +#define VBAT_TAMPERA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK) + #define VBAT_TAMPERA_SEC0_DET_MASK (0x1000U) #define VBAT_TAMPERA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96688,21 +90996,15 @@ typedef struct { #define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK (0xCU) #define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT (2U) -/*! COARSE_AMP_GAIN - Amplifier Gain Coarse Adjustment - * 0b00..0.5 uA/V - * 0b01..1.0 uA/V - * 0b10..1.8 uA/V - * 0b11..3.3 uA/V +/*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external + * crystal ESR values See the device datasheet for the ranges supported by this device + * 0b00..ESR Range 0 + * 0b01..ESR Range 1 + * 0b10..ESR Range 2 + * 0b11..ESR Range 3 */ #define VBAT_OSCCTLA_COARSE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) -#define VBAT_OSCCTLA_FINE_AMP_GAIN_MASK (0x30U) -#define VBAT_OSCCTLA_FINE_AMP_GAIN_SHIFT (4U) -/*! FINE_AMP_GAIN - Amplifier Gain Fine Adjustment - * 0b00..200 mV - */ -#define VBAT_OSCCTLA_FINE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_FINE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_FINE_AMP_GAIN_MASK) - #define VBAT_OSCCTLA_CAP_SEL_EN_MASK (0x80U) #define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT (7U) /*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable @@ -96758,15 +91060,18 @@ typedef struct { #define VBAT_OSCCTLA_MODE_EN_MASK (0x30000U) #define VBAT_OSCCTLA_MODE_EN_SHIFT (16U) /*! MODE_EN - Mode Enable - * 0b00..Transconductance Oscillator mode - * 0b01..Low-Power Backup mode - * 0b10..Low-Power Switched mode + * 0b00..Normal mode + * 0b01..Startup mode + * 0b11..Low power mode */ #define VBAT_OSCCTLA_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK) #define VBAT_OSCCTLA_SUPPLY_DET_MASK (0xC0000U) #define VBAT_OSCCTLA_SUPPLY_DET_SHIFT (18U) -/*! SUPPLY_DET - Supply Detector Trim */ +/*! SUPPLY_DET - Supply Detector Trim + * 0b00..VBAT supply is less than 3V + * 0b01..VBAT supply is greater than 3V + */ #define VBAT_OSCCTLA_SUPPLY_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK) /*! @} */ @@ -96782,19 +91087,43 @@ typedef struct { /*! @name OSCCFGA - Oscillator Configuration A */ /*! @{ */ -#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x7U) +#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x3U) #define VBAT_OSCCFGA_CMP_TRIM_SHIFT (0U) -/*! CMP_TRIM - Comparator Trim */ +/*! CMP_TRIM - Comparator Trim + * 0b00..760 mV + * 0b01..770 mV + * 0b11..740 mV + */ #define VBAT_OSCCFGA_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK) +#define VBAT_OSCCFGA_CAP2_TRIM_MASK (0x4U) +#define VBAT_OSCCFGA_CAP2_TRIM_SHIFT (2U) +/*! CAP2_TRIM - CAP2_TRIM */ +#define VBAT_OSCCFGA_CAP2_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK) + #define VBAT_OSCCFGA_DLY_TRIM_MASK (0x78U) #define VBAT_OSCCFGA_DLY_TRIM_SHIFT (3U) -/*! DLY_TRIM - Delay Trim */ +/*! DLY_TRIM - Delay Trim + * 0b0000..P current 9(nA) and N Current 6(nA) + * 0b0001..P current 13(nA) and N Current 6(nA) + * 0b0011..P current 4(nA) and N Current 6(nA) + * 0b0100..P current 9(nA) and N Current 4(nA) + * 0b0101..P current 13(nA) and N Current 4(nA) + * 0b0111..P current 4(nA) and N Current 4(nA) + * 0b1000..P current 9(nA) and N Current 2(nA) + * 0b1001..P current 13(nA) and N Current 2(nA) + * 0b1011..P current 4(nA) and N Current 2(nA) + */ #define VBAT_OSCCFGA_DLY_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK) #define VBAT_OSCCFGA_CAP_TRIM_MASK (0x180U) #define VBAT_OSCCFGA_CAP_TRIM_SHIFT (7U) -/*! CAP_TRIM - Capacitor Trim */ +/*! CAP_TRIM - Capacitor Trim + * 0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ) + * 0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01) + * 0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10) + * 0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11) + */ #define VBAT_OSCCFGA_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK) #define VBAT_OSCCFGA_INIT_TRIM_MASK (0xE00U) @@ -96930,8 +91259,8 @@ typedef struct { #define VBAT_LDOCTLA_REFRESH_EN_MASK (0x4U) #define VBAT_LDOCTLA_REFRESH_EN_SHIFT (2U) /*! REFRESH_EN - Refresh Enable - * 0b0..Disable - * 0b1..Enable + * 0b0..Refresh mode is disabled + * 0b1..Refresh mode is enabled for low power operation */ #define VBAT_LDOCTLA_REFRESH_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK) /*! @} */ @@ -96988,13 +91317,37 @@ typedef struct { */ #define VBAT_LDORAMC_SWI(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK) -#define VBAT_LDORAMC_RET_MASK (0xF00U) -#define VBAT_LDORAMC_RET_SHIFT (8U) -/*! RET - Retention - * 0b0000..Retained - * 0b0001..Not retained +#define VBAT_LDORAMC_RET0_MASK (0x100U) +#define VBAT_LDORAMC_RET0_SHIFT (8U) +/*! RET0 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes */ -#define VBAT_LDORAMC_RET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK) +#define VBAT_LDORAMC_RET0(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK) + +#define VBAT_LDORAMC_RET1_MASK (0x200U) +#define VBAT_LDORAMC_RET1_SHIFT (9U) +/*! RET1 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET1(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK) + +#define VBAT_LDORAMC_RET2_MASK (0x400U) +#define VBAT_LDORAMC_RET2_SHIFT (10U) +/*! RET2 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET2(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK) + +#define VBAT_LDORAMC_RET3_MASK (0x800U) +#define VBAT_LDORAMC_RET3_SHIFT (11U) +/*! RET3 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET3(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK) /*! @} */ /*! @name LDOTIMER0 - Bandgap Timer 0 */ @@ -97139,6 +91492,14 @@ typedef struct { * 0b1..Temperature detect is enabled */ #define VBAT_TAMCTLA_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK) + +#define VBAT_TAMCTLA_LIGHT_EN_MASK (0x4U) +#define VBAT_TAMCTLA_LIGHT_EN_SHIFT (2U) +/*! LIGHT_EN - Light Detect Enable + * 0b0..Light detect is disabled + * 0b1..Light detect is enabled + */ +#define VBAT_TAMCTLA_LIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK) /*! @} */ /*! @name TAMCTLB - TAMPER Control B */ @@ -97327,9 +91688,9 @@ typedef struct { /** VREF - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ - uint32_t PARAM; /**< Parameters, offset: 0x4 */ - __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ uint8_t RESERVED_0[4]; + __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ + uint8_t RESERVED_1[4]; __IO uint32_t UTRIM; /**< User Trim, offset: 0x10 */ } VREF_Type; @@ -97412,39 +91773,6 @@ typedef struct { */ #define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) -#define VREF_CSR_REFCHSELN_EN_MASK (0x40U) -#define VREF_CSR_REFCHSELN_EN_SHIFT (6U) -/*! REFCHSELN_EN - Reference Channel Select Negative Enable - * 0b0..Disables - * 0b1..Enables - */ -#define VREF_CSR_REFCHSELN_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELN_EN_SHIFT)) & VREF_CSR_REFCHSELN_EN_MASK) - -#define VREF_CSR_REFCHSELP_EN_MASK (0x80U) -#define VREF_CSR_REFCHSELP_EN_SHIFT (7U) -/*! REFCHSELP_EN - Reference Channel Select Positive Enable - * 0b0..Disables - * 0b1..Enables - */ -#define VREF_CSR_REFCHSELP_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELP_EN_SHIFT)) & VREF_CSR_REFCHSELP_EN_MASK) - -#define VREF_CSR_VRSEL_MASK (0x300U) -#define VREF_CSR_VRSEL_SHIFT (8U) -/*! VRSEL - Voltage Reference Selection - * 0b00..Internal bandgap - * 0b01..Low-power buffered 1v - * 0b10..Buffer 2.1v output - */ -#define VREF_CSR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VRSEL_SHIFT)) & VREF_CSR_VRSEL_MASK) - -#define VREF_CSR_REFL_GRD_SEL_MASK (0x400U) -#define VREF_CSR_REFL_GRD_SEL_SHIFT (10U) -/*! REFL_GRD_SEL - Ground Select - * 0b0..vrefl_3v - * 0b1..VSSA - */ -#define VREF_CSR_REFL_GRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFL_GRD_SEL_SHIFT)) & VREF_CSR_REFL_GRD_SEL_MASK) - #define VREF_CSR_HI_PWR_LV_MASK (0x800U) #define VREF_CSR_HI_PWR_LV_SHIFT (11U) /*! HI_PWR_LV - High-Power Level @@ -97475,7 +91803,7 @@ typedef struct { #define VREF_UTRIM_TRIM2V1_MASK (0xFU) #define VREF_UTRIM_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1V Trim */ +/*! TRIM2V1 - VREF 2.1 V Trim */ #define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) #define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) @@ -97574,6 +91902,7 @@ typedef struct { * 0b0000000000000000..Standard features implemented * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for * external pin/filter detection during all power modes enabled. + * *.. */ #define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) @@ -97921,21 +92250,21 @@ typedef struct { #define WUU_PE2_WUPE30_MASK (0x30000000U) #define WUU_PE2_WUPE30_SHIFT (28U) -/*! WUPE30 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported - * 0b11..Not supported +/*! WUPE30 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK) #define WUU_PE2_WUPE31_MASK (0xC0000000U) #define WUU_PE2_WUPE31_SHIFT (30U) -/*! WUPE31 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported - * 0b11..Not supported +/*! WUPE31 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK) /*! @} */ @@ -97945,81 +92274,81 @@ typedef struct { #define WUU_ME_WUME0_MASK (0x1U) #define WUU_ME_WUME0_SHIFT (0U) -/*! WUME0 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) #define WUU_ME_WUME1_MASK (0x2U) #define WUU_ME_WUME1_SHIFT (1U) -/*! WUME1 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) #define WUU_ME_WUME2_MASK (0x4U) #define WUU_ME_WUME2_SHIFT (2U) -/*! WUME2 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) #define WUU_ME_WUME3_MASK (0x8U) #define WUU_ME_WUME3_SHIFT (3U) -/*! WUME3 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME3 - Module Interrupt Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) #define WUU_ME_WUME4_MASK (0x10U) #define WUU_ME_WUME4_SHIFT (4U) -/*! WUME4 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME4 - Module Interrupt Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK) #define WUU_ME_WUME5_MASK (0x20U) #define WUU_ME_WUME5_SHIFT (5U) -/*! WUME5 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME5 - Module Interrupt Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK) #define WUU_ME_WUME6_MASK (0x40U) #define WUU_ME_WUME6_SHIFT (6U) -/*! WUME6 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) #define WUU_ME_WUME7_MASK (0x80U) #define WUU_ME_WUME7_SHIFT (7U) -/*! WUME7 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME7 - Module Interrupt Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK) #define WUU_ME_WUME8_MASK (0x100U) #define WUU_ME_WUME8_SHIFT (8U) -/*! WUME8 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) #define WUU_ME_WUME9_MASK (0x200U) #define WUU_ME_WUME9_SHIFT (9U) -/*! WUME9 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME9 - Module Interrupt Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME9(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK) /*! @} */ @@ -98029,81 +92358,81 @@ typedef struct { #define WUU_DE_WUDE0_MASK (0x1U) #define WUU_DE_WUDE0_SHIFT (0U) -/*! WUDE0 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK) #define WUU_DE_WUDE1_MASK (0x2U) #define WUU_DE_WUDE1_SHIFT (1U) -/*! WUDE1 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK) #define WUU_DE_WUDE2_MASK (0x4U) #define WUU_DE_WUDE2_SHIFT (2U) -/*! WUDE2 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK) #define WUU_DE_WUDE3_MASK (0x8U) #define WUU_DE_WUDE3_SHIFT (3U) -/*! WUDE3 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK) #define WUU_DE_WUDE4_MASK (0x10U) #define WUU_DE_WUDE4_SHIFT (4U) -/*! WUDE4 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) #define WUU_DE_WUDE5_MASK (0x20U) #define WUU_DE_WUDE5_SHIFT (5U) -/*! WUDE5 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK) #define WUU_DE_WUDE6_MASK (0x40U) #define WUU_DE_WUDE6_SHIFT (6U) -/*! WUDE6 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) #define WUU_DE_WUDE7_MASK (0x80U) #define WUU_DE_WUDE7_SHIFT (7U) -/*! WUDE7 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK) #define WUU_DE_WUDE8_MASK (0x100U) #define WUU_DE_WUDE8_SHIFT (8U) -/*! WUDE8 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) #define WUU_DE_WUDE9_MASK (0x200U) #define WUU_DE_WUDE9_SHIFT (9U) -/*! WUDE9 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK) /*! @} */ @@ -98353,17 +92682,17 @@ typedef struct { #define WUU_PF_WUF30_MASK (0x40000000U) #define WUU_PF_WUF30_SHIFT (30U) -/*! WUF30 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUF30 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes */ #define WUU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK) #define WUU_PF_WUF31_MASK (0x80000000U) #define WUU_PF_WUF31_SHIFT (31U) -/*! WUF31 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUF31 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes */ #define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK) /*! @} */ @@ -98727,20 +93056,20 @@ typedef struct { #define WUU_PDC2_WUPDC30_MASK (0x30000000U) #define WUU_PDC2_WUPDC30_SHIFT (28U) -/*! WUPDC30 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported +/*! WUPDC30 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK) #define WUU_PDC2_WUPDC31_MASK (0xC0000000U) #define WUU_PDC2_WUPDC31_SHIFT (30U) -/*! WUPDC31 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported +/*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK) @@ -99045,17 +93374,19 @@ typedef struct { #define WUU_PMC_WUPMC30_MASK (0x40000000U) #define WUU_PMC_WUPMC30_SHIFT (30U) -/*! WUPMC30 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUPMC30 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK) #define WUU_PMC_WUPMC31_MASK (0x80000000U) #define WUU_PMC_WUPMC31_SHIFT (31U) -/*! WUPMC31 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK) /*! @} */ @@ -99377,8 +93708,30 @@ typedef struct { * @{ */ -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_MINOR_REVISION_MASK; + + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} /*! @@ -99386,5 +93739,5 @@ typedef struct { */ /* end of group SDK_Compatibility_Symbols */ -#endif /* _MCXN947_CM33_CORE0_H_ */ +#endif /* MCXN947_CM33_CORE0_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h index c7ada2b53e..246b92bc9d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h @@ -1,15 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b230131 +** Build: b240410 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP -** All rights reserved. -** +** Copyright 2016-2024 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -31,22 +29,20 @@ #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) /* @brief CACHE64_POLSEL availability on the SoC. */ #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) /* @brief CMC availability on the SoC. */ #define FSL_FEATURE_SOC_CMC_COUNT (1) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief CTIMER availability on the SoC. */ #define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief CDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CDOG_COUNT (2) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (2) /* @brief EIM availability on the SoC. */ #define FSL_FEATURE_SOC_EIM_COUNT (1) /* @brief EMVSIM availability on the SoC. */ #define FSL_FEATURE_SOC_EMVSIM_COUNT (2) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (2) /* @brief EVTG availability on the SoC. */ #define FSL_FEATURE_SOC_EVTG_COUNT (1) /* @brief EWM availability on the SoC. */ @@ -65,12 +61,16 @@ #define FSL_FEATURE_SOC_GPIO_COUNT (12) /* @brief SPC availability on the SoC. */ #define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) /* @brief I3C availability on the SoC. */ #define FSL_FEATURE_SOC_I3C_COUNT (2) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (2) /* @brief INPUTMUX availability on the SoC. */ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (2) /* @brief LPCMP availability on the SoC. */ @@ -101,6 +101,8 @@ #define FSL_FEATURE_SOC_PDM_COUNT (1) /* @brief PINT availability on the SoC. */ #define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) /* @brief POWERQUAD availability on the SoC. */ #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) /* @brief PORT availability on the SoC. */ @@ -109,20 +111,24 @@ #define FSL_FEATURE_SOC_PWM_COUNT (2) /* @brief PUF availability on the SoC. */ #define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) /* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (2) +#define FSL_FEATURE_SOC_RTC_COUNT (1) /* @brief SCG availability on the SoC. */ #define FSL_FEATURE_SOC_SCG_COUNT (1) /* @brief SCT availability on the SoC. */ #define FSL_FEATURE_SOC_SCT_COUNT (1) /* @brief SEMA42 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) /* @brief SMARTDMA availability on the SoC. */ #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) /* @brief SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) /* @brief TSI availability on the SoC. */ #define FSL_FEATURE_SOC_TSI_COUNT (1) /* @brief USB availability on the SoC. */ @@ -178,6 +184,8 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) /* @brief Has Trigger status register. */ #define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ @@ -192,6 +200,28 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) /* @brief Temperature sensor parameter A (slope). */ #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) /* @brief Temperature sensor parameter B (offset). */ @@ -212,6 +242,8 @@ /* FLEXCAN module features */ +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -232,18 +264,13 @@ #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) -/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a - * specific moment during the arbitration process). */ +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) -/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be - * transmitted in a specific moment during the arbitration process). */ +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) -/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus - * when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle - * state). */ +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) -/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode - * are entered during a Bus-Off state). */ +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) @@ -263,6 +290,8 @@ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) /* CDOG module features */ @@ -271,10 +300,31 @@ /* CMC module features */ +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) /* @brief Has RSTCNT register */ -#define FSL_FEATURE_CMC_HAS_RSTCNT_REGISTER (1) -/* @brief Does not have SRAMCTL register */ -#define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1) /* SYSPM module features */ @@ -282,6 +332,8 @@ #define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) /* @brief Temperature sensor parameter B (offset). */ #define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) /* CTIMER module features */ @@ -295,6 +347,8 @@ #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) /* LPDAC module features */ @@ -310,59 +364,87 @@ #define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) /* @brief Has internal reference current options. */ #define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) /* EDMA module features */ -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid - * only for eDMA modules.) */ +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) /* @brief Has DMA_Error interrupt vector. */ #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) -/* @brief Has register access permission. */ -#define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) /* @brief If channel clock controlled independently */ #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) -/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference - * instance) */ +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) /* @brief Has no register bit fields MP_CSR[EBW]. */ #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) -/* @brief If dma has channel mux */ -#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) /* @brief If dma has common clock gate */ #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) /* @brief If dma channel IRQ support parameter */ #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) /* @brief Has no register bit fields CH_SBR[ATTR]. */ #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) -/* @brief If 8 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) -/* @brief If 16 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) -/* @brief If 64 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) - -/* DMA_TCD module features */ - -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_OSCE (1) - -/* ENC module features */ - -/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ -#define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0) -/* @brief Has register CTRL3. */ -#define FSL_FEATURE_ENC_HAS_CTRL3 (1) -/* @brief Has register LASTEDGE or LASTEDGEH. */ -#define FSL_FEATURE_ENC_HAS_LASTEDGE (1) -/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ -#define FSL_FEATURE_ENC_HAS_POSDPER (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) /* EVTG module features */ @@ -375,6 +457,8 @@ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -391,6 +475,8 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* FLEXSPI module features */ @@ -404,6 +490,8 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) /* @brief FlexSPI DMA needs multiple DES to transfer */ #define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* GPIO module features */ @@ -421,7 +509,7 @@ /* I3C module features */ /* @brief Has TERM bitfile in MERRWARN register. */ -#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (0) /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ @@ -429,6 +517,13 @@ /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + /* INTM module features */ /* @brief Up to 4 programmable interrupt monitors */ @@ -449,6 +544,10 @@ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -458,15 +557,20 @@ #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) /* LPUART module features */ /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the - * registers are 32-bit wide). */ +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) @@ -486,8 +590,7 @@ #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) /* @brief Baud rate fine adjustment is available. */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], - * BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) @@ -499,13 +602,11 @@ #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are - * 32-bit wide). */ +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit - * wide). */ +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) @@ -552,7 +653,7 @@ /* MRT module features */ /* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) /* OPAMP module features */ @@ -569,7 +670,7 @@ /* @brief Opamp has OPAMP_CTR TRIGMD bit */ #define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) /* @brief OPAMP support reference buffer */ -#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) /* PDM module features */ @@ -580,7 +681,7 @@ /* @brief PDM FIFO WIDTH Size */ #define FSL_FEATURE_PDM_FIFO_WIDTH (4) /* @brief PDM FIFO DEPTH Size */ -#define FSL_FEATURE_PDM_FIFO_DEPTH (8) +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) /* @brief PDM has RANGE_CTRL register */ #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) /* @brief PDM Has Low Frequency */ @@ -591,6 +692,10 @@ #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) /* @brief PDM Has DC_OUT_CTRL */ #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) /* @brief PDM Has Fixed DC CTRL VALUE. */ @@ -642,6 +747,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -661,6 +768,13 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + /* PWM module features */ /* @brief If (e)FlexPWM has module A channels (outputs). */ @@ -674,11 +788,34 @@ /* @brief If (e)FlexPWM has mux trigger source select bit field. */ #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) /* @brief Number of submodules in each (e)FlexPWM module. */ -#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) /* @brief Number of fault channel in each (e)FlexPWM module. */ #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ #define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) /* RTC module features */ @@ -696,7 +833,7 @@ #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) /* @brief Has CLKO_DIS bitfile in CTRL register. */ #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) -/* @brief Has Tamper in RTC. */ +/* @brief Has No Tamper in RTC. */ #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) @@ -711,31 +848,26 @@ /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ #define FSL_FEATURE_SAI_HAS_FIFO (1) -/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], - * RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) -/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], - * RMR[RWM]). */ +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) -/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], - * TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) -/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], - * RCR4[FPACK]). */ +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) -/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields - * TCR4[FCONT], RCR4[FCONT]). */ +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) -/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning - * flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) -/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], - * RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) /* @brief Has bit field MICS of the MCR register. */ @@ -748,6 +880,8 @@ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* SCT module features */ @@ -765,20 +899,45 @@ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SINC module features */ + +/* @brief SINC channel count. */ +#define FSL_FEATURE_SINC_CHANNEL_COUNT (5) +/* @brief SINC CACFR register has bitfield ADMASEL. */ +#define FSL_FEATURE_SINC_CACFR_HAS_ADMASEL (1) +/* @brief SINC CACFR register has no bitfield PTMUX. */ +#define FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX (1) + /* SPC module features */ -/* @brief Has 2P4G power domain. */ -#define FSL_FEATURE_SPC_HAS_2P4G_POWER_DOMAIN (1) -/* @brief Has SPC_CFG. */ -#define FSL_FEATURE_SPC_HAS_CFG_REGISTER (0) -/* @brief Has core ldo vdd driver strength (register bit ACTIVE_CFG[CORELDO_VDD_DS]). */ +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ #define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) -/* @brief Has bias enable (register bit LP_CFG[WBIAS_EN]). */ -#define FSL_FEATURE_SPC_HAS_WBIAS_EN (0) -/* @brief Set CORELDO_VDD_LVL to 0 then regulate to Under Drive Voltage (0.95v). */ -#define FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE (0) -/* @brief Set DCDC_VDD_LVL to 0 then regulate to Low Under Voltage (1.25v). */ -#define FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE (0) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) /* SYSCON module features */ @@ -795,28 +954,24 @@ /* @brief Powerlib API is different with other series devices.. */ #define FSL_FEATURE_POWERLIB_EXTEND (1) -/* TRNG module features */ +/* TRDC module features */ -/* @brief TRNG does not support SCR4L. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1) -/* @brief TRNG does not support SCR5L. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1) -/* @brief TRNG does not support SCR6L. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) -/* @brief TRNG does not support PKRMAX. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1) -/* @brief TRNG does not support SAMP mode. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) -/* @brief TRNG does not support ACC. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) -/* @brief TRNG does not support SBLIM. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1) -/* @brief TRNG supports reset control. */ -#define FSL_FEATURE_TRNG_HAS_RSTCTL (1) -/* @brief TRNG does not support FOR_CLK mode. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) -/* @brief TRNG has two oscillators. */ -#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) /* TSI module features */ @@ -894,12 +1049,33 @@ #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) /* @brief Has no VSELECT bit in VEND_SPEC register */ #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) /* UTICK module features */ /* @brief UTICK does not support PD configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + /* WWDT module features */ /* @brief Has no RESET register. */ @@ -908,3 +1084,4 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) #endif /* _MCXN947_cm33_core0_FEATURES_H_ */ + diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1.h index ed21e4dba9..b1702ec306 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1.h @@ -8,17 +8,15 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCX N1xNxxx Reference Manual -** Version: rev. 1.0, 2022-10-01 -** Build: b230203 +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 2.0, 2023-02-01 +** Build: b240510 ** ** Abstract: ** CMSIS Peripheral Access Layer for MCXN947_cm33_core1 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP -** All rights reserved. -** +** Copyright 2016-2024 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -26,26 +24,28 @@ ** ** Revisions: ** - rev. 1.0 (2022-10-01) -** Initial version based on SPEC1.14 +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN947_cm33_core1.h - * @version 1.0 - * @date 2022-10-01 + * @version 2.0 + * @date 2023-02-01 * @brief CMSIS Peripheral Access Layer for MCXN947_cm33_core1 * * CMSIS Peripheral Access Layer for MCXN947_cm33_core1 */ -#ifndef _MCXN947_CM33_CORE1_H_ -#define _MCXN947_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ +#if !defined(MCXN947_CM33_CORE1_H_) +#define MCXN947_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U +#define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U @@ -203,14 +203,14 @@ typedef enum IRQn { FLEXPWM1_SUBMODULE1_IRQn = 121, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE2_IRQn = 122, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ FLEXPWM1_SUBMODULE3_IRQn = 123, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ - ENC0_COMPARE_IRQn = 124, /**< ENC0_Compare interrupt */ - ENC0_HOME_IRQn = 125, /**< ENC0_Home interrupt */ - ENC0_WDG_SAB_IRQn = 126, /**< ENC0_WDG_IRQ/SAB interrupt */ - ENC0_IDX_IRQn = 127, /**< ENC0_IDX interrupt */ - ENC1_COMPARE_IRQn = 128, /**< ENC1_Compare interrupt */ - ENC1_HOME_IRQn = 129, /**< ENC1_Home interrupt */ - ENC1_WDG_SAB_IRQn = 130, /**< ENC1_WDG_IRQ/SAB interrupt */ - ENC1_IDX_IRQn = 131, /**< ENC1_IDX interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ + QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ + QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ + QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ BSP32_IRQn = 133, /**< CoolFlux BSP32 interrupt */ ELS_ERR_IRQn = 134, /**< ELS error interrupt */ @@ -229,8 +229,8 @@ typedef enum IRQn { WUU_IRQn = 147, /**< Wake Up Unit interrupt */ PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ ETB0_IRQn = 149, /**< ETB counter expires interrupt */ - SM3_IRQn = 150, /**< Secure Generic Interface (SGI) SAFO interrupt */ - TRNG0_IRQn = 151, /**< True Random Number Generator interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ @@ -276,6 +276,262 @@ typedef enum IRQn { */ /** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestMuxFlexSpi0Rx = 1U, /**< FlexSPI0 Receive event */ + kDma1RequestMuxFlexSpi0Rx = 1U, /**< FlexSPI0 Receive event */ + kDma0RequestMuxFlexSpi0Tx = 2U, /**< FlexSPI0 Transmit event */ + kDma1RequestMuxFlexSpi0Tx = 2U, /**< FlexSPI0 Transmit event */ + kDma0RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma1RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma0RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma1RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma0RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma1RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma0RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma1RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma0RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma1RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma1RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma1RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma1RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma1RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma1RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma1RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma1RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma1RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma1RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma1RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma0RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma1RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma0RequestMuxSct0Dma0 = 19U, /**< SCT0 DMA0 */ + kDma1RequestMuxSct0Dma0 = 19U, /**< SCT0 DMA0 */ + kDma0RequestMuxSct0Dma1 = 20U, /**< SCT0 DMA1 */ + kDma1RequestMuxSct0Dma1 = 20U, /**< SCT0 DMA1 */ + kDma0RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma1RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma0RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma1RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma0RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma1RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma0RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma0RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ + kDma1RequestMuxDac0FifoRequest = 25U, /**< DAC0 FIFO_request */ + kDma0RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ + kDma1RequestMuxDac1FifoRequest = 26U, /**< DAC1 FIFO_request */ + kDma0RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ + kDma1RequestMuxDac2FifoRequest = 27U, /**< DAC2 FIFO_request */ + kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma1RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma0RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ + kDma1RequestMuxHsCmp2DmaRequest = 30U, /**< CMP2 DMA_request */ + kDma0RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma1RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma0RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma1RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma0RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma1RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma0RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma1RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma0RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma1RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma0RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma1RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma0RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma1RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma0RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma1RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma0RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma1RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma0RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma1RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma0RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma1RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma0RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma1RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma0RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma1RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma0RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma1RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma0RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma0RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma1RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma0RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma1RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma0RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma1RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma0RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma1RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma0RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma1RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma0RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma1RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma0RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma1RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma0RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma1RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma0RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma1RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma0RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma1RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma0RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma1RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma0RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma1RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma0RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma1RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma0RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma1RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma0RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma1RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma0RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma1RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma0RequestMuxLpFlexcomm8Rx = 85U, /**< LP_FLEXCOMM8 Receive request */ + kDma1RequestMuxLpFlexcomm8Rx = 85U, /**< LP_FLEXCOMM8 Receive request */ + kDma0RequestMuxLpFlexcomm8Tx = 86U, /**< LP_FLEXCOMM8 Transmit request */ + kDma1RequestMuxLpFlexcomm8Tx = 86U, /**< LP_FLEXCOMM8 Transmit request */ + kDma0RequestMuxLpFlexcomm9Rx = 87U, /**< LP_FLEXCOMM9 Receive request */ + kDma1RequestMuxLpFlexcomm9Rx = 87U, /**< LP_FLEXCOMM9 Receive request */ + kDma0RequestMuxLpFlexcomm9Tx = 88U, /**< LP_FLEXCOMM9 Transmit request */ + kDma1RequestMuxLpFlexcomm9Tx = 88U, /**< LP_FLEXCOMM9 Transmit request */ + kDma0RequestMuxEmvSim0Rx = 91U, /**< EMVSIM0 Receive request */ + kDma1RequestMuxEmvSim0Rx = 91U, /**< EMVSIM0 Receive request */ + kDma0RequestMuxEmvSim0Tx = 92U, /**< EMVSIM0 Transmit request */ + kDma1RequestMuxEmvSim0Tx = 92U, /**< EMVSIM0 Transmit request */ + kDma0RequestMuxEmvSim1Rx = 93U, /**< EMVSIM1 Receive request */ + kDma1RequestMuxEmvSim1Rx = 93U, /**< EMVSIM1 Receive request */ + kDma0RequestMuxEmvSim1Tx = 94U, /**< EMVSIM1 Transmit request */ + kDma1RequestMuxEmvSim1Tx = 94U, /**< EMVSIM1 Transmit request */ + kDma0RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma1RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma1RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma0RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma1RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma0RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma1RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma0RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma1RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma0RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma1RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma0RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma0RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ + kDma1RequestMuxSinc0IpdReqSincAlt0 = 103U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ + kDma0RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ + kDma1RequestMuxSinc1IpdReqSincAlt1 = 104U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ + kDma0RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ + kDma1RequestMuxSinc2IpdReqSincAlt2 = 105U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ + kDma0RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ + kDma1RequestMuxSinc3IpdReqSincAlt3 = 106U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ + kDma0RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ + kDma1RequestMuxSinc4IpdReqSincAlt4 = 107U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ + kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma1RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma0RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma1RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma1RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma0RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma1RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma1RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma0RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma1RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma1RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma0RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma1RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma1RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma0RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma0RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ + kDma1RequestMuxTsi0EndOfScan = 120U, /**< TSI0 End of Scan */ + kDma0RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ + kDma1RequestMuxTsi0OutOfRange = 121U, /**< TSI0 Out of Range */ +} dma_request_source_t; + +/* @} */ + /*! * @addtogroup eim_memory_channel * @{ @@ -323,7 +579,7 @@ typedef enum _eim_memory_channel typedef enum _eim_error_injection_channel_enable { - kEIM_MemoryChannelRAMXEnable = +0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ + kEIM_MemoryChannelRAMXEnable = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ kEIM_MemoryChannelRAMAEnable = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable */ kEIM_MemoryChannelRAMBEnable = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */ kEIM_MemoryChannelRAMCEnable = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */ @@ -1280,7 +1536,7 @@ typedef struct { /*! TSRC - Trigger Source * 0b00..Trigger source 0 * 0b01..Trigger source 1 - * 0b10-0b10..Corresponding trigger source initiated this conversion. + * 0b10..Trigger source 2 * 0b11..Trigger source 3 */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) @@ -2691,16 +2947,6 @@ typedef struct { */ #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) -#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_MASK (0x3000U) -#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_SHIFT (12U) -/*! SPI_FILTER - GPIO0 - * 0b00..Non-secure and non-privilege user access allowed - * 0b01..Non-secure and privilege access allowed - * 0b10..Secure and non-privilege user access allowed - * 0b11..Secure and privilege user access allowed - */ -#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SPI_FILTER_MASK) - #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) #define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) /*! PINT0 - PINT0 @@ -6912,7 +7158,7 @@ typedef struct { #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x3000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (12U) -/*! SEC_CPU1_INT_MASK0_LOCK - SSEC_CPU1_INT_MASK0 Lock +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU1_INT_MASK0 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK0 cannot be written * 0b10..SEC_GPIO_MASK0 can be written @@ -6922,7 +7168,7 @@ typedef struct { #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC000U) #define AHBSC_SEC_GP_REG_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (14U) -/*! SEC_CPU1_INT_MASK1_LOCK - SEC_GPIO_MASK1 Lock +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU1_INT_MASK1 Lock * 0b00..Reserved * 0b01..SEC_GPIO_MASK1 cannot be written * 0b10..SEC_GPIO_MASK1 can be written @@ -7377,8 +7623,8 @@ typedef struct { #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) /*! DISABLE_STRICT_MODE - Disable Strict Mode * 0b00..Reserved - * 0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level. - * 0b10..Master strict mode is disabled and can access memories and peripherals at same level only + * 0b01..Master can access memories and peripherals at the same level or below that level. + * 0b10..Master can access memories and peripherals at same level only * 0b11..Reserved */ #define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) @@ -7795,6 +8041,22 @@ typedef struct { */ #define CACHE64_CTRL_CCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK) +#define CACHE64_CTRL_CCR_FRCWT_MASK (0x4U) +#define CACHE64_CTRL_CCR_FRCWT_SHIFT (2U) +/*! FRCWT - Force Write Through Mode + * 0b0..Does not force + * 0b1..Force + */ +#define CACHE64_CTRL_CCR_FRCWT(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCWT_SHIFT)) & CACHE64_CTRL_CCR_FRCWT_MASK) + +#define CACHE64_CTRL_CCR_FRCNOALLC_MASK (0x8U) +#define CACHE64_CTRL_CCR_FRCNOALLC_SHIFT (3U) +/*! FRCNOALLC - Forces No Allocation On Cache Misses + * 0b0..Allocation on cache misses + * 0b1..Forces no allocation on cache misses (FRCWT must be asserted) + */ +#define CACHE64_CTRL_CCR_FRCNOALLC(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_FRCNOALLC_SHIFT)) & CACHE64_CTRL_CCR_FRCNOALLC_MASK) + #define CACHE64_CTRL_CCR_INVW0_MASK (0x1000000U) #define CACHE64_CTRL_CCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 @@ -7979,7 +8241,7 @@ typedef struct { /** Array initializer of CACHE64_CTRL peripheral base pointers */ #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } #endif -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** CACHE64_CTRL physical memory base address */ #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u} /** CACHE64_CTRL physical memory size */ @@ -8131,26 +8393,26 @@ typedef struct { /** CAN - Register Layout Typedef */ typedef struct { - __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ - __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ - __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; - __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ - __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ - __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ - __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ uint8_t RESERVED_1[4]; - __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ uint8_t RESERVED_2[4]; - __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ - __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ - __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ uint8_t RESERVED_3[8]; - __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ - __IO uint32_t RXFGMASK; /**< Legacy Rx FIFO Global Mask Register, offset: 0x48 */ - __I uint32_t RXFIR; /**< Legacy Rx FIFO Information Register, offset: 0x4C */ - __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ uint8_t RESERVED_4[44]; union { /* offset: 0x80 */ struct { /* offset: 0x80, array step: 0x10 */ @@ -8181,38 +8443,38 @@ typedef struct { } MB[32]; }; uint8_t RESERVED_5[1536]; - __IO uint32_t RXIMR[32]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_6[512]; - __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1 Register, offset: 0xB00 */ - __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2 Register, offset: 0xB04 */ - __IO uint32_t WU_MTC; /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */ - __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */ - __IO uint32_t FLT_DLC; /**< Pretended Networking DLC Filter Register, offset: 0xB10 */ - __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */ - __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */ - __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */ - __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register, offset: 0xB20 */ - __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */ + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ uint8_t RESERVED_7[24]; struct { /* offset: 0xB40, array step: 0x10 */ - __I uint32_t CS; /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */ - __I uint32_t ID; /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */ - __I uint32_t D03; /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */ - __I uint32_t D47; /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ } WMB[4]; uint8_t RESERVED_8[112]; __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ - __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ - __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ - __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ - __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ - __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ - __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */ - __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ uint8_t RESERVED_9[9192]; - __IO uint32_t ERFFEL[32]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ + __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ } CAN_Type; /* ---------------------------------------------------------------------------- @@ -8224,12 +8486,12 @@ typedef struct { * @{ */ -/*! @name MCR - Module Configuration Register */ +/*! @name MCR - Module Configuration */ /*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) -/*! MAXMB - Number Of The Last Message Buffer */ +/*! MAXMB - Number of the Last Message Buffer */ #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) @@ -8244,159 +8506,158 @@ typedef struct { #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) -/*! FDEN - CAN FD operation enable - * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. - * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. +/*! FDEN - CAN FD Operation Enable + * 0b1..Enable + * 0b0..Disable */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable - * 0b0..Abort disabled. - * 0b1..Abort enabled. + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable - * 0b0..Local Priority disabled. - * 0b1..Local Priority enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_PNET_EN_MASK (0x4000U) #define CAN_MCR_PNET_EN_SHIFT (14U) /*! PNET_EN - Pretended Networking Enable - * 0b0..Pretended Networking mode is disabled. - * 0b1..Pretended Networking mode is enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable - * 0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO disabled. - * 0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) -/*! IRMQ - Individual Rx Masking And Queue Enable - * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy - * applications, the reading of C/S word locks the MB even if it is EMPTY. - * 0b1..Individual Rx masking and queue feature are enabled. +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) -/*! SRXDIS - Self Reception Disable - * 0b0..Self-reception enabled. - * 0b1..Self-reception disabled. +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) -/*! WAKSRC - Wake Up Source - * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. - * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge - * 0b0..FlexCAN is not in a low-power mode. - * 0b1..FlexCAN is in a low-power mode. + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable - * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. - * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) -/*! SLFWAK - Self Wake Up - * 0b0..FlexCAN Self Wake Up feature is disabled. - * 0b1..FlexCAN Self Wake Up feature is enabled. +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge - * 0b0..FlexCAN not in Freeze mode, prescaler running. - * 0b1..FlexCAN in Freeze mode, prescaler stopped. + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset - * 0b0..No reset request. - * 0b1..Resets the registers affected by soft reset. + * 0b0..No reset + * 0b1..Soft reset affects reset registers */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) -/*! WAKMSK - Wake Up Interrupt Mask - * 0b0..Wake Up interrupt is disabled. - * 0b1..Wake Up interrupt is enabled. +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready - * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. - * 0b1..FlexCAN module is either in Disable mode, Stop mode, or Freeze mode. + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN - * 0b0..No Freeze mode request. - * 0b1..Enters Freeze mode if the FRZ bit is asserted. + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) -/*! RFEN - Legacy Rx FIFO Enable - * 0b0..Legacy Rx FIFO not enabled. - * 0b1..Legacy Rx FIFO enabled. +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable - * 0b0..Not enabled to enter Freeze mode. - * 0b1..Enabled to enter Freeze mode. + * 0b0..Disable + * 0b1..Enable */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable - * 0b0..Enable the FlexCAN module. - * 0b1..Disable the FlexCAN module. + * 0b0..Enable + * 0b1..Disable */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ -/*! @name CTRL1 - Control 1 Register */ +/*! @name CTRL1 - Control 1 */ /*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) @@ -8423,65 +8684,65 @@ typedef struct { #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync - * 0b0..Timer sync feature disabled - * 0b1..Timer sync feature enabled + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery - * 0b0..Automatic recovering from Bus Off state enabled. - * 0b1..Automatic recovering from Bus Off state disabled. + * 0b0..Enabled + * 0b1..Disabled */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling - * 0b0..Just one sample is used to determine the bit value. + * 0b0..One sample is used to determine the bit value. * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two - * preceding samples; a majority rule is used. + * preceding samples. A majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) -/*! RWRNMSK - Rx Warning Interrupt Mask - * 0b0..Rx Warning interrupt disabled. - * 0b1..Rx Warning interrupt enabled. +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) -/*! TWRNMSK - Tx Warning Interrupt Mask - * 0b0..Tx Warning interrupt disabled. - * 0b1..Tx Warning interrupt enabled. +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) -/*! LPB - Loop Back Mode - * 0b0..Loop Back disabled. - * 0b1..Loop Back enabled. +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask - * 0b0..Error interrupt disabled. - * 0b1..Error interrupt enabled. + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask - * 0b0..Bus Off interrupt disabled. - * 0b1..Bus Off interrupt enabled. + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) @@ -8506,7 +8767,7 @@ typedef struct { #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @} */ -/*! @name TIMER - Free Running Timer */ +/*! @name TIMER - Free-Running Timer */ /*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) @@ -8515,30 +8776,30 @@ typedef struct { #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @} */ -/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @name RXMGMASK - RX Message Buffers Global Mask */ /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) -/*! MG - Rx Mailboxes Global Mask Bits */ +/*! MG - Global Mask for RX Message Buffers */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ -/*! @name RX14MASK - Rx 14 Mask Register */ +/*! @name RX14MASK - Receive 14 Mask */ /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) -/*! RX14M - Rx Buffer 14 Mask Bits */ +/*! RX14M - RX Buffer 14 Mask Bits */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ -/*! @name RX15MASK - Rx 15 Mask Register */ +/*! @name RX15MASK - Receive 15 Mask */ /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) -/*! RX15M - Rx Buffer 15 Mask Bits */ +/*! RX15M - RX Buffer 15 Mask Bits */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ @@ -8557,37 +8818,37 @@ typedef struct { #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) -/*! TXERRCNT_FAST - Transmit Error Counter for fast bits */ +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) -/*! RXERRCNT_FAST - Receive Error Counter for fast bits */ +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) /*! @} */ -/*! @name ESR1 - Error and Status 1 Register */ +/*! @name ESR1 - Error and Status 1 */ /*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) -/*! WAKINT - Wake-Up Interrupt +/*! WAKINT - Wake-up Interrupt Flag * 0b0..No such occurrence. - * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) -/*! ERRINT - Error Interrupt +/*! ERRINT - Error Interrupt Flag * 0b0..No such occurrence. - * 0b1..Indicates setting of any error bit in the Error and Status register. + * 0b1..Indicates setting of any error flag in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) -/*! BOFFINT - Bus Off Interrupt +/*! BOFFINT - Bus Off Interrupt Flag * 0b0..No such occurrence. * 0b1..FlexCAN module entered Bus Off state. */ @@ -8595,9 +8856,9 @@ typedef struct { #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) -/*! RX - FlexCAN In Reception - * 0b0..FlexCAN is not receiving a message. - * 0b1..FlexCAN is receiving a message. +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) @@ -8613,22 +8874,22 @@ typedef struct { #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission - * 0b0..FlexCAN is not transmitting a message. - * 0b1..FlexCAN is transmitting a message. + * 0b0..Not transmitting + * 0b1..Transmitting */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) -/*! IDLE - IDLE - * 0b0..No such occurrence. - * 0b1..CAN bus is now IDLE. +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) -/*! RXWRN - Rx Error Warning +/*! RXWRN - RX Error Warning Flag * 0b0..No such occurrence. * 0b1..RXERRCNT is greater than or equal to 96. */ @@ -8636,47 +8897,47 @@ typedef struct { #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) -/*! TXWRN - TX Error Warning +/*! TXWRN - TX Error Warning Flag * 0b0..No such occurrence. - * 0b1..TXERRCNT is greater than or equal to 96. + * 0b1..TXERRCNT is 96 or greater. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) -/*! STFERR - Stuffing Error - * 0b0..No such occurrence. - * 0b1..A stuffing error occurred since last read of this register. +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) -/*! FRMERR - Form Error - * 0b0..No such occurrence. - * 0b1..A Form Error occurred since last read of this register. +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) -/*! CRCERR - Cyclic Redundancy Check Error - * 0b0..No such occurrence. - * 0b1..A CRC error occurred since last read of this register. +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) -/*! ACKERR - Acknowledge Error - * 0b0..No such occurrence. - * 0b1..An ACK error occurred since last read of this register. +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) -/*! BIT0ERR - Bit0 Error +/*! BIT0ERR - Bit0 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ @@ -8684,7 +8945,7 @@ typedef struct { #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) -/*! BIT1ERR - Bit1 Error +/*! BIT1ERR - Bit1 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ @@ -8692,55 +8953,55 @@ typedef struct { #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) -/*! RWRNINT - Rx Warning Interrupt Flag - * 0b0..No such occurrence. - * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) -/*! TWRNINT - Tx Warning Interrupt Flag - * 0b0..No such occurrence. - * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) -/*! SYNCH - CAN Synchronization Status - * 0b0..FlexCAN is not synchronized to the CAN bus. - * 0b1..FlexCAN is synchronized to the CAN bus. +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) -/*! BOFFDONEINT - Bus Off Done Interrupt - * 0b0..No such occurrence. +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) -/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set +/*! ERRINT_FAST - Fast Error Interrupt Flag * 0b0..No such occurrence. - * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) -/*! ERROVR - Error Overrun - * 0b0..Overrun has not occurred. - * 0b1..Overrun has occurred. +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) -/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set +/*! STFERR_FAST - Fast Stuffing Error Flag * 0b0..No such occurrence. * 0b1..A stuffing error occurred since last read of this register. */ @@ -8748,7 +9009,7 @@ typedef struct { #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) -/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set +/*! FRMERR_FAST - Fast Form Error Flag * 0b0..No such occurrence. * 0b1..A form error occurred since last read of this register. */ @@ -8756,7 +9017,7 @@ typedef struct { #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) -/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ @@ -8764,22 +9025,22 @@ typedef struct { #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) -/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set +/*! BIT0ERR_FAST - Fast Bit0 Error Flag * 0b0..No such occurrence. - * 0b1..At least one bit sent as dominant is received as recessive. + * 0b1..At least one bit transmitted as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) -/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set +/*! BIT1ERR_FAST - Fast Bit1 Error Flag * 0b0..No such occurrence. - * 0b1..At least one bit sent as recessive is received as dominant. + * 0b1..At least one bit transmitted as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) /*! @} */ -/*! @name IMASK1 - Interrupt Masks 1 Register */ +/*! @name IMASK1 - Interrupt Masks 1 */ /*! @{ */ #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) @@ -8788,44 +9049,43 @@ typedef struct { #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) /*! @} */ -/*! @name IFLAG1 - Interrupt Flags 1 Register */ +/*! @name IFLAG1 - Interrupt Flags 1 */ /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) -/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit - * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. - * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) -/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */ +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) -/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Legacy Rx FIFO - * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when MCR[RFEN]=1 - * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when - * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) -/*! BUF6I - Buffer MB6 Interrupt Or Legacy Rx FIFO Warning - * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO almost full when MCR[RFEN]=1 - * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO almost full when MCR[RFEN]=1 +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) -/*! BUF7I - Buffer MB7 Interrupt Or Legacy Rx FIFO Overflow - * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO overflow when MCR[RFEN]=1 - * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO overflow when MCR[RFEN]=1 +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) @@ -8835,119 +9095,118 @@ typedef struct { #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ -/*! @name CTRL2 - Control 2 Register */ +/*! @name CTRL2 - Control 2 */ /*! @{ */ #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) /*! EDFLTDIS - Edge Filter Disable - * 0b0..Edge filter is enabled - * 0b1..Edge filter is disabled + * 0b0..Enabled + * 0b1..Disabled */ #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable - * 0b0..FlexCAN operates using the non-ISO CAN FD protocol. - * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1:2015). + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_BTE_MASK (0x2000U) #define CAN_CTRL2_BTE_SHIFT (13U) -/*! BTE - Bit Timing Expansion enable - * 0b0..CAN Bit timing expansion is disabled. - * 0b1..CAN bit timing expansion is enabled. +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) #define CAN_CTRL2_PREXCEN_MASK (0x4000U) #define CAN_CTRL2_PREXCEN_SHIFT (14U) /*! PREXCEN - Protocol Exception Enable - * 0b0..Protocol exception is disabled. - * 0b1..Protocol exception is enabled. + * 0b0..Disabled + * 0b1..Enabled */ #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) -/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes - * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. - * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within - * the incoming frame. Mask bits do apply. +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing - * 0b0..Remote response frame is generated. - * 0b1..Remote request frame is stored. + * 0b0..Generated + * 0b1..Stored */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) -/*! MRP - Mailboxes Reception Priority - * 0b0..Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on mailboxes. - * 0b1..Matching starts from mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO. +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) -/*! TASD - Tx Arbitration Start Delay */ +/*! TASD - Transmission Arbitration Start Delay */ #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) -/*! RFFN - Number Of Legacy Rx FIFO Filters */ +/*! RFFN - Number of Legacy Receive FIFO Filters */ #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask - * 0b0..Bus off done interrupt disabled. - * 0b1..Bus off done interrupt enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) -/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames - * 0b0..ERRINT_FAST error interrupt disabled. - * 0b1..ERRINT_FAST error interrupt enabled. +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) /*! @} */ -/*! @name ESR2 - Error and Status 2 Register */ +/*! @name ESR2 - Error and Status 2 */ /*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) -/*! IMB - Inactive Mailbox - * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. - * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status - * 0b0..Contents of IMB and LPTM are invalid. - * 0b1..Contents of IMB and LPTM are valid. + * 0b0..Invalid + * 0b1..Valid */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) -/*! LPTM - Lowest Priority Tx Mailbox */ +/*! LPTM - Lowest Priority TX Message Buffer */ #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @} */ -/*! @name CRCR - CRC Register */ +/*! @name CRCR - Cyclic Redundancy Check */ /*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) @@ -8957,20 +9216,20 @@ typedef struct { #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) -/*! MBCRC - CRC Mailbox */ +/*! MBCRC - CRC Message Buffer */ #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @} */ -/*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register */ +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) -/*! FGM - Legacy Rx FIFO Global Mask Bits */ +/*! FGM - Legacy RX FIFO Global Mask Bits */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ -/*! @name RXFIR - Legacy Rx FIFO Information Register */ +/*! @name RXFIR - Legacy RX FIFO Information */ /*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) @@ -8979,7 +9238,7 @@ typedef struct { #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @} */ -/*! @name CBT - CAN Bit Timing Register */ +/*! @name CBT - CAN Bit Timing */ /*! @{ */ #define CAN_CBT_EPSEG2_MASK (0x1FU) @@ -9010,8 +9269,8 @@ typedef struct { #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable - * 0b0..Extended bit time definitions disabled. - * 0b1..Extended bit time definitions enabled. + * 0b0..Disable + * 0b1..Enable */ #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ @@ -9526,7 +9785,7 @@ typedef struct { /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (32U) -/*! @name RXIMR - Rx Individual Mask Registers */ +/*! @name RXIMR - Receive Individual Mask */ /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) @@ -9538,7 +9797,7 @@ typedef struct { /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (32U) -/*! @name CTRL1_PN - Pretended Networking Control 1 Register */ +/*! @name CTRL1_PN - Pretended Networking Control 1 */ /*! @{ */ #define CAN_CTRL1_PN_FCS_MASK (0x3U) @@ -9554,52 +9813,50 @@ typedef struct { #define CAN_CTRL1_PN_IDFS_MASK (0xCU) #define CAN_CTRL1_PN_IDFS_SHIFT (2U) /*! IDFS - ID Filtering Selection - * 0b00..Match upon ID contents against an exact target value - * 0b01..Match upon an ID value greater than or equal to a specified target value - * 0b10..Match upon an ID value smaller than or equal to a specified target value - * 0b11..Match upon an ID value inside a range, greater than or equal to a specified lower limit, and smaller - * than or equal to a specified upper limit + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive */ #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) #define CAN_CTRL1_PN_PLFS_MASK (0x30U) #define CAN_CTRL1_PN_PLFS_SHIFT (4U) /*! PLFS - Payload Filtering Selection - * 0b00..Match upon a payload contents against an exact target value - * 0b01..Match upon a payload value greater than or equal to a specified target value - * 0b10..Match upon a payload value smaller than or equal to a specified target value - * 0b11..Match upon a payload value inside a range, greater than or equal to a specified lower limit, and smaller - * than or equal to a specified upper limit + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive */ #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) #define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) #define CAN_CTRL1_PN_NMATCH_SHIFT (8U) /*! NMATCH - Number of Messages Matching the Same Filtering Criteria - * 0b00000001..Received message must match the predefined filtering criteria for ID and/or PL once before generating a wakeup event. - * 0b00000010..Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wakeup event. - * 0b11111111..Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wakeup event. + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times */ #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) #define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) #define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) -/*! WUMF_MSK - Wake Up by Match Flag Mask Bit - * 0b0..Wakeup match event is disabled - * 0b1..Wakeup match event is enabled +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) #define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) #define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) -/*! WTOF_MSK - Wake Up by Timeout Flag Mask Bit - * 0b0..Timeout wakeup event is disabled - * 0b1..Timeout wakeup event is enabled +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable */ #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) /*! @} */ -/*! @name CTRL2_PN - Pretended Networking Control 2 Register */ +/*! @name CTRL2_PN - Pretended Networking Control 2 */ /*! @{ */ #define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) @@ -9608,32 +9865,32 @@ typedef struct { #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) /*! @} */ -/*! @name WU_MTC - Pretended Networking Wake Up Match Register */ +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ /*! @{ */ #define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) #define CAN_WU_MTC_MCOUNTER_SHIFT (8U) -/*! MCOUNTER - Number of Matches when in Pretended Networking */ +/*! MCOUNTER - Number of Matches in Pretended Networking */ #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) #define CAN_WU_MTC_WUMF_MASK (0x10000U) #define CAN_WU_MTC_WUMF_SHIFT (16U) -/*! WUMF - Wake Up by Match Flag Bit - * 0b0..No wakeup by match event detected - * 0b1..Wakeup by match event detected +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected */ #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) #define CAN_WU_MTC_WTOF_MASK (0x20000U) #define CAN_WU_MTC_WTOF_SHIFT (17U) -/*! WTOF - Wake Up by Timeout Flag Bit - * 0b0..No wakeup by timeout event detected - * 0b1..Wakeup by timeout event detected +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected */ #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) /*! @} */ -/*! @name FLT_ID1 - Pretended Networking ID Filter 1 Register */ +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ /*! @{ */ #define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) @@ -9652,13 +9909,13 @@ typedef struct { #define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) #define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) /*! FLT_IDE - ID Extended Filter - * 0b0..Accept standard frame format - * 0b1..Accept extended frame format + * 0b0..Standard + * 0b1..Extended */ #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) /*! @} */ -/*! @name FLT_DLC - Pretended Networking DLC Filter Register */ +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ /*! @{ */ #define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) @@ -9672,144 +9929,128 @@ typedef struct { #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) /*! @} */ -/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 Register */ +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ /*! @{ */ #define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) #define CAN_PL1_LO_Data_byte_3_SHIFT (0U) -/*! Data_byte_3 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 3. */ +/*! Data_byte_3 - Data byte 3 */ #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) #define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) #define CAN_PL1_LO_Data_byte_2_SHIFT (8U) -/*! Data_byte_2 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2. */ +/*! Data_byte_2 - Data byte 2 */ #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) #define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) #define CAN_PL1_LO_Data_byte_1_SHIFT (16U) -/*! Data_byte_1 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 1. */ +/*! Data_byte_1 - Data byte 1 */ #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) #define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) #define CAN_PL1_LO_Data_byte_0_SHIFT (24U) -/*! Data_byte_0 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 0. */ +/*! Data_byte_0 - Data byte 0 */ #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) /*! @} */ -/*! @name PL1_HI - Pretended Networking Payload High Filter 1 Register */ +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ /*! @{ */ #define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) #define CAN_PL1_HI_Data_byte_7_SHIFT (0U) -/*! Data_byte_7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 7. */ +/*! Data_byte_7 - Data byte 7 */ #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) #define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) #define CAN_PL1_HI_Data_byte_6_SHIFT (8U) -/*! Data_byte_6 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 6. */ +/*! Data_byte_6 - Data byte 6 */ #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) #define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) #define CAN_PL1_HI_Data_byte_5_SHIFT (16U) -/*! Data_byte_5 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 5. */ +/*! Data_byte_5 - Data byte 5 */ #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) #define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) #define CAN_PL1_HI_Data_byte_4_SHIFT (24U) -/*! Data_byte_4 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 4. */ +/*! Data_byte_4 - Data byte 4 */ #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) /*! @} */ -/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 Register / ID Mask Register */ +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ /*! @{ */ #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) -/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering */ +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) -/*! RTR_MSK - Remote Transmission Request Mask Bit - * 0b0..The corresponding bit in the filter is "don't care" - * 0b1..The corresponding bit in the filter is checked +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. */ #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) -/*! IDE_MSK - ID Extended Mask Bit - * 0b0..The corresponding bit in the filter is "don't care" - * 0b1..The corresponding bit in the filter is checked +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. */ #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) /*! @} */ -/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register */ +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ /*! @{ */ #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) -/*! Data_byte_3 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 3. - */ +/*! Data_byte_3 - Data Byte 3 */ #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) -/*! Data_byte_2 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 2. - */ +/*! Data_byte_2 - Data Byte 2 */ #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) -/*! Data_byte_1 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 1. - */ +/*! Data_byte_1 - Data Byte 1 */ #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) -/*! Data_byte_0 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended - * Networking payload filtering corresponding to the data byte 0. - */ +/*! Data_byte_0 - Data Byte 0 */ #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) /*! @} */ -/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */ +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ /*! @{ */ #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) -/*! Data_byte_7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 7. - */ +/*! Data_byte_7 - Data Byte 7 */ #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) -/*! Data_byte_6 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 6. - */ +/*! Data_byte_6 - Data Byte 6 */ #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) -/*! Data_byte_5 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 5. - */ +/*! Data_byte_5 - Data Byte 5 */ #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) -/*! Data_byte_4 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended - * Networking payload filtering corresponding to the data byte 4. - */ +/*! Data_byte_4 - Data Byte 4 */ #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) /*! @} */ -/*! @name WMB_CS - Wake Up Message Buffer register for C/S */ +/*! @name WMB_CS - Wake-Up Message Buffer */ /*! @{ */ #define CAN_WMB_CS_DLC_MASK (0xF0000U) @@ -9819,89 +10060,92 @@ typedef struct { #define CAN_WMB_CS_RTR_MASK (0x100000U) #define CAN_WMB_CS_RTR_SHIFT (20U) -/*! RTR - Remote Transmission Request Bit - * 0b0..Frame is data one (not remote) - * 0b1..Frame is a remote one +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote */ #define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) #define CAN_WMB_CS_IDE_MASK (0x200000U) #define CAN_WMB_CS_IDE_SHIFT (21U) /*! IDE - ID Extended Bit - * 0b0..Frame format is standard - * 0b1..Frame format is extended + * 0b0..Standard + * 0b1..Extended */ #define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) #define CAN_WMB_CS_SRR_MASK (0x400000U) #define CAN_WMB_CS_SRR_SHIFT (22U) -/*! SRR - Substitute Remote Request */ +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ #define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) /*! @} */ /* The count of CAN_WMB_CS */ #define CAN_WMB_CS_COUNT (4U) -/*! @name WMB_ID - Wake Up Message Buffer Register for ID */ +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ /*! @{ */ #define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) #define CAN_WMB_ID_ID_SHIFT (0U) -/*! ID - Received ID under Pretended Networking mode */ +/*! ID - Received ID in Pretended Networking Mode */ #define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) /*! @} */ /* The count of CAN_WMB_ID */ #define CAN_WMB_ID_COUNT (4U) -/*! @name WMB_D03 - Wake Up Message Buffer Register for Data 0-3 */ +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ /*! @{ */ #define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) #define CAN_WMB_D03_Data_byte_3_SHIFT (0U) -/*! Data_byte_3 - Received payload corresponding to the data byte 3 under Pretended Networking mode */ +/*! Data_byte_3 - Data Byte 3 */ #define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) #define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) #define CAN_WMB_D03_Data_byte_2_SHIFT (8U) -/*! Data_byte_2 - Received payload corresponding to the data byte 2 under Pretended Networking mode */ +/*! Data_byte_2 - Data Byte 2 */ #define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) #define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) #define CAN_WMB_D03_Data_byte_1_SHIFT (16U) -/*! Data_byte_1 - Received payload corresponding to the data byte 1 under Pretended Networking mode */ +/*! Data_byte_1 - Data Byte 1 */ #define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) #define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) #define CAN_WMB_D03_Data_byte_0_SHIFT (24U) -/*! Data_byte_0 - Received payload corresponding to the data byte 0 under Pretended Networking mode */ +/*! Data_byte_0 - Data Byte 0 */ #define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) /*! @} */ /* The count of CAN_WMB_D03 */ #define CAN_WMB_D03_COUNT (4U) -/*! @name WMB_D47 - Wake Up Message Buffer Register Data 4-7 */ +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ /*! @{ */ #define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) #define CAN_WMB_D47_Data_byte_7_SHIFT (0U) -/*! Data_byte_7 - Received payload corresponding to the data byte 7 under Pretended Networking mode */ +/*! Data_byte_7 - Data Byte 7 */ #define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) #define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) #define CAN_WMB_D47_Data_byte_6_SHIFT (8U) -/*! Data_byte_6 - Received payload corresponding to the data byte 6 under Pretended Networking mode */ +/*! Data_byte_6 - Data Byte 6 */ #define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) #define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) #define CAN_WMB_D47_Data_byte_5_SHIFT (16U) -/*! Data_byte_5 - Received payload corresponding to the data byte 5 under Pretended Networking mode */ +/*! Data_byte_5 - Data Byte 5 */ #define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) #define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) #define CAN_WMB_D47_Data_byte_4_SHIFT (24U) -/*! Data_byte_4 - Received payload corresponding to the data byte 4 under Pretended Networking mode */ +/*! Data_byte_4 - Data Byte 4 */ #define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) /*! @} */ @@ -9941,7 +10185,7 @@ typedef struct { #define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) /*! @} */ -/*! @name EDCBT - Enhanced Data Phase CAN bit Timing */ +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ /*! @{ */ #define CAN_EDCBT_DTSEG1_MASK (0x1FU) @@ -9971,8 +10215,8 @@ typedef struct { #define CAN_ETDC_ETDCFAIL_MASK (0x8000U) #define CAN_ETDC_ETDCFAIL_SHIFT (15U) /*! ETDCFAIL - Transceiver Delay Compensation Fail - * 0b0..Measured loop delay is in range. - * 0b1..Measured loop delay is out of range. + * 0b0..In range + * 0b1..Out of range */ #define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) @@ -9984,21 +10228,21 @@ typedef struct { #define CAN_ETDC_TDMDIS_MASK (0x40000000U) #define CAN_ETDC_TDMDIS_SHIFT (30U) /*! TDMDIS - Transceiver Delay Measurement Disable - * 0b0..TDC measurement is enabled - * 0b1..TDC measurement is disabled + * 0b0..Enable + * 0b1..Disable */ #define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) #define CAN_ETDC_ETDCEN_MASK (0x80000000U) #define CAN_ETDC_ETDCEN_SHIFT (31U) /*! ETDCEN - Transceiver Delay Compensation Enable - * 0b0..TDC is disabled - * 0b1..TDC is enabled + * 0b0..Disable + * 0b1..Enable */ #define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) /*! @} */ -/*! @name FDCTRL - CAN FD Control Register */ +/*! @name FDCTRL - CAN FD Control */ /*! @{ */ #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) @@ -10014,39 +10258,39 @@ typedef struct { #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail - * 0b0..Measured loop delay is in range. - * 0b1..Measured loop delay is out of range. + * 0b0..In range + * 0b1..Out of range */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable - * 0b0..TDC is disabled - * 0b1..TDC is enabled + * 0b0..Disable + * 0b1..Enable */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 - * 0b00..Selects 8 bytes per message buffer. - * 0b01..Selects 16 bytes per message buffer. - * 0b10..Selects 32 bytes per message buffer. - * 0b11..Selects 64 bytes per message buffer. + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable - * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. - * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. + * 0b0..Disable + * 0b1..Enable */ #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) /*! @} */ -/*! @name FDCBT - CAN FD Bit Timing Register */ +/*! @name FDCBT - CAN FD Bit Timing */ /*! @{ */ #define CAN_FDCBT_FPSEG2_MASK (0x7U) @@ -10075,7 +10319,7 @@ typedef struct { #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) /*! @} */ -/*! @name FDCRC - CAN FD CRC Register */ +/*! @name FDCRC - CAN FD CRC */ /*! @{ */ #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) @@ -10085,21 +10329,21 @@ typedef struct { #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) -/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC */ +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /*! @} */ -/*! @name ERFCR - Enhanced Rx FIFO Control Register */ +/*! @name ERFCR - Enhanced RX FIFO Control */ /*! @{ */ #define CAN_ERFCR_ERFWM_MASK (0x1FU) #define CAN_ERFCR_ERFWM_SHIFT (0U) -/*! ERFWM - Enhanced Rx FIFO Watermark */ +/*! ERFWM - Enhanced RX FIFO Watermark */ #define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) #define CAN_ERFCR_NFE_MASK (0x3F00U) #define CAN_ERFCR_NFE_SHIFT (8U) -/*! NFE - Number of Enhanced Rx FIFO Filter Elements */ +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ #define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) #define CAN_ERFCR_NEXIF_MASK (0x7F0000U) @@ -10114,115 +10358,115 @@ typedef struct { #define CAN_ERFCR_ERFEN_MASK (0x80000000U) #define CAN_ERFCR_ERFEN_SHIFT (31U) -/*! ERFEN - Enhanced Rx FIFO enable - * 0b0..Enhanced Rx FIFO is disabled - * 0b1..Enhanced Rx FIFO is enabled +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) /*! @} */ -/*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */ +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ /*! @{ */ #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) #define CAN_ERFIER_ERFDAIE_SHIFT (28U) -/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable - * 0b0..Enhanced Rx FIFO Data Available interrupt is disabled - * 0b1..Enhanced Rx FIFO Data Available interrupt is enabled +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) #define CAN_ERFIER_ERFWMIIE_SHIFT (29U) -/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable - * 0b0..Enhanced Rx FIFO Watermark interrupt is disabled - * 0b1..Enhanced Rx FIFO Watermark interrupt is enabled +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) #define CAN_ERFIER_ERFOVFIE_SHIFT (30U) -/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable - * 0b0..Enhanced Rx FIFO Overflow is disabled - * 0b1..Enhanced Rx FIFO Overflow is enabled +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) #define CAN_ERFIER_ERFUFWIE_SHIFT (31U) -/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable - * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled - * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) /*! @} */ -/*! @name ERFSR - Enhanced Rx FIFO Status Register */ +/*! @name ERFSR - Enhanced RX FIFO Status */ /*! @{ */ #define CAN_ERFSR_ERFEL_MASK (0x3FU) #define CAN_ERFSR_ERFEL_SHIFT (0U) -/*! ERFEL - Enhanced Rx FIFO Elements */ +/*! ERFEL - Enhanced RX FIFO Elements */ #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) #define CAN_ERFSR_ERFF_MASK (0x10000U) #define CAN_ERFSR_ERFF_SHIFT (16U) -/*! ERFF - Enhanced Rx FIFO full - * 0b0..Enhanced Rx FIFO is not full - * 0b1..Enhanced Rx FIFO is full +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full */ #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) #define CAN_ERFSR_ERFE_MASK (0x20000U) #define CAN_ERFSR_ERFE_SHIFT (17U) -/*! ERFE - Enhanced Rx FIFO empty - * 0b0..Enhanced Rx FIFO is not empty - * 0b1..Enhanced Rx FIFO is empty +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty */ #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) #define CAN_ERFSR_ERFCLR_MASK (0x8000000U) #define CAN_ERFSR_ERFCLR_SHIFT (27U) -/*! ERFCLR - Enhanced Rx FIFO Clear +/*! ERFCLR - Enhanced RX FIFO Clear * 0b0..No effect - * 0b1..Clear Enhanced Rx FIFO content + * 0b1..Clear enhanced RX FIFO content */ #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) #define CAN_ERFSR_ERFDA_MASK (0x10000000U) #define CAN_ERFSR_ERFDA_SHIFT (28U) -/*! ERFDA - Enhanced Rx FIFO Data Available +/*! ERFDA - Enhanced RX FIFO Data Available Flag * 0b0..No such occurrence - * 0b1..There is at least one message stored in Enhanced Rx FIFO + * 0b1..At least one message stored in Enhanced RX FIFO */ #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) #define CAN_ERFSR_ERFWMI_SHIFT (29U) -/*! ERFWMI - Enhanced Rx FIFO Watermark Indication +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag * 0b0..No such occurrence - * 0b1..The number of messages in FIFO is greater than the watermark + * 0b1..Number of messages in FIFO is greater than the watermark */ #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) #define CAN_ERFSR_ERFOVF_MASK (0x40000000U) #define CAN_ERFSR_ERFOVF_SHIFT (30U) -/*! ERFOVF - Enhanced Rx FIFO Overflow +/*! ERFOVF - Enhanced RX FIFO Overflow Flag * 0b0..No such occurrence - * 0b1..Enhanced Rx FIFO overflow + * 0b1..Overflow */ #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) #define CAN_ERFSR_ERFUFW_MASK (0x80000000U) #define CAN_ERFSR_ERFUFW_SHIFT (31U) -/*! ERFUFW - Enhanced Rx FIFO Underflow +/*! ERFUFW - Enhanced RX FIFO Underflow Flag * 0b0..No such occurrence - * 0b1..Enhanced Rx FIFO underflow + * 0b1..Underflow */ #define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) /*! @} */ -/*! @name ERFFEL - Enhanced Rx FIFO Filter Element */ +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ /*! @{ */ #define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) @@ -10736,7 +10980,7 @@ typedef struct { uint8_t RESERVED_6[12]; __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ uint8_t RESERVED_7[28]; - __IO uint32_t BSR; /**< BootROM Status, offset: 0x100 */ + __IO uint32_t BSR; /**< BootROM Status Register, offset: 0x100 */ uint8_t RESERVED_8[8]; __IO uint32_t BLR; /**< BootROM Lock Register, offset: 0x10C */ __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ @@ -10779,6 +11023,7 @@ typedef struct { #define CMC_CKCTRL_CKMODE_SHIFT (0U) /*! CKMODE - Clocking Mode * 0b0000..No clock gating + * 0b0001..Core clock is gated * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. */ #define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) @@ -10799,6 +11044,7 @@ typedef struct { #define CMC_CKSTAT_CKMODE_SHIFT (0U) /*! CKMODE - Low Power Status * 0b0000..Core clock not gated + * 0b0001..Core clock was gated * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode * *.. */ @@ -11479,10 +11725,261 @@ typedef struct { /*! @name SRAMDIS - SRAM Disable */ /*! @{ */ -#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) -#define CMC_SRAMDIS_DIS_SHIFT (0U) -/*! DIS - SRAM Disable */ -#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) +#define CMC_SRAMDIS_DIS0_MASK (0x1U) +#define CMC_SRAMDIS_DIS0_SHIFT (0U) +/*! DIS0 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK) + +#define CMC_SRAMDIS_DIS1_MASK (0x2U) +#define CMC_SRAMDIS_DIS1_SHIFT (1U) +/*! DIS1 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK) + +#define CMC_SRAMDIS_DIS2_MASK (0x4U) +#define CMC_SRAMDIS_DIS2_SHIFT (2U) +/*! DIS2 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK) + +#define CMC_SRAMDIS_DIS3_MASK (0x8U) +#define CMC_SRAMDIS_DIS3_SHIFT (3U) +/*! DIS3 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK) + +#define CMC_SRAMDIS_DIS4_MASK (0x10U) +#define CMC_SRAMDIS_DIS4_SHIFT (4U) +/*! DIS4 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK) + +#define CMC_SRAMDIS_DIS5_MASK (0x20U) +#define CMC_SRAMDIS_DIS5_SHIFT (5U) +/*! DIS5 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK) + +#define CMC_SRAMDIS_DIS6_MASK (0x40U) +#define CMC_SRAMDIS_DIS6_SHIFT (6U) +/*! DIS6 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK) + +#define CMC_SRAMDIS_DIS7_MASK (0x80U) +#define CMC_SRAMDIS_DIS7_SHIFT (7U) +/*! DIS7 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK) + +#define CMC_SRAMDIS_DIS8_MASK (0x100U) +#define CMC_SRAMDIS_DIS8_SHIFT (8U) +/*! DIS8 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK) + +#define CMC_SRAMDIS_DIS9_MASK (0x200U) +#define CMC_SRAMDIS_DIS9_SHIFT (9U) +/*! DIS9 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK) + +#define CMC_SRAMDIS_DIS10_MASK (0x400U) +#define CMC_SRAMDIS_DIS10_SHIFT (10U) +/*! DIS10 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK) + +#define CMC_SRAMDIS_DIS11_MASK (0x800U) +#define CMC_SRAMDIS_DIS11_SHIFT (11U) +/*! DIS11 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK) + +#define CMC_SRAMDIS_DIS12_MASK (0x1000U) +#define CMC_SRAMDIS_DIS12_SHIFT (12U) +/*! DIS12 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK) + +#define CMC_SRAMDIS_DIS13_MASK (0x2000U) +#define CMC_SRAMDIS_DIS13_SHIFT (13U) +/*! DIS13 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK) + +#define CMC_SRAMDIS_DIS14_MASK (0x4000U) +#define CMC_SRAMDIS_DIS14_SHIFT (14U) +/*! DIS14 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK) + +#define CMC_SRAMDIS_DIS15_MASK (0x8000U) +#define CMC_SRAMDIS_DIS15_SHIFT (15U) +/*! DIS15 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK) + +#define CMC_SRAMDIS_DIS16_MASK (0x10000U) +#define CMC_SRAMDIS_DIS16_SHIFT (16U) +/*! DIS16 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK) + +#define CMC_SRAMDIS_DIS17_MASK (0x20000U) +#define CMC_SRAMDIS_DIS17_SHIFT (17U) +/*! DIS17 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK) + +#define CMC_SRAMDIS_DIS18_MASK (0x40000U) +#define CMC_SRAMDIS_DIS18_SHIFT (18U) +/*! DIS18 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK) + +#define CMC_SRAMDIS_DIS19_MASK (0x80000U) +#define CMC_SRAMDIS_DIS19_SHIFT (19U) +/*! DIS19 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK) + +#define CMC_SRAMDIS_DIS20_MASK (0x100000U) +#define CMC_SRAMDIS_DIS20_SHIFT (20U) +/*! DIS20 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK) + +#define CMC_SRAMDIS_DIS21_MASK (0x200000U) +#define CMC_SRAMDIS_DIS21_SHIFT (21U) +/*! DIS21 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK) + +#define CMC_SRAMDIS_DIS22_MASK (0x400000U) +#define CMC_SRAMDIS_DIS22_SHIFT (22U) +/*! DIS22 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK) + +#define CMC_SRAMDIS_DIS23_MASK (0x800000U) +#define CMC_SRAMDIS_DIS23_SHIFT (23U) +/*! DIS23 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK) + +#define CMC_SRAMDIS_DIS24_MASK (0x1000000U) +#define CMC_SRAMDIS_DIS24_SHIFT (24U) +/*! DIS24 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK) + +#define CMC_SRAMDIS_DIS25_MASK (0x2000000U) +#define CMC_SRAMDIS_DIS25_SHIFT (25U) +/*! DIS25 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK) + +#define CMC_SRAMDIS_DIS26_MASK (0x4000000U) +#define CMC_SRAMDIS_DIS26_SHIFT (26U) +/*! DIS26 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK) + +#define CMC_SRAMDIS_DIS27_MASK (0x8000000U) +#define CMC_SRAMDIS_DIS27_SHIFT (27U) +/*! DIS27 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK) + +#define CMC_SRAMDIS_DIS28_MASK (0x10000000U) +#define CMC_SRAMDIS_DIS28_SHIFT (28U) +/*! DIS28 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK) + +#define CMC_SRAMDIS_DIS29_MASK (0x20000000U) +#define CMC_SRAMDIS_DIS29_SHIFT (29U) +/*! DIS29 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK) + +#define CMC_SRAMDIS_DIS30_MASK (0x40000000U) +#define CMC_SRAMDIS_DIS30_SHIFT (30U) +/*! DIS30 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK) + +#define CMC_SRAMDIS_DIS31_MASK (0x80000000U) +#define CMC_SRAMDIS_DIS31_SHIFT (31U) +/*! DIS31 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK) /*! @} */ /* The count of CMC_SRAMDIS */ @@ -11491,10 +11988,261 @@ typedef struct { /*! @name SRAMRET - SRAM Retention */ /*! @{ */ -#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) -#define CMC_SRAMRET_RET_SHIFT (0U) -/*! RET - SRAM Retention */ -#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) +#define CMC_SRAMRET_RET0_MASK (0x1U) +#define CMC_SRAMRET_RET0_SHIFT (0U) +/*! RET0 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK) + +#define CMC_SRAMRET_RET1_MASK (0x2U) +#define CMC_SRAMRET_RET1_SHIFT (1U) +/*! RET1 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK) + +#define CMC_SRAMRET_RET2_MASK (0x4U) +#define CMC_SRAMRET_RET2_SHIFT (2U) +/*! RET2 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK) + +#define CMC_SRAMRET_RET3_MASK (0x8U) +#define CMC_SRAMRET_RET3_SHIFT (3U) +/*! RET3 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK) + +#define CMC_SRAMRET_RET4_MASK (0x10U) +#define CMC_SRAMRET_RET4_SHIFT (4U) +/*! RET4 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK) + +#define CMC_SRAMRET_RET5_MASK (0x20U) +#define CMC_SRAMRET_RET5_SHIFT (5U) +/*! RET5 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK) + +#define CMC_SRAMRET_RET6_MASK (0x40U) +#define CMC_SRAMRET_RET6_SHIFT (6U) +/*! RET6 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK) + +#define CMC_SRAMRET_RET7_MASK (0x80U) +#define CMC_SRAMRET_RET7_SHIFT (7U) +/*! RET7 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK) + +#define CMC_SRAMRET_RET8_MASK (0x100U) +#define CMC_SRAMRET_RET8_SHIFT (8U) +/*! RET8 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK) + +#define CMC_SRAMRET_RET9_MASK (0x200U) +#define CMC_SRAMRET_RET9_SHIFT (9U) +/*! RET9 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK) + +#define CMC_SRAMRET_RET10_MASK (0x400U) +#define CMC_SRAMRET_RET10_SHIFT (10U) +/*! RET10 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK) + +#define CMC_SRAMRET_RET11_MASK (0x800U) +#define CMC_SRAMRET_RET11_SHIFT (11U) +/*! RET11 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK) + +#define CMC_SRAMRET_RET12_MASK (0x1000U) +#define CMC_SRAMRET_RET12_SHIFT (12U) +/*! RET12 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK) + +#define CMC_SRAMRET_RET13_MASK (0x2000U) +#define CMC_SRAMRET_RET13_SHIFT (13U) +/*! RET13 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK) + +#define CMC_SRAMRET_RET14_MASK (0x4000U) +#define CMC_SRAMRET_RET14_SHIFT (14U) +/*! RET14 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK) + +#define CMC_SRAMRET_RET15_MASK (0x8000U) +#define CMC_SRAMRET_RET15_SHIFT (15U) +/*! RET15 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK) + +#define CMC_SRAMRET_RET16_MASK (0x10000U) +#define CMC_SRAMRET_RET16_SHIFT (16U) +/*! RET16 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK) + +#define CMC_SRAMRET_RET17_MASK (0x20000U) +#define CMC_SRAMRET_RET17_SHIFT (17U) +/*! RET17 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK) + +#define CMC_SRAMRET_RET18_MASK (0x40000U) +#define CMC_SRAMRET_RET18_SHIFT (18U) +/*! RET18 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK) + +#define CMC_SRAMRET_RET19_MASK (0x80000U) +#define CMC_SRAMRET_RET19_SHIFT (19U) +/*! RET19 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK) + +#define CMC_SRAMRET_RET20_MASK (0x100000U) +#define CMC_SRAMRET_RET20_SHIFT (20U) +/*! RET20 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK) + +#define CMC_SRAMRET_RET21_MASK (0x200000U) +#define CMC_SRAMRET_RET21_SHIFT (21U) +/*! RET21 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK) + +#define CMC_SRAMRET_RET22_MASK (0x400000U) +#define CMC_SRAMRET_RET22_SHIFT (22U) +/*! RET22 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK) + +#define CMC_SRAMRET_RET23_MASK (0x800000U) +#define CMC_SRAMRET_RET23_SHIFT (23U) +/*! RET23 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK) + +#define CMC_SRAMRET_RET24_MASK (0x1000000U) +#define CMC_SRAMRET_RET24_SHIFT (24U) +/*! RET24 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK) + +#define CMC_SRAMRET_RET25_MASK (0x2000000U) +#define CMC_SRAMRET_RET25_SHIFT (25U) +/*! RET25 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK) + +#define CMC_SRAMRET_RET26_MASK (0x4000000U) +#define CMC_SRAMRET_RET26_SHIFT (26U) +/*! RET26 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK) + +#define CMC_SRAMRET_RET27_MASK (0x8000000U) +#define CMC_SRAMRET_RET27_SHIFT (27U) +/*! RET27 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK) + +#define CMC_SRAMRET_RET28_MASK (0x10000000U) +#define CMC_SRAMRET_RET28_SHIFT (28U) +/*! RET28 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK) + +#define CMC_SRAMRET_RET29_MASK (0x20000000U) +#define CMC_SRAMRET_RET29_SHIFT (29U) +/*! RET29 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK) + +#define CMC_SRAMRET_RET30_MASK (0x40000000U) +#define CMC_SRAMRET_RET30_SHIFT (30U) +/*! RET30 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK) + +#define CMC_SRAMRET_RET31_MASK (0x80000000U) +#define CMC_SRAMRET_RET31_SHIFT (31U) +/*! RET31 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK) /*! @} */ /* The count of CMC_SRAMRET */ @@ -11518,17 +12266,9 @@ typedef struct { * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) */ #define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) - -#define CMC_FLASHCR_FLASHWAKE_MASK (0x4U) -#define CMC_FLASHCR_FLASHWAKE_SHIFT (2U) -/*! FLASHWAKE - Flash Wake - * 0b0..No effect - * 0b1..Flash memory is not disabled during flash memory accesses - */ -#define CMC_FLASHCR_FLASHWAKE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK) /*! @} */ -/*! @name BSR - BootROM Status */ +/*! @name BSR - BootROM Status Register */ /*! @{ */ #define CMC_BSR_STAT_MASK (0xFFFFFFFFU) @@ -11607,13 +12347,16 @@ typedef struct { /** Array initializer of CMC peripheral base pointers */ #define CMC_BASE_PTRS { CMC0 } #endif -/* Backward compatibility */ -#define CMC_SRIE_WDOG0_MASK CMC_SRIE_WWDT0_MASK -#define CMC_SRIE_WDOG1_MASK CMC_SRIE_WWDT1_MASK -#define CMC_SRIF_WDOG0_MASK CMC_SRIF_WWDT0_MASK -#define CMC_SRIF_WDOG1_MASK CMC_SRIF_WWDT1_MASK -#define CMC_SRS_WDOG0_MASK CMC_SRS_WWDT0_MASK -#define CMC_SRS_WDOG1_MASK CMC_SRS_WWDT1_MASK +/* Backward compatibility for CMC */ +#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) +#define CMC_SRAMDIS_DIS_SHIFT (0U) +/*! DIS - SRAM Disable */ +#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) + +#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) +#define CMC_SRAMRET_RET_SHIFT (0U) +/*! RET - SRAM Retention */ +#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) /*! @@ -11643,7 +12386,7 @@ typedef struct { __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ } ACCESS16BIT; - __IO uint32_t DATA; /**< CRC Data, offset: 0x0 */ + __IO uint32_t DATA; /**< Data, offset: 0x0 */ }; union { /* offset: 0x4 */ struct { /* offset: 0x4 */ @@ -11656,14 +12399,14 @@ typedef struct { __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ } GPOLY_ACCESS16BIT; - __IO uint32_t GPOLY; /**< CRC Polynomial, offset: 0x4 */ + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ }; union { /* offset: 0x8 */ struct { /* offset: 0x8 */ uint8_t RESERVED_0[3]; __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ } CTRL_ACCESS8BIT; - __IO uint32_t CTRL; /**< CRC Control, offset: 0x8 */ + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ }; } CRC_Type; @@ -11724,27 +12467,27 @@ typedef struct { #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) /*! @} */ -/*! @name DATA - CRC Data */ +/*! @name DATA - Data */ /*! @{ */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) -/*! LL - CRC Low Lower Byte */ +/*! LL - Lower Part of Low Byte */ #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) #define CRC_DATA_LU_MASK (0xFF00U) #define CRC_DATA_LU_SHIFT (8U) -/*! LU - CRC Low Upper Byte */ +/*! LU - Upper Part of Low Byte */ #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) #define CRC_DATA_HL_MASK (0xFF0000U) #define CRC_DATA_HL_SHIFT (16U) -/*! HL - CRC High Lower Byte */ +/*! HL - Lower Part of High Byte */ #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) -/*! HU - CRC High Upper Byte */ +/*! HU - Upper Part of High Byte */ #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) /*! @} */ @@ -11796,17 +12539,17 @@ typedef struct { #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) /*! @} */ -/*! @name GPOLY - CRC Polynomial */ +/*! @name GPOLY - Polynomial */ /*! @{ */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) -/*! LOW - Low Polynomial Half-Word */ +/*! LOW - Low Half-Word */ #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) -/*! HIGH - High Polynomial Half-Word */ +/*! HIGH - High Half-Word */ #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) /*! @} */ @@ -11816,8 +12559,8 @@ typedef struct { #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) /*! TCRC - TCRC - * 0b0..16-bit - * 0b1..32-bit + * 0b0..16 bits + * 0b1..32 bits */ #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) @@ -11832,8 +12575,8 @@ typedef struct { #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) /*! FXOR - Complement Read of CRC Data Register - * 0b0..No XOR on reading - * 0b1..Inverts or complements the read value of the CRC Data + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. */ #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) @@ -11841,31 +12584,31 @@ typedef struct { #define CRC_CTRLHU_TOTR_SHIFT (4U) /*! TOTR - Transpose Type for Read * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) -/*! TOT - Transpose Type for Writes +/*! TOT - Transpose Type for Write * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) /*! @} */ -/*! @name CTRL - CRC Control */ +/*! @name CTRL - Control */ /*! @{ */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) /*! TCRC - TCRC - * 0b0..16-bit - * 0b1..32-bit + * 0b0..16 bits + * 0b1..32 bits */ #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) @@ -11880,8 +12623,8 @@ typedef struct { #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) /*! FXOR - Complement Read of CRC Data Register - * 0b0..No XOR on reading - * 0b1..Inverts or complements the read value of the CRC Data + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. */ #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) @@ -11889,19 +12632,19 @@ typedef struct { #define CRC_CTRL_TOTR_SHIFT (28U) /*! TOTR - Transpose Type for Read * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) -/*! TOT - Transpose Type for Writes +/*! TOT - Transpose Type for Write * 0b00..No transposition - * 0b01..Bits in bytes are transposed; bytes are not transposed - * 0b10..Both bits in bytes and bytes are transposed - * 0b11..Only bytes are transposed; no bits in a byte are transposed + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. */ #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) /*! @} */ @@ -15936,651 +16679,6 @@ typedef struct { */ /* end of group EMVSIM_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- ENC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer - * @{ - */ - -/** ENC - Register Layout Typedef */ -typedef struct { - __IO uint16_t CTRL; /**< Control, offset: 0x0 */ - __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ - __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ - __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ - __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ - __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ - __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ - __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ - __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ - __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ - __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ - __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ - __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ - __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ - __IO uint16_t TST; /**< Test, offset: 0x1C */ - __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ - __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ - __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ - __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ - __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ - __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ - __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ - __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ - __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ - __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ - __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ -} ENC_Type; - -/* ---------------------------------------------------------------------------- - -- ENC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Register_Masks ENC Register Masks - * @{ - */ - -/*! @name CTRL - Control */ -/*! @{ */ - -#define ENC_CTRL_CMPIE_MASK (0x1U) -#define ENC_CTRL_CMPIE_SHIFT (0U) -/*! CMPIE - Compare Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) - -#define ENC_CTRL_CMPIRQ_MASK (0x2U) -#define ENC_CTRL_CMPIRQ_SHIFT (1U) -/*! CMPIRQ - Compare Interrupt Request - * 0b0..No match has occurred - * 0b1..COMP match has occurred - */ -#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) - -#define ENC_CTRL_WDE_MASK (0x4U) -#define ENC_CTRL_WDE_SHIFT (2U) -/*! WDE - Watchdog Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) - -#define ENC_CTRL_DIE_MASK (0x8U) -#define ENC_CTRL_DIE_SHIFT (3U) -/*! DIE - Watchdog Timeout Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) - -#define ENC_CTRL_DIRQ_MASK (0x10U) -#define ENC_CTRL_DIRQ_SHIFT (4U) -/*! DIRQ - Watchdog Timeout Interrupt Request - * 0b0..Not occurred - * 0b1..Occurred - */ -#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) - -#define ENC_CTRL_XNE_MASK (0x20U) -#define ENC_CTRL_XNE_SHIFT (5U) -/*! XNE - Select Positive and Negative Edge of INDEX and PRESET Pulse - * 0b0..Use positive edge - * 0b1..Use negative edge - */ -#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) - -#define ENC_CTRL_XIP_MASK (0x40U) -#define ENC_CTRL_XIP_SHIFT (6U) -/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS - * 0b0..Does not initialize - * 0b1..Initializes - */ -#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) - -#define ENC_CTRL_XIE_MASK (0x80U) -#define ENC_CTRL_XIE_SHIFT (7U) -/*! XIE - INDEX Pulse Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) - -#define ENC_CTRL_XIRQ_MASK (0x100U) -#define ENC_CTRL_XIRQ_SHIFT (8U) -/*! XIRQ - INDEX Pulse Interrupt Request - * 0b0..Not occurred - * 0b1..Occurred - */ -#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) - -#define ENC_CTRL_PH1_MASK (0x200U) -#define ENC_CTRL_PH1_SHIFT (9U) -/*! PH1 - Enable Signal Phase Count Mode - * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. - * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. - * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; - * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. - */ -#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) - -#define ENC_CTRL_REV_MASK (0x400U) -#define ENC_CTRL_REV_SHIFT (10U) -/*! REV - Enable Reverse Direction Counting - * 0b0..Counts normally - * 0b1..Counts in the reverse direction - */ -#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) - -#define ENC_CTRL_SWIP_MASK (0x800U) -#define ENC_CTRL_SWIP_SHIFT (11U) -/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS - * 0b0..No action - * 0b1..Initialize position counter - */ -#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) - -#define ENC_CTRL_HNE_MASK (0x1000U) -#define ENC_CTRL_HNE_SHIFT (12U) -/*! HNE - Use Negative Edge of HOME Input - * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS - * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS - */ -#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) - -#define ENC_CTRL_HIP_MASK (0x2000U) -#define ENC_CTRL_HIP_SHIFT (13U) -/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS - * 0b0..No action - * 0b1..HOME signal initializes the position counter - */ -#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) - -#define ENC_CTRL_HIE_MASK (0x4000U) -#define ENC_CTRL_HIE_SHIFT (14U) -/*! HIE - HOME Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) - -#define ENC_CTRL_HIRQ_MASK (0x8000U) -#define ENC_CTRL_HIRQ_SHIFT (15U) -/*! HIRQ - HOME Signal Transition Interrupt Request - * 0b0..Not occurred - * 0b1..Occurred - */ -#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) -/*! @} */ - -/*! @name FILT - Input Filter */ -/*! @{ */ - -#define ENC_FILT_FILT_PER_MASK (0xFFU) -#define ENC_FILT_FILT_PER_SHIFT (0U) -/*! FILT_PER - Input Filter Sample Period */ -#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) - -#define ENC_FILT_FILT_CNT_MASK (0x700U) -#define ENC_FILT_FILT_CNT_SHIFT (8U) -/*! FILT_CNT - Input Filter Sample Count */ -#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) - -#define ENC_FILT_FILT_PRSC_MASK (0xE000U) -#define ENC_FILT_FILT_PRSC_SHIFT (13U) -/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ -#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK) -/*! @} */ - -/*! @name WTR - Watchdog Timeout */ -/*! @{ */ - -#define ENC_WTR_WDOG_MASK (0xFFFFU) -#define ENC_WTR_WDOG_SHIFT (0U) -/*! WDOG - WDOG */ -#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) -/*! @} */ - -/*! @name POSD - Position Difference Counter */ -/*! @{ */ - -#define ENC_POSD_POSD_MASK (0xFFFFU) -#define ENC_POSD_POSD_SHIFT (0U) -/*! POSD - POSD */ -#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) -/*! @} */ - -/*! @name POSDH - Position Difference Hold */ -/*! @{ */ - -#define ENC_POSDH_POSDH_MASK (0xFFFFU) -#define ENC_POSDH_POSDH_SHIFT (0U) -/*! POSDH - POSDH */ -#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) -/*! @} */ - -/*! @name REV - Revolution Counter */ -/*! @{ */ - -#define ENC_REV_REV_MASK (0xFFFFU) -#define ENC_REV_REV_SHIFT (0U) -/*! REV - REV */ -#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) -/*! @} */ - -/*! @name REVH - Revolution Hold */ -/*! @{ */ - -#define ENC_REVH_REVH_MASK (0xFFFFU) -#define ENC_REVH_REVH_SHIFT (0U) -/*! REVH - REVH */ -#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) -/*! @} */ - -/*! @name UPOS - Upper Position Counter */ -/*! @{ */ - -#define ENC_UPOS_POS_MASK (0xFFFFU) -#define ENC_UPOS_POS_SHIFT (0U) -/*! POS - POS */ -#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) -/*! @} */ - -/*! @name LPOS - Lower Position Counter */ -/*! @{ */ - -#define ENC_LPOS_POS_MASK (0xFFFFU) -#define ENC_LPOS_POS_SHIFT (0U) -/*! POS - POS */ -#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) -/*! @} */ - -/*! @name UPOSH - Upper Position Hold */ -/*! @{ */ - -#define ENC_UPOSH_POSH_MASK (0xFFFFU) -#define ENC_UPOSH_POSH_SHIFT (0U) -/*! POSH - POSH */ -#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) -/*! @} */ - -/*! @name LPOSH - Lower Position Hold */ -/*! @{ */ - -#define ENC_LPOSH_POSH_MASK (0xFFFFU) -#define ENC_LPOSH_POSH_SHIFT (0U) -/*! POSH - POSH */ -#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) -/*! @} */ - -/*! @name UINIT - Upper Initialization */ -/*! @{ */ - -#define ENC_UINIT_INIT_MASK (0xFFFFU) -#define ENC_UINIT_INIT_SHIFT (0U) -/*! INIT - INIT */ -#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) -/*! @} */ - -/*! @name LINIT - Lower Initialization */ -/*! @{ */ - -#define ENC_LINIT_INIT_MASK (0xFFFFU) -#define ENC_LINIT_INIT_SHIFT (0U) -/*! INIT - INIT */ -#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) -/*! @} */ - -/*! @name IMR - Input Monitor */ -/*! @{ */ - -#define ENC_IMR_HOME_MASK (0x1U) -#define ENC_IMR_HOME_SHIFT (0U) -/*! HOME - HOME */ -#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) - -#define ENC_IMR_INDEX_MASK (0x2U) -#define ENC_IMR_INDEX_SHIFT (1U) -/*! INDEX - INDEX */ -#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) - -#define ENC_IMR_PHB_MASK (0x4U) -#define ENC_IMR_PHB_SHIFT (2U) -/*! PHB - PHB */ -#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) - -#define ENC_IMR_PHA_MASK (0x8U) -#define ENC_IMR_PHA_SHIFT (3U) -/*! PHA - PHA */ -#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) - -#define ENC_IMR_FHOM_MASK (0x10U) -#define ENC_IMR_FHOM_SHIFT (4U) -/*! FHOM - FHOM */ -#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) - -#define ENC_IMR_FIND_MASK (0x20U) -#define ENC_IMR_FIND_SHIFT (5U) -/*! FIND - FIND */ -#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) - -#define ENC_IMR_FPHB_MASK (0x40U) -#define ENC_IMR_FPHB_SHIFT (6U) -/*! FPHB - FPHB */ -#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) - -#define ENC_IMR_FPHA_MASK (0x80U) -#define ENC_IMR_FPHA_SHIFT (7U) -/*! FPHA - FPHA */ -#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) -/*! @} */ - -/*! @name TST - Test */ -/*! @{ */ - -#define ENC_TST_TEST_COUNT_MASK (0xFFU) -#define ENC_TST_TEST_COUNT_SHIFT (0U) -/*! TEST_COUNT - TEST_COUNT */ -#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) - -#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) -#define ENC_TST_TEST_PERIOD_SHIFT (8U) -/*! TEST_PERIOD - TEST_PERIOD */ -#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) - -#define ENC_TST_QDN_MASK (0x2000U) -#define ENC_TST_QDN_SHIFT (13U) -/*! QDN - Quadrature Decoder Negative Signal - * 0b0..Positive quadrature decoder signal - * 0b1..Negative quadrature decoder signal - */ -#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) - -#define ENC_TST_TCE_MASK (0x4000U) -#define ENC_TST_TCE_SHIFT (14U) -/*! TCE - Test Counter Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) - -#define ENC_TST_TEN_MASK (0x8000U) -#define ENC_TST_TEN_SHIFT (15U) -/*! TEN - Test Mode Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) -/*! @} */ - -/*! @name CTRL2 - Control 2 */ -/*! @{ */ - -#define ENC_CTRL2_UPDHLD_MASK (0x1U) -#define ENC_CTRL2_UPDHLD_SHIFT (0U) -/*! UPDHLD - Update Hold Registers - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) - -#define ENC_CTRL2_UPDPOS_MASK (0x2U) -#define ENC_CTRL2_UPDPOS_SHIFT (1U) -/*! UPDPOS - Update Position Registers - * 0b0..No action - * 0b1..Clear - */ -#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) - -#define ENC_CTRL2_MOD_MASK (0x4U) -#define ENC_CTRL2_MOD_SHIFT (2U) -/*! MOD - Enable Modulo Counting - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) - -#define ENC_CTRL2_DIR_MASK (0x8U) -#define ENC_CTRL2_DIR_SHIFT (3U) -/*! DIR - Count Direction Flag - * 0b0..Down direction - * 0b1..Up direction - */ -#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) - -#define ENC_CTRL2_RUIE_MASK (0x10U) -#define ENC_CTRL2_RUIE_SHIFT (4U) -/*! RUIE - Roll-under Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) - -#define ENC_CTRL2_RUIRQ_MASK (0x20U) -#define ENC_CTRL2_RUIRQ_SHIFT (5U) -/*! RUIRQ - Roll-under Interrupt Request - * 0b0..No roll-under has occurred - * 0b1..Roll-under has occurred - */ -#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) - -#define ENC_CTRL2_ROIE_MASK (0x40U) -#define ENC_CTRL2_ROIE_SHIFT (6U) -/*! ROIE - Roll-over Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) - -#define ENC_CTRL2_ROIRQ_MASK (0x80U) -#define ENC_CTRL2_ROIRQ_SHIFT (7U) -/*! ROIRQ - Roll-over Interrupt Request - * 0b0..Did not occur - * 0b1..Occurred - */ -#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) - -#define ENC_CTRL2_REVMOD_MASK (0x100U) -#define ENC_CTRL2_REVMOD_SHIFT (8U) -/*! REVMOD - Revolution Counter Modulus Enable - * 0b0..Use INDEX pulse - * 0b1..Use modulus counting roll-over or roll-under - */ -#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) - -#define ENC_CTRL2_OUTCTL_MASK (0x200U) -#define ENC_CTRL2_OUTCTL_SHIFT (9U) -/*! OUTCTL - Output Control - * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) - * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read - */ -#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) - -#define ENC_CTRL2_SABIE_MASK (0x400U) -#define ENC_CTRL2_SABIE_SHIFT (10U) -/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable - * 0b0..Disable - * 0b1..Enable - */ -#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) - -#define ENC_CTRL2_SABIRQ_MASK (0x800U) -#define ENC_CTRL2_SABIRQ_SHIFT (11U) -/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request - * 0b0..No simultaneous change has occurred - * 0b1..A simultaneous change has occurred - */ -#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) - -#define ENC_CTRL2_INITPOS_MASK (0x1000U) -#define ENC_CTRL2_INITPOS_SHIFT (12U) -/*! INITPOS - Initialize Position Registers - * 0b0..Don't initialize position counter - * 0b1..Initialize position counter - */ -#define ENC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_INITPOS_SHIFT)) & ENC_CTRL2_INITPOS_MASK) -/*! @} */ - -/*! @name UMOD - Upper Modulus */ -/*! @{ */ - -#define ENC_UMOD_MOD_MASK (0xFFFFU) -#define ENC_UMOD_MOD_SHIFT (0U) -/*! MOD - MOD */ -#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) -/*! @} */ - -/*! @name LMOD - Lower Modulus */ -/*! @{ */ - -#define ENC_LMOD_MOD_MASK (0xFFFFU) -#define ENC_LMOD_MOD_SHIFT (0U) -/*! MOD - MOD */ -#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) -/*! @} */ - -/*! @name UCOMP - Upper Position Compare */ -/*! @{ */ - -#define ENC_UCOMP_COMP_MASK (0xFFFFU) -#define ENC_UCOMP_COMP_SHIFT (0U) -/*! COMP - COMP */ -#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) -/*! @} */ - -/*! @name LCOMP - Lower Position Compare */ -/*! @{ */ - -#define ENC_LCOMP_COMP_MASK (0xFFFFU) -#define ENC_LCOMP_COMP_SHIFT (0U) -/*! COMP - COMP */ -#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) -/*! @} */ - -/*! @name LASTEDGE - Last Edge Time */ -/*! @{ */ - -#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) -#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U) -/*! LASTEDGE - Last Edge Time Counter */ -#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK) -/*! @} */ - -/*! @name LASTEDGEH - Last Edge Time Hold */ -/*! @{ */ - -#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) -#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U) -/*! LASTEDGEH - Last Edge Time Hold */ -#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK) -/*! @} */ - -/*! @name POSDPER - Position Difference Period Counter */ -/*! @{ */ - -#define ENC_POSDPER_POSDPER_MASK (0xFFFFU) -#define ENC_POSDPER_POSDPER_SHIFT (0U) -/*! POSDPER - Position difference period */ -#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK) -/*! @} */ - -/*! @name POSDPERBFR - Position Difference Period Buffer */ -/*! @{ */ - -#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) -#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U) -/*! POSDPERBFR - Position difference period buffer */ -#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK) -/*! @} */ - -/*! @name POSDPERH - Position Difference Period Hold */ -/*! @{ */ - -#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU) -#define ENC_POSDPERH_POSDPERH_SHIFT (0U) -/*! POSDPERH - Position difference period hold */ -#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK) -/*! @} */ - -/*! @name CTRL3 - Control 3 */ -/*! @{ */ - -#define ENC_CTRL3_PMEN_MASK (0x1U) -#define ENC_CTRL3_PMEN_SHIFT (0U) -/*! PMEN - Period Measurement Function Enable - * 0b0..Not used - * 0b1..Used - */ -#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK) - -#define ENC_CTRL3_PRSC_MASK (0xF0U) -#define ENC_CTRL3_PRSC_SHIFT (4U) -/*! PRSC - Prescaler */ -#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ENC_Register_Masks */ - - -/* ENC - Peripheral instance base addresses */ -#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral ENC0 base address */ - #define ENC0_BASE (0x500CF000u) - /** Peripheral ENC0 base address */ - #define ENC0_BASE_NS (0x400CF000u) - /** Peripheral ENC0 base pointer */ - #define ENC0 ((ENC_Type *)ENC0_BASE) - /** Peripheral ENC0 base pointer */ - #define ENC0_NS ((ENC_Type *)ENC0_BASE_NS) - /** Peripheral ENC1 base address */ - #define ENC1_BASE (0x500D1000u) - /** Peripheral ENC1 base address */ - #define ENC1_BASE_NS (0x400D1000u) - /** Peripheral ENC1 base pointer */ - #define ENC1 ((ENC_Type *)ENC1_BASE) - /** Peripheral ENC1 base pointer */ - #define ENC1_NS ((ENC_Type *)ENC1_BASE_NS) - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS { ENC0, ENC1 } - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS_NS { ENC0_BASE_NS, ENC1_BASE_NS } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS_NS { ENC0_NS, ENC1_NS } -#else - /** Peripheral ENC0 base address */ - #define ENC0_BASE (0x400CF000u) - /** Peripheral ENC0 base pointer */ - #define ENC0 ((ENC_Type *)ENC0_BASE) - /** Peripheral ENC1 base address */ - #define ENC1_BASE (0x400D1000u) - /** Peripheral ENC1 base pointer */ - #define ENC1 ((ENC_Type *)ENC1_BASE) - /** Array initializer of ENC peripheral base addresses */ - #define ENC_BASE_ADDRS { ENC0_BASE, ENC1_BASE } - /** Array initializer of ENC peripheral base pointers */ - #define ENC_BASE_PTRS { ENC0, ENC1 } -#endif -/** Interrupt vectors for the ENC peripheral type */ -#define ENC_COMPARE_IRQS { ENC0_COMPARE_IRQn, ENC1_COMPARE_IRQn } -#define ENC_HOME_IRQS { ENC0_HOME_IRQn, ENC1_HOME_IRQn } -#define ENC_WDOG_IRQS { ENC0_WDG_SAB_IRQn, ENC1_WDG_SAB_IRQn } -#define ENC_INDEX_IRQS { ENC0_IDX_IRQn, ENC1_IDX_IRQn } - -/*! - * @} - */ /* end of group ENC_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -16703,7 +16801,7 @@ typedef struct { __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 1 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */ __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 1 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_CONTROL2; /**< Channeli Receive Control..DMA Channel 1 Receive Control, array offset: 0x1130, array step: 0x80 */ - __IO uint32_t DMA_CHX_INT_EN; /**< The Channeli Interrupt Enable register enables the interrupts reported by the Status register...Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ + __IO uint32_t DMA_CHX_INT_EN; /**< Channeli Interrupt Enable..Channel 1 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 1 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 1 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ uint8_t RESERVED_3[4]; @@ -18732,8 +18830,8 @@ typedef struct { #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control - * 0b0..Timestamp Digital or Binary Rollover Control is disabled - * 0b1..Timestamp Digital or Binary Rollover Control is enabled + * 0b0..Timestamp Digital Rollover Control is disabled and Binary Rollover Control is enabled + * 0b1..Timestamp Digital Rollover Control is enabled and Binary Rollover Control is disabled */ #define ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) @@ -19920,7 +20018,7 @@ typedef struct { /* The count of ENET_DMA_CH_DMA_CHX_RX_CONTROL2 */ #define ENET_DMA_CH_DMA_CHX_RX_CONTROL2_COUNT (2U) -/*! @name DMA_CH_DMA_CHX_INT_EN - The Channeli Interrupt Enable register enables the interrupts reported by the Status register...Channel 1 Interrupt Enable */ +/*! @name DMA_CH_DMA_CHX_INT_EN - Channeli Interrupt Enable..Channel 1 Interrupt Enable */ /*! @{ */ #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) @@ -21677,66 +21775,66 @@ typedef struct { /** FLEXIO - Register Layout Typedef */ typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CTRL; /**< FLEXIO Control Register, offset: 0x8 */ - __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ - __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ - __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ - __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ - __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ uint8_t RESERVED_3[4]; - __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ uint8_t RESERVED_4[4]; - __IO uint32_t TRGSTAT; /**< Trigger Status Register, offset: 0x48 */ - __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable Register, offset: 0x4C */ - __IO uint32_t PINSTAT; /**< Pin Status Register, offset: 0x50 */ - __IO uint32_t PINIEN; /**< Pin Interrupt Enable Register, offset: 0x54 */ - __IO uint32_t PINREN; /**< Pin Rising Edge Enable Register, offset: 0x58 */ - __IO uint32_t PINFEN; /**< Pin Falling Edge Enable Register, offset: 0x5C */ - __IO uint32_t PINOUTD; /**< Pin Output Data Register, offset: 0x60 */ - __IO uint32_t PINOUTE; /**< Pin Output Enable Register, offset: 0x64 */ - __O uint32_t PINOUTDIS; /**< Pin Output Disable Register, offset: 0x68 */ - __O uint32_t PINOUTCLR; /**< Pin Output Clear Register, offset: 0x6C */ - __O uint32_t PINOUTSET; /**< Pin Output Set Register, offset: 0x70 */ - __O uint32_t PINOUTTOG; /**< Pin Output Toggle Register, offset: 0x74 */ + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ uint8_t RESERVED_5[8]; - __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_6[96]; - __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_7[224]; - __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_8[96]; - __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_9[96]; - __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_10[96]; - __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_11[96]; - __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_12[96]; - __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_13[96]; - __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ uint8_t RESERVED_14[352]; - __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ uint8_t RESERVED_15[96]; - __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Halfword Swapped Register, array offset: 0x700, array step: 0x4 */ + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ uint8_t RESERVED_16[96]; - __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ uint8_t RESERVED_17[96]; - __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */ + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_18[96]; - __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */ + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_19[96]; - __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer N Halfword Byte Swapped Register, array offset: 0x900, array step: 0x4 */ + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ } FLEXIO_Type; /* ---------------------------------------------------------------------------- @@ -21748,16 +21846,16 @@ typedef struct { * @{ */ -/*! @name VERID - Version ID Register */ +/*! @name VERID - Version ID */ /*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented. - * 0b0000000000000001..Supports state, logic, and parallel modes. - * 0b0000000000000010..Supports pin control registers. - * 0b0000000000000011..Supports state, logic, and parallel modes, plus pin control registers. + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) @@ -21772,7 +21870,7 @@ typedef struct { #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) /*! @} */ -/*! @name PARAM - Parameter Register */ +/*! @name PARAM - Parameter */ /*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) @@ -21796,51 +21894,51 @@ typedef struct { #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) /*! @} */ -/*! @name CTRL - FLEXIO Control Register */ +/*! @name CTRL - FLEXIO Control */ /*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FLEXIO Enable - * 0b0..FLEXIO module is disabled. - * 0b1..FLEXIO module is enabled. + * 0b0..Disable + * 0b1..Enable */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset - * 0b0..Software reset is disabled - * 0b1..Software reset is enabled. All FLEXIO registers except the Control Register are reset. + * 0b0..Disabled + * 0b1..Enabled */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access - * 0b0..Configures for normal register accesses to FLEXIO - * 0b1..Configures for fast register accesses to FLEXIO + * 0b0..Normal + * 0b1..Fast */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable - * 0b0..FLEXIO is disabled in Debug modes. - * 0b1..FLEXIO is enabled in Debug modes. + * 0b0..Disable + * 0b1..Enable */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable - * 0b0..FLEXIO enabled in Doze modes. - * 0b1..FLEXIO disabled in Doze modes. + * 0b0..Enable + * 0b1..Disable */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) /*! @} */ -/*! @name PIN - Pin State Register */ +/*! @name PIN - Pin State */ /*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) @@ -21849,30 +21947,45 @@ typedef struct { #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /*! @} */ -/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @name SHIFTSTAT - Shifter Status */ /*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) -/*! SSF - Shifter Status Flag */ +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ -/*! @name SHIFTERR - Shifter Error Register */ +/*! @name SHIFTERR - Shifter Error */ /*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) -/*! SEF - Shifter Error Flags */ +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ -/*! @name TIMSTAT - Timer Status Register */ +/*! @name TIMSTAT - Timer Status Flag */ /*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) -/*! TSF - Timer Status Flags */ +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ @@ -21894,7 +22007,7 @@ typedef struct { #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) /*! @} */ -/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @name TIMIEN - Timer Interrupt Enable */ /*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) @@ -21921,7 +22034,7 @@ typedef struct { #define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) /*! @} */ -/*! @name SHIFTSTATE - Shifter State Register */ +/*! @name SHIFTSTATE - Shifter State */ /*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) @@ -21930,16 +22043,21 @@ typedef struct { #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) /*! @} */ -/*! @name TRGSTAT - Trigger Status Register */ +/*! @name TRGSTAT - Trigger Status */ /*! @{ */ #define FLEXIO_TRGSTAT_ETSF_MASK (0xFFU) #define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) -/*! ETSF - External Trigger Status Flags */ +/*! ETSF - External Trigger Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ #define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) /*! @} */ -/*! @name TRIGIEN - External Trigger Interrupt Enable Register */ +/*! @name TRIGIEN - External Trigger Interrupt Enable */ /*! @{ */ #define FLEXIO_TRIGIEN_TRIE_MASK (0xFFU) @@ -21948,16 +22066,21 @@ typedef struct { #define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) /*! @} */ -/*! @name PINSTAT - Pin Status Register */ +/*! @name PINSTAT - Pin Status */ /*! @{ */ #define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) #define FLEXIO_PINSTAT_PSF_SHIFT (0U) -/*! PSF - Pin Status Flags */ +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + */ #define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) /*! @} */ -/*! @name PINIEN - Pin Interrupt Enable Register */ +/*! @name PINIEN - Pin Interrupt Enable */ /*! @{ */ #define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) @@ -21966,7 +22089,7 @@ typedef struct { #define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) /*! @} */ -/*! @name PINREN - Pin Rising Edge Enable Register */ +/*! @name PINREN - Pin Rising Edge Enable */ /*! @{ */ #define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) @@ -21975,7 +22098,7 @@ typedef struct { #define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) /*! @} */ -/*! @name PINFEN - Pin Falling Edge Enable Register */ +/*! @name PINFEN - Pin Falling Edge Enable */ /*! @{ */ #define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) @@ -21984,7 +22107,7 @@ typedef struct { #define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) /*! @} */ -/*! @name PINOUTD - Pin Output Data Register */ +/*! @name PINOUTD - Pin Output Data */ /*! @{ */ #define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) @@ -21993,7 +22116,7 @@ typedef struct { #define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) /*! @} */ -/*! @name PINOUTE - Pin Output Enable Register */ +/*! @name PINOUTE - Pin Output Enable */ /*! @{ */ #define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) @@ -22002,7 +22125,7 @@ typedef struct { #define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) /*! @} */ -/*! @name PINOUTDIS - Pin Output Disable Register */ +/*! @name PINOUTDIS - Pin Output Disable */ /*! @{ */ #define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) @@ -22011,7 +22134,7 @@ typedef struct { #define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) /*! @} */ -/*! @name PINOUTCLR - Pin Output Clear Register */ +/*! @name PINOUTCLR - Pin Output Clear */ /*! @{ */ #define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) @@ -22020,7 +22143,7 @@ typedef struct { #define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) /*! @} */ -/*! @name PINOUTSET - Pin Output Set Register */ +/*! @name PINOUTSET - Pin Output Set */ /*! @{ */ #define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) @@ -22029,7 +22152,7 @@ typedef struct { #define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) /*! @} */ -/*! @name PINOUTTOG - Pin Output Toggle Register */ +/*! @name PINOUTTOG - Pin Output Toggle */ /*! @{ */ #define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) @@ -22038,28 +22161,28 @@ typedef struct { #define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) /*! @} */ -/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @name SHIFTCTL - Shifter Control */ /*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode - * 0b000..Disabled. - * 0b001..Receive mode. Captures the current shifter content into the SHIFTBUF on expiration of the timer. - * 0b010..Transmit mode. Load SHIFTBUF contents into the shifter on expiration of the timer. - * 0b011..Reserved. - * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the timer. - * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. - * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. - * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic lookup table. + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low + * 0b0..Active high + * 0b1..Active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) @@ -22081,8 +22204,8 @@ typedef struct { #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity - * 0b0..Shift on posedge of shift clock - * 0b1..Shift on negedge of shift clock + * 0b0..Positive edge + * 0b1..Negative edge */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) @@ -22095,31 +22218,33 @@ typedef struct { /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (8U) -/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @name SHIFTCFG - Shifter Configuration */ /*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) -/*! SSTART - Shifter Start Bit - * 0b00..Start bit disabled for transmitter/receiver/match store. Transmitter loads data on enable. - * 0b01..Start bit disabled for transmitter/receiver/match store. Transmitter loads data on first shift. - * 0b10..Transmitter outputs start bit value 0 before loading data on first shift. If start bit is not 0, receiver/match store sets error flag. - * 0b11..Transmitter outputs start bit value 1 before loading data on first shift. If start bit is not 1, receiver/match store sets error flag. +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) -/*! SSTOP - Shifter Stop bit - * 0b00..Stop bit disabled for transmitter/receiver/match store - * 0b01..Stop bit disabled for transmitter/receiver/match store. When timer is in stop condition, receiver/match - * store stores receive data on the configured shift edge. - * 0b10..Transmitter outputs stop bit value 0 on store. If stop bit is not 0, receiver/match store sets error - * flag. When timer is in stop condition, receiver/match stores also store receive data on the configured shift - * edge. - * 0b11..Transmitter outputs stop bit value 1 on store. If stop bit is not 1, receiver/match store sets error - * flag. When timer is in stop condition, receiver/match store also stores receive data on the configured shift - * edge. +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) @@ -22127,23 +22252,23 @@ typedef struct { #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source * 0b0..Pin - * 0b1..Shifter N+1 Output + * 0b1..Shifter n+1 output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) #define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) /*! LATST - Late Store - * 0b0..Shift register stores the pre-shift register state. - * 0b1..Shift register stores the post-shift register state. + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state */ #define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) #define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) #define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) /*! SSIZE - Shifter Size - * 0b0..Shift register is 32-bit. - * 0b1..Shift register is 24-bit. + * 0b0..32-bit + * 0b1..24-bit */ #define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) @@ -22156,7 +22281,7 @@ typedef struct { /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (8U) -/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @name SHIFTBUF - Shifter Buffer */ /*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) @@ -22168,7 +22293,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (8U) -/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) @@ -22180,7 +22305,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (8U) -/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) @@ -22192,7 +22317,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (8U) -/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) @@ -22204,44 +22329,44 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (8U) -/*! @name TIMCTL - Timer Control N Register */ +/*! @name TIMCTL - Timer Control */ /*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode - * 0b000..Timer disabled. - * 0b001..Dual 8-bit counters baud mode. - * 0b010..Dual 8-bit counters PWM high mode. - * 0b011..Single 16-bit counter mode. - * 0b100..Single 16-bit counter disable mode. - * 0b101..Dual 8-bit counters word mode. - * 0b110..Dual 8-bit counters PWM low mode. - * 0b111..Single 16-bit input capture mode. + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) #define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) /*! ONETIM - Timer One Time Operation - * 0b0..The timer enable event is generated as normal. - * 0b1..The timer enable event is blocked unless timer status flag is clear. + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear */ #define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) #define FLEXIO_TIMCTL_PININS_MASK (0x40U) #define FLEXIO_TIMCTL_PININS_SHIFT (6U) /*! PININS - Timer Pin Input Select - * 0b0..Timer pin input and output are selected by PINSEL. - * 0b1..Timer pin input is selected by PINSEL+1. Timer pin output remains selected by PINSEL. + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL */ #define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low + * 0b0..Active high + * 0b1..Active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) @@ -22263,16 +22388,16 @@ typedef struct { #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source - * 0b0..External trigger selected - * 0b1..Internal trigger selected + * 0b0..External + * 0b1..Internal */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity - * 0b0..Trigger active high - * 0b1..Trigger active low + * 0b0..Active high + * 0b1..Active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) @@ -22285,24 +22410,24 @@ typedef struct { /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (8U) -/*! @name TIMCFG - Timer Configuration N Register */ +/*! @name TIMCFG - Timer Configuration */ /*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) -/*! TSTART - Timer Start Bit - * 0b0..Start bit disabled - * 0b1..Start bit enabled +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) -/*! TSTOP - Timer Stop Bit - * 0b00..Stop bit disabled - * 0b01..Stop bit is enabled on timer compare - * 0b10..Stop bit is enabled on timer disable - * 0b11..Stop bit is enabled on timer compare and timer disable +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) @@ -22310,13 +22435,13 @@ typedef struct { #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable * 0b000..Timer always enabled - * 0b001..Timer enabled on Timer N-1 enable - * 0b010..Timer enabled on Trigger high - * 0b011..Timer enabled on Trigger high and Pin high - * 0b100..Timer enabled on Pin rising edge - * 0b101..Timer enabled on Pin rising edge and Trigger high - * 0b110..Timer enabled on Trigger rising edge - * 0b111..Timer enabled on Trigger rising or falling edge + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) @@ -22324,9 +22449,9 @@ typedef struct { #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable * 0b000..Timer never disabled - * 0b001..Timer disabled on Timer N-1 disable - * 0b010..Timer disabled on timer compare (upper 8-bits match and decrement) - * 0b011..Timer disabled on timer compare (upper 8-bits match and decrement) and trigger low + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low * 0b100..Timer disabled on pin rising or falling edge * 0b101..Timer disabled on pin rising or falling edge provided trigger is high * 0b110..Timer disabled on trigger falling edge @@ -22337,7 +22462,7 @@ typedef struct { #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset - * 0b000..Timer never reset + * 0b000..Never reset timer * 0b001..Timer reset on timer output high. * 0b010..Timer reset on timer pin equal to timer output * 0b011..Timer reset on timer trigger equal to timer output @@ -22351,24 +22476,24 @@ typedef struct { #define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement - * 0b000..Decrement counter on FLEXIO clock. Shift clock equals timer output. - * 0b001..Decrement counter on trigger input (both edges). Shift clock equals timer output. - * 0b010..Decrement counter on pin input (both edges). Shift clock equals pin input. - * 0b011..Decrement counter on trigger input (both edges). Shift clock equals trigger input. - * 0b100..Decrement counter on FLEXIO clock divided by 16. Shift clock equals timer output. - * 0b101..Decrement counter on FLEXIO clock divided by 256. Shift clock equals timer output. - * 0b110..Decrement counter on pin input (rising edge). Shift clock equals pin input. - * 0b111..Decrement counter on trigger input (rising edge). Shift clock equals trigger input. + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output - * 0b00..Timer output is logic one when enabled and is not affected by timer reset - * 0b01..Timer output is logic zero when enabled and is not affected by timer reset - * 0b10..Timer output is logic one when enabled and on timer reset - * 0b11..Timer output is logic zero when enabled and on timer reset + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) /*! @} */ @@ -22376,7 +22501,7 @@ typedef struct { /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (8U) -/*! @name TIMCMP - Timer Compare N Register */ +/*! @name TIMCMP - Timer Compare */ /*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) @@ -22388,7 +22513,7 @@ typedef struct { /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (8U) -/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) @@ -22400,7 +22525,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (8U) -/*! @name SHIFTBUFHWS - Shifter Buffer N Halfword Swapped Register */ +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) @@ -22412,7 +22537,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (8U) -/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) @@ -22424,7 +22549,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (8U) -/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */ +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) @@ -22436,7 +22561,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFOES */ #define FLEXIO_SHIFTBUFOES_COUNT (8U) -/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */ +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) @@ -22448,7 +22573,7 @@ typedef struct { /* The count of FLEXIO_SHIFTBUFEOS */ #define FLEXIO_SHIFTBUFEOS_COUNT (8U) -/*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */ +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) @@ -22805,8 +22930,11 @@ typedef struct { #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK (0x800000U) #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT (23U) /*! RX_CLK_SRC_DIFF - Sample Clock Source Different - * 0b0..Use MCR0[RXCLKSRC] for Port A and Port B. - * 0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. + * 0b0..Use MCR0[RXCLKSRC] for Port A and Port B. MCR2[RXCLKSRC_B] is ignored and MCR0[RXCLKSRC] selects the + * Sample Clock source for Flash Reading of both ports A and B. + * 0b1..Use MCR0[RXCLKSRC] for Port A, and MCR2[RXCLKSRC_B] for Port B. MCR0[RXCLKSRC] selects the Sample Clock + * source for Flash Reading of port A (A_SCLK) and MCR2[RXCLKSRC_B] selects the Sample Clock source for Flash + * Reading of port B (B_SCLK). */ #define FLEXSPI_MCR2_RX_CLK_SRC_DIFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RX_CLK_SRC_DIFF_SHIFT)) & FLEXSPI_MCR2_RX_CLK_SRC_DIFF_MASK) @@ -22902,6 +23030,11 @@ typedef struct { * 0b11..256 bytes */ #define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) + +#define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xE0000000U) +#define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (29U) +/*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */ +#define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ @@ -23555,7 +23688,7 @@ typedef struct { #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) -/*! SLVDLYTARGET - Target Delay Line For Target */ +/*! SLVDLYTARGET - Target Delay Line */ #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) @@ -23570,6 +23703,11 @@ typedef struct { #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Target Clock Delay Line Override Value */ #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) + +#define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) +#define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) +/*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */ +#define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ /* The count of FLEXSPI_DLLCR */ @@ -24652,14 +24790,32 @@ typedef struct { #endif /** Interrupt vectors for the FLEXSPI peripheral type */ #define FLEXSPI_IRQS { FLEXSPI0_IRQn } -#if (__ARM_FEATURE_CMSE & 0x2) -/** FlexSPI0 AMBA address */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +/** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE (0x18000000u) -/** FlexSPI0 AMBA address */ +/** FlexSPI0 AMBA end address */ +#define FlexSPI0_AMBA_END (0x1FFFFFFFu) +/** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE_NS (0x08000000U) +/** FlexSPI0 AMBA end address */ +#define FlexSPI0_AMBA_END_NS (0x0FFFFFFFU) +/* FlexSPI0 alias1 base address. */ +#define FlexSPI0_ALIAS1_BASE (0x80000000U) +/* FlexSPI0 alias1 base NS address. */ +#define FlexSPI0_ALIAS1_BASE_NS (0x90000000U) +/* FlexSPI0 alias2 base address. */ +#define FlexSPI0_ALIAS2_BASE (0xA0000000U) +/* FlexSPI0 alias2 base NS address. */ +#define FlexSPI0_ALIAS2_BASE_NS (0xB0000000U) #else -/** FlexSPI0 AMBA address */ +/** FlexSPI0 AMBA base address */ #define FlexSPI0_AMBA_BASE (0x08000000U) +/** FlexSPI0 AMBA end address */ +#define FlexSPI0_AMBA_END (0x0FFFFFFFU) +/* FlexSPI0 alias1 base address. */ +#define FlexSPI0_ALIAS1_BASE (0x80000000U) +/* FlexSPI0 alias2 base address. */ +#define FlexSPI0_ALIAS2_BASE (0xA0000000U) #endif @@ -27886,9 +28042,9 @@ typedef struct { /* FMUTEST - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) /** Peripheral FMU0TEST base address */ - #define FMU0TEST_BASE (0x5004E000u) + #define FMU0TEST_BASE (0x50043000u) /** Peripheral FMU0TEST base address */ - #define FMU0TEST_BASE_NS (0x4004E000u) + #define FMU0TEST_BASE_NS (0x40043000u) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) /** Peripheral FMU0TEST base pointer */ @@ -27903,7 +28059,7 @@ typedef struct { #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } #else /** Peripheral FMU0TEST base address */ - #define FMU0TEST_BASE (0x4004E000u) + #define FMU0TEST_BASE (0x40043000u) /** Peripheral FMU0TEST base pointer */ #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) /** Array initializer of FMUTEST peripheral base addresses */ @@ -28218,15 +28374,30 @@ typedef struct { /*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */ #define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) +#define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) +#define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) +/*! field_3_0 - GDET configuration 0 Field 3_0 */ +#define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) + #define GDET_GDET_CONF_0_SBZ_MASK (0x10U) #define GDET_GDET_CONF_0_SBZ_SHIFT (4U) /*! SBZ - Should Be Left to Zero */ #define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) +#define GDET_GDET_CONF_0_SBZ_MASK (0x10U) +#define GDET_GDET_CONF_0_SBZ_SHIFT (4U) +/*! sbz - Should be left to zero */ +#define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) + #define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) #define GDET_GDET_CONF_0_RFU_SHIFT (5U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) + +#define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) +#define GDET_GDET_CONF_0_RFU_SHIFT (5U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) /*! @} */ /*! @name GDET_CONF_1 - GDET Configuration 1 Register */ @@ -28237,50 +28408,100 @@ typedef struct { /*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */ #define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) +#define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) +#define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) +/*! field_1_0 - GDET configuration 1 Field 1_0 */ +#define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) + #define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) #define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) /*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */ #define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) +#define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) +#define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) +/*! field_3_2 - GDET configuration 1 Field 3_2 */ +#define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) + #define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) #define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) /*! SBZ1 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) +#define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) +#define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) +/*! sbz1 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) + #define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) #define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) /*! SBZ2 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) +#define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) +#define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) +/*! sbz2 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) + #define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) #define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) /*! SBZ3 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) +#define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) +#define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) +/*! sbz3 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) + #define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) #define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) /*! FIELD_7 - GDET Configuration 1 Field 7 */ #define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) +#define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) +#define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) +/*! field_7 - GDET configuration 1 Field 7 */ +#define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) + #define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) #define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) /*! FIELD_8 - GDET Configuration 1 Field 8 */ #define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) +#define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) +#define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) +/*! field_8 - GDET configuration 1 Field 8 */ +#define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) + #define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) #define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) /*! SBZ4 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) +#define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) +#define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) +/*! sbz4 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) + #define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) #define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) /*! SBZ5 - Should Be Left to Zero */ #define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) +#define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) +#define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) +/*! sbz5 - Should be left to zero */ +#define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) + #define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) #define GDET_GDET_CONF_1_RFU_SHIFT (11U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) + +#define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) +#define GDET_GDET_CONF_1_RFU_SHIFT (11U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) /*! @} */ /*! @name GDET_ENABLE1 - GDET Enable Register */ @@ -28291,10 +28512,20 @@ typedef struct { /*! EN1 - If set, the detector will be clock gated */ #define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) +#define GDET_GDET_ENABLE1_EN1_MASK (0x1U) +#define GDET_GDET_ENABLE1_EN1_SHIFT (0U) +/*! en1 - If set, the detector will be clock gated */ +#define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) + #define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_ENABLE1_RFU_SHIFT (1U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) + +#define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_ENABLE1_RFU_SHIFT (1U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) /*! @} */ /*! @name GDET_CONF_2 - GDET Configuration 2 Register */ @@ -28305,30 +28536,60 @@ typedef struct { /*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */ #define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) +#define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) +/*! field_6_0 - GDET configuration 2 Field 6_0 */ +#define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) + #define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) #define GDET_GDET_CONF_2_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) +#define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) +#define GDET_GDET_CONF_2_RFU1_SHIFT (7U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) + #define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) #define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) /*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */ #define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) +#define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) +#define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) +/*! field_21_16 - GDET configuration 2 Field 21_16 */ +#define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) + #define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) #define GDET_GDET_CONF_2_RFU2_SHIFT (22U) /*! RFU2 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) +#define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) +#define GDET_GDET_CONF_2_RFU2_SHIFT (22U) +/*! rfu2 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) + #define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) #define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) /*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */ #define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) +#define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) +#define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) +/*! field_29_24 - GDET configuration 2 Field 29_24 */ +#define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) + #define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) #define GDET_GDET_CONF_2_RFU3_SHIFT (30U) /*! RFU3 - Reserved for Future Use */ #define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) + +#define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) +#define GDET_GDET_CONF_2_RFU3_SHIFT (30U) +/*! rfu3 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) /*! @} */ /*! @name GDET_CONF_3 - GDET Configuration 3 Register */ @@ -28339,10 +28600,20 @@ typedef struct { /*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */ #define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) +#define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) +/*! field_6_0 - GDET configuration 3 Field 6_0 */ +#define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) + #define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_3_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) + +#define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_3_RFU1_SHIFT (7U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) /*! @} */ /*! @name GDET_CONF_4 - GDET Configuration 4 Register */ @@ -28353,10 +28624,20 @@ typedef struct { /*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */ #define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) +#define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) +/*! field_6_0 - GDET configuration 4 Field 6_0 */ +#define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) + #define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) #define GDET_GDET_CONF_4_RFU1_SHIFT (7U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) + +#define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_4_RFU1_SHIFT (7U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) /*! @} */ /*! @name GDET_CONF_5 - GDET Configuration 5 Register */ @@ -28367,15 +28648,30 @@ typedef struct { /*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */ #define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) +#define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) +#define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) +/*! field_5_0 - GDET configuration 5 Field 5_0 */ +#define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) + #define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) #define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) /*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */ #define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) +#define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) +#define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) +/*! field_11_6 - GDET configuration 5 Field 11_6 */ +#define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) + #define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) #define GDET_GDET_CONF_5_RFU1_SHIFT (12U) /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) + +#define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) +#define GDET_GDET_CONF_5_RFU1_SHIFT (12U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) /*! @} */ /*! @name GDET_RESET - GDET Reset Register */ @@ -28386,15 +28682,30 @@ typedef struct { /*! RFU1 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) +#define GDET_GDET_RESET_RFU1_MASK (0x7U) +#define GDET_GDET_RESET_RFU1_SHIFT (0U) +/*! rfu1 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) + #define GDET_GDET_RESET_SFT_RST_MASK (0x8U) #define GDET_GDET_RESET_SFT_RST_SHIFT (3U) /*! SFT_RST - Soft Reset for the Core Reset */ #define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) +#define GDET_GDET_RESET_SFT_RST_MASK (0x8U) +#define GDET_GDET_RESET_SFT_RST_SHIFT (3U) +/*! sft_rst - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 */ +#define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) + #define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) #define GDET_GDET_RESET_RFU2_SHIFT (4U) /*! RFU2 - Reserved for Future Use */ #define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) + +#define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) +#define GDET_GDET_RESET_RFU2_SHIFT (4U) +/*! rfu2 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) /*! @} */ /*! @name GDET_TEST - GDET Test Register */ @@ -28405,10 +28716,20 @@ typedef struct { /*! SBZ - Should Be Left to Zero */ #define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) +#define GDET_GDET_TEST_SBZ_MASK (0x1U) +#define GDET_GDET_TEST_SBZ_SHIFT (0U) +/*! sbz - Should be left to zero */ +#define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) + #define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) #define GDET_GDET_TEST_RFU_SHIFT (1U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) + +#define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_TEST_RFU_SHIFT (1U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) /*! @} */ /*! @name GDET_DLY_CTRL - GDET Delay Control Register */ @@ -28419,15 +28740,30 @@ typedef struct { /*! VOL_SEL - GDET Delay Control of the Voltage Mode */ #define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) +#define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) +#define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) +/*! vol_sel - GDET delay control of the voltage mode. Used to select the trim code appropiate to the voltage mode. */ +#define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) + #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) /*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */ #define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) +/*! sw_vol_ctrl - Select the control of the trim code to the delay line via HW port (0) or SW SFR (1) */ +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) + #define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) #define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) /*! RFU - Reserved for Future Use */ #define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) + +#define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) +#define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) +/*! rfu - Reserved for Future Use */ +#define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) /*! @} */ @@ -28497,25 +28833,25 @@ typedef struct { __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t LOCK; /**< Lock, offset: 0xC */ - __IO uint32_t PCNS; /**< Pin Control Non-Secure, offset: 0x10 */ - __IO uint32_t ICNS; /**< Interrupt Control Non-Secure, offset: 0x14 */ - __IO uint32_t PCNP; /**< Pin Control Non-Privilege, offset: 0x18 */ - __IO uint32_t ICNP; /**< Interrupt Control Non-Privilege, offset: 0x1C */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ uint8_t RESERVED_1[32]; - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x40 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x44 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x48 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0x4C */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x50 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x54 */ - __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x58 */ + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ uint8_t RESERVED_2[4]; - __IO uint8_t PDR[32]; /**< Pin Data Register a, array offset: 0x60, array step: 0x1 */ - __IO uint32_t ICR[32]; /**< Interrupt Control Register 0..Interrupt Control Register 31, array offset: 0x80, array step: 0x4 */ - __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x100 */ - __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x104 */ + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ uint8_t RESERVED_3[24]; - __IO uint32_t ISFR[2]; /**< Interrupt Status Flag Register, array offset: 0x120, array step: 0x4 */ + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -28533,8 +28869,8 @@ typedef struct { #define GPIO_VERID_FEATURE_MASK (0xFFFFU) #define GPIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number - * 0b0000000000000000..Basic implementation. - * 0b0000000000000001..Protection registers implemented. + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented */ #define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) @@ -28564,2760 +28900,2424 @@ typedef struct { #define GPIO_LOCK_PCNS_MASK (0x1U) #define GPIO_LOCK_PCNS_SHIFT (0U) /*! PCNS - Lock PCNS - * 0b0..PCNS register is writable by software in Secure-Privilege state. - * 0b1..PCNS register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK) #define GPIO_LOCK_ICNS_MASK (0x2U) #define GPIO_LOCK_ICNS_SHIFT (1U) /*! ICNS - Lock ICNS - * 0b0..ICNS register is writable by software in Secure-Privilege state. - * 0b1..ICNS register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK) #define GPIO_LOCK_PCNP_MASK (0x4U) #define GPIO_LOCK_PCNP_SHIFT (2U) /*! PCNP - Lock PCNP - * 0b0..PCNP register is writable by software in Secure-Privilege state. - * 0b1..PCNP register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK) #define GPIO_LOCK_ICNP_MASK (0x8U) #define GPIO_LOCK_ICNP_SHIFT (3U) /*! ICNP - Lock ICNP - * 0b0..ICNP register is writable by software in Secure-Privilege state. - * 0b1..ICNP register is not writable until the next reset. + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset */ #define GPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK) /*! @} */ -/*! @name PCNS - Pin Control Non-Secure */ +/*! @name PCNS - Pin Control Nonsecure */ /*! @{ */ #define GPIO_PCNS_NSE0_MASK (0x1U) #define GPIO_PCNS_NSE0_SHIFT (0U) -/*! NSE0 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK) #define GPIO_PCNS_NSE1_MASK (0x2U) #define GPIO_PCNS_NSE1_SHIFT (1U) -/*! NSE1 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK) #define GPIO_PCNS_NSE2_MASK (0x4U) #define GPIO_PCNS_NSE2_SHIFT (2U) -/*! NSE2 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK) #define GPIO_PCNS_NSE3_MASK (0x8U) #define GPIO_PCNS_NSE3_SHIFT (3U) -/*! NSE3 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK) #define GPIO_PCNS_NSE4_MASK (0x10U) #define GPIO_PCNS_NSE4_SHIFT (4U) -/*! NSE4 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK) #define GPIO_PCNS_NSE5_MASK (0x20U) #define GPIO_PCNS_NSE5_SHIFT (5U) -/*! NSE5 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK) #define GPIO_PCNS_NSE6_MASK (0x40U) #define GPIO_PCNS_NSE6_SHIFT (6U) -/*! NSE6 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK) #define GPIO_PCNS_NSE7_MASK (0x80U) #define GPIO_PCNS_NSE7_SHIFT (7U) -/*! NSE7 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK) #define GPIO_PCNS_NSE8_MASK (0x100U) #define GPIO_PCNS_NSE8_SHIFT (8U) -/*! NSE8 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK) #define GPIO_PCNS_NSE9_MASK (0x200U) #define GPIO_PCNS_NSE9_SHIFT (9U) -/*! NSE9 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK) #define GPIO_PCNS_NSE10_MASK (0x400U) #define GPIO_PCNS_NSE10_SHIFT (10U) -/*! NSE10 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK) #define GPIO_PCNS_NSE11_MASK (0x800U) #define GPIO_PCNS_NSE11_SHIFT (11U) -/*! NSE11 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK) #define GPIO_PCNS_NSE12_MASK (0x1000U) #define GPIO_PCNS_NSE12_SHIFT (12U) -/*! NSE12 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK) #define GPIO_PCNS_NSE13_MASK (0x2000U) #define GPIO_PCNS_NSE13_SHIFT (13U) -/*! NSE13 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK) #define GPIO_PCNS_NSE14_MASK (0x4000U) #define GPIO_PCNS_NSE14_SHIFT (14U) -/*! NSE14 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK) #define GPIO_PCNS_NSE15_MASK (0x8000U) #define GPIO_PCNS_NSE15_SHIFT (15U) -/*! NSE15 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK) #define GPIO_PCNS_NSE16_MASK (0x10000U) #define GPIO_PCNS_NSE16_SHIFT (16U) -/*! NSE16 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK) #define GPIO_PCNS_NSE17_MASK (0x20000U) #define GPIO_PCNS_NSE17_SHIFT (17U) -/*! NSE17 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK) #define GPIO_PCNS_NSE18_MASK (0x40000U) #define GPIO_PCNS_NSE18_SHIFT (18U) -/*! NSE18 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK) #define GPIO_PCNS_NSE19_MASK (0x80000U) #define GPIO_PCNS_NSE19_SHIFT (19U) -/*! NSE19 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK) #define GPIO_PCNS_NSE20_MASK (0x100000U) #define GPIO_PCNS_NSE20_SHIFT (20U) -/*! NSE20 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK) #define GPIO_PCNS_NSE21_MASK (0x200000U) #define GPIO_PCNS_NSE21_SHIFT (21U) -/*! NSE21 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK) #define GPIO_PCNS_NSE22_MASK (0x400000U) #define GPIO_PCNS_NSE22_SHIFT (22U) -/*! NSE22 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK) #define GPIO_PCNS_NSE23_MASK (0x800000U) #define GPIO_PCNS_NSE23_SHIFT (23U) -/*! NSE23 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK) #define GPIO_PCNS_NSE24_MASK (0x1000000U) #define GPIO_PCNS_NSE24_SHIFT (24U) -/*! NSE24 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK) #define GPIO_PCNS_NSE25_MASK (0x2000000U) #define GPIO_PCNS_NSE25_SHIFT (25U) -/*! NSE25 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK) #define GPIO_PCNS_NSE26_MASK (0x4000000U) #define GPIO_PCNS_NSE26_SHIFT (26U) -/*! NSE26 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK) #define GPIO_PCNS_NSE27_MASK (0x8000000U) #define GPIO_PCNS_NSE27_SHIFT (27U) -/*! NSE27 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK) #define GPIO_PCNS_NSE28_MASK (0x10000000U) #define GPIO_PCNS_NSE28_SHIFT (28U) -/*! NSE28 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK) #define GPIO_PCNS_NSE29_MASK (0x20000000U) #define GPIO_PCNS_NSE29_SHIFT (29U) -/*! NSE29 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK) #define GPIO_PCNS_NSE30_MASK (0x40000000U) #define GPIO_PCNS_NSE30_SHIFT (30U) -/*! NSE30 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK) #define GPIO_PCNS_NSE31_MASK (0x80000000U) #define GPIO_PCNS_NSE31_SHIFT (31U) -/*! NSE31 - Non-Secure Enable - * 0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and - * bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed - * by software in Non-Secure state, all bits in the registers related to that pin are read zero and write - * ignored. - * 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers - * and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are - * accessed by software in Secure state, all bits in the registers related to that pin are read zero and write - * ignored. +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK) /*! @} */ -/*! @name ICNS - Interrupt Control Non-Secure */ +/*! @name ICNS - Interrupt Control Nonsecure */ /*! @{ */ #define GPIO_ICNS_NSE0_MASK (0x1U) #define GPIO_ICNS_NSE0_SHIFT (0U) -/*! NSE0 - Non-Secure Enable - * 0b0..The interrupt, output trigger or DMA request is configured for Secure access. Only software in Secure - * state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a - * pin that is already configured to use the corresponding interrupt, output trigger or DMA request. - * 0b1..The interrupt, output trigger or DMA request is configured for Non-Secure access. Only software in - * Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or - * reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK) #define GPIO_ICNS_NSE1_MASK (0x2U) #define GPIO_ICNS_NSE1_SHIFT (1U) -/*! NSE1 - Non-Secure Enable - * 0b0..The interrupt, output trigger or DMA request is configured for Secure access. Only software in Secure - * state can configure a pin to use the corresponding interrupt, output trigger or DMA request or reconfigure a - * pin that is already configured to use the corresponding interrupt, output trigger or DMA request. - * 0b1..The interrupt, output trigger or DMA request is configured for Non-Secure access. Only software in - * Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or DMA request or - * reconfigure a pin that is already configured to use the corresponding interrupt, output trigger or DMA request. +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access */ #define GPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK) /*! @} */ -/*! @name PCNP - Pin Control Non-Privilege */ +/*! @name PCNP - Pin Control Nonprivilege */ /*! @{ */ #define GPIO_PCNP_NPE0_MASK (0x1U) #define GPIO_PCNP_NPE0_SHIFT (0U) -/*! NPE0 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK) #define GPIO_PCNP_NPE1_MASK (0x2U) #define GPIO_PCNP_NPE1_SHIFT (1U) -/*! NPE1 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK) #define GPIO_PCNP_NPE2_MASK (0x4U) #define GPIO_PCNP_NPE2_SHIFT (2U) -/*! NPE2 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK) #define GPIO_PCNP_NPE3_MASK (0x8U) #define GPIO_PCNP_NPE3_SHIFT (3U) -/*! NPE3 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK) #define GPIO_PCNP_NPE4_MASK (0x10U) #define GPIO_PCNP_NPE4_SHIFT (4U) -/*! NPE4 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK) #define GPIO_PCNP_NPE5_MASK (0x20U) #define GPIO_PCNP_NPE5_SHIFT (5U) -/*! NPE5 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK) #define GPIO_PCNP_NPE6_MASK (0x40U) #define GPIO_PCNP_NPE6_SHIFT (6U) -/*! NPE6 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK) #define GPIO_PCNP_NPE7_MASK (0x80U) #define GPIO_PCNP_NPE7_SHIFT (7U) -/*! NPE7 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK) #define GPIO_PCNP_NPE8_MASK (0x100U) #define GPIO_PCNP_NPE8_SHIFT (8U) -/*! NPE8 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK) #define GPIO_PCNP_NPE9_MASK (0x200U) #define GPIO_PCNP_NPE9_SHIFT (9U) -/*! NPE9 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK) #define GPIO_PCNP_NPE10_MASK (0x400U) #define GPIO_PCNP_NPE10_SHIFT (10U) -/*! NPE10 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK) #define GPIO_PCNP_NPE11_MASK (0x800U) #define GPIO_PCNP_NPE11_SHIFT (11U) -/*! NPE11 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK) #define GPIO_PCNP_NPE12_MASK (0x1000U) #define GPIO_PCNP_NPE12_SHIFT (12U) -/*! NPE12 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK) #define GPIO_PCNP_NPE13_MASK (0x2000U) #define GPIO_PCNP_NPE13_SHIFT (13U) -/*! NPE13 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK) #define GPIO_PCNP_NPE14_MASK (0x4000U) #define GPIO_PCNP_NPE14_SHIFT (14U) -/*! NPE14 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK) #define GPIO_PCNP_NPE15_MASK (0x8000U) #define GPIO_PCNP_NPE15_SHIFT (15U) -/*! NPE15 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK) #define GPIO_PCNP_NPE16_MASK (0x10000U) #define GPIO_PCNP_NPE16_SHIFT (16U) -/*! NPE16 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK) #define GPIO_PCNP_NPE17_MASK (0x20000U) #define GPIO_PCNP_NPE17_SHIFT (17U) -/*! NPE17 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK) #define GPIO_PCNP_NPE18_MASK (0x40000U) #define GPIO_PCNP_NPE18_SHIFT (18U) -/*! NPE18 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK) #define GPIO_PCNP_NPE19_MASK (0x80000U) #define GPIO_PCNP_NPE19_SHIFT (19U) -/*! NPE19 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK) #define GPIO_PCNP_NPE20_MASK (0x100000U) #define GPIO_PCNP_NPE20_SHIFT (20U) -/*! NPE20 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK) #define GPIO_PCNP_NPE21_MASK (0x200000U) #define GPIO_PCNP_NPE21_SHIFT (21U) -/*! NPE21 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK) #define GPIO_PCNP_NPE22_MASK (0x400000U) #define GPIO_PCNP_NPE22_SHIFT (22U) -/*! NPE22 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK) #define GPIO_PCNP_NPE23_MASK (0x800000U) #define GPIO_PCNP_NPE23_SHIFT (23U) -/*! NPE23 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK) #define GPIO_PCNP_NPE24_MASK (0x1000000U) #define GPIO_PCNP_NPE24_SHIFT (24U) -/*! NPE24 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK) #define GPIO_PCNP_NPE25_MASK (0x2000000U) #define GPIO_PCNP_NPE25_SHIFT (25U) -/*! NPE25 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK) #define GPIO_PCNP_NPE26_MASK (0x4000000U) #define GPIO_PCNP_NPE26_SHIFT (26U) -/*! NPE26 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK) #define GPIO_PCNP_NPE27_MASK (0x8000000U) #define GPIO_PCNP_NPE27_SHIFT (27U) -/*! NPE27 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK) #define GPIO_PCNP_NPE28_MASK (0x10000000U) #define GPIO_PCNP_NPE28_SHIFT (28U) -/*! NPE28 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK) #define GPIO_PCNP_NPE29_MASK (0x20000000U) #define GPIO_PCNP_NPE29_SHIFT (29U) -/*! NPE29 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK) #define GPIO_PCNP_NPE30_MASK (0x40000000U) #define GPIO_PCNP_NPE30_SHIFT (30U) -/*! NPE30 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK) #define GPIO_PCNP_NPE31_MASK (0x80000000U) #define GPIO_PCNP_NPE31_SHIFT (31U) -/*! NPE31 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit - * fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields - * are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable - * but write ignored. - * 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers - * is allowed by software in both Privilege and Non-Privilege state. +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK) /*! @} */ -/*! @name ICNP - Interrupt Control Non-Privilege */ +/*! @name ICNP - Interrupt Control Nonprivilege */ /*! @{ */ #define GPIO_ICNP_NPE0_MASK (0x1U) #define GPIO_ICNP_NPE0_SHIFT (0U) -/*! NPE0 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use - * the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to - * use the corresponding interrupt/trigger output/DMA request. - * 0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can - * configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is - * already configured to use the corresponding interrupt/trigger output/DMA request. +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK) #define GPIO_ICNP_NPE1_MASK (0x2U) #define GPIO_ICNP_NPE1_SHIFT (1U) -/*! NPE1 - Non-Privilege Enable - * 0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use - * the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is already configured to - * use the corresponding interrupt/trigger output/DMA request. - * 0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can - * configure a pin to use the corresponding interrupt/trigger output/DMA request or reconfigure a pin that is - * already configured to use the corresponding interrupt/trigger output/DMA request. +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access */ #define GPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK) /*! @} */ -/*! @name PDOR - Port Data Output Register */ +/*! @name PDOR - Port Data Output */ /*! @{ */ #define GPIO_PDOR_PDO0_MASK (0x1U) #define GPIO_PDOR_PDO0_SHIFT (0U) /*! PDO0 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) #define GPIO_PDOR_PDO1_MASK (0x2U) #define GPIO_PDOR_PDO1_SHIFT (1U) /*! PDO1 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) #define GPIO_PDOR_PDO2_MASK (0x4U) #define GPIO_PDOR_PDO2_SHIFT (2U) /*! PDO2 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) #define GPIO_PDOR_PDO3_MASK (0x8U) #define GPIO_PDOR_PDO3_SHIFT (3U) /*! PDO3 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) #define GPIO_PDOR_PDO4_MASK (0x10U) #define GPIO_PDOR_PDO4_SHIFT (4U) /*! PDO4 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) #define GPIO_PDOR_PDO5_MASK (0x20U) #define GPIO_PDOR_PDO5_SHIFT (5U) /*! PDO5 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) #define GPIO_PDOR_PDO6_MASK (0x40U) #define GPIO_PDOR_PDO6_SHIFT (6U) /*! PDO6 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) #define GPIO_PDOR_PDO7_MASK (0x80U) #define GPIO_PDOR_PDO7_SHIFT (7U) /*! PDO7 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) #define GPIO_PDOR_PDO8_MASK (0x100U) #define GPIO_PDOR_PDO8_SHIFT (8U) /*! PDO8 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) #define GPIO_PDOR_PDO9_MASK (0x200U) #define GPIO_PDOR_PDO9_SHIFT (9U) /*! PDO9 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) #define GPIO_PDOR_PDO10_MASK (0x400U) #define GPIO_PDOR_PDO10_SHIFT (10U) /*! PDO10 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) #define GPIO_PDOR_PDO11_MASK (0x800U) #define GPIO_PDOR_PDO11_SHIFT (11U) /*! PDO11 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) #define GPIO_PDOR_PDO12_MASK (0x1000U) #define GPIO_PDOR_PDO12_SHIFT (12U) /*! PDO12 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) #define GPIO_PDOR_PDO13_MASK (0x2000U) #define GPIO_PDOR_PDO13_SHIFT (13U) /*! PDO13 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) #define GPIO_PDOR_PDO14_MASK (0x4000U) #define GPIO_PDOR_PDO14_SHIFT (14U) /*! PDO14 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) #define GPIO_PDOR_PDO15_MASK (0x8000U) #define GPIO_PDOR_PDO15_SHIFT (15U) /*! PDO15 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) #define GPIO_PDOR_PDO16_MASK (0x10000U) #define GPIO_PDOR_PDO16_SHIFT (16U) /*! PDO16 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) #define GPIO_PDOR_PDO17_MASK (0x20000U) #define GPIO_PDOR_PDO17_SHIFT (17U) /*! PDO17 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) #define GPIO_PDOR_PDO18_MASK (0x40000U) #define GPIO_PDOR_PDO18_SHIFT (18U) /*! PDO18 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) #define GPIO_PDOR_PDO19_MASK (0x80000U) #define GPIO_PDOR_PDO19_SHIFT (19U) /*! PDO19 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) #define GPIO_PDOR_PDO20_MASK (0x100000U) #define GPIO_PDOR_PDO20_SHIFT (20U) /*! PDO20 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) #define GPIO_PDOR_PDO21_MASK (0x200000U) #define GPIO_PDOR_PDO21_SHIFT (21U) /*! PDO21 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) #define GPIO_PDOR_PDO22_MASK (0x400000U) #define GPIO_PDOR_PDO22_SHIFT (22U) /*! PDO22 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) #define GPIO_PDOR_PDO23_MASK (0x800000U) #define GPIO_PDOR_PDO23_SHIFT (23U) /*! PDO23 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) #define GPIO_PDOR_PDO24_MASK (0x1000000U) #define GPIO_PDOR_PDO24_SHIFT (24U) /*! PDO24 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) #define GPIO_PDOR_PDO25_MASK (0x2000000U) #define GPIO_PDOR_PDO25_SHIFT (25U) /*! PDO25 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) #define GPIO_PDOR_PDO26_MASK (0x4000000U) #define GPIO_PDOR_PDO26_SHIFT (26U) /*! PDO26 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) #define GPIO_PDOR_PDO27_MASK (0x8000000U) #define GPIO_PDOR_PDO27_SHIFT (27U) /*! PDO27 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) #define GPIO_PDOR_PDO28_MASK (0x10000000U) #define GPIO_PDOR_PDO28_SHIFT (28U) /*! PDO28 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) #define GPIO_PDOR_PDO29_MASK (0x20000000U) #define GPIO_PDOR_PDO29_SHIFT (29U) /*! PDO29 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) #define GPIO_PDOR_PDO30_MASK (0x40000000U) #define GPIO_PDOR_PDO30_SHIFT (30U) /*! PDO30 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) #define GPIO_PDOR_PDO31_MASK (0x80000000U) #define GPIO_PDOR_PDO31_SHIFT (31U) /*! PDO31 - Port Data Output - * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output. - * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output. + * 0b0..Logic level 0 + * 0b1..Logic level 1 */ #define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) /*! @} */ -/*! @name PSOR - Port Set Output Register */ +/*! @name PSOR - Port Set Output */ /*! @{ */ #define GPIO_PSOR_PTSO0_MASK (0x1U) #define GPIO_PSOR_PTSO0_SHIFT (0U) /*! PTSO0 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) #define GPIO_PSOR_PTSO1_MASK (0x2U) #define GPIO_PSOR_PTSO1_SHIFT (1U) /*! PTSO1 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) #define GPIO_PSOR_PTSO2_MASK (0x4U) #define GPIO_PSOR_PTSO2_SHIFT (2U) /*! PTSO2 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) #define GPIO_PSOR_PTSO3_MASK (0x8U) #define GPIO_PSOR_PTSO3_SHIFT (3U) /*! PTSO3 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) #define GPIO_PSOR_PTSO4_MASK (0x10U) #define GPIO_PSOR_PTSO4_SHIFT (4U) /*! PTSO4 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) #define GPIO_PSOR_PTSO5_MASK (0x20U) #define GPIO_PSOR_PTSO5_SHIFT (5U) /*! PTSO5 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) #define GPIO_PSOR_PTSO6_MASK (0x40U) #define GPIO_PSOR_PTSO6_SHIFT (6U) /*! PTSO6 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) #define GPIO_PSOR_PTSO7_MASK (0x80U) #define GPIO_PSOR_PTSO7_SHIFT (7U) /*! PTSO7 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) #define GPIO_PSOR_PTSO8_MASK (0x100U) #define GPIO_PSOR_PTSO8_SHIFT (8U) /*! PTSO8 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) #define GPIO_PSOR_PTSO9_MASK (0x200U) #define GPIO_PSOR_PTSO9_SHIFT (9U) /*! PTSO9 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) #define GPIO_PSOR_PTSO10_MASK (0x400U) #define GPIO_PSOR_PTSO10_SHIFT (10U) /*! PTSO10 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) #define GPIO_PSOR_PTSO11_MASK (0x800U) #define GPIO_PSOR_PTSO11_SHIFT (11U) /*! PTSO11 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) #define GPIO_PSOR_PTSO12_MASK (0x1000U) #define GPIO_PSOR_PTSO12_SHIFT (12U) /*! PTSO12 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) #define GPIO_PSOR_PTSO13_MASK (0x2000U) #define GPIO_PSOR_PTSO13_SHIFT (13U) /*! PTSO13 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) #define GPIO_PSOR_PTSO14_MASK (0x4000U) #define GPIO_PSOR_PTSO14_SHIFT (14U) /*! PTSO14 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) #define GPIO_PSOR_PTSO15_MASK (0x8000U) #define GPIO_PSOR_PTSO15_SHIFT (15U) /*! PTSO15 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) #define GPIO_PSOR_PTSO16_MASK (0x10000U) #define GPIO_PSOR_PTSO16_SHIFT (16U) /*! PTSO16 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) #define GPIO_PSOR_PTSO17_MASK (0x20000U) #define GPIO_PSOR_PTSO17_SHIFT (17U) /*! PTSO17 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) #define GPIO_PSOR_PTSO18_MASK (0x40000U) #define GPIO_PSOR_PTSO18_SHIFT (18U) /*! PTSO18 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) #define GPIO_PSOR_PTSO19_MASK (0x80000U) #define GPIO_PSOR_PTSO19_SHIFT (19U) /*! PTSO19 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) #define GPIO_PSOR_PTSO20_MASK (0x100000U) #define GPIO_PSOR_PTSO20_SHIFT (20U) /*! PTSO20 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) #define GPIO_PSOR_PTSO21_MASK (0x200000U) #define GPIO_PSOR_PTSO21_SHIFT (21U) /*! PTSO21 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) #define GPIO_PSOR_PTSO22_MASK (0x400000U) #define GPIO_PSOR_PTSO22_SHIFT (22U) /*! PTSO22 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) #define GPIO_PSOR_PTSO23_MASK (0x800000U) #define GPIO_PSOR_PTSO23_SHIFT (23U) /*! PTSO23 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) #define GPIO_PSOR_PTSO24_MASK (0x1000000U) #define GPIO_PSOR_PTSO24_SHIFT (24U) /*! PTSO24 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) #define GPIO_PSOR_PTSO25_MASK (0x2000000U) #define GPIO_PSOR_PTSO25_SHIFT (25U) /*! PTSO25 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) #define GPIO_PSOR_PTSO26_MASK (0x4000000U) #define GPIO_PSOR_PTSO26_SHIFT (26U) /*! PTSO26 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) #define GPIO_PSOR_PTSO27_MASK (0x8000000U) #define GPIO_PSOR_PTSO27_SHIFT (27U) /*! PTSO27 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) #define GPIO_PSOR_PTSO28_MASK (0x10000000U) #define GPIO_PSOR_PTSO28_SHIFT (28U) /*! PTSO28 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) #define GPIO_PSOR_PTSO29_MASK (0x20000000U) #define GPIO_PSOR_PTSO29_SHIFT (29U) /*! PTSO29 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) #define GPIO_PSOR_PTSO30_MASK (0x40000000U) #define GPIO_PSOR_PTSO30_SHIFT (30U) /*! PTSO30 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) #define GPIO_PSOR_PTSO31_MASK (0x80000000U) #define GPIO_PSOR_PTSO31_SHIFT (31U) /*! PTSO31 - Port Set Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to logic 1. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 */ #define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) /*! @} */ -/*! @name PCOR - Port Clear Output Register */ +/*! @name PCOR - Port Clear Output */ /*! @{ */ #define GPIO_PCOR_PTCO0_MASK (0x1U) #define GPIO_PCOR_PTCO0_SHIFT (0U) /*! PTCO0 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) #define GPIO_PCOR_PTCO1_MASK (0x2U) #define GPIO_PCOR_PTCO1_SHIFT (1U) /*! PTCO1 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) #define GPIO_PCOR_PTCO2_MASK (0x4U) #define GPIO_PCOR_PTCO2_SHIFT (2U) /*! PTCO2 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) #define GPIO_PCOR_PTCO3_MASK (0x8U) #define GPIO_PCOR_PTCO3_SHIFT (3U) /*! PTCO3 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) #define GPIO_PCOR_PTCO4_MASK (0x10U) #define GPIO_PCOR_PTCO4_SHIFT (4U) /*! PTCO4 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) #define GPIO_PCOR_PTCO5_MASK (0x20U) #define GPIO_PCOR_PTCO5_SHIFT (5U) /*! PTCO5 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) #define GPIO_PCOR_PTCO6_MASK (0x40U) #define GPIO_PCOR_PTCO6_SHIFT (6U) /*! PTCO6 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) #define GPIO_PCOR_PTCO7_MASK (0x80U) #define GPIO_PCOR_PTCO7_SHIFT (7U) /*! PTCO7 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) #define GPIO_PCOR_PTCO8_MASK (0x100U) #define GPIO_PCOR_PTCO8_SHIFT (8U) /*! PTCO8 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) #define GPIO_PCOR_PTCO9_MASK (0x200U) #define GPIO_PCOR_PTCO9_SHIFT (9U) /*! PTCO9 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) #define GPIO_PCOR_PTCO10_MASK (0x400U) #define GPIO_PCOR_PTCO10_SHIFT (10U) /*! PTCO10 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) #define GPIO_PCOR_PTCO11_MASK (0x800U) #define GPIO_PCOR_PTCO11_SHIFT (11U) /*! PTCO11 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) #define GPIO_PCOR_PTCO12_MASK (0x1000U) #define GPIO_PCOR_PTCO12_SHIFT (12U) /*! PTCO12 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) #define GPIO_PCOR_PTCO13_MASK (0x2000U) #define GPIO_PCOR_PTCO13_SHIFT (13U) /*! PTCO13 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) #define GPIO_PCOR_PTCO14_MASK (0x4000U) #define GPIO_PCOR_PTCO14_SHIFT (14U) /*! PTCO14 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) #define GPIO_PCOR_PTCO15_MASK (0x8000U) #define GPIO_PCOR_PTCO15_SHIFT (15U) /*! PTCO15 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) #define GPIO_PCOR_PTCO16_MASK (0x10000U) #define GPIO_PCOR_PTCO16_SHIFT (16U) /*! PTCO16 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) #define GPIO_PCOR_PTCO17_MASK (0x20000U) #define GPIO_PCOR_PTCO17_SHIFT (17U) /*! PTCO17 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) #define GPIO_PCOR_PTCO18_MASK (0x40000U) #define GPIO_PCOR_PTCO18_SHIFT (18U) /*! PTCO18 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) #define GPIO_PCOR_PTCO19_MASK (0x80000U) #define GPIO_PCOR_PTCO19_SHIFT (19U) /*! PTCO19 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) #define GPIO_PCOR_PTCO20_MASK (0x100000U) #define GPIO_PCOR_PTCO20_SHIFT (20U) /*! PTCO20 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) #define GPIO_PCOR_PTCO21_MASK (0x200000U) #define GPIO_PCOR_PTCO21_SHIFT (21U) /*! PTCO21 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) #define GPIO_PCOR_PTCO22_MASK (0x400000U) #define GPIO_PCOR_PTCO22_SHIFT (22U) /*! PTCO22 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) #define GPIO_PCOR_PTCO23_MASK (0x800000U) #define GPIO_PCOR_PTCO23_SHIFT (23U) /*! PTCO23 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) #define GPIO_PCOR_PTCO24_MASK (0x1000000U) #define GPIO_PCOR_PTCO24_SHIFT (24U) /*! PTCO24 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) #define GPIO_PCOR_PTCO25_MASK (0x2000000U) #define GPIO_PCOR_PTCO25_SHIFT (25U) /*! PTCO25 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) #define GPIO_PCOR_PTCO26_MASK (0x4000000U) #define GPIO_PCOR_PTCO26_SHIFT (26U) /*! PTCO26 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) #define GPIO_PCOR_PTCO27_MASK (0x8000000U) #define GPIO_PCOR_PTCO27_SHIFT (27U) /*! PTCO27 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) #define GPIO_PCOR_PTCO28_MASK (0x10000000U) #define GPIO_PCOR_PTCO28_SHIFT (28U) /*! PTCO28 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) #define GPIO_PCOR_PTCO29_MASK (0x20000000U) #define GPIO_PCOR_PTCO29_SHIFT (29U) /*! PTCO29 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) #define GPIO_PCOR_PTCO30_MASK (0x40000000U) #define GPIO_PCOR_PTCO30_SHIFT (30U) /*! PTCO30 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) #define GPIO_PCOR_PTCO31_MASK (0x80000000U) #define GPIO_PCOR_PTCO31_SHIFT (31U) /*! PTCO31 - Port Clear Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0. + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 */ #define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) /*! @} */ -/*! @name PTOR - Port Toggle Output Register */ +/*! @name PTOR - Port Toggle Output */ /*! @{ */ #define GPIO_PTOR_PTTO0_MASK (0x1U) #define GPIO_PTOR_PTTO0_SHIFT (0U) /*! PTTO0 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) #define GPIO_PTOR_PTTO1_MASK (0x2U) #define GPIO_PTOR_PTTO1_SHIFT (1U) /*! PTTO1 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) #define GPIO_PTOR_PTTO2_MASK (0x4U) #define GPIO_PTOR_PTTO2_SHIFT (2U) /*! PTTO2 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) #define GPIO_PTOR_PTTO3_MASK (0x8U) #define GPIO_PTOR_PTTO3_SHIFT (3U) /*! PTTO3 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) #define GPIO_PTOR_PTTO4_MASK (0x10U) #define GPIO_PTOR_PTTO4_SHIFT (4U) /*! PTTO4 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) #define GPIO_PTOR_PTTO5_MASK (0x20U) #define GPIO_PTOR_PTTO5_SHIFT (5U) /*! PTTO5 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) #define GPIO_PTOR_PTTO6_MASK (0x40U) #define GPIO_PTOR_PTTO6_SHIFT (6U) /*! PTTO6 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) #define GPIO_PTOR_PTTO7_MASK (0x80U) #define GPIO_PTOR_PTTO7_SHIFT (7U) /*! PTTO7 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) #define GPIO_PTOR_PTTO8_MASK (0x100U) #define GPIO_PTOR_PTTO8_SHIFT (8U) /*! PTTO8 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) #define GPIO_PTOR_PTTO9_MASK (0x200U) #define GPIO_PTOR_PTTO9_SHIFT (9U) /*! PTTO9 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) #define GPIO_PTOR_PTTO10_MASK (0x400U) #define GPIO_PTOR_PTTO10_SHIFT (10U) /*! PTTO10 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) #define GPIO_PTOR_PTTO11_MASK (0x800U) #define GPIO_PTOR_PTTO11_SHIFT (11U) /*! PTTO11 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) #define GPIO_PTOR_PTTO12_MASK (0x1000U) #define GPIO_PTOR_PTTO12_SHIFT (12U) /*! PTTO12 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) #define GPIO_PTOR_PTTO13_MASK (0x2000U) #define GPIO_PTOR_PTTO13_SHIFT (13U) /*! PTTO13 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) #define GPIO_PTOR_PTTO14_MASK (0x4000U) #define GPIO_PTOR_PTTO14_SHIFT (14U) /*! PTTO14 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) #define GPIO_PTOR_PTTO15_MASK (0x8000U) #define GPIO_PTOR_PTTO15_SHIFT (15U) /*! PTTO15 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) #define GPIO_PTOR_PTTO16_MASK (0x10000U) #define GPIO_PTOR_PTTO16_SHIFT (16U) /*! PTTO16 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) #define GPIO_PTOR_PTTO17_MASK (0x20000U) #define GPIO_PTOR_PTTO17_SHIFT (17U) /*! PTTO17 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) #define GPIO_PTOR_PTTO18_MASK (0x40000U) #define GPIO_PTOR_PTTO18_SHIFT (18U) /*! PTTO18 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) #define GPIO_PTOR_PTTO19_MASK (0x80000U) #define GPIO_PTOR_PTTO19_SHIFT (19U) /*! PTTO19 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) #define GPIO_PTOR_PTTO20_MASK (0x100000U) #define GPIO_PTOR_PTTO20_SHIFT (20U) /*! PTTO20 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) #define GPIO_PTOR_PTTO21_MASK (0x200000U) #define GPIO_PTOR_PTTO21_SHIFT (21U) /*! PTTO21 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) #define GPIO_PTOR_PTTO22_MASK (0x400000U) #define GPIO_PTOR_PTTO22_SHIFT (22U) /*! PTTO22 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) #define GPIO_PTOR_PTTO23_MASK (0x800000U) #define GPIO_PTOR_PTTO23_SHIFT (23U) /*! PTTO23 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) #define GPIO_PTOR_PTTO24_MASK (0x1000000U) #define GPIO_PTOR_PTTO24_SHIFT (24U) /*! PTTO24 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) #define GPIO_PTOR_PTTO25_MASK (0x2000000U) #define GPIO_PTOR_PTTO25_SHIFT (25U) /*! PTTO25 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) #define GPIO_PTOR_PTTO26_MASK (0x4000000U) #define GPIO_PTOR_PTTO26_SHIFT (26U) /*! PTTO26 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) #define GPIO_PTOR_PTTO27_MASK (0x8000000U) #define GPIO_PTOR_PTTO27_SHIFT (27U) /*! PTTO27 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) #define GPIO_PTOR_PTTO28_MASK (0x10000000U) #define GPIO_PTOR_PTTO28_SHIFT (28U) /*! PTTO28 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) #define GPIO_PTOR_PTTO29_MASK (0x20000000U) #define GPIO_PTOR_PTTO29_SHIFT (29U) /*! PTTO29 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) #define GPIO_PTOR_PTTO30_MASK (0x40000000U) #define GPIO_PTOR_PTTO30_SHIFT (30U) /*! PTTO30 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) #define GPIO_PTOR_PTTO31_MASK (0x80000000U) #define GPIO_PTOR_PTTO31_SHIFT (31U) /*! PTTO31 - Port Toggle Output - * 0b0..Corresponding field of PDOR[PDOn] does not change. - * 0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state. + * 0b0..No change + * 0b1..Set to the inverse of its current logic state */ #define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) /*! @} */ -/*! @name PDIR - Port Data Input Register */ +/*! @name PDIR - Port Data Input */ /*! @{ */ #define GPIO_PDIR_PDI0_MASK (0x1U) #define GPIO_PDIR_PDI0_SHIFT (0U) /*! PDI0 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) #define GPIO_PDIR_PDI1_MASK (0x2U) #define GPIO_PDIR_PDI1_SHIFT (1U) /*! PDI1 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) #define GPIO_PDIR_PDI2_MASK (0x4U) #define GPIO_PDIR_PDI2_SHIFT (2U) /*! PDI2 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) #define GPIO_PDIR_PDI3_MASK (0x8U) #define GPIO_PDIR_PDI3_SHIFT (3U) /*! PDI3 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) #define GPIO_PDIR_PDI4_MASK (0x10U) #define GPIO_PDIR_PDI4_SHIFT (4U) /*! PDI4 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) #define GPIO_PDIR_PDI5_MASK (0x20U) #define GPIO_PDIR_PDI5_SHIFT (5U) /*! PDI5 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) #define GPIO_PDIR_PDI6_MASK (0x40U) #define GPIO_PDIR_PDI6_SHIFT (6U) /*! PDI6 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) #define GPIO_PDIR_PDI7_MASK (0x80U) #define GPIO_PDIR_PDI7_SHIFT (7U) /*! PDI7 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) #define GPIO_PDIR_PDI8_MASK (0x100U) #define GPIO_PDIR_PDI8_SHIFT (8U) /*! PDI8 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) #define GPIO_PDIR_PDI9_MASK (0x200U) #define GPIO_PDIR_PDI9_SHIFT (9U) /*! PDI9 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) #define GPIO_PDIR_PDI10_MASK (0x400U) #define GPIO_PDIR_PDI10_SHIFT (10U) /*! PDI10 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) #define GPIO_PDIR_PDI11_MASK (0x800U) #define GPIO_PDIR_PDI11_SHIFT (11U) /*! PDI11 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) #define GPIO_PDIR_PDI12_MASK (0x1000U) #define GPIO_PDIR_PDI12_SHIFT (12U) /*! PDI12 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) #define GPIO_PDIR_PDI13_MASK (0x2000U) #define GPIO_PDIR_PDI13_SHIFT (13U) /*! PDI13 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) #define GPIO_PDIR_PDI14_MASK (0x4000U) #define GPIO_PDIR_PDI14_SHIFT (14U) /*! PDI14 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) #define GPIO_PDIR_PDI15_MASK (0x8000U) #define GPIO_PDIR_PDI15_SHIFT (15U) /*! PDI15 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) #define GPIO_PDIR_PDI16_MASK (0x10000U) #define GPIO_PDIR_PDI16_SHIFT (16U) /*! PDI16 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) #define GPIO_PDIR_PDI17_MASK (0x20000U) #define GPIO_PDIR_PDI17_SHIFT (17U) /*! PDI17 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) #define GPIO_PDIR_PDI18_MASK (0x40000U) #define GPIO_PDIR_PDI18_SHIFT (18U) /*! PDI18 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) #define GPIO_PDIR_PDI19_MASK (0x80000U) #define GPIO_PDIR_PDI19_SHIFT (19U) /*! PDI19 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) #define GPIO_PDIR_PDI20_MASK (0x100000U) #define GPIO_PDIR_PDI20_SHIFT (20U) /*! PDI20 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) #define GPIO_PDIR_PDI21_MASK (0x200000U) #define GPIO_PDIR_PDI21_SHIFT (21U) /*! PDI21 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) #define GPIO_PDIR_PDI22_MASK (0x400000U) #define GPIO_PDIR_PDI22_SHIFT (22U) /*! PDI22 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) #define GPIO_PDIR_PDI23_MASK (0x800000U) #define GPIO_PDIR_PDI23_SHIFT (23U) /*! PDI23 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) #define GPIO_PDIR_PDI24_MASK (0x1000000U) #define GPIO_PDIR_PDI24_SHIFT (24U) /*! PDI24 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) #define GPIO_PDIR_PDI25_MASK (0x2000000U) #define GPIO_PDIR_PDI25_SHIFT (25U) /*! PDI25 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) #define GPIO_PDIR_PDI26_MASK (0x4000000U) #define GPIO_PDIR_PDI26_SHIFT (26U) /*! PDI26 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) #define GPIO_PDIR_PDI27_MASK (0x8000000U) #define GPIO_PDIR_PDI27_SHIFT (27U) /*! PDI27 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) #define GPIO_PDIR_PDI28_MASK (0x10000000U) #define GPIO_PDIR_PDI28_SHIFT (28U) /*! PDI28 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) #define GPIO_PDIR_PDI29_MASK (0x20000000U) #define GPIO_PDIR_PDI29_SHIFT (29U) /*! PDI29 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) #define GPIO_PDIR_PDI30_MASK (0x40000000U) #define GPIO_PDIR_PDI30_SHIFT (30U) /*! PDI30 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) #define GPIO_PDIR_PDI31_MASK (0x80000000U) #define GPIO_PDIR_PDI31_SHIFT (31U) /*! PDI31 - Port Data Input - * 0b0..Pin logic level is logic 0 or is not configured for use by digital function. - * 0b1..Pin logic level is logic 1. + * 0b0..Logic 0 + * 0b1..Logic 1 */ #define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) /*! @} */ -/*! @name PDDR - Port Data Direction Register */ +/*! @name PDDR - Port Data Direction */ /*! @{ */ #define GPIO_PDDR_PDD0_MASK (0x1U) #define GPIO_PDDR_PDD0_SHIFT (0U) /*! PDD0 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) #define GPIO_PDDR_PDD1_MASK (0x2U) #define GPIO_PDDR_PDD1_SHIFT (1U) /*! PDD1 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) #define GPIO_PDDR_PDD2_MASK (0x4U) #define GPIO_PDDR_PDD2_SHIFT (2U) /*! PDD2 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) #define GPIO_PDDR_PDD3_MASK (0x8U) #define GPIO_PDDR_PDD3_SHIFT (3U) /*! PDD3 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) #define GPIO_PDDR_PDD4_MASK (0x10U) #define GPIO_PDDR_PDD4_SHIFT (4U) /*! PDD4 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) #define GPIO_PDDR_PDD5_MASK (0x20U) #define GPIO_PDDR_PDD5_SHIFT (5U) /*! PDD5 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) #define GPIO_PDDR_PDD6_MASK (0x40U) #define GPIO_PDDR_PDD6_SHIFT (6U) /*! PDD6 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) #define GPIO_PDDR_PDD7_MASK (0x80U) #define GPIO_PDDR_PDD7_SHIFT (7U) /*! PDD7 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) #define GPIO_PDDR_PDD8_MASK (0x100U) #define GPIO_PDDR_PDD8_SHIFT (8U) /*! PDD8 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) #define GPIO_PDDR_PDD9_MASK (0x200U) #define GPIO_PDDR_PDD9_SHIFT (9U) /*! PDD9 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) #define GPIO_PDDR_PDD10_MASK (0x400U) #define GPIO_PDDR_PDD10_SHIFT (10U) /*! PDD10 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) #define GPIO_PDDR_PDD11_MASK (0x800U) #define GPIO_PDDR_PDD11_SHIFT (11U) /*! PDD11 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) #define GPIO_PDDR_PDD12_MASK (0x1000U) #define GPIO_PDDR_PDD12_SHIFT (12U) /*! PDD12 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) #define GPIO_PDDR_PDD13_MASK (0x2000U) #define GPIO_PDDR_PDD13_SHIFT (13U) /*! PDD13 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) #define GPIO_PDDR_PDD14_MASK (0x4000U) #define GPIO_PDDR_PDD14_SHIFT (14U) /*! PDD14 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) #define GPIO_PDDR_PDD15_MASK (0x8000U) #define GPIO_PDDR_PDD15_SHIFT (15U) /*! PDD15 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) #define GPIO_PDDR_PDD16_MASK (0x10000U) #define GPIO_PDDR_PDD16_SHIFT (16U) /*! PDD16 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) #define GPIO_PDDR_PDD17_MASK (0x20000U) #define GPIO_PDDR_PDD17_SHIFT (17U) /*! PDD17 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) #define GPIO_PDDR_PDD18_MASK (0x40000U) #define GPIO_PDDR_PDD18_SHIFT (18U) /*! PDD18 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) #define GPIO_PDDR_PDD19_MASK (0x80000U) #define GPIO_PDDR_PDD19_SHIFT (19U) /*! PDD19 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) #define GPIO_PDDR_PDD20_MASK (0x100000U) #define GPIO_PDDR_PDD20_SHIFT (20U) /*! PDD20 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) #define GPIO_PDDR_PDD21_MASK (0x200000U) #define GPIO_PDDR_PDD21_SHIFT (21U) /*! PDD21 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) #define GPIO_PDDR_PDD22_MASK (0x400000U) #define GPIO_PDDR_PDD22_SHIFT (22U) /*! PDD22 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) #define GPIO_PDDR_PDD23_MASK (0x800000U) #define GPIO_PDDR_PDD23_SHIFT (23U) /*! PDD23 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) #define GPIO_PDDR_PDD24_MASK (0x1000000U) #define GPIO_PDDR_PDD24_SHIFT (24U) /*! PDD24 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) #define GPIO_PDDR_PDD25_MASK (0x2000000U) #define GPIO_PDDR_PDD25_SHIFT (25U) /*! PDD25 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) #define GPIO_PDDR_PDD26_MASK (0x4000000U) #define GPIO_PDDR_PDD26_SHIFT (26U) /*! PDD26 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) #define GPIO_PDDR_PDD27_MASK (0x8000000U) #define GPIO_PDDR_PDD27_SHIFT (27U) /*! PDD27 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) #define GPIO_PDDR_PDD28_MASK (0x10000000U) #define GPIO_PDDR_PDD28_SHIFT (28U) /*! PDD28 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) #define GPIO_PDDR_PDD29_MASK (0x20000000U) #define GPIO_PDDR_PDD29_SHIFT (29U) /*! PDD29 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) #define GPIO_PDDR_PDD30_MASK (0x40000000U) #define GPIO_PDDR_PDD30_SHIFT (30U) /*! PDD30 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) #define GPIO_PDDR_PDD31_MASK (0x80000000U) #define GPIO_PDDR_PDD31_SHIFT (31U) /*! PDD31 - Port Data Direction - * 0b0..Pin is configured as general-purpose input for the GPIO function. - * 0b1..Pin is configured as general-purpose output for the GPIO function. + * 0b0..Input + * 0b1..Output */ #define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) /*! @} */ -/*! @name PIDR - Port Input Disable Register */ +/*! @name PIDR - Port Input Disable */ /*! @{ */ #define GPIO_PIDR_PID0_MASK (0x1U) #define GPIO_PIDR_PID0_SHIFT (0U) /*! PID0 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) #define GPIO_PIDR_PID1_MASK (0x2U) #define GPIO_PIDR_PID1_SHIFT (1U) /*! PID1 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) #define GPIO_PIDR_PID2_MASK (0x4U) #define GPIO_PIDR_PID2_SHIFT (2U) /*! PID2 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) #define GPIO_PIDR_PID3_MASK (0x8U) #define GPIO_PIDR_PID3_SHIFT (3U) /*! PID3 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) #define GPIO_PIDR_PID4_MASK (0x10U) #define GPIO_PIDR_PID4_SHIFT (4U) /*! PID4 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) #define GPIO_PIDR_PID5_MASK (0x20U) #define GPIO_PIDR_PID5_SHIFT (5U) /*! PID5 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) #define GPIO_PIDR_PID6_MASK (0x40U) #define GPIO_PIDR_PID6_SHIFT (6U) /*! PID6 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) #define GPIO_PIDR_PID7_MASK (0x80U) #define GPIO_PIDR_PID7_SHIFT (7U) /*! PID7 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) #define GPIO_PIDR_PID8_MASK (0x100U) #define GPIO_PIDR_PID8_SHIFT (8U) /*! PID8 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) #define GPIO_PIDR_PID9_MASK (0x200U) #define GPIO_PIDR_PID9_SHIFT (9U) /*! PID9 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) #define GPIO_PIDR_PID10_MASK (0x400U) #define GPIO_PIDR_PID10_SHIFT (10U) /*! PID10 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) #define GPIO_PIDR_PID11_MASK (0x800U) #define GPIO_PIDR_PID11_SHIFT (11U) /*! PID11 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) #define GPIO_PIDR_PID12_MASK (0x1000U) #define GPIO_PIDR_PID12_SHIFT (12U) /*! PID12 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) #define GPIO_PIDR_PID13_MASK (0x2000U) #define GPIO_PIDR_PID13_SHIFT (13U) /*! PID13 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) #define GPIO_PIDR_PID14_MASK (0x4000U) #define GPIO_PIDR_PID14_SHIFT (14U) /*! PID14 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) #define GPIO_PIDR_PID15_MASK (0x8000U) #define GPIO_PIDR_PID15_SHIFT (15U) /*! PID15 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) #define GPIO_PIDR_PID16_MASK (0x10000U) #define GPIO_PIDR_PID16_SHIFT (16U) /*! PID16 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) #define GPIO_PIDR_PID17_MASK (0x20000U) #define GPIO_PIDR_PID17_SHIFT (17U) /*! PID17 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) #define GPIO_PIDR_PID18_MASK (0x40000U) #define GPIO_PIDR_PID18_SHIFT (18U) /*! PID18 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) #define GPIO_PIDR_PID19_MASK (0x80000U) #define GPIO_PIDR_PID19_SHIFT (19U) /*! PID19 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) #define GPIO_PIDR_PID20_MASK (0x100000U) #define GPIO_PIDR_PID20_SHIFT (20U) /*! PID20 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) #define GPIO_PIDR_PID21_MASK (0x200000U) #define GPIO_PIDR_PID21_SHIFT (21U) /*! PID21 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) #define GPIO_PIDR_PID22_MASK (0x400000U) #define GPIO_PIDR_PID22_SHIFT (22U) /*! PID22 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) #define GPIO_PIDR_PID23_MASK (0x800000U) #define GPIO_PIDR_PID23_SHIFT (23U) /*! PID23 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) #define GPIO_PIDR_PID24_MASK (0x1000000U) #define GPIO_PIDR_PID24_SHIFT (24U) /*! PID24 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) #define GPIO_PIDR_PID25_MASK (0x2000000U) #define GPIO_PIDR_PID25_SHIFT (25U) /*! PID25 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) #define GPIO_PIDR_PID26_MASK (0x4000000U) #define GPIO_PIDR_PID26_SHIFT (26U) /*! PID26 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) #define GPIO_PIDR_PID27_MASK (0x8000000U) #define GPIO_PIDR_PID27_SHIFT (27U) /*! PID27 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) #define GPIO_PIDR_PID28_MASK (0x10000000U) #define GPIO_PIDR_PID28_SHIFT (28U) /*! PID28 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) #define GPIO_PIDR_PID29_MASK (0x20000000U) #define GPIO_PIDR_PID29_SHIFT (29U) /*! PID29 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) #define GPIO_PIDR_PID30_MASK (0x40000000U) #define GPIO_PIDR_PID30_SHIFT (30U) /*! PID30 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) #define GPIO_PIDR_PID31_MASK (0x80000000U) #define GPIO_PIDR_PID31_SHIFT (31U) /*! PID31 - Port Input Disable - * 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function. - * 0b1..Pin is disabled for general-purpose input. + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input */ #define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) /*! @} */ -/*! @name PDR - Pin Data Register a */ +/*! @name PDR - Pin Data */ /*! @{ */ #define GPIO_PDR_PD_MASK (0x1U) #define GPIO_PDR_PD_SHIFT (0U) -/*! PD - Pin Data (input and output) - * 0b0..Pin logic level is logic zero or not configured for use by digital function. - * 0b1..Pin logic level is logic one. +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one */ #define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) /*! @} */ @@ -31325,57 +31325,56 @@ typedef struct { /* The count of GPIO_PDR */ #define GPIO_PDR_COUNT (32U) -/*! @name ICR - Interrupt Control Register 0..Interrupt Control Register 31 */ +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ /*! @{ */ #define GPIO_ICR_IRQC_MASK (0xF0000U) #define GPIO_ICR_IRQC_SHIFT (16U) /*! IRQC - Interrupt Configuration - * 0b0000..Interrupt Status Flag (ISF) is disabled. - * 0b0001..ISF flag and DMA request on rising edge. - * 0b0010..ISF flag and DMA request on falling edge. - * 0b0011..ISF flag and DMA request on either edge. - * 0b0100..Reserved. - * 0b0101..ISF flag sets on rising edge. - * 0b0110..ISF flag sets on falling edge. - * 0b0111..ISF flag sets on either edge. - * 0b1000..ISF flag and Interrupt when logic 0. - * 0b1001..ISF flag and Interrupt on rising-edge. - * 0b1010..ISF flag and Interrupt on falling-edge. - * 0b1011..ISF flag and Interrupt on either edge. - * 0b1100..ISF flag and Interrupt when logic 1. - * 0b1101..Enable active high trigger output, ISF flag on rising edge. Pin state is ORed with other enabled - * triggers to generate the output trigger, for use by other peripherals. - * 0b1110..Enable active low trigger output, ISF flag on falling edge. Pin state is inverted and ORed with other - * enabled triggers to generate the output trigger, for use by other peripherals. - * 0b1111..Reserved. + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved */ #define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) #define GPIO_ICR_IRQS_MASK (0x100000U) #define GPIO_ICR_IRQS_SHIFT (20U) /*! IRQS - Interrupt Select - * 0b0..Interrupt/trigger output/DMA request 0. - * 0b1..Interrupt/trigger output/DMA request 1. + * 0b0..Interrupt, trigger output, or DMA request 0 + * 0b1..Interrupt, trigger output, or DMA request 1 */ #define GPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK) #define GPIO_ICR_LK_MASK (0x800000U) #define GPIO_ICR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Interrupt configuration by ICR[23:0] is not locked and can be updated. - * 0b1..Interrupt configuration by ICR[23:0] is locked and cannot be updated until next system reset. +/*! LK - Lock + * 0b0..Lock + * 0b1..Do not lock */ #define GPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK) #define GPIO_ICR_ISF_MASK (0x1000000U) #define GPIO_ICR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag - * 0b0..Configured interrupt is not detected. - * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the - * corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the - * flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive - * interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) /*! @} */ @@ -31383,134 +31382,134 @@ typedef struct { /* The count of GPIO_ICR */ #define GPIO_ICR_COUNT (32U) -/*! @name GICLR - Global Interrupt Control Low Register */ +/*! @name GICLR - Global Interrupt Control Low */ /*! @{ */ #define GPIO_GICLR_GIWE0_MASK (0x1U) #define GPIO_GICLR_GIWE0_SHIFT (0U) /*! GIWE0 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) #define GPIO_GICLR_GIWE1_MASK (0x2U) #define GPIO_GICLR_GIWE1_SHIFT (1U) /*! GIWE1 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) #define GPIO_GICLR_GIWE2_MASK (0x4U) #define GPIO_GICLR_GIWE2_SHIFT (2U) /*! GIWE2 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) #define GPIO_GICLR_GIWE3_MASK (0x8U) #define GPIO_GICLR_GIWE3_SHIFT (3U) /*! GIWE3 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) #define GPIO_GICLR_GIWE4_MASK (0x10U) #define GPIO_GICLR_GIWE4_SHIFT (4U) /*! GIWE4 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) #define GPIO_GICLR_GIWE5_MASK (0x20U) #define GPIO_GICLR_GIWE5_SHIFT (5U) /*! GIWE5 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) #define GPIO_GICLR_GIWE6_MASK (0x40U) #define GPIO_GICLR_GIWE6_SHIFT (6U) /*! GIWE6 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) #define GPIO_GICLR_GIWE7_MASK (0x80U) #define GPIO_GICLR_GIWE7_SHIFT (7U) /*! GIWE7 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) #define GPIO_GICLR_GIWE8_MASK (0x100U) #define GPIO_GICLR_GIWE8_SHIFT (8U) /*! GIWE8 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) #define GPIO_GICLR_GIWE9_MASK (0x200U) #define GPIO_GICLR_GIWE9_SHIFT (9U) /*! GIWE9 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) #define GPIO_GICLR_GIWE10_MASK (0x400U) #define GPIO_GICLR_GIWE10_SHIFT (10U) /*! GIWE10 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) #define GPIO_GICLR_GIWE11_MASK (0x800U) #define GPIO_GICLR_GIWE11_SHIFT (11U) /*! GIWE11 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) #define GPIO_GICLR_GIWE12_MASK (0x1000U) #define GPIO_GICLR_GIWE12_SHIFT (12U) /*! GIWE12 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) #define GPIO_GICLR_GIWE13_MASK (0x2000U) #define GPIO_GICLR_GIWE13_SHIFT (13U) /*! GIWE13 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) #define GPIO_GICLR_GIWE14_MASK (0x4000U) #define GPIO_GICLR_GIWE14_SHIFT (14U) /*! GIWE14 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) #define GPIO_GICLR_GIWE15_MASK (0x8000U) #define GPIO_GICLR_GIWE15_SHIFT (15U) /*! GIWE15 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated + * 0b1..Updated */ #define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) @@ -31520,134 +31519,134 @@ typedef struct { #define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) /*! @} */ -/*! @name GICHR - Global Interrupt Control High Register */ +/*! @name GICHR - Global Interrupt Control High */ /*! @{ */ #define GPIO_GICHR_GIWE16_MASK (0x1U) #define GPIO_GICHR_GIWE16_SHIFT (0U) /*! GIWE16 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) #define GPIO_GICHR_GIWE17_MASK (0x2U) #define GPIO_GICHR_GIWE17_SHIFT (1U) /*! GIWE17 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) #define GPIO_GICHR_GIWE18_MASK (0x4U) #define GPIO_GICHR_GIWE18_SHIFT (2U) /*! GIWE18 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) #define GPIO_GICHR_GIWE19_MASK (0x8U) #define GPIO_GICHR_GIWE19_SHIFT (3U) /*! GIWE19 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) #define GPIO_GICHR_GIWE20_MASK (0x10U) #define GPIO_GICHR_GIWE20_SHIFT (4U) /*! GIWE20 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) #define GPIO_GICHR_GIWE21_MASK (0x20U) #define GPIO_GICHR_GIWE21_SHIFT (5U) /*! GIWE21 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) #define GPIO_GICHR_GIWE22_MASK (0x40U) #define GPIO_GICHR_GIWE22_SHIFT (6U) /*! GIWE22 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) #define GPIO_GICHR_GIWE23_MASK (0x80U) #define GPIO_GICHR_GIWE23_SHIFT (7U) /*! GIWE23 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) #define GPIO_GICHR_GIWE24_MASK (0x100U) #define GPIO_GICHR_GIWE24_SHIFT (8U) /*! GIWE24 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) #define GPIO_GICHR_GIWE25_MASK (0x200U) #define GPIO_GICHR_GIWE25_SHIFT (9U) /*! GIWE25 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) #define GPIO_GICHR_GIWE26_MASK (0x400U) #define GPIO_GICHR_GIWE26_SHIFT (10U) /*! GIWE26 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) #define GPIO_GICHR_GIWE27_MASK (0x800U) #define GPIO_GICHR_GIWE27_SHIFT (11U) /*! GIWE27 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) #define GPIO_GICHR_GIWE28_MASK (0x1000U) #define GPIO_GICHR_GIWE28_SHIFT (12U) /*! GIWE28 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) #define GPIO_GICHR_GIWE29_MASK (0x2000U) #define GPIO_GICHR_GIWE29_SHIFT (13U) /*! GIWE29 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) #define GPIO_GICHR_GIWE30_MASK (0x4000U) #define GPIO_GICHR_GIWE30_SHIFT (14U) /*! GIWE30 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) #define GPIO_GICHR_GIWE31_MASK (0x8000U) #define GPIO_GICHR_GIWE31_SHIFT (15U) /*! GIWE31 - Global Interrupt Write Enable - * 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD. - * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD. + * 0b0..Not updated. + * 0b1..Updated */ #define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) @@ -31657,390 +31656,326 @@ typedef struct { #define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) /*! @} */ -/*! @name ISFR - Interrupt Status Flag Register */ +/*! @name ISFR - Interrupt Status Flag */ /*! @{ */ #define GPIO_ISFR_ISF0_MASK (0x1U) #define GPIO_ISFR_ISF0_SHIFT (0U) /*! ISF0 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) #define GPIO_ISFR_ISF1_MASK (0x2U) #define GPIO_ISFR_ISF1_SHIFT (1U) /*! ISF1 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) #define GPIO_ISFR_ISF2_MASK (0x4U) #define GPIO_ISFR_ISF2_SHIFT (2U) /*! ISF2 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) #define GPIO_ISFR_ISF3_MASK (0x8U) #define GPIO_ISFR_ISF3_SHIFT (3U) /*! ISF3 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) #define GPIO_ISFR_ISF4_MASK (0x10U) #define GPIO_ISFR_ISF4_SHIFT (4U) /*! ISF4 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) #define GPIO_ISFR_ISF5_MASK (0x20U) #define GPIO_ISFR_ISF5_SHIFT (5U) /*! ISF5 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) #define GPIO_ISFR_ISF6_MASK (0x40U) #define GPIO_ISFR_ISF6_SHIFT (6U) /*! ISF6 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) #define GPIO_ISFR_ISF7_MASK (0x80U) #define GPIO_ISFR_ISF7_SHIFT (7U) /*! ISF7 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) #define GPIO_ISFR_ISF8_MASK (0x100U) #define GPIO_ISFR_ISF8_SHIFT (8U) /*! ISF8 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) #define GPIO_ISFR_ISF9_MASK (0x200U) #define GPIO_ISFR_ISF9_SHIFT (9U) /*! ISF9 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) #define GPIO_ISFR_ISF10_MASK (0x400U) #define GPIO_ISFR_ISF10_SHIFT (10U) /*! ISF10 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) #define GPIO_ISFR_ISF11_MASK (0x800U) #define GPIO_ISFR_ISF11_SHIFT (11U) /*! ISF11 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) #define GPIO_ISFR_ISF12_MASK (0x1000U) #define GPIO_ISFR_ISF12_SHIFT (12U) /*! ISF12 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) #define GPIO_ISFR_ISF13_MASK (0x2000U) #define GPIO_ISFR_ISF13_SHIFT (13U) /*! ISF13 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) #define GPIO_ISFR_ISF14_MASK (0x4000U) #define GPIO_ISFR_ISF14_SHIFT (14U) /*! ISF14 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) #define GPIO_ISFR_ISF15_MASK (0x8000U) #define GPIO_ISFR_ISF15_SHIFT (15U) /*! ISF15 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) #define GPIO_ISFR_ISF16_MASK (0x10000U) #define GPIO_ISFR_ISF16_SHIFT (16U) /*! ISF16 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) #define GPIO_ISFR_ISF17_MASK (0x20000U) #define GPIO_ISFR_ISF17_SHIFT (17U) /*! ISF17 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) #define GPIO_ISFR_ISF18_MASK (0x40000U) #define GPIO_ISFR_ISF18_SHIFT (18U) /*! ISF18 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) #define GPIO_ISFR_ISF19_MASK (0x80000U) #define GPIO_ISFR_ISF19_SHIFT (19U) /*! ISF19 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) #define GPIO_ISFR_ISF20_MASK (0x100000U) #define GPIO_ISFR_ISF20_SHIFT (20U) /*! ISF20 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) #define GPIO_ISFR_ISF21_MASK (0x200000U) #define GPIO_ISFR_ISF21_SHIFT (21U) /*! ISF21 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) #define GPIO_ISFR_ISF22_MASK (0x400000U) #define GPIO_ISFR_ISF22_SHIFT (22U) /*! ISF22 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) #define GPIO_ISFR_ISF23_MASK (0x800000U) #define GPIO_ISFR_ISF23_SHIFT (23U) /*! ISF23 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) #define GPIO_ISFR_ISF24_MASK (0x1000000U) #define GPIO_ISFR_ISF24_SHIFT (24U) /*! ISF24 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) #define GPIO_ISFR_ISF25_MASK (0x2000000U) #define GPIO_ISFR_ISF25_SHIFT (25U) /*! ISF25 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) #define GPIO_ISFR_ISF26_MASK (0x4000000U) #define GPIO_ISFR_ISF26_SHIFT (26U) /*! ISF26 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) #define GPIO_ISFR_ISF27_MASK (0x8000000U) #define GPIO_ISFR_ISF27_SHIFT (27U) /*! ISF27 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) #define GPIO_ISFR_ISF28_MASK (0x10000000U) #define GPIO_ISFR_ISF28_SHIFT (28U) /*! ISF28 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) #define GPIO_ISFR_ISF29_MASK (0x20000000U) #define GPIO_ISFR_ISF29_SHIFT (29U) /*! ISF29 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) #define GPIO_ISFR_ISF30_MASK (0x40000000U) #define GPIO_ISFR_ISF30_SHIFT (30U) /*! ISF30 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) #define GPIO_ISFR_ISF31_MASK (0x80000000U) #define GPIO_ISFR_ISF31_SHIFT (31U) /*! ISF31 - Interrupt Status Flag - * 0b0..Configured interrupt is not detected on the pin of the same number. - * 0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a - * DMA request, then the corresponding flag will be cleared automatically at the completion of the requested - * DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is - * configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately - * after it is cleared. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) /*! @} */ @@ -32153,13 +32088,17 @@ typedef struct { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO0_ALIAS1_BASE, GPIO1_BASE, GPIO1_ALIAS1_BASE, GPIO2_BASE, GPIO2_ALIAS1_BASE, GPIO3_BASE, GPIO3_ALIAS1_BASE, GPIO4_BASE, GPIO4_ALIAS1_BASE, GPIO5_BASE, GPIO5_ALIAS1_BASE } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS { GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5, GPIO5_ALIAS1 } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } /** Array initializer of GPIO peripheral base addresses */ - #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO0_ALIAS1_BASE_NS, GPIO1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_BASE_NS, GPIO5_ALIAS1_BASE_NS } + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } + #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } /** Array initializer of GPIO peripheral base pointers */ - #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO0_ALIAS1_NS, GPIO1_NS, GPIO1_ALIAS1_NS, GPIO2_NS, GPIO2_ALIAS1_NS, GPIO3_NS, GPIO3_ALIAS1_NS, GPIO4_NS, GPIO4_ALIAS1_NS, GPIO5_NS, GPIO5_ALIAS1_NS } + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } + #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } #else /** Peripheral GPIO0 base address */ #define GPIO0_BASE (0x40096000u) @@ -32210,24 +32149,11 @@ typedef struct { /** Peripheral GPIO5_ALIAS1 base pointer */ #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) /** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS \ - { \ - GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE \ - } -#define GPIO_ALIAS1_BASE_ADDRS \ - { \ - GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, \ - GPIO5_ALIAS1_BASE \ - } + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } /** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS \ - { \ - GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 \ - } -#define GPIO_ALIAS1_BASE_PTRS \ - { \ - GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 \ - } + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } #endif /* Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn} @@ -32333,7 +32259,7 @@ typedef struct { #define HPDAC_GCR_FIFOEN_MASK (0x8U) #define HPDAC_GCR_FIFOEN_SHIFT (3U) /*! FIFOEN - FIFO Enable - * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to goes to buffer then goes to conversion. + * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. */ #define HPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << HPDAC_GCR_FIFOEN_SHIFT)) & HPDAC_GCR_FIFOEN_MASK) @@ -32675,7 +32601,7 @@ typedef struct { #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard feature set. + * 0b0000000000000000..Standard feature set */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) @@ -32695,7 +32621,7 @@ typedef struct { #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) -/*! DATALINE - Number of Datalinks */ +/*! DATALINE - Number of Data Lines */ #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) #define I2S_PARAM_FIFO_MASK (0xF00U) @@ -32715,96 +32641,102 @@ typedef struct { #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables the DMA warning. - * 0b1..Enables the DMA warning. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag - * 0b0..Transmit FIFO watermark has not been reached. - * 0b1..Transmit FIFO watermark has been reached. + * 0b0..Watermark not reached + * 0b1..Watermark reached */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag - * 0b0..No enabled transmit FIFO is empty. - * 0b1..Enabled transmit FIFO is empty. + * 0b0..Not empty + * 0b1..Empty */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag - * 0b0..Transmit underrun not detected. - * 0b1..Transmit underrun detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) @@ -32819,40 +32751,40 @@ typedef struct { #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. + * 0b0..No effect + * 0b1..FIFO reset */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable - * 0b0..Transmit bit clock is disabled. - * 0b1..Transmit bit clock is enabled. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable - * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. - * 0b1..Transmitter is enabled in Debug mode. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable - * 0b0..Transmitter disabled in Stop mode. - * 0b1..Transmitter enabled in Stop mode. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable - * 0b0..Transmitter is disabled. - * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ @@ -32863,10 +32795,10 @@ typedef struct { #define I2S_TCR1_TFW_MASK (0x7U) #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark - * 0b000..1 FIFO word - * 0b001..2 FIFO words - * 0b010-0b110..(TFW +1) FIFO words - * 0b111..8 FIFO words + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(TFW +1) + * 0b111..8 */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ @@ -32882,50 +32814,50 @@ typedef struct { #define I2S_TCR2_BYP_MASK (0x800000U) #define I2S_TCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass - * 0b0..Internal bit clock is generated from bit clock divider. - * 0b1..Internal bit clock is divide-by-one of the audio master clock. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity - * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + * 0b0..Active high + * 0b1..Active low */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. + * 0b0..Disable + * 0b1..Enable */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) @@ -32965,48 +32897,48 @@ typedef struct { #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction - * 0b0..Frame sync is generated externally in Slave mode. - * 0b1..Frame sync is generated internally in Master mode. + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. + * 0b0..Active high + * 0b1..Active low */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is 0. +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First - * 0b0..LSB is transmitted first. - * 0b1..MSB is transmitted first. + * 0b0..LSB + * 0b1..MSB */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode - * 0b0..TDM mode, transmit data pins are 3-stated when slots are masked or channels are disabled. - * 0b1..Output mode, transmit data pins are never 3-stated and output zero when slots are masked or channels are disabled. + * 0b0..TDM mode + * 0b1..Output mode */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) @@ -33017,34 +32949,34 @@ typedef struct { #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) -/*! FRSZ - Frame size */ +/*! FRSZ - Frame Size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled. + * 0b00..Disable FIFO packing * 0b01..Reserved - * 0b10..8-bit FIFO packing is enabled. - * 0b11..16-bit FIFO packing is enabled. + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode - * 0b00..FIFO Combine mode disabled. - * 0b01..FIFO Combine mode enabled on FIFO reads (from transmit shift registers). - * 0b10..FIFO Combine mode enabled on FIFO writes (by software). - * 0b11..FIFO Combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, SAI continues from the start of the next frame after the FIFO error flag has been cleared. - * 0b1..On FIFO error, SAI continues from the same word that caused the FIFO error to become 1 after the FIFO warning flag returns to 0. + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ @@ -33055,29 +32987,29 @@ typedef struct { #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted - * 0b00000..Bit index is 0. - * 0b00001-0b11110..Bit index is FBT value. - * 0b11111..Bit index is 31. + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width - * 0b00111..8 bits per word - * 0b01000..9 bits per word - * 0b01001-0b11110..(W0W value + 1) bits per word - * 0b11111..32 bits per word + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width - * 0b00111..8 bits per word - * 0b01000..9 bits per word - * 0b01001-0b11110..(WNW value + 1) bits per word - * 0b11111..32 bits per word + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 */ #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ @@ -33087,7 +33019,7 @@ typedef struct { #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) -/*! TDR - Transmit Data Register */ +/*! TDR - Transmit Data */ #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ @@ -33111,7 +33043,7 @@ typedef struct { #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer * 0b0..No effect - * 0b1..FIFO Combine mode is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + * 0b1..Next FIFO to be written */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) /*! @} */ @@ -33125,8 +33057,8 @@ typedef struct { #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are 3-stated or drive zero when masked. + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ @@ -33137,144 +33069,150 @@ typedef struct { #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables DMA warnings. - * 0b1..Enables DMA warnings. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag - * 0b0..Receive FIFO watermark not reached. - * 0b1..Receive FIFO watermark has been reached. + * 0b0..Watermark not reached + * 0b1..Watermark reached */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag - * 0b0..No enabled receive FIFO is full. - * 0b1..Enabled receive FIFO is full. + * 0b0..Not full + * 0b1..Full */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag - * 0b0..Receive overflow not detected. - * 0b1..Receive overflow detected. + * 0b0..No error + * 0b1..Receive overflow detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset - * 0b0..No effect. - * 0b1..Software reset. + * 0b0..No effect + * 0b1..Software reset */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. + * 0b0..No effect + * 0b1..Reset */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable - * 0b0..Receive bit clock is disabled. - * 0b1..Receive bit clock is enabled. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable - * 0b0..Receiver is disabled in Debug mode, after completing the current frame. - * 0b1..Receiver is enabled in Debug mode. + * 0b0..Disable after completing the current frame + * 0b1..Enable */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable - * 0b0..Receiver disabled in Stop mode. - * 0b1..Receiver enabled in Stop mode. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable - * 0b0..Receiver is disabled. - * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ @@ -33285,10 +33223,10 @@ typedef struct { #define I2S_RCR1_RFW_MASK (0x7U) #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark - * 0b000..1 FIFO word - * 0b001..2 FIFO words - * 0b010-0b110..(RFW value + 1) FIFO words - * 0b111..8 FIFO words + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(RFW value + 1) + * 0b111..8 */ #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ @@ -33304,50 +33242,50 @@ typedef struct { #define I2S_RCR2_BYP_MASK (0x800000U) #define I2S_RCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass - * 0b0..Internal bit clock is generated from bit clock divider. - * 0b1..Internal bit clock is divide-by-one of the audio master clock. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity - * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + * 0b0..Active high + * 0b1..Active low */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. + * 0b0..Disable + * 0b1..Enable */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) @@ -33392,88 +33330,88 @@ typedef struct { #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction - * 0b0..Frame Sync is generated externally in Slave mode. - * 0b1..Frame Sync is generated internally in Master mode. + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. + * 0b0..Active high + * 0b1..Active low */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is 0. +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First - * 0b0..LSB is received first. - * 0b1..MSB is received first. + * 0b0..LSB + * 0b1..MSB */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width - * 0b00000..1 bit-clock cycle - * 0b00001..2 bit-clock cycle - * 0b00010-0b11110..(SYWD value + 1) bit-clock cycle - * 0b11111..32 bit-clock cycle + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size - * 0b00000..1 word per frame - * 0b00001..2 words per frame - * 0b00010-0b11110..(FRSZ value + 1) words per frame - * 0b11111..32 words per frame + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled + * 0b00..Disable * 0b01..Reserved - * 0b10..8-bit FIFO packing is enabled - * 0b11..16-bit FIFO packing is enabled + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode - * 0b00..FIFO Combine mode disabled. - * 0b01..FIFO Combine mode enabled on FIFO writes (from receive shift registers). - * 0b10..FIFO Combine mode enabled on FIFO reads (by software). - * 0b11..FIFO Combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, SAI continues from the start of the next frame after the FIFO error flag returns to 0. - * 0b1..On FIFO error, SAI continues from the same word that caused the FIFO error to become 1 after the FIFO warning flag returns to 0. + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ @@ -33484,29 +33422,29 @@ typedef struct { #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted - * 0b00000..Bit index is 0. - * 0b00001-0b11110..Bit index is FBT value. - * 0b11111..Bit index is 31. + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width - * 0b00000..1 bit per word - * 0b00001..2 bits per word - * 0b00010-0b11110..(W0W value + 1) bits per word - * 0b11111..32 bits per word + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width - * 0b00111..8 bits per word - * 0b01000..9 bits per word - * 0b01001-0b11110..(WNW value + 1) bits per word - * 0b11111..32 bits per word + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 */ #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ @@ -33516,7 +33454,7 @@ typedef struct { #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) -/*! RDR - Receive Data Register */ +/*! RDR - Receive Data */ #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ @@ -33533,9 +33471,9 @@ typedef struct { #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) -/*! RCP - Receive Channel Pointer - * 0b0..No effect. - * 0b1..FIFO Combine mode is enabled for FIFO reads and this FIFO will be read on the next FIFO read. +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) @@ -33554,8 +33492,8 @@ typedef struct { #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @} */ @@ -33571,26 +33509,26 @@ typedef struct { #define I2S_MCR_DIVEN_MASK (0x800000U) #define I2S_MCR_DIVEN_SHIFT (23U) /*! DIVEN - MCLK Post Divide Enable - * 0b0..Output on MCLK signal pin is the audio master clock. - * 0b1..Output on MCLK signal pin is a post-divided version of audio master clock. + * 0b0..Disable + * 0b1..Enable */ #define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) #define I2S_MCR_MSEL_MASK (0x3000000U) #define I2S_MCR_MSEL_SHIFT (24U) /*! MSEL - MCLK Select - * 0b00..Master Clock (MCLK) 1 option selected. + * 0b00..Controller clock (MCLK) option 1 * 0b01..Reserved - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 */ #define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) /*! MOE - MCLK Output Enable - * 0b0..MCLK signal pin is an input. - * 0b1..MCLK signal pin is an output. + * 0b0..Input + * 0b1..Output */ #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) /*! @} */ @@ -33674,13 +33612,13 @@ typedef struct { __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ - __O uint32_t SWDATAH; /**< Target Write Data Half-word, offset: 0x38 */ - __O uint32_t SWDATAHE; /**< Target Write Data Half-word End, offset: 0x3C */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ uint8_t RESERVED_1[4]; __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ uint8_t RESERVED_2[8]; - __IO uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ uint8_t RESERVED_3[4]; __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ @@ -33709,7 +33647,7 @@ typedef struct { __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ uint8_t RESERVED_6[4]; __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ - __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1(to bus), offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ union { /* offset: 0xD0 */ __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ @@ -33717,7 +33655,7 @@ typedef struct { __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ union { /* offset: 0xD8 */ __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ - __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ }; __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ @@ -33757,15 +33695,15 @@ typedef struct { #define I3C_MCONFIG_DISTO_MASK (0x8U) #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout - * 0b1..Timeout disabled, if timeout is configured - * 0b0..Timeout enabled + * 0b1..Disabled, if configured + * 0b0..Enabled */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) #define I3C_MCONFIG_HKEEP_MASK (0x30U) #define I3C_MCONFIG_HKEEP_SHIFT (4U) /*! HKEEP - High-Keeper - * 0b00..NONE + * 0b00..None * 0b01..WIRED_IN * 0b10..PASSIVE_SDA * 0b11..PASSIVE_ON_SDA_SCL @@ -33775,9 +33713,8 @@ typedef struct { #define I3C_MCONFIG_ODSTOP_MASK (0x40U) #define I3C_MCONFIG_ODSTOP_SHIFT (6U) /*! ODSTOP - Open Drain Stop - * 0b1..Enable open-drain stop. STOP is emitted at open-drain speeds even for I3C messages. In legacy devices, - * this feature can ensure that the legacy devices see the STOP. - * 0b0..Disable open-drain stop. ODSTOP must be disabled when sending an HDR exit pattern. + * 0b1..Enable + * 0b0..Disable */ #define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) @@ -33799,10 +33736,8 @@ typedef struct { #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) #define I3C_MCONFIG_ODHPP_SHIFT (24U) /*! ODHPP - Open Drain High Push-Pull - * 0b1..ODHPP enabled. Open-Drain High SCL half-lock period is one PPBAUD count for I3C messages. This setting is - * faster (and works for I3C devices). Any legacy I2C devices on the bus will not see the SCL High at all - * (less than the spike filter period). - * 0b0..ODHPP disabled. Open-Drain SCL High half-clock period is the same as the Open-Drain Low SCL half-period. + * 0b1..Enable + * 0b0..Disable */ #define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) @@ -33823,59 +33758,55 @@ typedef struct { #define I3C_SCONFIG_SLVENA_MASK (0x1U) #define I3C_SCONFIG_SLVENA_SHIFT (0U) /*! SLVENA - Target Enable - * 0b1..Target can operate on the I2C or I3C bus - * 0b0..Target ignores the I2C or I3C bus + * 0b1..Enable + * 0b0..Disable */ #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) #define I3C_SCONFIG_NACK_MASK (0x2U) #define I3C_SCONFIG_NACK_SHIFT (1U) /*! NACK - Not Acknowledge - * 0b1..Always NACK enable. The target rejects all requests to it, except for a Common Command Code (CCC) - * broadcast. NACK = 1 should be used with caution, because the controller may decide that the target is missing, if - * NACK is overused. - * 0b0..Always NACK disable + * 0b1..Always enable NACK mode (works normally) + * 0b0..Always disable NACK mode */ #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) #define I3C_SCONFIG_MATCHSS_MASK (0x4U) #define I3C_SCONFIG_MATCHSS_SHIFT (2U) -/*! MATCHSS - Match START or STOP - * 0b1..Match START or STOP enable. START and STOP sticky SSTATUS bits only become 1 when SSTATUS[MATCHED] is 1. - * This setting allows START and STOP to be used to detect the end of a message to/from this target. - * 0b0..Match START or STOP disable +/*! MATCHSS - Match Start or Stop + * 0b1..Enable + * 0b0..Disable */ #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) #define I3C_SCONFIG_S0IGNORE_MASK (0x8U) #define I3C_SCONFIG_S0IGNORE_SHIFT (3U) -/*! S0IGNORE - Ignore TE0/TE1 Errors - * 0b1..Ignore TE0/TE1 errors. Target does not detect TE0 or TE1 errors, so it does not lock up waiting on an - * Exit Pattern. This setting should only be used when the bus does not use HDR mode. - * 0b0..Do not ignore TE0/TE1 errors +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b1..Ignore TE0 or TE1 errors + * 0b0..Do not ignore TE0 or TE1 errors */ #define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) #define I3C_SCONFIG_DDROK_MASK (0x10U) #define I3C_SCONFIG_DDROK_SHIFT (4U) /*! DDROK - Double Data Rate OK - * 0b1..Allow HDR-DDR messaging. - * 0b0..Do not allow HDR-DDR messaging. + * 0b1..Allow HDR-DDR messaging + * 0b0..Do not allow HDR-DDR messaging */ #define I3C_SCONFIG_DDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK) #define I3C_SCONFIG_IDRAND_MASK (0x100U) #define I3C_SCONFIG_IDRAND_SHIFT (8U) /*! IDRAND - ID random - * 0b1..SIDPARTNO[PARTNO] is a random value. - * 0b0..SIDPARTNO[PARTNO] is a part number and an instance. + * 0b1..Random value + * 0b0..Part number and an instance */ #define I3C_SCONFIG_IDRAND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK) #define I3C_SCONFIG_OFFLINE_MASK (0x200U) #define I3C_SCONFIG_OFFLINE_SHIFT (9U) /*! OFFLINE - Offline - * 0b1..Enables wait to ensure the bus is not in HDR mode. + * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) @@ -33896,57 +33827,56 @@ typedef struct { #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) -/*! STNOTSTOP - Status Not Stop - * 0b1..The bus is busy (has activity). - * 0b0..I3C module is in a STOP condition. +/*! STNOTSTOP - Status not Stop + * 0b1..Busy + * 0b0..In STOP condition */ #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) #define I3C_SSTATUS_STMSG_MASK (0x2U) #define I3C_SSTATUS_STMSG_SHIFT (1U) -/*! STMSG - Status message - * 0b1..This bus target is listening to the bus traffic or responding. - * 0b0..Bus target not listening or responding. +/*! STMSG - Status Message + * 0b1..Busy + * 0b0..Idle */ #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) #define I3C_SSTATUS_STCCCH_MASK (0x4U) #define I3C_SSTATUS_STCCCH_SHIFT (2U) /*! STCCCH - Status Common Command Code Handler - * 0b1..A CCC message is being handled automatically. - * 0b0..No CCC message is being handled. + * 0b1..Handled automatically + * 0b0..No CCC message handled */ #define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) #define I3C_SSTATUS_STREQRD_MASK (0x8U) #define I3C_SSTATUS_STREQRD_SHIFT (3U) /*! STREQRD - Status Request Read - * 0b1..The REQ in process is an SDR read from this target, or an In-Band Interrupt (IBI) is being pushed out. - * 0b0..REQ in process is not an SDR read from this target. + * 0b1..SDR read from this target or an IBI is being pushed out + * 0b0..Not an SDR read */ #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) #define I3C_SSTATUS_STREQWR_MASK (0x10U) #define I3C_SSTATUS_STREQWR_SHIFT (4U) /*! STREQWR - Status Request Write - * 0b1..REQ in process is SDR write data from the controller to this bus target (or all I3C targets), but not in ENTDAA mode. - * 0b0..REQ in process is not SDR write data from the controller. + * 0b1..SDR write data from the controller, but not in ENTDAA mode + * 0b0..Not an SDR write */ #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) #define I3C_SSTATUS_STDAA_MASK (0x20U) #define I3C_SSTATUS_STDAA_SHIFT (5U) /*! STDAA - Status Dynamic Address Assignment - * 0b1..I3C bus is in Enter Dynamic Address Assignment (ENTDAA) mode, regardless of whether this bus target has a Dynamic Address or not. - * 0b0..Not in ENTDAA mode. + * 0b1..In ENTDAA mode + * 0b0..Not in ENTDAA mode */ #define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) #define I3C_SSTATUS_STHDR_MASK (0x40U) #define I3C_SSTATUS_STHDR_SHIFT (6U) /*! STHDR - Status High Data Rate - * 0b1..The I3C bus is in HDR-DDR mode , regardless of whether HDR mode is supported by this module or not, and - * regardless of whether the message is to this module or to some other module. + * 0b1..I3C bus in HDR-DDR mode * 0b0..I3C bus not in HDR-DDR mode */ #define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) @@ -33954,38 +33884,44 @@ typedef struct { #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) /*! START - Start - * 0b1..A START or repeated START was seen after the START bit was last cleared. - * 0b0..No START seen. + * 0b1..Detected + * 0b0..Not detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) #define I3C_SSTATUS_MATCHED_MASK (0x200U) #define I3C_SSTATUS_MATCHED_SHIFT (9U) /*! MATCHED - Matched - * 0b1..An incoming header matched the I3C Dynamic or I2C Static address of this device (if any) since the bus was last cleared. - * 0b0..No header matched. + * 0b1..Header matched + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) #define I3C_SSTATUS_STOP_MASK (0x400U) #define I3C_SSTATUS_STOP_SHIFT (10U) /*! STOP - Stop - * 0b1..Stopped state detected. A STOP state was present on the bus since the bus was last cleared. - * 0b0..No STOP detected. + * 0b1..Stopped state detected + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) #define I3C_SSTATUS_RX_PEND_MASK (0x800U) #define I3C_SSTATUS_RX_PEND_SHIFT (11U) /*! RX_PEND - Received Message Pending - * 0b1..Received message is pending. - * 0b0..No received message is pending. + * 0b1..Received message pending + * 0b0..No received message pending */ #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - Transmit Buffer Is Not Full +/*! TXNOTFULL - Transmit Buffer Not Full * 0b1..Transmit buffer not full * 0b0..Transmit buffer full */ @@ -33994,16 +33930,20 @@ typedef struct { #define I3C_SSTATUS_DACHG_MASK (0x2000U) #define I3C_SSTATUS_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change - * 0b1..DA change detected. The target DA has been assigned, re-assigned, or reset (lost) and is now in the state of being valid or none. - * 0b0..No DA change detected. + * 0b1..DA change detected + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) #define I3C_SSTATUS_CCC_MASK (0x4000U) #define I3C_SSTATUS_CCC_SHIFT (14U) /*! CCC - Common Command Code - * 0b1..CCC received. - * 0b0..No CCC received. + * 0b1..CCC received + * 0b0..CCC not received + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) @@ -34015,78 +33955,84 @@ typedef struct { #define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) #define I3C_SSTATUS_HDRMATCH_SHIFT (16U) /*! HDRMATCH - High Data Rate Command Match - * 0b1..HDR command matched the I3C Dynamic Address of this device. - * 0b0..HDR command did not match. + * 0b1..Matched the I3C dynamic address + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) #define I3C_SSTATUS_CHANDLED_MASK (0x20000U) #define I3C_SSTATUS_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code Handled - * 0b1..CCC handling in progress. - * 0b0..CCC handling not in progress. + * 0b1..CCC handling in progress + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) #define I3C_SSTATUS_EVENT_MASK (0x40000U) #define I3C_SSTATUS_EVENT_SHIFT (18U) /*! EVENT - Event - * 0b1..An IBI, CR, or HJ has occurred. - * 0b0..No event has occurred. + * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) #define I3C_SSTATUS_EVDET_MASK (0x300000U) #define I3C_SSTATUS_EVDET_SHIFT (20U) /*! EVDET - Event Details - * 0b00..NONE - * 0b01..NO_REQUEST - * 0b10..NACKED - * 0b11..ACKED + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) */ #define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) #define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) #define I3C_SSTATUS_IBIDIS_SHIFT (24U) -/*! IBIDIS - In-Band Interrupts Are Disabled - * 0b1..In-Band Interrupts disabled - * 0b0..In-Band Interrupts not disabled +/*! IBIDIS - In-Band Interrupts Disable + * 0b1..Disabled + * 0b0..Enabled */ #define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) #define I3C_SSTATUS_MRDIS_MASK (0x2000000U) #define I3C_SSTATUS_MRDIS_SHIFT (25U) -/*! MRDIS - Controller Requests Are Disabled - * 0b1..Controller Requests disabled - * 0b0..Controller Requests not disabled +/*! MRDIS - Controller Requests Disable + * 0b1..Disabled + * 0b0..Enabled */ #define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) #define I3C_SSTATUS_HJDIS_MASK (0x8000000U) #define I3C_SSTATUS_HJDIS_SHIFT (27U) /*! HJDIS - Hot-Join Disabled - * 0b1..Hot-Join disabled - * 0b0..Hot-Join not disabled + * 0b1..Disabled + * 0b0..Enabled */ #define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) #define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) #define I3C_SSTATUS_ACTSTATE_SHIFT (28U) /*! ACTSTATE - Activity State from Common Command Codes (CCC) - * 0b00..NO_LATENCY - * 0b01..LATENCY_1MS - * 0b10..LATENCY_100MS - * 0b11..LATENCY_10S + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) */ #define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) #define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) #define I3C_SSTATUS_TIMECTRL_SHIFT (30U) /*! TIMECTRL - Time Control - * 0b00..NO_TIME_CONTROL - * 0b01..SYNC_MODE - * 0b10..ASYNC_MODE - * 0b11..BOTHSYNCASYNC + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) */ #define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) /*! @} */ @@ -34107,8 +34053,8 @@ typedef struct { #define I3C_SCTRL_EXTDATA_MASK (0x8U) #define I3C_SCTRL_EXTDATA_SHIFT (3U) /*! EXTDATA - Extended Data - * 0b1..Extended data enabled. After IBIDATA is emitted, extended data is taken from IBIEXT1 and IBIEXT2 if configured. - * 0b0..Extended data disabled. + * 0b1..Enable + * 0b0..Disable */ #define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) @@ -34139,88 +34085,88 @@ typedef struct { #define I3C_SINTSET_START_MASK (0x100U) #define I3C_SINTSET_START_SHIFT (8U) /*! START - Start Interrupt Enable - * 0b1..Enable START interrupt - * 0b0..Disable START interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) #define I3C_SINTSET_MATCHED_MASK (0x200U) #define I3C_SINTSET_MATCHED_SHIFT (9U) -/*! MATCHED - Match interrupt enable - * 0b1..Enable match interrupt - * 0b0..Disable match interrupt +/*! MATCHED - Match Interrupt Enable + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) #define I3C_SINTSET_STOP_MASK (0x400U) #define I3C_SINTSET_STOP_SHIFT (10U) /*! STOP - Stop Interrupt Enable - * 0b1..Enable STOP interrupt - * 0b0..Disable STOP interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) #define I3C_SINTSET_RXPEND_MASK (0x800U) #define I3C_SINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Interrupt Enable - * 0b1..Enable Receive interrupt - * 0b0..Disable Receive interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) #define I3C_SINTSET_TXSEND_MASK (0x1000U) #define I3C_SINTSET_TXSEND_SHIFT (12U) /*! TXSEND - Transmit Interrupt Enable - * 0b1..Enable Transmit interrupt - * 0b0..Disable Transmit interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) #define I3C_SINTSET_DACHG_MASK (0x2000U) #define I3C_SINTSET_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change Interrupt Enable - * 0b1..Enable DA Change interrupt - * 0b0..Disable DA Change interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) #define I3C_SINTSET_CCC_MASK (0x4000U) #define I3C_SINTSET_CCC_SHIFT (14U) -/*! CCC - CCC (that was not handled by I3C module) Interrupt Enable - * 0b1..Enable CCC interrupt - * 0b0..Disable CCC interrupt +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) #define I3C_SINTSET_ERRWARN_MASK (0x8000U) #define I3C_SINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning Interrupt Enable - * 0b1..Enable error or warning interrupt - * 0b0..Disable error or warning interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) #define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) #define I3C_SINTSET_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - Double Data Rate Interrupt Enable - * 0b1..Enable DDR interrupt - * 0b0..Disable DDR interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) #define I3C_SINTSET_CHANDLED_MASK (0x20000U) #define I3C_SINTSET_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code (CCC) Interrupt Enable - * 0b1..Enable CCC Handled interrupt - * 0b0..Disable CCC Handled interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) #define I3C_SINTSET_EVENT_MASK (0x40000U) #define I3C_SINTSET_EVENT_SHIFT (18U) /*! EVENT - Event Interrupt Enable - * 0b1..Enable Event interrupt - * 0b0..Disable Event interrupt + * 0b1..Enable + * 0b0..Disable */ #define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) /*! @} */ @@ -34235,7 +34181,7 @@ typedef struct { #define I3C_SINTCLR_MATCHED_MASK (0x200U) #define I3C_SINTCLR_MATCHED_SHIFT (9U) -/*! MATCHED - MATCHED Interrupt Enable Clear */ +/*! MATCHED - Matched Interrupt Enable Clear */ #define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) #define I3C_SINTCLR_STOP_MASK (0x400U) @@ -34289,7 +34235,7 @@ typedef struct { #define I3C_SINTMASKED_START_MASK (0x100U) #define I3C_SINTMASKED_START_SHIFT (8U) -/*! START - START interrupt mask */ +/*! START - START Interrupt Mask */ #define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) #define I3C_SINTMASKED_MATCHED_MASK (0x200U) @@ -34351,6 +34297,8 @@ typedef struct { /*! ORUN - Overrun Error * 0b1..Overrun error * 0b0..No overrun error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) @@ -34359,14 +34307,18 @@ typedef struct { /*! URUN - Underrun Error * 0b1..Underrun error * 0b0..No underrun error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) -/*! URUNNACK - Underrun and Not Acknowledged (NACKED) Error - * 0b1..Underrun and not acknowledged error - * 0b0..No underrun and not acknowledged error +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error + * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) @@ -34375,6 +34327,8 @@ typedef struct { /*! TERM - Terminated Error * 0b1..Terminated error * 0b0..No terminated error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) @@ -34383,54 +34337,68 @@ typedef struct { /*! INVSTART - Invalid Start Error * 0b1..Invalid start error * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) #define I3C_SERRWARN_SPAR_MASK (0x100U) #define I3C_SERRWARN_SPAR_SHIFT (8U) /*! SPAR - SDR Parity Error - * 0b1..SDR Parity error - * 0b0..No SDR Parity error + * 0b1..SDR parity error + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) #define I3C_SERRWARN_HPAR_MASK (0x200U) #define I3C_SERRWARN_HPAR_SHIFT (9U) /*! HPAR - HDR Parity Error - * 0b1..HDR Parity error - * 0b0..No HDR Parity error + * 0b1..HDR parity error + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) #define I3C_SERRWARN_HCRC_MASK (0x400U) #define I3C_SERRWARN_HCRC_SHIFT (10U) /*! HCRC - HDR-DDR CRC Error - * 0b1..HDR-DDR CRC error - * 0b0..No HDR-DDR CRC error + * 0b1..HDR-DDR CRC error occurred + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) #define I3C_SERRWARN_S0S1_MASK (0x800U) #define I3C_SERRWARN_S0S1_SHIFT (11U) /*! S0S1 - TE0 or TE1 Error - * 0b1..TE0 or TE1 error - * 0b0..No TE0 or TE1 error + * 0b1..TE0 or TE1 error occurred + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) -/*! OREAD - Over-read Error +/*! OREAD - Over-Read Error * 0b1..Over-read error - * 0b0..No Over-read error + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) -/*! OWRITE - Over-write Error +/*! OWRITE - Over-Write Error * 0b1..Overwrite error - * 0b0..No Overwrite error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ @@ -34440,9 +34408,9 @@ typedef struct { #define I3C_SDMACTRL_DMAFB_MASK (0x3U) #define I3C_SDMACTRL_DMAFB_SHIFT (0U) -/*! DMAFB - DMA Read (From-bus) Trigger +/*! DMAFB - DMA Read (From-Bus) Trigger * 0b00..DMA not used - * 0b01..DMA is enabled for one frame + * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ @@ -34450,9 +34418,9 @@ typedef struct { #define I3C_SDMACTRL_DMATB_MASK (0xCU) #define I3C_SDMACTRL_DMATB_SHIFT (2U) -/*! DMATB - DMA Write (To-bus) Trigger +/*! DMATB - DMA Write (To-Bus) Trigger * 0b00..DMA not used - * 0b01..DMA enabled for one frame (ended by DMA or terminated) + * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ @@ -34462,7 +34430,7 @@ typedef struct { #define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) /*! DMAWIDTH - Width of DMA Operations * 0b00, 0b01..Byte - * 0b10..Half word (16 bits) + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) * 0b11.. */ #define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) @@ -34473,19 +34441,19 @@ typedef struct { #define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) -/*! FLUSHTB - Flush the To-bus Buffer or FIFO */ +/*! FLUSHTB - Flush To-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) #define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) -/*! FLUSHFB - Flush the From-bus Buffer or FIFO */ +/*! FLUSHFB - Flush From-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) #define I3C_SDATACTRL_UNLOCK_MASK (0x8U) #define I3C_SDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock - * 0b0..RXTRIG and TXTRIG fields cannot be changed on a write. - * 0b1..RXTRIG and TXTRIG fields can be changed on a write. + * 0b0..Cannot be changed + * 0b1..Can be changed */ #define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) @@ -34495,7 +34463,7 @@ typedef struct { * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less - * 0b11..Default. Trigger when 1 less than full or less + * 0b11..Default (trigger when 1 less than full or less) */ #define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) @@ -34521,7 +34489,7 @@ typedef struct { #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_SDATACTRL_TXFULL_SHIFT (30U) -/*! TXFULL - Transmit Is Full +/*! TXFULL - Transmit is Full * 0b1..Full * 0b0..Not full */ @@ -34529,7 +34497,7 @@ typedef struct { #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) -/*! RXEMPTY - Receive Is Empty +/*! RXEMPTY - Receive is Empty * 0b1..Empty * 0b0..Not empty */ @@ -34547,16 +34515,16 @@ typedef struct { #define I3C_SWDATAB_END_MASK (0x100U) #define I3C_SWDATAB_END_SHIFT (8U) /*! END - End - * 0b1..End. This bit marks the last byte of the message. - * 0b0..Not the end. There are more bytes in the message. + * 0b1..End + * 0b0..Not the end */ #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) #define I3C_SWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End Also - * 0b1..End. This bit marks the last byte of the message. - * 0b0..Not the end. There are more bytes in the message. + * 0b1..End + * 0b0..Not the end */ #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) /*! @} */ @@ -34570,7 +34538,7 @@ typedef struct { #define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) /*! @} */ -/*! @name SWDATAH - Target Write Data Half-word */ +/*! @name SWDATAH - Target Write Data Halfword */ /*! @{ */ #define I3C_SWDATAH_DATA0_MASK (0xFFU) @@ -34585,14 +34553,14 @@ typedef struct { #define I3C_SWDATAH_END_MASK (0x10000U) #define I3C_SWDATAH_END_SHIFT (16U) -/*! END - End of message - * 0b1..End. This bit marks the last byte of the message. - * 0b0..Not the end. There are more bytes in the message. +/*! END - End of Message + * 0b1..End + * 0b0..Not the end */ #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) /*! @} */ -/*! @name SWDATAHE - Target Write Data Half-word End */ +/*! @name SWDATAHE - Target Write Data Halfword End */ /*! @{ */ #define I3C_SWDATAHE_DATA0_MASK (0xFFU) @@ -34620,12 +34588,12 @@ typedef struct { #define I3C_SRDATAH_LSB_MASK (0xFFU) #define I3C_SRDATAH_LSB_SHIFT (0U) -/*! LSB - The first byte read from the target */ +/*! LSB - Low Byte */ #define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) #define I3C_SRDATAH_MSB_MASK (0xFF00U) #define I3C_SRDATAH_MSB_SHIFT (8U) -/*! MSB - The second byte read from the target */ +/*! MSB - High Byte */ #define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) /*! @} */ @@ -34636,11 +34604,6 @@ typedef struct { #define I3C_SWDATAB1_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) - -#define I3C_SWDATAB1_IGNORED_MASK (0xFFFFFF00U) -#define I3C_SWDATAB1_IGNORED_SHIFT (8U) -/*! IGNORED - Ignored field */ -#define I3C_SWDATAB1_IGNORED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_IGNORED_SHIFT)) & I3C_SWDATAB1_IGNORED_MASK) /*! @} */ /*! @name SCAPABILITIES2 - Target Capabilities 2 */ @@ -34654,66 +34617,66 @@ typedef struct { #define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) #define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) /*! I2C10B - I2C 10-bit Address - * 0b0..Does not support 10-bit I2C address - * 0b1..Supports 10-bit I2C address + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) #define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) #define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) /*! I2CRST - I2C Software Reset - * 0b0..Does not support I2C software reset - * 0b1..Supports I2C software reset + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) #define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) /*! I2CDEVID - I2C Device ID - * 0b0..Does not support I2C device ID - * 0b1..Supports I2C device ID + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) #define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) #define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) /*! IBIEXT - In-Band Interrupt EXTDATA - * 0b0..Does not support IBIEXT - * 0b1..Supports IBIEXT + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) #define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) #define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) /*! IBIXREG - In-Band Interrupt Extended Register - * 0b0..Does not support extended registers for IBIs - * 0b1..Supports extended registers for IBIs + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) #define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) #define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) /*! SLVRST - Target Reset - * 0b0..Does not support Target Reset - * 0b1..Supports Target Reset + * 0b0..Not supported + * 0b1..Supported */ #define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) #define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) #define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) /*! GROUP - Group - * 0b00..Does not supports v1.1 Group addressing - * 0b01..Supports one group - * 0b10..Supports two groups - * 0b11..Supports three groups + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported */ #define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) #define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) #define I3C_SCAPABILITIES2_AASA_SHIFT (21U) -/*! AASA - Supports SETAASA - * 0b1..Supports SETAASA - * 0b0..Does not support SETAASA +/*! AASA - SETAASA + * 0b1..SETAASA supported + * 0b0..SETAASA not supported */ #define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) @@ -34750,11 +34713,11 @@ typedef struct { #define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) #define I3C_SCAPABILITIES_IDREG_SHIFT (2U) /*! IDREG - ID Register - * 0b0000..All ID register features below are disabled. - * 0bxxx1..ID Instance is a register, and is used if there is no PARTNO register. - * 0bxx1x..An ID Random field is available. - * 0bx1xx..A Device Characteristic Register (DCR) is available. - * 0b1xxx..A Bus Characteristics Register (BCR) is available. + * 0b0000..All ID register features disabled + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + * 0bxx1x..An ID Random field is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0b1xxx..A Bus Characteristics Register (BCR) is available */ #define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) @@ -34762,7 +34725,7 @@ typedef struct { #define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) /*! HDRSUPP - High Data Rate Support * 0b00..No HDR modes supported - * 0b01..Double Data Rate mode supported + * 0b01..DDR mode supported * *.. */ #define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) @@ -34788,30 +34751,30 @@ typedef struct { #define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) /*! CCCHANDLE - Common Command Codes Handling - * 0b0000..All handling features below are disabled. - * 0bxxx1..The block (I3C module) manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items. - * 0bxx1x..The block manages maximum read and write lengths, and max data speed. - * 0bx1xx..GETSTATUS CCC returns SCTRL[PENDINT] and SCTRL[ACTSTATE] values. - * 0b1xxx..GETSTATUS CCC returns SCTRL[VENDINFO] value. + * 0b0000..All handling features disabled + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] */ #define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) #define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events - * 0b00000..Application cannot generate IBI, CR, or HJ. - * 0bxxxx1..Application can generate an IBI. - * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register. - * 0bxx1xx..Application can generate a Controller Request for a secondary controller. - * 0bx1xxx..Application can generate a Hot-Join event. - * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing. + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0bxxxx1..Application can generate an IBI + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bx1xxx..Application can generate a Hot-Join event + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing */ #define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) #define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) #define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) /*! TIMECTRL - Time Control - * 0b0..No time control enabled + * 0b0..No time control supported * 0b1..At least one time-control type supported */ #define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) @@ -34819,7 +34782,7 @@ typedef struct { #define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) #define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) /*! EXTFIFO - External FIFO - * 0b000..No external FIFO is available + * 0b000..No external FIFO available * 0b001..Standard available or free external FIFO * 0b010..Request track external FIFO * *.. @@ -34869,8 +34832,8 @@ typedef struct { #define I3C_SDYNADDR_DAVALID_MASK (0x1U) #define I3C_SDYNADDR_DAVALID_SHIFT (0U) /*! DAVALID - Dynamic Address Valid - * 0b0..DANOTASSIGNED: a Dynamic Address is not assigned - * 0b1..DAASSIGNED: a Dynamic Address is assigned + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned */ #define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) @@ -34886,7 +34849,7 @@ typedef struct { #define I3C_SDYNADDR_SA10B_MASK (0xE000U) #define I3C_SDYNADDR_SA10B_SHIFT (13U) -/*! SA10B - 10bit Static Address */ +/*! SA10B - 10-Bit Static Address */ #define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) #define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) @@ -34914,7 +34877,7 @@ typedef struct { #define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) #define I3C_SIDPARTNO_PARTNO_SHIFT (0U) -/*! PARTNO - Part number */ +/*! PARTNO - Part Number */ #define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) /*! @} */ @@ -35043,9 +35006,9 @@ typedef struct { #define I3C_MSTATUS_STATE_MASK (0x7U) #define I3C_MSTATUS_STATE_SHIFT (0U) -/*! STATE - State Of The Controller - * 0b000..IDLE - * 0b001..SLVREQ +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) * 0b010..MSGSDR * 0b011..NORMACT * 0b100..MSGDDR @@ -35058,7 +35021,7 @@ typedef struct { #define I3C_MSTATUS_BETWEEN_MASK (0x10U) #define I3C_MSTATUS_BETWEEN_SHIFT (4U) /*! BETWEEN - Between - * 0b0..Inactive + * 0b0..Inactive (for other cases) * 0b1..Active */ #define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) @@ -35074,10 +35037,10 @@ typedef struct { #define I3C_MSTATUS_IBITYPE_MASK (0xC0U) #define I3C_MSTATUS_IBITYPE_SHIFT (6U) /*! IBITYPE - In-Band Interrupt (IBI) Type - * 0b00..NONE - * 0b01..In-Band Interrupt - * 0b10..Controller Request - * 0b11..Hot-Join + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ */ #define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) @@ -35086,6 +35049,8 @@ typedef struct { /*! SLVSTART - Target Start * 0b1..Target requesting START * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) @@ -35094,6 +35059,8 @@ typedef struct { /*! MCTRLDONE - Controller Control Done * 0b1..Done * 0b0..Not done + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) @@ -35102,6 +35069,8 @@ typedef struct { /*! COMPLETE - Complete * 0b1..Complete * 0b0..Not complete + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) @@ -35126,12 +35095,14 @@ typedef struct { /*! IBIWON - In-Band Interrupt (IBI) Won * 0b1..IBI arbitration won * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) #define I3C_MSTATUS_ERRWARN_SHIFT (15U) -/*! ERRWARN - Error Or Warning +/*! ERRWARN - Error or Warning * 0b1..Error or warning * 0b0..No error or warning */ @@ -35139,9 +35110,11 @@ typedef struct { #define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) #define I3C_MSTATUS_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - Module Is Now Controller - * 0b1..Module has become controller - * 0b0..Module has not become controller +/*! NOWMASTER - Module is now Controller + * 0b1..Controller + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) @@ -35181,9 +35154,9 @@ typedef struct { #define I3C_MIBIRULES_MSB0_MASK (0x40000000U) #define I3C_MIBIRULES_MSB0_SHIFT (30U) -/*! MSB0 - Most Significant Address Bit Is 0 - * 0b1..For all I3C dynamic addresses, MSB is 0. - * 0b0..MSB is not 0. +/*! MSB0 - Most Significant Address Bit is 0 + * 0b1..MSB is 0 + * 0b0..MSB is not 0 */ #define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) @@ -35225,12 +35198,12 @@ typedef struct { #define I3C_MINTSET_RXPEND_MASK (0x800U) #define I3C_MINTSET_RXPEND_SHIFT (11U) -/*! RXPEND - Rx Pending Interrupt Enable */ +/*! RXPEND - Receive Pending Interrupt Enable */ #define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) -/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable * 0b1..Enable * 0b0..Disable */ @@ -35238,7 +35211,7 @@ typedef struct { #define I3C_MINTSET_IBIWON_MASK (0x2000U) #define I3C_MINTSET_IBIWON_SHIFT (13U) -/*! IBIWON - In-Band Interrupt (IBI) Won Interrupt Enable +/*! IBIWON - IBI Won Interrupt Enable * 0b1..Enable * 0b0..Disable */ @@ -35254,7 +35227,7 @@ typedef struct { #define I3C_MINTSET_NOWMASTER_MASK (0x80000U) #define I3C_MINTSET_NOWMASTER_SHIFT (19U) -/*! NOWMASTER - Now Controller (now this I3C module is a controller) Interrupt Enable +/*! NOWMASTER - Now Controller Interrupt Enable * 0b1..Enable * 0b0..Disable */ @@ -35267,64 +35240,80 @@ typedef struct { #define I3C_MINTCLR_SLVSTART_MASK (0x100U) #define I3C_MINTCLR_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) #define I3C_MINTCLR_COMPLETE_MASK (0x400U) #define I3C_MINTCLR_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) #define I3C_MINTCLR_RXPEND_MASK (0x800U) #define I3C_MINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) #define I3C_MINTCLR_IBIWON_MASK (0x2000U) #define I3C_MINTCLR_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) #define I3C_MINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) #define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) #define I3C_MINTCLR_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear - * 0b1..Corresponding interrupt enable becomes 0 + * 0b1..Interrupt enable cleared * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) /*! @} */ @@ -35335,24 +35324,24 @@ typedef struct { #define I3C_MINTMASKED_SLVSTART_MASK (0x100U) #define I3C_MINTMASKED_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) @@ -35364,32 +35353,32 @@ typedef struct { #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) #define I3C_MINTMASKED_IBIWON_MASK (0x2000U) #define I3C_MINTMASKED_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) #define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) #define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Mask - * 0b1..Interrupt enabled and active - * 0b0..Interrupt not enabled and/or not active + * 0b1..Enabled + * 0b0..Disabled */ #define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) /*! @} */ @@ -35397,19 +35386,13 @@ typedef struct { /*! @name MERRWARN - Controller Errors and Warnings */ /*! @{ */ -#define I3C_MERRWARN_URUN_MASK (0x2U) -#define I3C_MERRWARN_URUN_SHIFT (1U) -/*! URUN - Underrun error - * 0b1..Error - * 0b0..No error - */ -#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) - #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) /*! NACK - Not Acknowledge Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) @@ -35418,22 +35401,18 @@ typedef struct { /*! WRABT - Write Abort Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) -#define I3C_MERRWARN_TERM_MASK (0x10U) -#define I3C_MERRWARN_TERM_SHIFT (4U) -/*! TERM - Terminate Error - * 0b1..Error - * 0b0..No error - */ -#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) - #define I3C_MERRWARN_HPAR_MASK (0x200U) #define I3C_MERRWARN_HPAR_SHIFT (9U) /*! HPAR - High Data Rate Parity * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) @@ -35442,22 +35421,28 @@ typedef struct { /*! HCRC - High Data Rate CRC Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) -/*! OREAD - Over-read Error +/*! OREAD - Overread Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) -/*! OWRITE - Over-write Error +/*! OWRITE - Overwrite Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) @@ -35466,6 +35451,8 @@ typedef struct { /*! MSGERR - Message Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) @@ -35474,6 +35461,8 @@ typedef struct { /*! INVREQ - Invalid Request Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) @@ -35482,6 +35471,8 @@ typedef struct { /*! TIMEOUT - Timeout Error * 0b1..Error * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag */ #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ @@ -35491,8 +35482,8 @@ typedef struct { #define I3C_MDMACTRL_DMAFB_MASK (0x3U) #define I3C_MDMACTRL_DMAFB_SHIFT (0U) -/*! DMAFB - DMA From Bus - * 0b00..DMA is not used +/*! DMAFB - DMA from Bus + * 0b00..DMA not used * 0b01..Enable DMA for one frame * 0b10..Enable DMA until DMA is turned off * 0b11.. @@ -35501,9 +35492,9 @@ typedef struct { #define I3C_MDMACTRL_DMATB_MASK (0xCU) #define I3C_MDMACTRL_DMATB_SHIFT (2U) -/*! DMATB - DMA To Bus - * 0b00..DMA is not used - * 0b01..Enable DMA for one frame (ended by DMA or Terminated) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) * 0b10..Enable DMA until DMA is turned off * 0b11.. */ @@ -35524,7 +35515,7 @@ typedef struct { #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) -/*! FLUSHTB - Flush To-bus Buffer or FIFO +/*! FLUSHTB - Flush To-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ @@ -35532,7 +35523,7 @@ typedef struct { #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) -/*! FLUSHFB - Flush From-bus Buffer or FIFO +/*! FLUSHFB - Flush From-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ @@ -35541,8 +35532,8 @@ typedef struct { #define I3C_MDATACTRL_UNLOCK_MASK (0x8U) #define I3C_MDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock - * 0b0..Locked. RXTRIG and TXTRIG fields cannot be changed on a write. - * 0b1..Unlocked. RXTRIG and TXTRIG fields can be changed on a write. + * 0b0..Locked + * 0b1..Unlocked */ #define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) @@ -35552,7 +35543,7 @@ typedef struct { * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less - * 0b11..Default. Trigger when 1 less than full or less + * 0b11..Trigger when 1 less than full or less (default) */ #define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) @@ -35578,17 +35569,17 @@ typedef struct { #define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_MDATACTRL_TXFULL_SHIFT (30U) -/*! TXFULL - Transmit Is Full - * 0b0..Transmit FIFO or buffer is not yet full. - * 0b1..Transmit FIFO or buffer is full. +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full */ #define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) #define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) -/*! RXEMPTY - Receive Is Empty - * 0b0..Receive FIFO or buffer is not yet empty. - * 0b1..Receive FIFO or buffer is empty. +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty */ #define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) /*! @} */ @@ -35604,16 +35595,16 @@ typedef struct { #define I3C_MWDATAB_END_MASK (0x100U) #define I3C_MWDATAB_END_SHIFT (8U) /*! END - End of Message - * 0b0..Not the end. More bytes are assumed to be in the message. - * 0b1..End. The END bit marks the last byte of the message. + * 0b0..Not the end + * 0b1..End */ #define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) #define I3C_MWDATAB_END_ALSO_MASK (0x10000U) #define I3C_MWDATAB_END_ALSO_SHIFT (16U) -/*! END_ALSO - End of Message Also - * 0b0..Not the end. More bytes are assumed to be in the message. - * 0b1..End. The END bit marks the last byte of the message. +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End */ #define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) /*! @} */ @@ -35642,9 +35633,9 @@ typedef struct { #define I3C_MWDATAH_END_MASK (0x10000U) #define I3C_MWDATAH_END_SHIFT (16U) -/*! END - End of message - * 0b0..Not the end. More bytes are assumed to be in the message. - * 0b1..End. The END bit marks the last byte of the message. +/*! END - End of Message + * 0b0..Not the end + * 0b1..End */ #define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) /*! @} */ @@ -35677,16 +35668,16 @@ typedef struct { #define I3C_MRDATAH_LSB_MASK (0xFFU) #define I3C_MRDATAH_LSB_SHIFT (0U) -/*! LSB - LSB */ +/*! LSB - Low Byte */ #define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) #define I3C_MRDATAH_MSB_MASK (0xFF00U) #define I3C_MRDATAH_MSB_SHIFT (8U) -/*! MSB - MSB */ +/*! MSB - High Byte */ #define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) /*! @} */ -/*! @name MWDATAB1 - Controller Write Byte Data 1(to bus) */ +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ /*! @{ */ #define I3C_MWDATAB1_VALUE_MASK (0xFFU) @@ -35714,8 +35705,8 @@ typedef struct { #define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) #define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) /*! END - End of SDR Message - * 0b0..Not the end. SDR message ends waiting for a new SDR message (issues a repeated START for a new message). - * 0b1..End. SDR message ends at the STOP. + * 0b0..Not the end + * 0b1..End */ #define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) @@ -35760,7 +35751,7 @@ typedef struct { #define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) /*! @} */ -/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR mode Control 2 */ +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ /*! @{ */ #define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) @@ -35770,9 +35761,9 @@ typedef struct { #define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) -/*! END - End of message - * 0b1..End. DDR message ends on HDR Exit. - * 0b0..Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message). +/*! END - End of Message + * 0b1..End + * 0b0..Not the end */ #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) /*! @} */ @@ -35800,7 +35791,7 @@ typedef struct { #define I3C_MDYNADDR_DAVALID_MASK (0x1U) #define I3C_MDYNADDR_DAVALID_SHIFT (0U) -/*! DAVALID - Dynamic address valid +/*! DAVALID - Dynamic Address Valid * 0b1..Valid DA assigned * 0b0..No valid DA assigned */ @@ -35808,7 +35799,7 @@ typedef struct { #define I3C_MDYNADDR_DADDR_MASK (0xFEU) #define I3C_MDYNADDR_DADDR_SHIFT (1U) -/*! DADDR - Dynamic address */ +/*! DADDR - Dynamic Address */ #define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) /*! @} */ @@ -35818,8 +35809,8 @@ typedef struct { #define I3C_SMAPCTRL0_ENA_MASK (0x1U) #define I3C_SMAPCTRL0_ENA_SHIFT (0U) /*! ENA - Enable Primary Dynamic Address - * 0b0..Disable - * 0b1..Enable + * 0b0..Disabled + * 0b1..Enabled */ #define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) @@ -35831,12 +35822,11 @@ typedef struct { #define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) #define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) /*! CAUSE - Cause - * 0b000..No information. This value occurs when not configured to write DA. + * 0b000..No information (this value occurs when not configured to write DA) * 0b001..Set using ENTDAA * 0b010..Set using SETDASA, SETAASA, or SETNEWDA * 0b011..Cleared using RSTDAA - * 0b100..Auto MAP change happened last. The change may have changed this DA as well (for example, ENTDAA, and - * SETAASA), but at least one MAP entry automatically changed after. + * 0b100..Auto MAP change happened last * *.. */ #define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) @@ -35857,17 +35847,17 @@ typedef struct { #define I3C_IBIEXT1_EXT1_MASK (0xFF00U) #define I3C_IBIEXT1_EXT1_SHIFT (8U) -/*! EXT1 - Extra byte 1 */ +/*! EXT1 - Extra Byte 1 */ #define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) #define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) #define I3C_IBIEXT1_EXT2_SHIFT (16U) -/*! EXT2 - Extra byte 2 */ +/*! EXT2 - Extra Byte 2 */ #define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) #define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) #define I3C_IBIEXT1_EXT3_SHIFT (24U) -/*! EXT3 - Extra byte 3 */ +/*! EXT3 - Extra Byte 3 */ #define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) /*! @} */ @@ -35876,22 +35866,22 @@ typedef struct { #define I3C_IBIEXT2_EXT4_MASK (0xFFU) #define I3C_IBIEXT2_EXT4_SHIFT (0U) -/*! EXT4 - Extra byte 4 */ +/*! EXT4 - Extra Byte 4 */ #define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) #define I3C_IBIEXT2_EXT5_MASK (0xFF00U) #define I3C_IBIEXT2_EXT5_SHIFT (8U) -/*! EXT5 - Extra byte 5 */ +/*! EXT5 - Extra Byte 5 */ #define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) #define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) #define I3C_IBIEXT2_EXT6_SHIFT (16U) -/*! EXT6 - Extra byte 6 */ +/*! EXT6 - Extra Byte 6 */ #define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) #define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) #define I3C_IBIEXT2_EXT7_SHIFT (24U) -/*! EXT7 - Extra byte 7 */ +/*! EXT7 - Extra Byte 7 */ #define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) /*! @} */ @@ -35974,19 +35964,19 @@ typedef struct { __IO uint32_t CTIMER0CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */ __IO uint32_t CTIMER0CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */ __IO uint32_t CTIMER0CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */ - __IO uint32_t TIMER0TRIG; /**< Trigger Register for TIMER, offset: 0x30 */ + __IO uint32_t TIMER0TRIG; /**< Trigger Register for CTIMER, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CTIMER1CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */ __IO uint32_t CTIMER1CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */ __IO uint32_t CTIMER1CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */ __IO uint32_t CTIMER1CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */ - __IO uint32_t TIMER1TRIG; /**< Trigger Register for TIMER, offset: 0x50 */ + __IO uint32_t TIMER1TRIG; /**< Trigger Register for CTIMER, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t CTIMER2CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */ __IO uint32_t CTIMER2CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */ __IO uint32_t CTIMER2CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */ __IO uint32_t CTIMER2CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */ - __IO uint32_t TIMER2TRIG; /**< Trigger Register for TIMER, offset: 0x70 */ + __IO uint32_t TIMER2TRIG; /**< Trigger Register for CTIMER, offset: 0x70 */ uint8_t RESERVED_2[44]; __IO uint32_t SMARTDMAARCHB_INMUX[8]; /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */ __IO uint32_t PINTSEL[8]; /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */ @@ -35998,13 +35988,13 @@ typedef struct { __IO uint32_t CTIMER3CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */ __IO uint32_t CTIMER3CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */ __IO uint32_t CTIMER3CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */ - __IO uint32_t TIMER3TRIG; /**< Trigger Register for TIMER, offset: 0x1B0 */ + __IO uint32_t TIMER3TRIG; /**< Trigger Register for CTIMER, offset: 0x1B0 */ uint8_t RESERVED_5[12]; __IO uint32_t CTIMER4CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */ __IO uint32_t CTIMER4CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */ __IO uint32_t CTIMER4CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */ __IO uint32_t CTIMER4CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */ - __IO uint32_t TIMER4TRIG; /**< Trigger Register for TIMER, offset: 0x1D0 */ + __IO uint32_t TIMER4TRIG; /**< Trigger Register for CTIMER, offset: 0x1D0 */ uint8_t RESERVED_6[140]; __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ uint8_t RESERVED_7[28]; @@ -36018,101 +36008,62 @@ typedef struct { uint8_t RESERVED_11[28]; __IO uint32_t DAC2_TRIG; /**< DAC2 Trigger Inputs, offset: 0x340 */ uint8_t RESERVED_12[28]; - __IO uint32_t ENC0_TRIG; /**< ENC0 Trigger Input Connections, offset: 0x360 */ - __IO uint32_t ENC0_HOME; /**< ENC0 Input Connections, offset: 0x364 */ - __IO uint32_t ENC0_INDEX; /**< ENC0 Input Connections, offset: 0x368 */ - __IO uint32_t ENC0_PHASEB; /**< ENC0 Input Connections, offset: 0x36C */ - __IO uint32_t ENC0_PHASEA; /**< ENC0 Input Connections, offset: 0x370 */ - uint8_t RESERVED_13[12]; - __IO uint32_t ENC1_TRIG; /**< ENC1 Trigger Input Connections, offset: 0x380 */ - __IO uint32_t ENC1_HOME; /**< ENC1 Input Connections, offset: 0x384 */ - __IO uint32_t ENC1_INDEX; /**< ENC1 Input Connections, offset: 0x388 */ - __IO uint32_t ENC1_PHASEB; /**< ENC1 Input Connections, offset: 0x38C */ - __IO uint32_t ENC1_PHASEA; /**< ENC1 Input Connections, offset: 0x390 */ - uint8_t RESERVED_14[12]; + struct { /* offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_TRIG; /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_HOME; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */ + __IO uint32_t QDC_INDEX; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */ + __IO uint32_t QDC_PHASEB; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */ + __IO uint32_t QDC_PHASEA; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */ + uint8_t RESERVED_0[12]; + } QDCN[2]; __IO uint32_t FLEXPWM0_SM_EXTSYNC[4]; /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */ __IO uint32_t FLEXPWM0_SM_EXTA[4]; /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */ __IO uint32_t FLEXPWM0_EXTFORCE; /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */ __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */ - uint8_t RESERVED_15[12]; + uint8_t RESERVED_13[12]; __IO uint32_t FLEXPWM1_SM_EXTSYNC[4]; /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */ - __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input Trigger Connections, array offset: 0x3F0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */ __IO uint32_t FLEXPWM1_EXTFORCE; /**< PWM1 External Force Trigger Connections, offset: 0x400 */ __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */ - uint8_t RESERVED_16[12]; + uint8_t RESERVED_14[12]; __IO uint32_t PWM0_EXT_CLK; /**< PWM0 External Clock Trigger, offset: 0x420 */ __IO uint32_t PWM1_EXT_CLK; /**< PWM1 External Clock Trigger, offset: 0x424 */ - uint8_t RESERVED_17[24]; - __IO uint32_t EVTG_TRIG0; /**< EVTG Trigger Input Connections 0, offset: 0x440 */ - __IO uint32_t EVTG_TRIG1; /**< EVTG Trigger Input Connections 1, offset: 0x444 */ - __IO uint32_t EVTG_TRIG2; /**< EVTG Trigger Input Connections 2, offset: 0x448 */ - __IO uint32_t EVTG_TRIG3; /**< EVTG Trigger Input Connections 3, offset: 0x44C */ - __IO uint32_t EVTG_TRIG4; /**< EVTG Trigger Input Connections 4, offset: 0x450 */ - __IO uint32_t EVTG_TRIG5; /**< EVTG Trigger Input Connections 5, offset: 0x454 */ - __IO uint32_t EVTG_TRIG6; /**< EVTG Trigger Input Connections 6, offset: 0x458 */ - __IO uint32_t EVTG_TRIG7; /**< EVTG Trigger Input Connections 7, offset: 0x45C */ - __IO uint32_t EVTG_TRIG8; /**< EVTG Trigger Input Connections 8, offset: 0x460 */ - __IO uint32_t EVTG_TRIG9; /**< EVTG Trigger Input Connections 9, offset: 0x464 */ - __IO uint32_t EVTG_TRIG10; /**< EVTG Trigger Input Connections 10, offset: 0x468 */ - __IO uint32_t EVTG_TRIG11; /**< EVTG Trigger Input Connections 11, offset: 0x46C */ - __IO uint32_t EVTG_TRIG12; /**< EVTG Trigger Input Connections 12, offset: 0x470 */ - __IO uint32_t EVTG_TRIG13; /**< EVTG Trigger Input Connections 13, offset: 0x474 */ - __IO uint32_t EVTG_TRIG14; /**< EVTG Trigger Input Connections 14, offset: 0x478 */ - __IO uint32_t EVTG_TRIG15; /**< EVTG Trigger Input Connections 15, offset: 0x47C */ + uint8_t RESERVED_15[24]; + __IO uint32_t EVTG_TRIG[16]; /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */ __IO uint32_t USBFS_TRIG; /**< USB-FS Trigger Input Connections, offset: 0x480 */ - uint8_t RESERVED_18[28]; + uint8_t RESERVED_16[28]; __IO uint32_t TSI_TRIG; /**< TSI Trigger Input Connections, offset: 0x4A0 */ - uint8_t RESERVED_19[28]; - __IO uint32_t EXT_TRIG0; /**< EXT Trigger Connections 0, offset: 0x4C0 */ - __IO uint32_t EXT_TRIG1; /**< EXT Trigger Connections 1, offset: 0x4C4 */ - __IO uint32_t EXT_TRIG2; /**< EXT Trigger Connections 2, offset: 0x4C8 */ - __IO uint32_t EXT_TRIG3; /**< EXT Trigger Connections 3, offset: 0x4CC */ - __IO uint32_t EXT_TRIG4; /**< EXT Trigger Connections 4, offset: 0x4D0 */ - __IO uint32_t EXT_TRIG5; /**< EXT Trigger Connections 5, offset: 0x4D4 */ - __IO uint32_t EXT_TRIG6; /**< EXT Trigger Connections 6, offset: 0x4D8 */ - __IO uint32_t EXT_TRIG7; /**< EXT Trigger Connections 7, offset: 0x4DC */ + uint8_t RESERVED_17[28]; + __IO uint32_t EXT_TRIG[8]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ __IO uint32_t CMP1_TRIG; /**< CMP1 Input Connections, offset: 0x4E0 */ - uint8_t RESERVED_20[28]; + uint8_t RESERVED_18[28]; __IO uint32_t CMP2_TRIG; /**< CMP2 Input Connections, offset: 0x500 */ - uint8_t RESERVED_21[28]; - __IO uint32_t SINC_FILTER_CH0; /**< SINC Filter Channel0 Trigger Input Connections, offset: 0x520 */ - __IO uint32_t SINC_FILTER_CH1; /**< SINC Filter Channel1 Trigger Input Connections, offset: 0x524 */ - __IO uint32_t SINC_FILTER_CH2; /**< SINC Filter Channel2 Trigger Input Connections, offset: 0x528 */ - __IO uint32_t SINC_FILTER_CH3; /**< SINC Filter Channel3 Trigger Input Connections, offset: 0x52C */ - __IO uint32_t SINC_FILTER_CH4; /**< SINC Filter Channel4 Trigger Input Connections, offset: 0x530 */ - uint8_t RESERVED_22[76]; - __IO uint32_t OPAMP0_TRIG; /**< OPAMP0 Trigger Input Connections, offset: 0x580 */ - __IO uint32_t OPAMP1_TRIG; /**< OPAMP1 Trigger Input Connections, offset: 0x584 */ - __IO uint32_t OPAMP2_TRIG; /**< OPAMP2 Trigger Input Connections, offset: 0x588 */ - uint8_t RESERVED_23[20]; + uint8_t RESERVED_19[28]; + __IO uint32_t SINC_FILTER_CH[5]; /**< SINC Filter Channel Trigger Input Connections, array offset: 0x520, array step: 0x4 */ + uint8_t RESERVED_20[76]; + __IO uint32_t OPAMP_TRIG[3]; /**< OPAMP Trigger Input Connections, array offset: 0x580, array step: 0x4 */ + uint8_t RESERVED_21[20]; __IO uint32_t FLEXCOMM0_TRIG; /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */ - uint8_t RESERVED_24[28]; + uint8_t RESERVED_22[28]; __IO uint32_t FLEXCOMM1_TRIG; /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */ - uint8_t RESERVED_25[28]; + uint8_t RESERVED_23[28]; __IO uint32_t FLEXCOMM2_TRIG; /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */ - uint8_t RESERVED_26[28]; + uint8_t RESERVED_24[28]; __IO uint32_t FLEXCOMM3_TRIG; /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */ - uint8_t RESERVED_27[28]; + uint8_t RESERVED_25[28]; __IO uint32_t FLEXCOMM4_TRIG; /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */ - uint8_t RESERVED_28[28]; + uint8_t RESERVED_26[28]; __IO uint32_t FLEXCOMM5_TRIG; /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */ - uint8_t RESERVED_29[28]; + uint8_t RESERVED_27[28]; __IO uint32_t FLEXCOMM6_TRIG; /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */ - uint8_t RESERVED_30[28]; + uint8_t RESERVED_28[28]; __IO uint32_t FLEXCOMM7_TRIG; /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */ - uint8_t RESERVED_31[28]; + uint8_t RESERVED_29[28]; __IO uint32_t FLEXCOMM8_TRIG; /**< LP_FLEXCOMM8 Trigger Input Connections, offset: 0x6A0 */ - uint8_t RESERVED_32[28]; + uint8_t RESERVED_30[28]; __IO uint32_t FLEXCOMM9_TRIG; /**< LP_FLEXCOMM9 Trigger Input Connections, offset: 0x6C0 */ - uint8_t RESERVED_33[28]; - __IO uint32_t FLEXIO_TRIG0; /**< FlexIO Trigger Input Connections 0, offset: 0x6E0 */ - __IO uint32_t FLEXIO_TRIG1; /**< FlexIO Trigger Input Connections 1, offset: 0x6E4 */ - __IO uint32_t FLEXIO_TRIG2; /**< FlexIO Trigger Input Connections 2, offset: 0x6E8 */ - __IO uint32_t FLEXIO_TRIG3; /**< FlexIO Trigger Input Connections 3, offset: 0x6EC */ - __IO uint32_t FLEXIO_TRIG4; /**< FlexIO Trigger Input Connections 4, offset: 0x6F0 */ - __IO uint32_t FLEXIO_TRIG5; /**< FlexIO Trigger Input Connections 5, offset: 0x6F4 */ - __IO uint32_t FLEXIO_TRIG6; /**< FlexIO Trigger Input Connections 6, offset: 0x6F8 */ - __IO uint32_t FLEXIO_TRIG7; /**< FlexIO Trigger Input Connections 7, offset: 0x6FC */ + uint8_t RESERVED_31[28]; + __IO uint32_t FLEXIO_TRIG[8]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ __IO uint32_t DMA0_REQ_ENABLE0; /**< DMA0 Request Enable0, offset: 0x700 */ __O uint32_t DMA0_REQ_ENABLE0_SET; /**< DMA0 Request Enable0, offset: 0x704 */ __O uint32_t DMA0_REQ_ENABLE0_CLR; /**< DMA0 Request Enable0, offset: 0x708 */ @@ -36128,7 +36079,7 @@ typedef struct { __IO uint32_t DMA0_REQ_ENABLE3; /**< DMA0 Request Enable3, offset: 0x730 */ __O uint32_t DMA0_REQ_ENABLE3_SET; /**< DMA0 Request Enable3, offset: 0x734 */ __O uint32_t DMA0_REQ_ENABLE3_CLR; /**< DMA0 Request Enable3, offset: 0x738 */ - uint8_t RESERVED_34[68]; + uint8_t RESERVED_32[68]; __IO uint32_t DMA1_REQ_ENABLE0; /**< DMA1 Request Enable0, offset: 0x780 */ __O uint32_t DMA1_REQ_ENABLE0_SET; /**< DMA1 Request Enable0, offset: 0x784 */ __O uint32_t DMA1_REQ_ENABLE0_CLR; /**< DMA1 Request Enable0, offset: 0x788 */ @@ -36183,7 +36134,7 @@ typedef struct { * 0b0010011..SINC Filter CH2 Conversion Complete input is selected * 0b0010100..SINC Filter CH3 Conversion Complete input is selected * 0b0010101..SINC Filter CH4 Conversion Complete input is selected - * 0b0010110..ARM_TXEV (CM33 event output) input is selected + * 0b0010110..Reserved * 0b0010111..DEBUG_HALTED input is selected * 0b0011000..ADC1_IRQ input is selected * 0b0011001..ADC0_tcomp[0] input is selected @@ -36197,16 +36148,16 @@ typedef struct { * 0b0100001..CMP0_OUT input is selected * 0b0100010..CMP1_OUT input is selected * 0b0100011..CMP2_OUT input is selected - * 0b0100100..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0100101..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100110..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100111..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0101000..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0101001..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0101010..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0101100..ENC0_CMP/POS_MATCH input is selected - * 0b0101101..ENC1_CMP/POS_MATCH input is selected + * 0b0100100..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0100101..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100111..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0101000..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0101100..QDC0_CMP/POS_MATCH input is selected + * 0b0101101..QDC1_CMP/POS_MATCH input is selected * 0b0101110..EVTG_OUT0A input is selected * 0b0101111..EVTG_OUT0B input is selected * 0b0110000..EVTG_OUT1A input is selected @@ -36215,10 +36166,10 @@ typedef struct { * 0b0110011..EVTG_OUT2B input is selected * 0b0110100..EVTG_OUT3A input is selected * 0b0110101..EVTG_OUT3B input is selected - * 0b0110110..FC3_P0 (SDO, RXD, SDA) input is selected - * 0b0110111..FC3_P1 (SCK, TXD, SCL)) input is selected - * 0b0111000..FC3_P2 (SDI, RTS, SCLS, TXD) input is selected - * 0b0111001..FC3_P3 (PCS[0], CTS, SDAS, RXD) input is selected + * 0b0110110..FC3_P0 (SDO, SDA) input is selected + * 0b0110111..FC3_P1 (SCK, TXD, SCL) input is selected + * 0b0111000..FC3_P2 (RTS, SCLS, TXD) input is selected + * 0b0111001..FC3_P3 (PCS[0], CTS, SDAS) input is selected * 0b0111010..Reserved * 0b0111011..Reserved * 0b0111100..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected @@ -36251,7 +36202,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36275,23 +36226,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36315,8 +36266,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK) @@ -36327,7 +36278,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36351,23 +36302,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36391,8 +36342,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK) @@ -36403,7 +36354,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36427,23 +36378,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36467,8 +36418,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK) @@ -36479,7 +36430,7 @@ typedef struct { #define INPUTMUX_CTIMER0CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER0CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36503,23 +36454,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36543,19 +36494,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER0CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK) /*! @} */ -/*! @name TIMER0TRIG - Trigger Register for TIMER */ +/*! @name TIMER0TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36579,23 +36530,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36619,8 +36570,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) @@ -36631,7 +36582,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36655,23 +36606,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36695,8 +36646,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK) @@ -36707,7 +36658,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36731,23 +36682,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36771,8 +36722,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK) @@ -36783,7 +36734,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36807,23 +36758,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36847,8 +36798,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK) @@ -36859,7 +36810,7 @@ typedef struct { #define INPUTMUX_CTIMER1CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER1CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36883,23 +36834,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36923,19 +36874,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER1CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK) /*! @} */ -/*! @name TIMER1TRIG - Trigger Register for TIMER */ +/*! @name TIMER1TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -36959,23 +36910,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -36999,8 +36950,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) @@ -37011,7 +36962,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37035,23 +36986,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37075,8 +37026,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK) @@ -37087,7 +37038,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37111,23 +37062,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37151,8 +37102,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK) @@ -37163,7 +37114,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37187,23 +37138,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37227,8 +37178,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK) @@ -37239,7 +37190,7 @@ typedef struct { #define INPUTMUX_CTIMER2CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER2CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37263,23 +37214,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37303,19 +37254,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER2CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK) /*! @} */ -/*! @name TIMER2TRIG - Trigger Register for TIMER */ +/*! @name TIMER2TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37339,23 +37290,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0_IRQ input is selected * 0b0011010..ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37379,8 +37330,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) @@ -37392,7 +37343,7 @@ typedef struct { #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU) #define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U) /*! INP - Input number select to SmartDMA ARCHB input - * 0b0000000..GPIO P0_0 input is selected + * 0b0000000..FlexIO interrupt is selected as input * 0b0000001..GPIO P0_1 input is selected * 0b0000010..GPIO P0_2 input is selected * 0b0000011..GPIO P0_3 input is selected @@ -37424,7 +37375,7 @@ typedef struct { * 0b0011101..WWDT0 WDT0_IRQ input is selected * 0b0011110..ADC0 ADC0_IRQ input is selected * 0b0011111..CMP0_IRQ input is selected - * 0b0100000..LPSPI LSPI_HS_IRQ input is selected + * 0b0100000..Reserved * 0b0100001..LP_FLEXCOMM7_IRQ input is selected * 0b0100010..LP_FLEXCOMM6_IRQ input is selected * 0b0100011..LP_FLEXCOMM5_IRQ input is selected @@ -37435,10 +37386,12 @@ typedef struct { * 0b0101000..LP_FLEXCOMM0_IRQ input is selected * 0b0101001..DMA0_IRQ input is selected * 0b0101010..DMA1_IRQ input is selected - * 0b0101011..SYS_IRQ input is selected + * 0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure + * violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR + * operation. input is selected * 0b0101100..RTC_COMBO_IRQ input is selected * 0b0101101..ARM_TXEV input is selected - * 0b0101110..PINT GPIO_INT_BMATCH input is selected + * 0b0101110..PINT0 GPIO_INT_BMATCH input is selected * 0b0101111..Reserved * 0b0110000..Reserved * 0b0110001..CMP0_OUT input is selected @@ -37451,8 +37404,8 @@ typedef struct { * 0b0111000..DAC1_IRQ/DAC2_IRQ input is selected * 0b0111001..PWM0_IRQ input is selected * 0b0111010..PWM1_IRQ input is selected - * 0b0111011..ENC0_IRQ input is selected - * 0b0111100..ENC1_IRQ input is selected + * 0b0111011..QDC0_IRQ input is selected + * 0b0111100..QDC1_IRQ input is selected * 0b0111101..EVTG_OUT0A input is selected * 0b0111110..EVTG_OUT1A input is selected * 0b0111111..Reserved @@ -37555,7 +37508,7 @@ typedef struct { #define INPUTMUX_FREQMEAS_REF_INP_MASK (0x3FU) #define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) -/*! INP - Clock source number (binary value) for frequency measure function target clock. +/*! INP - Clock source number (binary value) for frequency measure function reference clock. * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected * 0b000001..FRO_12M input is selected * 0b000010..FRO_144M input is selected @@ -37597,7 +37550,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37621,23 +37574,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37661,8 +37614,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK) @@ -37673,7 +37626,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37697,23 +37650,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37737,8 +37690,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK) @@ -37749,7 +37702,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37773,23 +37726,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37813,8 +37766,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK) @@ -37825,7 +37778,7 @@ typedef struct { #define INPUTMUX_CTIMER3CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER3CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37849,23 +37802,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37889,19 +37842,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER3CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK) /*! @} */ -/*! @name TIMER3TRIG - Trigger Register for TIMER */ +/*! @name TIMER3TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -37925,23 +37878,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -37965,8 +37918,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) @@ -37977,7 +37930,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP0_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP0_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38001,23 +37954,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38041,8 +37994,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK) @@ -38053,7 +38006,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP1_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP1_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38077,23 +38030,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38117,8 +38070,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK) @@ -38129,7 +38082,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP2_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP2_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38153,23 +38106,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38193,8 +38146,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK) @@ -38205,7 +38158,7 @@ typedef struct { #define INPUTMUX_CTIMER4CAP3_INP_MASK (0x7FU) #define INPUTMUX_CTIMER4CAP3_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38229,23 +38182,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38269,19 +38222,19 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_CTIMER4CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK) /*! @} */ -/*! @name TIMER4TRIG - Trigger Register for TIMER */ +/*! @name TIMER4TRIG - Trigger Register for CTIMER */ /*! @{ */ #define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) #define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) -/*! INP - Input number for CTIMER0 +/*! INP - Input number for CTIMER * 0b0000000..CT_INP0 input is selected * 0b0000001..CT_INP1 input is selected * 0b0000010..CT_INP2 input is selected @@ -38305,23 +38258,23 @@ typedef struct { * 0b0010100..usb0 start of frame input is selected * 0b0010101..usb1 start of frame input is selected * 0b0010110..DCDC_BURST_ACTIVE input is selected - * 0b0010111..sai0_tx_sync_out input is selected - * 0b0011000..sai0_rx_sync_out input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * 0b0011001..ADC0 ADC0_IRQ input is selected * 0b0011010..ADC0 ADC1_IRQ input is selected * 0b0011011..CMP0_OUT input is selected * 0b0011100..CMP1_OUT input is selected * 0b0011101..CMP2_OUT input is selected - * 0b0011110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b0100000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b0100001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b0100010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b0100011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b0100100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b0100101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b0100110..ENC0_CMP/POS_MATCH input is selected - * 0b0100111..ENC1_CMP/POS_MATCH input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected * 0b0101000..EVTG_OUT0A input is selected * 0b0101001..EVTG_OUT0B input is selected * 0b0101010..EVTG_OUT1A input is selected @@ -38345,8 +38298,8 @@ typedef struct { * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected - * 0b0111111..sai1_tx_sync_out input is selected - * 0b1000000..sai1_rx_sync_out input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected * *.. */ #define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) @@ -38369,22 +38322,22 @@ typedef struct { * 0b001000..CTIMER0_MAT0 input is selected * 0b001001..CTIMER4_MAT0 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC1_tcomp[0] input is selected * 0b001111..Reserved * 0b010000..Reserved - * 0b010001..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b010010..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b010011..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b010100..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b010101..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b010110..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b010111..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b011000..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b011001..ENC0_CMP/POS_MATCH input is selected - * 0b011010..ENC1_CMP/POS_MATCH input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected @@ -38421,7 +38374,7 @@ typedef struct { * 0b00001000..CTIMER3_MAT3 input is selected * 0b00001001..CTIMER4_MAT3 input is selected * 0b00001010..DCDC_Burst_Done_Trig input is selected - * 0b00001011..ARM_TXEV input is selected + * 0b00001011..Reserved * 0b00001100..PINT GPIO_INT_BMAT input is selected * 0b00001101..ADC0_tcomp[0] input is selected * 0b00001110..ADC0_tcomp[1] input is selected @@ -38434,24 +38387,24 @@ typedef struct { * 0b00010101..CMP0_OUT input is selected * 0b00010110..CMP1_OUT input is selected * 0b00010111..CMP2_OUT input is selected - * 0b00011000..PWM0_A0_TRIG0 input is selected - * 0b00011001..PWM0_A0_TRIG1 input is selected - * 0b00011010..PWM0_A1_TRIG0 input is selected - * 0b00011011..PWM0_A1_TRIG1 input is selected - * 0b00011100..PWM0_A2_TRIG0 input is selected - * 0b00011101..PWM0_A2_TRIG1 input is selected - * 0b00011110..PWM0_A3_TRIG0 input is selected - * 0b00011111..PWM0_A3_TRIG1 input is selected - * 0b00100000..PWM1_A0_TRIG0 input is selected - * 0b00100001..PWM1_A0_TRIG1 input is selected - * 0b00100010..PWM1_A1_TRIG0 input is selected - * 0b00100011..PWM1_A1_TRIG1 input is selected - * 0b00100100..PWM1_A2_TRIG0 input is selected - * 0b00100101..PWM1_A2_TRIG1 input is selected - * 0b00100110..PWM1_A3_TRIG0 input is selected - * 0b00100111..PWM1_A3_TRIG1 input is selected - * 0b00101000..ENC0_CMP/POS_MATCH input is selected - * 0b00101001..ENC1_CMP/POS_MATCH input is selected + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected * 0b00101010..EVTG_OUT0A input is selected * 0b00101011..EVTG_OUT0B input is selected * 0b00101100..EVTG_OUT1A input is selected @@ -38489,7 +38442,7 @@ typedef struct { #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU) #define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) -/*! TRIGIN - ADC0 trigger inputs +/*! TRIGIN - ADC1 trigger inputs * 0b00000000..PINT PIN_INT0 input is selected * 0b00000001..PINT PIN_INT2 input is selected * 0b00000010..SCT0 SCT_OUT4 input is selected @@ -38501,7 +38454,7 @@ typedef struct { * 0b00001000..CTIMER3_MAT2 input is selected * 0b00001001..CTIMER4_MAT1 input is selected * 0b00001010..DCDC_Burst_Done_Trig input is selected - * 0b00001011..ARM_TXEV input is selected + * 0b00001011..Reserved * 0b00001100..PINT GPIO_INT_BMAT input is selected * 0b00001101..ADC0_tcomp[0] input is selected * 0b00001110..ADC0_tcomp[1] input is selected @@ -38514,24 +38467,24 @@ typedef struct { * 0b00010101..CMP0_OUT input is selected * 0b00010110..CMP1_OUT input is selected * 0b00010111..CMP2_OUT input is selected - * 0b00011000..PWM0_A0_TRIG0 input is selected - * 0b00011001..PWM0_A0_TRIG1 input is selected - * 0b00011010..PWM0_A1_TRIG0 input is selected - * 0b00011011..PWM0_A1_TRIG1 input is selected - * 0b00011100..PWM0_A2_TRIG0 input is selected - * 0b00011101..PWM0_A2_TRIG1 input is selected - * 0b00011110..PWM0_A3_TRIG0 input is selected - * 0b00011111..PWM0_A3_TRIG1 input is selected - * 0b00100000..PWM1_A0_TRIG0 input is selected - * 0b00100001..PWM1_A0_TRIG1 input is selected - * 0b00100010..PWM1_A1_TRIG0 input is selected - * 0b00100011..PWM1_A1_TRIG1 input is selected - * 0b00100100..PWM1_A2_TRIG0 input is selected - * 0b00100101..PWM1_A2_TRIG1 input is selected - * 0b00100110..PWM1_A3_TRIG0 input is selected - * 0b00100111..PWM1_A3_TRIG1 input is selected - * 0b00101000..ENC0_CMP/POS_MATCH input is selected - * 0b00101001..ENC1_CMP/POS_MATCH input is selected + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected * 0b00101010..EVTG_OUT0A input is selected * 0b00101011..EVTG_OUT0B input is selected * 0b00101100..EVTG_OUT1A input is selected @@ -38581,7 +38534,7 @@ typedef struct { * 0b001000..CTIMER2_MAT0 input is selected * 0b001001..CTIMER3_MAT0 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC1_tcomp[0] input is selected @@ -38624,7 +38577,7 @@ typedef struct { * 0b001000..CTIMER2_MAT1 input is selected * 0b001001..CTIMER3_MAT1 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[1] input is selected * 0b001110..ADC1_tcomp[1] input is selected @@ -38667,7 +38620,7 @@ typedef struct { * 0b001000..CTIMER2_MAT2 input is selected * 0b001001..CTIMER3_MAT2 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[2] input is selected * 0b001110..ADC1_tcomp[2] input is selected @@ -38693,12 +38646,12 @@ typedef struct { #define INPUTMUX_DAC2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK) /*! @} */ -/*! @name ENC0_TRIG - ENC0 Trigger Input Connections */ +/*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_TRIG_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38723,16 +38676,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38753,15 +38706,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_TRIG_INP_SHIFT)) & INPUTMUX_ENC0_TRIG_INP_MASK) +#define INPUTMUX_QDCN_QDC_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK) /*! @} */ -/*! @name ENC0_HOME - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_TRIG */ +#define INPUTMUX_QDCN_QDC_TRIG_COUNT (2U) + +/*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_HOME_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_HOME_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_HOME_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT (0U) +/*! INP - QDC1 HOME input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT0 SCT_OUT4 input is selected @@ -38786,16 +38742,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38816,15 +38772,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_HOME_INP_SHIFT)) & INPUTMUX_ENC0_HOME_INP_MASK) +#define INPUTMUX_QDCN_QDC_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK) /*! @} */ -/*! @name ENC0_INDEX - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_HOME */ +#define INPUTMUX_QDCN_QDC_HOME_COUNT (2U) + +/*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_INDEX_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_INDEX_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_INDEX_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 INDEX input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38849,16 +38808,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38879,15 +38838,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_INDEX_INP_SHIFT)) & INPUTMUX_ENC0_INDEX_INP_MASK) +#define INPUTMUX_QDCN_QDC_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK) /*! @} */ -/*! @name ENC0_PHASEB - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_INDEX */ +#define INPUTMUX_QDCN_QDC_INDEX_COUNT (2U) + +/*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_PHASEB_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_PHASEB_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 PHASEB input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38912,16 +38874,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -38942,15 +38904,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEB_INP_SHIFT)) & INPUTMUX_ENC0_PHASEB_INP_MASK) +#define INPUTMUX_QDCN_QDC_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK) /*! @} */ -/*! @name ENC0_PHASEA - ENC0 Input Connections */ +/* The count of INPUTMUX_QDCN_QDC_PHASEB */ +#define INPUTMUX_QDCN_QDC_PHASEB_COUNT (2U) + +/*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */ /*! @{ */ -#define INPUTMUX_ENC0_PHASEA_INP_MASK (0x3FU) -#define INPUTMUX_ENC0_PHASEA_INP_SHIFT (0U) -/*! INP - ENC0 input connections +#define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT (0U) +/*! INP - QDC1 PHASEA input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT4 input is selected * 0b000010..SCT_OUT4 input is selected @@ -38975,16 +38940,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39005,330 +38970,18 @@ typedef struct { * 0b110011..TRIG_IN9 input is selected * *.. */ -#define INPUTMUX_ENC0_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEA_INP_SHIFT)) & INPUTMUX_ENC0_PHASEA_INP_MASK) +#define INPUTMUX_QDCN_QDC_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK) /*! @} */ -/*! @name ENC1_TRIG - ENC1 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_TRIG_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_TRIG_INP_SHIFT)) & INPUTMUX_ENC1_TRIG_INP_MASK) -/*! @} */ - -/*! @name ENC1_HOME - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_HOME_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_HOME_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_HOME_INP_SHIFT)) & INPUTMUX_ENC1_HOME_INP_MASK) -/*! @} */ - -/*! @name ENC1_INDEX - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_INDEX_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_INDEX_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_INDEX_INP_SHIFT)) & INPUTMUX_ENC1_INDEX_INP_MASK) -/*! @} */ - -/*! @name ENC1_PHASEB - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_PHASEB_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_PHASEB_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEB_INP_SHIFT)) & INPUTMUX_ENC1_PHASEB_INP_MASK) -/*! @} */ - -/*! @name ENC1_PHASEA - ENC1 Input Connections */ -/*! @{ */ - -#define INPUTMUX_ENC1_PHASEA_INP_MASK (0x3FU) -#define INPUTMUX_ENC1_PHASEA_INP_SHIFT (0U) -/*! INP - ENC1 input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT5 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT1 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER1_MAT1 input is selected - * 0b001001..CTIMER3_MAT1 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected - * 0b100010..EVTG_OUT0A input is selected - * 0b100011..EVTG_OUT0B input is selected - * 0b100100..EVTG_OUT1A input is selected - * 0b100101..EVTG_OUT1B input is selected - * 0b100110..EVTG_OUT2A input is selected - * 0b100111..EVTG_OUT2B input is selected - * 0b101000..EVTG_OUT3A input is selected - * 0b101001..EVTG_OUT3B input is selected - * 0b101010..TRIG_IN0 input is selected - * 0b101011..TRIG_IN1 input is selected - * 0b101100..TRIG_IN2 input is selected - * 0b101101..TRIG_IN3 input is selected - * 0b101110..TRIG_IN4 input is selected - * 0b101111..TRIG_IN5 input is selected - * 0b110000..TRIG_IN6 input is selected - * 0b110001..TRIG_IN7 input is selected - * 0b110010..TRIG_IN8 input is selected - * 0b110011..TRIG_IN9 input is selected - * *.. - */ -#define INPUTMUX_ENC1_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEA_INP_SHIFT)) & INPUTMUX_ENC1_PHASEA_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_QDCN_QDC_PHASEA */ +#define INPUTMUX_QDCN_QDC_PHASEA_COUNT (2U) /*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTSYNC input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39353,16 +39006,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39403,7 +39056,7 @@ typedef struct { #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTA input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39428,16 +39081,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39478,7 +39131,7 @@ typedef struct { #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTFORCE input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39503,16 +39156,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39550,7 +39203,7 @@ typedef struct { #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - FAULT input connections for PWM0 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39575,16 +39228,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM1_A0_TRIG0 input is selected - * 0b011001..PWM1_A0_TRIG1 input is selected - * 0b011010..PWM1_A1_TRIG0 input is selected - * 0b011011..PWM1_A1_TRIG1 input is selected - * 0b011100..PWM1_A2_TRIG0 input is selected - * 0b011101..PWM1_A2_TRIG1 input is selected - * 0b011110..PWM1_A3_TRIG0 input is selected - * 0b011111..PWM1_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39625,7 +39278,7 @@ typedef struct { #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTSYNC input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39650,16 +39303,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39695,12 +39348,12 @@ typedef struct { /* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */ #define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U) -/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input Trigger Connections */ +/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */ /*! @{ */ #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM0 +/*! TRIGIN - EXTA input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39725,16 +39378,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39775,7 +39428,7 @@ typedef struct { #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 +/*! TRIGIN - EXTFORCE input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39800,16 +39453,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39847,7 +39500,7 @@ typedef struct { #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) #define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM1 +/*! TRIGIN - FAULT input connections for PWM1 * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT2 input is selected * 0b000010..SCT_OUT4 input is selected @@ -39872,16 +39525,16 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..ENC0_CMP/POS_MATCH input is selected - * 0b100001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected * 0b100010..EVTG_OUT0A input is selected * 0b100011..EVTG_OUT0B input is selected * 0b100100..EVTG_OUT1A input is selected @@ -39922,7 +39575,7 @@ typedef struct { #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U) #define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM +/*! TRIGIN - EXT_CLK input connections for PWM0 * 0b000..FRO16K input is selected * 0b001..OSC_32k input is selected * 0b010..EVTG_OUT0A input is selected @@ -39939,7 +39592,7 @@ typedef struct { #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) #define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) -/*! TRIGIN - Trigger input connections for PWM +/*! TRIGIN - EXT_CLK input connections for PWM1 * 0b0000..FRO16K input is selected * 0b0001..OSC_32k input is selected * 0b0010..EVTG_OUT0A input is selected @@ -39951,11 +39604,11 @@ typedef struct { #define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) /*! @} */ -/*! @name EVTG_TRIG0 - EVTG Trigger Input Connections 0 */ +/*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_EVTG_TRIG0_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG0_INP_SHIFT (0U) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT (0U) /*! INP - EVTG trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected @@ -39984,24 +39637,24 @@ typedef struct { * 0b011000..CMP0_OUT input is selected * 0b011001..CMP1_OUT input is selected * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected + * 0b011011..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100111..PWM1_SM2_MUX_TRIG0 input is selected + * 0b101000..PWM1_SM2_MUX_TRIG1 input is selected + * 0b101001..PWM1_SM3_MUX_TRIG0 input is selected + * 0b101010..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101011..QDC0_CMP/POS_MATCH input is selected + * 0b101100..QDC1_CMP/POS_MATCH input is selected * 0b101101..TRIG_IN0 input is selected * 0b101110..TRIG_IN1 input is selected * 0b101111..TRIG_IN2 input is selected @@ -40017,1043 +39670,11 @@ typedef struct { * 0b111001..Reserved * *.. */ -#define INPUTMUX_EVTG_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG0_INP_SHIFT)) & INPUTMUX_EVTG_TRIG0_INP_MASK) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK) /*! @} */ -/*! @name EVTG_TRIG1 - EVTG Trigger Input Connections 1 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG1_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG1_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG1_INP_SHIFT)) & INPUTMUX_EVTG_TRIG1_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG2 - EVTG Trigger Input Connections 2 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG2_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG2_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG2_INP_SHIFT)) & INPUTMUX_EVTG_TRIG2_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG3 - EVTG Trigger Input Connections 3 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG3_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG3_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG3_INP_SHIFT)) & INPUTMUX_EVTG_TRIG3_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG4 - EVTG Trigger Input Connections 4 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG4_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG4_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..GPIO_INT_BMATCH input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG4_INP_SHIFT)) & INPUTMUX_EVTG_TRIG4_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG5 - EVTG Trigger Input Connections 5 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG5_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG5_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG5_INP_SHIFT)) & INPUTMUX_EVTG_TRIG5_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG6 - EVTG Trigger Input Connections 6 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG6_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG6_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG6_INP_SHIFT)) & INPUTMUX_EVTG_TRIG6_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG7 - EVTG Trigger Input Connections 7 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG7_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG7_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG7_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG7_INP_SHIFT)) & INPUTMUX_EVTG_TRIG7_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG8 - EVTG Trigger Input Connections 8 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG8_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG8_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG8_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG8_INP_SHIFT)) & INPUTMUX_EVTG_TRIG8_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG9 - EVTG Trigger Input Connections 9 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG9_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG9_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG9_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG9_INP_SHIFT)) & INPUTMUX_EVTG_TRIG9_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG10 - EVTG Trigger Input Connections 10 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG10_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG10_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG10_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG10_INP_SHIFT)) & INPUTMUX_EVTG_TRIG10_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG11 - EVTG Trigger Input Connections 11 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG11_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG11_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG11_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG11_INP_SHIFT)) & INPUTMUX_EVTG_TRIG11_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG12 - EVTG Trigger Input Connections 12 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG12_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG12_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG12_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG12_INP_SHIFT)) & INPUTMUX_EVTG_TRIG12_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG13 - EVTG Trigger Input Connections 13 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG13_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG13_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG13_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG13_INP_SHIFT)) & INPUTMUX_EVTG_TRIG13_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG14 - EVTG Trigger Input Connections 14 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG14_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG14_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG14_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG14_INP_SHIFT)) & INPUTMUX_EVTG_TRIG14_INP_MASK) -/*! @} */ - -/*! @name EVTG_TRIG15 - EVTG Trigger Input Connections 15 */ -/*! @{ */ - -#define INPUTMUX_EVTG_TRIG15_INP_MASK (0x3FU) -#define INPUTMUX_EVTG_TRIG15_INP_SHIFT (0U) -/*! INP - EVTG trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT0 input is selected - * 0b000011..SCT_OUT1 input is selected - * 0b000100..SCT_OUT2 input is selected - * 0b000101..SCT_OUT3 input is selected - * 0b000110..CTIMER0_MAT3 input is selected - * 0b000111..CTIMER1_MAT3 input is selected - * 0b001000..CTIMER2_MAT3 input is selected - * 0b001001..CTIMER2_MAT2 input is selected - * 0b001010..CTIMER3_MAT2 input is selected - * 0b001011..CTIMER4_MAT2 input is selected - * 0b001100..Reserved - * 0b001101..PINT GPIO_INT_BMAT input is selected - * 0b001110..ADC0_IRQ input is selected - * 0b001111..ADC1_IRQ input is selected - * 0b010000..ADC0_tcomp[0] input is selected - * 0b010001..ADC0_tcomp[1] input is selected - * 0b010010..ADC0_tcomp[2] input is selected - * 0b010011..ADC0_tcomp[3] input is selected - * 0b010100..ADC1_tcomp[0] input is selected - * 0b010101..ADC1_tcomp[1] input is selected - * 0b010110..ADC1_tcomp[2] input is selected - * 0b010111..ADC1_tcomp[3] input is selected - * 0b011000..CMP0_OUT input is selected - * 0b011001..CMP1_OUT input is selected - * 0b011010..CMP2_OUT input is selected - * 0b011011..PWM0_A0_TRIG0 input is selected - * 0b011100..PWM0_A0_TRIG1 input is selected - * 0b011101..PWM0_A1_TRIG0 input is selected - * 0b011110..PWM0_A1_TRIG1 input is selected - * 0b011111..PWM0_A2_TRIG0 input is selected - * 0b100000..PWM0_A2_TRIG1 input is selected - * 0b100001..PWM0_A3_TRIG0 input is selected - * 0b100010..PWM0_A3_TRIG1 input is selected - * 0b100011..PWM1_A0_TRIG0 input is selected - * 0b100100..PWM1_A0_TRIG1 input is selected - * 0b100101..PWM1_A1_TRIG0 input is selected - * 0b100110..PWM1_A1_TRIG1 input is selected - * 0b100111..PWM1_A2_TRIG0 input is selected - * 0b101000..PWM1_A2_TRIG1 input is selected - * 0b101001..PWM1_A3_TRIG0 input is selected - * 0b101010..PWM1_A3_TRIG1 input is selected - * 0b101011..ENC0_CMP/POS_MATCH input is selected - * 0b101100..ENC1_CMP/POS_MATCH input is selected - * 0b101101..TRIG_IN0 input is selected - * 0b101110..TRIG_IN1 input is selected - * 0b101111..TRIG_IN2 input is selected - * 0b110000..TRIG_IN3 input is selected - * 0b110001..LPTMR0 input is selected - * 0b110010..LPTMR1 input is selected - * 0b110011..SINC Filter CH0 Break input is selected - * 0b110100..SINC Filter CH1 Break input is selected - * 0b110101..SINC Filter CH2 Break input is selected - * 0b110110..SINC Filter CH3 Break input is selected - * 0b110111..SINC Filter CH4 Break input is selected - * 0b111000..Reserved - * 0b111001..Reserved - * *.. - */ -#define INPUTMUX_EVTG_TRIG15_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIG15_INP_SHIFT)) & INPUTMUX_EVTG_TRIG15_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT (16U) /*! @name USBFS_TRIG - USB-FS Trigger Input Connections */ /*! @{ */ @@ -41089,28 +39710,28 @@ typedef struct { #define INPUTMUX_TSI_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TSI_TRIG_INP_SHIFT)) & INPUTMUX_TSI_TRIG_INP_MASK) /*! @} */ -/*! @name EXT_TRIG0 - EXT Trigger Connections 0 */ +/*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */ /*! @{ */ -#define INPUTMUX_EXT_TRIG0_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG0_INP_SHIFT (0U) -/*! INP - EXT trigger input connections +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) +/*! INP - TRIG_OUTa pin input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected * 0b000010..ADC0_IRQ input is selected * 0b000011..ADC1_IRQ input is selected * 0b000100..ADC0_tcomp[0] input is selected * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected + * 0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b001110..QDC0_CMP/POS_MATCH input is selected + * 0b001111..QDC1_CMP/POS_MATCH input is selected * 0b010000..EVTG_OUT0A input is selected * 0b010001..EVTG_OUT0B input is selected * 0b010010..EVTG_OUT1A input is selected @@ -41129,437 +39750,27 @@ typedef struct { * 0b011111..SCT Out3 input is selected * 0b100000..SCT Out4 input is selected * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected + * 0b100010..LP_FLEXCOMM0 trigger output 3 input is selected + * 0b100011..LP_FLEXCOMM1 trigger output 3 input is selected + * 0b100100..LP_FLEXCOMM2 trigger output 3 input is selected + * 0b100101..LP_FLEXCOMM3 trigger output 3 input is selected + * 0b100110..LP_FLEXCOMM4 trigger output 3 input is selected + * 0b100111..LP_FLEXCOMM5 trigger output 3 input is selected + * 0b101000..LP_FLEXCOMM6 trigger output 3 input is selected + * 0b101001..LP_FLEXCOMM7 trigger output 3 input is selected + * 0b101010..LP_FLEXCOMM8 trigger output 3 input is selected + * 0b101011..LP_FLEXCOMM9 trigger output 3 input is selected * 0b101100..CMP0_OUT input is selected * 0b101101..CMP1_OUT input is selected * 0b101110..CMP2_OUT input is selected * 0b101111..ENET_PPS_OUT_0 input is selected * *.. */ -#define INPUTMUX_EXT_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG0_INP_SHIFT)) & INPUTMUX_EXT_TRIG0_INP_MASK) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) /*! @} */ -/*! @name EXT_TRIG1 - EXT Trigger Connections 1 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG1_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG1_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG1_INP_SHIFT)) & INPUTMUX_EXT_TRIG1_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG2 - EXT Trigger Connections 2 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG2_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG2_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG2_INP_SHIFT)) & INPUTMUX_EXT_TRIG2_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG3 - EXT Trigger Connections 3 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG3_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG3_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG3_INP_SHIFT)) & INPUTMUX_EXT_TRIG3_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG4 - EXT Trigger Connections 4 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG4_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG4_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG4_INP_SHIFT)) & INPUTMUX_EXT_TRIG4_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG5 - EXT Trigger Connections 5 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG5_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG5_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG5_INP_SHIFT)) & INPUTMUX_EXT_TRIG5_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG6 - EXT Trigger Connections 6 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG6_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG6_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG6_INP_SHIFT)) & INPUTMUX_EXT_TRIG6_INP_MASK) -/*! @} */ - -/*! @name EXT_TRIG7 - EXT Trigger Connections 7 */ -/*! @{ */ - -#define INPUTMUX_EXT_TRIG7_INP_MASK (0x3FU) -#define INPUTMUX_EXT_TRIG7_INP_SHIFT (0U) -/*! INP - EXT trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..ADC0_IRQ input is selected - * 0b000011..ADC1_IRQ input is selected - * 0b000100..ADC0_tcomp[0] input is selected - * 0b000101..ADC1_tcomp[0] input is selected - * 0b000110..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b000111..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b001000..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b001001..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b001010..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b001011..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b001100..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b001101..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b001110..ENC0_CMP/POS_MATCH input is selected - * 0b001111..ENC1_CMP/POS_MATCH input is selected - * 0b010000..EVTG_OUT0A input is selected - * 0b010001..EVTG_OUT0B input is selected - * 0b010010..EVTG_OUT1A input is selected - * 0b010011..EVTG_OUT1B input is selected - * 0b010100..EVTG_OUT2A input is selected - * 0b010101..EVTG_OUT2B input is selected - * 0b010110..EVTG_OUT3A input is selected - * 0b010111..EVTG_OUT3B input is selected - * 0b011000..Reserved - * 0b011001..Reserved - * 0b011010..LPTMR0 input is selected - * 0b011011..LPTMR1 input is selected - * 0b011100..SCT Out0 input is selected - * 0b011101..SCT Out1 input is selected - * 0b011110..SCT Out2 input is selected - * 0b011111..SCT Out3 input is selected - * 0b100000..SCT Out4 input is selected - * 0b100001..SCT Out5 input is selected - * 0b100010..Flexcomm0 trigger output 3 input is selected - * 0b100011..Flexcomm1 trigger output 3 input is selected - * 0b100100..Flexcomm2 trigger output 3 input is selected - * 0b100101..Flexcomm3 trigger output 3 input is selected - * 0b100110..Flexcomm4 trigger output 3 input is selected - * 0b100111..Flexcomm5 trigger output 3 input is selected - * 0b101000..Flexcomm6 trigger output 3 input is selected - * 0b101001..Flexcomm7 trigger output 3 input is selected - * 0b101010..Flexcomm8 trigger output 3 input is selected - * 0b101011..Flexcomm9 trigger output 3 input is selected - * 0b101100..CMP0_OUT input is selected - * 0b101101..CMP1_OUT input is selected - * 0b101110..CMP2_OUT input is selected - * 0b101111..ENET_PPS_OUT_0 input is selected - * *.. - */ -#define INPUTMUX_EXT_TRIG7_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG7_INP_SHIFT)) & INPUTMUX_EXT_TRIG7_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) /*! @name CMP1_TRIG - CMP1 Input Connections */ /*! @{ */ @@ -41578,22 +39789,22 @@ typedef struct { * 0b001000..CTIMER3_MAT1 input is selected * 0b001001..CTIMER4_MAT1 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[1] input is selected * 0b001110..ADC1_tcomp[1] input is selected * 0b001111..Reserved * 0b010000..Reserved - * 0b010001..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b010010..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b010011..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b010100..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b010101..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b010110..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b010111..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b011000..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b011001..ENC0_CMP/POS_MATCH input is selected - * 0b011010..ENC1_CMP/POS_MATCH input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected @@ -41630,22 +39841,22 @@ typedef struct { * 0b001000..CTIMER3_MAT2 input is selected * 0b001001..CTIMER4_MAT2 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[2] input is selected * 0b001110..ADC1_tcomp[2] input is selected * 0b001111..Reserved * 0b010000..Reserved - * 0b010001..PWM0_A0_TRIG0/PWM0_A0_TRIG1 input is selected - * 0b010010..PWM0_A1_TRIG0/PWM0_A1_TRIG1 input is selected - * 0b010011..PWM0_A2_TRIG0/PWM0_A2_TRIG1 input is selected - * 0b010100..PWM0_A3_TRIG0/PWM0_A3_TRIG1 input is selected - * 0b010101..PWM1_A0_TRIG0/PWM1_A0_TRIG1 input is selected - * 0b010110..PWM1_A1_TRIG0/PWM1_A1_TRIG1 input is selected - * 0b010111..PWM1_A2_TRIG0/PWM1_A2_TRIG1 input is selected - * 0b011000..PWM1_A3_TRIG0/PWM1_A3_TRIG1 input is selected - * 0b011001..ENC0_CMP/POS_MATCH input is selected - * 0b011010..ENC1_CMP/POS_MATCH input is selected + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected * 0b011011..EVTG_OUT0A input is selected * 0b011100..EVTG_OUT0B input is selected * 0b011101..EVTG_OUT1A input is selected @@ -41665,11 +39876,11 @@ typedef struct { #define INPUTMUX_CMP2_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP2_TRIG_TRIGIN_MASK) /*! @} */ -/*! @name SINC_FILTER_CH0 - SINC Filter Channel0 Trigger Input Connections */ +/*! @name SINC_FILTER_CHN_SINC_FILTER_CH - SINC Filter Channel Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_SINC_FILTER_CH0_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH0_INP_SHIFT (0U) +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK (0x3FU) +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT (0U) /*! INP - SINC FILTER trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected @@ -41682,7 +39893,7 @@ typedef struct { * 0b001000..CTIMER3_MAT3 input is selected * 0b001001..CTIMER4_MAT3 input is selected * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected + * 0b001011..Reserved * 0b001100..PINT GPIO_INT_BMAT input is selected * 0b001101..ADC0_tcomp[0] input is selected * 0b001110..ADC0_tcomp[1] input is selected @@ -41695,24 +39906,24 @@ typedef struct { * 0b010101..CMP0_OUT input is selected * 0b010110..CMP1_OUT input is selected * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101000..QDC0_CMP/POS_MATCH input is selected + * 0b101001..QDC1_CMP/POS_MATCH input is selected * 0b101010..EVTG_OUT0A input is selected * 0b101011..EVTG_OUT0B input is selected * 0b101100..EVTG_OUT1A input is selected @@ -41730,286 +39941,17 @@ typedef struct { * 0b111000..WUU input is selected * *.. */ -#define INPUTMUX_SINC_FILTER_CH0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH0_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH0_INP_MASK) +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_INP_MASK) /*! @} */ -/*! @name SINC_FILTER_CH1 - SINC Filter Channel1 Trigger Input Connections */ +/* The count of INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH */ +#define INPUTMUX_SINC_FILTER_CHN_SINC_FILTER_CH_COUNT (5U) + +/*! @name OPAMPN_TRIG_OPAMP_TRIG - OPAMP Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_SINC_FILTER_CH1_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH1_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH1_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH1_INP_MASK) -/*! @} */ - -/*! @name SINC_FILTER_CH2 - SINC Filter Channel2 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_SINC_FILTER_CH2_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH2_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH2_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH2_INP_MASK) -/*! @} */ - -/*! @name SINC_FILTER_CH3 - SINC Filter Channel3 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_SINC_FILTER_CH3_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH3_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH3_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH3_INP_MASK) -/*! @} */ - -/*! @name SINC_FILTER_CH4 - SINC Filter Channel4 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_SINC_FILTER_CH4_INP_MASK (0x3FU) -#define INPUTMUX_SINC_FILTER_CH4_INP_SHIFT (0U) -/*! INP - SINC FILTER trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..SCT_OUT4 input is selected - * 0b000011..SCT_OUT5 input is selected - * 0b000100..SCT_OUT9 input is selected - * 0b000101..CTIMER0_MAT3 input is selected - * 0b000110..CTIMER1_MAT3 input is selected - * 0b000111..CTIMER2_MAT3 input is selected - * 0b001000..CTIMER3_MAT3 input is selected - * 0b001001..CTIMER4_MAT3 input is selected - * 0b001010..Reserved - * 0b001011..ARM_TXEV input is selected - * 0b001100..PINT GPIO_INT_BMAT input is selected - * 0b001101..ADC0_tcomp[0] input is selected - * 0b001110..ADC0_tcomp[1] input is selected - * 0b001111..ADC0_tcomp[2] input is selected - * 0b010000..ADC0_tcomp[3] input is selected - * 0b010001..ADC1_tcomp[0] input is selected - * 0b010010..ADC1_tcomp[1] input is selected - * 0b010011..ADC1_tcomp[2] input is selected - * 0b010100..ADC1_tcomp[3] input is selected - * 0b010101..CMP0_OUT input is selected - * 0b010110..CMP1_OUT input is selected - * 0b010111..CMP2_OUT input is selected - * 0b011000..PWM0_A0_TRIG0 input is selected - * 0b011001..PWM0_A0_TRIG1 input is selected - * 0b011010..PWM0_A1_TRIG0 input is selected - * 0b011011..PWM0_A1_TRIG1 input is selected - * 0b011100..PWM0_A2_TRIG0 input is selected - * 0b011101..PWM0_A2_TRIG1 input is selected - * 0b011110..PWM0_A3_TRIG0 input is selected - * 0b011111..PWM0_A3_TRIG1 input is selected - * 0b100000..PWM1_A0_TRIG0 input is selected - * 0b100001..PWM1_A0_TRIG1 input is selected - * 0b100010..PWM1_A1_TRIG0 input is selected - * 0b100011..PWM1_A1_TRIG1 input is selected - * 0b100100..PWM1_A2_TRIG0 input is selected - * 0b100101..PWM1_A2_TRIG1 input is selected - * 0b100110..PWM1_A3_TRIG0 input is selected - * 0b100111..PWM1_A3_TRIG1 input is selected - * 0b101000..ENC0_CMP/POS_MATCH input is selected - * 0b101001..ENC1_CMP/POS_MATCH input is selected - * 0b101010..EVTG_OUT0A input is selected - * 0b101011..EVTG_OUT0B input is selected - * 0b101100..EVTG_OUT1A input is selected - * 0b101101..EVTG_OUT1B input is selected - * 0b101110..EVTG_OUT2A input is selected - * 0b101111..EVTG_OUT2B input is selected - * 0b110000..EVTG_OUT3A input is selected - * 0b110001..EVTG_OUT3B input is selected - * 0b110010..LPTMR0 input is selected - * 0b110011..LPTMR1 input is selected - * 0b110100..FlexIO CH0 input is selected - * 0b110101..FlexIO CH1 input is selected - * 0b110110..FlexIO CH2 input is selected - * 0b110111..FlexIO CH3 input is selected - * 0b111000..WUU input is selected - * *.. - */ -#define INPUTMUX_SINC_FILTER_CH4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SINC_FILTER_CH4_INP_SHIFT)) & INPUTMUX_SINC_FILTER_CH4_INP_MASK) -/*! @} */ - -/*! @name OPAMP0_TRIG - OPAMP0 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_OPAMP0_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_OPAMP0_TRIG_INP_SHIFT (0U) +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT (0U) /*! INP - OPAMP trigger input connections * 0b000000..PINT PIN_INT0 input is selected * 0b000001..PINT PIN_INT1 input is selected @@ -42034,22 +39976,22 @@ typedef struct { * 0b010100..ADC1_tcomp[1] input is selected * 0b010101..ADC1_tcomp[2] input is selected * 0b010110..ADC1_tcomp[3] input is selected - * 0b010111..PWM0_A0_TRIG0 input is selected - * 0b011000..PWM0_A0_TRIG1 input is selected - * 0b011001..PWM0_A1_TRIG0 input is selected - * 0b011010..PWM0_A1_TRIG1 input is selected - * 0b011011..PWM0_A2_TRIG0 input is selected - * 0b011100..PWM0_A2_TRIG1 input is selected - * 0b011101..PWM0_A3_TRIG0 input is selected - * 0b011110..PWM0_A3_TRIG1 input is selected - * 0b011111..PWM1_A0_TRIG0 input is selected - * 0b100000..PWM1_A0_TRIG1 input is selected - * 0b100001..PWM1_A1_TRIG0 input is selected - * 0b100010..PWM1_A1_TRIG1 input is selected - * 0b100011..PWM1_A2_TRIG0 input is selected - * 0b100100..PWM1_A2_TRIG1 input is selected - * 0b100101..PWM1_A3_TRIG0 input is selected - * 0b100110..PWM1_A3_TRIG1 input is selected + * 0b010111..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011000..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011001..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011011..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG1 input is selected + * 0b011111..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100000..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100001..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100010..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM2_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM2_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM3_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM3_MUX_TRIG1 input is selected * 0b100111..EVTG_OUT0A input is selected * 0b101000..EVTG_OUT0B input is selected * 0b101001..EVTG_OUT1A input is selected @@ -42068,147 +40010,18 @@ typedef struct { * 0b110110..FlexIO CH7 input is selected * *.. */ -#define INPUTMUX_OPAMP0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP0_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP0_TRIG_INP_MASK) +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_SHIFT)) & INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_INP_MASK) /*! @} */ -/*! @name OPAMP1_TRIG - OPAMP1 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_OPAMP1_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_OPAMP1_TRIG_INP_SHIFT (0U) -/*! INP - OPAMP trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..PINT PIN_INT2 input is selected - * 0b000011..PINT PIN_INT3 input is selected - * 0b000100..SCT_OUT4 input is selected - * 0b000101..SCT_OUT5 input is selected - * 0b000110..SCT_OUT6 input is selected - * 0b000111..SCT_OUT7 input is selected - * 0b001000..SCT_OUT8 input is selected - * 0b001001..CTIMER0_MAT3 input is selected - * 0b001010..CTIMER1_MAT3 input is selected - * 0b001011..CTIMER2_MAT3 input is selected - * 0b001100..CTIMER3_MAT3 input is selected - * 0b001101..CTIMER4_MAT3 input is selected - * 0b001110..PINT GPIO_INT_BMAT input is selected - * 0b001111..ADC0_tcomp[0] input is selected - * 0b010000..ADC0_tcomp[1] input is selected - * 0b010001..ADC0_tcomp[2] input is selected - * 0b010010..ADC0_tcomp[3] input is selected - * 0b010011..ADC1_tcomp[0] input is selected - * 0b010100..ADC1_tcomp[1] input is selected - * 0b010101..ADC1_tcomp[2] input is selected - * 0b010110..ADC1_tcomp[3] input is selected - * 0b010111..PWM0_A0_TRIG0 input is selected - * 0b011000..PWM0_A0_TRIG1 input is selected - * 0b011001..PWM0_A1_TRIG0 input is selected - * 0b011010..PWM0_A1_TRIG1 input is selected - * 0b011011..PWM0_A2_TRIG0 input is selected - * 0b011100..PWM0_A2_TRIG1 input is selected - * 0b011101..PWM0_A3_TRIG0 input is selected - * 0b011110..PWM0_A3_TRIG1 input is selected - * 0b011111..PWM1_A0_TRIG0 input is selected - * 0b100000..PWM1_A0_TRIG1 input is selected - * 0b100001..PWM1_A1_TRIG0 input is selected - * 0b100010..PWM1_A1_TRIG1 input is selected - * 0b100011..PWM1_A2_TRIG0 input is selected - * 0b100100..PWM1_A2_TRIG1 input is selected - * 0b100101..PWM1_A3_TRIG0 input is selected - * 0b100110..PWM1_A3_TRIG1 input is selected - * 0b100111..EVTG_OUT0A input is selected - * 0b101000..EVTG_OUT0B input is selected - * 0b101001..EVTG_OUT1A input is selected - * 0b101010..EVTG_OUT1B input is selected - * 0b101011..EVTG_OUT2A input is selected - * 0b101100..EVTG_OUT2B input is selected - * 0b101101..EVTG_OUT3A input is selected - * 0b101110..EVTG_OUT3B input is selected - * 0b101111..TRIG_IN0 input is selected - * 0b110000..TRIG_IN1 input is selected - * 0b110001..TRIG_IN2 input is selected - * 0b110010..TRIG_IN3 input is selected - * 0b110011..FlexIO CH4 input is selected - * 0b110100..FlexIO CH5 input is selected - * 0b110101..FlexIO CH6 input is selected - * 0b110110..FlexIO CH7 input is selected - * *.. - */ -#define INPUTMUX_OPAMP1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP1_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP1_TRIG_INP_MASK) -/*! @} */ - -/*! @name OPAMP2_TRIG - OPAMP2 Trigger Input Connections */ -/*! @{ */ - -#define INPUTMUX_OPAMP2_TRIG_INP_MASK (0x3FU) -#define INPUTMUX_OPAMP2_TRIG_INP_SHIFT (0U) -/*! INP - OPAMP trigger input connections - * 0b000000..PINT PIN_INT0 input is selected - * 0b000001..PINT PIN_INT1 input is selected - * 0b000010..PINT PIN_INT2 input is selected - * 0b000011..PINT PIN_INT3 input is selected - * 0b000100..SCT_OUT4 input is selected - * 0b000101..SCT_OUT5 input is selected - * 0b000110..SCT_OUT6 input is selected - * 0b000111..SCT_OUT7 input is selected - * 0b001000..SCT_OUT8 input is selected - * 0b001001..CTIMER0_MAT3 input is selected - * 0b001010..CTIMER1_MAT3 input is selected - * 0b001011..CTIMER2_MAT3 input is selected - * 0b001100..CTIMER3_MAT3 input is selected - * 0b001101..CTIMER4_MAT3 input is selected - * 0b001110..PINT GPIO_INT_BMAT input is selected - * 0b001111..ADC0_tcomp[0] input is selected - * 0b010000..ADC0_tcomp[1] input is selected - * 0b010001..ADC0_tcomp[2] input is selected - * 0b010010..ADC0_tcomp[3] input is selected - * 0b010011..ADC1_tcomp[0] input is selected - * 0b010100..ADC1_tcomp[1] input is selected - * 0b010101..ADC1_tcomp[2] input is selected - * 0b010110..ADC1_tcomp[3] input is selected - * 0b010111..PWM0_A0_TRIG0 input is selected - * 0b011000..PWM0_A0_TRIG1 input is selected - * 0b011001..PWM0_A1_TRIG0 input is selected - * 0b011010..PWM0_A1_TRIG1 input is selected - * 0b011011..PWM0_A2_TRIG0 input is selected - * 0b011100..PWM0_A2_TRIG1 input is selected - * 0b011101..PWM0_A3_TRIG0 input is selected - * 0b011110..PWM0_A3_TRIG1 input is selected - * 0b011111..PWM1_A0_TRIG0 input is selected - * 0b100000..PWM1_A0_TRIG1 input is selected - * 0b100001..PWM1_A1_TRIG0 input is selected - * 0b100010..PWM1_A1_TRIG1 input is selected - * 0b100011..PWM1_A2_TRIG0 input is selected - * 0b100100..PWM1_A2_TRIG1 input is selected - * 0b100101..PWM1_A3_TRIG0 input is selected - * 0b100110..PWM1_A3_TRIG1 input is selected - * 0b100111..EVTG_OUT0A input is selected - * 0b101000..EVTG_OUT0B input is selected - * 0b101001..EVTG_OUT1A input is selected - * 0b101010..EVTG_OUT1B input is selected - * 0b101011..EVTG_OUT2A input is selected - * 0b101100..EVTG_OUT2B input is selected - * 0b101101..EVTG_OUT3A input is selected - * 0b101110..EVTG_OUT3B input is selected - * 0b101111..TRIG_IN0 input is selected - * 0b110000..TRIG_IN1 input is selected - * 0b110001..TRIG_IN2 input is selected - * 0b110010..TRIG_IN3 input is selected - * 0b110011..FlexIO CH4 input is selected - * 0b110100..FlexIO CH5 input is selected - * 0b110101..FlexIO CH6 input is selected - * 0b110110..FlexIO CH7 input is selected - * *.. - */ -#define INPUTMUX_OPAMP2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP2_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP2_TRIG_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG */ +#define INPUTMUX_OPAMPN_TRIG_OPAMP_TRIG_COUNT (3U) /*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */ /*! @{ */ #define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM0 trigger input connections +/*! INP - LP_FLEXCOMM0 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT6 input is selected @@ -42222,7 +40035,7 @@ typedef struct { * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42262,7 +40075,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM1 trigger input connections +/*! INP - LP_FLEXCOMM1 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT6 input is selected @@ -42276,7 +40089,7 @@ typedef struct { * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42316,7 +40129,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM2 trigger input connections +/*! INP - LP_FLEXCOMM2 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT6 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42330,7 +40143,7 @@ typedef struct { * 0b001010..CTIMER4_MAT1 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42370,7 +40183,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM3 trigger input connections +/*! INP - LP_FLEXCOMM3 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42384,7 +40197,7 @@ typedef struct { * 0b001010..CTIMER4_MAT1 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42424,7 +40237,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM4 trigger input connections +/*! INP - LP_FLEXCOMM4 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42438,7 +40251,7 @@ typedef struct { * 0b001010..CTIMER4_MAT2 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42478,7 +40291,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM5 trigger input connections +/*! INP - LP_FLEXCOMM5 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42492,7 +40305,7 @@ typedef struct { * 0b001010..CTIMER4_MAT2 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42532,7 +40345,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM6 trigger input connections +/*! INP - LP_FLEXCOMM6 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42546,7 +40359,7 @@ typedef struct { * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42586,7 +40399,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT (0U) -/*! INP - FLEXCOMM7 trigger input connections +/*! INP - LP_FLEXCOMM7 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42600,7 +40413,7 @@ typedef struct { * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42640,7 +40453,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM8_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM8_TRIG_INP_SHIFT (0U) -/*! INP - Flexcomm8 trigger input connections +/*! INP - LP_FLEXCOMM8 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42654,7 +40467,7 @@ typedef struct { * 0b001010..CTIMER4_MAT3 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42694,7 +40507,7 @@ typedef struct { #define INPUTMUX_FLEXCOMM9_TRIG_INP_MASK (0x3FU) #define INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT (0U) -/*! INP - Flexcomm9 trigger input connections +/*! INP - LP_FLEXCOMM9 trigger input connections * 0b000000..PINT PIN_INT4 input is selected * 0b000001..PINT PIN_INT5 input is selected * 0b000010..PINT PIN_INT7 input is selected @@ -42708,7 +40521,7 @@ typedef struct { * 0b001010..CTIMER4_MAT0 input is selected * 0b001011..LPTMR0 input is selected * 0b001100..LPTMR1 input is selected - * 0b001101..ARM_TXEV input is selected + * 0b001101..Reserved * 0b001110..PINT GPIO_INT_BMAT input is selected * 0b001111..CMP0_OUT input is selected * 0b010000..CMP1_OUT input is selected @@ -42743,11 +40556,11 @@ typedef struct { #define INPUTMUX_FLEXCOMM9_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM9_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM9_TRIG_INP_MASK) /*! @} */ -/*! @name FLEXIO_TRIG0 - FlexIO Trigger Input Connections 0 */ +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ /*! @{ */ -#define INPUTMUX_FLEXIO_TRIG0_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG0_INP_SHIFT (0U) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) /*! INP - Input number for FlexIO0. * 0b0000000..PINT PIN_INT4 input is selected * 0b0000001..PINT PIN_INT5 input is selected @@ -42765,7 +40578,7 @@ typedef struct { * 0b0001101..T4_MAT1 input is selected * 0b0001110..LPTMR0 input is selected * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected + * 0b0010000..Reserved * 0b0010001..PINT GPIO_INT_BMAT input is selected * 0b0010010..ADC0_tcomp[0] input is selected * 0b0010011..ADC0_tcomp[1] input is selected @@ -42778,22 +40591,22 @@ typedef struct { * 0b0011010..CMP0_OUT input is selected * 0b0011011..CMP1_OUT input is selected * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected + * 0b0011101..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100011..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100100..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100110..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100111..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0101000..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101100..PWM1_SM3_MUX_TRIG1 input is selected * 0b0101101..EVTG_OUT0A input is selected * 0b0101110..EVTG_OUT0B input is selected * 0b0101111..EVTG_OUT1A input is selected @@ -42828,624 +40641,11 @@ typedef struct { * 0b1001100..WUU input is selected * *.. */ -#define INPUTMUX_FLEXIO_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG0_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG0_INP_MASK) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) /*! @} */ -/*! @name FLEXIO_TRIG1 - FlexIO Trigger Input Connections 1 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG1_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG1_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG1_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG1_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG2 - FlexIO Trigger Input Connections 2 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG2_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG2_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG2_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG2_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG3 - FlexIO Trigger Input Connections 3 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG3_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG3_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG3_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG3_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG4 - FlexIO Trigger Input Connections 4 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG4_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG4_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG4_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG4_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG5 - FlexIO Trigger Input Connections 5 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG5_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG5_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG5_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG5_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG5_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG6 - FlexIO Trigger Input Connections 6 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG6_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG6_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG6_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG6_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG6_INP_MASK) -/*! @} */ - -/*! @name FLEXIO_TRIG7 - FlexIO Trigger Input Connections 7 */ -/*! @{ */ - -#define INPUTMUX_FLEXIO_TRIG7_INP_MASK (0x7FU) -#define INPUTMUX_FLEXIO_TRIG7_INP_SHIFT (0U) -/*! INP - Input number for FlexIO0. - * 0b0000000..PINT PIN_INT4 input is selected - * 0b0000001..PINT PIN_INT5 input is selected - * 0b0000010..PINT PIN_INT6 input is selected - * 0b0000011..PINT PIN_INT7 input is selected - * 0b0000100..SCT_OUT5 input is selected - * 0b0000101..SCT_OUT6 input is selected - * 0b0000110..SCT_OUT7 input is selected - * 0b0000111..SCT_OUT8 input is selected - * 0b0001000..SCT_OUT9 input is selected - * 0b0001001..T0_MAT1 input is selected - * 0b0001010..T1_MAT1 input is selected - * 0b0001011..T2_MAT1 input is selected - * 0b0001100..T3_MAT1 input is selected - * 0b0001101..T4_MAT1 input is selected - * 0b0001110..LPTMR0 input is selected - * 0b0001111..LPTMR1 input is selected - * 0b0010000..ARM_TXEV input is selected - * 0b0010001..PINT GPIO_INT_BMAT input is selected - * 0b0010010..ADC0_tcomp[0] input is selected - * 0b0010011..ADC0_tcomp[1] input is selected - * 0b0010100..ADC0_tcomp[2] input is selected - * 0b0010101..ADC0_tcomp[3] input is selected - * 0b0010110..ADC1_tcomp[0] input is selected - * 0b0010111..ADC1_tcomp[1] input is selected - * 0b0011000..ADC1_tcomp[2] input is selected - * 0b0011001..ADC1_tcomp[3] input is selected - * 0b0011010..CMP0_OUT input is selected - * 0b0011011..CMP1_OUT input is selected - * 0b0011100..CMP2_OUT input is selected - * 0b0011101..PWM0_A0_TRIG0 input is selected - * 0b0011110..PWM0_A0_TRIG1 input is selected - * 0b0011111..PWM0_A1_TRIG0 input is selected - * 0b0100000..PWM0_A1_TRIG1 input is selected - * 0b0100001..PWM0_A2_TRIG0 input is selected - * 0b0100010..PWM0_A2_TRIG1 input is selected - * 0b0100011..PWM0_A3_TRIG0 input is selected - * 0b0100100..PWM0_A3_TRIG1 input is selected - * 0b0100101..PWM1_A0_TRIG0 input is selected - * 0b0100110..PWM1_A0_TRIG1 input is selected - * 0b0100111..PWM1_A1_TRIG0 input is selected - * 0b0101000..PWM1_A1_TRIG1 input is selected - * 0b0101001..PWM1_A2_TRIG0 input is selected - * 0b0101010..PWM1_A2_TRIG1 input is selected - * 0b0101011..PWM1_A3_TRIG0 input is selected - * 0b0101100..PWM1_A3_TRIG1 input is selected - * 0b0101101..EVTG_OUT0A input is selected - * 0b0101110..EVTG_OUT0B input is selected - * 0b0101111..EVTG_OUT1A input is selected - * 0b0110000..EVTG_OUT1B input is selected - * 0b0110001..EVTG_OUT2A input is selected - * 0b0110010..EVTG_OUT2B input is selected - * 0b0110011..EVTG_OUT3A input is selected - * 0b0110100..EVTG_OUT3B input is selected - * 0b0110101..TRIG_IN0 input is selected - * 0b0110110..TRIG_IN1 input is selected - * 0b0110111..TRIG_IN2 input is selected - * 0b0111000..TRIG_IN3 input is selected - * 0b0111001..TRIG_IN4 input is selected - * 0b0111010..SINC Filter CH0 Conversion Complete input is selected - * 0b0111011..SINC Filter CH1 Conversion Complete input is selected - * 0b0111100..SINC Filter CH2 Conversion Complete input is selected - * 0b0111101..SINC Filter CH3 Conversion Complete input is selected - * 0b0111110..SINC Filter CH4 Conversion Complete input is selected - * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected - * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected - * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected - * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected - * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected - * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected - * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected - * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected - * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected - * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected - * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected - * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected - * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected - * 0b1001100..WUU input is selected - * *.. - */ -#define INPUTMUX_FLEXIO_TRIG7_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIG7_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIG7_INP_MASK) -/*! @} */ +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (8U) /*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */ /*! @{ */ @@ -43468,7 +40668,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U) -/*! REQ3_EN0 - This register is used to enable and disable INT0 request. +/*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request. * 0b0..Disable * 0b1..Enable */ @@ -43476,7 +40676,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U) -/*! REQ4_EN0 - This register is used to enable and disable INT1 request. +/*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request. * 0b0..Disable * 0b1..Enable */ @@ -43484,7 +40684,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U) -/*! REQ5_EN0 - This register is used to enable and disable INT2 request. +/*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request. * 0b0..Disable * 0b1..Enable */ @@ -43492,7 +40692,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U) -/*! REQ6_EN0 - This register is used to enable and disable INT3 request. +/*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request. * 0b0..Disable * 0b1..Enable */ @@ -43500,7 +40700,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U) -/*! REQ7_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43508,7 +40708,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U) -/*! REQ8_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43516,7 +40716,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U) -/*! REQ9_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43524,7 +40724,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U) -/*! REQ10_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43532,7 +40732,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U) -/*! REQ11_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43540,7 +40740,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U) -/*! REQ12_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43548,7 +40748,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U) -/*! REQ13_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43556,7 +40756,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U) -/*! REQ14_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43564,7 +40764,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U) -/*! REQ15_EN0 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -43572,7 +40772,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U) -/*! REQ16_EN0 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -43580,7 +40780,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U) -/*! REQ17_EN0 - This register is used to enable and disable wake up event request. +/*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request. * 0b0..Disable * 0b1..Enable */ @@ -43588,7 +40788,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U) -/*! REQ18_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43596,7 +40796,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ19_EN0_SHIFT (19U) -/*! REQ19_EN0 - This register is used to enable and disable DMA0 request. +/*! REQ19_EN0 - This register is used to enable and disable SCT0 DMA0 request. * 0b0..Disable * 0b1..Enable */ @@ -43604,7 +40804,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ20_EN0_SHIFT (20U) -/*! REQ20_EN0 - This register is used to enable and disable DMA1 request. +/*! REQ20_EN0 - This register is used to enable and disable SCT0 DMA1 request. * 0b0..Disable * 0b1..Enable */ @@ -43612,7 +40812,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U) -/*! REQ21_EN0 - This register is used to enable and disable FIFO A request. +/*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -43620,7 +40820,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U) -/*! REQ22_EN0 - This register is used to enable and disable FIFO B request. +/*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -43628,7 +40828,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U) -/*! REQ23_EN0 - This register is used to enable and disable FIFO A request. +/*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -43636,7 +40836,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U) -/*! REQ24_EN0 - This register is used to enable and disable FIFO B request. +/*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -43644,7 +40844,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ25_EN0_SHIFT (25U) -/*! REQ25_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ25_EN0 - This register is used to enable and disable DAC0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43652,7 +40852,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ26_EN0_SHIFT (26U) -/*! REQ26_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ26_EN0 - This register is used to enable and disable DAC1 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43660,7 +40860,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ27_EN0_SHIFT (27U) -/*! REQ27_EN0 - This register is used to enable and disable FIFO_request. +/*! REQ27_EN0 - This register is used to enable and disable DAC2 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -43668,7 +40868,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U) -/*! REQ28_EN0 - This register is used to enable and disable DMA_request. +/*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -43676,7 +40876,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U) -/*! REQ29_EN0 - This register is used to enable and disable DMA_request. +/*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -43684,7 +40884,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ30_EN0_SHIFT (30U) -/*! REQ30_EN0 - This register is used to enable and disable DMA_request. +/*! REQ30_EN0 - This register is used to enable and disable CMP2 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -43692,7 +40892,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U) -/*! REQ31_EN0 - This register is used to enable and disable OUT0A request. +/*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request. * 0b0..Disable * 0b1..Enable */ @@ -44181,7 +41381,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U) -/*! REQ32_EN0 - This register is used to enable and disable OUT0B request. +/*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request. * 0b0..Disable * 0b1..Enable */ @@ -44189,7 +41389,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U) -/*! REQ33_EN0 - This register is used to enable and disable OUT1A request. +/*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request. * 0b0..Disable * 0b1..Enable */ @@ -44197,7 +41397,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U) -/*! REQ34_EN0 - This register is used to enable and disable OUT1B request. +/*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request. * 0b0..Disable * 0b1..Enable */ @@ -44205,7 +41405,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U) -/*! REQ35_EN0 - This register is used to enable and disable OUT2A request. +/*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request. * 0b0..Disable * 0b1..Enable */ @@ -44213,7 +41413,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U) -/*! REQ36_EN0 - This register is used to enable and disable OUT2B request. +/*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request. * 0b0..Disable * 0b1..Enable */ @@ -44221,7 +41421,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U) -/*! REQ37_EN0 - This register is used to enable and disable OUT3A request. +/*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request. * 0b0..Disable * 0b1..Enable */ @@ -44229,7 +41429,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U) -/*! REQ38_EN0 - This register is used to enable and disable OUT3B request. +/*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request. * 0b0..Disable * 0b1..Enable */ @@ -44237,7 +41437,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U) -/*! REQ39_EN0 - This register is used to enable and disable Req_capt0 request. +/*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -44245,7 +41445,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U) -/*! REQ40_EN0 - This register is used to enable and disable Req_capt1 request. +/*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -44253,7 +41453,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U) -/*! REQ41_EN0 - This register is used to enable and disable Req_capt2 request. +/*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -44261,7 +41461,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U) -/*! REQ42_EN0 - This register is used to enable and disable Req_capt3 request. +/*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -44269,7 +41469,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U) -/*! REQ43_EN0 - This register is used to enable and disable Req_val0 request. +/*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -44277,7 +41477,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U) -/*! REQ44_EN0 - This register is used to enable and disable Req_val1 request. +/*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -44285,7 +41485,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U) -/*! REQ45_EN0 - This register is used to enable and disable Req_val2 request. +/*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -44293,7 +41493,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U) -/*! REQ46_EN0 - This register is used to enable and disable Req_val3 request. +/*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -44301,7 +41501,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U) -/*! REQ47_EN0 - This register is used to enable and disable Req_capt0 request. +/*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -44309,7 +41509,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U) -/*! REQ48_EN0 - This register is used to enable and disable Req_capt1 request. +/*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -44317,7 +41517,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U) -/*! REQ49_EN0 - This register is used to enable and disable Req_capt2 request. +/*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -44325,7 +41525,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U) -/*! REQ50_EN0 - This register is used to enable and disable Req_capt3 request. +/*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -44333,7 +41533,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U) -/*! REQ51_EN0 - This register is used to enable and disable Req_val0 request. +/*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -44341,7 +41541,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U) -/*! REQ52_EN0 - This register is used to enable and disable Req_val1 request. +/*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -44349,7 +41549,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U) -/*! REQ53_EN0 - This register is used to enable and disable Req_val2 request. +/*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -44357,7 +41557,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U) -/*! REQ54_EN0 - This register is used to enable and disable Req_val3 request. +/*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -44365,7 +41565,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U) -/*! REQ57_EN0 - This register is used to enable and disable counter match event request. +/*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -44373,7 +41573,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U) -/*! REQ58_EN0 - This register is used to enable and disable counter match event request. +/*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -44381,7 +41581,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U) -/*! REQ59_EN0 - This register is used to enable and disable DMA request. +/*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44389,7 +41589,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U) -/*! REQ60_EN0 - This register is used to enable and disable DMA request. +/*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44397,7 +41597,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U) -/*! REQ61_EN0 - This register is used to enable and disable shift register 0 request. +/*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44405,7 +41605,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U) -/*! REQ62_EN0 - This register is used to enable and disable shift register 1 request. +/*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44413,7 +41613,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U) -/*! REQ63_EN0 - This register is used to enable and disable shift register 2 request. +/*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -44538,16 +41738,6 @@ typedef struct { /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_MASK (0x800000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_SHIFT (23U) -/*! REQ55_EN0 - Writing a 1 to REQ55_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ55_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_SHIFT (24U) -/*! REQ56_EN0 - Writing a 1 to REQ56_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ56_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ @@ -44702,16 +41892,6 @@ typedef struct { /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_MASK (0x800000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_SHIFT (23U) -/*! REQ55_EN0 - Writing a 1 to REQ55_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ55_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_SHIFT (24U) -/*! REQ56_EN0 - Writing a 1 to REQ56_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ56_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ @@ -44866,16 +42046,6 @@ typedef struct { /*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_MASK (0x800000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_SHIFT (23U) -/*! REQ55_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ55_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_MASK (0x1000000U) -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_SHIFT (24U) -/*! REQ56_EN0 - Writing a 1 to REQ56_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ -#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ56_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U) /*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ @@ -44917,7 +42087,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U) -/*! REQ64_EN0 - This register is used to enable and disable shift register 3 request. +/*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request. * 0b0..Disable * 0b1..Enable */ @@ -44925,7 +42095,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U) -/*! REQ65_EN0 - This register is used to enable and disable shift register 4 request. +/*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request. * 0b0..Disable * 0b1..Enable */ @@ -44933,7 +42103,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U) -/*! REQ66_EN0 - This register is used to enable and disable shift register 5 request. +/*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request. * 0b0..Disable * 0b1..Enable */ @@ -44941,7 +42111,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U) -/*! REQ67_EN0 - This register is used to enable and disable shift register 6 request. +/*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request. * 0b0..Disable * 0b1..Enable */ @@ -44949,7 +42119,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U) -/*! REQ68_EN0 - This register is used to enable and disable shift register 7 request. +/*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request. * 0b0..Disable * 0b1..Enable */ @@ -44957,7 +42127,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U) -/*! REQ69_EN0 - This register is used to enable and disable receive request. +/*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -44965,7 +42135,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U) -/*! REQ70_EN0 - This register is used to enable and disable transmit request. +/*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -44973,7 +42143,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U) -/*! REQ71_EN0 - This register is used to enable and disable receive request. +/*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -44981,7 +42151,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U) -/*! REQ72_EN0 - This register is used to enable and disable transmit request. +/*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -44989,7 +42159,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U) -/*! REQ73_EN0 - This register is used to enable and disable receive request. +/*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request. * 0b0..Disable * 0b1..Enable */ @@ -44997,7 +42167,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U) -/*! REQ74_EN0 - This register is used to enable and disable transmit request. +/*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45005,7 +42175,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U) -/*! REQ75_EN0 - This register is used to enable and disable receive request. +/*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45013,7 +42183,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U) -/*! REQ76_EN0 - This register is used to enable and disable transmit request. +/*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45021,7 +42191,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U) -/*! REQ77_EN0 - This register is used to enable and disable receive request. +/*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45029,7 +42199,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U) -/*! REQ78_EN0 - This register is used to enable and disable transmit request. +/*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45037,7 +42207,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U) -/*! REQ79_EN0 - This register is used to enable and disable receive request. +/*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45045,7 +42215,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U) -/*! REQ80_EN0 - This register is used to enable and disable transmit request. +/*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45053,7 +42223,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U) -/*! REQ81_EN0 - This register is used to enable and disable receive request. +/*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45061,7 +42231,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U) -/*! REQ82_EN0 - This register is used to enable and disable transmit request. +/*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45069,7 +42239,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U) -/*! REQ83_EN0 - This register is used to enable and disable receive request. +/*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45077,7 +42247,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U) -/*! REQ84_EN0 - This register is used to enable and disable transmit request. +/*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45085,7 +42255,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ85_EN0_SHIFT (21U) -/*! REQ85_EN0 - This register is used to enable and disable receive request. +/*! REQ85_EN0 - This register is used to enable and disable LP_FLEXCOMM8 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45093,7 +42263,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ86_EN0_SHIFT (22U) -/*! REQ86_EN0 - This register is used to enable and disable transmit request. +/*! REQ86_EN0 - This register is used to enable and disable LP_FLEXCOMM8 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45101,7 +42271,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ87_EN0_SHIFT (23U) -/*! REQ87_EN0 - This register is used to enable and disable receive request. +/*! REQ87_EN0 - This register is used to enable and disable LP_FLEXCOMM9 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45109,31 +42279,15 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT (24U) -/*! REQ88_EN0 - This register is used to enable and disable transmit request. +/*! REQ88_EN0 - This register is used to enable and disable LP_FLEXCOMM9 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - This register is used to enable and disable channel 0 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - This register is used to enable and disable channel 1 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ91_EN0_SHIFT (27U) -/*! REQ91_EN0 - This register is used to enable and disable receive request. +/*! REQ91_EN0 - This register is used to enable and disable EMVSIM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45141,7 +42295,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_MASK (0x10000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ92_EN0_SHIFT (28U) -/*! REQ92_EN0 - This register is used to enable and disable transmit request. +/*! REQ92_EN0 - This register is used to enable and disable EMVSIM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45149,7 +42303,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_MASK (0x20000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ93_EN0_SHIFT (29U) -/*! REQ93_EN0 - This register is used to enable and disable receive request. +/*! REQ93_EN0 - This register is used to enable and disable EMVSIM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45157,7 +42311,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_MASK (0x40000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ94_EN0_SHIFT (30U) -/*! REQ94_EN0 - This register is used to enable and disable transmit request. +/*! REQ94_EN0 - This register is used to enable and disable EMVSIM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45165,7 +42319,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U) -/*! REQ95_EN0 - This register is used to enable and disable receive request. +/*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45300,16 +42454,6 @@ typedef struct { /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - Writing a 1 to REQ89_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - Writing a 1 to REQ90_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ @@ -45464,16 +42608,6 @@ typedef struct { /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - Writing a 1 to REQ89_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - Writing a 1 to REQ90_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ @@ -45628,16 +42762,6 @@ typedef struct { /*! REQ88_EN0 - Writing a 1 to REQ88_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ88_EN0_MASK) -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_MASK (0x2000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_SHIFT (25U) -/*! REQ89_EN0 - Writing a 1 to REQ89_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ89_EN0_MASK) - -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_MASK (0x4000000U) -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_SHIFT (26U) -/*! REQ90_EN0 - Writing a 1 to REQ90_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ -#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ90_EN0_MASK) - #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_MASK (0x8000000U) #define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ91_EN0_SHIFT (27U) /*! REQ91_EN0 - Writing a 1 to REQ91_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ @@ -45669,7 +42793,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U) -/*! REQ96_EN0 - This register is used to enable and disable transmit request. +/*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45677,7 +42801,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U) -/*! REQ97_EN0 - This register is used to enable and disable shift register 4 request. +/*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45685,7 +42809,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U) -/*! REQ98_EN0 - This register is used to enable and disable transmit request. +/*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45693,7 +42817,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U) -/*! REQ99_EN0 - This register is used to enable and disable shift register 6 request. +/*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45701,7 +42825,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U) -/*! REQ100_EN0 - This register is used to enable and disable transmit request. +/*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45709,7 +42833,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U) -/*! REQ101_EN0 - This register is used to enable and disable receive request. +/*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -45717,7 +42841,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U) -/*! REQ102_EN0 - This register is used to enable and disable transmit request. +/*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -45725,7 +42849,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_MASK (0x80U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ103_EN0_SHIFT (7U) -/*! REQ103_EN0 - This register is used to enable and disable ipd_req_sinc[0] or ipd_req_alt [0] request. +/*! REQ103_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request. * 0b0..Disable * 0b1..Enable */ @@ -45733,7 +42857,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_MASK (0x100U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ104_EN0_SHIFT (8U) -/*! REQ104_EN0 - This register is used to enable and disable ipd_req_sinc[1] or ipd_req_alt [1] request. +/*! REQ104_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request. * 0b0..Disable * 0b1..Enable */ @@ -45741,7 +42865,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_MASK (0x200U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ105_EN0_SHIFT (9U) -/*! REQ105_EN0 - This register is used to enable and disable ipd_req_sinc[2] or ipd_req_alt [2] request. +/*! REQ105_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request. * 0b0..Disable * 0b1..Enable */ @@ -45749,7 +42873,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_MASK (0x400U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ106_EN0_SHIFT (10U) -/*! REQ106_EN0 - This register is used to enable and disable ipd_req_sinc[3] or ipd_req_alt [3] request. +/*! REQ106_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request. * 0b0..Disable * 0b1..Enable */ @@ -45757,7 +42881,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_MASK (0x800U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ107_EN0_SHIFT (11U) -/*! REQ107_EN0 - This register is used to enable and disable ipd_req_sinc[4] or ipd_req_alt [4] request. +/*! REQ107_EN0 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request. * 0b0..Disable * 0b1..Enable */ @@ -45765,7 +42889,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U) -/*! REQ108_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45773,7 +42897,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U) -/*! REQ109_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45781,7 +42905,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U) -/*! REQ110_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45789,7 +42913,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U) -/*! REQ111_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45797,7 +42921,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U) -/*! REQ112_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45805,7 +42929,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U) -/*! REQ113_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45813,7 +42937,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U) -/*! REQ114_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45821,7 +42945,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U) -/*! REQ115_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45829,7 +42953,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U) -/*! REQ116_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45837,7 +42961,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U) -/*! REQ117_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45845,7 +42969,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U) -/*! REQ118_EN0 - This register is used to enable and disable pin event request 0. +/*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -45853,7 +42977,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U) -/*! REQ119_EN0 - This register is used to enable and disable pin event request 1. +/*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -45861,7 +42985,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_MASK (0x1000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ120_EN0_SHIFT (24U) -/*! REQ120_EN0 - This register is used to enable and disable end of scan request. +/*! REQ120_EN0 - This register is used to enable and disable TSI0 end of scan request. * 0b0..Disable * 0b1..Enable */ @@ -45869,7 +42993,7 @@ typedef struct { #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_MASK (0x2000000U) #define INPUTMUX_DMA0_REQ_ENABLE3_REQ121_EN0_SHIFT (25U) -/*! REQ121_EN0 - This register is used to enable and disable out of range request. +/*! REQ121_EN0 - This register is used to enable and disable TSI0 out of range request. * 0b0..Disable * 0b1..Enable */ @@ -46165,7 +43289,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U) -/*! REQ3_EN1 - This register is used to enable and disable INT0 request. +/*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request. * 0b0..Disable * 0b1..Enable */ @@ -46173,7 +43297,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U) -/*! REQ4_EN1 - This register is used to enable and disable INT1 request. +/*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request. * 0b0..Disable * 0b1..Enable */ @@ -46181,7 +43305,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U) -/*! REQ5_EN1 - This register is used to enable and disable INT2 request. +/*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request. * 0b0..Disable * 0b1..Enable */ @@ -46189,7 +43313,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U) -/*! REQ6_EN1 - This register is used to enable and disable INT3 request. +/*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request. * 0b0..Disable * 0b1..Enable */ @@ -46197,7 +43321,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U) -/*! REQ7_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46205,7 +43329,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U) -/*! REQ8_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46213,7 +43337,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U) -/*! REQ9_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46221,7 +43345,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U) -/*! REQ10_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46229,7 +43353,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U) -/*! REQ11_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46237,7 +43361,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U) -/*! REQ12_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46245,7 +43369,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U) -/*! REQ13_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46253,7 +43377,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U) -/*! REQ14_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46261,7 +43385,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U) -/*! REQ15_EN1 - This register is used to enable and disable DMAREQ_M0 request. +/*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. * 0b0..Disable * 0b1..Enable */ @@ -46269,7 +43393,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U) -/*! REQ16_EN1 - This register is used to enable and disable DMAREQ_M1 request. +/*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. * 0b0..Disable * 0b1..Enable */ @@ -46277,7 +43401,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U) -/*! REQ17_EN1 - This register is used to enable and disable wake up event request. +/*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request. * 0b0..Disable * 0b1..Enable */ @@ -46285,7 +43409,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U) -/*! REQ18_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46293,7 +43417,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ19_EN1_SHIFT (19U) -/*! REQ19_EN1 - This register is used to enable and disable DMA0 request. +/*! REQ19_EN1 - This register is used to enable and disable SCT0 DMA0 request. * 0b0..Disable * 0b1..Enable */ @@ -46301,7 +43425,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ20_EN1_SHIFT (20U) -/*! REQ20_EN1 - This register is used to enable and disable DMA1 request. +/*! REQ20_EN1 - This register is used to enable and disable SCT0 DMA1 request. * 0b0..Disable * 0b1..Enable */ @@ -46309,7 +43433,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U) -/*! REQ21_EN1 - This register is used to enable and disable FIFO A request. +/*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -46317,7 +43441,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U) -/*! REQ22_EN1 - This register is used to enable and disable FIFO B request. +/*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -46325,7 +43449,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U) -/*! REQ23_EN1 - This register is used to enable and disable FIFO A request. +/*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request. * 0b0..Disable * 0b1..Enable */ @@ -46333,7 +43457,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U) -/*! REQ24_EN1 - This register is used to enable and disable FIFO B request. +/*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request. * 0b0..Disable * 0b1..Enable */ @@ -46341,7 +43465,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ25_EN1_SHIFT (25U) -/*! REQ25_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ25_EN1 - This register is used to enable and disable DAC0 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46349,7 +43473,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ26_EN1_SHIFT (26U) -/*! REQ26_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ26_EN1 - This register is used to enable and disable DAC1 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46357,7 +43481,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ27_EN1_SHIFT (27U) -/*! REQ27_EN1 - This register is used to enable and disable FIFO_request. +/*! REQ27_EN1 - This register is used to enable and disable DAC2 FIFO_request. * 0b0..Disable * 0b1..Enable */ @@ -46365,7 +43489,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U) -/*! REQ28_EN1 - This register is used to enable and disable DMA_request. +/*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -46373,7 +43497,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U) -/*! REQ29_EN1 - This register is used to enable and disable DMA_request. +/*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -46381,7 +43505,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ30_EN1_SHIFT (30U) -/*! REQ30_EN1 - This register is used to enable and disable DMA_request. +/*! REQ30_EN1 - This register is used to enable and disable CMP2 DMA_request. * 0b0..Disable * 0b1..Enable */ @@ -46389,7 +43513,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U) -/*! REQ31_EN1 - This register is used to enable and disable OUT0A request. +/*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request. * 0b0..Disable * 0b1..Enable */ @@ -46878,7 +44002,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U) -/*! REQ32_EN1 - This register is used to enable and disable OUT0B request. +/*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request. * 0b0..Disable * 0b1..Enable */ @@ -46886,7 +44010,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U) -/*! REQ33_EN1 - This register is used to enable and disable OUT1A request. +/*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request. * 0b0..Disable * 0b1..Enable */ @@ -46894,7 +44018,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U) -/*! REQ34_EN1 - This register is used to enable and disable OUT1B request. +/*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request. * 0b0..Disable * 0b1..Enable */ @@ -46902,7 +44026,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U) -/*! REQ35_EN1 - This register is used to enable and disable OUT2A request. +/*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request. * 0b0..Disable * 0b1..Enable */ @@ -46910,7 +44034,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U) -/*! REQ36_EN1 - This register is used to enable and disable OUT2B request. +/*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request. * 0b0..Disable * 0b1..Enable */ @@ -46918,7 +44042,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U) -/*! REQ37_EN1 - This register is used to enable and disable OUT3A request. +/*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request. * 0b0..Disable * 0b1..Enable */ @@ -46926,7 +44050,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U) -/*! REQ38_EN1 - This register is used to enable and disable OUT3B request. +/*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request. * 0b0..Disable * 0b1..Enable */ @@ -46934,7 +44058,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U) -/*! REQ39_EN1 - This register is used to enable and disable Req_capt0 request. +/*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -46942,7 +44066,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U) -/*! REQ40_EN1 - This register is used to enable and disable Req_capt1 request. +/*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -46950,7 +44074,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U) -/*! REQ41_EN1 - This register is used to enable and disable Req_capt2 request. +/*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -46958,7 +44082,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U) -/*! REQ42_EN1 - This register is used to enable and disable Req_capt3 request. +/*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -46966,7 +44090,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U) -/*! REQ43_EN1 - This register is used to enable and disable Req_val0 request. +/*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -46974,7 +44098,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U) -/*! REQ44_EN1 - This register is used to enable and disable Req_val1 request. +/*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -46982,7 +44106,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U) -/*! REQ45_EN1 - This register is used to enable and disable Req_val2 request. +/*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -46990,7 +44114,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U) -/*! REQ46_EN1 - This register is used to enable and disable Req_val3 request. +/*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -46998,7 +44122,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U) -/*! REQ47_EN1 - This register is used to enable and disable Req_capt0 request. +/*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request. * 0b0..Disable * 0b1..Enable */ @@ -47006,7 +44130,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U) -/*! REQ48_EN1 - This register is used to enable and disable Req_capt1 request. +/*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request. * 0b0..Disable * 0b1..Enable */ @@ -47014,7 +44138,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U) -/*! REQ49_EN1 - This register is used to enable and disable Req_capt2 request. +/*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request. * 0b0..Disable * 0b1..Enable */ @@ -47022,7 +44146,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U) -/*! REQ50_EN1 - This register is used to enable and disable Req_capt3 request. +/*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request. * 0b0..Disable * 0b1..Enable */ @@ -47030,7 +44154,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U) -/*! REQ51_EN1 - This register is used to enable and disable Req_val0 request. +/*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request. * 0b0..Disable * 0b1..Enable */ @@ -47038,7 +44162,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U) -/*! REQ52_EN1 - This register is used to enable and disable Req_val1 request. +/*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request. * 0b0..Disable * 0b1..Enable */ @@ -47046,7 +44170,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U) -/*! REQ53_EN1 - This register is used to enable and disable Req_val2 request. +/*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request. * 0b0..Disable * 0b1..Enable */ @@ -47054,7 +44178,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U) -/*! REQ54_EN1 - This register is used to enable and disable Req_val3 request. +/*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request. * 0b0..Disable * 0b1..Enable */ @@ -47062,7 +44186,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U) -/*! REQ57_EN1 - This register is used to enable and disable counter match event request. +/*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -47070,7 +44194,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U) -/*! REQ58_EN1 - This register is used to enable and disable counter match event request. +/*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request. * 0b0..Disable * 0b1..Enable */ @@ -47078,7 +44202,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U) -/*! REQ59_EN1 - This register is used to enable and disable DMA request. +/*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47086,7 +44210,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U) -/*! REQ60_EN1 - This register is used to enable and disable DMA request. +/*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47094,7 +44218,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U) -/*! REQ61_EN1 - This register is used to enable and disable shift register 0 request. +/*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47102,7 +44226,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U) -/*! REQ62_EN1 - This register is used to enable and disable shift register 1 request. +/*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47110,7 +44234,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U) -/*! REQ63_EN1 - This register is used to enable and disable shift register 2 request. +/*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47235,16 +44359,6 @@ typedef struct { /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_MASK (0x800000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_SHIFT (23U) -/*! REQ55_EN1 - Writing a 1 to REQ55_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ55_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_MASK (0x1000000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_SHIFT (24U) -/*! REQ56_EN1 - Writing a 1 to REQ56_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ56_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ @@ -47399,16 +44513,6 @@ typedef struct { /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_MASK (0x800000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_SHIFT (23U) -/*! REQ55_EN1 - Writing a 1 to REQ55_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ55_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_MASK (0x1000000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_SHIFT (24U) -/*! REQ56_EN1 - Writing a 1 to REQ56_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ56_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ @@ -47563,16 +44667,6 @@ typedef struct { /*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_MASK (0x800000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_SHIFT (23U) -/*! REQ55_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ55_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_MASK (0x1000000U) -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_SHIFT (24U) -/*! REQ56_EN1 - Writing a 1 to REQ56_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ -#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ56_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U) /*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ @@ -47614,7 +44708,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U) -/*! REQ64_EN1 - This register is used to enable and disable shift register 3 request. +/*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47622,7 +44716,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U) -/*! REQ65_EN1 - This register is used to enable and disable shift register 4 request. +/*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47630,7 +44724,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U) -/*! REQ66_EN1 - This register is used to enable and disable shift register 5 request. +/*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47638,7 +44732,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U) -/*! REQ67_EN1 - This register is used to enable and disable shift register 6 request. +/*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47646,7 +44740,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U) -/*! REQ68_EN1 - This register is used to enable and disable shift register 7 request. +/*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request. * 0b0..Disable * 0b1..Enable */ @@ -47654,7 +44748,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U) -/*! REQ69_EN1 - This register is used to enable and disable receive request. +/*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47662,7 +44756,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U) -/*! REQ70_EN1 - This register is used to enable and disable transmit request. +/*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47670,7 +44764,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U) -/*! REQ71_EN1 - This register is used to enable and disable receive request. +/*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47678,7 +44772,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U) -/*! REQ72_EN1 - This register is used to enable and disable transmit request. +/*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47686,7 +44780,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U) -/*! REQ73_EN1 - This register is used to enable and disable receive request. +/*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47694,7 +44788,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U) -/*! REQ74_EN1 - This register is used to enable and disable transmit request. +/*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47702,7 +44796,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U) -/*! REQ75_EN1 - This register is used to enable and disable receive request. +/*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47710,7 +44804,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U) -/*! REQ76_EN1 - This register is used to enable and disable transmit request. +/*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47718,7 +44812,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U) -/*! REQ77_EN1 - This register is used to enable and disable receive request. +/*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47726,7 +44820,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U) -/*! REQ78_EN1 - This register is used to enable and disable transmit request. +/*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47734,7 +44828,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U) -/*! REQ79_EN1 - This register is used to enable and disable receive request. +/*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47742,7 +44836,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U) -/*! REQ80_EN1 - This register is used to enable and disable transmit request. +/*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47750,7 +44844,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U) -/*! REQ81_EN1 - This register is used to enable and disable receive request. +/*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47758,7 +44852,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U) -/*! REQ82_EN1 - This register is used to enable and disable transmit request. +/*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47766,7 +44860,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U) -/*! REQ83_EN1 - This register is used to enable and disable receive request. +/*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47774,7 +44868,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U) -/*! REQ84_EN1 - This register is used to enable and disable transmit request. +/*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47782,7 +44876,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ85_EN1_SHIFT (21U) -/*! REQ85_EN1 - This register is used to enable and disable receive request. +/*! REQ85_EN1 - This register is used to enable and disable LP_FLEXCOMM8 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47790,7 +44884,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ86_EN1_SHIFT (22U) -/*! REQ86_EN1 - This register is used to enable and disable transmit request. +/*! REQ86_EN1 - This register is used to enable and disable LP_FLEXCOMM8 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47798,7 +44892,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ87_EN1_SHIFT (23U) -/*! REQ87_EN1 - This register is used to enable and disable receive request. +/*! REQ87_EN1 - This register is used to enable and disable LP_FLEXCOMM9 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47806,31 +44900,15 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT (24U) -/*! REQ88_EN1 - This register is used to enable and disable transmit request. +/*! REQ88_EN1 - This register is used to enable and disable LP_FLEXCOMM9 transmit request. * 0b0..Disable * 0b1..Enable */ #define INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ88_EN1_MASK) -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_MASK (0x2000000U) -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_SHIFT (25U) -/*! REQ89_EN1 - This register is used to enable and disable channel 0 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ89_EN1_MASK) - -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_MASK (0x4000000U) -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_SHIFT (26U) -/*! REQ90_EN1 - This register is used to enable and disable channel 1 request. - * 0b0..Disable - * 0b1..Enable - */ -#define INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ90_EN1_MASK) - #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_MASK (0x8000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ91_EN1_SHIFT (27U) -/*! REQ91_EN1 - This register is used to enable and disable receive request. +/*! REQ91_EN1 - This register is used to enable and disable EMVSIM0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47838,7 +44916,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_MASK (0x10000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ92_EN1_SHIFT (28U) -/*! REQ92_EN1 - This register is used to enable and disable transmit request. +/*! REQ92_EN1 - This register is used to enable and disable EMVSIM0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47846,7 +44924,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_MASK (0x20000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ93_EN1_SHIFT (29U) -/*! REQ93_EN1 - This register is used to enable and disable receive request. +/*! REQ93_EN1 - This register is used to enable and disable EMVSIM1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -47854,7 +44932,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_MASK (0x40000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ94_EN1_SHIFT (30U) -/*! REQ94_EN1 - This register is used to enable and disable transmit request. +/*! REQ94_EN1 - This register is used to enable and disable EMVSIM1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -47862,7 +44940,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U) #define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U) -/*! REQ95_EN1 - This register is used to enable and disable receive request. +/*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48366,7 +45444,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) -/*! REQ96_EN1 - This register is used to enable and disable transmit request. +/*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48374,7 +45452,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U) -/*! REQ97_EN1 - This register is used to enable and disable shift register 4 request. +/*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48382,7 +45460,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U) -/*! REQ98_EN1 - This register is used to enable and disable transmit request. +/*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48390,7 +45468,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U) -/*! REQ99_EN1 - This register is used to enable and disable shift register 6 request. +/*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48398,7 +45476,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U) -/*! REQ100_EN1 - This register is used to enable and disable transmit request. +/*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48406,7 +45484,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U) -/*! REQ101_EN1 - This register is used to enable and disable receive request. +/*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request. * 0b0..Disable * 0b1..Enable */ @@ -48414,7 +45492,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U) -/*! REQ102_EN1 - This register is used to enable and disable transmit request. +/*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request. * 0b0..Disable * 0b1..Enable */ @@ -48422,7 +45500,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_MASK (0x80U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ103_EN1_SHIFT (7U) -/*! REQ103_EN1 - This register is used to enable and disable ipd_req_sinc[0] or ipd_req_alt [0] request. +/*! REQ103_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[0] or ipd_req_alt [0] request. * 0b0..Disable * 0b1..Enable */ @@ -48430,7 +45508,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_MASK (0x100U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ104_EN1_SHIFT (8U) -/*! REQ104_EN1 - This register is used to enable and disable ipd_req_sinc[1] or ipd_req_alt [1] request. +/*! REQ104_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[1] or ipd_req_alt [1] request. * 0b0..Disable * 0b1..Enable */ @@ -48438,7 +45516,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_MASK (0x200U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ105_EN1_SHIFT (9U) -/*! REQ105_EN1 - This register is used to enable and disable ipd_req_sinc[2] or ipd_req_alt [2] request. +/*! REQ105_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[2] or ipd_req_alt [2] request. * 0b0..Disable * 0b1..Enable */ @@ -48446,7 +45524,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_MASK (0x400U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ106_EN1_SHIFT (10U) -/*! REQ106_EN1 - This register is used to enable and disable ipd_req_sinc[3] or ipd_req_alt [3] request. +/*! REQ106_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[3] or ipd_req_alt [3] request. * 0b0..Disable * 0b1..Enable */ @@ -48454,7 +45532,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_MASK (0x800U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ107_EN1_SHIFT (11U) -/*! REQ107_EN1 - This register is used to enable and disable ipd_req_sinc[4] or ipd_req_alt [4] request. +/*! REQ107_EN1 - This register is used to enable and disable SINC0 ipd_req_sinc[4] or ipd_req_alt [4] request. * 0b0..Disable * 0b1..Enable */ @@ -48462,7 +45540,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U) -/*! REQ108_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48470,7 +45548,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U) -/*! REQ109_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48478,7 +45556,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U) -/*! REQ110_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48486,7 +45564,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U) -/*! REQ111_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48494,7 +45572,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U) -/*! REQ112_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48502,7 +45580,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U) -/*! REQ113_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48510,7 +45588,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U) -/*! REQ114_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48518,7 +45596,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U) -/*! REQ115_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48526,7 +45604,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U) -/*! REQ116_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48534,7 +45612,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U) -/*! REQ117_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48542,7 +45620,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U) -/*! REQ118_EN1 - This register is used to enable and disable pin event request 0. +/*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0. * 0b0..Disable * 0b1..Enable */ @@ -48550,7 +45628,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U) -/*! REQ119_EN1 - This register is used to enable and disable pin event request 1. +/*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1. * 0b0..Disable * 0b1..Enable */ @@ -48558,7 +45636,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_MASK (0x1000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ120_EN1_SHIFT (24U) -/*! REQ120_EN1 - This register is used to enable and disable end of scan request. +/*! REQ120_EN1 - This register is used to enable and disable TSI0 end of scan request. * 0b0..Disable * 0b1..Enable */ @@ -48566,7 +45644,7 @@ typedef struct { #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_MASK (0x2000000U) #define INPUTMUX_DMA1_REQ_ENABLE3_REQ121_EN1_SHIFT (25U) -/*! REQ121_EN1 - This register is used to enable and disable out of range request. +/*! REQ121_EN1 - This register is used to enable and disable TSI0 out of range request. * 0b0..Disable * 0b1..Enable */ @@ -49087,7 +46165,7 @@ typedef struct { #define ITRC_STATUS_IN3_STATUS_MASK (0x8U) #define ITRC_STATUS_IN3_STATUS_SHIFT (3U) -/*! IN3_STATUS - VDD_MAIN volt tamper output. +/*! IN3_STATUS - VBAT volt tamper output. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ @@ -49283,7 +46361,7 @@ typedef struct { #define ITRC_STATUS1_IN20_STATUS_MASK (0x10U) #define ITRC_STATUS1_IN20_STATUS_SHIFT (4U) -/*! IN20_STATUS - VDD_MAIN clock tamper output event occurred. +/*! IN20_STATUS - VBAT clock tamper output event occurred. * 0b0..Output not triggered. * 0b1..Output has been triggered. */ @@ -49382,7 +46460,7 @@ typedef struct { #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U) -/*! IN3_SELn - Selects VDD_MAIN voltage tamper event as a trigger source. */ +/*! IN3_SELn - Selects VBAT voltage tamper event as a trigger source. */ #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK) #define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U) @@ -49472,12 +46550,12 @@ typedef struct { #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U) -/*! IN19_SELn - Selects VDD_MAIN temperature tamper output event as a trigger source. */ +/*! IN19_SELn - Selects VBAT temperature tamper output event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U) -/*! IN20_SELn - Selects VDD_MAIN clock tamper output event as a trigger source. */ +/*! IN20_SELn - Selects VBAT clock tamper output event as a trigger source. */ #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) #define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U) @@ -49731,15 +46809,15 @@ typedef struct { #define LPCMP_CCR0_CMP_EN_MASK (0x1U) #define LPCMP_CCR0_CMP_EN_SHIFT (0U) /*! CMP_EN - Comparator Enable - * 0b0..Disables (The analog logic remains off and consumes no power.) - * 0b1..Enables + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable */ #define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) #define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) #define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) /*! CMP_STOP_EN - Comparator Deep sleep Mode Enable - * 0b0..Disable the analog comparator regardless of CMP_EN. + * 0b0..Disables the analog comparator regardless of CMP_EN. * 0b1..Allows CMP_EN to enable the analog comparator. */ #define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) @@ -49751,24 +46829,24 @@ typedef struct { #define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) #define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) /*! WINDOW_EN - Windowing Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) #define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) #define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) /*! SAMPLE_EN - Sampling Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) #define LPCMP_CCR1_DMA_EN_MASK (0x4U) #define LPCMP_CCR1_DMA_EN_SHIFT (2U) /*! DMA_EN - DMA Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) @@ -49889,10 +46967,10 @@ typedef struct { #define LPCMP_CCR2_HYSTCTR_MASK (0x30U) #define LPCMP_CCR2_HYSTCTR_SHIFT (4U) /*! HYSTCTR - Comparator Hysteresis Control - * 0b00..Level 0 - * 0b01..Level 1 - * 0b10..Level 2 - * 0b11..Level 3 + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. */ #define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) @@ -49931,24 +47009,24 @@ typedef struct { #define LPCMP_DCR_DAC_EN_MASK (0x1U) #define LPCMP_DCR_DAC_EN_SHIFT (0U) /*! DAC_EN - DAC Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) #define LPCMP_DCR_DAC_HPMD_MASK (0x2U) #define LPCMP_DCR_DAC_HPMD_SHIFT (1U) -/*! DAC_HPMD - DAC High Power Mode Select - * 0b0..Disables - * 0b1..Enables +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable */ #define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) #define LPCMP_DCR_VRSEL_MASK (0x100U) #define LPCMP_DCR_VRSEL_SHIFT (8U) /*! VRSEL - DAC Reference High Voltage Source Select - * 0b0..vrefh0 - * 0b1..vrefh1 + * 0b0..VREFH0 + * 0b1..VREFH1 */ #define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) @@ -50025,8 +47103,8 @@ typedef struct { #define LPCMP_RRCR0_RR_EN_MASK (0x1U) #define LPCMP_RRCR0_RR_EN_SHIFT (0U) /*! RR_EN - Round-Robin Enable - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) @@ -50040,7 +47118,7 @@ typedef struct { #define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU) #define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U) -/*! RR_EXTTRG_SEL - Select the External Trigger Source +/*! RR_EXTTRG_SEL - External Trigger Source Select * 0b0000..Select external trigger source 0 * 0b0001..Select external trigger source 1 * 0b0010..Select external trigger source 2 @@ -50139,64 +47217,64 @@ typedef struct { #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) #define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) /*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) #define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) #define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) /*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) #define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) #define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) /*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) #define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) #define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) /*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) #define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) #define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) /*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) #define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) #define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) /*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) #define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) #define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) /*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) #define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) #define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) /*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode - * 0b1..Enables - * 0b0..Disables + * 0b1..Enable + * 0b0..Disable */ #define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) @@ -50273,7 +47351,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH0F_MASK (0x1U) #define LPCMP_RRSR_RR_CH0F_SHIFT (0U) /*! RR_CH0F - Channel 0 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) @@ -50281,7 +47359,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH1F_MASK (0x2U) #define LPCMP_RRSR_RR_CH1F_SHIFT (1U) /*! RR_CH1F - Channel 1 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) @@ -50289,7 +47367,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH2F_MASK (0x4U) #define LPCMP_RRSR_RR_CH2F_SHIFT (2U) /*! RR_CH2F - Channel 2 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) @@ -50297,7 +47375,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH3F_MASK (0x8U) #define LPCMP_RRSR_RR_CH3F_SHIFT (3U) /*! RR_CH3F - Channel 3 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) @@ -50305,7 +47383,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH4F_MASK (0x10U) #define LPCMP_RRSR_RR_CH4F_SHIFT (4U) /*! RR_CH4F - Channel 4 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) @@ -50313,7 +47391,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH5F_MASK (0x20U) #define LPCMP_RRSR_RR_CH5F_SHIFT (5U) /*! RR_CH5F - Channel 5 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) @@ -50321,7 +47399,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH6F_MASK (0x40U) #define LPCMP_RRSR_RR_CH6F_SHIFT (6U) /*! RR_CH6F - Channel 6 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) @@ -50329,7 +47407,7 @@ typedef struct { #define LPCMP_RRSR_RR_CH7F_MASK (0x80U) #define LPCMP_RRSR_RR_CH7F_SHIFT (7U) /*! RR_CH7F - Channel 7 Input Changed Flag - * 0b0..Not different + * 0b0..No different * 0b1..Different */ #define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) @@ -50512,9 +47590,9 @@ typedef struct { #define LPDAC_GCR_DACRFS_MASK (0x6U) #define LPDAC_GCR_DACRFS_SHIFT (1U) /*! DACRFS - DAC Reference Select - * 0b00..Selects VREFH0 as the reference voltage - * 0b01..Selects VREFH1 as the reference voltage - * 0b10..Selects VREFH2 as the reference voltage + * 0b00..Selects VREFH0 as the reference voltage. + * 0b01..Selects VREFH1 as the reference voltage. + * 0b10..Selects VREFH2 as the reference voltage. * 0b11..Reserved. */ #define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) @@ -50522,7 +47600,7 @@ typedef struct { #define LPDAC_GCR_FIFOEN_MASK (0x8U) #define LPDAC_GCR_FIFOEN_SHIFT (3U) /*! FIFOEN - FIFO Enable - * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to goes to buffer then goes to conversion. + * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. */ #define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) @@ -50891,7 +47969,7 @@ typedef struct { uint8_t RESERVED_7[148]; __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ - __IO uint32_t SIER; /**< Target interrupt enable, offset: 0x118 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ @@ -50963,32 +48041,32 @@ typedef struct { #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Controller Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset - * 0b0..Not reset + * 0b0..No effect * 0b1..Reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) -/*! DOZEN - Doze mode enable - * 0b0..Controller is enabled in doze mode - * 0b1..Controller is disabled in doze mode +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable - * 0b0..Controller is disabled in debug mode - * 0b1..Controller is enabled in debug mode + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) @@ -50996,7 +48074,7 @@ typedef struct { #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect - * 0b1..Transmit FIFO is reset + * 0b1..Reset transmit FIFO */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) @@ -51004,7 +48082,7 @@ typedef struct { #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect - * 0b1..Receive FIFO is reset + * 0b1..Reset receive FIFO */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ @@ -51015,80 +48093,96 @@ typedef struct { #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag - * 0b0..Transmit data is not requested - * 0b1..Transmit data is requested + * 0b0..Transmit data not requested + * 0b1..Transmit data requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag - * 0b0..Receive data is not ready - * 0b1..Receive data is ready + * 0b0..Receive data not ready + * 0b1..Receive data ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag - * 0b0..Controller has not generated a STOP or Repeated START condition - * 0b1..Controller has generated a STOP or Repeated START condition + * 0b0..No Stop or repeated Start generated + * 0b1..Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) -/*! SDF - STOP Detect Flag - * 0b0..Controller has not generated a STOP condition - * 0b1..Controller has generated a STOP condition +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b1..Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag - * 0b0..Unexpected NACK was not detected - * 0b1..Unexpected NACK was detected + * 0b0..No unexpected NACK detected + * 0b1..Unexpected NACK detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag - * 0b0..Controller has not lost arbitration - * 0b1..Controller has lost arbitration + * 0b0..Controller did not lose arbitration + * 0b1..Controller lost arbitration + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag - * 0b0..No error - * 0b1..Controller sending or receiving data without a START condition + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag - * 0b0..Pin low timeout has not occurred or is disabled - * 0b1..Pin low timeout has occurred + * 0b0..Pin low timeout did not occur + * 0b1..Pin low timeout occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag - * 0b0..Have not received matching data - * 0b1..Have received matching data + * 0b0..Matching data not received + * 0b1..Matching data received + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_STF_MASK (0x8000U) #define LPI2C_MSR_STF_SHIFT (15U) -/*! STF - START Flag - * 0b0..START condition not detected. - * 0b1..START condition detected. +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b1..Start condition detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) @@ -51115,80 +48209,80 @@ typedef struct { #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) -/*! SDIE - STOP Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) #define LPI2C_MIER_STIE_MASK (0x8000U) #define LPI2C_MIER_STIE_SHIFT (15U) -/*! STIE - START Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) /*! @} */ @@ -51199,16 +48293,16 @@ typedef struct { #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ @@ -51218,15 +48312,15 @@ typedef struct { #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) -/*! HREN - Host request enable - * 0b0..Host request input is disabled - * 0b1..Host request input is enabled +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host request polarity +/*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ @@ -51234,7 +48328,7 @@ typedef struct { #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host request select +/*! HRSEL - Host Request Select * 0b0..Host request input is pin HREQ * 0b1..Host request input is input trigger */ @@ -51242,7 +48336,7 @@ typedef struct { #define LPI2C_MCFGR0_HRDIR_MASK (0x8U) #define LPI2C_MCFGR0_HRDIR_SHIFT (3U) -/*! HRDIR - Host request direction +/*! HRDIR - Host Request Direction * 0b0..HREQ pin is input (for LPI2C controller) * 0b1..HREQ pin is output (for LPI2C target) */ @@ -51250,17 +48344,17 @@ typedef struct { #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) -/*! CIRFIFO - Circular FIFO enable - * 0b0..Circular FIFO is disabled - * 0b1..Circular FIFO is enabled +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) -/*! RDMO - Receive data match only +/*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO - * 0b1..Received data is discarded unless the Data Match Flag (MSR[DMF]) is 1. + * 0b1..Received data is discarded unless MSR[DMF] is set */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) @@ -51276,7 +48370,7 @@ typedef struct { #define LPI2C_MCFGR0_ABORT_SHIFT (17U) /*! ABORT - Abort Transfer * 0b0..Normal transfer - * 0b1..Abort existing transfer and do not start new transfer + * 0b1..Abort existing transfer and do not start a new one */ #define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) /*! @} */ @@ -51300,9 +48394,9 @@ typedef struct { #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) -/*! AUTOSTOP - Automatic STOP Generation +/*! AUTOSTOP - Automatic Stop Generation * 0b0..No effect - * 0b1..STOP condition is automatically generated when the transmit FIFO is empty and the LPI2C controller is busy + * 0b1..Stop automatically generated */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) @@ -51310,34 +48404,31 @@ typedef struct { #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - Ignore NACK * 0b0..No effect - * 0b1..LPI2C controller treats a received NACK as if it (NACK) was an ACK and the NACK Detect Flag is never written 1. + * 0b1..Treat a received NACK as an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration - * 0b0..MSR[PLTF] becomes 1 if SCL is low for longer than the configured timeout. - * 0b1..MSR[PLTF] becomes 1 if either SCL or SDA is low for longer than the configured timeout. + * 0b0..SCL + * 0b1..SCL or SDA */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) #define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) -/*! STOPCFG - STOP Configuration - * 0b0..MSR[SDF] asserts on any STOP condition generated by LPI2C controller. - * 0b1..MSR[SDF] asserts on last STOP condition before LPI2C controller is idle (that is, the transmit FIFO is - * empty at the time of the STOP condition). +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition */ #define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) #define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) #define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) -/*! STARTCFG - START Configuration - * 0b0..MSR[STF] asserts on START condition provided both I2C bus and LPI2C controller are idle (that is, any - * non-repeated START condition initiated by any other controller on the bus but not the LPI2C controller). - * 0b1..MSR[STF] asserts on START condition provided I2C bus is idle (that is, any non-repeated START condition - * initiated by any controller on the bus including the LPI2C controller). +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle */ #define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) @@ -51346,12 +48437,12 @@ typedef struct { /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved - * 0b010..Match is enabled (first data word equals MDMR[MATCH0] OR MDMR[MATCH1]) - * 0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) - * 0b100..Match is enabled (first data word equals MDMR[MATCH0] AND second data word equals MDMR[MATCH1) - * 0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) - * 0b110..Match is enabled (first data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) - * 0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) @@ -51359,11 +48450,11 @@ typedef struct { #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..Two-pin open drain mode - * 0b001..Two-pin output only mode (ultra-fast mode) + * 0b001..Two-pin output only mode (Ultra-Fast mode) * 0b010..Two-pin push-pull mode * 0b011..Four-pin push-pull mode - * 0b100..Two-pin open drain mode with separate LPI2C target - * 0b101..Two-pin output only mode (ultra-fast mode) with separate LPI2C target + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target * 0b110..Two-pin push-pull mode with separate LPI2C target * 0b111..Four-pin push-pull mode (inverted outputs) */ @@ -51394,7 +48485,7 @@ typedef struct { #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) -/*! PINLOW - Pin low timeout */ +/*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ @@ -51499,14 +48590,14 @@ typedef struct { #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data - * 0b000..Transmit DATA[7:0] + * 0b000..Transmit the value in DATA[7:0] * 0b001..Receive (DATA[7:0] + 1) bytes - * 0b010..Generate STOP condition + * 0b010..Generate Stop condition on I2C bus * 0b011..Receive and discard (DATA[7:0] + 1) bytes - * 0b100..Generate (repeated) START and transmit address in DATA[7:0] - * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. - * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode - * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode. This transfer expects a NACK to be returned. + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ @@ -51522,8 +48613,8 @@ typedef struct { #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty - * 0b0..Receive FIFO is not empty - * 0b1..Receive FIFO is empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ @@ -51539,8 +48630,8 @@ typedef struct { #define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty - * 0b0..Receive FIFO is not empty - * 0b1..Receive FIFO is empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) /*! @} */ @@ -51551,40 +48642,40 @@ typedef struct { #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Target Enable - * 0b0..I2C Target mode is disabled - * 0b1..I2C Target mode is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) -/*! RST - Software reset - * 0b0..Target mode logic is not reset - * 0b1..Target mode logic is reset +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) -/*! FILTEN - Filter enable - * 0b0..Disable digital filter and output delay counter for target mode - * 0b1..Enable digital filter and output delay counter for target mode +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) -/*! FILTDZ - Filter doze enable - * 0b0..Filter remains enabled in Doze mode - * 0b1..Filter is disabled in Doze mode +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) -/*! RTF - Reset transmit FIFO +/*! RTF - Reset Transmit FIFO * 0b0..No effect - * 0b1..Transmit Data Register is now empty. + * 0b1..STDR is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) @@ -51592,7 +48683,7 @@ typedef struct { #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect - * 0b1..Receive Data Register is now empty. + * 0b1..SRDR is now empty */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ @@ -51602,7 +48693,7 @@ typedef struct { #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) -/*! TDF - Transmit data flag +/*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ @@ -51610,63 +48701,71 @@ typedef struct { #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) -/*! RDF - Receive data flag - * 0b0..Receive data is not ready - * 0b1..Receive data is ready +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) -/*! AVF - Address valid flag - * 0b0..Address Status Register is not valid - * 0b1..Address Status Register is valid +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) -/*! TAF - Transmit ACK flag - * 0b0..Transmit ACK/NACK is not required - * 0b1..Transmit ACK/NACK is required +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) -/*! RSF - Repeated start flag - * 0b0..Target has not detected a Repeated START condition - * 0b1..Target has detected a Repeated START condition +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b1..Repeated Start detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) -/*! SDF - STOP detect flag - * 0b0..Target has not detected a STOP condition - * 0b1..Target has detected a STOP condition +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b1..Stop detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) -/*! BEF - Bit error flag - * 0b0..Target has not detected a bit error - * 0b1..Target has detected a bit error +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b1..Bit error occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) -/*! FEF - FIFO error flag - * 0b0..FIFO underflow or overflow was not detected - * 0b1..FIFO underflow or overflow was detected +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) -/*! AM0F - Address match 0 flag +/*! AM0F - Address Match 0 Flag * 0b0..ADDR0 matching address not received * 0b1..ADDR0 matching address received */ @@ -51674,31 +48773,31 @@ typedef struct { #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) -/*! AM1F - Address match 1 flag - * 0b0..ADDR1 or ADDR0/ADDR1 range matching address not received - * 0b1..ADDR1 or ADDR0/ADDR1 range matching address received +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) -/*! GCF - General call flag - * 0b0..Target has not detected the General Call Address or the General Call Address is disabled - * 0b1..Target has detected the General Call Address +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) -/*! SARF - SMBus alert response flag - * 0b0..SMBus alert response is disabled or not detected - * 0b1..SMBus alert response is enabled and detected +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) -/*! SBF - Target busy flag +/*! SBF - Target Busy Flag * 0b0..Idle * 0b1..Busy */ @@ -51706,99 +48805,99 @@ typedef struct { #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) -/*! BBF - Bus busy flag +/*! BBF - Bus Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ -/*! @name SIER - Target interrupt enable */ +/*! @name SIER - Target Interrupt Enable */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) -/*! TDIE - Transmit data interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) -/*! RDIE - Receive data interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) -/*! AVIE - Address valid interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) -/*! TAIE - Transmit ACK interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) -/*! RSIE - Repeated start interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) -/*! SDIE - STOP detect interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) -/*! BEIE - Bit error interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) -/*! FEIE - FIFO error interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) -/*! AM0IE - Address match 0 interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1IE_MASK (0x2000U) #define LPI2C_SIER_AM1IE_SHIFT (13U) -/*! AM1IE - Address match 1 interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) -/*! GCIE - General call interrupt enable +/*! GCIE - General Call Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ @@ -51806,9 +48905,9 @@ typedef struct { #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) -/*! SARIE - SMBus alert response interrupt enable - * 0b0..Disabled - * 0b1..Enabled +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ @@ -51818,41 +48917,41 @@ typedef struct { #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) -/*! TDDE - Transmit data DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) -/*! RDDE - Receive data DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) -/*! AVDE - Address valid DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) #define LPI2C_SDER_RSDE_MASK (0x100U) #define LPI2C_SDER_RSDE_SHIFT (8U) -/*! RSDE - Repeated start DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) #define LPI2C_SDER_SDDE_MASK (0x200U) #define LPI2C_SDER_SDDE_SHIFT (9U) -/*! SDDE - Stop detect DMA enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) /*! @} */ @@ -51863,14 +48962,14 @@ typedef struct { #define LPI2C_SCFGR0_RDREQ_MASK (0x1U) #define LPI2C_SCFGR0_RDREQ_SHIFT (0U) /*! RDREQ - Read Request - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) #define LPI2C_SCFGR0_RDACK_MASK (0x2U) #define LPI2C_SCFGR0_RDACK_SHIFT (1U) -/*! RDACK - Read Acknowledge +/*! RDACK - Read Acknowledge Flag * 0b0..Read Request not acknowledged * 0b1..Read Request acknowledged */ @@ -51882,89 +48981,87 @@ typedef struct { #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) -/*! ADRSTALL - Address SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) -/*! RXSTALL - RX SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) -/*! TXDSTALL - Transmit data SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) -/*! ACKSTALL - ACK SCL stall - * 0b0..Disabled - * 0b1..Enabled +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_RXNACK_MASK (0x10U) #define LPI2C_SCFGR1_RXNACK_SHIFT (4U) /*! RXNACK - Receive NACK - * 0b0..ACK/NACK always written 1 by TXNACK - * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK/NACK is written 1 by TXNACK. + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] */ #define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) -/*! GCEN - General call enable - * 0b0..General Call address is disabled - * 0b1..General Call address is enabled +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) -/*! SAEN - SMBus alert enable - * 0b0..Disables match on SMBus Alert - * 0b1..Enables match on SMBus Alert +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) -/*! TXCFG - Transmit flag configuration - * 0b0..MSR[TDF] becomes 1 only during a target-transmit transfer when the Transmit Data register is empty - * 0b1..MSR[TDF] becomes 1 whenever the Transmit Data register is empty +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration - * 0b0..Reading the Receive Data register returns received data and writes 0 to the Receive Data flag. - * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is 1, returns the Address Status - * register and writes 0 to SSR[AVF]. Reading the Receive Data register when SSR[AVF] is 0, returns received - * data and writes 0 to the Receive Data flag (MSR[RDF]). + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK - * 0b0..Target ends transfer when NACK is detected - * 0b1..Target does not end transfer when NACK detected + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) -/*! HSMEN - High-speed mode enable +/*! HSMEN - HS Mode Enable * 0b0..Disable * 0b1..Enable */ @@ -51972,39 +49069,39 @@ typedef struct { #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) -/*! ADDRCFG - Address configuration +/*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit) * 0b001..Address match 0 (10-bit) - * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) - * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) - * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) - * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) - * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) - * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) #define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) #define LPI2C_SCFGR1_RXALL_SHIFT (24U) -/*! RXALL - Receive all - * 0b0..Receive all disabled - * 0b1..Receive all enabled +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable */ #define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) #define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) #define LPI2C_SCFGR1_RSCFG_SHIFT (25U) -/*! RSCFG - Repeated start configuration - * 0b0..Any repeated START condition following an address match - * 0b1..Any repeated START condition +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition */ #define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) #define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) #define LPI2C_SCFGR1_SDCFG_SHIFT (26U) /*! SDCFG - Stop Detect Configuration - * 0b0..Any STOP condition following an address match - * 0b1..Any STOP condition + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition */ #define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) /*! @} */ @@ -52014,22 +49111,22 @@ typedef struct { #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) -/*! CLKHOLD - Clock hold time */ +/*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) -/*! DATAVD - Data valid delay */ +/*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) -/*! FILTSCL - Glitch filter SCL */ +/*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) -/*! FILTSDA - Glitch filter SDA */ +/*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ @@ -52038,12 +49135,12 @@ typedef struct { #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) -/*! ADDR0 - Address 0 value */ +/*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) -/*! ADDR1 - Address 1 value */ +/*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ @@ -52057,9 +49154,9 @@ typedef struct { #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) -/*! ANV - Address not valid - * 0b0..Received Address (RADDR) is valid - * 0b1..Received Address (RADDR) is not valid +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ @@ -52070,8 +49167,8 @@ typedef struct { #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK - * 0b0..Write a Transmit ACK for each received word - * 0b1..Write a Transmit NACK for each received word + * 0b0..Transmit ACK + * 0b1..Transmit NACK */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ @@ -52081,7 +49178,7 @@ typedef struct { #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) -/*! DATA - Transmit data */ +/*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ @@ -52090,27 +49187,27 @@ typedef struct { #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) -/*! DATA - Receive data */ +/*! DATA - Received Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RADDR_MASK (0x700U) #define LPI2C_SRDR_RADDR_SHIFT (8U) -/*! RADDR - Received address */ +/*! RADDR - Received Address */ #define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - Receive empty - * 0b0..The Receive Data Register is not empty - * 0b1..The Receive Data Register is empty +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) -/*! SOF - Start of frame - * 0b0..Not the first data word since a (repeated) START or STOP condition - * 0b1..Is the first data word since a (repeated) START or STOP condition +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ @@ -52120,27 +49217,27 @@ typedef struct { #define LPI2C_SRDROR_DATA_MASK (0xFFU) #define LPI2C_SRDROR_DATA_SHIFT (0U) -/*! DATA - Receive data */ +/*! DATA - Receive Data */ #define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) #define LPI2C_SRDROR_RADDR_MASK (0x700U) #define LPI2C_SRDROR_RADDR_SHIFT (8U) -/*! RADDR - Received address */ +/*! RADDR - Received Address */ #define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) #define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - Receive empty - * 0b0..The Receive Data Register is not empty - * 0b1..The Receive Data Register is empty +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty */ #define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) #define LPI2C_SRDROR_SOF_MASK (0x8000U) #define LPI2C_SRDROR_SOF_SHIFT (15U) -/*! SOF - Start of frame - * 0b0..Is not the first data word since a (repeated) START or STOP condition - * 0b1..Is the first data word since a (repeated) START or STOP condition +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First */ #define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) /*! @} */ @@ -52481,7 +49578,7 @@ typedef struct { #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested - * 0b1..Transmit data is requested + * 0b1..Transmit data requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) @@ -52489,7 +49586,7 @@ typedef struct { #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data not ready - * 0b1..Receive data is ready + * 0b1..Receive data ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) @@ -52498,6 +49595,8 @@ typedef struct { /*! WCF - Word Complete Flag * 0b0..Not complete * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) @@ -52506,6 +49605,8 @@ typedef struct { /*! FCF - Frame Complete Flag * 0b0..Not complete * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) @@ -52514,6 +49615,8 @@ typedef struct { /*! TCF - Transfer Complete Flag * 0b0..Not complete * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) @@ -52522,6 +49625,8 @@ typedef struct { /*! TEF - Transmit Error Flag * 0b0..No underrun * 0b1..Underrun + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) @@ -52530,6 +49635,8 @@ typedef struct { /*! REF - Receive Error Flag * 0b0..No overflow * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) @@ -52538,6 +49645,8 @@ typedef struct { /*! DMF - Data Match Flag * 0b0..No match * 0b1..Match + * 0b0..No effect + * 0b1..Clear the flag */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) @@ -52743,7 +49852,10 @@ typedef struct { #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) -/*! PCSPOL - Peripheral Chip Select Polarity */ +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) @@ -52763,26 +49875,26 @@ typedef struct { #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration - * 0b00..SIN is used for input data; SOUT is used for output data. - * 0b01..SIN is used for both input and output data. Only half-duplex serial transfers are supported. - * 0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are supported. - * 0b11..SOUT is used for input data; SIN is used for output data. + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration - * 0b0..Output data retains last value. - * 0b1..Output data is 3-stated. + * 0b0..Retain last value + * 0b1..3-stated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration - * 0b0..PCS[3:2] are configured for chip select function - * 0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ @@ -52844,7 +49956,7 @@ typedef struct { #define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) #define LPSPI_CCR1_PCSPCS_SHIFT (16U) -/*! PCSPCS - PCS to PCS delay */ +/*! PCSPCS - PCS to PCS Delay */ #define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) #define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) @@ -52911,7 +50023,7 @@ typedef struct { #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer - * 0b1..Receive data is masked + * 0b1..Mask receive data */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) @@ -52926,24 +50038,24 @@ typedef struct { #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer - * 0b0..Continuous transfer is disabled - * 0b1..Continuous transfer is enabled + * 0b0..Disable + * 0b1..Enable */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable byte swap + * 0b1..Enable byte swap */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First - * 0b0..Data is transferred MSB first - * 0b1..Data is transferred LSB first + * 0b0..MSB first + * 0b1..LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) @@ -53002,7 +50114,7 @@ typedef struct { #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) -/*! SOF - Start Of Frame +/*! SOF - Start of Frame * 0b0..Subsequent data word * 0b1..First data word */ @@ -53230,7 +50342,7 @@ typedef struct { /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ - __IO uint32_t PSR; /**< Prescale and Glitch Filter, offset: 0x4 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ __IO uint32_t CMR; /**< Compare, offset: 0x8 */ __IO uint32_t CNR; /**< Counter, offset: 0xC */ } LPTMR_Type; @@ -53258,15 +50370,15 @@ typedef struct { #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) /*! TMS - Timer Mode Select - * 0b0..Time Counter mode - * 0b1..Pulse Counter mode + * 0b0..Time Counter + * 0b1..Pulse Counter */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) /*! TFC - Timer Free-Running Counter - * 0b0..Reset if TCF set + * 0b0..Reset when TCF asserts * 0b1..Reset on overflow */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) @@ -53302,6 +50414,8 @@ typedef struct { /*! TCF - Timer Compare Flag * 0b0..CNR != (CMR + 1) * 0b1..CNR = (CMR + 1) + * 0b0..No effect + * 0b1..Clear the flag */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) @@ -53314,12 +50428,12 @@ typedef struct { #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) /*! @} */ -/*! @name PSR - Prescale and Glitch Filter */ +/*! @name PSR - Prescaler and Glitch Filter */ /*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) -/*! PCS - Prescaler/Glitch Filter Clock Select +/*! PCS - Prescaler and Glitch Filter Clock Select * 0b00..Clock 0 * 0b01..Clock 1 * 0b10..Clock 2 @@ -53329,31 +50443,31 @@ typedef struct { #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) -/*! PBYP - Prescaler/Glitch Filter Bypass - * 0b0..Prescaler/glitch filter enable - * 0b1..Prescaler/glitch filter bypass +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) -/*! PRESCALE - Prescale/Glitch Filter Value - * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. - * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. - * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. - * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. - * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. - * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. - * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. - * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. - * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. - * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. - * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. - * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. - * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. - * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. - * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. - * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @} */ @@ -53560,72 +50674,72 @@ typedef struct { #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable - * 0b0..Disables hardware interrupts from STAT[RXEDGIF] - * 0b1..Requests hardware interrupts when STAT[RXEDGIF] is 1 + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable - * 0b0..Disables hardware interrupts from STAT[LBKDIF] (uses polling) - * 0b1..Requests hardware interrupt when STAT[LBKDIF] is 1 + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable - * 0b0..Enables resynchronization - * 0b1..Disables resynchronization + * 0b0..Enable + * 0b1..Disable */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling - * 0b0..Receiver samples input data using the rising edge of the baud rate clock - * 0b1..Receiver samples input data using the rising and falling edges of the baud rate clock + * 0b0..Rising edge + * 0b1..Both rising and falling edges */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration - * 0b00..Address match wakeup - * 0b01..Idle match wakeup + * 0b00..Address match wake-up + * 0b01..Idle match wake-up * 0b10..Match on and match off - * 0b11..Enables RWU on data match and match on/off for the transmitter CTS input + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable - * 0b0..DMA request disabled - * 0b1..DMA request enabled + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable - * 0b0..Disables DMA request - * 0b1..Enables DMA request + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable - * 0b0..Disables DMA request - * 0b1..Enables DMA request + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) -/*! OSR - Oversampling Ratio (OSR) +/*! OSR - Oversampling Ratio * 0b00000..Results in an OSR of 16 * 0b00001..Reserved * 0b00010..Reserved @@ -53672,16 +50786,16 @@ typedef struct { #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ @@ -53692,16 +50806,16 @@ typedef struct { #define LPUART_STAT_LBKFE_MASK (0x1U) #define LPUART_STAT_LBKFE_SHIFT (0U) /*! LBKFE - LIN Break Flag Enable - * 0b0..Disables LIN break detect - * 0b1..Enables LIN break detect + * 0b0..Disable + * 0b1..Enable */ #define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) #define LPUART_STAT_AME_MASK (0x2U) #define LPUART_STAT_AME_SHIFT (1U) /*! AME - Address Mark Enable - * 0b0..Address mark in character is MSB - * 0b1..Address mark in character is the last bit before the stop bit (or parity bit when enabled) + * 0b0..Disable + * 0b1..Enable */ #define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) @@ -53726,6 +50840,8 @@ typedef struct { /*! MA2F - Match 2 Flag * 0b0..Not equal to MA2 * 0b1..Equal to MA2 + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) @@ -53734,30 +50850,38 @@ typedef struct { /*! MA1F - Match 1 Flag * 0b0..Not equal to MA1 * 0b1..Equal to MA1 + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) -/*! PF - Parity Error Flag (PF) +/*! PF - Parity Error Flag * 0b0..No parity error detected * 0b1..Parity error detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) -/*! FE - Framing Error Flag (FE) +/*! FE - Framing Error Flag * 0b0..No framing error detected (this does not guarantee that the framing is correct) * 0b1..Framing error detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) -/*! NF - Noise Flag (NF) +/*! NF - Noise Flag * 0b0..No noise detected * 0b1..Noise detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) @@ -53765,15 +50889,19 @@ typedef struct { #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun - * 0b1..Receive overrun (new LPUART data lost) + * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag - * 0b0..No idle line detected - * 0b1..Idle line detected + * 0b0..Idle line detected + * 0b1..Idle line not detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) @@ -53788,8 +50916,8 @@ typedef struct { #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag - * 0b0..Transmitter active (sending data, a preamble, or a break) - * 0b1..Transmitter idle (transmission activity complete) + * 0b0..Transmitter active + * 0b1..Transmitter idle */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) @@ -53812,8 +50940,8 @@ typedef struct { #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) @@ -53854,6 +50982,8 @@ typedef struct { /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag * 0b0..Not occurred * 0b1..Occurred + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) @@ -53862,6 +50992,8 @@ typedef struct { /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..Not detected * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ @@ -53880,8 +51012,8 @@ typedef struct { #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) @@ -53895,17 +51027,17 @@ typedef struct { #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) -/*! WAKE - Receiver Wakeup Method Select - * 0b0..Configures CTRL[RWU] for idle-line wakeup - * 0b1..Configures CTRL[RWU] with address-mark wakeup +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit Or 8-Bit Mode Select - * 0b0..8-bit data characters - * 0b1..9-bit data characters + * 0b0..8-bit + * 0b1..9-bit */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) @@ -53919,9 +51051,9 @@ typedef struct { #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) -/*! DOZEEN - Enables LPUART in Doze mode. - * 0b0..Enables - * 0b1..Disables +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) @@ -53950,24 +51082,24 @@ typedef struct { #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select - * 0b0..8-bit to 10-bit data characters - * 0b1..7-bit data characters + * 0b0..8-bit to 10-bit + * 0b1..7-bit */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 (MA2F) Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 (MA1F) Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) @@ -53981,89 +51113,89 @@ typedef struct { #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) -/*! RWU - Receiver Wakeup Control +/*! RWU - Receiver Wake-Up Control * 0b0..Normal receiver operation - * 0b1..LPUART receiver in standby, waiting for a wakeup condition + * 0b1..LPUART receiver in standby, waiting for a wake-up condition */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable - * 0b0..Disables hardware interrupts from STAT[IDLE]; use polling - * 0b1..Enables hardware interrupts when STAT[IDLE] = 1 + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) @@ -54078,8 +51210,8 @@ typedef struct { #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode - * 0b0..TXD pin is an input in Single-Wire mode - * 0b1..TXD pin is an output in Single-Wire mode + * 0b0..Input + * 0b1..Output */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) @@ -54099,75 +51231,75 @@ typedef struct { #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) -/*! R0T0 - Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0 */ +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) -/*! R1T1 - Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1 */ +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) -/*! R2T2 - Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2 */ +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) -/*! R3T3 - Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3 */ +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) -/*! R4T4 - Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4 */ +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) -/*! R5T5 - Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5 */ +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) -/*! R6T6 - Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6 */ +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) -/*! R7T7 - Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7 */ +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) -/*! R8T8 - Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8 */ +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) -/*! R9T9 - Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9 */ +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_LINBRK_MASK (0x400U) #define LPUART_DATA_LINBRK_SHIFT (10U) /*! LINBRK - LIN Break - * 0b0..LIN break not detected or LIN break detect circuitry disabled - * 0b1..LIN break detected + * 0b0..Not detected + * 0b1..Detected */ #define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line - * 0b0..Received was not idle - * 0b1..Receiver was idle + * 0b0..Not idle + * 0b1..Idle */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty - * 0b0..Contains valid data - * 0b1..Contains invalid data and is empty + * 0b0..Valid data + * 0b1..Invalid data and empty */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) @@ -54216,32 +51348,32 @@ typedef struct { #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter CTS Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter RTS Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter RTS Polarity - * 0b0..Transmitter RTS is active low - * 0b1..Transmitter RTS is active high + * 0b0..Active low + * 0b1..Active high */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver RTS Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) @@ -54279,8 +51411,8 @@ typedef struct { #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - IR Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ @@ -54291,74 +51423,74 @@ typedef struct { #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth - * 0b000..Receive FIFO buffer depth = 1 dataword - * 0b001..Receive FIFO buffer depth = 4 datawords - * 0b010..Receive FIFO buffer depth = 8 datawords - * 0b011..Receive FIFO buffer depth = 16 datawords - * 0b100..Receive FIFO buffer depth = 32 datawords - * 0b101..Receive FIFO buffer depth = 64 datawords - * 0b110..Receive FIFO buffer depth = 128 datawords - * 0b111..Receive FIFO buffer depth = 256 datawords + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable - * 0b0..Disables; buffer depth is 1 - * 0b1..Enables; FIFO[RXFIFOSIZE] indicates the buffer depth + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth - * 0b000..Transmit FIFO buffer depth = 1 dataword - * 0b001..Transmit FIFO buffer depth = 4 datawords - * 0b010..Transmit FIFO buffer depth = 8 datawords - * 0b011..Transmit FIFO buffer depth = 16 datawords - * 0b100..Transmit FIFO buffer depth = 32 datawords - * 0b101..Transmit FIFO buffer depth = 64 datawords - * 0b110..Transmit FIFO buffer depth = 128 datawords - * 0b111..Transmit FIFO buffer depth = 256 datawords + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable - * 0b0..Disables; buffer depth is 1 - * 0b1..Enables; FIFO[TXFIFOSIZE] indicates the buffer depth + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable - * 0b0..Disables - * 0b1..Enables + * 0b0..Disable + * 0b1..Enable */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable - * 0b000..Disables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle - * 0b001..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character - * 0b010..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters - * 0b011..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters - * 0b100..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters - * 0b101..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters - * 0b110..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters - * 0b111..Enables STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) @@ -54366,7 +51498,7 @@ typedef struct { #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO Flush * 0b0..No effect - * 0b1..All data is flushed out + * 0b1..All data flushed out */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) @@ -54374,7 +51506,7 @@ typedef struct { #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO Flush * 0b0..No effect - * 0b1..All data is flushed out + * 0b1..All data flushed out */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) @@ -54383,6 +51515,8 @@ typedef struct { /*! RXUF - Receiver FIFO Underflow Flag * 0b0..No underflow * 0b1..Underflow + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) @@ -54391,6 +51525,8 @@ typedef struct { /*! TXOF - Transmitter FIFO Overflow Flag * 0b0..No overflow * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) @@ -54450,48 +51586,48 @@ typedef struct { #define LPUART_MCR_CTS_MASK (0x1U) #define LPUART_MCR_CTS_SHIFT (0U) /*! CTS - Clear To Send - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) #define LPUART_MCR_DSR_MASK (0x2U) #define LPUART_MCR_DSR_SHIFT (1U) /*! DSR - Data Set Ready - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) #define LPUART_MCR_RIN_MASK (0x4U) #define LPUART_MCR_RIN_SHIFT (2U) /*! RIN - Ring Indicator - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) #define LPUART_MCR_DCD_MASK (0x8U) #define LPUART_MCR_DCD_SHIFT (3U) /*! DCD - Data Carrier Detect - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ #define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) #define LPUART_MCR_DTR_MASK (0x100U) #define LPUART_MCR_DTR_SHIFT (8U) /*! DTR - Data Terminal Ready - * 0b0..Default state is logic one - * 0b1..Default state is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) #define LPUART_MCR_RTS_MASK (0x200U) #define LPUART_MCR_RTS_SHIFT (9U) /*! RTS - Request To Send - * 0b0..Default state is logic one - * 0b1..Default state is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) /*! @} */ @@ -54504,6 +51640,8 @@ typedef struct { /*! DCTS - Delta Clear To Send * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) @@ -54512,6 +51650,8 @@ typedef struct { /*! DDSR - Delta Data Set Ready * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) @@ -54520,6 +51660,8 @@ typedef struct { /*! DRI - Delta Ring Indicator * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) @@ -54528,38 +51670,40 @@ typedef struct { /*! DDCD - Delta Data Carrier Detect * 0b0..Did not change state * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag */ #define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) #define LPUART_MSR_CTS_MASK (0x10U) #define LPUART_MSR_CTS_SHIFT (4U) /*! CTS - Clear To Send - * 0b0..The CTS_B pin is logic one - * 0b1..The CTS_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) #define LPUART_MSR_DSR_MASK (0x20U) #define LPUART_MSR_DSR_SHIFT (5U) /*! DSR - Data Set Ready - * 0b0..The DSR_B pin is logic one - * 0b1..The DSR_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) #define LPUART_MSR_RIN_MASK (0x40U) #define LPUART_MSR_RIN_SHIFT (6U) /*! RIN - Ring Indicator - * 0b0..The RIN_B pin is logic one - * 0b1..The RIN_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) #define LPUART_MSR_DCD_MASK (0x80U) #define LPUART_MSR_DCD_SHIFT (7U) /*! DCD - Data Carrier Detect - * 0b0..The DCD_B pin is logic one - * 0b1..The DCD_B pin is logic zero + * 0b0..Logic one + * 0b1..Logic zero */ #define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) /*! @} */ @@ -54604,16 +51748,16 @@ typedef struct { #define LPUART_HDCR_RXWRMSK_MASK (0x4U) #define LPUART_HDCR_RXWRMSK_SHIFT (2U) /*! RXWRMSK - Receive FIFO Write Mask - * 0b0..Does not mask - * 0b1..Masks + * 0b0..Do not mask + * 0b1..Mask */ #define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) #define LPUART_HDCR_RXMSK_MASK (0x8U) #define LPUART_HDCR_RXMSK_SHIFT (3U) /*! RXMSK - Receive Mask - * 0b0..Does not mask - * 0b1..Masks + * 0b0..Do not mask + * 0b1..Mask */ #define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) @@ -54647,7 +51791,12 @@ typedef struct { #define LPUART_TOSR_TOF_MASK (0xF00U) #define LPUART_TOSR_TOF_SHIFT (8U) -/*! TOF - Timeout Flag */ +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0001..Occurred + * 0b0000..No effect + * 0b0001..Clear the flag + */ #define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) /*! @} */ @@ -55146,9 +52295,9 @@ typedef struct { /** MAILBOX - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t IRQ; /**< Cortex_M33 (CPU0) Interrupt..Cortex_M33 (CPU1) Interrupt, array offset: 0x0, array step: 0x10 */ - __O uint32_t IRQSET; /**< Cortex_M33 (CPU0) Interrupt Set..Cortex_M33 (CPU1) Interrupt Set, array offset: 0x4, array step: 0x10 */ - __O uint32_t IRQCLR; /**< Cortex_M33 (CPU0) Interrupt Clear..Cortex_M33 (CPU1) Interrupt Clear, array offset: 0x8, array step: 0x10 */ + __IO uint32_t IRQ; /**< Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt, array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear, array offset: 0x8, array step: 0x10 */ uint8_t RESERVED_0[4]; } MBOXIRQ[2]; uint8_t RESERVED_0[216]; @@ -55164,7 +52313,7 @@ typedef struct { * @{ */ -/*! @name MBOXIRQ_IRQ - Cortex_M33 (CPU0) Interrupt..Cortex_M33 (CPU1) Interrupt */ +/*! @name MBOXIRQ_IRQ - Cortex-M33 (CPU0) Interrupt..CoolFlux (CPU1) Interrupt */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) @@ -55176,7 +52325,7 @@ typedef struct { /* The count of MAILBOX_MBOXIRQ_IRQ */ #define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) -/*! @name MBOXIRQ_IRQSET - Cortex_M33 (CPU0) Interrupt Set..Cortex_M33 (CPU1) Interrupt Set */ +/*! @name MBOXIRQ_IRQSET - Cortex-M33 (CPU0) Interrupt Set..CoolFlux (CPU1) Interrupt Set */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) @@ -55188,7 +52337,7 @@ typedef struct { /* The count of MAILBOX_MBOXIRQ_IRQSET */ #define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) -/*! @name MBOXIRQ_IRQCLR - Cortex_M33 (CPU0) Interrupt Clear..Cortex_M33 (CPU1) Interrupt Clear */ +/*! @name MBOXIRQ_IRQCLR - Cortex-M33 (CPU0) Interrupt Clear..CoolFlux (CPU1) Interrupt Clear */ /*! @{ */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) @@ -55252,3592 +52401,6 @@ typedef struct { */ /* end of group MAILBOX_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- MBC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MBC_Peripheral_Access_Layer MBC Peripheral Access Layer - * @{ - */ - -/** MBC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4096]; - __IO uint32_t MBC0_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x1000, array step: 0x4 */ - __IO uint32_t MBC0_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, offset: 0x1010 */ - __O uint32_t MBC0_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, offset: 0x1014 */ - __O uint32_t MBC0_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, offset: 0x1018 */ - __O uint32_t MBC0_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, offset: 0x101C */ - __IO uint32_t MBC0_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x1020, array step: 0x4 */ - struct { /* offset: 0x1040, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x1040, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W1; /**< MBC Memory Block Configuration Word, array offset: 0x1044, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W2; /**< MBC Memory Block Configuration Word, array offset: 0x1048, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W3; /**< MBC Memory Block Configuration Word, array offset: 0x104C, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W4; /**< MBC Memory Block Configuration Word, array offset: 0x1050, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W5; /**< MBC Memory Block Configuration Word, array offset: 0x1054, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W6; /**< MBC Memory Block Configuration Word, array offset: 0x1058, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_CFG_W7; /**< MBC Memory Block Configuration Word, array offset: 0x105C, array step: 0x18C */ - uint8_t RESERVED_0[224]; - __IO uint32_t MBC0_DOM_MEM0_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1140, array step: 0x18C */ - __IO uint32_t MBC0_DOM_MEM0_BLK_NSE_W1; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1144, array step: 0x18C */ - uint8_t RESERVED_1[56]; - __IO uint32_t MBC0_DOM_MEM1_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x1180, array step: 0x18C */ - uint8_t RESERVED_2[28]; - __IO uint32_t MBC0_DOM_MEM1_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11A0, array step: 0x18C */ - uint8_t RESERVED_3[4]; - __IO uint32_t MBC0_DOM_MEM2_BLK_CFG_W0; /**< MBC Memory Block Configuration Word, array offset: 0x11A8, array step: 0x18C */ - uint8_t RESERVED_4[28]; - __IO uint32_t MBC0_DOM_MEM2_BLK_NSE_W0; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11C8, array step: 0x18C */ - } MBC_DOM0[1]; -} MBC_Type; - -/* ---------------------------------------------------------------------------- - -- MBC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MBC_Register_Masks MBC Register Masks - * @{ - */ - -/*! @name MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG - MBC Global Configuration Register */ -/*! @{ */ - -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_MASK (0x3FFU) -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_SHIFT (0U) -/*! NBLKS - Number of blocks in this memory */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_NBLKS_MASK) - -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) -/*! SIZE_LOG2 - Log2 size per block */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_SIZE_LOG2_MASK) - -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_MASK (0xC0000000U) -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_SHIFT (30U) -/*! CLRE - Clear Error */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_SHIFT)) & MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_CLRE_MASK) -/*! @} */ - -/* The count of MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG */ -#define MBC_MBC_MEM_GLBCFG0_MBC0_MEM_GLBCFG_COUNT (4U) - -/*! @name MBC0_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_INDEX_WNDX_MASK (0x3CU) -#define MBC_MBC0_NSE_BLK_INDEX_WNDX_SHIFT (2U) -/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ -#define MBC_MBC0_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_WNDX_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_WNDX_MASK) - -#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) -#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) -/*! MEM_SEL - Memory Select */ -#define MBC_MBC0_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_MEM_SEL_MASK) - -#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) -#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) -/*! DID_SEL0 - DID Select - * 0b0..No effect. - * 0b1..Selects NSE bits for this domain. - */ -#define MBC_MBC0_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_DID_SEL0_MASK) - -#define MBC_MBC0_NSE_BLK_INDEX_AI_MASK (0x80000000U) -#define MBC_MBC0_NSE_BLK_INDEX_AI_SHIFT (31U) -/*! AI - Auto Increment - * 0b0..No effect. - * 0b1..Add 1 to the WNDX field after the register write. - */ -#define MBC_MBC0_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_INDEX_AI_SHIFT)) & MBC_MBC0_NSE_BLK_INDEX_AI_MASK) -/*! @} */ - -/*! @name MBC0_NSE_BLK_SET - MBC NonSecure Enable Block Set */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) -#define MBC_MBC0_NSE_BLK_SET_W1SET_SHIFT (0U) -/*! W1SET - Write-1 Set */ -#define MBC_MBC0_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_SET_W1SET_SHIFT)) & MBC_MBC0_NSE_BLK_SET_W1SET_MASK) -/*! @} */ - -/*! @name MBC0_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) -#define MBC_MBC0_NSE_BLK_CLR_W1CLR_SHIFT (0U) -/*! W1CLR - Write-1 Clear */ -#define MBC_MBC0_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_W1CLR_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_W1CLR_MASK) -/*! @} */ - -/*! @name MBC0_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ -/*! @{ */ - -#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) -#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) -/*! MEMSEL - Memory Select */ -#define MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_ALL_MEMSEL_MASK) - -#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) -#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) -/*! DID_SEL0 - DID Select - * 0b0..No effect. - * 0b1..Clear all NSE bits for this domain. - */ -#define MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & MBC_MBC0_NSE_BLK_CLR_ALL_DID_SEL0_MASK) -/*! @} */ - -/*! @name MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC - MBC Global Access Control */ -/*! @{ */ - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_MASK (0x1U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_SHIFT (0U) -/*! NUX - NonsecureUser Execute - * 0b0..Execute access is not allowed in Nonsecure User mode. - * 0b1..Execute access is allowed in Nonsecure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_MASK (0x2U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_SHIFT (1U) -/*! NUW - NonsecureUser Write - * 0b0..Write access is not allowed in Nonsecure User mode. - * 0b1..Write access is allowed in Nonsecure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_MASK (0x4U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_SHIFT (2U) -/*! NUR - NonsecureUser Read - * 0b0..Read access is not allowed in Nonsecure User mode. - * 0b1..Read access is allowed in Nonsecure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NUR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_MASK (0x10U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_SHIFT (4U) -/*! NPX - NonsecurePriv Execute - * 0b0..Execute access is not allowed in Nonsecure Privilege mode. - * 0b1..Execute access is allowed in Nonsecure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_MASK (0x20U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_SHIFT (5U) -/*! NPW - NonsecurePriv Write - * 0b0..Write access is not allowed in Nonsecure Privilege mode. - * 0b1..Write access is allowed in Nonsecure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_MASK (0x40U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_SHIFT (6U) -/*! NPR - NonsecurePriv Read - * 0b0..Read access is not allowed in Nonsecure Privilege mode. - * 0b1..Read access is allowed in Nonsecure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_NPR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_MASK (0x100U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_SHIFT (8U) -/*! SUX - SecureUser Execute - * 0b0..Execute access is not allowed in Secure User mode. - * 0b1..Execute access is allowed in Secure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_MASK (0x200U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_SHIFT (9U) -/*! SUW - SecureUser Write - * 0b0..Write access is not allowed in Secure User mode. - * 0b1..Write access is allowed in Secure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_MASK (0x400U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_SHIFT (10U) -/*! SUR - SecureUser Read - * 0b0..Read access is not allowed in Secure User mode. - * 0b1..Read access is allowed in Secure User mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SUR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_MASK (0x1000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_SHIFT (12U) -/*! SPX - SecurePriv Execute - * 0b0..Execute access is not allowed in Secure Privilege mode. - * 0b1..Execute access is allowed in Secure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPX_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_MASK (0x2000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_SHIFT (13U) -/*! SPW - SecurePriv Write - * 0b0..Write access is not allowed in Secure Privilege mode. - * 0b1..Write access is allowed in Secure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPW_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_MASK (0x4000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_SHIFT (14U) -/*! SPR - SecurePriv Read - * 0b0..Read access is not allowed in Secure Privilege mode. - * 0b1..Read access is allowed in Secure Privilege mode. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_SPR_MASK) - -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_MASK (0x80000000U) -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_SHIFT (31U) -/*! LK - LOCK - * 0b0..This register is not locked and can be altered. - * 0b1..This register is locked and cannot be altered. - */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_SHIFT)) & MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_LK_MASK) -/*! @} */ - -/* The count of MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC */ -#define MBC_MBC_MEMN_GLBAC0_MBC0_MEMN_GLBAC_COUNT (8U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W1_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W2_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W3_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W4_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W5_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W6_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_CFG_W7_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM0_BLK_NSE_W1_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_CFG_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM1_BLK_NSE_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0 - MBC Memory Block Configuration Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_MASK (0x7U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_SHIFT (0U) -/*! MBACSEL0 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_SHIFT (3U) -/*! NSE0 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_MASK (0x70U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_SHIFT (4U) -/*! MBACSEL1 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_SHIFT (7U) -/*! NSE1 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_MASK (0x700U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_SHIFT (8U) -/*! MBACSEL2 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_SHIFT (11U) -/*! NSE2 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_MASK (0x7000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_SHIFT (12U) -/*! MBACSEL3 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_SHIFT (15U) -/*! NSE3 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_MASK (0x70000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_SHIFT (16U) -/*! MBACSEL4 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_SHIFT (19U) -/*! NSE4 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_MASK (0x700000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_SHIFT (20U) -/*! MBACSEL5 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_SHIFT (23U) -/*! NSE5 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_MASK (0x7000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_SHIFT (24U) -/*! MBACSEL6 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_SHIFT (27U) -/*! NSE6 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_MASK (0x70000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_SHIFT (28U) -/*! MBACSEL7 - Memory Block Access Control Select for block B - * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B - * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B - * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B - * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B - * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B - * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B - * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B - * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_MBACSEL7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_SHIFT (31U) -/*! NSE7 - NonSecure Enable for block B - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_NSE7_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_CFG_W0_COUNT (1U) - -/*! @name MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0 - MBC Memory Block NonSecure Enable Word */ -/*! @{ */ - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_MASK (0x1U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_SHIFT (0U) -/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT0_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_MASK (0x2U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_SHIFT (1U) -/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT1_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_MASK (0x4U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_SHIFT (2U) -/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT2_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_MASK (0x8U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_SHIFT (3U) -/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT3_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_MASK (0x10U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_SHIFT (4U) -/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT4_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_MASK (0x20U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_SHIFT (5U) -/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT5_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_MASK (0x40U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_SHIFT (6U) -/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT6_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_MASK (0x80U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_SHIFT (7U) -/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT7_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_MASK (0x100U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_SHIFT (8U) -/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT8_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_MASK (0x200U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_SHIFT (9U) -/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT9_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_MASK (0x400U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_SHIFT (10U) -/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT10_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_MASK (0x800U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_SHIFT (11U) -/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT11_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_MASK (0x1000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_SHIFT (12U) -/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT12_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_MASK (0x2000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_SHIFT (13U) -/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT13_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_MASK (0x4000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_SHIFT (14U) -/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT14_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_MASK (0x8000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_SHIFT (15U) -/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT15_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_MASK (0x10000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_SHIFT (16U) -/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT16_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_MASK (0x20000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_SHIFT (17U) -/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT17_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_MASK (0x40000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_SHIFT (18U) -/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT18_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_MASK (0x80000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_SHIFT (19U) -/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT19_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_MASK (0x100000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_SHIFT (20U) -/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT20_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_MASK (0x200000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_SHIFT (21U) -/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT21_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_MASK (0x400000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_SHIFT (22U) -/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT22_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_MASK (0x800000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_SHIFT (23U) -/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT23_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_MASK (0x1000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_SHIFT (24U) -/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT24_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_MASK (0x2000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_SHIFT (25U) -/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT25_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_MASK (0x4000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_SHIFT (26U) -/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT26_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_MASK (0x8000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_SHIFT (27U) -/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT27_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_MASK (0x10000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_SHIFT (28U) -/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT28_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_MASK (0x20000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_SHIFT (29U) -/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT29_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_MASK (0x40000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_SHIFT (30U) -/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT30_MASK) - -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_MASK (0x80000000U) -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_SHIFT (31U) -/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] - * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register - * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. - * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding - * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). - */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31(x) (((uint32_t)(((uint32_t)(x)) << MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_SHIFT)) & MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_BIT31_MASK) -/*! @} */ - -/* The count of MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0 */ -#define MBC_MBC_DOM0_MBC0_DOM_MEM2_BLK_NSE_W0_COUNT (1U) - - -/*! - * @} - */ /* end of group MBC_Register_Masks */ - - -/* MBC - Peripheral instance base addresses */ -#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral TRDC base address */ - #define TRDC_BASE (0x500C6000u) - /** Peripheral TRDC base address */ - #define TRDC_BASE_NS (0x400C6000u) - /** Peripheral TRDC base pointer */ - #define TRDC ((MBC_Type *)TRDC_BASE) - /** Peripheral TRDC base pointer */ - #define TRDC_NS ((MBC_Type *)TRDC_BASE_NS) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { TRDC_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { TRDC } - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS_NS { TRDC_BASE_NS } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS_NS { TRDC_NS } -#else - /** Peripheral TRDC base address */ - #define TRDC_BASE (0x400C6000u) - /** Peripheral TRDC base pointer */ - #define TRDC ((MBC_Type *)TRDC_BASE) - /** Array initializer of MBC peripheral base addresses */ - #define MBC_BASE_ADDRS { TRDC_BASE } - /** Array initializer of MBC peripheral base pointers */ - #define MBC_BASE_PTRS { TRDC } -#endif - -/*! - * @} - */ /* end of group MBC_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- MRT Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -58932,10 +52495,7 @@ typedef struct { #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. Writing 0 indicates no pending interrupt or no operation. - * Writing 1 indicates pending interrupt, because TIMERn has reached the end of the time - * interval. If CTRL and the global interrupt are generated. Writing 1 to this field bit clears the - * interrupt request.n in the CONTROLn also gets 1, then the interrupt for timer channel n +/*! INTFLAG - Interrupt Flag * 0b0..No pending interrupt. * 0b1..Pending interrupt. */ @@ -59233,12 +52793,12 @@ typedef struct { #define NPX_REMAP_LIM_MASK (0x1F0000U) #define NPX_REMAP_LIM_SHIFT (16U) -/*! LIM - LIM data */ +/*! LIM - LIM Remapping Address */ #define NPX_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK) #define NPX_REMAP_LIMDP_MASK (0x1F000000U) #define NPX_REMAP_LIMDP_SHIFT (24U) -/*! LIMDP - LIM_DP data */ +/*! LIMDP - LIMDP Remapping Address */ #define NPX_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK) /*! @} */ @@ -59911,10 +53471,10 @@ typedef struct { #define OPAMP_OPAMP_CTR_INTREF_MASK (0x30U) #define OPAMP_OPAMP_CTR_INTREF_SHIFT (4U) -/*! INTREF - Internal Reference Voltage Selection - * 0b00..Select VDDA/2 - * 0b01..Select VDDA_3V - * 0b10..Select VSSA_3V +/*! INTREF - Provide OPAMP rail to rail voltage selection + * 0b00..Select OPAMP input rail to rail voltage from 0 to VDD_ANA + * 0b01..Select OPAMP input rail to rail voltage from 0 to VDD_ANA-0.8V + * 0b10..Select OPAMP input rail to rail voltage from 0.8V to VDD_ANA * 0b11..Not allowed */ #define OPAMP_OPAMP_CTR_INTREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK) @@ -59954,10 +53514,10 @@ typedef struct { #define OPAMP_OPAMP_CTR_PREF_MASK (0x60000U) #define OPAMP_OPAMP_CTR_PREF_SHIFT (17U) /*! PREF - Positive Reference Voltage Selection - * 0b00..DACx_OUT - * 0b01..VDDA/2 - * 0b10..VREFO - * 0b11..520 mV + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 */ #define OPAMP_OPAMP_CTR_PREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK) @@ -59989,13 +53549,13 @@ typedef struct { #define OPAMP_OPAMP_CTR_PGAIN_SHIFT (24U) /*! PGAIN - Positive PGA Selection * 0b000..Positive input 1 (INP1) - * 0b001..Gain application 1* - * 0b010..Gain application 2* - * 0b011..Gain application 4* - * 0b100..Gain application 8* - * 0b101..Gain application 16* - * 0b110..Gain application 33* - * 0b111..Gain application 64* + * 0b001..Pgain=1 + * 0b010..Pgain=2 + * 0b011..Pgain=4 + * 0b100..Pgain=8 + * 0b101..Pgain=16 + * 0b110..Pgain=33 + * 0b111..Pgain=64 */ #define OPAMP_OPAMP_CTR_PGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK) @@ -60003,13 +53563,13 @@ typedef struct { #define OPAMP_OPAMP_CTR_NGAIN_SHIFT (28U) /*! NGAIN - Negative PGA Selection * 0b000..Buffer - * 0b001..Gain application 1* - * 0b010..Gain application 2* - * 0b011..Gain application 4* - * 0b100..Gain application 8* - * 0b101..Gain application 16* - * 0b110..Gain application 33* - * 0b111..Gain application 64* + * 0b001..Ngain=1 + * 0b010..Ngain=2 + * 0b011..Ngain=4 + * 0b100..Ngain=8 + * 0b101..Ngain=16 + * 0b110..Ngain=33 + * 0b111..Ngain=64 */ #define OPAMP_OPAMP_CTR_NGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK) /*! @} */ @@ -60850,7 +54410,10 @@ typedef struct { #define PDM_CTRL_1_DOZEN_MASK (0x40000000U) #define PDM_CTRL_1_DOZEN_SHIFT (30U) -/*! DOZEN - Doze Enable */ +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ #define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) #define PDM_CTRL_1_MDIS_MASK (0x80000000U) @@ -60867,7 +54430,12 @@ typedef struct { #define PDM_CTRL_2_CLKDIV_MASK (0xFFU) #define PDM_CTRL_2_CLKDIV_SHIFT (0U) -/*! CLKDIV - Clock Divider */ +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ #define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) #define PDM_CTRL_2_CLKDIVDIS_MASK (0x8000U) @@ -60880,7 +54448,12 @@ typedef struct { #define PDM_CTRL_2_CICOSR_MASK (0xF0000U) #define PDM_CTRL_2_CICOSR_SHIFT (16U) -/*! CICOSR - CIC Decimation Rate */ +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ #define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) #define PDM_CTRL_2_QSEL_MASK (0xE000000U) @@ -61242,12 +54815,24 @@ typedef struct { #define PDM_PARAM_NPAIR_MASK (0xFU) #define PDM_PARAM_NPAIR_SHIFT (0U) -/*! NPAIR - Number of Microphone Pairs */ +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ #define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) #define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) #define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) -/*! FIFO_PTRWID - FIFO Pointer Width */ +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ #define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) #define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) @@ -61519,112 +55104,112 @@ typedef struct { #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) /*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) #define PINT_PMSRC_SRC1_MASK (0x3800U) #define PINT_PMSRC_SRC1_SHIFT (11U) /*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) #define PINT_PMSRC_SRC2_MASK (0x1C000U) #define PINT_PMSRC_SRC2_SHIFT (14U) /*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) #define PINT_PMSRC_SRC3_MASK (0xE0000U) #define PINT_PMSRC_SRC3_SHIFT (17U) /*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) #define PINT_PMSRC_SRC4_MASK (0x700000U) #define PINT_PMSRC_SRC4_SHIFT (20U) /*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) #define PINT_PMSRC_SRC5_MASK (0x3800000U) #define PINT_PMSRC_SRC5_SHIFT (23U) /*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) #define PINT_PMSRC_SRC6_MASK (0x1C000000U) #define PINT_PMSRC_SRC6_SHIFT (26U) /*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) /*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0 (selects the pin identified in PINT_SEL0) - * 0b001..Input 1 (selects the pin identified in PINT_SEL1) - * 0b010..Input 2 (selects the pin identified in PINT_SEL2) - * 0b011..Input 3 (selects the pin identified in PINT_SEL3) - * 0b100..Input 4 (selects the pin identified in PINT_SEL4) - * 0b101..Input 5 (selects the pin identified in PINT_SEL5) - * 0b110..Input 6 (selects the pin identified in PINT_SEL6) - * 0b111..Input 7 (selects the pin identified in PINT_SEL7) + * 0b000..Input 0 (selects the pin identified in PINSEL0) + * 0b001..Input 1 (selects the pin identified in PINSEL1) + * 0b010..Input 2 (selects the pin identified in PINSEL2) + * 0b011..Input 3 (selects the pin identified in PINSEL3) + * 0b100..Input 4 (selects the pin identified in PINSEL4) + * 0b101..Input 5 (selects the pin identified in PINSEL5) + * 0b110..Input 6 (selects the pin identified in PINSEL6) + * 0b111..Input 7 (selects the pin identified in PINSEL7) */ #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) /*! @} */ @@ -61871,8 +55456,8 @@ typedef struct { /** PKC - Register Layout Typedef */ typedef struct { - __I uint32_t PKC_STATUS; /**< Status register, offset: 0x0 */ - __IO uint32_t PKC_CTRL; /**< Control register, offset: 0x4 */ + __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ @@ -61916,151 +55501,97 @@ typedef struct { * @{ */ -/*! @name PKC_STATUS - Status register */ +/*! @name PKC_STATUS - Status Register */ /*! @{ */ #define PKC_PKC_STATUS_ACTIV_MASK (0x1U) #define PKC_PKC_STATUS_ACTIV_SHIFT (0U) -/*! activ - PKC active: ACTIV=1 signals that a calculation is in progress or about to start. At the - * end of a calculation ACTIV is automatically reset to logic 0 in case no further GO bit is set. - * If the next PKC operation has been started by setting a GO bit during a calculation, ACTIV - * remains high. ACTIV is always '1' in case PKC_STATUS.GOANY is set. ACTIV is always '0' in case - * PKC_CTRL_RESET is set. - */ +/*! ACTIV - PKC ACTIV */ #define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) #define PKC_PKC_STATUS_CARRY_MASK (0x2U) #define PKC_PKC_STATUS_CARRY_SHIFT (1U) -/*! carry - Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case */ +/*! CARRY - Carry overflow flag */ #define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) #define PKC_PKC_STATUS_ZERO_MASK (0x4U) #define PKC_PKC_STATUS_ZERO_SHIFT (2U) -/*! zero - Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result - * of the calculation is equal zero. ZERO is updated for each PKC calculation mode, except for - * MUL1 (opcode 0x20) and MUL1_GF2 (opcode 0x24). - */ +/*! ZERO - Zero result flag */ #define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) #define PKC_PKC_STATUS_GOANY_MASK (0x8U) #define PKC_PKC_STATUS_GOANY_SHIFT (3U) -/*! goany - Combined GO status flag: GOANY is set in case either PKC_CTRL.GOD1, GOD2, GOM1, GOM2 or - * GOU is set. The 1-to-0 transition of GOANY indicates that a calculation has been started and - * that a new GO bit can be set. If GOANY is cleared also all PKC_STATUS.LOCKED bits are cleared - * to indicate that the parameter set can be updated. GOANY is always '0' in case PKC_CTRL.RESET - * is set. - */ +/*! GOANY - Combined GO status flag */ #define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) -#define PKC_PKC_STATUS_RESERVED4_MASK (0x10U) -#define PKC_PKC_STATUS_RESERVED4_SHIFT (4U) -/*! reserved4 - reserved */ -#define PKC_PKC_STATUS_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_RESERVED4_SHIFT)) & PKC_PKC_STATUS_RESERVED4_MASK) - #define PKC_PKC_STATUS_LOCKED_MASK (0x60U) #define PKC_PKC_STATUS_LOCKED_SHIFT (5U) -/*! locked - Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten. */ +/*! LOCKED - Parameter set locked */ #define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) - -#define PKC_PKC_STATUS_RESERVED31_MASK (0xFFFFFF80U) -#define PKC_PKC_STATUS_RESERVED31_SHIFT (7U) -/*! reserved31 - reserved */ -#define PKC_PKC_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_RESERVED31_SHIFT)) & PKC_PKC_STATUS_RESERVED31_MASK) /*! @} */ -/*! @name PKC_CTRL - Control register */ +/*! @name PKC_CTRL - Control Register */ /*! @{ */ #define PKC_PKC_CTRL_RESET_MASK (0x1U) #define PKC_PKC_CTRL_RESET_SHIFT (0U) -/*! reset - PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation - * cannot be started and by which any ongoing calculation process is stopped. RESET can be - * set/cleared by the CPU in order to switch between PKC reset and calculation enable. RESET=1 is the - * default state after a chip reset. - */ +/*! RESET - PKC reset control bit */ #define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) #define PKC_PKC_CTRL_STOP_MASK (0x2U) #define PKC_PKC_CTRL_STOP_SHIFT (1U) -/*! stop - Freeze PKC calculation: STOP=1 freezes all PKC activity incl. RAM accesses and reduces - * the PKC power consumption to its minimum. The difference compared to the reset of the PKC is - * that a stopped calculation can be continued when STOP is released (reset to '0') again. The - * status flags are not affected by the STOP control bit. - */ +/*! STOP - Freeze PKC calculation */ #define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) #define PKC_PKC_CTRL_GOD1_MASK (0x4U) #define PKC_PKC_CTRL_GOD1_SHIFT (2U) -/*! god1 - Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will - * start a direct / L0 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, PKC_LEN1). - */ +/*! GOD1 - Control bit to start direct operation using parameter set 1 */ #define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) #define PKC_PKC_CTRL_GOD2_MASK (0x8U) #define PKC_PKC_CTRL_GOD2_SHIFT (3U) -/*! god2 - Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will - * start a direct / L0 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2). - */ +/*! GOD2 - Control bit to start direct operation using parameter set 2 */ #define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) #define PKC_PKC_CTRL_GOM1_MASK (0x10U) #define PKC_PKC_CTRL_GOM1_SHIFT (4U) -/*! gom1 - Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC - * pattern / L1 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, PKC_LEN1). - */ +/*! GOM1 - Control bit to start MC pattern using parameter set 1 */ #define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) #define PKC_PKC_CTRL_GOM2_MASK (0x20U) #define PKC_PKC_CTRL_GOM2_SHIFT (5U) -/*! gom2 - Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC - * pattern / L1 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2). - */ +/*! GOM2 - Control bit to start MC pattern using parameter set 2 */ #define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) #define PKC_PKC_CTRL_GOU_MASK (0x40U) #define PKC_PKC_CTRL_GOU_SHIFT (6U) -/*! gou - Control bit to start pipe operation: If GOU is set PKC will start the pipe / L2 operation - * (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch Operation'. - */ +/*! GOU - Control bit to start pipe operation */ #define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) #define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) #define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) -/*! gf2conv - Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes. */ +/*! GF2CONV - Convert to GF2 calculation modes */ #define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) #define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) #define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) -/*! clrcache - Clear universal pointer cache: Invalidates the cache such that all previously fetched - * parameters are withdrawn and have to be fetched again via DMA accesses. - */ +/*! CLRCACHE - Clear universal pointer cache */ #define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) #define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) #define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) -/*! cache_en - Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer - * parameters is enabled. In case a parameter value is found in the cache (from a previous fetch) no - * DMA access is triggered. As such the amount of DMA accesses for the parameter fetch vary - * between 0 and 4. To further optimize the cache utilization not used parameters, e.g. XPTR for a - * plain addition (opcode 0x0A), could be defined equal to a used one (e.g. equal YPTR or RPTR) or - * a previously fetched parameter. - */ +/*! CACHE_EN - Enable universal pointer cache */ #define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) #define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) #define PKC_PKC_CTRL_REDMUL_SHIFT (10U) -/*! redmul - Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor. +/*! REDMUL - Reduced multiplier mode * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 - * 0b01..RFU Error Generated if selected + * 0b01..Reserved - Error Generated if selected * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 - * 0b11..RFU Error Generated if selected + * 0b11..Reserved - Error Generated if selected */ #define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) - -#define PKC_PKC_CTRL_RESERVED31_MASK (0xFFFFF000U) -#define PKC_PKC_CTRL_RESERVED31_SHIFT (12U) -/*! reserved31 - reserved */ -#define PKC_PKC_CTRL_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESERVED31_SHIFT)) & PKC_PKC_CTRL_RESERVED31_MASK) /*! @} */ /*! @name PKC_CFG - Configuration register */ @@ -62068,53 +55599,39 @@ typedef struct { #define PKC_PKC_CFG_IDLEOP_MASK (0x1U) #define PKC_PKC_CFG_IDLEOP_SHIFT (0U) -/*! idleop - Idle operation feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) #define PKC_PKC_CFG_RFU1_MASK (0x2U) #define PKC_PKC_CFG_RFU1_SHIFT (1U) -/*! rfu1 - RFU */ #define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) #define PKC_PKC_CFG_RFU2_MASK (0x4U) #define PKC_PKC_CFG_RFU2_SHIFT (2U) -/*! rfu2 - RFU */ #define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) #define PKC_PKC_CFG_CLKRND_MASK (0x8U) #define PKC_PKC_CFG_CLKRND_SHIFT (3U) -/*! clkrnd - Clock randomization feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) #define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) #define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) -/*! redmulnoise - Noise in reduced multiplier mode feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) #define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) #define PKC_PKC_CFG_RNDDLY_SHIFT (5U) -/*! rnddly - Random delay feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) #define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) #define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) -/*! sbxnoise - Noise feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) #define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) #define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) -/*! alpnoise - Noise feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) #define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) #define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) -/*! fmulnoise - Noise feature not available in this version (flag is don't care). */ #define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) - -#define PKC_PKC_CFG_RESERVED31_MASK (0xFFFFF800U) -#define PKC_PKC_CFG_RESERVED31_SHIFT (11U) -/*! reserved31 - reserved */ -#define PKC_PKC_CFG_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RESERVED31_SHIFT)) & PKC_PKC_CFG_RESERVED31_MASK) /*! @} */ /*! @name PKC_MODE1 - Mode register, parameter set 1 */ @@ -62122,13 +55639,8 @@ typedef struct { #define PKC_PKC_MODE1_MODE_MASK (0xFFU) #define PKC_PKC_MODE1_MODE_SHIFT (0U) -/*! mode - Calculation Mode / MC Start address: */ +/*! MODE - Calculation Mode / MC Start address */ #define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) - -#define PKC_PKC_MODE1_RESERVED31_MASK (0xFFFFFF00U) -#define PKC_PKC_MODE1_RESERVED31_SHIFT (8U) -/*! reserved31 - reserved */ -#define PKC_PKC_MODE1_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_RESERVED31_SHIFT)) & PKC_PKC_MODE1_RESERVED31_MASK) /*! @} */ /*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ @@ -62136,18 +55648,12 @@ typedef struct { #define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) #define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) -/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) #define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) #define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) -/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) /*! @} */ @@ -62156,15 +55662,12 @@ typedef struct { #define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) #define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) -/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: */ +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ #define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) #define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) #define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) -/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ #define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) /*! @} */ @@ -62173,19 +55676,12 @@ typedef struct { #define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) #define PKC_PKC_LEN1_LEN_SHIFT (0U) -/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length - * of Y, Z and R depend furthermore on the selected calculation mode. - */ +/*! LEN - Operand length */ #define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) #define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) #define PKC_PKC_LEN1_MCLEN_SHIFT (16U) -/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that - * can be used in L1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC patterns - * Modular Multiplication (MC start address 0x00), Plain Multiplication (0x13), Plain - * Multiplication with Addition (0x1D) and Modular Reduction (0x33) MCLEN defines the length of the X operand - * in bytes. - */ +/*! MCLEN - Loop counter for microcode pattern */ #define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) /*! @} */ @@ -62194,13 +55690,8 @@ typedef struct { #define PKC_PKC_MODE2_MODE_MASK (0xFFU) #define PKC_PKC_MODE2_MODE_SHIFT (0U) -/*! mode - Calculation Mode / MC Start address: */ +/*! MODE - Calculation Mode / MC Start address */ #define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) - -#define PKC_PKC_MODE2_RESERVED31_MASK (0xFFFFFF00U) -#define PKC_PKC_MODE2_RESERVED31_SHIFT (8U) -/*! reserved31 - reserved */ -#define PKC_PKC_MODE2_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_RESERVED31_SHIFT)) & PKC_PKC_MODE2_RESERVED31_MASK) /*! @} */ /*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ @@ -62208,35 +55699,26 @@ typedef struct { #define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) #define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) -/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) #define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) #define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) -/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ #define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) /*! @} */ /*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ /*! @{ */ -#define PKC_PKC_ZRPTR2_ZPTR_MASK (0xFFFFU) -#define PKC_PKC_ZRPTR2_ZPTR_SHIFT (0U) -/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST: */ -#define PKC_PKC_ZRPTR2_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPTR_SHIFT)) & PKC_PKC_ZRPTR2_ZPTR_MASK) +#define PKC_PKC_ZRPTR2_ZPT_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_ZPT_SHIFT (0U) +/*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR2_ZPT(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK) #define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) #define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) -/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are - * ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on - * available PKCRAM size. - */ +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ #define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) /*! @} */ @@ -62245,17 +55727,12 @@ typedef struct { #define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) #define PKC_PKC_LEN2_LEN_SHIFT (0U) -/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length - * of Y, Z and R depend furthermore on the selected calculation mode. - */ +/*! LEN - Operand length */ #define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) #define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) #define PKC_PKC_LEN2_MCLEN_SHIFT (16U) -/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that - * can be used in L1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC patterns - * Modular Multiplication (MC start address 0x00) - */ +/*! MCLEN - Loop counter for microcode pattern */ #define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) /*! @} */ @@ -62264,11 +55741,7 @@ typedef struct { #define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) #define PKC_PKC_UPTR_PTR_SHIFT (0U) -/*! ptr - Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting - * a universal pointer PKC calculation (L2) via PKC_CTRL.GOU. The pointer address needs to be - * valid and the memory space the pointer addresses needs to be enabled for PKC access by the - * system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). - */ +/*! PTR - Pointer to start address of PKC FUP program */ #define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) /*! @} */ @@ -62277,11 +55750,7 @@ typedef struct { #define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) #define PKC_PKC_UPTRT_PTR_SHIFT (0U) -/*! ptr - Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a - * universal pointer PKC calculation (L2) via PKC_CTRL.GOU. The pointer address needs to be - * valid and the memory space the pointer addresses needs to be enabled for PKC access by the system. - * Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set). - */ +/*! PTR - Pointer to start address of PKC FUP table */ #define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) /*! @} */ @@ -62290,16 +55759,8 @@ typedef struct { #define PKC_PKC_ULEN_LEN_MASK (0xFFU) #define PKC_PKC_ULEN_LEN_SHIFT (0U) -/*! len - Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries - * shall be processed for one L2 calculation started via PKC_CTRL.GOU. The FUP program entries - * include L0 calculations, L1 calculations and CRC entries for FUP program integrity protection. - */ +/*! LEN - Length of universal pointer calculation */ #define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) - -#define PKC_PKC_ULEN_RESERVED31_MASK (0xFFFFFF00U) -#define PKC_PKC_ULEN_RESERVED31_SHIFT (8U) -/*! reserved31 - reserved */ -#define PKC_PKC_ULEN_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_RESERVED31_SHIFT)) & PKC_PKC_ULEN_RESERVED31_MASK) /*! @} */ /*! @name PKC_MCDATA - MC pattern data interface */ @@ -62307,10 +55768,7 @@ typedef struct { #define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) #define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) -/*! mcdata - Microcode read/write data: This IP version does not support flexible MC patterns (only - * hard coded ones). Any read or write access to PKC_MCDATA triggers a security alarm - * (PKC_ACCESS_ERR.CTRL is set). - */ +/*! MCDATA - Microcode read/write data */ #define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) /*! @} */ @@ -62319,67 +55777,54 @@ typedef struct { #define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) #define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) -/*! mulsize - native multiplier size and operand granularity +/*! MULSIZE * 0b01..32-bit multiplier * 0b10..64-bit multiplier * 0b11..128-bit multiplier + * 0b10..128-bit multiplier + * 0b01..64-bit multiplier */ #define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) #define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) #define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) -/*! mcavail - MC feature (L1 calculation) is available */ #define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) #define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) #define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) -/*! upavail - UP feature (L2 calculation) is available */ #define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) #define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) #define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) -/*! upcacheavail - UP cache is available */ #define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) #define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) #define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) -/*! gf2avail - GF2 calculation modes are available */ #define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) #define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) #define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) -/*! paramnum - Number of parameter sets for real calculation */ #define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) #define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) #define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) -/*! sbx0avail - SBX0 operation is available */ #define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) #define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) #define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) -/*! sbx1avail - SBX1 operation is available */ #define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) #define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) #define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) -/*! sbx2avail - SBX2 operation is available */ #define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) #define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) #define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) -/*! sbx3avail - SBX3 operation is available */ #define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) #define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) #define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) -/*! mcreconf_size - Size of reconfigurable MC table in bytes */ #define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) - -#define PKC_PKC_VERSION_RESERVED31_MASK (0xFFF00000U) -#define PKC_PKC_VERSION_RESERVED31_SHIFT (20U) -/*! reserved31 - reserved */ -#define PKC_PKC_VERSION_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_RESERVED31_SHIFT)) & PKC_PKC_VERSION_RESERVED31_MASK) /*! @} */ /*! @name PKC_SOFT_RST - Software reset */ @@ -62387,15 +55832,7 @@ typedef struct { #define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) #define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) -/*! soft_rst - Write 1 to reset module (0 has no effect). All running and pending PKC calculation - * are stopped. All PKC SFRs are reset except PKC_ACCESS_ERR. - */ #define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) - -#define PKC_PKC_SOFT_RST_RESERVED31_MASK (0xFFFFFFFEU) -#define PKC_PKC_SOFT_RST_RESERVED31_SHIFT (1U) -/*! reserved31 - reserved */ -#define PKC_PKC_SOFT_RST_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_RESERVED31_SHIFT)) & PKC_PKC_SOFT_RST_RESERVED31_MASK) /*! @} */ /*! @name PKC_ACCESS_ERR - Access Error */ @@ -62403,68 +55840,38 @@ typedef struct { #define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) #define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) -/*! apb_notav - APB Error: address not available */ +/*! APB_NOTAV - APB Error */ #define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) #define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) #define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) -/*! apb_wrgmd - APB Error: Wrong access mode */ +/*! APB_WRGMD - APB Error */ #define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) -#define PKC_PKC_ACCESS_ERR_RESERVED3_MASK (0xCU) -#define PKC_PKC_ACCESS_ERR_RESERVED3_SHIFT (2U) -/*! reserved3 - reserved for future erors on APB I/F */ -#define PKC_PKC_ACCESS_ERR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED3_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED3_MASK) - #define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) #define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) -/*! apb_master - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV) */ #define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) -#define PKC_PKC_ACCESS_ERR_RESERVED9_MASK (0x300U) -#define PKC_PKC_ACCESS_ERR_RESERVED9_SHIFT (8U) -/*! reserved9 - reserved for future erors on AHB I/F L2 Only */ -#define PKC_PKC_ACCESS_ERR_RESERVED9(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED9_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED9_MASK) - #define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) #define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) -/*! ahb - AHB Error: invalid AHB access L2 Only */ +/*! AHB - AHB Error */ #define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) -#define PKC_PKC_ACCESS_ERR_RESERVED15_MASK (0xF800U) -#define PKC_PKC_ACCESS_ERR_RESERVED15_SHIFT (11U) -/*! reserved15 - reserved for future erors on AHB I/F L2 Only */ -#define PKC_PKC_ACCESS_ERR_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED15_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED15_MASK) - #define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) #define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) -/*! pkcc - Error in PKC coprocessor kernel */ #define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) #define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) #define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) -/*! fdet - Error due to error detection circuitry */ #define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) #define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) #define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) -/*! ctrl - Error in PKC software control */ #define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) #define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) #define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) -/*! ucrc - Error in L2 CRC check */ #define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) - -#define PKC_PKC_ACCESS_ERR_RESERVED20_MASK (0x100000U) -#define PKC_PKC_ACCESS_ERR_RESERVED20_SHIFT (20U) -/*! reserved20 - reserved */ -#define PKC_PKC_ACCESS_ERR_RESERVED20(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED20_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED20_MASK) - -#define PKC_PKC_ACCESS_ERR_RESERVED31_MASK (0xFFE00000U) -#define PKC_PKC_ACCESS_ERR_RESERVED31_SHIFT (21U) -/*! reserved31 - reserved for more block errors */ -#define PKC_PKC_ACCESS_ERR_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_RESERVED31_SHIFT)) & PKC_PKC_ACCESS_ERR_RESERVED31_MASK) /*! @} */ /*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ @@ -62472,13 +55879,7 @@ typedef struct { #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) -/*! err_clr - Write 1 to reset PKC_ACCESS_ERR SFR. */ #define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) - -#define PKC_PKC_ACCESS_ERR_CLR_RESERVED31_MASK (0xFFFFFFFEU) -#define PKC_PKC_ACCESS_ERR_CLR_RESERVED31_SHIFT (1U) -/*! reserved31 - reserved */ -#define PKC_PKC_ACCESS_ERR_CLR_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_RESERVED31_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ @@ -62486,18 +55887,7 @@ typedef struct { #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) -/*! en_pdone - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=0). */ #define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) - -#define PKC_PKC_INT_CLR_ENABLE_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_CLR_ENABLE_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_CLR_ENABLE_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_RESERVED1_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_RESERVED1_MASK) - -#define PKC_PKC_INT_CLR_ENABLE_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_CLR_ENABLE_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_CLR_ENABLE_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_RESERVED31_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ @@ -62505,18 +55895,7 @@ typedef struct { #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) -/*! en_pdone - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=1). */ #define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) - -#define PKC_PKC_INT_SET_ENABLE_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_SET_ENABLE_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_SET_ENABLE_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_RESERVED1_SHIFT)) & PKC_PKC_INT_SET_ENABLE_RESERVED1_MASK) - -#define PKC_PKC_INT_SET_ENABLE_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_SET_ENABLE_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_SET_ENABLE_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_RESERVED31_SHIFT)) & PKC_PKC_INT_SET_ENABLE_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_STATUS - Interrupt status */ @@ -62524,22 +55903,8 @@ typedef struct { #define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) -/*! int_pdone - End-of-computation status flag: INT_PDONE is set after EACH single PKC L0 or L1 - * calculation. In case of a universal pointer calculation (L2) INT_PDONE is set at the end of the - * pipe calculation when PKC_ULEN has been decremented to zero and the final PKC calculation has - * completed. - */ +/*! INT_PDONE - End-of-computation status flag */ #define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) - -#define PKC_PKC_INT_STATUS_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_STATUS_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_STATUS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_RESERVED1_SHIFT)) & PKC_PKC_INT_STATUS_RESERVED1_MASK) - -#define PKC_PKC_INT_STATUS_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_STATUS_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_RESERVED31_SHIFT)) & PKC_PKC_INT_STATUS_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_ENABLE - Interrupt enable */ @@ -62547,20 +55912,8 @@ typedef struct { #define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) #define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) -/*! en_pdone - PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time - * PKC_INT_STATUS.INT_PDONE is set. Otherwise the interrupt generation is suppressed. - */ +/*! EN_PDONE - PDONE interrupt enable flag */ #define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) - -#define PKC_PKC_INT_ENABLE_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_ENABLE_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_ENABLE_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_RESERVED1_SHIFT)) & PKC_PKC_INT_ENABLE_RESERVED1_MASK) - -#define PKC_PKC_INT_ENABLE_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_ENABLE_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_ENABLE_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_RESERVED31_SHIFT)) & PKC_PKC_INT_ENABLE_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ @@ -62568,18 +55921,7 @@ typedef struct { #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) -/*! int_pdone - Write to clear End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=0). */ #define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) - -#define PKC_PKC_INT_CLR_STATUS_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_CLR_STATUS_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_CLR_STATUS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_RESERVED1_SHIFT)) & PKC_PKC_INT_CLR_STATUS_RESERVED1_MASK) - -#define PKC_PKC_INT_CLR_STATUS_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_CLR_STATUS_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_CLR_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_RESERVED31_SHIFT)) & PKC_PKC_INT_CLR_STATUS_RESERVED31_MASK) /*! @} */ /*! @name PKC_INT_SET_STATUS - Interrupt status set */ @@ -62587,20 +55929,7 @@ typedef struct { #define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) #define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) -/*! int_pdone - Write to set End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=1) to trigger - * a PKC interrupt via software, e.g. for debug purposes. - */ #define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) - -#define PKC_PKC_INT_SET_STATUS_RESERVED1_MASK (0x2U) -#define PKC_PKC_INT_SET_STATUS_RESERVED1_SHIFT (1U) -/*! reserved1 - reserved */ -#define PKC_PKC_INT_SET_STATUS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_RESERVED1_SHIFT)) & PKC_PKC_INT_SET_STATUS_RESERVED1_MASK) - -#define PKC_PKC_INT_SET_STATUS_RESERVED31_MASK (0xFFFFFFFCU) -#define PKC_PKC_INT_SET_STATUS_RESERVED31_SHIFT (2U) -/*! reserved31 - reserved */ -#define PKC_PKC_INT_SET_STATUS_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_RESERVED31_SHIFT)) & PKC_PKC_INT_SET_STATUS_RESERVED31_MASK) /*! @} */ /*! @name PKC_MODULE_ID - Module ID */ @@ -62608,22 +55937,18 @@ typedef struct { #define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) #define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) -/*! size - Address space of the IP */ #define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) #define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) #define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) -/*! minor_rev - Minor revision */ #define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) #define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) #define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) -/*! major_rev - Major revision */ #define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) #define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) #define PKC_PKC_MODULE_ID_ID_SHIFT (16U) -/*! id - Module ID */ #define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) /*! @} */ @@ -62923,7 +56248,7 @@ typedef struct { __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ uint8_t RESERVED_4[24]; - __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 23, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ + __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ } PORT_Type; /* ---------------------------------------------------------------------------- @@ -63317,14 +56642,6 @@ typedef struct { */ #define PORT_EDFR_EDF8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK) -#define PORT_EDFR_Reserved8_MASK (0x100U) -#define PORT_EDFR_Reserved8_SHIFT (8U) -/*! Reserved8 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved8_SHIFT)) & PORT_EDFR_Reserved8_MASK) - #define PORT_EDFR_EDF9_MASK (0x200U) #define PORT_EDFR_EDF9_SHIFT (9U) /*! EDF9 - EFT Detect Flag @@ -63333,14 +56650,6 @@ typedef struct { */ #define PORT_EDFR_EDF9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK) -#define PORT_EDFR_Reserved9_MASK (0x200U) -#define PORT_EDFR_Reserved9_SHIFT (9U) -/*! Reserved9 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved9_SHIFT)) & PORT_EDFR_Reserved9_MASK) - #define PORT_EDFR_EDF10_MASK (0x400U) #define PORT_EDFR_EDF10_SHIFT (10U) /*! EDF10 - EFT Detect Flag @@ -63349,14 +56658,6 @@ typedef struct { */ #define PORT_EDFR_EDF10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK) -#define PORT_EDFR_Reserved10_MASK (0x400U) -#define PORT_EDFR_Reserved10_SHIFT (10U) -/*! Reserved10 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved10_SHIFT)) & PORT_EDFR_Reserved10_MASK) - #define PORT_EDFR_EDF11_MASK (0x800U) #define PORT_EDFR_EDF11_SHIFT (11U) /*! EDF11 - EFT Detect Flag @@ -63365,14 +56666,6 @@ typedef struct { */ #define PORT_EDFR_EDF11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK) -#define PORT_EDFR_Reserved11_MASK (0x800U) -#define PORT_EDFR_Reserved11_SHIFT (11U) -/*! Reserved11 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved11_SHIFT)) & PORT_EDFR_Reserved11_MASK) - #define PORT_EDFR_EDF12_MASK (0x1000U) #define PORT_EDFR_EDF12_SHIFT (12U) /*! EDF12 - EFT Detect Flag @@ -63381,14 +56674,6 @@ typedef struct { */ #define PORT_EDFR_EDF12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK) -#define PORT_EDFR_Reserved12_MASK (0x1000U) -#define PORT_EDFR_Reserved12_SHIFT (12U) -/*! Reserved12 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved12_SHIFT)) & PORT_EDFR_Reserved12_MASK) - #define PORT_EDFR_EDF13_MASK (0x2000U) #define PORT_EDFR_EDF13_SHIFT (13U) /*! EDF13 - EFT Detect Flag @@ -63397,14 +56682,6 @@ typedef struct { */ #define PORT_EDFR_EDF13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK) -#define PORT_EDFR_Reserved13_MASK (0x2000U) -#define PORT_EDFR_Reserved13_SHIFT (13U) -/*! Reserved13 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved13_SHIFT)) & PORT_EDFR_Reserved13_MASK) - #define PORT_EDFR_EDF14_MASK (0x4000U) #define PORT_EDFR_EDF14_SHIFT (14U) /*! EDF14 - EFT Detect Flag @@ -63413,14 +56690,6 @@ typedef struct { */ #define PORT_EDFR_EDF14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK) -#define PORT_EDFR_Reserved14_MASK (0x4000U) -#define PORT_EDFR_Reserved14_SHIFT (14U) -/*! Reserved14 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved14_SHIFT)) & PORT_EDFR_Reserved14_MASK) - #define PORT_EDFR_EDF15_MASK (0x8000U) #define PORT_EDFR_EDF15_SHIFT (15U) /*! EDF15 - EFT Detect Flag @@ -63429,14 +56698,6 @@ typedef struct { */ #define PORT_EDFR_EDF15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK) -#define PORT_EDFR_Reserved15_MASK (0x8000U) -#define PORT_EDFR_Reserved15_SHIFT (15U) -/*! Reserved15 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved15_SHIFT)) & PORT_EDFR_Reserved15_MASK) - #define PORT_EDFR_EDF16_MASK (0x10000U) #define PORT_EDFR_EDF16_SHIFT (16U) /*! EDF16 - EFT Detect Flag @@ -63445,14 +56706,6 @@ typedef struct { */ #define PORT_EDFR_EDF16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK) -#define PORT_EDFR_Reserved16_MASK (0x10000U) -#define PORT_EDFR_Reserved16_SHIFT (16U) -/*! Reserved16 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved16_SHIFT)) & PORT_EDFR_Reserved16_MASK) - #define PORT_EDFR_EDF17_MASK (0x20000U) #define PORT_EDFR_EDF17_SHIFT (17U) /*! EDF17 - EFT Detect Flag @@ -63461,14 +56714,6 @@ typedef struct { */ #define PORT_EDFR_EDF17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK) -#define PORT_EDFR_Reserved17_MASK (0x20000U) -#define PORT_EDFR_Reserved17_SHIFT (17U) -/*! Reserved17 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved17_SHIFT)) & PORT_EDFR_Reserved17_MASK) - #define PORT_EDFR_EDF18_MASK (0x40000U) #define PORT_EDFR_EDF18_SHIFT (18U) /*! EDF18 - EFT Detect Flag @@ -63477,14 +56722,6 @@ typedef struct { */ #define PORT_EDFR_EDF18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK) -#define PORT_EDFR_Reserved18_MASK (0x40000U) -#define PORT_EDFR_Reserved18_SHIFT (18U) -/*! Reserved18 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved18_SHIFT)) & PORT_EDFR_Reserved18_MASK) - #define PORT_EDFR_EDF19_MASK (0x80000U) #define PORT_EDFR_EDF19_SHIFT (19U) /*! EDF19 - EFT Detect Flag @@ -63493,14 +56730,6 @@ typedef struct { */ #define PORT_EDFR_EDF19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK) -#define PORT_EDFR_Reserved19_MASK (0x80000U) -#define PORT_EDFR_Reserved19_SHIFT (19U) -/*! Reserved19 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved19_SHIFT)) & PORT_EDFR_Reserved19_MASK) - #define PORT_EDFR_EDF20_MASK (0x100000U) #define PORT_EDFR_EDF20_SHIFT (20U) /*! EDF20 - EFT Detect Flag @@ -63509,14 +56738,6 @@ typedef struct { */ #define PORT_EDFR_EDF20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK) -#define PORT_EDFR_Reserved20_MASK (0x100000U) -#define PORT_EDFR_Reserved20_SHIFT (20U) -/*! Reserved20 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved20_SHIFT)) & PORT_EDFR_Reserved20_MASK) - #define PORT_EDFR_EDF21_MASK (0x200000U) #define PORT_EDFR_EDF21_SHIFT (21U) /*! EDF21 - EFT Detect Flag @@ -63525,14 +56746,6 @@ typedef struct { */ #define PORT_EDFR_EDF21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK) -#define PORT_EDFR_Reserved21_MASK (0x200000U) -#define PORT_EDFR_Reserved21_SHIFT (21U) -/*! Reserved21 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved21_SHIFT)) & PORT_EDFR_Reserved21_MASK) - #define PORT_EDFR_EDF22_MASK (0x400000U) #define PORT_EDFR_EDF22_SHIFT (22U) /*! EDF22 - EFT Detect Flag @@ -63541,14 +56754,6 @@ typedef struct { */ #define PORT_EDFR_EDF22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK) -#define PORT_EDFR_Reserved22_MASK (0x400000U) -#define PORT_EDFR_Reserved22_SHIFT (22U) -/*! Reserved22 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved22_SHIFT)) & PORT_EDFR_Reserved22_MASK) - #define PORT_EDFR_EDF23_MASK (0x800000U) #define PORT_EDFR_EDF23_SHIFT (23U) /*! EDF23 - EFT Detect Flag @@ -63557,14 +56762,6 @@ typedef struct { */ #define PORT_EDFR_EDF23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK) -#define PORT_EDFR_Reserved23_MASK (0x800000U) -#define PORT_EDFR_Reserved23_SHIFT (23U) -/*! Reserved23 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved23_SHIFT)) & PORT_EDFR_Reserved23_MASK) - #define PORT_EDFR_EDF24_MASK (0x1000000U) #define PORT_EDFR_EDF24_SHIFT (24U) /*! EDF24 - EFT Detect Flag @@ -63573,14 +56770,6 @@ typedef struct { */ #define PORT_EDFR_EDF24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK) -#define PORT_EDFR_Reserved24_MASK (0x1000000U) -#define PORT_EDFR_Reserved24_SHIFT (24U) -/*! Reserved24 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved24_SHIFT)) & PORT_EDFR_Reserved24_MASK) - #define PORT_EDFR_EDF25_MASK (0x2000000U) #define PORT_EDFR_EDF25_SHIFT (25U) /*! EDF25 - EFT Detect Flag @@ -63589,14 +56778,6 @@ typedef struct { */ #define PORT_EDFR_EDF25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK) -#define PORT_EDFR_Reserved25_MASK (0x2000000U) -#define PORT_EDFR_Reserved25_SHIFT (25U) -/*! Reserved25 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved25_SHIFT)) & PORT_EDFR_Reserved25_MASK) - #define PORT_EDFR_EDF26_MASK (0x4000000U) #define PORT_EDFR_EDF26_SHIFT (26U) /*! EDF26 - EFT Detect Flag @@ -63605,14 +56786,6 @@ typedef struct { */ #define PORT_EDFR_EDF26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK) -#define PORT_EDFR_Reserved26_MASK (0x4000000U) -#define PORT_EDFR_Reserved26_SHIFT (26U) -/*! Reserved26 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved26_SHIFT)) & PORT_EDFR_Reserved26_MASK) - #define PORT_EDFR_EDF27_MASK (0x8000000U) #define PORT_EDFR_EDF27_SHIFT (27U) /*! EDF27 - EFT Detect Flag @@ -63621,14 +56794,6 @@ typedef struct { */ #define PORT_EDFR_EDF27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK) -#define PORT_EDFR_Reserved27_MASK (0x8000000U) -#define PORT_EDFR_Reserved27_SHIFT (27U) -/*! Reserved27 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved27_SHIFT)) & PORT_EDFR_Reserved27_MASK) - #define PORT_EDFR_EDF28_MASK (0x10000000U) #define PORT_EDFR_EDF28_SHIFT (28U) /*! EDF28 - EFT Detect Flag @@ -63637,14 +56802,6 @@ typedef struct { */ #define PORT_EDFR_EDF28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK) -#define PORT_EDFR_Reserved28_MASK (0x10000000U) -#define PORT_EDFR_Reserved28_SHIFT (28U) -/*! Reserved28 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved28_SHIFT)) & PORT_EDFR_Reserved28_MASK) - #define PORT_EDFR_EDF29_MASK (0x20000000U) #define PORT_EDFR_EDF29_SHIFT (29U) /*! EDF29 - EFT Detect Flag @@ -63653,14 +56810,6 @@ typedef struct { */ #define PORT_EDFR_EDF29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK) -#define PORT_EDFR_Reserved29_MASK (0x20000000U) -#define PORT_EDFR_Reserved29_SHIFT (29U) -/*! Reserved29 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved29_SHIFT)) & PORT_EDFR_Reserved29_MASK) - #define PORT_EDFR_EDF30_MASK (0x40000000U) #define PORT_EDFR_EDF30_SHIFT (30U) /*! EDF30 - EFT Detect Flag @@ -63669,14 +56818,6 @@ typedef struct { */ #define PORT_EDFR_EDF30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK) -#define PORT_EDFR_Reserved30_MASK (0x40000000U) -#define PORT_EDFR_Reserved30_SHIFT (30U) -/*! Reserved30 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved30_SHIFT)) & PORT_EDFR_Reserved30_MASK) - #define PORT_EDFR_EDF31_MASK (0x80000000U) #define PORT_EDFR_EDF31_SHIFT (31U) /*! EDF31 - EFT Detect Flag @@ -63684,14 +56825,6 @@ typedef struct { * 0b1..High or/and low EFT event detected */ #define PORT_EDFR_EDF31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK) - -#define PORT_EDFR_Reserved31_MASK (0x80000000U) -#define PORT_EDFR_Reserved31_SHIFT (31U) -/*! Reserved31 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDFR_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved31_SHIFT)) & PORT_EDFR_Reserved31_MASK) /*! @} */ /*! @name EDIER - EFT Detect Interrupt Enable */ @@ -63769,14 +56902,6 @@ typedef struct { */ #define PORT_EDIER_EDIE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK) -#define PORT_EDIER_Reserved8_MASK (0x100U) -#define PORT_EDIER_Reserved8_SHIFT (8U) -/*! Reserved8 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved8_SHIFT)) & PORT_EDIER_Reserved8_MASK) - #define PORT_EDIER_EDIE9_MASK (0x200U) #define PORT_EDIER_EDIE9_SHIFT (9U) /*! EDIE9 - EFT Detect Interrupt Enable @@ -63785,14 +56910,6 @@ typedef struct { */ #define PORT_EDIER_EDIE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK) -#define PORT_EDIER_Reserved9_MASK (0x200U) -#define PORT_EDIER_Reserved9_SHIFT (9U) -/*! Reserved9 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved9_SHIFT)) & PORT_EDIER_Reserved9_MASK) - #define PORT_EDIER_EDIE10_MASK (0x400U) #define PORT_EDIER_EDIE10_SHIFT (10U) /*! EDIE10 - EFT Detect Interrupt Enable @@ -63801,14 +56918,6 @@ typedef struct { */ #define PORT_EDIER_EDIE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK) -#define PORT_EDIER_Reserved10_MASK (0x400U) -#define PORT_EDIER_Reserved10_SHIFT (10U) -/*! Reserved10 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved10_SHIFT)) & PORT_EDIER_Reserved10_MASK) - #define PORT_EDIER_EDIE11_MASK (0x800U) #define PORT_EDIER_EDIE11_SHIFT (11U) /*! EDIE11 - EFT Detect Interrupt Enable @@ -63817,14 +56926,6 @@ typedef struct { */ #define PORT_EDIER_EDIE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK) -#define PORT_EDIER_Reserved11_MASK (0x800U) -#define PORT_EDIER_Reserved11_SHIFT (11U) -/*! Reserved11 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved11_SHIFT)) & PORT_EDIER_Reserved11_MASK) - #define PORT_EDIER_EDIE12_MASK (0x1000U) #define PORT_EDIER_EDIE12_SHIFT (12U) /*! EDIE12 - EFT Detect Interrupt Enable @@ -63833,14 +56934,6 @@ typedef struct { */ #define PORT_EDIER_EDIE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK) -#define PORT_EDIER_Reserved12_MASK (0x1000U) -#define PORT_EDIER_Reserved12_SHIFT (12U) -/*! Reserved12 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved12_SHIFT)) & PORT_EDIER_Reserved12_MASK) - #define PORT_EDIER_EDIE13_MASK (0x2000U) #define PORT_EDIER_EDIE13_SHIFT (13U) /*! EDIE13 - EFT Detect Interrupt Enable @@ -63849,14 +56942,6 @@ typedef struct { */ #define PORT_EDIER_EDIE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK) -#define PORT_EDIER_Reserved13_MASK (0x2000U) -#define PORT_EDIER_Reserved13_SHIFT (13U) -/*! Reserved13 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved13_SHIFT)) & PORT_EDIER_Reserved13_MASK) - #define PORT_EDIER_EDIE14_MASK (0x4000U) #define PORT_EDIER_EDIE14_SHIFT (14U) /*! EDIE14 - EFT Detect Interrupt Enable @@ -63865,14 +56950,6 @@ typedef struct { */ #define PORT_EDIER_EDIE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK) -#define PORT_EDIER_Reserved14_MASK (0x4000U) -#define PORT_EDIER_Reserved14_SHIFT (14U) -/*! Reserved14 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved14_SHIFT)) & PORT_EDIER_Reserved14_MASK) - #define PORT_EDIER_EDIE15_MASK (0x8000U) #define PORT_EDIER_EDIE15_SHIFT (15U) /*! EDIE15 - EFT Detect Interrupt Enable @@ -63881,14 +56958,6 @@ typedef struct { */ #define PORT_EDIER_EDIE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK) -#define PORT_EDIER_Reserved15_MASK (0x8000U) -#define PORT_EDIER_Reserved15_SHIFT (15U) -/*! Reserved15 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved15_SHIFT)) & PORT_EDIER_Reserved15_MASK) - #define PORT_EDIER_EDIE16_MASK (0x10000U) #define PORT_EDIER_EDIE16_SHIFT (16U) /*! EDIE16 - EFT Detect Interrupt Enable @@ -63897,14 +56966,6 @@ typedef struct { */ #define PORT_EDIER_EDIE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK) -#define PORT_EDIER_Reserved16_MASK (0x10000U) -#define PORT_EDIER_Reserved16_SHIFT (16U) -/*! Reserved16 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved16_SHIFT)) & PORT_EDIER_Reserved16_MASK) - #define PORT_EDIER_EDIE17_MASK (0x20000U) #define PORT_EDIER_EDIE17_SHIFT (17U) /*! EDIE17 - EFT Detect Interrupt Enable @@ -63913,14 +56974,6 @@ typedef struct { */ #define PORT_EDIER_EDIE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK) -#define PORT_EDIER_Reserved17_MASK (0x20000U) -#define PORT_EDIER_Reserved17_SHIFT (17U) -/*! Reserved17 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved17_SHIFT)) & PORT_EDIER_Reserved17_MASK) - #define PORT_EDIER_EDIE18_MASK (0x40000U) #define PORT_EDIER_EDIE18_SHIFT (18U) /*! EDIE18 - EFT Detect Interrupt Enable @@ -63929,14 +56982,6 @@ typedef struct { */ #define PORT_EDIER_EDIE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK) -#define PORT_EDIER_Reserved18_MASK (0x40000U) -#define PORT_EDIER_Reserved18_SHIFT (18U) -/*! Reserved18 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved18_SHIFT)) & PORT_EDIER_Reserved18_MASK) - #define PORT_EDIER_EDIE19_MASK (0x80000U) #define PORT_EDIER_EDIE19_SHIFT (19U) /*! EDIE19 - EFT Detect Interrupt Enable @@ -63945,14 +56990,6 @@ typedef struct { */ #define PORT_EDIER_EDIE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK) -#define PORT_EDIER_Reserved19_MASK (0x80000U) -#define PORT_EDIER_Reserved19_SHIFT (19U) -/*! Reserved19 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved19_SHIFT)) & PORT_EDIER_Reserved19_MASK) - #define PORT_EDIER_EDIE20_MASK (0x100000U) #define PORT_EDIER_EDIE20_SHIFT (20U) /*! EDIE20 - EFT Detect Interrupt Enable @@ -63961,14 +56998,6 @@ typedef struct { */ #define PORT_EDIER_EDIE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK) -#define PORT_EDIER_Reserved20_MASK (0x100000U) -#define PORT_EDIER_Reserved20_SHIFT (20U) -/*! Reserved20 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved20_SHIFT)) & PORT_EDIER_Reserved20_MASK) - #define PORT_EDIER_EDIE21_MASK (0x200000U) #define PORT_EDIER_EDIE21_SHIFT (21U) /*! EDIE21 - EFT Detect Interrupt Enable @@ -63977,14 +57006,6 @@ typedef struct { */ #define PORT_EDIER_EDIE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK) -#define PORT_EDIER_Reserved21_MASK (0x200000U) -#define PORT_EDIER_Reserved21_SHIFT (21U) -/*! Reserved21 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved21_SHIFT)) & PORT_EDIER_Reserved21_MASK) - #define PORT_EDIER_EDIE22_MASK (0x400000U) #define PORT_EDIER_EDIE22_SHIFT (22U) /*! EDIE22 - EFT Detect Interrupt Enable @@ -63993,14 +57014,6 @@ typedef struct { */ #define PORT_EDIER_EDIE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK) -#define PORT_EDIER_Reserved22_MASK (0x400000U) -#define PORT_EDIER_Reserved22_SHIFT (22U) -/*! Reserved22 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved22_SHIFT)) & PORT_EDIER_Reserved22_MASK) - #define PORT_EDIER_EDIE23_MASK (0x800000U) #define PORT_EDIER_EDIE23_SHIFT (23U) /*! EDIE23 - EFT Detect Interrupt Enable @@ -64009,14 +57022,6 @@ typedef struct { */ #define PORT_EDIER_EDIE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK) -#define PORT_EDIER_Reserved23_MASK (0x800000U) -#define PORT_EDIER_Reserved23_SHIFT (23U) -/*! Reserved23 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved23_SHIFT)) & PORT_EDIER_Reserved23_MASK) - #define PORT_EDIER_EDIE24_MASK (0x1000000U) #define PORT_EDIER_EDIE24_SHIFT (24U) /*! EDIE24 - EFT Detect Interrupt Enable @@ -64025,14 +57030,6 @@ typedef struct { */ #define PORT_EDIER_EDIE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK) -#define PORT_EDIER_Reserved24_MASK (0x1000000U) -#define PORT_EDIER_Reserved24_SHIFT (24U) -/*! Reserved24 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved24_SHIFT)) & PORT_EDIER_Reserved24_MASK) - #define PORT_EDIER_EDIE25_MASK (0x2000000U) #define PORT_EDIER_EDIE25_SHIFT (25U) /*! EDIE25 - EFT Detect Interrupt Enable @@ -64041,14 +57038,6 @@ typedef struct { */ #define PORT_EDIER_EDIE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK) -#define PORT_EDIER_Reserved25_MASK (0x2000000U) -#define PORT_EDIER_Reserved25_SHIFT (25U) -/*! Reserved25 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved25_SHIFT)) & PORT_EDIER_Reserved25_MASK) - #define PORT_EDIER_EDIE26_MASK (0x4000000U) #define PORT_EDIER_EDIE26_SHIFT (26U) /*! EDIE26 - EFT Detect Interrupt Enable @@ -64057,14 +57046,6 @@ typedef struct { */ #define PORT_EDIER_EDIE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK) -#define PORT_EDIER_Reserved26_MASK (0x4000000U) -#define PORT_EDIER_Reserved26_SHIFT (26U) -/*! Reserved26 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved26_SHIFT)) & PORT_EDIER_Reserved26_MASK) - #define PORT_EDIER_EDIE27_MASK (0x8000000U) #define PORT_EDIER_EDIE27_SHIFT (27U) /*! EDIE27 - EFT Detect Interrupt Enable @@ -64073,14 +57054,6 @@ typedef struct { */ #define PORT_EDIER_EDIE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK) -#define PORT_EDIER_Reserved27_MASK (0x8000000U) -#define PORT_EDIER_Reserved27_SHIFT (27U) -/*! Reserved27 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved27_SHIFT)) & PORT_EDIER_Reserved27_MASK) - #define PORT_EDIER_EDIE28_MASK (0x10000000U) #define PORT_EDIER_EDIE28_SHIFT (28U) /*! EDIE28 - EFT Detect Interrupt Enable @@ -64089,14 +57062,6 @@ typedef struct { */ #define PORT_EDIER_EDIE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK) -#define PORT_EDIER_Reserved28_MASK (0x10000000U) -#define PORT_EDIER_Reserved28_SHIFT (28U) -/*! Reserved28 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved28_SHIFT)) & PORT_EDIER_Reserved28_MASK) - #define PORT_EDIER_EDIE29_MASK (0x20000000U) #define PORT_EDIER_EDIE29_SHIFT (29U) /*! EDIE29 - EFT Detect Interrupt Enable @@ -64105,14 +57070,6 @@ typedef struct { */ #define PORT_EDIER_EDIE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK) -#define PORT_EDIER_Reserved29_MASK (0x20000000U) -#define PORT_EDIER_Reserved29_SHIFT (29U) -/*! Reserved29 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved29_SHIFT)) & PORT_EDIER_Reserved29_MASK) - #define PORT_EDIER_EDIE30_MASK (0x40000000U) #define PORT_EDIER_EDIE30_SHIFT (30U) /*! EDIE30 - EFT Detect Interrupt Enable @@ -64121,14 +57078,6 @@ typedef struct { */ #define PORT_EDIER_EDIE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK) -#define PORT_EDIER_Reserved30_MASK (0x40000000U) -#define PORT_EDIER_Reserved30_SHIFT (30U) -/*! Reserved30 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved30_SHIFT)) & PORT_EDIER_Reserved30_MASK) - #define PORT_EDIER_EDIE31_MASK (0x80000000U) #define PORT_EDIER_EDIE31_SHIFT (31U) /*! EDIE31 - EFT Detect Interrupt Enable @@ -64136,14 +57085,6 @@ typedef struct { * 0b1..Interrupt generated upon detection of the EFT event */ #define PORT_EDIER_EDIE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK) - -#define PORT_EDIER_Reserved31_MASK (0x80000000U) -#define PORT_EDIER_Reserved31_SHIFT (31U) -/*! Reserved31 - Reserved - * 0b0..Not supported - * 0b1..Not supported - */ -#define PORT_EDIER_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved31_SHIFT)) & PORT_EDIER_Reserved31_MASK) /*! @} */ /*! @name EDCR - EFT Detect Clear */ @@ -64194,7 +57135,7 @@ typedef struct { #define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) /*! @} */ -/*! @name PCR - Pin Control 0..Pin Control 23 */ +/*! @name PCR - Pin Control 0..Pin Control 31 */ /*! @{ */ #define PORT_PCR_PS_MASK (0x1U) @@ -64253,7 +57194,7 @@ typedef struct { */ #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) -#define PORT_PCR_MUX_MASK (0xF00U) +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define PORT_PCR_MUX_SHIFT (8U) /*! MUX - Pin Multiplex Control * 0b0000..Alternative 0 (GPIO) @@ -64271,7 +57212,7 @@ typedef struct { * 0b1100..Alternative 12 (chip-specific) * 0b1101..Alternative 13 (chip-specific) */ -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define PORT_PCR_IBE_MASK (0x1000U) #define PORT_PCR_IBE_SHIFT (12U) @@ -64416,20 +57357,20 @@ typedef struct { __IO uint32_t OUTFORMAT; /**< Output Format, offset: 0x4 */ __IO uint32_t TMPBASE; /**< Temporary Base, offset: 0x8 */ __IO uint32_t TMPFORMAT; /**< Temporary Format, offset: 0xC */ - __IO uint32_t INABASE; /**< Input A base, offset: 0x10 */ - __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ - __IO uint32_t INBBASE; /**< Input B base, offset: 0x18 */ - __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + __IO uint32_t INABASE; /**< Input A Base, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A Format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Input B Base, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B Format, offset: 0x1C */ uint8_t RESERVED_0[224]; __IO uint32_t CONTROL; /**< Control, offset: 0x100 */ __IO uint32_t LENGTH; /**< Length, offset: 0x104 */ - __IO uint32_t CPPRE; /**< Coprocessor Pre-scale, offset: 0x108 */ + __IO uint32_t CPPRE; /**< Coprocessor Prescale, offset: 0x108 */ __IO uint32_t MISC; /**< Miscellaneous, offset: 0x10C */ __IO uint32_t CURSORY; /**< Cursory, offset: 0x110 */ uint8_t RESERVED_1[108]; - __IO uint32_t CORDIC_X; /**< CORDIC input X, offset: 0x180 */ - __IO uint32_t CORDIC_Y; /**< CORDIC input Y, offset: 0x184 */ - __IO uint32_t CORDIC_Z; /**< CORDIC input Z, offset: 0x188 */ + __IO uint32_t CORDIC_X; /**< CORDIC Input X, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< CORDIC Input Y, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< CORDIC Input Z, offset: 0x188 */ __IO uint32_t ERRSTAT; /**< Error Status, offset: 0x18C */ __IO uint32_t INTREN; /**< Interrupt Enable, offset: 0x190 */ __IO uint32_t EVENTEN; /**< Event Enable, offset: 0x194 */ @@ -64453,7 +57394,7 @@ typedef struct { #define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) -/*! OUTBASE - Base address for the output region */ +/*! OUTBASE - Output Region Base Address */ #define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) /*! @} */ @@ -64462,25 +57403,27 @@ typedef struct { #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) -/*! OUT_FORMATINT - Output internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! OUT_FORMATINT - Output Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) -/*! OUT_FORMATEXT - Output external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! OUT_FORMATEXT - Output External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) -/*! OUT_SCALER - Output scaler value */ +/*! OUT_SCALER - 8-bit Scaling Value for Result Data */ #define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) /*! @} */ @@ -64489,7 +57432,7 @@ typedef struct { #define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) -/*! TMPBASE - Base address for the temporary region */ +/*! TMPBASE - Base Address for the Temporary Region */ #define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) /*! @} */ @@ -64498,97 +57441,103 @@ typedef struct { #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) -/*! TMP_FORMATINT - Temporary internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! TMP_FORMATINT - Temporary Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) -/*! TMP_FORMATEXT - Temporary external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! TMP_FORMATEXT - Temporary External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) -/*! TMP_SCALER - Temporary scaler value */ +/*! TMP_SCALER - Scaling Value for Temporary Data. */ #define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) /*! @} */ -/*! @name INABASE - Input A base */ +/*! @name INABASE - Input A Base */ /*! @{ */ #define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INABASE_INABASE_SHIFT (0U) -/*! INABASE - Input A base */ +/*! INABASE - Input A Base */ #define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) /*! @} */ -/*! @name INAFORMAT - Input A format */ +/*! @name INAFORMAT - Input A Format */ /*! @{ */ #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) -/*! INA_FORMATINT - Input A internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INA_FORMATINT - Input A Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) -/*! INA_FORMATEXT - Input A external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INA_FORMATEXT - Input A External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) #define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) -/*! INA_SCALER - Input A scaler value */ +/*! INA_SCALER - Input A Scaler Value */ #define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) /*! @} */ -/*! @name INBBASE - Input B base */ +/*! @name INBBASE - Input B Base */ /*! @{ */ #define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) -/*! INBBASE - Input B base */ +/*! INBBASE - Input B Base */ #define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) /*! @} */ -/*! @name INBFORMAT - Input B format */ +/*! @name INBFORMAT - Input B Format */ /*! @{ */ #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) -/*! INB_FORMATINT - Input B internal format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INB_FORMATINT - Input B Internal Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) -/*! INB_FORMATEXT - Input B external format - * 0b00..q15 - * 0b01..q31 - * 0b10..float +/*! INB_FORMATEXT - Input B External Format + * 0b00..Q15 16-bit fixed-point integer + * 0b01..Q31 32-bit fixed-point integer + * 0b10..F32 32-bit floating-point format + * 0b11.. */ #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) #define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) -/*! INB_SCALER - Input B scaler value */ +/*! INB_SCALER - Input B Scaler */ #define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) /*! @} */ @@ -64597,18 +57546,25 @@ typedef struct { #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) -/*! DECODE_OPCODE - Decode opcode */ +/*! DECODE_OPCODE - Decode Opcode */ #define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) -/*! DECODE_MACHINE - Decode machine */ +/*! DECODE_MACHINE - Decode Machine + * 0b0000..Coprocessor + * 0b0001..Matrix engine + * 0b0010..Transform engine + * 0b0011..Filter engine + * 0b0101..CORDIC engine + * 0b0100, 0b0110-0b1111.. + */ #define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) #define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) #define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) -/*! INST_BUSY - Instruction busy - * 0b1..busy +/*! INST_BUSY - Instruction Busy + * 0b1..Busy * 0b0..Not busy */ #define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) @@ -64623,17 +57579,17 @@ typedef struct { #define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) /*! @} */ -/*! @name CPPRE - Coprocessor Pre-scale */ +/*! @name CPPRE - Coprocessor Prescale */ /*! @{ */ #define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) -/*! CPPRE_IN - Input */ +/*! CPPRE_IN - Prescaling Input */ #define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) #define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) -/*! CPPRE_OUT - Output */ +/*! CPPRE_OUT - Postscaling Output */ #define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) #define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) @@ -64658,7 +57614,7 @@ typedef struct { #define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) #define POWERQUAD_MISC_INST_MISC_SHIFT (0U) -/*! INST_MISC - For matrix operations used for scaling factor */ +/*! INST_MISC - Scaling Factor */ #define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) /*! @} */ @@ -64668,36 +57624,36 @@ typedef struct { #define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) #define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) /*! CURSORY - Cursory Mode - * 0b0..Disable cursory mode - * 0b1..Enable cursory Mode + * 0b0..Disable cursory mode, full floating-point accuracy (24-bit mantissa + 2 bits before rounding). + * 0b1..Enable cursory Mode, 16-bit mantissa (bottom bits are zeroed for inputs and outputs of MACs). */ #define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) /*! @} */ -/*! @name CORDIC_X - CORDIC input X */ +/*! @name CORDIC_X - CORDIC Input X */ /*! @{ */ #define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) -/*! CORDIC_X - CORDIC input x */ +/*! CORDIC_X - CORDIC Input X */ #define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) /*! @} */ -/*! @name CORDIC_Y - CORDIC input Y */ +/*! @name CORDIC_Y - CORDIC Input Y */ /*! @{ */ #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) -/*! CORDIC_Y - CORDIC input y */ +/*! CORDIC_Y - CORDIC Input Y */ #define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) /*! @} */ -/*! @name CORDIC_Z - CORDIC input Z */ +/*! @name CORDIC_Z - CORDIC Input Z */ /*! @{ */ #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) -/*! CORDIC_Z - CORDIC input z */ +/*! CORDIC_Z - CORDIC Input Z */ #define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) /*! @} */ @@ -64706,25 +57662,25 @@ typedef struct { #define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) -/*! OVERFLOW - Floating point overflow +/*! OVERFLOW - Floating-point Overflow * 0b0..No error - * 0b1..Error on floating point overflow + * 0b1..Error on floating-point overflow */ #define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) #define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) #define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) -/*! NAN - Floating Point NaN +/*! NAN - Floating-Point Not-a-Number (NaN) * 0b0..No error - * 0b1..Error on Floating Point NaN + * 0b1..Error on floating-point NaN */ #define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) -/*! FIXEDOVERFLOW - Fixed point overflow +/*! FIXEDOVERFLOW - Fixed-point Overflow * 0b0..No error - * 0b1..Error on fixed point overflow + * 0b1..Error on fixed-point overflow */ #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) @@ -64738,7 +57694,7 @@ typedef struct { #define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) -/*! BUSERROR - Bus error +/*! BUSERROR - Bus Error * 0b0..No error * 0b1..Error on bus */ @@ -64750,7 +57706,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) -/*! INTR_OFLOW - Interrupt floating point overflow +/*! INTR_OFLOW - Interrupt Floating-point Overflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64758,7 +57714,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) #define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) -/*! INTR_NAN - Interrupt floating point NaN +/*! INTR_NAN - Interrupt Floating-point NaN * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64766,7 +57722,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) #define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) -/*! INTR_FIXED - Interrupt on fixed-point overflow +/*! INTR_FIXED - Interrupt on Fixed-point Overflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64774,7 +57730,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) -/*! INTR_UFLOW - Interrupt on subnormal truncation +/*! INTR_UFLOW - Interrupt on Underflow * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64782,7 +57738,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) #define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) -/*! INTR_BERR - Interrupt on AHBM bus error +/*! INTR_BERR - Interrupt on AHBM Bus Error * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64790,7 +57746,7 @@ typedef struct { #define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) #define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) -/*! INTR_COMP - Interrupt on instruction completion +/*! INTR_COMP - Interrupt on Instruction Completion * 0b0..Disable interrupt * 0b1..Enable interrupt */ @@ -64802,7 +57758,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) -/*! EVENT_OFLOW - Event trigger on floating point overflow +/*! EVENT_OFLOW - Event Trigger on Floating-point Overflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64810,7 +57766,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) -/*! EVENT_NAN - Event trigger on floating point NaN +/*! EVENT_NAN - Event Trigger on Floating-Point NaN * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64818,7 +57774,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) -/*! EVENT_FIXED - Event trigger on fixed-point overflow +/*! EVENT_FIXED - Event Trigger on Fixed-point Overflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64826,7 +57782,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) -/*! EVENT_UFLOW - Event trigger on subnormal truncation +/*! EVENT_UFLOW - Event Trigger on Underflow * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64834,7 +57790,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) -/*! EVENT_BERR - Event trigger on AHBM bus error +/*! EVENT_BERR - Event Trigger on AHBM Bus Error * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64842,7 +57798,7 @@ typedef struct { #define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) -/*! EVENT_COMP - Event trigger on instruction completion +/*! EVENT_COMP - Event Trigger on Instruction Completion * 0b0..Disable event trigger * 0b1..Enable event trigger */ @@ -64919,6 +57875,8 @@ typedef struct { /** Array initializer of POWERQUAD peripheral base pointers */ #define POWERQUAD_BASE_PTRS { POWERQUAD } #endif +/** Interrupt vectors for the POWERQUAD peripheral type */ +#define POWERQUAD_IRQS { PQ_IRQn } /*! * @} @@ -64962,7 +57920,10 @@ typedef struct { __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ - uint8_t RESERVED_7[512]; + __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ + __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ + __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ + uint8_t RESERVED_7[500]; __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ uint8_t RESERVED_8[208]; @@ -65157,8 +58118,8 @@ typedef struct { #define PUF_AR_ALLOW_STOP_MASK (0x20U) #define PUF_AR_ALLOW_STOP_SHIFT (5U) /*! ALLOW_STOP - Stop operation - * 0b1..Indicates that the Stop operation is allowed * 0b0..Indicates that the Stop operation is not allowed + * 0b1..Indicates that the Stop operation is allowed */ #define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) @@ -65484,22 +58445,136 @@ typedef struct { #define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) /*! @} */ +/*! @name CONFIG - PUF command blocking configuration */ +/*! @{ */ + +#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) +#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) +/*! DIS_PUF_ENROLL - Disable PUF enroll command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) + +#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) +#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) +/*! DIS_PUF_START - Disable PUF start command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) + +#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) +#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) +/*! DIS_PUF_STOP - Disable PUF stop command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) + +#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) +#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) +/*! DIS_PUF_GET_KEY - Disable PUF get key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) +/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) +/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) +/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) +/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) + +#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) +#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) +/*! DIS_PUF_TEST - Disable PUF test command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) +/*! @} */ + +/*! @name SEC_LOCK - Security level lock */ +/*! @{ */ + +#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) +#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) +/*! SEC_LEVEL - Security Level + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) +/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) +#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Pattern */ +#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name APP_CTX_MASK - Application defined context mask */ +/*! @{ */ + +#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) +#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) +/*! APP_CTX_MASK - Application defined context */ +#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) +/*! @} */ + /*! @name SRAM_CFG - SRAM Configuration */ /*! @{ */ #define PUF_SRAM_CFG_ENABLE_MASK (0x1U) #define PUF_SRAM_CFG_ENABLE_SHIFT (0U) /*! ENABLE - PUF SRAM Controller activation + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) #define PUF_SRAM_CFG_CKGATING_MASK (0x4U) #define PUF_SRAM_CFG_CKGATING_SHIFT (2U) /*! CKGATING - PUF SRAM Clock Gating control + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) /*! @} */ @@ -65561,16 +58636,16 @@ typedef struct { #define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) #define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) /*! READY - READY Interrupt Enable + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) /*! SRAM_APB_ERR - APB_ERR Interrupt Enable + * 0b0..Disabled * 0b1..Enabled - * 0b1..Disabled */ #define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) /*! @} */ @@ -65685,222 +58760,6 @@ typedef struct { */ /* end of group PUF_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- PUF_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_CTRL_Peripheral_Access_Layer PUF_CTRL Peripheral Access Layer - * @{ - */ - -/** PUF_CTRL - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[256]; - __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ - __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ - __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ -} PUF_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- PUF_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PUF_CTRL_Register_Masks PUF_CTRL Register Masks - * @{ - */ - -/*! @name CONFIG - PUF command blocking configuration */ -/*! @{ */ - -#define PUF_CTRL_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) -#define PUF_CTRL_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) -/*! DIS_PUF_ENROLL - Disable PUF enroll command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_ENROLL_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_START_MASK (0x4U) -#define PUF_CTRL_CONFIG_DIS_PUF_START_SHIFT (2U) -/*! DIS_PUF_START - Disable PUF start command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_START_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_STOP_MASK (0x20U) -#define PUF_CTRL_CONFIG_DIS_PUF_STOP_SHIFT (5U) -/*! DIS_PUF_STOP - Disable PUF stop command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_STOP_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) -#define PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) -/*! DIS_PUF_GET_KEY - Disable PUF get key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_GET_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) -#define PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) -/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) -/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) -#define PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) -/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_WRAP_KEY_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) -/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) - -#define PUF_CTRL_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) -#define PUF_CTRL_CONFIG_DIS_PUF_TEST_SHIFT (31U) -/*! DIS_PUF_TEST - Disable PUF test command - * 0b0..Command enabled - * 0b1..Command disabled - */ -#define PUF_CTRL_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CTRL_CONFIG_DIS_PUF_TEST_MASK) -/*! @} */ - -/*! @name SEC_LOCK - Security level lock */ -/*! @{ */ - -#define PUF_CTRL_SEC_LOCK_SEC_LEVEL_MASK (0x3U) -#define PUF_CTRL_SEC_LOCK_SEC_LEVEL_SHIFT (0U) -/*! SEC_LEVEL - Security Level - * 0b00..Non-secure and non-privileged Master - * 0b01..Non-secure and privileged Master - * 0b10..Secure and non-privileged Master - * 0b11..Secure and privileged Master - */ -#define PUF_CTRL_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_CTRL_SEC_LOCK_SEC_LEVEL_MASK) - -#define PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) -#define PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) -/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level - * 0b00..Secure and privileged Master - * 0b01..Secure and non-privileged Master - * 0b10..Non-secure and privileged Master - * 0b11..Non-secure and non-privileged Master - */ -#define PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_CTRL_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) - -#define PUF_CTRL_SEC_LOCK_PATTERN_MASK (0xFFF0U) -#define PUF_CTRL_SEC_LOCK_PATTERN_SHIFT (4U) -/*! PATTERN - Pattern */ -#define PUF_CTRL_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SEC_LOCK_PATTERN_SHIFT)) & PUF_CTRL_SEC_LOCK_PATTERN_MASK) -/*! @} */ - -/*! @name APP_CTX_MASK - Application defined context mask */ -/*! @{ */ - -#define PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) -#define PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) -/*! APP_CTX_MASK - Application defined context */ -#define PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_CTRL_APP_CTX_MASK_APP_CTX_MASK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PUF_CTRL_Register_Masks */ - - -/* PUF_CTRL - Peripheral instance base addresses */ -#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral PUF_CTRL base address */ - #define PUF_CTRL_BASE (0x5002C000u) - /** Peripheral PUF_CTRL base address */ - #define PUF_CTRL_BASE_NS (0x4002C000u) - /** Peripheral PUF_CTRL base pointer */ - #define PUF_CTRL ((PUF_CTRL_Type *)PUF_CTRL_BASE) - /** Peripheral PUF_CTRL base pointer */ - #define PUF_CTRL_NS ((PUF_CTRL_Type *)PUF_CTRL_BASE_NS) - /** Peripheral PUF_CTRL_ALIAS1 base address */ - #define PUF_CTRL_ALIAS1_BASE (0x5002D000u) - /** Peripheral PUF_CTRL_ALIAS1 base address */ - #define PUF_CTRL_ALIAS1_BASE_NS (0x4002D000u) - /** Peripheral PUF_CTRL_ALIAS1 base pointer */ - #define PUF_CTRL_ALIAS1 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS1_BASE) - /** Peripheral PUF_CTRL_ALIAS1 base pointer */ - #define PUF_CTRL_ALIAS1_NS ((PUF_CTRL_Type *)PUF_CTRL_ALIAS1_BASE_NS) - /** Peripheral PUF_CTRL_ALIAS2 base address */ - #define PUF_CTRL_ALIAS2_BASE (0x5002E000u) - /** Peripheral PUF_CTRL_ALIAS2 base address */ - #define PUF_CTRL_ALIAS2_BASE_NS (0x4002E000u) - /** Peripheral PUF_CTRL_ALIAS2 base pointer */ - #define PUF_CTRL_ALIAS2 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS2_BASE) - /** Peripheral PUF_CTRL_ALIAS2 base pointer */ - #define PUF_CTRL_ALIAS2_NS ((PUF_CTRL_Type *)PUF_CTRL_ALIAS2_BASE_NS) - /** Peripheral PUF_CTRL_ALIAS3 base address */ - #define PUF_CTRL_ALIAS3_BASE (0x5002F000u) - /** Peripheral PUF_CTRL_ALIAS3 base address */ - #define PUF_CTRL_ALIAS3_BASE_NS (0x4002F000u) - /** Peripheral PUF_CTRL_ALIAS3 base pointer */ - #define PUF_CTRL_ALIAS3 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS3_BASE) - /** Peripheral PUF_CTRL_ALIAS3 base pointer */ - #define PUF_CTRL_ALIAS3_NS ((PUF_CTRL_Type *)PUF_CTRL_ALIAS3_BASE_NS) - /** Array initializer of PUF_CTRL peripheral base addresses */ - #define PUF_CTRL_BASE_ADDRS { PUF_CTRL_BASE, PUF_CTRL_ALIAS1_BASE, PUF_CTRL_ALIAS2_BASE, PUF_CTRL_ALIAS3_BASE } - /** Array initializer of PUF_CTRL peripheral base pointers */ - #define PUF_CTRL_BASE_PTRS { PUF_CTRL, PUF_CTRL_ALIAS1, PUF_CTRL_ALIAS2, PUF_CTRL_ALIAS3 } - /** Array initializer of PUF_CTRL peripheral base addresses */ - #define PUF_CTRL_BASE_ADDRS_NS { PUF_CTRL_BASE_NS, PUF_CTRL_ALIAS1_BASE_NS, PUF_CTRL_ALIAS2_BASE_NS, PUF_CTRL_ALIAS3_BASE_NS } - /** Array initializer of PUF_CTRL peripheral base pointers */ - #define PUF_CTRL_BASE_PTRS_NS { PUF_CTRL_NS, PUF_CTRL_ALIAS1_NS, PUF_CTRL_ALIAS2_NS, PUF_CTRL_ALIAS3_NS } -#else - /** Peripheral PUF_CTRL base address */ - #define PUF_CTRL_BASE (0x4002C000u) - /** Peripheral PUF_CTRL base pointer */ - #define PUF_CTRL ((PUF_CTRL_Type *)PUF_CTRL_BASE) - /** Peripheral PUF_CTRL_ALIAS1 base address */ - #define PUF_CTRL_ALIAS1_BASE (0x4002D000u) - /** Peripheral PUF_CTRL_ALIAS1 base pointer */ - #define PUF_CTRL_ALIAS1 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS1_BASE) - /** Peripheral PUF_CTRL_ALIAS2 base address */ - #define PUF_CTRL_ALIAS2_BASE (0x4002E000u) - /** Peripheral PUF_CTRL_ALIAS2 base pointer */ - #define PUF_CTRL_ALIAS2 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS2_BASE) - /** Peripheral PUF_CTRL_ALIAS3 base address */ - #define PUF_CTRL_ALIAS3_BASE (0x4002F000u) - /** Peripheral PUF_CTRL_ALIAS3 base pointer */ - #define PUF_CTRL_ALIAS3 ((PUF_CTRL_Type *)PUF_CTRL_ALIAS3_BASE) - /** Array initializer of PUF_CTRL peripheral base addresses */ - #define PUF_CTRL_BASE_ADDRS { PUF_CTRL_BASE, PUF_CTRL_ALIAS1_BASE, PUF_CTRL_ALIAS2_BASE, PUF_CTRL_ALIAS3_BASE } - /** Array initializer of PUF_CTRL peripheral base pointers */ - #define PUF_CTRL_BASE_PTRS { PUF_CTRL, PUF_CTRL_ALIAS1, PUF_CTRL_ALIAS2, PUF_CTRL_ALIAS3 } -#endif - -/*! - * @} - */ /* end of group PUF_CTRL_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -67197,12 +60056,12 @@ typedef struct { #define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) -/*! CAPTA_FILT_PER - Fault Filter Period */ +/*! CAPTA_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) #define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) -/*! CAPTA_FILT_CNT - Fault Filter Count */ +/*! CAPTA_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) /*! @} */ @@ -67214,12 +60073,12 @@ typedef struct { #define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) -/*! CAPTB_FILT_PER - Fault Filter Period */ +/*! CAPTB_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) #define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) -/*! CAPTB_FILT_CNT - Fault Filter Count */ +/*! CAPTB_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) /*! @} */ @@ -67231,12 +60090,12 @@ typedef struct { #define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) #define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) -/*! CAPTX_FILT_PER - Fault Filter Period */ +/*! CAPTX_FILT_PER - Input Capture Filter Period */ #define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) #define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) #define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) -/*! CAPTX_FILT_CNT - Fault Filter Count */ +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ #define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) /*! @} */ @@ -67248,26 +60107,17 @@ typedef struct { #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) -/*! PWMX_EN - PWM_X Output Enables - * 0b0000..PWM_X output disabled. - * 0b0001..PWM_X output enabled. - */ +/*! PWMX_EN - PWM_X Output Enables */ #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) #define PWM_OUTEN_PWMB_EN_MASK (0xF0U) #define PWM_OUTEN_PWMB_EN_SHIFT (4U) -/*! PWMB_EN - PWM_B Output Enables - * 0b0000..PWM_B output disabled. - * 0b0001..PWM_B output enabled. - */ +/*! PWMB_EN - PWM_B Output Enables */ #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) -/*! PWMA_EN - PWM_A Output Enables - * 0b0000..PWM_A output disabled. - * 0b0001..PWM_A output enabled. - */ +/*! PWMA_EN - PWM_A Output Enables */ #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) /*! @} */ @@ -67276,34 +60126,22 @@ typedef struct { #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) -/*! MASKX - PWM_X Masks - * 0b0000..PWM_X output normal. - * 0b0001..PWM_X output masked. - */ +/*! MASKX - PWM_X Masks */ #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) #define PWM_MASK_MASKB_MASK (0xF0U) #define PWM_MASK_MASKB_SHIFT (4U) -/*! MASKB - PWM_B Masks - * 0b0000..PWM_B output normal. - * 0b0001..PWM_B output masked. - */ +/*! MASKB - PWM_B Masks */ #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) #define PWM_MASK_MASKA_MASK (0xF00U) #define PWM_MASK_MASKA_SHIFT (8U) -/*! MASKA - PWM_A Masks - * 0b0000..PWM_A output normal. - * 0b0001..PWM_A output masked. - */ +/*! MASKA - PWM_A Masks */ #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) #define PWM_MASK_UPDATE_MASK_MASK (0xF000U) #define PWM_MASK_UPDATE_MASK_SHIFT (12U) -/*! UPDATE_MASK - Update Mask Bits Immediately - * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. - * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. - */ +/*! UPDATE_MASK - Update Mask Bits Immediately */ #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) /*! @} */ @@ -67384,7 +60222,7 @@ typedef struct { * 0b00..Generated SM0PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. - * 0b11..PWM0_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) @@ -67404,7 +60242,7 @@ typedef struct { * 0b00..Generated SM1PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. - * 0b11..PWM1_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) @@ -67424,7 +60262,7 @@ typedef struct { * 0b00..Generated SM2PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. - * 0b11..PWM2_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) @@ -67444,7 +60282,7 @@ typedef struct { * 0b00..Generated SM3PWM45 signal used by the deadtime logic. * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. - * 0b11..PWM3_EXTB signal used by the deadtime logic. + * 0b11..Reserved */ #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) @@ -67495,18 +60333,6 @@ typedef struct { /*! @name MCTRL2 - Master Control 2 Register */ /*! @{ */ -#define PWM_MCTRL2_MONPLL_MASK (0x3U) -#define PWM_MCTRL2_MONPLL_SHIFT (0U) -/*! MONPLL - Monitor PLL State - * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. - * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. - * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock - * will be controlled by software. These bits are write protected until the next reset. - * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL - * encounters problems. These bits are write protected until the next reset. - */ -#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) - #define PWM_MCTRL2_WRPROT_MASK (0xCU) #define PWM_MCTRL2_WRPROT_SHIFT (2U) /*! WRPROT - Write protect @@ -67716,6 +60542,651 @@ typedef struct { */ /* end of group PWM_Peripheral_Access_Layer */ +/* ---------------------------------------------------------------------------- + -- QDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer + * @{ + */ + +/** QDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ + __IO uint16_t TST; /**< Test, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ +} QDC_Type; + +/* ---------------------------------------------------------------------------- + -- QDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Register_Masks QDC Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define QDC_CTRL_CMPIE_MASK (0x1U) +#define QDC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK) + +#define QDC_CTRL_CMPIRQ_MASK (0x2U) +#define QDC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK) + +#define QDC_CTRL_WDE_MASK (0x4U) +#define QDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK) + +#define QDC_CTRL_DIE_MASK (0x8U) +#define QDC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK) + +#define QDC_CTRL_DIRQ_MASK (0x10U) +#define QDC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK) + +#define QDC_CTRL_XNE_MASK (0x20U) +#define QDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive and Negative Edge of INDEX Pulse + * 0b0..Use positive edge + * 0b1..Use negative edge + */ +#define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK) + +#define QDC_CTRL_XIP_MASK (0x40U) +#define QDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..Does not initialize + * 0b1..Initializes + */ +#define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK) + +#define QDC_CTRL_XIE_MASK (0x80U) +#define QDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK) + +#define QDC_CTRL_XIRQ_MASK (0x100U) +#define QDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK) + +#define QDC_CTRL_PH1_MASK (0x200U) +#define QDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. + * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; + * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. + */ +#define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK) + +#define QDC_CTRL_REV_MASK (0x400U) +#define QDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Counts normally + * 0b1..Counts in the reverse direction + */ +#define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK) + +#define QDC_CTRL_SWIP_MASK (0x800U) +#define QDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK) + +#define QDC_CTRL_HNE_MASK (0x1000U) +#define QDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK) + +#define QDC_CTRL_HIP_MASK (0x2000U) +#define QDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK) + +#define QDC_CTRL_HIE_MASK (0x4000U) +#define QDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK) + +#define QDC_CTRL_HIRQ_MASK (0x8000U) +#define QDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter */ +/*! @{ */ + +#define QDC_FILT_FILT_PER_MASK (0xFFU) +#define QDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK) + +#define QDC_FILT_FILT_CNT_MASK (0x700U) +#define QDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK) + +#define QDC_FILT_FILT_PRSC_MASK (0xE000U) +#define QDC_FILT_FILT_PRSC_SHIFT (13U) +/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ +#define QDC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout */ +/*! @{ */ + +#define QDC_WTR_WDOG_MASK (0xFFFFU) +#define QDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter */ +/*! @{ */ + +#define QDC_POSD_POSD_MASK (0xFFFFU) +#define QDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold */ +/*! @{ */ + +#define QDC_POSDH_POSDH_MASK (0xFFFFU) +#define QDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter */ +/*! @{ */ + +#define QDC_REV_REV_MASK (0xFFFFU) +#define QDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold */ +/*! @{ */ + +#define QDC_REVH_REVH_MASK (0xFFFFU) +#define QDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter */ +/*! @{ */ + +#define QDC_UPOS_POS_MASK (0xFFFFU) +#define QDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter */ +/*! @{ */ + +#define QDC_LPOS_POS_MASK (0xFFFFU) +#define QDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold */ +/*! @{ */ + +#define QDC_UPOSH_POSH_MASK (0xFFFFU) +#define QDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold */ +/*! @{ */ + +#define QDC_LPOSH_POSH_MASK (0xFFFFU) +#define QDC_LPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization */ +/*! @{ */ + +#define QDC_UINIT_INIT_MASK (0xFFFFU) +#define QDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization */ +/*! @{ */ + +#define QDC_LINIT_INIT_MASK (0xFFFFU) +#define QDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor */ +/*! @{ */ + +#define QDC_IMR_HOME_MASK (0x1U) +#define QDC_IMR_HOME_SHIFT (0U) +/*! HOME - HOME */ +#define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK) + +#define QDC_IMR_INDEX_MASK (0x2U) +#define QDC_IMR_INDEX_SHIFT (1U) +/*! INDEX - INDEX */ +#define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK) + +#define QDC_IMR_PHB_MASK (0x4U) +#define QDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK) + +#define QDC_IMR_PHA_MASK (0x8U) +#define QDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK) + +#define QDC_IMR_FHOM_MASK (0x10U) +#define QDC_IMR_FHOM_SHIFT (4U) +/*! FHOM - FHOM */ +#define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK) + +#define QDC_IMR_FIND_MASK (0x20U) +#define QDC_IMR_FIND_SHIFT (5U) +/*! FIND - FIND */ +#define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK) + +#define QDC_IMR_FPHB_MASK (0x40U) +#define QDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - FPHB */ +#define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK) + +#define QDC_IMR_FPHA_MASK (0x80U) +#define QDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - FPHA */ +#define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test */ +/*! @{ */ + +#define QDC_TST_TEST_COUNT_MASK (0xFFU) +#define QDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK) + +#define QDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define QDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK) + +#define QDC_TST_QDN_MASK (0x2000U) +#define QDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Positive quadrature decoder signal + * 0b1..Negative quadrature decoder signal + */ +#define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK) + +#define QDC_TST_TCE_MASK (0x4000U) +#define QDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK) + +#define QDC_TST_TEN_MASK (0x8000U) +#define QDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define QDC_CTRL2_UPDHLD_MASK (0x1U) +#define QDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK) + +#define QDC_CTRL2_UPDPOS_MASK (0x2U) +#define QDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action + * 0b1..Clear + */ +#define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK) + +#define QDC_CTRL2_MOD_MASK (0x4U) +#define QDC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK) + +#define QDC_CTRL2_DIR_MASK (0x8U) +#define QDC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Down direction + * 0b1..Up direction + */ +#define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK) + +#define QDC_CTRL2_RUIE_MASK (0x10U) +#define QDC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK) + +#define QDC_CTRL2_RUIRQ_MASK (0x20U) +#define QDC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK) + +#define QDC_CTRL2_ROIE_MASK (0x40U) +#define QDC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK) + +#define QDC_CTRL2_ROIRQ_MASK (0x80U) +#define QDC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..Did not occur + * 0b1..Occurred + */ +#define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK) + +#define QDC_CTRL2_REVMOD_MASK (0x100U) +#define QDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse + * 0b1..Use modulus counting roll-over or roll-under + */ +#define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK) + +#define QDC_CTRL2_OUTCTL_MASK (0x200U) +#define QDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + */ +#define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK) + +#define QDC_CTRL2_SABIE_MASK (0x400U) +#define QDC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK) + +#define QDC_CTRL2_SABIRQ_MASK (0x800U) +#define QDC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change has occurred + * 0b1..A simultaneous change has occurred + */ +#define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK) + +#define QDC_CTRL2_INITPOS_MASK (0x1000U) +#define QDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initialize Position Registers + * 0b0..Don't initialize position counter + * 0b1..Initialize position counter + */ +#define QDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus */ +/*! @{ */ + +#define QDC_UMOD_MOD_MASK (0xFFFFU) +#define QDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus */ +/*! @{ */ + +#define QDC_LMOD_MOD_MASK (0xFFFFU) +#define QDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare */ +/*! @{ */ + +#define QDC_UCOMP_COMP_MASK (0xFFFFU) +#define QDC_UCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare */ +/*! @{ */ + +#define QDC_LCOMP_COMP_MASK (0xFFFFU) +#define QDC_LCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time */ +/*! @{ */ + +#define QDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define QDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define QDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold */ +/*! @{ */ + +#define QDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define QDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define QDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter */ +/*! @{ */ + +#define QDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define QDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define QDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer */ +/*! @{ */ + +#define QDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define QDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define QDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold */ +/*! @{ */ + +#define QDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define QDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define QDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 */ +/*! @{ */ + +#define QDC_CTRL3_PMEN_MASK (0x1U) +#define QDC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period Measurement Function Enable + * 0b0..Not used + * 0b1..Used + */ +#define QDC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK) + +#define QDC_CTRL3_PRSC_MASK (0xF0U) +#define QDC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler */ +#define QDC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group QDC_Register_Masks */ + + +/* QDC - Peripheral instance base addresses */ +#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x500D1000u) + /** Peripheral QDC1 base address */ + #define QDC1_BASE_NS (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Peripheral QDC1 base pointer */ + #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } + +/*! + * @} + */ /* end of group QDC_Peripheral_Access_Layer */ + + /* ---------------------------------------------------------------------------- -- RTC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -68312,8 +61783,8 @@ typedef struct { #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) /*! SUB_SECOND_CNT_EN - Subsecond Counter Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) /*! @} */ @@ -68333,32 +61804,32 @@ typedef struct { #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) /*! WAKE_FLAG - Wake Timer Status Flag - * 0b0..Wake timer has not timed out. - * 0b1..Wake timer has timed out. + * 0b0..Not timed out + * 0b1..Timed out */ #define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) /*! CLR_WAKE_TIMER - Clear Wake Timer - * 0b0..No effect. - * 0b1..Clears the wake timer counter and halts operation until a new count value is loaded. + * 0b0..No effect + * 0b1..Clear the wake timer counter */ #define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) /*! OSC_DIV_ENA - OSC Divide Enable - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) #define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) #define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) /*! INTR_EN - Enable Interrupt - * 0b0..Disabled - * 0b1..Enabled + * 0b0..Disable + * 0b1..Enable */ #define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) /*! @} */ @@ -68428,37 +61899,37 @@ typedef struct { /** S50 - Register Layout Typedef */ typedef struct { - __I uint32_t STATUS; /**< Status Register, offset: 0x0 */ - __IO uint32_t CTRL; /**< Control Register, offset: 0x4 */ - __IO uint32_t CMDCFG0; /**< Command Configuration Register, offset: 0x8 */ - __IO uint32_t CFG; /**< Configuration Register, offset: 0xC */ - __IO uint32_t KIDX0; /**< Keystore Index 0 Register, offset: 0x10 */ - __IO uint32_t KIDX1; /**< Keystore Index 1 Register, offset: 0x14 */ - __IO uint32_t KPROPIN; /**< Key Properties Request Register, offset: 0x18 */ + __I uint32_t ELS_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t ELS_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t ELS_CMDCFG0; /**< Command Configuration, offset: 0x8 */ + __IO uint32_t ELS_CFG; /**< Configuration Register, offset: 0xC */ + __IO uint32_t ELS_KIDX0; /**< Keystore Index 0, offset: 0x10 */ + __IO uint32_t ELS_KIDX1; /**< Keystore Index 1, offset: 0x14 */ + __IO uint32_t ELS_KPROPIN; /**< Key Properties Request, offset: 0x18 */ uint8_t RESERVED_0[4]; - __IO uint32_t DMA_SRC0; /**< DMA Source 0 Register, offset: 0x20 */ - __IO uint32_t DMA_SRC0_LEN; /**< DMA Source 0 Length Register, offset: 0x24 */ - __IO uint32_t DMA_SRC1; /**< DMA Source 1 Register, offset: 0x28 */ + __IO uint32_t ELS_DMA_SRC0; /**< DMA Source 0, offset: 0x20 */ + __IO uint32_t ELS_DMA_SRC0_LEN; /**< DMA Source 0 Length, offset: 0x24 */ + __IO uint32_t ELS_DMA_SRC1; /**< DMA Source 1, offset: 0x28 */ uint8_t RESERVED_1[4]; - __IO uint32_t DMA_SRC2; /**< DMA Source 2 Register, offset: 0x30 */ - __IO uint32_t DMA_SRC2_LEN; /**< DMA Source 2 Length Register, offset: 0x34 */ - __IO uint32_t DMA_RES0; /**< DMA Result 0 Register, offset: 0x38 */ - __IO uint32_t DMA_RES0_LEN; /**< DMA Result 0 Size Register, offset: 0x3C */ - __IO uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x40 */ - __O uint32_t INT_STATUS_CLR; /**< Interrupt Status Clear Register, offset: 0x44 */ - __O uint32_t INT_STATUS_SET; /**< Interrupt Status Set Register, offset: 0x48 */ - __I uint32_t ERR_STATUS; /**< Error Status Register, offset: 0x4C */ - __O uint32_t ERR_STATUS_CLR; /**< Error Status Clear Register, offset: 0x50 */ - __I uint32_t VERSION; /**< Version Register, offset: 0x54 */ + __IO uint32_t ELS_DMA_SRC2; /**< DMA Source 2, offset: 0x30 */ + __IO uint32_t ELS_DMA_SRC2_LEN; /**< DMA Source 2 Length, offset: 0x34 */ + __IO uint32_t ELS_DMA_RES0; /**< DMA Result 0, offset: 0x38 */ + __IO uint32_t ELS_DMA_RES0_LEN; /**< DMA Result 0 Length, offset: 0x3C */ + __IO uint32_t ELS_INT_ENABLE; /**< Interrupt Enable, offset: 0x40 */ + __O uint32_t ELS_INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0x44 */ + __O uint32_t ELS_INT_STATUS_SET; /**< Interrupt Status Set, offset: 0x48 */ + __I uint32_t ELS_ERR_STATUS; /**< Error Status, offset: 0x4C */ + __O uint32_t ELS_ERR_STATUS_CLR; /**< Error Status Clear, offset: 0x50 */ + __I uint32_t ELS_VERSION; /**< Version Register, offset: 0x54 */ uint8_t RESERVED_2[4]; - __I uint32_t PRNG_DATOUT; /**< PRNG SW Read Out Register, offset: 0x5C */ - __IO uint32_t CMDCRC_CTRL; /**< CRC Configuration Register, offset: 0x60 */ - __I uint32_t CMDCRC; /**< Command CRC Value Register, offset: 0x64 */ - __IO uint32_t SESSION_ID; /**< Session ID Register, offset: 0x68 */ + __I uint32_t ELS_PRNG_DATOUT; /**< PRNG SW Read Out, offset: 0x5C */ + __IO uint32_t ELS_CMDCRC_CTRL; /**< CRC Configuration, offset: 0x60 */ + __I uint32_t ELS_CMDCRC; /**< Command CRC Value, offset: 0x64 */ + __IO uint32_t ELS_SESSION_ID; /**< Session ID, offset: 0x68 */ uint8_t RESERVED_3[4]; - __I uint32_t DMA_FIN_ADDR; /**< Final DMA Address Register, offset: 0x70 */ - __IO uint32_t MASTER_ID; /**< Master ID Register, offset: 0x74 */ - __IO uint32_t KIDX2; /**< Keystore Index 2 Register, offset: 0x78 */ + __I uint32_t ELS_DMA_FIN_ADDR; /**< Final DMA Address, offset: 0x70 */ + __IO uint32_t ELS_MASTER_ID; /**< Master ID, offset: 0x74 */ + __IO uint32_t ELS_KIDX2; /**< Keystore Index 2, offset: 0x78 */ uint8_t RESERVED_4[212]; __I uint32_t ELS_KS0; /**< Status Register, offset: 0x150 */ __I uint32_t ELS_KS1; /**< Status Register, offset: 0x154 */ @@ -68491,383 +61962,423 @@ typedef struct { * @{ */ -/*! @name STATUS - Status Register */ +/*! @name ELS_STATUS - Status Register */ /*! @{ */ -#define S50_STATUS_ELS_BUSY_MASK (0x1U) -#define S50_STATUS_ELS_BUSY_SHIFT (0U) +#define S50_ELS_STATUS_ELS_BUSY_MASK (0x1U) +#define S50_ELS_STATUS_ELS_BUSY_SHIFT (0U) /*! ELS_BUSY * 0b1..Crypto sequence executing * 0b0..Crypto sequence not executing */ -#define S50_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_BUSY_SHIFT)) & S50_STATUS_ELS_BUSY_MASK) +#define S50_ELS_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK) -#define S50_STATUS_ELS_IRQ_MASK (0x2U) -#define S50_STATUS_ELS_IRQ_SHIFT (1U) +#define S50_ELS_STATUS_ELS_IRQ_MASK (0x2U) +#define S50_ELS_STATUS_ELS_IRQ_SHIFT (1U) /*! ELS_IRQ * 0b1..Active interrupt * 0b0..No active interrupt */ -#define S50_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_IRQ_SHIFT)) & S50_STATUS_ELS_IRQ_MASK) +#define S50_ELS_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK) -#define S50_STATUS_ELS_ERR_MASK (0x4U) -#define S50_STATUS_ELS_ERR_SHIFT (2U) +#define S50_ELS_STATUS_ELS_ERR_MASK (0x4U) +#define S50_ELS_STATUS_ELS_ERR_SHIFT (2U) /*! ELS_ERR * 0b1..Internal error detected * 0b0..Internal error not detected */ -#define S50_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_ERR_SHIFT)) & S50_STATUS_ELS_ERR_MASK) +#define S50_ELS_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK) -#define S50_STATUS_PRNG_RDY_MASK (0x8U) -#define S50_STATUS_PRNG_RDY_SHIFT (3U) +#define S50_ELS_STATUS_PRNG_RDY_MASK (0x8U) +#define S50_ELS_STATUS_PRNG_RDY_SHIFT (3U) /*! PRNG_RDY * 0b0..Internal PRNG not ready * 0b1..Internal PRNG ready */ -#define S50_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_PRNG_RDY_SHIFT)) & S50_STATUS_PRNG_RDY_MASK) +#define S50_ELS_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK) -#define S50_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) -#define S50_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) /*! ECDSA_VFY_STATUS * 0b11..Invalid, Error * 0b00..No verify run * 0b01..Signature verify failed * 0b10..Signature verify passed */ -#define S50_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_STATUS_ECDSA_VFY_STATUS_MASK) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK) -#define S50_STATUS_PPROT_MASK (0xC0U) -#define S50_STATUS_PPROT_SHIFT (6U) +#define S50_ELS_STATUS_PPROT_MASK (0xC0U) +#define S50_ELS_STATUS_PPROT_SHIFT (6U) /*! PPROT * 0b10..Non-secure, non-privileged * 0b11..Non-secure, privileged * 0b00..Secure, non-privileged * 0b01..Secure, privileged */ -#define S50_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_PPROT_SHIFT)) & S50_STATUS_PPROT_MASK) +#define S50_ELS_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK) -#define S50_STATUS_DRBG_ENT_LVL_MASK (0x300U) -#define S50_STATUS_DRBG_ENT_LVL_SHIFT (8U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_MASK (0x300U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT (8U) /*! DRBG_ENT_LVL * 0b10..HIGH, DRBG generates random numbers of high quality entropy * 0b01..LOW, DRBG generates random numbers of low quality entropy * 0b00..NONE * 0b11..RFU, Reserved for Future Use */ -#define S50_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_STATUS_DRBG_ENT_LVL_MASK) +#define S50_ELS_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK) -#define S50_STATUS_DTRNG_BUSY_MASK (0x400U) -#define S50_STATUS_DTRNG_BUSY_SHIFT (10U) +#define S50_ELS_STATUS_DTRNG_BUSY_MASK (0x400U) +#define S50_ELS_STATUS_DTRNG_BUSY_SHIFT (10U) /*! DTRNG_BUSY * 0b1..Gathering entropy * 0b0..Not gathering entropy */ -#define S50_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_DTRNG_BUSY_SHIFT)) & S50_STATUS_DTRNG_BUSY_MASK) +#define S50_ELS_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK) -#define S50_STATUS_ELS_LOCKED_MASK (0x10000U) -#define S50_STATUS_ELS_LOCKED_SHIFT (16U) +#define S50_ELS_STATUS_ELS_LOCKED_MASK (0x10000U) +#define S50_ELS_STATUS_ELS_LOCKED_SHIFT (16U) /*! ELS_LOCKED * 0b1..Locked by master * 0b0..Not locked by master */ -#define S50_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_STATUS_ELS_LOCKED_SHIFT)) & S50_STATUS_ELS_LOCKED_MASK) +#define S50_ELS_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK) /*! @} */ -/*! @name CTRL - Control Register */ +/*! @name ELS_CTRL - Control Register */ /*! @{ */ -#define S50_CTRL_ELS_EN_MASK (0x1U) -#define S50_CTRL_ELS_EN_SHIFT (0U) +#define S50_ELS_CTRL_ELS_EN_MASK (0x1U) +#define S50_ELS_CTRL_ELS_EN_SHIFT (0U) /*! ELS_EN * 0b0..Disabled * 0b1..Enabled */ -#define S50_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_EN_SHIFT)) & S50_CTRL_ELS_EN_MASK) +#define S50_ELS_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK) -#define S50_CTRL_ELS_START_MASK (0x2U) -#define S50_CTRL_ELS_START_SHIFT (1U) -#define S50_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_START_SHIFT)) & S50_CTRL_ELS_START_MASK) +#define S50_ELS_CTRL_ELS_START_MASK (0x2U) +#define S50_ELS_CTRL_ELS_START_SHIFT (1U) +#define S50_ELS_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK) -#define S50_CTRL_ELS_RESET_MASK (0x4U) -#define S50_CTRL_ELS_RESET_SHIFT (2U) -#define S50_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_RESET_SHIFT)) & S50_CTRL_ELS_RESET_MASK) +#define S50_ELS_CTRL_ELS_RESET_MASK (0x4U) +#define S50_ELS_CTRL_ELS_RESET_SHIFT (2U) +#define S50_ELS_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK) -#define S50_CTRL_ELS_CMD_MASK (0xF8U) -#define S50_CTRL_ELS_CMD_SHIFT (3U) +#define S50_ELS_CTRL_ELS_CMD_MASK (0xF8U) +#define S50_ELS_CTRL_ELS_CMD_SHIFT (3U) /*! ELS_CMD - ELS Command ID */ -#define S50_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_ELS_CMD_SHIFT)) & S50_CTRL_ELS_CMD_MASK) +#define S50_ELS_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK) -#define S50_CTRL_BYTE_ORDER_MASK (0x100U) -#define S50_CTRL_BYTE_ORDER_SHIFT (8U) +#define S50_ELS_CTRL_BYTE_ORDER_MASK (0x100U) +#define S50_ELS_CTRL_BYTE_ORDER_SHIFT (8U) /*! BYTE_ORDER * 0b1..Big endian * 0b0..Little endian */ -#define S50_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_CTRL_BYTE_ORDER_SHIFT)) & S50_CTRL_BYTE_ORDER_MASK) +#define S50_ELS_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK) /*! @} */ -/*! @name CMDCFG0 - Command Configuration Register */ +/*! @name ELS_CMDCFG0 - Command Configuration */ /*! @{ */ -#define S50_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) -#define S50_CMDCFG0_CMDCFG0_SHIFT (0U) -#define S50_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCFG0_CMDCFG0_SHIFT)) & S50_CMDCFG0_CMDCFG0_MASK) +#define S50_ELS_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCFG0_CMDCFG0_SHIFT (0U) +#define S50_ELS_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK) /*! @} */ -/*! @name CFG - Configuration Register */ +/*! @name ELS_CFG - Configuration Register */ /*! @{ */ -#define S50_CFG_ADCTRL_MASK (0x3FF0000U) -#define S50_CFG_ADCTRL_SHIFT (16U) -#define S50_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_CFG_ADCTRL_SHIFT)) & S50_CFG_ADCTRL_MASK) +#define S50_ELS_CFG_ADCTRL_MASK (0x3FF0000U) +#define S50_ELS_CFG_ADCTRL_SHIFT (16U) +#define S50_ELS_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK) /*! @} */ -/*! @name KIDX0 - Keystore Index 0 Register */ +/*! @name ELS_KIDX0 - Keystore Index 0 */ /*! @{ */ -#define S50_KIDX0_KIDX0_MASK (0x1FU) -#define S50_KIDX0_KIDX0_SHIFT (0U) -#define S50_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_KIDX0_KIDX0_SHIFT)) & S50_KIDX0_KIDX0_MASK) +#define S50_ELS_KIDX0_KIDX0_MASK (0x1FU) +#define S50_ELS_KIDX0_KIDX0_SHIFT (0U) +#define S50_ELS_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK) /*! @} */ -/*! @name KIDX1 - Keystore Index 1 Register */ +/*! @name ELS_KIDX1 - Keystore Index 1 */ /*! @{ */ -#define S50_KIDX1_KIDX1_MASK (0x1FU) -#define S50_KIDX1_KIDX1_SHIFT (0U) -#define S50_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_KIDX1_KIDX1_SHIFT)) & S50_KIDX1_KIDX1_MASK) +#define S50_ELS_KIDX1_KIDX1_MASK (0x1FU) +#define S50_ELS_KIDX1_KIDX1_SHIFT (0U) +#define S50_ELS_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK) /*! @} */ -/*! @name KPROPIN - Key Properties Request Register */ +/*! @name ELS_KPROPIN - Key Properties Request */ /*! @{ */ -#define S50_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) -#define S50_KPROPIN_KPROPIN_SHIFT (0U) -#define S50_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_KPROPIN_KPROPIN_SHIFT)) & S50_KPROPIN_KPROPIN_MASK) +#define S50_ELS_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) +#define S50_ELS_KPROPIN_KPROPIN_SHIFT (0U) +#define S50_ELS_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK) /*! @} */ -/*! @name DMA_SRC0 - DMA Source 0 Register */ +/*! @name ELS_DMA_SRC0 - DMA Source 0 */ /*! @{ */ -#define S50_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC0_ADDR_SRC0_SHIFT (0U) -#define S50_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_DMA_SRC0_ADDR_SRC0_MASK) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT (0U) +#define S50_ELS_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK) /*! @} */ -/*! @name DMA_SRC0_LEN - DMA Source 0 Length Register */ +/*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */ /*! @{ */ -#define S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) -#define S50_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) /*! @} */ -/*! @name DMA_SRC1 - DMA Source 1 Register */ +/*! @name ELS_DMA_SRC1 - DMA Source 1 */ /*! @{ */ -#define S50_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC1_ADDR_SRC1_SHIFT (0U) -#define S50_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_DMA_SRC1_ADDR_SRC1_MASK) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT (0U) +#define S50_ELS_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK) /*! @} */ -/*! @name DMA_SRC2 - DMA Source 2 Register */ +/*! @name ELS_DMA_SRC2 - DMA Source 2 */ /*! @{ */ -#define S50_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC2_ADDR_SRC2_SHIFT (0U) -#define S50_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_DMA_SRC2_ADDR_SRC2_MASK) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT (0U) +#define S50_ELS_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK) /*! @} */ -/*! @name DMA_SRC2_LEN - DMA Source 2 Length Register */ +/*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */ /*! @{ */ -#define S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) -#define S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) -#define S50_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) /*! @} */ -/*! @name DMA_RES0 - DMA Result 0 Register */ +/*! @name ELS_DMA_RES0 - DMA Result 0 */ /*! @{ */ -#define S50_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) -#define S50_DMA_RES0_ADDR_RES0_SHIFT (0U) -#define S50_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_RES0_ADDR_RES0_SHIFT)) & S50_DMA_RES0_ADDR_RES0_MASK) +#define S50_ELS_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT (0U) +#define S50_ELS_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK) /*! @} */ -/*! @name DMA_RES0_LEN - DMA Result 0 Size Register */ +/*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */ /*! @{ */ -#define S50_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) -#define S50_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) -#define S50_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) /*! @} */ -/*! @name INT_ENABLE - Interrupt Enable Register */ +/*! @name ELS_INT_ENABLE - Interrupt Enable */ /*! @{ */ -#define S50_INT_ENABLE_INT_EN_MASK (0x1U) -#define S50_INT_ENABLE_INT_EN_SHIFT (0U) -#define S50_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_INT_ENABLE_INT_EN_SHIFT)) & S50_INT_ENABLE_INT_EN_MASK) +#define S50_ELS_INT_ENABLE_INT_EN_MASK (0x1U) +#define S50_ELS_INT_ENABLE_INT_EN_SHIFT (0U) +/*! INT_EN + * 0b0..Disables + * 0b1..Enables + */ +#define S50_ELS_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK) /*! @} */ -/*! @name INT_STATUS_CLR - Interrupt Status Clear Register */ +/*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */ /*! @{ */ -#define S50_INT_STATUS_CLR_INT_CLR_MASK (0x1U) -#define S50_INT_STATUS_CLR_INT_CLR_SHIFT (0U) -#define S50_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_INT_STATUS_CLR_INT_CLR_MASK) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK (0x1U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT (0U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK) /*! @} */ -/*! @name INT_STATUS_SET - Interrupt Status Set Register */ +/*! @name ELS_INT_STATUS_SET - Interrupt Status Set */ /*! @{ */ -#define S50_INT_STATUS_SET_INT_SET_MASK (0x1U) -#define S50_INT_STATUS_SET_INT_SET_SHIFT (0U) -#define S50_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_INT_STATUS_SET_INT_SET_SHIFT)) & S50_INT_STATUS_SET_INT_SET_MASK) +#define S50_ELS_INT_STATUS_SET_INT_SET_MASK (0x1U) +#define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT (0U) +#define S50_ELS_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK) /*! @} */ -/*! @name ERR_STATUS - Error Status Register */ +/*! @name ELS_ERR_STATUS - Error Status */ /*! @{ */ -#define S50_ERR_STATUS_BUS_ERR_MASK (0x1U) -#define S50_ERR_STATUS_BUS_ERR_SHIFT (0U) -#define S50_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ERR_STATUS_BUS_ERR_MASK) +#define S50_ELS_ERR_STATUS_BUS_ERR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT (0U) +/*! BUS_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK) -#define S50_ERR_STATUS_OPN_ERR_MASK (0x2U) -#define S50_ERR_STATUS_OPN_ERR_SHIFT (1U) -#define S50_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ERR_STATUS_OPN_ERR_MASK) +#define S50_ELS_ERR_STATUS_OPN_ERR_MASK (0x2U) +#define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT (1U) +/*! OPN_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK) -#define S50_ERR_STATUS_ALG_ERR_MASK (0x4U) -#define S50_ERR_STATUS_ALG_ERR_SHIFT (2U) -#define S50_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ERR_STATUS_ALG_ERR_MASK) +#define S50_ELS_ERR_STATUS_ALG_ERR_MASK (0x4U) +#define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT (2U) +/*! ALG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK) -#define S50_ERR_STATUS_ITG_ERR_MASK (0x8U) -#define S50_ERR_STATUS_ITG_ERR_SHIFT (3U) -#define S50_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ERR_STATUS_ITG_ERR_MASK) +#define S50_ELS_ERR_STATUS_ITG_ERR_MASK (0x8U) +#define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT (3U) +/*! ITG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK) -#define S50_ERR_STATUS_FLT_ERR_MASK (0x10U) -#define S50_ERR_STATUS_FLT_ERR_SHIFT (4U) -#define S50_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ERR_STATUS_FLT_ERR_MASK) +#define S50_ELS_ERR_STATUS_FLT_ERR_MASK (0x10U) +#define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT (4U) +/*! FLT_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK) -#define S50_ERR_STATUS_PRNG_ERR_MASK (0x20U) -#define S50_ERR_STATUS_PRNG_ERR_SHIFT (5U) -#define S50_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ERR_STATUS_PRNG_ERR_MASK) +#define S50_ELS_ERR_STATUS_PRNG_ERR_MASK (0x20U) +#define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT (5U) +/*! PRNG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK) -#define S50_ERR_STATUS_ERR_LVL_MASK (0xC0U) -#define S50_ERR_STATUS_ERR_LVL_SHIFT (6U) -#define S50_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ERR_STATUS_ERR_LVL_MASK) +#define S50_ELS_ERR_STATUS_ERR_LVL_MASK (0xC0U) +#define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT (6U) +#define S50_ELS_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK) -#define S50_ERR_STATUS_DTRNG_ERR_MASK (0x100U) -#define S50_ERR_STATUS_DTRNG_ERR_SHIFT (8U) -#define S50_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ERR_STATUS_DTRNG_ERR_MASK) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK (0x100U) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT (8U) +/*! DTRNG_ERR + * 0b0..No error + * 0b1..TRNG error occurred + */ +#define S50_ELS_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK) /*! @} */ -/*! @name ERR_STATUS_CLR - Error Status Clear Register */ +/*! @name ELS_ERR_STATUS_CLR - Error Status Clear */ /*! @{ */ -#define S50_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) -#define S50_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) /*! ERR_CLR - * 0b1..Clears ELS error status bits + * 0b1..Clears ELS error state * 0b0..Exits ELS error state */ -#define S50_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ERR_STATUS_CLR_ERR_CLR_MASK) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK) /*! @} */ -/*! @name VERSION - Version Register */ +/*! @name ELS_VERSION - Version Register */ /*! @{ */ -#define S50_VERSION_Z_MASK (0xFU) -#define S50_VERSION_Z_SHIFT (0U) -#define S50_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_Z_SHIFT)) & S50_VERSION_Z_MASK) +#define S50_ELS_VERSION_Z_MASK (0xFU) +#define S50_ELS_VERSION_Z_SHIFT (0U) +#define S50_ELS_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK) -#define S50_VERSION_Y2_MASK (0xF0U) -#define S50_VERSION_Y2_SHIFT (4U) -#define S50_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_Y2_SHIFT)) & S50_VERSION_Y2_MASK) +#define S50_ELS_VERSION_Y2_MASK (0xF0U) +#define S50_ELS_VERSION_Y2_SHIFT (4U) +#define S50_ELS_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK) -#define S50_VERSION_Y1_MASK (0xF00U) -#define S50_VERSION_Y1_SHIFT (8U) -#define S50_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_Y1_SHIFT)) & S50_VERSION_Y1_MASK) +#define S50_ELS_VERSION_Y1_MASK (0xF00U) +#define S50_ELS_VERSION_Y1_SHIFT (8U) +#define S50_ELS_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK) -#define S50_VERSION_X_MASK (0xF000U) -#define S50_VERSION_X_SHIFT (12U) -#define S50_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_X_SHIFT)) & S50_VERSION_X_MASK) +#define S50_ELS_VERSION_X_MASK (0xF000U) +#define S50_ELS_VERSION_X_SHIFT (12U) +#define S50_ELS_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK) -#define S50_VERSION_SW_Z_MASK (0xF0000U) -#define S50_VERSION_SW_Z_SHIFT (16U) -#define S50_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_Z_SHIFT)) & S50_VERSION_SW_Z_MASK) +#define S50_ELS_VERSION_SW_Z_MASK (0xF0000U) +#define S50_ELS_VERSION_SW_Z_SHIFT (16U) +#define S50_ELS_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK) -#define S50_VERSION_SW_Y2_MASK (0xF00000U) -#define S50_VERSION_SW_Y2_SHIFT (20U) -#define S50_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_Y2_SHIFT)) & S50_VERSION_SW_Y2_MASK) +#define S50_ELS_VERSION_SW_Y2_MASK (0xF00000U) +#define S50_ELS_VERSION_SW_Y2_SHIFT (20U) +#define S50_ELS_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK) -#define S50_VERSION_SW_Y1_MASK (0xF000000U) -#define S50_VERSION_SW_Y1_SHIFT (24U) -#define S50_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_Y1_SHIFT)) & S50_VERSION_SW_Y1_MASK) +#define S50_ELS_VERSION_SW_Y1_MASK (0xF000000U) +#define S50_ELS_VERSION_SW_Y1_SHIFT (24U) +#define S50_ELS_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK) -#define S50_VERSION_SW_X_MASK (0xF0000000U) -#define S50_VERSION_SW_X_SHIFT (28U) -#define S50_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_VERSION_SW_X_SHIFT)) & S50_VERSION_SW_X_MASK) +#define S50_ELS_VERSION_SW_X_MASK (0xF0000000U) +#define S50_ELS_VERSION_SW_X_SHIFT (28U) +#define S50_ELS_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK) /*! @} */ -/*! @name PRNG_DATOUT - PRNG SW Read Out Register */ +/*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */ /*! @{ */ -#define S50_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) -#define S50_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) -#define S50_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_PRNG_DATOUT_PRNG_DATOUT_MASK) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK) /*! @} */ -/*! @name CMDCRC_CTRL - CRC Configuration Register */ +/*! @name ELS_CMDCRC_CTRL - CRC Configuration */ /*! @{ */ -#define S50_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) -#define S50_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) -#define S50_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_CMDCRC_CTRL_CMDCRC_RST_MASK) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) +/*! CMDCRC_RST + * 0b1..Resets the CRC command to its default value + * 0b0..No effect + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK) -#define S50_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) -#define S50_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) -#define S50_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_CMDCRC_CTRL_CMDCRC_EN_MASK) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) +/*! CMDCRC_EN + * 0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command. + * 0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command. + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK) /*! @} */ -/*! @name CMDCRC - Command CRC Value Register */ +/*! @name ELS_CMDCRC - Command CRC Value */ /*! @{ */ -#define S50_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) -#define S50_CMDCRC_CMDCRC_SHIFT (0U) -#define S50_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_CMDCRC_CMDCRC_SHIFT)) & S50_CMDCRC_CMDCRC_MASK) +#define S50_ELS_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCRC_CMDCRC_SHIFT (0U) +#define S50_ELS_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK) /*! @} */ -/*! @name SESSION_ID - Session ID Register */ +/*! @name ELS_SESSION_ID - Session ID */ /*! @{ */ -#define S50_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) -#define S50_SESSION_ID_SESSION_ID_SHIFT (0U) -#define S50_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_SESSION_ID_SESSION_ID_SHIFT)) & S50_SESSION_ID_SESSION_ID_MASK) +#define S50_ELS_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) +#define S50_ELS_SESSION_ID_SESSION_ID_SHIFT (0U) +#define S50_ELS_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK) /*! @} */ -/*! @name DMA_FIN_ADDR - Final DMA Address Register */ +/*! @name ELS_DMA_FIN_ADDR - Final DMA Address */ /*! @{ */ -#define S50_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) -#define S50_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) -#define S50_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) /*! @} */ -/*! @name MASTER_ID - Master ID Register */ +/*! @name ELS_MASTER_ID - Master ID */ /*! @{ */ -#define S50_MASTER_ID_MASTER_ID_MASK (0x1FU) -#define S50_MASTER_ID_MASTER_ID_SHIFT (0U) -#define S50_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_MASTER_ID_MASTER_ID_SHIFT)) & S50_MASTER_ID_MASTER_ID_MASK) +#define S50_ELS_MASTER_ID_MASTER_ID_MASK (0x1FU) +#define S50_ELS_MASTER_ID_MASTER_ID_SHIFT (0U) +#define S50_ELS_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK) /*! @} */ -/*! @name KIDX2 - Keystore Index 2 Register */ +/*! @name ELS_KIDX2 - Keystore Index 2 */ /*! @{ */ -#define S50_KIDX2_KIDX2_MASK (0x1FU) -#define S50_KIDX2_KIDX2_SHIFT (0U) -#define S50_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_KIDX2_KIDX2_SHIFT)) & S50_KIDX2_KIDX2_MASK) +#define S50_ELS_KIDX2_KIDX2_MASK (0x1FU) +#define S50_ELS_KIDX2_KIDX2_SHIFT (0U) +#define S50_ELS_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK) /*! @} */ /*! @name ELS_KS0 - Status Register */ @@ -71211,7 +64722,8 @@ typedef struct { __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ uint8_t RESERVED_4[8]; __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ - uint8_t RESERVED_5[8]; + __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ + uint8_t RESERVED_5[4]; __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ uint8_t RESERVED_6[228]; __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ @@ -71255,8 +64767,6 @@ typedef struct { __IO uint32_t UPLLCSR; /**< UPLL Control Status Register, offset: 0x700 */ uint8_t RESERVED_17[252]; __IO uint32_t LDOCSR; /**< LDO Control and Status Register, offset: 0x800 */ - uint8_t RESERVED_18[252]; - __IO uint32_t TROCSR; /**< TRO Control Status Register, offset: 0x900 */ } SCG_Type; /* ---------------------------------------------------------------------------- @@ -71335,14 +64845,6 @@ typedef struct { * 0b0..UPLL clock source is not present */ #define SCG_PARAM_UPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK) - -#define SCG_PARAM_TROCLKPRES_MASK (0x100U) -#define SCG_PARAM_TROCLKPRES_SHIFT (8U) -/*! TROCLKPRES - TRO Clock Present - * 0b1..TRO clock source is present - * 0b0..TRO clock source is not present - */ -#define SCG_PARAM_TROCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_TROCLKPRES_SHIFT)) & SCG_PARAM_TROCLKPRES_MASK) /*! @} */ /*! @name TRIM_LOCK - Trim Lock register */ @@ -71384,8 +64886,7 @@ typedef struct { * 0b0101..APLL * 0b0110..SPLL * 0b0111..UPLL - * 0b1000..TRO - * 0b1001-0b1111..Reserved + * 0b1000-0b1111..Reserved */ #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) /*! @} */ @@ -71404,8 +64905,7 @@ typedef struct { * 0b0101..APLL * 0b0110..SPLL * 0b0111..UPLL - * 0b1000..TRO - * 0b1001-0b1111..Reserved + * 0b1000-0b1111..Reserved */ #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) /*! @} */ @@ -71619,6 +65119,29 @@ typedef struct { #define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) /*! @} */ +/*! @name SIRCTRIM - SIRC Trim Register */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + /*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ /*! @{ */ @@ -71906,14 +65429,6 @@ typedef struct { */ #define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) -#define SCG_APLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) -#define SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) -/*! FRM_CLOCKSTABLE - Free running mode clock stable - * 0b0..Free running mode clockstable is disabled - * 0b1..Free running mode clockstable is enabled - */ -#define SCG_APLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_APLLCSR_FRM_CLOCKSTABLE_MASK) - #define SCG_APLLCSR_APLLCM_MASK (0x10000U) #define SCG_APLLCSR_APLLCM_SHIFT (16U) /*! APLLCM - APLL Clock Monitor @@ -72029,20 +65544,12 @@ typedef struct { */ #define SCG_APLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) -#define SCG_APLLCTRL_FRM_MASK (0x400000U) -#define SCG_APLLCTRL_FRM_SHIFT (22U) -/*! FRM - Free Running Mode Enable - * 0b0..Free running mode disabled - * 0b1..Free running mode enabled - */ -#define SCG_APLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_FRM_SHIFT)) & SCG_APLLCTRL_FRM_MASK) - #define SCG_APLLCTRL_SOURCE_MASK (0x6000000U) #define SCG_APLLCTRL_SOURCE_SHIFT (25U) /*! SOURCE - Clock Source * 0b00..SOSC * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. - * 0b10..ROSC + * 0b10..Reserved * 0b11..No clock */ #define SCG_APLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK) @@ -72074,14 +65581,6 @@ typedef struct { * 0b1..The postdivider (P) ratio change is accepted by the analog PLL */ #define SCG_APLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK) - -#define SCG_APLLSTAT_FRMDET_MASK (0x10U) -#define SCG_APLLSTAT_FRMDET_SHIFT (4U) -/*! FRMDET - Free running detector (active high) - * 0b0..Free running is not detected - * 0b1..Free running is detected - */ -#define SCG_APLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_FRMDET_SHIFT)) & SCG_APLLSTAT_FRMDET_MASK) /*! @} */ /*! @name APLLNDIV - APLL N Divider Register */ @@ -72279,14 +65778,6 @@ typedef struct { */ #define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) -#define SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) -#define SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) -/*! FRM_CLOCKSTABLE - Free running mode clock stable - * 0b0..Free running mode clockstable is disabled - * 0b1..Free running mode clockstable is enabled - */ -#define SCG_SPLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK) - #define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) #define SCG_SPLLCSR_SPLLCM_SHIFT (16U) /*! SPLLCM - SPLL Clock Monitor @@ -72402,20 +65893,12 @@ typedef struct { */ #define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) -#define SCG_SPLLCTRL_FRM_MASK (0x400000U) -#define SCG_SPLLCTRL_FRM_SHIFT (22U) -/*! FRM - Free Running Mode Enable - * 0b0..Free running mode disabled - * 0b1..Free running mode enabled - */ -#define SCG_SPLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_FRM_SHIFT)) & SCG_SPLLCTRL_FRM_MASK) - #define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) #define SCG_SPLLCTRL_SOURCE_SHIFT (25U) /*! SOURCE - Clock Source * 0b00..SOSC * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. - * 0b10..ROSC + * 0b10..Reserved * 0b11..No clock */ #define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) @@ -72447,14 +65930,6 @@ typedef struct { * 0b1..The postdivider (P) ratio change is accepted by the analog PLL */ #define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) - -#define SCG_SPLLSTAT_FRMDET_MASK (0x10U) -#define SCG_SPLLSTAT_FRMDET_SHIFT (4U) -/*! FRMDET - Free running detector (active high) - * 0b0..Free running is not detected - * 0b1..Free running is detected - */ -#define SCG_SPLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_FRMDET_SHIFT)) & SCG_SPLLSTAT_FRMDET_MASK) /*! @} */ /*! @name SPLLNDIV - SPLL N Divider Register */ @@ -72719,68 +66194,6 @@ typedef struct { #define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) /*! @} */ -/*! @name TROCSR - TRO Control Status Register */ -/*! @{ */ - -#define SCG_TROCSR_TROCM_MASK (0x10000U) -#define SCG_TROCSR_TROCM_SHIFT (16U) -/*! TROCM - TRO Clock Monitor - * 0b0..TRO Clock Monitor is disabled - * 0b1..TRO Clock Monitor is enabled - */ -#define SCG_TROCSR_TROCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCM_SHIFT)) & SCG_TROCSR_TROCM_MASK) - -#define SCG_TROCSR_TROCMRE_MASK (0x20000U) -#define SCG_TROCSR_TROCMRE_SHIFT (17U) -/*! TROCMRE - TRO Clock Monitor Reset Enable - * 0b0..Clock monitor generates an interrupt when an error is detected - * 0b1..Clock monitor generates a reset when an error is detected - */ -#define SCG_TROCSR_TROCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCMRE_SHIFT)) & SCG_TROCSR_TROCMRE_MASK) - -#define SCG_TROCSR_TRO_REFCLK_SEL_MASK (0xC0000U) -#define SCG_TROCSR_TRO_REFCLK_SEL_SHIFT (18U) -/*! TRO_REFCLK_SEL - TRO reference clock selection - * 0b00..SOSC - * 0b01..SIRC - * 0b10..FIRC (144 MHz or 48 MHz, based on RANGE selection) - * 0b11..Reserved - */ -#define SCG_TROCSR_TRO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TRO_REFCLK_SEL_SHIFT)) & SCG_TROCSR_TRO_REFCLK_SEL_MASK) - -#define SCG_TROCSR_LK_MASK (0x800000U) -#define SCG_TROCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written - * 0b1..Control Status Register cannot be written - */ -#define SCG_TROCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_LK_SHIFT)) & SCG_TROCSR_LK_MASK) - -#define SCG_TROCSR_TROVLD_MASK (0x1000000U) -#define SCG_TROCSR_TROVLD_SHIFT (24U) -/*! TROVLD - TRO Valid - * 0b0..TRO is not enabled or clock is not valid - * 0b1..TRO is enabled and output clock is valid - */ -#define SCG_TROCSR_TROVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROVLD_SHIFT)) & SCG_TROCSR_TROVLD_MASK) - -#define SCG_TROCSR_TROSEL_MASK (0x2000000U) -#define SCG_TROCSR_TROSEL_SHIFT (25U) -/*! TROSEL - TRO Selected - * 0b0..TRO is not the system clock source - * 0b1..TRO is the system clock source - */ -#define SCG_TROCSR_TROSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROSEL_SHIFT)) & SCG_TROCSR_TROSEL_MASK) - -#define SCG_TROCSR_TROERR_MASK (0x4000000U) -#define SCG_TROCSR_TROERR_SHIFT (26U) -/*! TROERR - TRO Clock Error - * 0b0..TRO clock monitor is disabled or has not detected an error - * 0b1..TRO clock monitor is enabled and detected an error - */ -#define SCG_TROCSR_TROERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROERR_SHIFT)) & SCG_TROCSR_TROERR_MASK) -/*! @} */ - /*! * @} @@ -74983,10 +68396,10 @@ typedef struct { /*! @name FRACMATREL - Fractional Match Reload */ /*! @{ */ -#define SCT_FRACMATREL_FRACMAT_L_MASK (0xFU) -#define SCT_FRACMATREL_FRACMAT_L_SHIFT (0U) -/*! FRACMAT_L - Reload Fractional Match Low */ -#define SCT_FRACMATREL_FRACMAT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_FRACMAT_L_SHIFT)) & SCT_FRACMATREL_FRACMAT_L_MASK) +#define SCT_FRACMATREL_RELFRAC_L_MASK (0xFU) +#define SCT_FRACMATREL_RELFRAC_L_SHIFT (0U) +/*! RELFRAC_L - Reload Fractional Match Low */ +#define SCT_FRACMATREL_RELFRAC_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_L_SHIFT)) & SCT_FRACMATREL_RELFRAC_L_MASK) #define SCT_FRACMATREL_RELFRAC_H_MASK (0xF0000U) #define SCT_FRACMATREL_RELFRAC_H_SHIFT (16U) @@ -75185,8 +68598,8 @@ typedef struct { __IO uint8_t GATE12; /**< Gate, offset: 0xF */ uint8_t RESERVED_0[50]; union { /* offset: 0x42 */ - __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ - __O uint16_t W; /**< Reset Gate Write, offset: 0x42 */ + __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ + __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ }; } SEMA42_Type; @@ -75615,21 +69028,21 @@ typedef struct { #define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) /*! @} */ -/*! @name R - Reset Gate Read */ +/*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ -#define SEMA42_R_RSTGTN_MASK (0xFFU) -#define SEMA42_R_RSTGTN_SHIFT (0U) +#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ -#define SEMA42_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_R_RSTGTN_SHIFT)) & SEMA42_R_RSTGTN_MASK) +#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) -#define SEMA42_R_RSTGMS_MASK (0xF00U) -#define SEMA42_R_RSTGMS_SHIFT (8U) +#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) +#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) /*! RSTGMS - Reset Gate Domain */ -#define SEMA42_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_R_RSTGMS_SHIFT)) & SEMA42_R_RSTGMS_MASK) +#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) -#define SEMA42_R_RSTGSM_MASK (0x3000U) -#define SEMA42_R_RSTGSM_SHIFT (12U) +#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) +#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) /*! RSTGSM - Reset Gate Finite State Machine * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write @@ -75637,21 +69050,21 @@ typedef struct { * this machine returns to the idle (waiting for first data pattern write) state. * 0b11..This state encoding is never used and therefore reserved. */ -#define SEMA42_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_R_RSTGSM_SHIFT)) & SEMA42_R_RSTGSM_MASK) +#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) /*! @} */ -/*! @name W - Reset Gate Write */ +/*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ -#define SEMA42_W_RSTGTN_MASK (0xFFU) -#define SEMA42_W_RSTGTN_SHIFT (0U) +#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ -#define SEMA42_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_W_RSTGTN_SHIFT)) & SEMA42_W_RSTGTN_MASK) +#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) -#define SEMA42_W_RSTGDP_MASK (0xFF00U) -#define SEMA42_W_RSTGDP_SHIFT (8U) +#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) +#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) /*! RSTGDP - Reset Gate Data Pattern */ -#define SEMA42_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_W_RSTGDP_SHIFT)) & SEMA42_W_RSTGDP_MASK) +#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) /*! @} */ @@ -77062,75 +70475,75 @@ typedef struct { #define SINC_SR_MCLKRDY2(x) (((uint32_t)(((uint32_t)(x)) << SINC_SR_MCLKRDY2_SHIFT)) & SINC_SR_MCLKRDY2_MASK) /*! @} */ -/*! @name CHANNEL_CCR - Channel 0 Control..Channel 4 Control */ +/*! @name CCR - Channel 0 Control..Channel 4 Control */ /*! @{ */ -#define SINC_CHANNEL_CCR_CHEN_MASK (0x1U) -#define SINC_CHANNEL_CCR_CHEN_SHIFT (0U) +#define SINC_CCR_CHEN_MASK (0x1U) +#define SINC_CCR_CHEN_SHIFT (0U) /*! CHEN - Channel Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_CHEN_SHIFT)) & SINC_CHANNEL_CCR_CHEN_MASK) +#define SINC_CCR_CHEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CHEN_SHIFT)) & SINC_CCR_CHEN_MASK) -#define SINC_CHANNEL_CCR_PFEN_MASK (0x2U) -#define SINC_CHANNEL_CCR_PFEN_SHIFT (1U) +#define SINC_CCR_PFEN_MASK (0x2U) +#define SINC_CCR_PFEN_SHIFT (1U) /*! PFEN - PF Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_PFEN_SHIFT)) & SINC_CHANNEL_CCR_PFEN_MASK) +#define SINC_CCR_PFEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_PFEN_SHIFT)) & SINC_CCR_PFEN_MASK) -#define SINC_CHANNEL_CCR_DMAEN_MASK (0x8U) -#define SINC_CHANNEL_CCR_DMAEN_SHIFT (3U) +#define SINC_CCR_DMAEN_MASK (0x8U) +#define SINC_CCR_DMAEN_SHIFT (3U) /*! DMAEN - DMA Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_DMAEN_SHIFT)) & SINC_CHANNEL_CCR_DMAEN_MASK) +#define SINC_CCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DMAEN_SHIFT)) & SINC_CCR_DMAEN_MASK) -#define SINC_CHANNEL_CCR_SCDEN_MASK (0x100U) -#define SINC_CHANNEL_CCR_SCDEN_SHIFT (8U) +#define SINC_CCR_SCDEN_MASK (0x100U) +#define SINC_CCR_SCDEN_SHIFT (8U) /*! SCDEN - Short Circuit Detect Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_SCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_SCDEN_SHIFT)) & SINC_CHANNEL_CCR_SCDEN_MASK) +#define SINC_CCR_SCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_SCDEN_SHIFT)) & SINC_CCR_SCDEN_MASK) -#define SINC_CHANNEL_CCR_CADEN_MASK (0x200U) -#define SINC_CHANNEL_CCR_CADEN_SHIFT (9U) +#define SINC_CCR_CADEN_MASK (0x200U) +#define SINC_CCR_CADEN_SHIFT (9U) /*! CADEN - Clock Absence Detect Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_CADEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_CADEN_SHIFT)) & SINC_CHANNEL_CCR_CADEN_MASK) +#define SINC_CCR_CADEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_CADEN_SHIFT)) & SINC_CCR_CADEN_MASK) -#define SINC_CHANNEL_CCR_ZCDEN_MASK (0x1000U) -#define SINC_CHANNEL_CCR_ZCDEN_SHIFT (12U) +#define SINC_CCR_ZCDEN_MASK (0x1000U) +#define SINC_CCR_ZCDEN_SHIFT (12U) /*! ZCDEN - Zero Cross Detect Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_ZCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_ZCDEN_SHIFT)) & SINC_CHANNEL_CCR_ZCDEN_MASK) +#define SINC_CCR_ZCDEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_ZCDEN_SHIFT)) & SINC_CCR_ZCDEN_MASK) -#define SINC_CHANNEL_CCR_LMTEN_MASK (0x2000U) -#define SINC_CHANNEL_CCR_LMTEN_SHIFT (13U) +#define SINC_CCR_LMTEN_MASK (0x2000U) +#define SINC_CCR_LMTEN_SHIFT (13U) /*! LMTEN - Limit Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_LMTEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_LMTEN_SHIFT)) & SINC_CHANNEL_CCR_LMTEN_MASK) +#define SINC_CCR_LMTEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_LMTEN_SHIFT)) & SINC_CCR_LMTEN_MASK) -#define SINC_CHANNEL_CCR_FIFOEN_MASK (0x4000U) -#define SINC_CHANNEL_CCR_FIFOEN_SHIFT (14U) +#define SINC_CCR_FIFOEN_MASK (0x4000U) +#define SINC_CCR_FIFOEN_SHIFT (14U) /*! FIFOEN - FIFO Enable * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_FIFOEN_SHIFT)) & SINC_CHANNEL_CCR_FIFOEN_MASK) +#define SINC_CCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_FIFOEN_SHIFT)) & SINC_CCR_FIFOEN_MASK) -#define SINC_CHANNEL_CCR_DBGSEL_MASK (0xF00000U) -#define SINC_CHANNEL_CCR_DBGSEL_SHIFT (20U) +#define SINC_CCR_DBGSEL_MASK (0xF00000U) +#define SINC_CCR_DBGSEL_SHIFT (20U) /*! DBGSEL - Debug Output Selection * 0b0000..Final data from the PF (24 bits) * 0b0001..Offset data (24 bits) @@ -77144,77 +70557,77 @@ typedef struct { * 0b1010..Status of the parallel or serial data converter * *.. */ -#define SINC_CHANNEL_CCR_DBGSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCR_DBGSEL_SHIFT)) & SINC_CHANNEL_CCR_DBGSEL_MASK) +#define SINC_CCR_DBGSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCR_DBGSEL_SHIFT)) & SINC_CCR_DBGSEL_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CCR */ -#define SINC_CHANNEL_CCR_COUNT (5U) +/* The count of SINC_CCR */ +#define SINC_CCR_COUNT (5U) -/*! @name CHANNEL_CDR - Channel 0 Data Rate..Channel 4 Data Rate */ +/*! @name CDR - Channel 0 Data Rate..Channel 4 Data Rate */ /*! @{ */ -#define SINC_CHANNEL_CDR_PFOSR_MASK (0x7FFU) -#define SINC_CHANNEL_CDR_PFOSR_SHIFT (0U) +#define SINC_CDR_PFOSR_MASK (0x7FFU) +#define SINC_CDR_PFOSR_SHIFT (0U) /*! PFOSR - PF OSR */ -#define SINC_CHANNEL_CDR_PFOSR(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDR_PFOSR_SHIFT)) & SINC_CHANNEL_CDR_PFOSR_MASK) +#define SINC_CDR_PFOSR(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFOSR_SHIFT)) & SINC_CDR_PFOSR_MASK) -#define SINC_CHANNEL_CDR_PFORD_MASK (0x1800U) -#define SINC_CHANNEL_CDR_PFORD_SHIFT (11U) +#define SINC_CDR_PFORD_MASK (0x1800U) +#define SINC_CDR_PFORD_SHIFT (11U) /*! PFORD - PF Order * 0b00..FastSinc * 0b01..First order * 0b10..Second order * 0b11..Third order */ -#define SINC_CHANNEL_CDR_PFORD(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDR_PFORD_SHIFT)) & SINC_CHANNEL_CDR_PFORD_MASK) +#define SINC_CDR_PFORD(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFORD_SHIFT)) & SINC_CDR_PFORD_MASK) -#define SINC_CHANNEL_CDR_PFCM_MASK (0xC000U) -#define SINC_CHANNEL_CDR_PFCM_SHIFT (14U) +#define SINC_CDR_PFCM_MASK (0xC000U) +#define SINC_CDR_PFCM_SHIFT (14U) /*! PFCM - PF Conversion Mode * 0b00..Single * 0b01..Continuous * 0b10..Always * 0b11..Fixed number */ -#define SINC_CHANNEL_CDR_PFCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDR_PFCM_SHIFT)) & SINC_CHANNEL_CDR_PFCM_MASK) +#define SINC_CDR_PFCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDR_PFCM_SHIFT)) & SINC_CDR_PFCM_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CDR */ -#define SINC_CHANNEL_CDR_COUNT (5U) +/* The count of SINC_CDR */ +#define SINC_CDR_COUNT (5U) -/*! @name CHANNEL_CCFR - Channel 0 Configuration..Channel 4 Configuration */ +/*! @name CCFR - Channel 0 Configuration..Channel 4 Configuration */ /*! @{ */ -#define SINC_CHANNEL_CCFR_PFSFT_MASK (0x1FU) -#define SINC_CHANNEL_CCFR_PFSFT_SHIFT (0U) +#define SINC_CCFR_PFSFT_MASK (0x1FU) +#define SINC_CCFR_PFSFT_SHIFT (0U) /*! PFSFT - PF Shift */ -#define SINC_CHANNEL_CCFR_PFSFT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_PFSFT_SHIFT)) & SINC_CHANNEL_CCFR_PFSFT_MASK) +#define SINC_CCFR_PFSFT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_PFSFT_SHIFT)) & SINC_CCFR_PFSFT_MASK) -#define SINC_CHANNEL_CCFR_RDFMT_MASK (0x40U) -#define SINC_CHANNEL_CCFR_RDFMT_SHIFT (6U) +#define SINC_CCFR_RDFMT_MASK (0x40U) +#define SINC_CCFR_RDFMT_SHIFT (6U) /*! RDFMT - Result Data Format * 0b0..Left justified, signed * 0b1..Left justified, unsigned */ -#define SINC_CHANNEL_CCFR_RDFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_RDFMT_SHIFT)) & SINC_CHANNEL_CCFR_RDFMT_MASK) +#define SINC_CCFR_RDFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_RDFMT_SHIFT)) & SINC_CCFR_RDFMT_MASK) -#define SINC_CHANNEL_CCFR_FIFOWMK_MASK (0x1C00U) -#define SINC_CHANNEL_CCFR_FIFOWMK_SHIFT (10U) +#define SINC_CCFR_FIFOWMK_MASK (0x1C00U) +#define SINC_CCFR_FIFOWMK_SHIFT (10U) /*! FIFOWMK - FIFO Watermark */ -#define SINC_CHANNEL_CCFR_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_FIFOWMK_SHIFT)) & SINC_CHANNEL_CCFR_FIFOWMK_MASK) +#define SINC_CCFR_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_FIFOWMK_SHIFT)) & SINC_CCFR_FIFOWMK_MASK) -#define SINC_CHANNEL_CCFR_IBFMT_MASK (0x30000U) -#define SINC_CHANNEL_CCFR_IBFMT_SHIFT (16U) +#define SINC_CCFR_IBFMT_MASK (0x30000U) +#define SINC_CCFR_IBFMT_SHIFT (16U) /*! IBFMT - Input Bit Format * 0b00..External bitstream from the MBIT[n] signal * 0b01..External Manchester code; ICESEL selects the rise or fall decoder * 0b10..Internal 16-bit parallel data from MPDATA * 0b11..Internal 32-bit serial data from MPDATA */ -#define SINC_CHANNEL_CCFR_IBFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_IBFMT_SHIFT)) & SINC_CHANNEL_CCFR_IBFMT_MASK) +#define SINC_CCFR_IBFMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBFMT_SHIFT)) & SINC_CCFR_IBFMT_MASK) -#define SINC_CHANNEL_CCFR_ICSEL_MASK (0x1C0000U) -#define SINC_CHANNEL_CCFR_ICSEL_SHIFT (18U) +#define SINC_CCFR_ICSEL_MASK (0x1C0000U) +#define SINC_CCFR_ICSEL_SHIFT (18U) /*! ICSEL - Input Clock Select * 0b000..MCLK_OUT0 with internal routeback * 0b001..MCLK_OUT1 with internal routeback @@ -77223,10 +70636,10 @@ typedef struct { * 0b111..Grouped clock shared with an adjacent channel; the adjacent channel's ICSEL field determines the input clock * *.. */ -#define SINC_CHANNEL_CCFR_ICSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ICSEL_SHIFT)) & SINC_CHANNEL_CCFR_ICSEL_MASK) +#define SINC_CCFR_ICSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICSEL_SHIFT)) & SINC_CCFR_ICSEL_MASK) -#define SINC_CHANNEL_CCFR_ICESEL_MASK (0xE00000U) -#define SINC_CHANNEL_CCFR_ICESEL_SHIFT (21U) +#define SINC_CCFR_ICESEL_MASK (0xE00000U) +#define SINC_CCFR_ICESEL_SHIFT (21U) /*! ICESEL - Input Clock Edge Select * 0b001..Positive edge * 0b010..Negative edge @@ -77237,206 +70650,206 @@ typedef struct { * 0b111..Every other even negative edge * *.. */ -#define SINC_CHANNEL_CCFR_ICESEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ICESEL_SHIFT)) & SINC_CHANNEL_CCFR_ICESEL_MASK) +#define SINC_CCFR_ICESEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ICESEL_SHIFT)) & SINC_CCFR_ICESEL_MASK) -#define SINC_CHANNEL_CCFR_ITSEL_MASK (0x3000000U) -#define SINC_CHANNEL_CCFR_ITSEL_SHIFT (24U) +#define SINC_CCFR_ITSEL_MASK (0x3000000U) +#define SINC_CCFR_ITSEL_SHIFT (24U) /*! ITSEL - Input Trigger Select * 0b00..Software * 0b01..Hardware trigger dedicated to the channel * 0b11..Grouped trigger shared with an adjacent channel; the adjacent channel's ITSEL field determines the trigger * *.. */ -#define SINC_CHANNEL_CCFR_ITSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ITSEL_SHIFT)) & SINC_CHANNEL_CCFR_ITSEL_MASK) +#define SINC_CCFR_ITSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITSEL_SHIFT)) & SINC_CCFR_ITSEL_MASK) -#define SINC_CHANNEL_CCFR_IBSEL_MASK (0xC000000U) -#define SINC_CHANNEL_CCFR_IBSEL_SHIFT (26U) +#define SINC_CCFR_IBSEL_MASK (0xC000000U) +#define SINC_CCFR_IBSEL_SHIFT (26U) /*! IBSEL - Input Bit Select * 0b00..External bitstream from the MBIT[n] signal * 0b01..Alternate internal bitstream from the INP[n] signal * 0b11..Grouped bitstream shared with an adjacent channel; the adjacent channel's IBSEL field determines the input * *.. */ -#define SINC_CHANNEL_CCFR_IBSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_IBSEL_SHIFT)) & SINC_CHANNEL_CCFR_IBSEL_MASK) +#define SINC_CCFR_IBSEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_IBSEL_SHIFT)) & SINC_CCFR_IBSEL_MASK) -#define SINC_CHANNEL_CCFR_ITLVL_MASK (0x10000000U) -#define SINC_CHANNEL_CCFR_ITLVL_SHIFT (28U) +#define SINC_CCFR_ITLVL_MASK (0x10000000U) +#define SINC_CCFR_ITLVL_SHIFT (28U) /*! ITLVL - Input Trigger Level Type * 0b0..Edge * 0b1..Level */ -#define SINC_CHANNEL_CCFR_ITLVL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ITLVL_SHIFT)) & SINC_CHANNEL_CCFR_ITLVL_MASK) +#define SINC_CCFR_ITLVL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ITLVL_SHIFT)) & SINC_CCFR_ITLVL_MASK) -#define SINC_CHANNEL_CCFR_ZCOP_MASK (0xC0000000U) -#define SINC_CHANNEL_CCFR_ZCOP_SHIFT (30U) +#define SINC_CCFR_ZCOP_MASK (0xC0000000U) +#define SINC_CCFR_ZCOP_SHIFT (30U) /*! ZCOP - Zero Cross Option * 0b00..Both rise and fall * 0b10..Rise * 0b01..Fall * *.. */ -#define SINC_CHANNEL_CCFR_ZCOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CCFR_ZCOP_SHIFT)) & SINC_CHANNEL_CCFR_ZCOP_MASK) +#define SINC_CCFR_ZCOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CCFR_ZCOP_SHIFT)) & SINC_CCFR_ZCOP_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CCFR */ -#define SINC_CHANNEL_CCFR_COUNT (5U) +/* The count of SINC_CCFR */ +#define SINC_CCFR_COUNT (5U) -/*! @name CHANNEL_CPROT - Channel 0 Protection..Channel 4 Protection */ +/*! @name CPROT - Channel 0 Protection..Channel 4 Protection */ /*! @{ */ -#define SINC_CHANNEL_CPROT_SCDLMT_MASK (0xFFU) -#define SINC_CHANNEL_CPROT_SCDLMT_SHIFT (0U) +#define SINC_CPROT_SCDLMT_MASK (0xFFU) +#define SINC_CPROT_SCDLMT_SHIFT (0U) /*! SCDLMT - SCD Limit Threshold * 0b00000000-0b00000001..Disables SCD * *..Threshold value */ -#define SINC_CHANNEL_CPROT_SCDLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDLMT_SHIFT)) & SINC_CHANNEL_CPROT_SCDLMT_MASK) +#define SINC_CPROT_SCDLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDLMT_SHIFT)) & SINC_CPROT_SCDLMT_MASK) -#define SINC_CHANNEL_CPROT_SCDCM_MASK (0x800U) -#define SINC_CHANNEL_CPROT_SCDCM_SHIFT (11U) +#define SINC_CPROT_SCDCM_MASK (0x800U) +#define SINC_CPROT_SCDCM_SHIFT (11U) /*! SCDCM - SCD Conversion Mode * 0b0..Constantly when CnCR[CHEN] = MCR[MEN] = 1 * 0b1..Only when the PF is performing a conversion */ -#define SINC_CHANNEL_CPROT_SCDCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDCM_SHIFT)) & SINC_CHANNEL_CPROT_SCDCM_MASK) +#define SINC_CPROT_SCDCM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDCM_SHIFT)) & SINC_CPROT_SCDCM_MASK) -#define SINC_CHANNEL_CPROT_SCDOP_MASK (0x3000U) -#define SINC_CHANNEL_CPROT_SCDOP_SHIFT (12U) +#define SINC_CPROT_SCDOP_MASK (0x3000U) +#define SINC_CPROT_SCDOP_SHIFT (12U) /*! SCDOP - SCD Option * 0b00..Both 0 and 1 * 0b01..Only 1 * 0b10..Only 0 * 0b11.. */ -#define SINC_CHANNEL_CPROT_SCDOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDOP_SHIFT)) & SINC_CHANNEL_CPROT_SCDOP_MASK) +#define SINC_CPROT_SCDOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDOP_SHIFT)) & SINC_CPROT_SCDOP_MASK) -#define SINC_CHANNEL_CPROT_LMTOP_MASK (0xC000U) -#define SINC_CHANNEL_CPROT_LMTOP_SHIFT (14U) +#define SINC_CPROT_LMTOP_MASK (0xC000U) +#define SINC_CPROT_LMTOP_SHIFT (14U) /*! LMTOP - Limit Detection Option * 0b00..Both high and low limits * 0b01..High limit * 0b10..Low limit * 0b11..Windowed value */ -#define SINC_CHANNEL_CPROT_LMTOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_LMTOP_SHIFT)) & SINC_CHANNEL_CPROT_LMTOP_MASK) +#define SINC_CPROT_LMTOP(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LMTOP_SHIFT)) & SINC_CPROT_LMTOP_MASK) -#define SINC_CHANNEL_CPROT_CADLMT_MASK (0xF0000U) -#define SINC_CHANNEL_CPROT_CADLMT_SHIFT (16U) +#define SINC_CPROT_CADLMT_MASK (0xF0000U) +#define SINC_CPROT_CADLMT_SHIFT (16U) /*! CADLMT - CAD Limit Threshold * 0b0000..Disables CAD * *..Threshold value */ -#define SINC_CHANNEL_CPROT_CADLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_CADLMT_SHIFT)) & SINC_CHANNEL_CPROT_CADLMT_MASK) +#define SINC_CPROT_CADLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADLMT_SHIFT)) & SINC_CPROT_CADLMT_MASK) -#define SINC_CHANNEL_CPROT_CADBK_MASK (0x4000000U) -#define SINC_CHANNEL_CPROT_CADBK_SHIFT (26U) +#define SINC_CPROT_CADBK_MASK (0x4000000U) +#define SINC_CPROT_CADBK_SHIFT (26U) /*! CADBK - CAD Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_CADBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_CADBK_SHIFT)) & SINC_CHANNEL_CPROT_CADBK_MASK) +#define SINC_CPROT_CADBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_CADBK_SHIFT)) & SINC_CPROT_CADBK_MASK) -#define SINC_CHANNEL_CPROT_SCDBK_MASK (0x8000000U) -#define SINC_CHANNEL_CPROT_SCDBK_SHIFT (27U) +#define SINC_CPROT_SCDBK_MASK (0x8000000U) +#define SINC_CPROT_SCDBK_SHIFT (27U) /*! SCDBK - SCD Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_SCDBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_SCDBK_SHIFT)) & SINC_CHANNEL_CPROT_SCDBK_MASK) +#define SINC_CPROT_SCDBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_SCDBK_SHIFT)) & SINC_CPROT_SCDBK_MASK) -#define SINC_CHANNEL_CPROT_LLMTBK_MASK (0x20000000U) -#define SINC_CHANNEL_CPROT_LLMTBK_SHIFT (29U) +#define SINC_CPROT_LLMTBK_MASK (0x20000000U) +#define SINC_CPROT_LLMTBK_SHIFT (29U) /*! LLMTBK - Low Limit Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_LLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_LLMTBK_SHIFT)) & SINC_CHANNEL_CPROT_LLMTBK_MASK) +#define SINC_CPROT_LLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_LLMTBK_SHIFT)) & SINC_CPROT_LLMTBK_MASK) -#define SINC_CHANNEL_CPROT_WLMTBK_MASK (0x40000000U) -#define SINC_CHANNEL_CPROT_WLMTBK_SHIFT (30U) +#define SINC_CPROT_WLMTBK_MASK (0x40000000U) +#define SINC_CPROT_WLMTBK_SHIFT (30U) /*! WLMTBK - Window Limit Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_WLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_WLMTBK_SHIFT)) & SINC_CHANNEL_CPROT_WLMTBK_MASK) +#define SINC_CPROT_WLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_WLMTBK_SHIFT)) & SINC_CPROT_WLMTBK_MASK) -#define SINC_CHANNEL_CPROT_HLMTBK_MASK (0x80000000U) -#define SINC_CHANNEL_CPROT_HLMTBK_SHIFT (31U) +#define SINC_CPROT_HLMTBK_MASK (0x80000000U) +#define SINC_CPROT_HLMTBK_SHIFT (31U) /*! HLMTBK - High Limit Break Signal * 0b0..Disables * 0b1..Enables */ -#define SINC_CHANNEL_CPROT_HLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CPROT_HLMTBK_SHIFT)) & SINC_CHANNEL_CPROT_HLMTBK_MASK) +#define SINC_CPROT_HLMTBK(x) (((uint32_t)(((uint32_t)(x)) << SINC_CPROT_HLMTBK_SHIFT)) & SINC_CPROT_HLMTBK_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CPROT */ -#define SINC_CHANNEL_CPROT_COUNT (5U) +/* The count of SINC_CPROT */ +#define SINC_CPROT_COUNT (5U) -/*! @name CHANNEL_CBIAS - Channel 0 Bias..Channel 4 Bias */ +/*! @name CBIAS - Channel 0 Bias..Channel 4 Bias */ /*! @{ */ -#define SINC_CHANNEL_CBIAS_BIAS_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CBIAS_BIAS_SHIFT (8U) +#define SINC_CBIAS_BIAS_MASK (0xFFFFFF00U) +#define SINC_CBIAS_BIAS_SHIFT (8U) /*! BIAS - Bias Value */ -#define SINC_CHANNEL_CBIAS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CBIAS_BIAS_SHIFT)) & SINC_CHANNEL_CBIAS_BIAS_MASK) +#define SINC_CBIAS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CBIAS_BIAS_SHIFT)) & SINC_CBIAS_BIAS_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CBIAS */ -#define SINC_CHANNEL_CBIAS_COUNT (5U) +/* The count of SINC_CBIAS */ +#define SINC_CBIAS_COUNT (5U) -/*! @name CHANNEL_CLOLMT - Channel 0 Low Limit..Channel 4 Low Limit */ +/*! @name CLOLMT - Channel 0 Low Limit..Channel 4 Low Limit */ /*! @{ */ -#define SINC_CHANNEL_CLOLMT_LOLMT_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CLOLMT_LOLMT_SHIFT (8U) +#define SINC_CLOLMT_LOLMT_MASK (0xFFFFFF00U) +#define SINC_CLOLMT_LOLMT_SHIFT (8U) /*! LOLMT - Low Limit Threshold */ -#define SINC_CHANNEL_CLOLMT_LOLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CLOLMT_LOLMT_SHIFT)) & SINC_CHANNEL_CLOLMT_LOLMT_MASK) +#define SINC_CLOLMT_LOLMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CLOLMT_LOLMT_SHIFT)) & SINC_CLOLMT_LOLMT_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CLOLMT */ -#define SINC_CHANNEL_CLOLMT_COUNT (5U) +/* The count of SINC_CLOLMT */ +#define SINC_CLOLMT_COUNT (5U) -/*! @name CHANNEL_CHILMT - Channel 0 High Limit..Channel 4 High Limit */ +/*! @name CHILMT - Channel 0 High Limit..Channel 4 High Limit */ /*! @{ */ -#define SINC_CHANNEL_CHILMT_HILMT_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CHILMT_HILMT_SHIFT (8U) +#define SINC_CHILMT_HILMT_MASK (0xFFFFFF00U) +#define SINC_CHILMT_HILMT_SHIFT (8U) /*! HILMT - High Limit Threshold */ -#define SINC_CHANNEL_CHILMT_HILMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CHILMT_HILMT_SHIFT)) & SINC_CHANNEL_CHILMT_HILMT_MASK) +#define SINC_CHILMT_HILMT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHILMT_HILMT_SHIFT)) & SINC_CHILMT_HILMT_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CHILMT */ -#define SINC_CHANNEL_CHILMT_COUNT (5U) +/* The count of SINC_CHILMT */ +#define SINC_CHILMT_COUNT (5U) -/*! @name CHANNEL_CRDATA - Channel 0 Result Data..Channel 4 Result Data */ +/*! @name CRDATA - Channel 0 Result Data..Channel 4 Result Data */ /*! @{ */ -#define SINC_CHANNEL_CRDATA_RDATA_MASK (0xFFFFFF00U) -#define SINC_CHANNEL_CRDATA_RDATA_SHIFT (8U) +#define SINC_CRDATA_RDATA_MASK (0xFFFFFF00U) +#define SINC_CRDATA_RDATA_SHIFT (8U) /*! RDATA - Result Data */ -#define SINC_CHANNEL_CRDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CRDATA_RDATA_SHIFT)) & SINC_CHANNEL_CRDATA_RDATA_MASK) +#define SINC_CRDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CRDATA_RDATA_SHIFT)) & SINC_CRDATA_RDATA_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CRDATA */ -#define SINC_CHANNEL_CRDATA_COUNT (5U) +/* The count of SINC_CRDATA */ +#define SINC_CRDATA_COUNT (5U) -/*! @name CHANNEL_CMPDATA - Channel 0 Multipurpose Data..Channel 4 Multipurpose Data */ +/*! @name CMPDATA - Channel 0 Multipurpose Data..Channel 4 Multipurpose Data */ /*! @{ */ -#define SINC_CHANNEL_CMPDATA_MPDATA_MASK (0xFFFFFFFFU) -#define SINC_CHANNEL_CMPDATA_MPDATA_SHIFT (0U) +#define SINC_CMPDATA_MPDATA_MASK (0xFFFFFFFFU) +#define SINC_CMPDATA_MPDATA_SHIFT (0U) /*! MPDATA - Multipurpose Data */ -#define SINC_CHANNEL_CMPDATA_MPDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CMPDATA_MPDATA_SHIFT)) & SINC_CHANNEL_CMPDATA_MPDATA_MASK) +#define SINC_CMPDATA_MPDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CMPDATA_MPDATA_SHIFT)) & SINC_CMPDATA_MPDATA_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CMPDATA */ -#define SINC_CHANNEL_CMPDATA_COUNT (5U) +/* The count of SINC_CMPDATA */ +#define SINC_CMPDATA_COUNT (5U) -/*! @name CHANNEL_CACFR - Channel 0 Advanced Configuration..Channel 4 Advanced Configuration */ +/*! @name CACFR - Channel 0 Advanced Configuration..Channel 4 Advanced Configuration */ /*! @{ */ -#define SINC_CHANNEL_CACFR_ADMASEL_MASK (0xF000U) -#define SINC_CHANNEL_CACFR_ADMASEL_SHIFT (12U) +#define SINC_CACFR_ADMASEL_MASK (0xF000U) +#define SINC_CACFR_ADMASEL_SHIFT (12U) /*! ADMASEL - Alternate DMA Source Selection * 0b0000..Alternate DMA disabled * 0b0001..PF conversion complete @@ -77451,127 +70864,127 @@ typedef struct { * 0b1010..Clock absence * 0b1011..Saturation */ -#define SINC_CHANNEL_CACFR_ADMASEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CACFR_ADMASEL_SHIFT)) & SINC_CHANNEL_CACFR_ADMASEL_MASK) +#define SINC_CACFR_ADMASEL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_ADMASEL_SHIFT)) & SINC_CACFR_ADMASEL_MASK) -#define SINC_CHANNEL_CACFR_HPFA_MASK (0xF0000U) -#define SINC_CHANNEL_CACFR_HPFA_SHIFT (16U) +#define SINC_CACFR_HPFA_MASK (0xF0000U) +#define SINC_CACFR_HPFA_SHIFT (16U) /*! HPFA - HPF DC Remover Alpha Coefficient */ -#define SINC_CHANNEL_CACFR_HPFA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CACFR_HPFA_SHIFT)) & SINC_CHANNEL_CACFR_HPFA_MASK) +#define SINC_CACFR_HPFA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_HPFA_SHIFT)) & SINC_CACFR_HPFA_MASK) -#define SINC_CHANNEL_CACFR_IBDLY_MASK (0xF00000U) -#define SINC_CHANNEL_CACFR_IBDLY_SHIFT (20U) +#define SINC_CACFR_IBDLY_MASK (0xF00000U) +#define SINC_CACFR_IBDLY_SHIFT (20U) /*! IBDLY - Input Modulator Bitstream Delay * 0b0000..Disabled * *..Delay in clock cycles */ -#define SINC_CHANNEL_CACFR_IBDLY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CACFR_IBDLY_SHIFT)) & SINC_CHANNEL_CACFR_IBDLY_MASK) +#define SINC_CACFR_IBDLY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CACFR_IBDLY_SHIFT)) & SINC_CACFR_IBDLY_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CACFR */ -#define SINC_CHANNEL_CACFR_COUNT (5U) +/* The count of SINC_CACFR */ +#define SINC_CACFR_COUNT (5U) -/*! @name CHANNEL_CSR - Channel 0 Status..Channel 4 Status */ +/*! @name CSR - Channel 0 Status..Channel 4 Status */ /*! @{ */ -#define SINC_CHANNEL_CSR_FIFOAVIL_MASK (0x1FU) -#define SINC_CHANNEL_CSR_FIFOAVIL_SHIFT (0U) +#define SINC_CSR_FIFOAVIL_MASK (0x1FU) +#define SINC_CSR_FIFOAVIL_SHIFT (0U) /*! FIFOAVIL - FIFO Available Data */ -#define SINC_CHANNEL_CSR_FIFOAVIL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_FIFOAVIL_SHIFT)) & SINC_CHANNEL_CSR_FIFOAVIL_MASK) +#define SINC_CSR_FIFOAVIL(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_FIFOAVIL_SHIFT)) & SINC_CSR_FIFOAVIL_MASK) -#define SINC_CHANNEL_CSR_PSRDY_MASK (0x80U) -#define SINC_CHANNEL_CSR_PSRDY_SHIFT (7U) +#define SINC_CSR_PSRDY_MASK (0x80U) +#define SINC_CSR_PSRDY_SHIFT (7U) /*! PSRDY - Parallel or Serial Data Ready * 0b0..Not ready * 0b1..Ready */ -#define SINC_CHANNEL_CSR_PSRDY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_PSRDY_SHIFT)) & SINC_CHANNEL_CSR_PSRDY_MASK) +#define SINC_CSR_PSRDY(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PSRDY_SHIFT)) & SINC_CSR_PSRDY_MASK) -#define SINC_CHANNEL_CSR_PFSAT_MASK (0x100U) -#define SINC_CHANNEL_CSR_PFSAT_SHIFT (8U) +#define SINC_CSR_PFSAT_MASK (0x100U) +#define SINC_CSR_PFSAT_SHIFT (8U) /*! PFSAT - Primary CIC Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_PFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_PFSAT_SHIFT)) & SINC_CHANNEL_CSR_PFSAT_MASK) +#define SINC_CSR_PFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_PFSAT_SHIFT)) & SINC_CSR_PFSAT_MASK) -#define SINC_CHANNEL_CSR_HPFSAT_MASK (0x200U) -#define SINC_CHANNEL_CSR_HPFSAT_SHIFT (9U) +#define SINC_CSR_HPFSAT_MASK (0x200U) +#define SINC_CSR_HPFSAT_SHIFT (9U) /*! HPFSAT - HPF Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_HPFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_HPFSAT_SHIFT)) & SINC_CHANNEL_CSR_HPFSAT_MASK) +#define SINC_CSR_HPFSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_HPFSAT_SHIFT)) & SINC_CSR_HPFSAT_MASK) -#define SINC_CHANNEL_CSR_SFTSAT_MASK (0x400U) -#define SINC_CHANNEL_CSR_SFTSAT_SHIFT (10U) +#define SINC_CSR_SFTSAT_MASK (0x400U) +#define SINC_CSR_SFTSAT_SHIFT (10U) /*! SFTSAT - Shift Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_SFTSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_SFTSAT_SHIFT)) & SINC_CHANNEL_CSR_SFTSAT_MASK) +#define SINC_CSR_SFTSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SFTSAT_SHIFT)) & SINC_CSR_SFTSAT_MASK) -#define SINC_CHANNEL_CSR_BIASSAT_MASK (0x800U) -#define SINC_CHANNEL_CSR_BIASSAT_SHIFT (11U) +#define SINC_CSR_BIASSAT_MASK (0x800U) +#define SINC_CSR_BIASSAT_SHIFT (11U) /*! BIASSAT - Bias Saturation Flag * 0b0..Did not occur * 0b1..Occurred */ -#define SINC_CHANNEL_CSR_BIASSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_BIASSAT_SHIFT)) & SINC_CHANNEL_CSR_BIASSAT_MASK) +#define SINC_CSR_BIASSAT(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_BIASSAT_SHIFT)) & SINC_CSR_BIASSAT_MASK) -#define SINC_CHANNEL_CSR_RDRS_MASK (0x1000U) -#define SINC_CHANNEL_CSR_RDRS_SHIFT (12U) +#define SINC_CSR_RDRS_MASK (0x1000U) +#define SINC_CSR_RDRS_SHIFT (12U) /*! RDRS - Result Data Direct Read Status * 0b0..Valid * 0b1..Invalid */ -#define SINC_CHANNEL_CSR_RDRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_RDRS_SHIFT)) & SINC_CHANNEL_CSR_RDRS_MASK) +#define SINC_CSR_RDRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_RDRS_SHIFT)) & SINC_CSR_RDRS_MASK) -#define SINC_CHANNEL_CSR_SRDS_MASK (0x2000U) -#define SINC_CHANNEL_CSR_SRDS_SHIFT (13U) +#define SINC_CSR_SRDS_MASK (0x2000U) +#define SINC_CSR_SRDS_SHIFT (13U) /*! SRDS - Start Read Debug Data Sync * 0b0..Data valid * 0b1..Procedure in progress * 0b0..No effect * 0b1..Starts the procedure */ -#define SINC_CHANNEL_CSR_SRDS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_SRDS_SHIFT)) & SINC_CHANNEL_CSR_SRDS_MASK) +#define SINC_CSR_SRDS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_SRDS_SHIFT)) & SINC_CSR_SRDS_MASK) -#define SINC_CHANNEL_CSR_DBGRS_MASK (0xC000U) -#define SINC_CHANNEL_CSR_DBGRS_SHIFT (14U) +#define SINC_CSR_DBGRS_MASK (0xC000U) +#define SINC_CSR_DBGRS_SHIFT (14U) /*! DBGRS - Debug Data Read Status * 0b00..Valid * 0b01-0b11..Invalid */ -#define SINC_CHANNEL_CSR_DBGRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_DBGRS_SHIFT)) & SINC_CHANNEL_CSR_DBGRS_MASK) +#define SINC_CSR_DBGRS(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_DBGRS_SHIFT)) & SINC_CSR_DBGRS_MASK) -#define SINC_CHANNEL_CSR_CNUM_MASK (0x7F0000U) -#define SINC_CHANNEL_CSR_CNUM_SHIFT (16U) +#define SINC_CSR_CNUM_MASK (0x7F0000U) +#define SINC_CSR_CNUM_SHIFT (16U) /*! CNUM - Number Of Conversions */ -#define SINC_CHANNEL_CSR_CNUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_CNUM_SHIFT)) & SINC_CHANNEL_CSR_CNUM_MASK) +#define SINC_CSR_CNUM(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_SHIFT)) & SINC_CSR_CNUM_MASK) -#define SINC_CHANNEL_CSR_CNUM_OV_MASK (0x800000U) -#define SINC_CHANNEL_CSR_CNUM_OV_SHIFT (23U) +#define SINC_CSR_CNUM_OV_MASK (0x800000U) +#define SINC_CSR_CNUM_OV_SHIFT (23U) /*! CNUM_OV - Overflow In Number Of Conversions * 0b0..No overflow * 0b1..Overflow */ -#define SINC_CHANNEL_CSR_CNUM_OV(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CSR_CNUM_OV_SHIFT)) & SINC_CHANNEL_CSR_CNUM_OV_MASK) +#define SINC_CSR_CNUM_OV(x) (((uint32_t)(((uint32_t)(x)) << SINC_CSR_CNUM_OV_SHIFT)) & SINC_CSR_CNUM_OV_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CSR */ -#define SINC_CHANNEL_CSR_COUNT (5U) +/* The count of SINC_CSR */ +#define SINC_CSR_COUNT (5U) -/*! @name CHANNEL_CDBGR - Channel 0 Debug..Channel 4 Debug */ +/*! @name CDBGR - Channel 0 Debug..Channel 4 Debug */ /*! @{ */ -#define SINC_CHANNEL_CDBGR_DBGDATA_MASK (0xFFFFFFFFU) -#define SINC_CHANNEL_CDBGR_DBGDATA_SHIFT (0U) +#define SINC_CDBGR_DBGDATA_MASK (0xFFFFFFFFU) +#define SINC_CDBGR_DBGDATA_SHIFT (0U) /*! DBGDATA - Debug Data */ -#define SINC_CHANNEL_CDBGR_DBGDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CHANNEL_CDBGR_DBGDATA_SHIFT)) & SINC_CHANNEL_CDBGR_DBGDATA_MASK) +#define SINC_CDBGR_DBGDATA(x) (((uint32_t)(((uint32_t)(x)) << SINC_CDBGR_DBGDATA_SHIFT)) & SINC_CDBGR_DBGDATA_MASK) /*! @} */ -/* The count of SINC_CHANNEL_CDBGR */ -#define SINC_CHANNEL_CDBGR_COUNT (5U) +/* The count of SINC_CDBGR */ +#define SINC_CDBGR_COUNT (5U) /*! @@ -77613,580 +71026,6 @@ typedef struct { */ /* end of group SINC_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- SM3 Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SM3_Peripheral_Access_Layer SM3 Peripheral Access Layer - * @{ - */ - -/** SM3 - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[512]; - __IO uint32_t DATIN0A; /**< Input Data register 0 lower-bank low, offset: 0x200 */ - __IO uint32_t DATIN0B; /**< Input Data register 0 lower-bank high, offset: 0x204 */ - __IO uint32_t DATIN0C; /**< Input Data register 0 upper-bank low, offset: 0x208 */ - __IO uint32_t DATIN0D; /**< Input Data register 0 upper-bank high, offset: 0x20C */ - __IO uint32_t DATIN1A; /**< Input Data register 1 lower-bank low, offset: 0x210 */ - __IO uint32_t DATIN1B; /**< Input Data register 1 lower-bank high, offset: 0x214 */ - __IO uint32_t DATIN1C; /**< Input Data register 1 upper-bank low, offset: 0x218 */ - __IO uint32_t DATIN1D; /**< Input Data register 1 upper-bank high, offset: 0x21C */ - uint8_t RESERVED_1[32]; - __IO uint32_t KEY0A; /**< Input Key register 0 lower-bank low, offset: 0x240 */ - __IO uint32_t KEY0B; /**< Input Key register 0 lower-bank high, offset: 0x244 */ - __IO uint32_t KEY0C; /**< Input Key register 0 upper-bank low, offset: 0x248 */ - __IO uint32_t KEY0D; /**< Input Key register 0 upper-bank high, offset: 0x24C */ - __IO uint32_t KEY1A; /**< Input Key register 1 lower-bank low, offset: 0x250 */ - __IO uint32_t KEY1B; /**< Input Key register 1 lower-bank high, offset: 0x254 */ - __IO uint32_t KEY1C; /**< Input Key register 1 upper-bank low, offset: 0x258 */ - __IO uint32_t KEY1D; /**< Input Key register 1 upper-bank high, offset: 0x25C */ - uint8_t RESERVED_2[96]; - __I uint32_t DATOUTA; /**< Output Data register lower-bank low, offset: 0x2C0 */ - __I uint32_t DATOUTB; /**< Ouput Data register lower-bank high, offset: 0x2C4 */ - __I uint32_t DATOUTC; /**< Ouput Data register upper-bank low, offset: 0x2C8 */ - __I uint32_t DATOUTD; /**< Output Data register upper-bank high, offset: 0x2CC */ - uint8_t RESERVED_3[2352]; - __I uint32_t STATUS; /**< Status Register, offset: 0xC00 */ - __IO uint32_t COUNT; /**< Calculation Counter, offset: 0xC04 */ - uint8_t RESERVED_4[248]; - __IO uint32_t CTRL; /**< SGI Control Register, offset: 0xD00 */ - __IO uint32_t CTRL2; /**< SGI Control Register 2, offset: 0xD04 */ - uint8_t RESERVED_5[12]; - __IO uint32_t SM3_CTRL; /**< SM3 Control Register, offset: 0xD14 */ - __O uint32_t SM3_FIFO; /**< SM3 FIFO Register, offset: 0xD18 */ - __I uint32_t CONFIG; /**< SGI Configuration Register, offset: 0xD1C */ - uint8_t RESERVED_6[708]; - __IO uint32_t INT_ENABLE; /**< Interrupt Enable, offset: 0xFE4 */ - __O uint32_t INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0xFE8 */ - __O uint32_t INT_STATUS_SET; /**< Interrupt Status Set, offset: 0xFEC */ -} SM3_Type; - -/* ---------------------------------------------------------------------------- - -- SM3 Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SM3_Register_Masks SM3 Register Masks - * @{ - */ - -/*! @name DATIN0A - Input Data register 0 lower-bank low */ -/*! @{ */ - -#define SM3_DATIN0A_DATIN0A_MASK (0xFFFFFFFFU) -#define SM3_DATIN0A_DATIN0A_SHIFT (0U) -/*! DATIN0A - Input Data register */ -#define SM3_DATIN0A_DATIN0A(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0A_DATIN0A_SHIFT)) & SM3_DATIN0A_DATIN0A_MASK) -/*! @} */ - -/*! @name DATIN0B - Input Data register 0 lower-bank high */ -/*! @{ */ - -#define SM3_DATIN0B_DATIN0B_MASK (0xFFFFFFFFU) -#define SM3_DATIN0B_DATIN0B_SHIFT (0U) -/*! DATIN0B - Input Data register */ -#define SM3_DATIN0B_DATIN0B(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0B_DATIN0B_SHIFT)) & SM3_DATIN0B_DATIN0B_MASK) -/*! @} */ - -/*! @name DATIN0C - Input Data register 0 upper-bank low */ -/*! @{ */ - -#define SM3_DATIN0C_DATIN0C_MASK (0xFFFFFFFFU) -#define SM3_DATIN0C_DATIN0C_SHIFT (0U) -/*! DATIN0C - Input Data register */ -#define SM3_DATIN0C_DATIN0C(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0C_DATIN0C_SHIFT)) & SM3_DATIN0C_DATIN0C_MASK) -/*! @} */ - -/*! @name DATIN0D - Input Data register 0 upper-bank high */ -/*! @{ */ - -#define SM3_DATIN0D_DATIN0D_MASK (0xFFFFFFFFU) -#define SM3_DATIN0D_DATIN0D_SHIFT (0U) -/*! DATIN0D - Input Data register */ -#define SM3_DATIN0D_DATIN0D(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN0D_DATIN0D_SHIFT)) & SM3_DATIN0D_DATIN0D_MASK) -/*! @} */ - -/*! @name DATIN1A - Input Data register 1 lower-bank low */ -/*! @{ */ - -#define SM3_DATIN1A_DATIN1A_MASK (0xFFFFFFFFU) -#define SM3_DATIN1A_DATIN1A_SHIFT (0U) -/*! DATIN1A - Input Data register */ -#define SM3_DATIN1A_DATIN1A(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1A_DATIN1A_SHIFT)) & SM3_DATIN1A_DATIN1A_MASK) -/*! @} */ - -/*! @name DATIN1B - Input Data register 1 lower-bank high */ -/*! @{ */ - -#define SM3_DATIN1B_DATIN1B_MASK (0xFFFFFFFFU) -#define SM3_DATIN1B_DATIN1B_SHIFT (0U) -/*! DATIN1B - Input Data register */ -#define SM3_DATIN1B_DATIN1B(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1B_DATIN1B_SHIFT)) & SM3_DATIN1B_DATIN1B_MASK) -/*! @} */ - -/*! @name DATIN1C - Input Data register 1 upper-bank low */ -/*! @{ */ - -#define SM3_DATIN1C_DATIN1C_MASK (0xFFFFFFFFU) -#define SM3_DATIN1C_DATIN1C_SHIFT (0U) -/*! DATIN1C - Input Data register */ -#define SM3_DATIN1C_DATIN1C(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1C_DATIN1C_SHIFT)) & SM3_DATIN1C_DATIN1C_MASK) -/*! @} */ - -/*! @name DATIN1D - Input Data register 1 upper-bank high */ -/*! @{ */ - -#define SM3_DATIN1D_DATIN1D_MASK (0xFFFFFFFFU) -#define SM3_DATIN1D_DATIN1D_SHIFT (0U) -/*! DATIN1D - Input Data register */ -#define SM3_DATIN1D_DATIN1D(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATIN1D_DATIN1D_SHIFT)) & SM3_DATIN1D_DATIN1D_MASK) -/*! @} */ - -/*! @name KEY0A - Input Key register 0 lower-bank low */ -/*! @{ */ - -#define SM3_KEY0A_KEY0A_MASK (0xFFFFFFFFU) -#define SM3_KEY0A_KEY0A_SHIFT (0U) -/*! KEY0A - Input Key register */ -#define SM3_KEY0A_KEY0A(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0A_KEY0A_SHIFT)) & SM3_KEY0A_KEY0A_MASK) -/*! @} */ - -/*! @name KEY0B - Input Key register 0 lower-bank high */ -/*! @{ */ - -#define SM3_KEY0B_KEY0B_MASK (0xFFFFFFFFU) -#define SM3_KEY0B_KEY0B_SHIFT (0U) -/*! KEY0B - Input Key register */ -#define SM3_KEY0B_KEY0B(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0B_KEY0B_SHIFT)) & SM3_KEY0B_KEY0B_MASK) -/*! @} */ - -/*! @name KEY0C - Input Key register 0 upper-bank low */ -/*! @{ */ - -#define SM3_KEY0C_KEY0C_MASK (0xFFFFFFFFU) -#define SM3_KEY0C_KEY0C_SHIFT (0U) -/*! KEY0C - Input Key register */ -#define SM3_KEY0C_KEY0C(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0C_KEY0C_SHIFT)) & SM3_KEY0C_KEY0C_MASK) -/*! @} */ - -/*! @name KEY0D - Input Key register 0 upper-bank high */ -/*! @{ */ - -#define SM3_KEY0D_KEY0D_MASK (0xFFFFFFFFU) -#define SM3_KEY0D_KEY0D_SHIFT (0U) -/*! KEY0D - Input Key register */ -#define SM3_KEY0D_KEY0D(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY0D_KEY0D_SHIFT)) & SM3_KEY0D_KEY0D_MASK) -/*! @} */ - -/*! @name KEY1A - Input Key register 1 lower-bank low */ -/*! @{ */ - -#define SM3_KEY1A_KEY1A_MASK (0xFFFFFFFFU) -#define SM3_KEY1A_KEY1A_SHIFT (0U) -/*! KEY1A - Input Key register */ -#define SM3_KEY1A_KEY1A(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1A_KEY1A_SHIFT)) & SM3_KEY1A_KEY1A_MASK) -/*! @} */ - -/*! @name KEY1B - Input Key register 1 lower-bank high */ -/*! @{ */ - -#define SM3_KEY1B_KEY1B_MASK (0xFFFFFFFFU) -#define SM3_KEY1B_KEY1B_SHIFT (0U) -/*! KEY1B - Input Key register */ -#define SM3_KEY1B_KEY1B(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1B_KEY1B_SHIFT)) & SM3_KEY1B_KEY1B_MASK) -/*! @} */ - -/*! @name KEY1C - Input Key register 1 upper-bank low */ -/*! @{ */ - -#define SM3_KEY1C_KEY1C_MASK (0xFFFFFFFFU) -#define SM3_KEY1C_KEY1C_SHIFT (0U) -/*! KEY1C - Input Key register */ -#define SM3_KEY1C_KEY1C(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1C_KEY1C_SHIFT)) & SM3_KEY1C_KEY1C_MASK) -/*! @} */ - -/*! @name KEY1D - Input Key register 1 upper-bank high */ -/*! @{ */ - -#define SM3_KEY1D_KEY1D_MASK (0xFFFFFFFFU) -#define SM3_KEY1D_KEY1D_SHIFT (0U) -/*! KEY1D - Input Key register */ -#define SM3_KEY1D_KEY1D(x) (((uint32_t)(((uint32_t)(x)) << SM3_KEY1D_KEY1D_SHIFT)) & SM3_KEY1D_KEY1D_MASK) -/*! @} */ - -/*! @name DATOUTA - Output Data register lower-bank low */ -/*! @{ */ - -#define SM3_DATOUTA_DATOUTA_MASK (0xFFFFFFFFU) -#define SM3_DATOUTA_DATOUTA_SHIFT (0U) -/*! DATOUTA - Output Data register */ -#define SM3_DATOUTA_DATOUTA(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTA_DATOUTA_SHIFT)) & SM3_DATOUTA_DATOUTA_MASK) -/*! @} */ - -/*! @name DATOUTB - Ouput Data register lower-bank high */ -/*! @{ */ - -#define SM3_DATOUTB_DATOUTB_MASK (0xFFFFFFFFU) -#define SM3_DATOUTB_DATOUTB_SHIFT (0U) -/*! DATOUTB - Ouput Data register */ -#define SM3_DATOUTB_DATOUTB(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTB_DATOUTB_SHIFT)) & SM3_DATOUTB_DATOUTB_MASK) -/*! @} */ - -/*! @name DATOUTC - Ouput Data register upper-bank low */ -/*! @{ */ - -#define SM3_DATOUTC_DATOUTC_MASK (0xFFFFFFFFU) -#define SM3_DATOUTC_DATOUTC_SHIFT (0U) -/*! DATOUTC - Ouput Data register */ -#define SM3_DATOUTC_DATOUTC(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTC_DATOUTC_SHIFT)) & SM3_DATOUTC_DATOUTC_MASK) -/*! @} */ - -/*! @name DATOUTD - Output Data register upper-bank high */ -/*! @{ */ - -#define SM3_DATOUTD_DOUTD_MASK (0xFFFFFFFFU) -#define SM3_DATOUTD_DOUTD_SHIFT (0U) -/*! DOUTD - Output Data register */ -#define SM3_DATOUTD_DOUTD(x) (((uint32_t)(((uint32_t)(x)) << SM3_DATOUTD_DOUTD_SHIFT)) & SM3_DATOUTD_DOUTD_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ - -#define SM3_STATUS_BUSY_MASK (0x1U) -#define SM3_STATUS_BUSY_SHIFT (0U) -/*! BUSY - Busy Flag */ -#define SM3_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_BUSY_SHIFT)) & SM3_STATUS_BUSY_MASK) - -#define SM3_STATUS_PRNG_RDY_MASK (0x4U) -#define SM3_STATUS_PRNG_RDY_SHIFT (2U) -/*! PRNG_RDY - PRNG Ready */ -#define SM3_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_PRNG_RDY_SHIFT)) & SM3_STATUS_PRNG_RDY_MASK) - -#define SM3_STATUS_ERROR_MASK (0x38U) -#define SM3_STATUS_ERROR_SHIFT (3U) -/*! ERROR - Error Indicator */ -#define SM3_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_ERROR_SHIFT)) & SM3_STATUS_ERROR_MASK) - -#define SM3_STATUS_SM3_BUSY_MASK (0x40U) -#define SM3_STATUS_SM3_BUSY_SHIFT (6U) -/*! SM3_BUSY - SM3 Busy Status Flag */ -#define SM3_STATUS_SM3_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_BUSY_SHIFT)) & SM3_STATUS_SM3_BUSY_MASK) - -#define SM3_STATUS_IRQ_MASK (0x80U) -#define SM3_STATUS_IRQ_SHIFT (7U) -/*! IRQ - Interrupt Status Flag */ -#define SM3_STATUS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_IRQ_SHIFT)) & SM3_STATUS_IRQ_MASK) - -#define SM3_STATUS_SM3_FIFO_FULL_MASK (0x100U) -#define SM3_STATUS_SM3_FIFO_FULL_SHIFT (8U) -/*! SM3_FIFO_FULL - SM3 FIFO Full Indicator */ -#define SM3_STATUS_SM3_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_FIFO_FULL_SHIFT)) & SM3_STATUS_SM3_FIFO_FULL_MASK) - -#define SM3_STATUS_SM3_FIFO_LEVEL_MASK (0x7E00U) -#define SM3_STATUS_SM3_FIFO_LEVEL_SHIFT (9U) -/*! SM3_FIFO_LEVEL - SM3 FIFO Level */ -#define SM3_STATUS_SM3_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_FIFO_LEVEL_SHIFT)) & SM3_STATUS_SM3_FIFO_LEVEL_MASK) - -#define SM3_STATUS_SM3_ERROR_MASK (0x8000U) -#define SM3_STATUS_SM3_ERROR_SHIFT (15U) -/*! SM3_ERROR - SM3 ERROR */ -#define SM3_STATUS_SM3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SM3_STATUS_SM3_ERROR_SHIFT)) & SM3_STATUS_SM3_ERROR_MASK) -/*! @} */ - -/*! @name COUNT - Calculation Counter */ -/*! @{ */ - -#define SM3_COUNT_COUNT_MASK (0xFFFFU) -#define SM3_COUNT_COUNT_SHIFT (0U) -/*! COUNT - Calculation Counter */ -#define SM3_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SM3_COUNT_COUNT_SHIFT)) & SM3_COUNT_COUNT_MASK) -/*! @} */ - -/*! @name CTRL - SGI Control Register */ -/*! @{ */ - -#define SM3_CTRL_START_MASK (0x1U) -#define SM3_CTRL_START_SHIFT (0U) -/*! START - Start Crypto Operation */ -#define SM3_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL_START_SHIFT)) & SM3_CTRL_START_MASK) - -#define SM3_CTRL_CRYPTO_OP_MASK (0x70U) -#define SM3_CTRL_CRYPTO_OP_SHIFT (4U) -/*! CRYPTO_OP - Crypto Operation Type */ -#define SM3_CTRL_CRYPTO_OP(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL_CRYPTO_OP_SHIFT)) & SM3_CTRL_CRYPTO_OP_MASK) - -#define SM3_CTRL_DATOUT_RES_MASK (0xC000U) -#define SM3_CTRL_DATOUT_RES_SHIFT (14U) -/*! DATOUT_RES - Kernels Data Out Options */ -#define SM3_CTRL_DATOUT_RES(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL_DATOUT_RES_SHIFT)) & SM3_CTRL_DATOUT_RES_MASK) -/*! @} */ - -/*! @name CTRL2 - SGI Control Register 2 */ -/*! @{ */ - -#define SM3_CTRL2_FLUSH_MASK (0x1U) -#define SM3_CTRL2_FLUSH_SHIFT (0U) -/*! FLUSH - Start Full SGI Flush */ -#define SM3_CTRL2_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_FLUSH_SHIFT)) & SM3_CTRL2_FLUSH_MASK) - -#define SM3_CTRL2_KEY_FLUSH_MASK (0x2U) -#define SM3_CTRL2_KEY_FLUSH_SHIFT (1U) -/*! KEY_FLUSH - Start KEY register-bank Flush */ -#define SM3_CTRL2_KEY_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_KEY_FLUSH_SHIFT)) & SM3_CTRL2_KEY_FLUSH_MASK) - -#define SM3_CTRL2_DATIN_FLUSH_MASK (0x4U) -#define SM3_CTRL2_DATIN_FLUSH_SHIFT (2U) -/*! DATIN_FLUSH - Start DATIN register-bank Flush */ -#define SM3_CTRL2_DATIN_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_DATIN_FLUSH_SHIFT)) & SM3_CTRL2_DATIN_FLUSH_MASK) - -#define SM3_CTRL2_FLUSHWR_MASK (0x20U) -#define SM3_CTRL2_FLUSHWR_SHIFT (5U) -/*! FLUSHWR - Flush Write control */ -#define SM3_CTRL2_FLUSHWR(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_FLUSHWR_SHIFT)) & SM3_CTRL2_FLUSHWR_MASK) - -#define SM3_CTRL2_BYTES_ORDER_MASK (0x400000U) -#define SM3_CTRL2_BYTES_ORDER_SHIFT (22U) -/*! BYTES_ORDER - Byte order of regbank read/write data */ -#define SM3_CTRL2_BYTES_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SM3_CTRL2_BYTES_ORDER_SHIFT)) & SM3_CTRL2_BYTES_ORDER_MASK) -/*! @} */ - -/*! @name SM3_CTRL - SM3 Control Register */ -/*! @{ */ - -#define SM3_SM3_CTRL_SM3_MODE_MASK (0x2U) -#define SM3_SM3_CTRL_SM3_MODE_SHIFT (1U) -/*! SM3_MODE - SM3 mode normal or automatic */ -#define SM3_SM3_CTRL_SM3_MODE(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_MODE_SHIFT)) & SM3_SM3_CTRL_SM3_MODE_MASK) - -#define SM3_SM3_CTRL_SM3_LOW_LIM_MASK (0xF0U) -#define SM3_SM3_CTRL_SM3_LOW_LIM_SHIFT (4U) -/*! SM3_LOW_LIM - SM3 FIFO low limit */ -#define SM3_SM3_CTRL_SM3_LOW_LIM(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_LOW_LIM_SHIFT)) & SM3_SM3_CTRL_SM3_LOW_LIM_MASK) - -#define SM3_SM3_CTRL_SM3_HIGH_LIM_MASK (0xF00U) -#define SM3_SM3_CTRL_SM3_HIGH_LIM_SHIFT (8U) -/*! SM3_HIGH_LIM - SM3 FIFO high limit */ -#define SM3_SM3_CTRL_SM3_HIGH_LIM(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_HIGH_LIM_SHIFT)) & SM3_SM3_CTRL_SM3_HIGH_LIM_MASK) - -#define SM3_SM3_CTRL_SM3_COUNT_EN_MASK (0x1000U) -#define SM3_SM3_CTRL_SM3_COUNT_EN_SHIFT (12U) -/*! SM3_COUNT_EN - SM3 Calculation Counter Enable */ -#define SM3_SM3_CTRL_SM3_COUNT_EN(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_COUNT_EN_SHIFT)) & SM3_SM3_CTRL_SM3_COUNT_EN_MASK) - -#define SM3_SM3_CTRL_HASH_RELOAD_MASK (0x2000U) -#define SM3_SM3_CTRL_HASH_RELOAD_SHIFT (13U) -/*! HASH_RELOAD - SM3 HASH reload */ -#define SM3_SM3_CTRL_HASH_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_HASH_RELOAD_SHIFT)) & SM3_SM3_CTRL_HASH_RELOAD_MASK) - -#define SM3_SM3_CTRL_SM3_STOP_MASK (0x4000U) -#define SM3_SM3_CTRL_SM3_STOP_SHIFT (14U) -/*! SM3_STOP - STOP SM3 AUTO mode */ -#define SM3_SM3_CTRL_SM3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_STOP_SHIFT)) & SM3_SM3_CTRL_SM3_STOP_MASK) - -#define SM3_SM3_CTRL_NO_AUTO_INIT_MASK (0x8000U) -#define SM3_SM3_CTRL_NO_AUTO_INIT_SHIFT (15U) -/*! NO_AUTO_INIT - SM3 no automatic HASH initialisation. */ -#define SM3_SM3_CTRL_NO_AUTO_INIT(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_NO_AUTO_INIT_SHIFT)) & SM3_SM3_CTRL_NO_AUTO_INIT_MASK) - -#define SM3_SM3_CTRL_SM3_EN_MASK (0x10000U) -#define SM3_SM3_CTRL_SM3_EN_SHIFT (16U) -/*! SM3_EN - SM3 enable */ -#define SM3_SM3_CTRL_SM3_EN(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_CTRL_SM3_EN_SHIFT)) & SM3_SM3_CTRL_SM3_EN_MASK) -/*! @} */ - -/*! @name SM3_FIFO - SM3 FIFO Register */ -/*! @{ */ - -#define SM3_SM3_FIFO_FIFO_MASK (0xFFFFFFFFU) -#define SM3_SM3_FIFO_FIFO_SHIFT (0U) -/*! FIFO - SM3 FIFO Register */ -#define SM3_SM3_FIFO_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SM3_SM3_FIFO_FIFO_SHIFT)) & SM3_SM3_FIFO_FIFO_MASK) -/*! @} */ - -/*! @name CONFIG - SGI Configuration Register */ -/*! @{ */ - -#define SM3_CONFIG_ROW_MASK (0x1U) -#define SM3_CONFIG_ROW_SHIFT (0U) -/*! ROW - ROW */ -#define SM3_CONFIG_ROW(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_ROW_SHIFT)) & SM3_CONFIG_ROW_MASK) - -#define SM3_CONFIG_CHINA_MASK (0x2U) -#define SM3_CONFIG_CHINA_SHIFT (1U) -/*! CHINA - CHINA */ -#define SM3_CONFIG_CHINA(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_CHINA_SHIFT)) & SM3_CONFIG_CHINA_MASK) - -#define SM3_CONFIG_CC_MASK (0x4U) -#define SM3_CONFIG_CC_SHIFT (2U) -/*! CC - CC */ -#define SM3_CONFIG_CC(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_CC_SHIFT)) & SM3_CONFIG_CC_MASK) - -#define SM3_CONFIG_HAS_AES_MASK (0x8U) -#define SM3_CONFIG_HAS_AES_SHIFT (3U) -/*! HAS_AES - Has AES */ -#define SM3_CONFIG_HAS_AES(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_AES_SHIFT)) & SM3_CONFIG_HAS_AES_MASK) - -#define SM3_CONFIG_HAS_DES_MASK (0x10U) -#define SM3_CONFIG_HAS_DES_SHIFT (4U) -/*! HAS_DES - Has DES */ -#define SM3_CONFIG_HAS_DES(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_DES_SHIFT)) & SM3_CONFIG_HAS_DES_MASK) - -#define SM3_CONFIG_HAS_SHA_MASK (0x20U) -#define SM3_CONFIG_HAS_SHA_SHIFT (5U) -/*! HAS_SHA - Has SHA */ -#define SM3_CONFIG_HAS_SHA(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_SHA_SHIFT)) & SM3_CONFIG_HAS_SHA_MASK) - -#define SM3_CONFIG_HAS_MOVEM_MASK (0x40U) -#define SM3_CONFIG_HAS_MOVEM_SHIFT (6U) -/*! HAS_MOVEM - Has MOVEM */ -#define SM3_CONFIG_HAS_MOVEM(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_MOVEM_SHIFT)) & SM3_CONFIG_HAS_MOVEM_MASK) - -#define SM3_CONFIG_HAS_CMAC_MASK (0x80U) -#define SM3_CONFIG_HAS_CMAC_SHIFT (7U) -/*! HAS_CMAC - Has CMAC */ -#define SM3_CONFIG_HAS_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_CMAC_SHIFT)) & SM3_CONFIG_HAS_CMAC_MASK) - -#define SM3_CONFIG_HAS_GFMUL_MASK (0x100U) -#define SM3_CONFIG_HAS_GFMUL_SHIFT (8U) -/*! HAS_GFMUL - Has GFMUL */ -#define SM3_CONFIG_HAS_GFMUL(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_GFMUL_SHIFT)) & SM3_CONFIG_HAS_GFMUL_MASK) - -#define SM3_CONFIG_INTERNAL_PRNG_MASK (0x200U) -#define SM3_CONFIG_INTERNAL_PRNG_SHIFT (9U) -/*! INTERNAL_PRNG - Has internal PRNG */ -#define SM3_CONFIG_INTERNAL_PRNG(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_INTERNAL_PRNG_SHIFT)) & SM3_CONFIG_INTERNAL_PRNG_MASK) - -#define SM3_CONFIG_KEY_DIGEST_MASK (0x400U) -#define SM3_CONFIG_KEY_DIGEST_SHIFT (10U) -/*! KEY_DIGEST - Has key digest */ -#define SM3_CONFIG_KEY_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_KEY_DIGEST_SHIFT)) & SM3_CONFIG_KEY_DIGEST_MASK) - -#define SM3_CONFIG_MST_MASK (0x4000U) -#define SM3_CONFIG_MST_SHIFT (14U) -/*! MST - Has MST */ -#define SM3_CONFIG_MST(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_MST_SHIFT)) & SM3_CONFIG_MST_MASK) - -#define SM3_CONFIG_BUS_WIDTH_MASK (0x8000U) -#define SM3_CONFIG_BUS_WIDTH_SHIFT (15U) -/*! BUS_WIDTH - Bus width */ -#define SM3_CONFIG_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_BUS_WIDTH_SHIFT)) & SM3_CONFIG_BUS_WIDTH_MASK) - -#define SM3_CONFIG_NUM_DATIN_MASK (0x30000U) -#define SM3_CONFIG_NUM_DATIN_SHIFT (16U) -/*! NUM_DATIN - Number DATIN */ -#define SM3_CONFIG_NUM_DATIN(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_NUM_DATIN_SHIFT)) & SM3_CONFIG_NUM_DATIN_MASK) - -#define SM3_CONFIG_NUM_KEY_MASK (0x1C0000U) -#define SM3_CONFIG_NUM_KEY_SHIFT (18U) -/*! NUM_KEY - Number KEY */ -#define SM3_CONFIG_NUM_KEY(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_NUM_KEY_SHIFT)) & SM3_CONFIG_NUM_KEY_MASK) - -#define SM3_CONFIG_EDC_MASK (0x200000U) -#define SM3_CONFIG_EDC_SHIFT (21U) -/*! EDC - EDC enable */ -#define SM3_CONFIG_EDC(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_EDC_SHIFT)) & SM3_CONFIG_EDC_MASK) - -#define SM3_CONFIG_DUAL_SGI_MASK (0x400000U) -#define SM3_CONFIG_DUAL_SGI_SHIFT (22U) -/*! DUAL_SGI - Has dual SGI */ -#define SM3_CONFIG_DUAL_SGI(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_DUAL_SGI_SHIFT)) & SM3_CONFIG_DUAL_SGI_MASK) - -#define SM3_CONFIG_SHA_256_ONLY_MASK (0x1000000U) -#define SM3_CONFIG_SHA_256_ONLY_SHIFT (24U) -/*! SHA_256_ONLY - Has SHA 256 only */ -#define SM3_CONFIG_SHA_256_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SHA_256_ONLY_SHIFT)) & SM3_CONFIG_SHA_256_ONLY_MASK) - -#define SM3_CONFIG_SPB_SUPPORT_MASK (0x2000000U) -#define SM3_CONFIG_SPB_SUPPORT_SHIFT (25U) -/*! SPB_SUPPORT - ID_CFG_SPB_SUPPORT is set */ -#define SM3_CONFIG_SPB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SPB_SUPPORT_SHIFT)) & SM3_CONFIG_SPB_SUPPORT_MASK) - -#define SM3_CONFIG_SPB_MASKING_MASK (0x4000000U) -#define SM3_CONFIG_SPB_MASKING_SHIFT (26U) -/*! SPB_MASKING - ID_CFG_SGI_SPB_MASKING is set */ -#define SM3_CONFIG_SPB_MASKING(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SPB_MASKING_SHIFT)) & SM3_CONFIG_SPB_MASKING_MASK) - -#define SM3_CONFIG_SFR_SW_MASK_MASK (0x8000000U) -#define SM3_CONFIG_SFR_SW_MASK_SHIFT (27U) -/*! SFR_SW_MASK - ID_CFG_SGI_USE_SFR_SW_MASK is set */ -#define SM3_CONFIG_SFR_SW_MASK(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_SFR_SW_MASK_SHIFT)) & SM3_CONFIG_SFR_SW_MASK_MASK) - -#define SM3_CONFIG_HAS_SM3_MASK (0x10000000U) -#define SM3_CONFIG_HAS_SM3_SHIFT (28U) -/*! HAS_SM3 - Has SM3 */ -#define SM3_CONFIG_HAS_SM3(x) (((uint32_t)(((uint32_t)(x)) << SM3_CONFIG_HAS_SM3_SHIFT)) & SM3_CONFIG_HAS_SM3_MASK) -/*! @} */ - -/*! @name INT_ENABLE - Interrupt Enable */ -/*! @{ */ - -#define SM3_INT_ENABLE_INT_EN_MASK (0x1U) -#define SM3_INT_ENABLE_INT_EN_SHIFT (0U) -/*! INT_EN - Interrupt enable bit */ -#define SM3_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SM3_INT_ENABLE_INT_EN_SHIFT)) & SM3_INT_ENABLE_INT_EN_MASK) -/*! @} */ - -/*! @name INT_STATUS_CLR - Interrupt Status Clear */ -/*! @{ */ - -#define SM3_INT_STATUS_CLR_INT_CLR_MASK (0x1U) -#define SM3_INT_STATUS_CLR_INT_CLR_SHIFT (0U) -/*! INT_CLR - Interrupt Status Clear */ -#define SM3_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SM3_INT_STATUS_CLR_INT_CLR_SHIFT)) & SM3_INT_STATUS_CLR_INT_CLR_MASK) -/*! @} */ - -/*! @name INT_STATUS_SET - Interrupt Status Set */ -/*! @{ */ - -#define SM3_INT_STATUS_SET_INT_SET_MASK (0x1U) -#define SM3_INT_STATUS_SET_INT_SET_SHIFT (0U) -/*! INT_SET - Set Interrupt by SW */ -#define SM3_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << SM3_INT_STATUS_SET_INT_SET_SHIFT)) & SM3_INT_STATUS_SET_INT_SET_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SM3_Register_Masks */ - - -/* SM3 - Peripheral instance base addresses */ -#if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral SM3_0 base address */ - #define SM3_0_BASE (0x50031000u) - /** Peripheral SM3_0 base address */ - #define SM3_0_BASE_NS (0x40031000u) - /** Peripheral SM3_0 base pointer */ - #define SM3_0 ((SM3_Type *)SM3_0_BASE) - /** Peripheral SM3_0 base pointer */ - #define SM3_0_NS ((SM3_Type *)SM3_0_BASE_NS) - /** Array initializer of SM3 peripheral base addresses */ - #define SM3_BASE_ADDRS { SM3_0_BASE } - /** Array initializer of SM3 peripheral base pointers */ - #define SM3_BASE_PTRS { SM3_0 } - /** Array initializer of SM3 peripheral base addresses */ - #define SM3_BASE_ADDRS_NS { SM3_0_BASE_NS } - /** Array initializer of SM3 peripheral base pointers */ - #define SM3_BASE_PTRS_NS { SM3_0_NS } -#else - /** Peripheral SM3_0 base address */ - #define SM3_0_BASE (0x40031000u) - /** Peripheral SM3_0 base pointer */ - #define SM3_0 ((SM3_Type *)SM3_0_BASE) - /** Array initializer of SM3 peripheral base addresses */ - #define SM3_BASE_ADDRS { SM3_0_BASE } - /** Array initializer of SM3 peripheral base pointers */ - #define SM3_BASE_PTRS { SM3_0 } -#endif - -/*! - * @} - */ /* end of group SM3_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- SMARTDMA Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -78440,7 +71279,7 @@ typedef struct { __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ __IO uint32_t VD_IO_CFG; /**< IO Voltage Detect Configuration, offset: 0x13C */ __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ - __IO uint32_t VDD_CORE_GLITCH_DETECT_SC; /**< VDD Core Glitch Detect Status Control, offset: 0x144 */ + __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ uint8_t RESERVED_7[440]; __IO uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ uint8_t RESERVED_8[252]; @@ -78495,7 +71334,7 @@ typedef struct { #define SPC_SC_SPC_LP_REQ_MASK (0x2U) #define SPC_SC_SPC_LP_REQ_SHIFT (1U) /*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag - * 0b0..SPC is in Active mode; the ACTIVE_CFG register has control + * 0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register * 0b0..No effect * 0b1..Clear the flag @@ -78620,7 +71459,7 @@ typedef struct { * 0b00.. * 0b01..1.0 V * 0b10..1.1 V - * 0b11..SRAM configured for 1.2 V operation + * 0b11.. */ #define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) @@ -78699,9 +71538,9 @@ typedef struct { #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) -/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable - * 0b0..VDD Core Low Voltage Glitch Detect enabled - * 0b1..VDD Core Low Voltage Glitch Detect disabled +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Low Voltage Glitch Detect enabled + * 0b1..Low Voltage Glitch Detect disabled */ #define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) @@ -78803,11 +71642,10 @@ typedef struct { #define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) #define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level - * 0b00..Under voltage (0.95 V) + * 0b00..Retention voltage * 0b01..Mid voltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) - * *.. */ #define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) @@ -78832,8 +71670,7 @@ typedef struct { #define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) #define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level - * 0b00.. - * 0b00.. + * 0b00..Retention voltage (0.7 V) * 0b01..Mid voltage (1.0 V) * 0b10..Normal voltage (1.1 V) * 0b11..Overdrive voltage (1.2 V) @@ -78842,7 +71679,7 @@ typedef struct { #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) #define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) -/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable * 0b0..Enable * 0b1..Disable */ @@ -78963,7 +71800,7 @@ typedef struct { #define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) #define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) -/*! COREVDD_LVDF - Core VDD Low-Voltage Detect Flag +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect @@ -78973,7 +71810,7 @@ typedef struct { #define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) #define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) -/*! SYSVDD_LVDF - System VDD Low-Voltage Detect Flag +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect @@ -79003,7 +71840,7 @@ typedef struct { #define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) #define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) -/*! SYSVDD_HVDF - System VDD HVD Flag +/*! SYSVDD_HVDF - System HVD Flag * 0b0..Event not detected * 0b1..Event detected * 0b0..No effect @@ -79027,7 +71864,7 @@ typedef struct { #define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) #define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) -/*! LVDRE - Core VDD LVD Reset Enable +/*! LVDRE - Core LVD Reset Enable * 0b0..Disable * 0b1..Enable */ @@ -79035,7 +71872,7 @@ typedef struct { #define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) #define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) -/*! LVDIE - Core VDD LVD Interrupt Enable +/*! LVDIE - Core LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ @@ -79071,7 +71908,7 @@ typedef struct { #define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) #define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) -/*! LVDRE - System VDD LVD Reset Enable +/*! LVDRE - System LVD Reset Enable * 0b0..Disable * 0b1..Enable */ @@ -79079,7 +71916,7 @@ typedef struct { #define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) #define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) -/*! LVDIE - System VDD LVD Interrupt Enable +/*! LVDIE - System LVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ @@ -79087,7 +71924,7 @@ typedef struct { #define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) #define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) -/*! HVDRE - System VDD HVD Reset Enable +/*! HVDRE - System HVD Reset Enable * 0b0..Disable * 0b1..Enable */ @@ -79095,20 +71932,12 @@ typedef struct { #define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) #define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) -/*! HVDIE - System VDD HVD Interrupt Enable +/*! HVDIE - System HVD Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) -#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) -#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) -/*! LVSEL - System VDD Low-Voltage Level Select - * 0b0..Normal - * 0b1..Safe - */ -#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) - #define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) #define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) /*! LOCK - System Voltage Detect Reset Enable Lock @@ -79156,8 +71985,8 @@ typedef struct { #define SPC_VD_IO_CFG_LVSEL_MASK (0x100U) #define SPC_VD_IO_CFG_LVSEL_SHIFT (8U) /*! LVSEL - IO VDD Low-Voltage Level Select - * 0b0..Normal - * 0b1..Safe + * 0b0..High range + * 0b1..Low range */ #define SPC_VD_IO_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK) @@ -79189,52 +72018,52 @@ typedef struct { #define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) /*! @} */ -/*! @name VDD_CORE_GLITCH_DETECT_SC - VDD Core Glitch Detect Status Control */ +/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ /*! @{ */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) /*! CNT_SELECT - Counter Select * 0b00..0 * 0b01..1 * 0b10..2 * 0b11..3 */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) /*! TIMEOUT - Timeout */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK) +#define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK (0x40U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_SHIFT (6U) -/*! RE - Core VDD Glitch Detect Reset Enable +#define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) +#define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) +/*! RE - Glitch Detect Reset Enable * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK) +#define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK (0x80U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_SHIFT (7U) -/*! IE - Core VDD Glitch Detect Interrupt Enable +#define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) +#define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) +/*! IE - Glitch Detect Interrupt Enable * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK) +#define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) /*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) -#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_SHIFT (16U) -/*! LOCK - VDD Core Voltage Glitch Detect Reset Enable Lock Bit +#define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) +#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) +/*! LOCK - Glitch Detect Reset Enable Lock Bit * 0b0..Writes to RE are allowed. * 0b1..Writes to RE are ignored. */ -#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) +#define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) /*! @} */ /*! @name CORELDO_CFG - LDO_CORE Configuration */ @@ -79528,12 +72357,14 @@ typedef struct { __O uint32_t REF_CLK_CTRL_SET; /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */ __O uint32_t REF_CLK_CTRL_CLR; /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */ __IO uint32_t GDET_CTRL[2]; /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */ - uint8_t RESERVED_40[12]; + __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection Register, offset: 0x974 */ + __IO uint32_t ELS_LOCK_CTRL; /**< ELS Lock Control, offset: 0x978 */ + __IO uint32_t ELS_LOCK_CTRL_DP; /**< ELS Lock Control DP, offset: 0x97C */ __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0x980 */ __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0x984 */ __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0x988 */ __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0x98C */ - uint8_t RESERVED_41[64]; + uint8_t RESERVED_40[64]; __I uint32_t ELS_AS_CFG0; /**< ELS AS Configuration, offset: 0x9D0 */ __I uint32_t ELS_AS_CFG1; /**< ELS AS Configuration1, offset: 0x9D4 */ __I uint32_t ELS_AS_CFG2; /**< ELS AS Configuration2, offset: 0x9D8 */ @@ -79541,21 +72372,21 @@ typedef struct { __I uint32_t ELS_AS_ST0; /**< ELS AS State Register, offset: 0x9E0 */ __I uint32_t ELS_AS_ST1; /**< ELS AS State1, offset: 0x9E4 */ __I uint32_t ELS_AS_BOOT_LOG0; /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */ - __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: N-boot library log, offset: 0x9EC */ + __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: Library log, offset: 0x9EC */ __I uint32_t ELS_AS_BOOT_LOG2; /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */ __I uint32_t ELS_AS_BOOT_LOG3; /**< Boot state captured during boot: Security log, offset: 0x9F4 */ __I uint32_t ELS_AS_FLAG0; /**< ELS AS Flag0, offset: 0x9F8 */ __I uint32_t ELS_AS_FLAG1; /**< ELS AS Flag1, offset: 0x9FC */ - uint8_t RESERVED_42[24]; + uint8_t RESERVED_41[24]; __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ - uint8_t RESERVED_43[276]; + uint8_t RESERVED_42[276]; __IO uint32_t I3C1FCLKSEL; /**< I3C1 Functional Clock Selection, offset: 0xB30 */ __IO uint32_t I3C1FCLKSTCSEL; /**< Selects the I3C1 Time Control clock, offset: 0xB34 */ __IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ __IO uint32_t I3C1FCLKSDIV; /**< I3C1 FCLK Slow clock Divider, offset: 0xB3C */ __IO uint32_t I3C1FCLKDIV; /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */ __IO uint32_t I3C1FCLKSSEL; /**< I3C1 FCLK Slow Selection, offset: 0xB44 */ - uint8_t RESERVED_44[8]; + uint8_t RESERVED_43[8]; __IO uint32_t ETB_STATUS; /**< ETB Counter Status Register, offset: 0xB50 */ __IO uint32_t ETB_COUNTER_CTRL; /**< ETB Counter Control Register, offset: 0xB54 */ __IO uint32_t ETB_COUNTER_RELOAD; /**< ETB Counter Reload Register, offset: 0xB58 */ @@ -79564,25 +72395,25 @@ typedef struct { __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */ __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ - uint8_t RESERVED_45[660]; + uint8_t RESERVED_44[660]; __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control Automatic Clock Gating, offset: 0xE04 */ - uint8_t RESERVED_46[36]; + uint8_t RESERVED_45[36]; __IO uint32_t AUTOCLKGATEOVERRIDEC; /**< Control Automatic Clock Gating C, offset: 0xE2C */ - uint8_t RESERVED_47[8]; + uint8_t RESERVED_46[8]; __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0xE38 */ __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0xE3C */ __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0xE40 */ __IO uint32_t ECC_ENABLE_CTRL; /**< RAM ECC Enable Control, offset: 0xE44 */ - uint8_t RESERVED_48[344]; + uint8_t RESERVED_47[344]; __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ - uint8_t RESERVED_49[8]; + uint8_t RESERVED_48[8]; __IO uint32_t SWD_ACCESS_CPU[2]; /**< CPU0 Software Debug Access..CPU1 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ - uint8_t RESERVED_50[4]; + uint8_t RESERVED_49[4]; __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ __IO uint32_t SWD_ACCESS_DSP; /**< DSP Software Debug Access, offset: 0xFC4 */ - uint8_t RESERVED_51[40]; + uint8_t RESERVED_50[40]; __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ @@ -79818,13 +72649,17 @@ typedef struct { #define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) -/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is not exact or not given. */ +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ #define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) #define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) -/*! NOREF - Indicates whether the device provides a reference clock to the processor. 0 = reference - * clock is provided; 1 = no reference clock is provided. +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided */ #define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) /*! @} */ @@ -80418,21 +73253,21 @@ typedef struct { */ #define SYSCON_PRESETCTRL3_COOLFLUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_COOLFLUX_RST_SHIFT)) & SYSCON_PRESETCTRL3_COOLFLUX_RST_MASK) -#define SYSCON_PRESETCTRL3_ENC0_RST_MASK (0x10U) -#define SYSCON_PRESETCTRL3_ENC0_RST_SHIFT (4U) -/*! ENC0_RST - ENC0 reset control +#define SYSCON_PRESETCTRL3_QDC0_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT (4U) +/*! QDC0_RST - QDC0 reset control * 0b1..Block is reset * 0b0..Block is not reset */ -#define SYSCON_PRESETCTRL3_ENC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC0_RST_MASK) +#define SYSCON_PRESETCTRL3_QDC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK) -#define SYSCON_PRESETCTRL3_ENC1_RST_MASK (0x20U) -#define SYSCON_PRESETCTRL3_ENC1_RST_SHIFT (5U) -/*! ENC1_RST - ENC1 reset control +#define SYSCON_PRESETCTRL3_QDC1_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT (5U) +/*! QDC1_RST - QDC1 reset control * 0b1..Block is reset * 0b0..Block is not reset */ -#define SYSCON_PRESETCTRL3_ENC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC1_RST_MASK) +#define SYSCON_PRESETCTRL3_QDC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK) #define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x40U) #define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (6U) @@ -81266,21 +74101,21 @@ typedef struct { */ #define SYSCON_AHBCLKCTRL3_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_COOLFLUX_SHIFT)) & SYSCON_AHBCLKCTRL3_COOLFLUX_MASK) -#define SYSCON_AHBCLKCTRL3_ENC0_MASK (0x10U) -#define SYSCON_AHBCLKCTRL3_ENC0_SHIFT (4U) -/*! ENC0 - Enables the clock for ENC0 +#define SYSCON_AHBCLKCTRL3_QDC0_MASK (0x10U) +#define SYSCON_AHBCLKCTRL3_QDC0_SHIFT (4U) +/*! QDC0 - Enables the clock for QDC0 * 0b1..Enables clock * 0b0..Disables clock */ -#define SYSCON_AHBCLKCTRL3_ENC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC0_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC0_MASK) +#define SYSCON_AHBCLKCTRL3_QDC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK) -#define SYSCON_AHBCLKCTRL3_ENC1_MASK (0x20U) -#define SYSCON_AHBCLKCTRL3_ENC1_SHIFT (5U) -/*! ENC1 - Enables the clock for ENC1 +#define SYSCON_AHBCLKCTRL3_QDC1_MASK (0x20U) +#define SYSCON_AHBCLKCTRL3_QDC1_SHIFT (5U) +/*! QDC1 - Enables the clock for QDC1 * 0b1..Enables clock * 0b0..Disables clock */ -#define SYSCON_AHBCLKCTRL3_ENC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC1_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC1_MASK) +#define SYSCON_AHBCLKCTRL3_QDC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK) #define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x40U) #define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (6U) @@ -81606,7 +74441,7 @@ typedef struct { * 0b001..PLL divided clock * 0b010..FRO 12 MHz clock * 0b011..fro_hf_div clock - * 0b100..CLK_1MHz clock + * 0b100..clk_1m clock * 0b101..USB PLL clock * 0b110..LP Oscillator clock * 0b111..No clock @@ -84175,6 +77010,39 @@ typedef struct { /* The count of SYSCON_GDETX_CTRL_GDET_CTRL */ #define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT (2U) +/*! @name ELS_ASSET_PROT - ELS Asset Protection Register */ +/*! @{ */ + +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U) +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U) +/*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the + * ELS module. Refer to the ELS chapter in the SRM for more details. + * 0b00..ELS asset is protected + * 0b10..ELS asset is protected + * 0b11..ELS asset is protected + * 0b01..ELS asset is not protected + */ +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL - ELS Lock Control */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - ELS Lock Control */ +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U) +/*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */ +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK) +/*! @} */ + /*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ /*! @{ */ @@ -84678,7 +77546,7 @@ typedef struct { #define SYSCON_ELS_AS_BOOT_LOG0_ISP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK) /*! @} */ -/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: N-boot library log */ +/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */ /*! @{ */ #define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK (0x3U) @@ -84745,16 +77613,6 @@ typedef struct { #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U) /*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */ #define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK) - -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_MASK (0xFF0000U) -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_SHIFT (16U) -/*! ERR_CFG_FAIL_COUNT - CFPA->ERR_CFG_FAIL_COUNT[7:0] */ -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_CFG_FAIL_COUNT_MASK) - -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_MASK (0xFF000000U) -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_SHIFT (24U) -/*! ERR_COUNT3 - CFPA->ERR_COUNT3[7:0] */ -#define SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_COUNT3_MASK) /*! @} */ /*! @name ELS_AS_FLAG0 - ELS AS Flag0 */ @@ -85032,7 +77890,7 @@ typedef struct { #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U) -/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTIMER0/1 modules. +/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ @@ -85048,7 +77906,7 @@ typedef struct { #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK (0x8U) #define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT (3U) -/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTIMER0/1, and Frequency Measurement modules +/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules * 0b1..Clock is enabled * 0b0..Clock is not enabled */ @@ -85064,7 +77922,7 @@ typedef struct { #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) -/*! CLKIN_ENA - Enables clk_in clock for MICFIL, EMVSIM0/1, CAN0/1, I3C0/1, SAI0/1, SINC Filter (SINC), TSI, USBFS, SCT, uSDHC, clkout. +/*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout. * 0b1..Clock is enabled * 0b0..Clock is not enabled */ @@ -86049,659 +78907,1907 @@ typedef struct { /* ---------------------------------------------------------------------------- - -- TRNG Peripheral Access Layer + -- TRDC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer * @{ */ -/** TRNG - Register Layout Typedef */ +/** TRDC - Register Layout Typedef */ typedef struct { - __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ - __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - union { /* offset: 0x18 */ - __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ - __I uint32_t OSC2_FRQCNT; /**< Oscillator-2 Frequency Count Register, offset: 0x18 */ - }; - union { /* offset: 0x1C */ - __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ - __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ - }; - union { /* offset: 0x20 */ - __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ - __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ - }; - union { /* offset: 0x24 */ - __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ - __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ - }; - union { /* offset: 0x28 */ - __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ - __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ - }; - union { /* offset: 0x2C */ - __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ - __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ - }; - uint8_t RESERVED_2[12]; - __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ - __I uint32_t ENT[8]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_3[64]; - __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ - __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ - __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ - __I uint32_t CSER; /**< Common Security Error Register, offset: 0xB0 */ - __O uint32_t CSCLR; /**< Common Security Clear Register, offset: 0xB4 */ - uint8_t RESERVED_4[52]; - __IO uint32_t OSC2_CTL; /**< TRNG Oscillator 2 Control Register, offset: 0xEC */ - __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ - __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ -} TRNG_Type; + struct { /* offset: 0x0, array step: 0x1CC */ + __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_0[224]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */ + } MBC_INDEX[1]; +} TRDC_Type; /* ---------------------------------------------------------------------------- - -- TRNG Register Masks + -- TRDC Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @addtogroup TRDC_Register_Masks TRDC Register Masks * @{ */ -/*! @name MCTL - Miscellaneous Control Register */ +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ /*! @{ */ -#define TRNG_MCTL_OSC_DIV_MASK (0xCU) -#define TRNG_MCTL_OSC_DIV_SHIFT (2U) -/*! OSC_DIV - Oscillator1 Divide - * 0b00..use ring oscillator with no divide - * 0b01..use ring oscillator divided-by-2 - * 0b10..use ring oscillator divided-by-4 - * 0b11..use ring oscillator divided-by-8 - */ -#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) -#define TRNG_MCTL_DIS_SLF_TST_MASK (0x10U) -#define TRNG_MCTL_DIS_SLF_TST_SHIFT (4U) -/*! DIS_SLF_TST - Disable Self-Tests */ -#define TRNG_MCTL_DIS_SLF_TST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_DIS_SLF_TST_SHIFT)) & TRNG_MCTL_DIS_SLF_TST_MASK) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) -#define TRNG_MCTL_RST_DEF_MASK (0x40U) -#define TRNG_MCTL_RST_DEF_SHIFT (6U) -/*! RST_DEF - Reset Defaults - * 0b0..No impact. - * 0b1..Writing a 1 to this bit clears various TRNG registers, and bits within registers, to their default state. - */ -#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) - -#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) -#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) -/*! FCT_FAIL - Frequency Count Fail */ -#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) - -#define TRNG_MCTL_FCT_VAL_MASK (0x200U) -#define TRNG_MCTL_FCT_VAL_SHIFT (9U) -/*! FCT_VAL - Frequency Count Valid - * 0b0..Frequency Count is not valid - * 0b1..Frequency Count is valid - */ -#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) - -#define TRNG_MCTL_ENT_VAL_MASK (0x400U) -#define TRNG_MCTL_ENT_VAL_SHIFT (10U) -/*! ENT_VAL - Entropy Valid - * 0b0..Entropy is not valid - * 0b1..Entropy is valid - */ -#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) - -#define TRNG_MCTL_ERR_MASK (0x1000U) -#define TRNG_MCTL_ERR_SHIFT (12U) -/*! ERR - Error Status - * 0b0..No error - * 0b1..Error detected - */ -#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) - -#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) -#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) -/*! TSTOP_OK - TRNG is ok to stop - * 0b0..TRNG is generating entropy and is not ok to stop - * 0b1..TRNG is not generating entropy and is ok to stop - */ -#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) - -#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) -#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) -/*! LRUN_CONT - Long run count continues between entropy generations - * 0b0..The internal test's long run count is restarted for each entropy re-generation. - * 0b1..The count value (of TRNG's internal long_run test), at the start of an entropy generation will continue - * where it left off at the end of the previous entropy generation. - */ -#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) - -#define TRNG_MCTL_OSC2_FAIL_MASK (0x8000U) -#define TRNG_MCTL_OSC2_FAIL_SHIFT (15U) -/*! OSC2_FAIL - Oscillator 2 Failure - * 0b0..Oscillator 2 is running. - * 0b1..Oscillator 2 has failed (see OSC2_CTL[OSC_FAILSAFE_LMT]). - */ -#define TRNG_MCTL_OSC2_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC2_FAIL_SHIFT)) & TRNG_MCTL_OSC2_FAIL_MASK) - -#define TRNG_MCTL_PRGM_MASK (0x10000U) -#define TRNG_MCTL_PRGM_SHIFT (16U) -/*! PRGM - Program Mode - * 0b0..TRNG is in Run Mode - * 0b1..TRNG is in Program Mode - */ -#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) /*! @} */ -/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ /*! @{ */ -#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) -#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) -#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK) -#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) -#define TRNG_SCMISC_RTY_CT_SHIFT (16U) -#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK) /*! @} */ -/*! @name SDCTL - Seed Control Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ /*! @{ */ -#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) -#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) -#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) - -#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) -#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) -#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK) /*! @} */ -/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ /*! @{ */ -#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) -#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) -#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK) /*! @} */ -/*! @name OSC2_FRQCNT - Oscillator-2 Frequency Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ /*! @{ */ -#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT (0U) -#define TRNG_OSC2_FRQCNT_OSC2_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_SHIFT)) & TRNG_OSC2_FRQCNT_OSC2_FRQ_CT_MASK) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) /*! @} */ -/*! @name FRQCNT - Frequency Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ /*! @{ */ -#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) -#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) /*! @} */ -/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ -#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) -#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) -#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) /*! @} */ -/*! @name SCMC - Statistical Check Monobit Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ -#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) -#define TRNG_SCMC_MONO_CT_SHIFT (0U) -#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) /*! @} */ -/*! @name SCML - Statistical Check Monobit Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ -#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) -#define TRNG_SCML_MONO_MAX_SHIFT (0U) -#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) -#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) -#define TRNG_SCML_MONO_RNG_SHIFT (16U) -#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) /*! @} */ -/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ -#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) -#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) -/*! R1_0_CT - Runs of Zero, Length 1 Count */ -#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) -#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) -#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) -/*! R1_1_CT - Runs of One, Length 1 Count */ -#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) /*! @} */ -/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ /*! @{ */ -#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) -#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) -/*! RUN1_MAX - Run Length 1 Maximum Limit */ -#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) -#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) -#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) -/*! RUN1_RNG - Run Length 1 Range */ -#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) /*! @} */ -/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ /*! @{ */ -#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) -#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) -#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) -#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) -#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) -#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) /*! @} */ -/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ -/*! @{ */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U) -#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) -#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) -#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) - -#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) -#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) -#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) -/*! @} */ - -/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ -/*! @{ */ - -#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) -#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) -#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) - -#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) -#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) -#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) -/*! @} */ - -/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ -/*! @{ */ - -#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) -#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) -#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) - -#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) -#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) -#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ - -#define TRNG_STATUS_TF1BR0_MASK (0x1U) -#define TRNG_STATUS_TF1BR0_SHIFT (0U) -/*! TF1BR0 - * 0b0..The 1-Bit Run, Sampling 0s Test has passed - * 0b1..The 1-Bit Run, Sampling 0s Test has failed - */ -#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) - -#define TRNG_STATUS_TF1BR1_MASK (0x2U) -#define TRNG_STATUS_TF1BR1_SHIFT (1U) -/*! TF1BR1 - * 0b0..The 1-Bit Run, Sampling 1s Test has passed - * 0b1..The 1-Bit Run, Sampling 1s Test has failed - */ -#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) - -#define TRNG_STATUS_TF2BR0_MASK (0x4U) -#define TRNG_STATUS_TF2BR0_SHIFT (2U) -/*! TF2BR0 - * 0b0..The 2-Bit Run, Sampling 0s Test has passed - * 0b1..The 2-Bit Run, Sampling 0s Test has failed - */ -#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) - -#define TRNG_STATUS_TF2BR1_MASK (0x8U) -#define TRNG_STATUS_TF2BR1_SHIFT (3U) -/*! TF2BR1 - * 0b0..The 2-Bit Run, Sampling 1s Test has passed - * 0b1..The 2-Bit Run, Sampling 1s Test has failed - */ -#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) - -#define TRNG_STATUS_TF3BR0_MASK (0x10U) -#define TRNG_STATUS_TF3BR0_SHIFT (4U) -/*! TF3BR0 - * 0b0..The 3-Bit Run, Sampling 0s Test has passed - * 0b1..The 3-Bit Run, Sampling 0s Test has failed - */ -#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) - -#define TRNG_STATUS_TF3BR1_MASK (0x20U) -#define TRNG_STATUS_TF3BR1_SHIFT (5U) -/*! TF3BR1 - Test Fail - * 0b0..The 3-Bit Run, Sampling 1s Test has passed - * 0b1..The 3-Bit Run, Sampling 1s Test has failed - */ -#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) - -#define TRNG_STATUS_TFLR_MASK (0x2000U) -#define TRNG_STATUS_TFLR_SHIFT (13U) -/*! TFLR - Test Fail, Long Run. - * 0b0..The Long Run Test has passed - * 0b1..The Long Run Test has failed - */ -#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) - -#define TRNG_STATUS_TFMB_MASK (0x8000U) -#define TRNG_STATUS_TFMB_SHIFT (15U) -/*! TFMB - * 0b0..The Mono Bit Test has passed - * 0b1..The Mono Bit Test has failed - */ -#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) - -#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) -#define TRNG_STATUS_RETRY_CT_SHIFT (16U) -#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) -/*! @} */ - -/*! @name ENT - Entropy Read Register */ -/*! @{ */ - -#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) -#define TRNG_ENT_ENT_SHIFT (0U) -#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) -/*! @} */ - -/* The count of TRNG_ENT */ -#define TRNG_ENT_COUNT (8U) - -/*! @name SEC_CFG - Security Configuration Register */ -/*! @{ */ - -#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) -#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) -/*! NO_PRGM - * 0b0..TRNG configuration registers can be modified. - * 0b1..TRNG configuration registers cannot be modified. - */ -#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) -/*! @} */ - -/*! @name INT_CTRL - Interrupt Control Register */ -/*! @{ */ - -#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) -#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..Clears the INT_STATUS[HW_ERR] bit. Will automatically set after writing. - * 0b1..Enables the INT_STATUS[HW_ERR] bit to be set, thereby enabling interrupt generation for the HW_ERR condition. - */ -#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) - -#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) -#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Clears the INT_STATUS[ENT_VAL] bit. Will automatically set after writing. - * 0b1..Enables the INT_STATUS[ENT_VAL] bit to be set, thereby enabling interrupt generation for the ENT_VAL condition. - */ -#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) - -#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..Clears the INT_STATUS[FRQ_CT_FAIL] bit. Will automatically set after writing. - * 0b1..Enables the INT_STATUS[FRQ_CT_FAIL] bit to be set, thereby enabling interrupt generation for the FRQ_CT_FAIL condition. - */ -#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_MASK - Mask Register */ -/*! @{ */ - -#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) -#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..HW_ERR interrupt is disabled. - * 0b1..HW_ERR interrupt is enabled. - */ -#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) - -#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) -#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..ENT_VAL interrupt is disabled. - * 0b1..ENT_VAL interrupt is enabled. - */ -#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) - -#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..FRQ_CT_FAIL interrupt is disabled. - * 0b1..FRQ_CT_FAIL interrupt is enabled. - */ -#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ - -#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) -#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..No error. - * 0b1..Error detected. - */ -#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) - -#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) -#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Busy generating entropy. Any value read from the Entropy registers is invalid. - * 0b1..Values read from the Entropy registers are valid. - */ -#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) - -#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..No hardware nor self test frequency errors. - * 0b1..The frequency counter has detected a failure. - */ -#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name CSER - Common Security Error Register */ -/*! @{ */ - -#define TRNG_CSER_RED_FSM_MASK (0x2U) -#define TRNG_CSER_RED_FSM_SHIFT (1U) -/*! RED_FSM - Redundant FSM error/fault detected - * 0b0..No redundant FSM error/fault - * 0b1..Redundant FSM error/fault detected. - */ -#define TRNG_CSER_RED_FSM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSER_RED_FSM_SHIFT)) & TRNG_CSER_RED_FSM_MASK) -/*! @} */ - -/*! @name CSCLR - Common Security Clear Register */ -/*! @{ */ - -#define TRNG_CSCLR_RED_FSM_CLR_MASK (0x2U) -#define TRNG_CSCLR_RED_FSM_CLR_SHIFT (1U) -/*! RED_FSM_CLR - * 0b0..No effect, ignored - * 0b1..Clears the CSER[RED_FSM] bit. - */ -#define TRNG_CSCLR_RED_FSM_CLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CSCLR_RED_FSM_CLR_SHIFT)) & TRNG_CSCLR_RED_FSM_CLR_MASK) -/*! @} */ - -/*! @name OSC2_CTL - TRNG Oscillator 2 Control Register */ -/*! @{ */ - -#define TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK (0x3U) -#define TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT (0U) -/*! TRNG_ENT_CTL - TRNG entropy generation control. - * 0b00..Single oscillator mode, using OSC1 (default) - * 0b01..Dual oscillator mode - * 0b10..Single oscillator mode, using OSC2 - * 0b11..Unused, (bit field cannot be written to this value) - */ -#define TRNG_OSC2_CTL_TRNG_ENT_CTL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_TRNG_ENT_CTL_SHIFT)) & TRNG_OSC2_CTL_TRNG_ENT_CTL_MASK) - -#define TRNG_OSC2_CTL_OSC2_DIV_MASK (0xCU) -#define TRNG_OSC2_CTL_OSC2_DIV_SHIFT (2U) -/*! OSC2_DIV - Oscillator 2 Divide. - * 0b00..Use ring oscillator 2 with no divide - * 0b01..Use ring oscillator 2 divided-by-2 - * 0b10..Use ring oscillator 2 divided-by-4 - * 0b11..Use ring oscillator 2 divided-by-8 - */ -#define TRNG_OSC2_CTL_OSC2_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_DIV_SHIFT)) & TRNG_OSC2_CTL_OSC2_DIV_MASK) - -#define TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK (0x200U) -#define TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT (9U) -/*! OSC2_FCT_VAL - TRNG Oscillator 2 Frequency Count Valid - * 0b0..Frequency count is invalid. - * 0b1..If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT. - */ -#define TRNG_OSC2_CTL_OSC2_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC2_FCT_VAL_SHIFT)) & TRNG_OSC2_CTL_OSC2_FCT_VAL_MASK) - -#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK (0x3000U) -#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT (12U) -/*! OSC_FAILSAFE_LMT - Oscillator fail safe limit. - * 0b00..The limit N is 4096 (2^12) system clocks. - * 0b01..The limit N is 65536 (2^16) system clocks. (default) - * 0b10..N is 2^20 system clocks. - * 0b11..N is 2^22 system clocks (full range of the counter being used). - */ -#define TRNG_OSC2_CTL_OSC_FAILSAFE_LMT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_LMT_MASK) - -#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK (0x4000U) -#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT (14U) -/*! OSC_FAILSAFE_TEST - Oscillator fail safe test. - * 0b0..No impact. - * 0b1..Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b). - */ -#define TRNG_OSC2_CTL_OSC_FAILSAFE_TEST(x) (((uint32_t)(((uint32_t)(x)) << TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_SHIFT)) & TRNG_OSC2_CTL_OSC_FAILSAFE_TEST_MASK) -/*! @} */ - -/*! @name VID1 - Version ID Register (MS) */ -/*! @{ */ - -#define TRNG_VID1_MIN_REV_MASK (0xFFU) -#define TRNG_VID1_MIN_REV_SHIFT (0U) -/*! MIN_REV - * 0b00001011..Minor revision number for TRNG. - */ -#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) - -#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) -#define TRNG_VID1_MAJ_REV_SHIFT (8U) -/*! MAJ_REV - * 0b00010100..Major revision number for TRNG. - */ -#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) - -#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) -#define TRNG_VID1_IP_ID_SHIFT (16U) -/*! IP_ID - * 0b0000000000110000..ID for TRNG. - */ -#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name VID2 - Version ID Register (LS) */ -/*! @{ */ - -#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) -#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) -/*! CONFIG_OPT - * 0b00000000..TRNG_CONFIG_OPT for TRNG. - */ -#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) - -#define TRNG_VID2_ECO_REV_MASK (0xFF00U) -#define TRNG_VID2_ECO_REV_SHIFT (8U) -/*! ECO_REV - * 0b00000000..TRNG_ECO_REV for TRNG. - */ -#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) - -#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) -#define TRNG_VID2_INTG_OPT_SHIFT (16U) -/*! INTG_OPT - * 0b00001010..INTG_OPT for TRNG. - */ -#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) - -#define TRNG_VID2_ERA_MASK (0xFF000000U) -#define TRNG_VID2_ERA_SHIFT (24U) -/*! ERA - * 0b00001011..ERA of the TRNG. - */ -#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) -/*! @} */ +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) /*! * @} - */ /* end of group TRNG_Register_Masks */ + */ /* end of group TRDC_Register_Masks */ -/* TRNG - Peripheral instance base addresses */ +/* TRDC - Peripheral instance base addresses */ #if ((defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) || defined(CPU1_IS_SECURE_MASTER)) - /** Peripheral TRNG0 base address */ - #define TRNG0_BASE (0x5005A000u) - /** Peripheral TRNG0 base address */ - #define TRNG0_BASE_NS (0x4005A000u) - /** Peripheral TRNG0 base pointer */ - #define TRNG0 ((TRNG_Type *)TRNG0_BASE) - /** Peripheral TRNG0 base pointer */ - #define TRNG0_NS ((TRNG_Type *)TRNG0_BASE_NS) - /** Array initializer of TRNG peripheral base addresses */ - #define TRNG_BASE_ADDRS { TRNG0_BASE } - /** Array initializer of TRNG peripheral base pointers */ - #define TRNG_BASE_PTRS { TRNG0 } - /** Array initializer of TRNG peripheral base addresses */ - #define TRNG_BASE_ADDRS_NS { TRNG0_BASE_NS } - /** Array initializer of TRNG peripheral base pointers */ - #define TRNG_BASE_PTRS_NS { TRNG0_NS } + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } #else - /** Peripheral TRNG0 base address */ - #define TRNG0_BASE (0x4005A000u) - /** Peripheral TRNG0 base pointer */ - #define TRNG0 ((TRNG_Type *)TRNG0_BASE) - /** Array initializer of TRNG peripheral base addresses */ - #define TRNG_BASE_ADDRS { TRNG0_BASE } - /** Array initializer of TRNG peripheral base pointers */ - #define TRNG_BASE_PTRS { TRNG0 } + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } #endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + /*! * @} - */ /* end of group TRNG_Peripheral_Access_Layer */ + */ /* end of group TRDC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- @@ -89440,7 +83546,7 @@ typedef struct { /** USBHS - Register Layout Typedef */ typedef struct { - __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t ID; /**< Identification, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ @@ -89463,9 +83569,9 @@ typedef struct { uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; - __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ - __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ - __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ @@ -89482,17 +83588,17 @@ typedef struct { uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ - __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; - __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t OTGSC; /**< On-The-Go Status & Control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ - __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control 0, offset: 0x1C0 */ __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ } USBHS_Type; @@ -89505,22 +83611,22 @@ typedef struct { * @{ */ -/*! @name ID - Identification register */ +/*! @name ID - Identification */ /*! @{ */ #define USBHS_ID_ID_MASK (0x3FU) #define USBHS_ID_ID_SHIFT (0U) -/*! ID - ID */ +/*! ID - Configuration Number */ #define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK) #define USBHS_ID_NID_MASK (0x3F00U) #define USBHS_ID_NID_SHIFT (8U) -/*! NID - NID */ +/*! NID - Complement Version of ID */ #define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK) #define USBHS_ID_REVISION_MASK (0xFF0000U) #define USBHS_ID_REVISION_SHIFT (16U) -/*! REVISION - REVISION */ +/*! REVISION - Revision Number of the Controller Core */ #define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK) /*! @} */ @@ -89529,7 +83635,7 @@ typedef struct { #define USBHS_HWGENERAL_PHYW_MASK (0x30U) #define USBHS_HWGENERAL_PHYW_SHIFT (4U) -/*! PHYW - PHYW +/*! PHYW - Data width of the transceiver connected to the controller core * 0b00..8 bit wide data bus (Software non-programmable) * 0b01..16 bit wide data bus (Software non-programmable) * 0b10..Reset to 8 bit wide data bus (Software programmable) @@ -89539,7 +83645,7 @@ typedef struct { #define USBHS_HWGENERAL_PHYM_MASK (0x1C0U) #define USBHS_HWGENERAL_PHYM_SHIFT (6U) -/*! PHYM - PHYM +/*! PHYM - Transceiver Type * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI @@ -89553,9 +83659,9 @@ typedef struct { #define USBHS_HWGENERAL_SM_MASK (0x600U) #define USBHS_HWGENERAL_SM_SHIFT (9U) -/*! SM - SM - * 0b00..No Serial Engine, always use parallel signalling. - * 0b01..Serial Engine present, always use serial signalling for FS/LS. +/*! SM - Serial interface mode capability + * 0b00..No Serial Engine, always use parallel signalling + * 0b01..Serial Engine present, always use serial signalling for FS/LS * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ @@ -89567,7 +83673,7 @@ typedef struct { #define USBHS_HWHOST_HC_MASK (0x1U) #define USBHS_HWHOST_HC_SHIFT (0U) -/*! HC - HC +/*! HC - Host Capable * 0b1..Supported * 0b0..Not supported */ @@ -89575,7 +83681,7 @@ typedef struct { #define USBHS_HWHOST_NPORT_MASK (0xEU) #define USBHS_HWHOST_NPORT_SHIFT (1U) -/*! NPORT - NPORT */ +/*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */ #define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK) /*! @} */ @@ -89584,7 +83690,7 @@ typedef struct { #define USBHS_HWDEVICE_DC_MASK (0x1U) #define USBHS_HWDEVICE_DC_SHIFT (0U) -/*! DC - DC +/*! DC - Device Capable * 0b1..Supported * 0b0..Not supported */ @@ -89592,7 +83698,7 @@ typedef struct { #define USBHS_HWDEVICE_DEVEP_MASK (0x3EU) #define USBHS_HWDEVICE_DEVEP_SHIFT (1U) -/*! DEVEP - DEVEP */ +/*! DEVEP - Device Endpoint Number */ #define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK) /*! @} */ @@ -89601,12 +83707,12 @@ typedef struct { #define USBHS_HWTXBUF_TXBURST_MASK (0xFFU) #define USBHS_HWTXBUF_TXBURST_SHIFT (0U) -/*! TXBURST - TXBURST */ +/*! TXBURST - Default burst size for memory to TX buffer transfer */ #define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK) #define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U) -/*! TXCHANADD - TXCHANADD */ +/*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */ #define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK) /*! @} */ @@ -89615,12 +83721,12 @@ typedef struct { #define USBHS_HWRXBUF_RXBURST_MASK (0xFFU) #define USBHS_HWRXBUF_RXBURST_SHIFT (0U) -/*! RXBURST - RXBURST */ +/*! RXBURST - Default burst size for memory to RX buffer transfer */ #define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK) #define USBHS_HWRXBUF_RXADD_MASK (0xFF00U) #define USBHS_HWRXBUF_RXADD_SHIFT (8U) -/*! RXADD - RXADD */ +/*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */ #define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK) /*! @} */ @@ -89629,7 +83735,7 @@ typedef struct { #define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U) -/*! GPTLD - GPTLD */ +/*! GPTLD - General Purpose Timer Load Value */ #define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK) /*! @} */ @@ -89638,12 +83744,12 @@ typedef struct { #define USBHS_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -/*! GPTCNT - GPTCNT */ +/*! GPTCNT - General Purpose Timer Counter */ #define USBHS_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK) #define USBHS_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -/*! GPTMODE - GPTMODE +/*! GPTMODE - General Purpose Timer Mode * 0b0..One Shot Mode * 0b1..Repeat Mode */ @@ -89651,7 +83757,7 @@ typedef struct { #define USBHS_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USBHS_GPTIMER0CTRL_GPTRST_SHIFT (30U) -/*! GPTRST - GPTRST +/*! GPTRST - General Purpose Timer Reset * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ @@ -89659,7 +83765,7 @@ typedef struct { #define USBHS_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -/*! GPTRUN - GPTRUN +/*! GPTRUN - General Purpose Timer Run * 0b0..Stop counting * 0b1..Run */ @@ -89671,7 +83777,7 @@ typedef struct { #define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U) -/*! GPTLD - GPTLD */ +/*! GPTLD - General Purpose Timer Load Value */ #define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK) /*! @} */ @@ -89680,12 +83786,12 @@ typedef struct { #define USBHS_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -/*! GPTCNT - GPTCNT */ +/*! GPTCNT - General Purpose Timer Counter */ #define USBHS_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK) #define USBHS_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -/*! GPTMODE - GPTMODE +/*! GPTMODE - General Purpose Timer Mode * 0b0..One Shot Mode * 0b1..Repeat Mode */ @@ -89693,7 +83799,7 @@ typedef struct { #define USBHS_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USBHS_GPTIMER1CTRL_GPTRST_SHIFT (30U) -/*! GPTRST - GPTRST +/*! GPTRST - General Purpose Timer Reset * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ @@ -89701,7 +83807,7 @@ typedef struct { #define USBHS_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -/*! GPTRUN - GPTRUN +/*! GPTRUN - General Purpose Timer Run * 0b0..Stop counting * 0b1..Run */ @@ -89713,7 +83819,7 @@ typedef struct { #define USBHS_SBUSCFG_AHBBRST_MASK (0x7U) #define USBHS_SBUSCFG_AHBBRST_SHIFT (0U) -/*! AHBBRST - AHBBRST +/*! AHBBRST - AHB master interface Burst configuration * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer @@ -89731,7 +83837,9 @@ typedef struct { #define USBHS_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USBHS_CAPLENGTH_CAPLENGTH_SHIFT (0U) -/*! CAPLENGTH - CAPLENGTH */ +/*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of + * the Operational Register. Default value is '40h'. + */ #define USBHS_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ @@ -89740,7 +83848,7 @@ typedef struct { #define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USBHS_HCIVERSION_HCIVERSION_SHIFT (0U) -/*! HCIVERSION - HCIVERSION */ +/*! HCIVERSION - Host Controller Interface Version Number */ #define USBHS_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK) /*! @} */ @@ -89749,40 +83857,40 @@ typedef struct { #define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU) #define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U) -/*! N_PORTS - N_PORTS */ +/*! N_PORTS - Number of Downstream Ports */ #define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK) #define USBHS_HCSPARAMS_PPC_MASK (0x10U) #define USBHS_HCSPARAMS_PPC_SHIFT (4U) -/*! PPC - PPC */ +/*! PPC - Port Power Control */ #define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK) #define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U) #define USBHS_HCSPARAMS_N_PCC_SHIFT (8U) -/*! N_PCC - N_PCC */ +/*! N_PCC - Number of Ports per Companion Controller */ #define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK) #define USBHS_HCSPARAMS_N_CC_MASK (0xF000U) #define USBHS_HCSPARAMS_N_CC_SHIFT (12U) -/*! N_CC - N_CC - * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. - * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. +/*! N_CC - Number of Companion Controller + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported */ #define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK) #define USBHS_HCSPARAMS_PI_MASK (0x10000U) #define USBHS_HCSPARAMS_PI_SHIFT (16U) -/*! PI - PI */ +/*! PI - Port Indicators (P INDICATOR) */ #define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK) #define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USBHS_HCSPARAMS_N_PTT_SHIFT (20U) -/*! N_PTT - N_PTT */ +/*! N_PTT - Number of Ports per Transaction Translator */ #define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK) #define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U) #define USBHS_HCSPARAMS_N_TT_SHIFT (24U) -/*! N_TT - N_TT */ +/*! N_TT - Number of Transaction Translators */ #define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK) /*! @} */ @@ -89791,27 +83899,27 @@ typedef struct { #define USBHS_HCCPARAMS_ADC_MASK (0x1U) #define USBHS_HCCPARAMS_ADC_SHIFT (0U) -/*! ADC - ADC */ +/*! ADC - 64-bit Addressing Capability */ #define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK) #define USBHS_HCCPARAMS_PFL_MASK (0x2U) #define USBHS_HCCPARAMS_PFL_SHIFT (1U) -/*! PFL - PFL */ +/*! PFL - Programmable Frame List Flag */ #define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK) #define USBHS_HCCPARAMS_ASP_MASK (0x4U) #define USBHS_HCCPARAMS_ASP_SHIFT (2U) -/*! ASP - ASP */ +/*! ASP - Asynchronous Schedule Park Capability */ #define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK) #define USBHS_HCCPARAMS_IST_MASK (0xF0U) #define USBHS_HCCPARAMS_IST_SHIFT (4U) -/*! IST - IST */ +/*! IST - Isochronous Scheduling Threshold */ #define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK) #define USBHS_HCCPARAMS_EECP_MASK (0xFF00U) #define USBHS_HCCPARAMS_EECP_SHIFT (8U) -/*! EECP - EECP */ +/*! EECP - EHCI Extended Capabilities Pointer */ #define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK) /*! @} */ @@ -89820,7 +83928,7 @@ typedef struct { #define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U) -/*! DCIVERSION - DCIVERSION */ +/*! DCIVERSION - Device Controller Interface Version Number */ #define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK) /*! @} */ @@ -89829,87 +83937,90 @@ typedef struct { #define USBHS_DCCPARAMS_DEN_MASK (0x1FU) #define USBHS_DCCPARAMS_DEN_SHIFT (0U) -/*! DEN - DEN */ +/*! DEN - Device Endpoint Number */ #define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK) #define USBHS_DCCPARAMS_DC_MASK (0x80U) #define USBHS_DCCPARAMS_DC_SHIFT (7U) -/*! DC - DC */ +/*! DC - Device Capable */ #define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK) #define USBHS_DCCPARAMS_HC_MASK (0x100U) #define USBHS_DCCPARAMS_HC_SHIFT (8U) -/*! HC - HC */ +/*! HC - Host Capable */ #define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK) /*! @} */ -/*! @name USBCMD - USB Command Register */ +/*! @name USBCMD - USB Command */ /*! @{ */ #define USBHS_USBCMD_RS_MASK (0x1U) #define USBHS_USBCMD_RS_SHIFT (0U) -/*! RS - RS */ +/*! RS - Run/Stop + * 0b0..Stop + * 0b1..Run + */ #define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK) #define USBHS_USBCMD_RST_MASK (0x2U) #define USBHS_USBCMD_RST_SHIFT (1U) -/*! RST - RST */ +/*! RST - Controller Reset */ #define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK) #define USBHS_USBCMD_FS_1_MASK (0xCU) #define USBHS_USBCMD_FS_1_SHIFT (2U) -/*! FS_1 - FS_1 */ +/*! FS_1 - Frame List Size */ #define USBHS_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK) #define USBHS_USBCMD_PSE_MASK (0x10U) #define USBHS_USBCMD_PSE_SHIFT (4U) -/*! PSE - PSE +/*! PSE - Periodic Schedule Enable * 0b0..Do not process the Periodic Schedule - * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule */ #define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK) #define USBHS_USBCMD_ASE_MASK (0x20U) #define USBHS_USBCMD_ASE_SHIFT (5U) -/*! ASE - ASE - * 0b0..Do not process the Asynchronous Schedule. - * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. +/*! ASE - Asynchronous Schedule Enable + * 0b0..Do not process the Asynchronous Schedule + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule */ #define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK) #define USBHS_USBCMD_IAA_MASK (0x40U) #define USBHS_USBCMD_IAA_SHIFT (6U) -/*! IAA - IAA */ +/*! IAA - Interrupt on Async Advance Doorbell */ #define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK) #define USBHS_USBCMD_ASP_MASK (0x300U) #define USBHS_USBCMD_ASP_SHIFT (8U) -/*! ASP - ASP */ +/*! ASP - Asynchronous Schedule Park Mode Count */ #define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK) #define USBHS_USBCMD_ASPE_MASK (0x800U) #define USBHS_USBCMD_ASPE_SHIFT (11U) -/*! ASPE - ASPE */ +/*! ASPE - Asynchronous Schedule Park Mode Enable */ #define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK) #define USBHS_USBCMD_SUTW_MASK (0x2000U) #define USBHS_USBCMD_SUTW_SHIFT (13U) -/*! SUTW - SUTW */ +/*! SUTW - Setup TripWire [device mode only] */ #define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK) #define USBHS_USBCMD_ATDTW_MASK (0x4000U) #define USBHS_USBCMD_ATDTW_SHIFT (14U) -/*! ATDTW - ATDTW */ +/*! ATDTW - Add dTD TripWire[device mode only] */ #define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK) #define USBHS_USBCMD_FS_2_MASK (0x8000U) #define USBHS_USBCMD_FS_2_SHIFT (15U) -/*! FS_2 - FS_2 */ +/*! FS_2 - Frame List Size [host mode only] */ #define USBHS_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK) #define USBHS_USBCMD_ITC_MASK (0xFF0000U) #define USBHS_USBCMD_ITC_SHIFT (16U) -/*! ITC - ITC +/*! ITC - Interrupt Threshold Control * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames @@ -89922,166 +84033,166 @@ typedef struct { #define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK) /*! @} */ -/*! @name USBSTS - USB Status Register */ +/*! @name USBSTS - USB Status */ /*! @{ */ #define USBHS_USBSTS_UI_MASK (0x1U) #define USBHS_USBSTS_UI_SHIFT (0U) -/*! UI - UI */ +/*! UI - USB Interrupt (USBINT) */ #define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK) #define USBHS_USBSTS_UEI_MASK (0x2U) #define USBHS_USBSTS_UEI_SHIFT (1U) -/*! UEI - UEI */ +/*! UEI - USB Error Interrupt (USBERRINT) */ #define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK) #define USBHS_USBSTS_PCI_MASK (0x4U) #define USBHS_USBSTS_PCI_SHIFT (2U) -/*! PCI - PCI */ +/*! PCI - Port Change Detect */ #define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK) #define USBHS_USBSTS_FRI_MASK (0x8U) #define USBHS_USBSTS_FRI_SHIFT (3U) -/*! FRI - FRI */ +/*! FRI - Frame List Rollover */ #define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK) #define USBHS_USBSTS_SEI_MASK (0x10U) #define USBHS_USBSTS_SEI_SHIFT (4U) -/*! SEI - SEI */ +/*! SEI - System Error */ #define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK) #define USBHS_USBSTS_AAI_MASK (0x20U) #define USBHS_USBSTS_AAI_SHIFT (5U) -/*! AAI - AAI */ +/*! AAI - Interrupt on Async Advance */ #define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK) #define USBHS_USBSTS_URI_MASK (0x40U) #define USBHS_USBSTS_URI_SHIFT (6U) -/*! URI - URI */ +/*! URI - USB Reset Received */ #define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK) #define USBHS_USBSTS_SRI_MASK (0x80U) #define USBHS_USBSTS_SRI_SHIFT (7U) -/*! SRI - SRI */ +/*! SRI - SOF Received */ #define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK) #define USBHS_USBSTS_SLI_MASK (0x100U) #define USBHS_USBSTS_SLI_SHIFT (8U) -/*! SLI - SLI */ +/*! SLI - DCSuspend */ #define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK) #define USBHS_USBSTS_ULPII_MASK (0x400U) #define USBHS_USBSTS_ULPII_SHIFT (10U) -/*! ULPII - ULPII */ +/*! ULPII - ULPI Interrupt */ #define USBHS_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK) #define USBHS_USBSTS_HCH_MASK (0x1000U) #define USBHS_USBSTS_HCH_SHIFT (12U) -/*! HCH - HCH */ +/*! HCH - HCHaIted */ #define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK) #define USBHS_USBSTS_RCL_MASK (0x2000U) #define USBHS_USBSTS_RCL_SHIFT (13U) -/*! RCL - RCL */ +/*! RCL - Reclamation */ #define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK) #define USBHS_USBSTS_PS_MASK (0x4000U) #define USBHS_USBSTS_PS_SHIFT (14U) -/*! PS - PS */ +/*! PS - Periodic Schedule Status */ #define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK) #define USBHS_USBSTS_AS_MASK (0x8000U) #define USBHS_USBSTS_AS_SHIFT (15U) -/*! AS - AS */ +/*! AS - Asynchronous Schedule Status */ #define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK) #define USBHS_USBSTS_NAKI_MASK (0x10000U) #define USBHS_USBSTS_NAKI_SHIFT (16U) -/*! NAKI - NAKI */ +/*! NAKI - NAK Interrupt Bit */ #define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK) #define USBHS_USBSTS_TI0_MASK (0x1000000U) #define USBHS_USBSTS_TI0_SHIFT (24U) -/*! TI0 - TI0 */ +/*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */ #define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK) #define USBHS_USBSTS_TI1_MASK (0x2000000U) #define USBHS_USBSTS_TI1_SHIFT (25U) -/*! TI1 - TI1 */ +/*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */ #define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK) /*! @} */ -/*! @name USBINTR - Interrupt Enable Register */ +/*! @name USBINTR - Interrupt Enable */ /*! @{ */ #define USBHS_USBINTR_UE_MASK (0x1U) #define USBHS_USBINTR_UE_SHIFT (0U) -/*! UE - UE */ +/*! UE - USB Interrupt Enable */ #define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK) #define USBHS_USBINTR_UEE_MASK (0x2U) #define USBHS_USBINTR_UEE_SHIFT (1U) -/*! UEE - UEE */ +/*! UEE - USB Error Interrupt Enable */ #define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK) #define USBHS_USBINTR_PCE_MASK (0x4U) #define USBHS_USBINTR_PCE_SHIFT (2U) -/*! PCE - PCE */ +/*! PCE - Port Change Detect Interrupt Enable */ #define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK) #define USBHS_USBINTR_FRE_MASK (0x8U) #define USBHS_USBINTR_FRE_SHIFT (3U) -/*! FRE - FRE */ +/*! FRE - Frame List Rollover Interrupt Enable */ #define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK) #define USBHS_USBINTR_SEE_MASK (0x10U) #define USBHS_USBINTR_SEE_SHIFT (4U) -/*! SEE - SEE */ +/*! SEE - System Error Interrupt Enable */ #define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK) #define USBHS_USBINTR_AAE_MASK (0x20U) #define USBHS_USBINTR_AAE_SHIFT (5U) -/*! AAE - AAE */ +/*! AAE - Async Advance Interrupt Enable */ #define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK) #define USBHS_USBINTR_URE_MASK (0x40U) #define USBHS_USBINTR_URE_SHIFT (6U) -/*! URE - URE */ +/*! URE - USB Reset Interrupt Enable */ #define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK) #define USBHS_USBINTR_SRE_MASK (0x80U) #define USBHS_USBINTR_SRE_SHIFT (7U) -/*! SRE - SRE */ +/*! SRE - SOF Received Interrupt Enable */ #define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK) #define USBHS_USBINTR_SLE_MASK (0x100U) #define USBHS_USBINTR_SLE_SHIFT (8U) -/*! SLE - SLE */ +/*! SLE - Sleep Interrupt Enable */ #define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK) #define USBHS_USBINTR_NAKE_MASK (0x10000U) #define USBHS_USBINTR_NAKE_SHIFT (16U) -/*! NAKE - NAKE */ +/*! NAKE - NAK Interrupt Enable */ #define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK) #define USBHS_USBINTR_UAIE_MASK (0x40000U) #define USBHS_USBINTR_UAIE_SHIFT (18U) -/*! UAIE - UAIE */ +/*! UAIE - USB Host Asynchronous Interrupt Enable */ #define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK) #define USBHS_USBINTR_UPIE_MASK (0x80000U) #define USBHS_USBINTR_UPIE_SHIFT (19U) -/*! UPIE - UPIE */ +/*! UPIE - USB Host Periodic Interrupt Enable */ #define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK) #define USBHS_USBINTR_TIE0_MASK (0x1000000U) #define USBHS_USBINTR_TIE0_SHIFT (24U) -/*! TIE0 - TIE0 */ +/*! TIE0 - General Purpose Timer #0 Interrupt Enable */ #define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK) #define USBHS_USBINTR_TIE1_MASK (0x2000000U) #define USBHS_USBINTR_TIE1_SHIFT (25U) -/*! TIE1 - TIE1 */ +/*! TIE1 - General Purpose Timer #1 Interrupt Enable */ #define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK) /*! @} */ @@ -90090,7 +84201,7 @@ typedef struct { #define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USBHS_FRINDEX_FRINDEX_SHIFT (0U) -/*! FRINDEX - FRINDEX +/*! FRINDEX - Frame Index * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 @@ -90108,12 +84219,12 @@ typedef struct { #define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USBHS_DEVICEADDR_USBADRA_SHIFT (24U) -/*! USBADRA - USBADRA */ +/*! USBADRA - Device Address Advance */ #define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK) #define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USBHS_DEVICEADDR_USBADR_SHIFT (25U) -/*! USBADR - USBADR */ +/*! USBADR - Device Address */ #define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK) /*! @} */ @@ -90122,7 +84233,7 @@ typedef struct { #define USBHS_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USBHS_PERIODICLISTBASE_BASEADR_SHIFT (12U) -/*! BASEADR - BASEADR */ +/*! BASEADR - Base Address (Low) */ #define USBHS_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ @@ -90131,7 +84242,7 @@ typedef struct { #define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -/*! ASYBASE - ASYBASE */ +/*! ASYBASE - Link Pointer Low (LPL) */ #define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ @@ -90140,7 +84251,7 @@ typedef struct { #define USBHS_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USBHS_ENDPTLISTADDR_EPBASE_SHIFT (11U) -/*! EPBASE - EPBASE */ +/*! EPBASE - Endpoint List Pointer (Low) */ #define USBHS_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ @@ -90149,12 +84260,12 @@ typedef struct { #define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U) -/*! RXPBURST - RXPBURST */ +/*! RXPBURST - Programmable RX Burst Size */ #define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK) -#define USBHS_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U) #define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U) -/*! TXPBURST - TXPBURST */ +/*! TXPBURST - Programmable TX Burst Size */ #define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK) /*! @} */ @@ -90163,17 +84274,17 @@ typedef struct { #define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU) #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U) -/*! TXSCHOH - TXSCHOH */ +/*! TXSCHOH - Scheduler Overhead */ #define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK) #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -/*! TXSCHHEALTH - TXSCHHEALTH */ +/*! TXSCHHEALTH - Scheduler Health Counter */ #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK) #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -/*! TXFIFOTHRES - TXFIFOTHRES */ +/*! TXFIFOTHRES - FIFO Burst Threshold */ #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ @@ -90182,12 +84293,12 @@ typedef struct { #define USBHS_ENDPTNAK_EPRN_MASK (0xFFU) #define USBHS_ENDPTNAK_EPRN_SHIFT (0U) -/*! EPRN - EPRN */ +/*! EPRN - RX Endpoint NAK */ #define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK) #define USBHS_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USBHS_ENDPTNAK_EPTN_SHIFT (16U) -/*! EPTN - EPTN */ +/*! EPTN - TX Endpoint NAK */ #define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK) /*! @} */ @@ -90196,23 +84307,23 @@ typedef struct { #define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U) -/*! EPRNE - EPRNE */ +/*! EPRNE - RX Endpoint NAK Enable */ #define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK) #define USBHS_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U) -/*! EPTNE - EPTNE */ +/*! EPTNE - TX Endpoint NAK Enable */ #define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK) /*! @} */ -/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @name CONFIGFLAG - Configure Flag */ /*! @{ */ #define USBHS_CONFIGFLAG_CF_MASK (0x1U) #define USBHS_CONFIGFLAG_CF_SHIFT (0U) -/*! CF - CF - * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. - * 0b1..Port routing control logic default-routes all ports to this host controller. +/*! CF - Configure Flag + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller + * 0b1..Port routing control logic default-routes all ports to this host controller */ #define USBHS_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK) /*! @} */ @@ -90222,60 +84333,81 @@ typedef struct { #define USBHS_PORTSC1_CCS_MASK (0x1U) #define USBHS_PORTSC1_CCS_SHIFT (0U) -/*! CCS - CCS */ +/*! CCS - Current Connect Status + * 0b0..In Host mode: No device is present. In Device mode: Not attached + * 0b1..In Host mode: Device is present on port. In Device mode: Attached + */ #define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK) #define USBHS_PORTSC1_CSC_MASK (0x2U) #define USBHS_PORTSC1_CSC_SHIFT (1U) -/*! CSC - CSC */ +/*! CSC - Connect Status Change + * 0b0..No change + * 0b1..Change in current connect status + */ #define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK) #define USBHS_PORTSC1_PE_MASK (0x4U) #define USBHS_PORTSC1_PE_SHIFT (2U) -/*! PE - PE */ +/*! PE - Port Enabled/Disabled + * 0b0..Disable + * 0b1..Enable + */ #define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK) #define USBHS_PORTSC1_PEC_MASK (0x8U) #define USBHS_PORTSC1_PEC_SHIFT (3U) -/*! PEC - PEC */ +/*! PEC - Port Enable/Disable Change + * 0b0..No change + * 0b1..Port enabled/disabled status has changed + */ #define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK) #define USBHS_PORTSC1_OCA_MASK (0x10U) #define USBHS_PORTSC1_OCA_SHIFT (4U) -/*! OCA - OCA +/*! OCA - Over-Current Active * 0b1..This port currently has an over-current condition - * 0b0..This port does not have an over-current condition. + * 0b0..This port does not have an over-current condition */ #define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK) #define USBHS_PORTSC1_OCC_MASK (0x20U) #define USBHS_PORTSC1_OCC_SHIFT (5U) -/*! OCC - OCC */ +/*! OCC - Over-current Change */ #define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK) #define USBHS_PORTSC1_FPR_MASK (0x40U) #define USBHS_PORTSC1_FPR_SHIFT (6U) -/*! FPR - FPR */ +/*! FPR - Force Port Resume + * 0b0..No resume (K-state) detected/driven on port + * 0b1..Resume detected/driven on port + */ #define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK) #define USBHS_PORTSC1_SUSP_MASK (0x80U) #define USBHS_PORTSC1_SUSP_SHIFT (7U) -/*! SUSP - SUSP */ +/*! SUSP - Suspend + * 0b0..Port not in suspend state + * 0b1..Port in suspend state + */ #define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK) #define USBHS_PORTSC1_PR_MASK (0x100U) #define USBHS_PORTSC1_PR_SHIFT (8U) -/*! PR - PR */ +/*! PR - Port Reset + * 0b0..Port is not in reset + * 0b1..Port is in reset + */ #define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK) #define USBHS_PORTSC1_HSP_MASK (0x200U) #define USBHS_PORTSC1_HSP_SHIFT (9U) -/*! HSP - HSP */ +/*! HSP - High-Speed Port */ #define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK) #define USBHS_PORTSC1_LS_MASK (0xC00U) #define USBHS_PORTSC1_LS_SHIFT (10U) -/*! LS - LS +/*! LS - Line Status * 0b00..SE0 * 0b10..J-state * 0b01..K-state @@ -90285,17 +84417,17 @@ typedef struct { #define USBHS_PORTSC1_PP_MASK (0x1000U) #define USBHS_PORTSC1_PP_SHIFT (12U) -/*! PP - PP */ +/*! PP - Port Power */ #define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK) #define USBHS_PORTSC1_PO_MASK (0x2000U) #define USBHS_PORTSC1_PO_SHIFT (13U) -/*! PO - PO */ +/*! PO - Port Owner */ #define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK) #define USBHS_PORTSC1_PIC_MASK (0xC000U) #define USBHS_PORTSC1_PIC_SHIFT (14U) -/*! PIC - PIC +/*! PIC - Port Indicator Control * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green @@ -90305,7 +84437,7 @@ typedef struct { #define USBHS_PORTSC1_PTC_MASK (0xF0000U) #define USBHS_PORTSC1_PTC_SHIFT (16U) -/*! PTC - PTC +/*! PTC - Port Test Control * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE @@ -90320,22 +84452,22 @@ typedef struct { #define USBHS_PORTSC1_WKCN_MASK (0x100000U) #define USBHS_PORTSC1_WKCN_SHIFT (20U) -/*! WKCN - WKCN */ +/*! WKCN - Wake on Connect Enable (WKCNNT_E) */ #define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK) #define USBHS_PORTSC1_WKDC_MASK (0x200000U) #define USBHS_PORTSC1_WKDC_SHIFT (21U) -/*! WKDC - WKDC */ +/*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */ #define USBHS_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK) #define USBHS_PORTSC1_WKOC_MASK (0x400000U) #define USBHS_PORTSC1_WKOC_SHIFT (22U) -/*! WKOC - WKOC */ +/*! WKOC - Wake on Over-current Enable (WKOC_E) */ #define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK) #define USBHS_PORTSC1_PHCD_MASK (0x800000U) #define USBHS_PORTSC1_PHCD_SHIFT (23U) -/*! PHCD - PHCD +/*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD) * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ @@ -90343,7 +84475,7 @@ typedef struct { #define USBHS_PORTSC1_PFSC_MASK (0x1000000U) #define USBHS_PORTSC1_PFSC_SHIFT (24U) -/*! PFSC - PFSC +/*! PFSC - Port Force Full Speed Connect * 0b1..Forced to full speed * 0b0..Normal operation */ @@ -90351,12 +84483,12 @@ typedef struct { #define USBHS_PORTSC1_PTS_2_MASK (0x2000000U) #define USBHS_PORTSC1_PTS_2_SHIFT (25U) -/*! PTS_2 - PTS_2 */ +/*! PTS_2 - Parallel Transceiver Select */ #define USBHS_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK) #define USBHS_PORTSC1_PSPD_MASK (0xC000000U) #define USBHS_PORTSC1_PSPD_SHIFT (26U) -/*! PSPD - PSPD +/*! PSPD - Port Speed * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed @@ -90366,154 +84498,163 @@ typedef struct { #define USBHS_PORTSC1_PTW_MASK (0x10000000U) #define USBHS_PORTSC1_PTW_SHIFT (28U) -/*! PTW - PTW - * 0b0..Select the 8-bit UTMI interface [60MHz] - * 0b1..Select the 16-bit UTMI interface [30MHz] +/*! PTW - Parallel Transceiver Width - Read/Write + * 0b0..Select the 8-bit UTMI interface [60 MHz] + * 0b1..Select the 16-bit UTMI interface [30 MHz] */ #define USBHS_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK) #define USBHS_PORTSC1_STS_MASK (0x20000000U) #define USBHS_PORTSC1_STS_SHIFT (29U) -/*! STS - STS */ +/*! STS - Serial Transceiver Select + * 0b0..Parallel Interface signals is selected + * 0b1..Serial Interface Engine is selected + */ #define USBHS_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK) #define USBHS_PORTSC1_PTS_1_MASK (0xC0000000U) #define USBHS_PORTSC1_PTS_1_SHIFT (30U) -/*! PTS_1 - PTS_1 */ +/*! PTS_1 - Parallel Transceiver Select */ #define USBHS_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK) /*! @} */ -/*! @name OTGSC - On-The-Go Status & control */ +/*! @name OTGSC - On-The-Go Status & Control */ /*! @{ */ #define USBHS_OTGSC_VD_MASK (0x1U) #define USBHS_OTGSC_VD_SHIFT (0U) -/*! VD - VD */ +/*! VD - VBUS Discharge */ #define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK) #define USBHS_OTGSC_VC_MASK (0x2U) #define USBHS_OTGSC_VC_SHIFT (1U) -/*! VC - VC */ +/*! VC - VBUS Charge */ #define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK) #define USBHS_OTGSC_OT_MASK (0x8U) #define USBHS_OTGSC_OT_SHIFT (3U) -/*! OT - OT */ +/*! OT - OTG Termination */ #define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK) #define USBHS_OTGSC_DP_MASK (0x10U) #define USBHS_OTGSC_DP_SHIFT (4U) -/*! DP - DP */ +/*! DP - Data Pulsing */ #define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK) #define USBHS_OTGSC_IDPU_MASK (0x20U) #define USBHS_OTGSC_IDPU_SHIFT (5U) -/*! IDPU - IDPU */ +/*! IDPU - ID Pullup + * 0b0..Off + * 0b1..On + */ #define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK) #define USBHS_OTGSC_ID_MASK (0x100U) #define USBHS_OTGSC_ID_SHIFT (8U) -/*! ID - ID */ +/*! ID - USB ID + * 0b0..A device + * 0b1..B device + */ #define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK) #define USBHS_OTGSC_AVV_MASK (0x200U) #define USBHS_OTGSC_AVV_SHIFT (9U) -/*! AVV - AVV */ +/*! AVV - A VBus Valid */ #define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK) #define USBHS_OTGSC_ASV_MASK (0x400U) #define USBHS_OTGSC_ASV_SHIFT (10U) -/*! ASV - ASV */ +/*! ASV - A Session Valid */ #define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK) #define USBHS_OTGSC_BSV_MASK (0x800U) #define USBHS_OTGSC_BSV_SHIFT (11U) -/*! BSV - BSV */ +/*! BSV - B Session Valid */ #define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK) #define USBHS_OTGSC_BSE_MASK (0x1000U) #define USBHS_OTGSC_BSE_SHIFT (12U) -/*! BSE - BSE */ +/*! BSE - B Session End */ #define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK) #define USBHS_OTGSC_TOG_1MS_MASK (0x2000U) #define USBHS_OTGSC_TOG_1MS_SHIFT (13U) -/*! TOG_1MS - TOG_1MS */ +/*! TOG_1MS - 1 Millisecond Timer Toggle */ #define USBHS_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK) #define USBHS_OTGSC_DPS_MASK (0x4000U) #define USBHS_OTGSC_DPS_SHIFT (14U) -/*! DPS - DPS */ +/*! DPS - Data Bus Pulsing Status */ #define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK) #define USBHS_OTGSC_IDIS_MASK (0x10000U) #define USBHS_OTGSC_IDIS_SHIFT (16U) -/*! IDIS - IDIS */ +/*! IDIS - USB ID Interrupt Status */ #define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK) #define USBHS_OTGSC_AVVIS_MASK (0x20000U) #define USBHS_OTGSC_AVVIS_SHIFT (17U) -/*! AVVIS - AVVIS */ +/*! AVVIS - A VBus Valid Interrupt Status */ #define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK) #define USBHS_OTGSC_ASVIS_MASK (0x40000U) #define USBHS_OTGSC_ASVIS_SHIFT (18U) -/*! ASVIS - ASVIS */ +/*! ASVIS - A Session Valid Interrupt Status */ #define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK) #define USBHS_OTGSC_BSVIS_MASK (0x80000U) #define USBHS_OTGSC_BSVIS_SHIFT (19U) -/*! BSVIS - BSVIS */ +/*! BSVIS - B Session Valid Interrupt Status */ #define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK) #define USBHS_OTGSC_BSEIS_MASK (0x100000U) #define USBHS_OTGSC_BSEIS_SHIFT (20U) -/*! BSEIS - BSEIS */ +/*! BSEIS - B Session End Interrupt Status */ #define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK) #define USBHS_OTGSC_STATUS_1MS_MASK (0x200000U) #define USBHS_OTGSC_STATUS_1MS_SHIFT (21U) -/*! STATUS_1MS - STATUS_1MS */ +/*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */ #define USBHS_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK) #define USBHS_OTGSC_DPIS_MASK (0x400000U) #define USBHS_OTGSC_DPIS_SHIFT (22U) -/*! DPIS - DPIS */ +/*! DPIS - Data Pulse Interrupt Status */ #define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK) #define USBHS_OTGSC_IDIE_MASK (0x1000000U) #define USBHS_OTGSC_IDIE_SHIFT (24U) -/*! IDIE - IDIE */ +/*! IDIE - USB ID Interrupt Enable */ #define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK) #define USBHS_OTGSC_AVVIE_MASK (0x2000000U) #define USBHS_OTGSC_AVVIE_SHIFT (25U) -/*! AVVIE - AVVIE */ +/*! AVVIE - A VBus Valid Interrupt Enable */ #define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK) #define USBHS_OTGSC_ASVIE_MASK (0x4000000U) #define USBHS_OTGSC_ASVIE_SHIFT (26U) -/*! ASVIE - ASVIE */ +/*! ASVIE - A Session Valid Interrupt Enable */ #define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK) #define USBHS_OTGSC_BSVIE_MASK (0x8000000U) #define USBHS_OTGSC_BSVIE_SHIFT (27U) -/*! BSVIE - BSVIE */ +/*! BSVIE - B Session Valid Interrupt Enable */ #define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK) #define USBHS_OTGSC_BSEIE_MASK (0x10000000U) #define USBHS_OTGSC_BSEIE_SHIFT (28U) -/*! BSEIE - BSEIE */ +/*! BSEIE - B Session End Interrupt Enable */ #define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK) #define USBHS_OTGSC_EN_1MS_MASK (0x20000000U) #define USBHS_OTGSC_EN_1MS_SHIFT (29U) -/*! EN_1MS - EN_1MS */ +/*! EN_1MS - 1 Millisecond Timer Interrupt Enable */ #define USBHS_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK) #define USBHS_OTGSC_DPIE_MASK (0x40000000U) #define USBHS_OTGSC_DPIE_SHIFT (30U) -/*! DPIE - DPIE */ +/*! DPIE - Data Pulse Interrupt Enable */ #define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK) /*! @} */ @@ -90522,7 +84663,7 @@ typedef struct { #define USBHS_USBMODE_CM_MASK (0x3U) #define USBHS_USBMODE_CM_SHIFT (0U) -/*! CM - CM +/*! CM - Controller Mode * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] @@ -90532,15 +84673,15 @@ typedef struct { #define USBHS_USBMODE_ES_MASK (0x4U) #define USBHS_USBMODE_ES_SHIFT (2U) -/*! ES - ES - * 0b0..Little Endian [Default] +/*! ES - Endian Select + * 0b0..Little Endian * 0b1..Big Endian */ #define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK) #define USBHS_USBMODE_SLOM_MASK (0x8U) #define USBHS_USBMODE_SLOM_SHIFT (3U) -/*! SLOM - SLOM +/*! SLOM - Setup Lockout Mode * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off */ @@ -90548,7 +84689,10 @@ typedef struct { #define USBHS_USBMODE_SDIS_MASK (0x10U) #define USBHS_USBMODE_SDIS_SHIFT (4U) -/*! SDIS - SDIS */ +/*! SDIS - Stream Disable Mode + * 0b0..Inactive + * 0b1..Active + */ #define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK) /*! @} */ @@ -90557,7 +84701,7 @@ typedef struct { #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */ +/*! ENDPTSETUPSTAT - Setup Endpoint Status */ #define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ @@ -90566,12 +84710,12 @@ typedef struct { #define USBHS_ENDPTPRIME_PERB_MASK (0xFFU) #define USBHS_ENDPTPRIME_PERB_SHIFT (0U) -/*! PERB - PERB */ +/*! PERB - Prime Endpoint Receive Buffer */ #define USBHS_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK) #define USBHS_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USBHS_ENDPTPRIME_PETB_SHIFT (16U) -/*! PETB - PETB */ +/*! PETB - Prime Endpoint Transmit Buffer */ #define USBHS_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK) /*! @} */ @@ -90580,12 +84724,12 @@ typedef struct { #define USBHS_ENDPTFLUSH_FERB_MASK (0xFFU) #define USBHS_ENDPTFLUSH_FERB_SHIFT (0U) -/*! FERB - FERB */ +/*! FERB - Flush Endpoint Receive Buffer */ #define USBHS_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK) #define USBHS_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USBHS_ENDPTFLUSH_FETB_SHIFT (16U) -/*! FETB - FETB */ +/*! FETB - Flush Endpoint Transmit Buffer */ #define USBHS_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK) /*! @} */ @@ -90594,12 +84738,12 @@ typedef struct { #define USBHS_ENDPTSTAT_ERBR_MASK (0xFFU) #define USBHS_ENDPTSTAT_ERBR_SHIFT (0U) -/*! ERBR - ERBR */ +/*! ERBR - Endpoint Receive Buffer Ready */ #define USBHS_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK) #define USBHS_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USBHS_ENDPTSTAT_ETBR_SHIFT (16U) -/*! ETBR - ETBR */ +/*! ETBR - Endpoint Transmit Buffer Ready */ #define USBHS_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK) /*! @} */ @@ -90608,46 +84752,62 @@ typedef struct { #define USBHS_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USBHS_ENDPTCOMPLETE_ERCE_SHIFT (0U) -/*! ERCE - ERCE */ +/*! ERCE - Endpoint Receive Complete Event */ #define USBHS_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK) #define USBHS_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USBHS_ENDPTCOMPLETE_ETCE_SHIFT (16U) -/*! ETCE - ETCE */ +/*! ETCE - Endpoint Transmit Complete Event */ #define USBHS_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ -/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @name ENDPTCTRL0 - Endpoint Control 0 */ /*! @{ */ #define USBHS_ENDPTCTRL0_RXS_MASK (0x1U) #define USBHS_ENDPTCTRL0_RXS_SHIFT (0U) -/*! RXS - RXS */ +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK) #define USBHS_ENDPTCTRL0_RXT_MASK (0xCU) #define USBHS_ENDPTCTRL0_RXT_SHIFT (2U) -/*! RXT - RXT */ +/*! RXT - RX Endpoint Type + * 0b00..Control + */ #define USBHS_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK) #define USBHS_ENDPTCTRL0_RXE_MASK (0x80U) #define USBHS_ENDPTCTRL0_RXE_SHIFT (7U) -/*! RXE - RXE */ +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK) #define USBHS_ENDPTCTRL0_TXS_MASK (0x10000U) #define USBHS_ENDPTCTRL0_TXS_SHIFT (16U) -/*! TXS - TXS */ +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK) #define USBHS_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USBHS_ENDPTCTRL0_TXT_SHIFT (18U) -/*! TXT - TXT */ +/*! TXT - TX Endpoint Type + * 0b00..Control + */ #define USBHS_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK) #define USBHS_ENDPTCTRL0_TXE_MASK (0x800000U) #define USBHS_ENDPTCTRL0_TXE_SHIFT (23U) -/*! TXE - TXE */ +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK) /*! @} */ @@ -90656,62 +84816,98 @@ typedef struct { #define USBHS_ENDPTCTRL_RXS_MASK (0x1U) #define USBHS_ENDPTCTRL_RXS_SHIFT (0U) -/*! RXS - RXS */ +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK) #define USBHS_ENDPTCTRL_RXD_MASK (0x2U) #define USBHS_ENDPTCTRL_RXD_SHIFT (1U) -/*! RXD - RXD */ +/*! RXD - RX Endpoint Data Sink + * 0b0..Dual Port Memory Buffer/DMA Engine + */ #define USBHS_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK) #define USBHS_ENDPTCTRL_RXT_MASK (0xCU) #define USBHS_ENDPTCTRL_RXT_SHIFT (2U) -/*! RXT - RXT */ +/*! RXT - RX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ #define USBHS_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK) #define USBHS_ENDPTCTRL_RXI_MASK (0x20U) #define USBHS_ENDPTCTRL_RXI_SHIFT (5U) -/*! RXI - RXI */ +/*! RXI - RX Data Toggle Inhibit + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK) #define USBHS_ENDPTCTRL_RXR_MASK (0x40U) #define USBHS_ENDPTCTRL_RXR_SHIFT (6U) -/*! RXR - RXR */ +/*! RXR - RX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ #define USBHS_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK) #define USBHS_ENDPTCTRL_RXE_MASK (0x80U) #define USBHS_ENDPTCTRL_RXE_SHIFT (7U) -/*! RXE - RXE */ +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK) #define USBHS_ENDPTCTRL_TXS_MASK (0x10000U) #define USBHS_ENDPTCTRL_TXS_SHIFT (16U) -/*! TXS - TXS */ +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ #define USBHS_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK) #define USBHS_ENDPTCTRL_TXD_MASK (0x20000U) #define USBHS_ENDPTCTRL_TXD_SHIFT (17U) -/*! TXD - TXD */ +/*! TXD - TX Endpoint Data Source + * 0b0..Dual Port Memory Buffer/DMA Engine + */ #define USBHS_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK) #define USBHS_ENDPTCTRL_TXT_MASK (0xC0000U) #define USBHS_ENDPTCTRL_TXT_SHIFT (18U) -/*! TXT - TXT */ +/*! TXT - TX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ #define USBHS_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK) #define USBHS_ENDPTCTRL_TXI_MASK (0x200000U) #define USBHS_ENDPTCTRL_TXI_SHIFT (21U) -/*! TXI - TXI */ +/*! TXI - TX Data Toggle Inhibit + * 0b0..PID sequencing enabled + * 0b1..PID sequencing disabled + */ #define USBHS_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK) #define USBHS_ENDPTCTRL_TXR_MASK (0x400000U) #define USBHS_ENDPTCTRL_TXR_SHIFT (22U) -/*! TXR - TXR */ +/*! TXR - TX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ #define USBHS_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK) #define USBHS_ENDPTCTRL_TXE_MASK (0x800000U) #define USBHS_ENDPTCTRL_TXE_SHIFT (23U) -/*! TXE - TXE */ +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ #define USBHS_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK) /*! @} */ @@ -91187,10 +85383,10 @@ typedef struct { /** USBNC - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL1; /**< USB OTG Control 1 Register, offset: 0x0 */ - __IO uint32_t CTRL2; /**< USB OTG Control 2 Register, offset: 0x4 */ + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ uint8_t RESERVED_0[8]; - __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control Register, offset: 0x10 */ + __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control, offset: 0x10 */ } USBNC_Type; /* ---------------------------------------------------------------------------- @@ -91202,20 +85398,20 @@ typedef struct { * @{ */ -/*! @name CTRL1 - USB OTG Control 1 Register */ +/*! @name CTRL1 - USB OTG Control 1 */ /*! @{ */ #define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) -/*! OVER_CUR_DIS - OVER_CUR_DIS - * 0b1..Disables overcurrent detection - * 0b0..Enables overcurrent detection +/*! OVER_CUR_DIS - Disable Overcurrent Detection + * 0b1..Disables + * 0b0..Enables */ #define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) -/*! OVER_CUR_POL - OVER_CUR_POL +/*! OVER_CUR_POL - Polarity of Overcurrent * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ @@ -91223,7 +85419,7 @@ typedef struct { #define USBNC_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_CTRL1_PWR_POL_SHIFT (9U) -/*! PWR_POL - PWR_POL +/*! PWR_POL - Power Polarity * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ @@ -91231,7 +85427,7 @@ typedef struct { #define USBNC_CTRL1_WIE_MASK (0x400U) #define USBNC_CTRL1_WIE_SHIFT (10U) -/*! WIE - WIE +/*! WIE - Wake-up Interrupt Enable * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ @@ -91239,15 +85435,15 @@ typedef struct { #define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) -/*! WKUP_SW_EN - WKUP_SW_EN - * 0b1..Enable - * 0b0..Disable +/*! WKUP_SW_EN - Software Wake-up Enable + * 0b1..Enables + * 0b0..Disables */ #define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) #define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_CTRL1_WKUP_SW_SHIFT (15U) -/*! WKUP_SW - WKUP_SW +/*! WKUP_SW - Software Wake-up * 0b1..Force wake-up * 0b0..Inactive */ @@ -91255,43 +85451,43 @@ typedef struct { #define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) -/*! WKUP_ID_EN - WKUP_ID_EN - * 0b1..Enable - * 0b0..Disable +/*! WKUP_ID_EN - Wake-up on ID Change Enable + * 0b1..Enables + * 0b0..Disables */ #define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) #define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) -/*! WKUP_VBUS_EN - WKUP_VBUS_EN - * 0b1..Enable - * 0b0..Disable +/*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable + * 0b1..Enables + * 0b0..Disables */ #define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) -/*! WKUP_DPDM_EN - Wake-up on DPDM change enable - * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. - * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. +/*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable + * 0b1..DPDM changes wake-up to be enabled, it is for device only + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0 */ #define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_CTRL1_WIR_MASK (0x80000000U) #define USBNC_CTRL1_WIR_SHIFT (31U) -/*! WIR - WIR - * 0b1..Wake-up Interrupt Request received - * 0b0..No wake-up interrupt request received +/*! WIR - Wake-up Interrupt Request + * 0b1..Request received + * 0b0..No request received */ #define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) /*! @} */ -/*! @name CTRL2 - USB OTG Control 2 Register */ +/*! @name CTRL2 - USB OTG Control 2 */ /*! @{ */ #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) -/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL +/*! VBUS_SOURCE_SEL - VBUS Source Select * 0b00..vbus_valid * 0b01..sess_valid * 0b10..sess_valid @@ -91308,25 +85504,25 @@ typedef struct { #define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) -/*! LOWSPEED_EN - LOWSPEED_EN +/*! LOWSPEED_EN - Low Speed Enable * 0b0..Default */ #define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) #define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) -/*! UTMI_CLK_VLD - UTMI_CLK_VLD +/*! UTMI_CLK_VLD - UTMI Clock Valid * 0b0..Default */ #define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ -/*! @name HSIC_CTRL - USB Host HSIC Control Register */ +/*! @name HSIC_CTRL - USB Host HSIC Control */ /*! @{ */ #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) -/*! HSIC_CLK_ON - HSIC_CLK_ON +/*! HSIC_CLK_ON - HSIC Clock ON * 0b1..Active * 0b0..Inactive */ @@ -91334,7 +85530,7 @@ typedef struct { #define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) -/*! HSIC_EN - HSIC_EN +/*! HSIC_EN - Host HSIC Enable * 0b1..Enabled * 0b0..Disabled */ @@ -91342,7 +85538,7 @@ typedef struct { #define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) -/*! CLK_VLD - CLK_VLD +/*! CLK_VLD - Clock Valid * 0b1..Valid * 0b0..Invalid */ @@ -91433,69 +85629,69 @@ typedef struct { /** USBPHY - Register Layout Typedef */ typedef struct { - __IO uint32_t PWD; /**< Power Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< Power Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< Power Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< Power Down Register, offset: 0xC */ - __IO uint32_t TX; /**< Tx Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< Tx Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< Tx Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< Tx Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< Rx Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< Rx Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< Rx Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< Rx Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< General Purpose Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< General Purpose Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< General Purpose Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< General Purpose Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< Status Register, offset: 0x40 */ + __IO uint32_t PWD; /**< Power Down, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< Power Down, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< Power Down, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< Power Down, offset: 0xC */ + __IO uint32_t TX; /**< TX Control, offset: 0x10 */ + __IO uint32_t TX_SET; /**< TX Control, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< TX Control, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< TX Control, offset: 0x1C */ + __IO uint32_t RX; /**< RX Control, offset: 0x20 */ + __IO uint32_t RX_SET; /**< RX Control, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< RX Control, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< RX Control, offset: 0x2C */ + __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< General Purpose Control, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< General Purpose Control, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< General Purpose Control, offset: 0x3C */ + __IO uint32_t STATUS; /**< Status, offset: 0x40 */ uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< Debug Register 0, offset: 0x5C */ + __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< Debug 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< Debug 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< Debug 0, offset: 0x5C */ uint8_t RESERVED_1[32]; - __I uint32_t VERSION; /**< Version Register, offset: 0x80 */ + __I uint32_t VERSION; /**< Version, offset: 0x80 */ uint8_t RESERVED_2[12]; - __IO uint32_t IP; /**< IP Block Register, offset: 0x90 */ - __IO uint32_t IP_SET; /**< IP Block Register, offset: 0x94 */ - __IO uint32_t IP_CLR; /**< IP Block Register, offset: 0x98 */ - __IO uint32_t IP_TOG; /**< IP Block Register, offset: 0x9C */ - __IO uint32_t PLL_SIC; /**< PLL SIC Register, offset: 0xA0 */ - __IO uint32_t PLL_SIC_SET; /**< PLL SIC Register, offset: 0xA4 */ - __IO uint32_t PLL_SIC_CLR; /**< PLL SIC Register, offset: 0xA8 */ - __IO uint32_t PLL_SIC_TOG; /**< PLL SIC Register, offset: 0xAC */ + __IO uint32_t IP; /**< IP Block, offset: 0x90 */ + __IO uint32_t IP_SET; /**< IP Block, offset: 0x94 */ + __IO uint32_t IP_CLR; /**< IP Block, offset: 0x98 */ + __IO uint32_t IP_TOG; /**< IP Block, offset: 0x9C */ + __IO uint32_t PLL_SIC; /**< PLL SIC, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< PLL SIC, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< PLL SIC, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< PLL SIC, offset: 0xAC */ uint8_t RESERVED_3[16]; - __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect Register, offset: 0xC0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect Register, offset: 0xC4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect Register, offset: 0xC8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status Register, offset: 0xD0 */ - __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status Register, offset: 0xD4 */ - __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status Register, offset: 0xD8 */ - __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status Register, offset: 0xDC */ - __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect Register, offset: 0xE0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect Register, offset: 0xE4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect Register, offset: 0xE8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect Register, offset: 0xEC */ - __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status Register, offset: 0xF0 */ - __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status Register, offset: 0xF4 */ - __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status Register, offset: 0xF8 */ - __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status Register, offset: 0xFC */ - __IO uint32_t ANACTRL; /**< Analog Control Register, offset: 0x100 */ - __IO uint32_t ANACTRL_SET; /**< Analog Control Register, offset: 0x104 */ - __IO uint32_t ANACTRL_CLR; /**< Analog Control Register, offset: 0x108 */ - __IO uint32_t ANACTRL_TOG; /**< Analog Control Register, offset: 0x10C */ + __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */ + __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status, offset: 0xD4 */ + __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status, offset: 0xD8 */ + __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status, offset: 0xDC */ + __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status, offset: 0xF0 */ + __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status, offset: 0xF4 */ + __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status, offset: 0xF8 */ + __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status, offset: 0xFC */ + __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< Analog Control, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< Analog Control, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< Analog Control, offset: 0x10C */ uint8_t RESERVED_4[32]; - __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim Register, offset: 0x130 */ - __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim Register, offset: 0x134 */ - __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim Register, offset: 0x138 */ - __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim Register, offset: 0x13C */ - __IO uint32_t PFDA; /**< PFD Register A, offset: 0x140 */ - __IO uint32_t PFDA_SET; /**< PFD Register A, offset: 0x144 */ - __IO uint32_t PFDA_CLR; /**< PFD Register A, offset: 0x148 */ - __IO uint32_t PFDA_TOG; /**< PFD Register A, offset: 0x14C */ + __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim, offset: 0x130 */ + __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim, offset: 0x134 */ + __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim, offset: 0x138 */ + __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim, offset: 0x13C */ + __IO uint32_t PFDA; /**< PFD A, offset: 0x140 */ + __IO uint32_t PFDA_SET; /**< PFD A, offset: 0x144 */ + __IO uint32_t PFDA_CLR; /**< PFD A, offset: 0x148 */ + __IO uint32_t PFDA_TOG; /**< PFD A, offset: 0x14C */ } USBPHY_Type; /* ---------------------------------------------------------------------------- @@ -91507,576 +85703,637 @@ typedef struct { * @{ */ -/*! @name PWD - Power Down Register */ +/*! @name PWD - Power Down */ /*! @{ */ #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers - * 0b0..Provide bias to allow enable of FS Tx drivers - * 0b1..Power down FS Tx drivers and configure them to high impedance state +/*! TXPWDFS - Power Down USB FS TX Drivers + * 0b0..Provide bias to enable + * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block - * 0b0..Enable current mirror circuits for general transceiver/detector bias - * 0b1..Power down current bias mirrors +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror - * 0b0..Enable Tx V-to-I converter and current mirrors - * 0b1..Power down Tx V-to-I converter and current mirrors +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator - * 0b0..Enable the HS Rx envelope detector and Host Disconnect comparator - * 0b1..Power down the HS Rx envelope detector and Host Disconnect comparator +/*! RXPWDENV - Power Down USB HS RX Envelope Detector + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver - * 0b0..Enable the FS differential receiver - * 0b1..Power down the FS differential receiver +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver - * 0b0..Enable the HS differential receiver - * 0b1..Power down the HS differential receiver +/*! RXPWDDIFF - Power Down USB HS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator - * 0b0..Enable the PHY's receiver block except for the FS differential receiver - * 0b1..Power down the PHY's receiver block except for the FS differential receiver +/*! RXPWDRX - Power Down USBPHY Receiver Circuits + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) /*! @} */ -/*! @name PWD_SET - Power Down Register */ +/*! @name PWD_SET - Power Down */ /*! @{ */ #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers */ +/*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block */ +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror */ +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator */ +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver */ +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver */ +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator */ +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) /*! @} */ -/*! @name PWD_CLR - Power Down Register */ +/*! @name PWD_CLR - Power Down */ /*! @{ */ #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers */ +/*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block */ +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror */ +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator */ +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver */ +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver */ +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator */ +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) /*! @} */ -/*! @name PWD_TOG - Power Down Register */ +/*! @name PWD_TOG - Power Down */ /*! @{ */ #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - Power down USB FS drivers */ +/*! TXPWDFS - Power Down USB FS TX Drivers */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - Power down USBPHY current bias block */ +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - Power down USBPHY V-I converter and current mirror */ +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - Power down USB HS receiver envelope detector and Host Disconnect comparator */ +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - Power down USB FS differential receiver */ +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - Power down USB HS differential receiver */ +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - Power down USBPHY receiver circuits except the FS differential comparator */ +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) /*! @} */ -/*! @name TX - Tx Control Register */ +/*! @name TX - TX Control */ /*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) #define USBPHY_TX_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) /*! @} */ -/*! @name TX_SET - Tx Control Register */ +/*! @name TX_SET - TX Control */ /*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) #define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) /*! @} */ -/*! @name TX_CLR - Tx Control Register */ +/*! @name TX_CLR - TX Control */ /*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) #define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) /*! @} */ -/*! @name TX_TOG - Tx Control Register */ +/*! @name TX_TOG - TX Control */ /*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - HS Tx output current trim */ +/*! D_CAL - HS TX Output Current Trim */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) #define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) -/*! TXCAL45DN - DM series termination resistance trim */ +/*! TXCAL45DN - DM Series Termination Resistance Trim */ #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - DP series termination resistance trim */ +/*! TXCAL45DP - DP Series Termination Resistance Trim */ #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) /*! @} */ -/*! @name RX - Rx Control Register */ +/*! @name RX - RX Control */ /*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V +/*! ENVADJ - Envelope Detector Trip Point + * 0b000..0.1000 V + * 0b001..0.1125 V + * 0b010..0.1250 V + * 0b011..0.0875 V * 0b1xx.. */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V +/*! DISCONADJ - Disconnect Detector Trip Point + * 0b000..0.56875 V + * 0b001..0.55000 V + * 0b010..0.58125 V + * 0b011..0.60000 V * 0b1xx.. */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) /*! @} */ -/*! @name RX_SET - Rx Control Register */ +/*! @name RX_SET - RX Control */ /*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point */ +/*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point */ +/*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) /*! @} */ -/*! @name RX_CLR - Rx Control Register */ +/*! @name RX_CLR - RX Control */ /*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point */ +/*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point */ +/*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) /*! @} */ -/*! @name RX_TOG - Rx Control Register */ +/*! @name RX_TOG - RX Control */ /*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - Envelope detector trip point */ +/*! ENVADJ - Envelope Detector Trip Point */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - Disconnect detector trip point */ +/*! DISCONADJ - Disconnect Detector Trip Point */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) /*! @} */ -/*! @name CTRL - General Purpose Control Register */ +/*! @name CTRL - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt + * 0b0..Connected + * 0b1..Disconnected + */ #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection - * 0b0..Disables 200 kohm pullup resistors on USB_DP and USB_DM pins - * 0b1..Enables 200 kohm pullup resistors on USB_DP and USB_DM pins +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity + * 0b0..Plugged in + * 0b1..Unplugged + */ #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt + * 0b0..No ID change interrupt + * 0b1..ID change interrupt + */ #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector - * 0b0..Disable the PHY's internal ID pin detection circuit - * 0b1..Enable the PHY's internal ID pin detection circuit +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky + * 0b0..During the resume or reset state signaling period + * 0b1..Until you write 0 to it + */ #define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt + * 0b0..No resume interrupt + * 0b1..Resume interrupt + */ #define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable + * 0b0..Disable + * 0b1..Enable + */ #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value - * 0b0..False, when ID resistance to ground is less than Ra_Plug_ID, indicating Host (A) side - * 0b1..True, when ID resistance is greater than Rb_Plug_ID, indicating Device (B) side +/*! OTG_ID_VALUE - OTG ID Value + * 0b0..Host + * 0b1..Device */ #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -/*! UTMI_SUSPENDM - UTMI Suspend */ +/*! UTMI_SUSPENDM - UTMI Suspend + * 0b0..Not suspended + * 0b1..Suspended + */ #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate + * 0b0..Run clocks + * 0b1..Gate clocks + */ #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset + * 0b0..Release from reset + * 0b1..Soft-reset + */ #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) /*! @} */ -/*! @name CTRL_SET - General Purpose Control Register */ +/*! @name CTRL_SET - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */ +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector */ +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value */ +/*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) @@ -92086,126 +86343,126 @@ typedef struct { #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset */ #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) /*! @} */ -/*! @name CTRL_CLR - General Purpose Control Register */ +/*! @name CTRL_CLR - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */ +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector */ +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value */ +/*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) @@ -92215,126 +86472,126 @@ typedef struct { #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset */ #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) /*! @} */ -/*! @name CTRL_TOG - General Purpose Control Register */ +/*! @name CTRL_TOG - General Purpose Control */ /*! @{ */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) -/*! ENOTG_ID_CHG_IRQ - EN ID change IRQ */ +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -/*! ENHOSTDISCONDETECT - Disconnect detect */ +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -/*! ENIRQHOSTDISCON - Enable IRQ for Host disconnect */ +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -/*! HOSTDISCONDETECT_IRQ - Device disconnect indication */ +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) -/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */ +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -/*! DEVPLUGIN_POLARITY - Device plugin polarity interrupt configuration for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) -/*! OTG_ID_CHG_IRQ - OTG ID change IRQ */ +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) -/*! ENOTGIDDETECT - Enable internal OTG ID detector */ +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -/*! RESUMEIRQSTICKY - Resume IRQ */ +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -/*! ENIRQRESUMEDETECT - Enable IRQ Resume detect */ +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -/*! RESUME_IRQ - Resume IRQ */ +/*! RESUME_IRQ - Resume Interrupt */ #define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) -/*! ENIRQDEVPLUGIN - Enable IRQ for non-standard resistive plugged-in detection */ +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -/*! DEVPLUGIN_IRQ - Device connected indicator for non-standard resistive plugged-in detection */ +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) -/*! DATA_ON_LRADC - APB clock switch option */ +/*! DATA_ON_LRADC - APB Clock Switch Option */ #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -/*! ENUTMILEVEL2 - Enable level 2 operation */ +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -/*! ENUTMILEVEL3 - Enable level 3 operation */ +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -/*! ENIRQWAKEUP - Enable Wakeup IRQ */ +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -/*! WAKEUP_IRQ - Wakeup IRQ */ +/*! WAKEUP_IRQ - Wake-Up Interrupt */ #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) -/*! AUTORESUME_EN - Enable autoresume */ +/*! AUTORESUME_EN - Autoresume Enable */ #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -/*! ENAUTOCLR_CLKGATE - Autoclear clock gate */ +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -/*! ENAUTOCLR_PHY_PWD - Autoclear PWD register bits */ +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -/*! OTG_ID_VALUE - ID value */ +/*! OTG_ID_VALUE - OTG ID Value */ #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) @@ -92344,57 +86601,57 @@ typedef struct { #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -/*! CLKGATE - UTMI clock gate */ +/*! CLKGATE - UTMI Clock Gate */ #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -/*! SFTRST - Software reset */ +/*! SFTRST - Software Reset */ #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) /*! @} */ -/*! @name STATUS - Status Register */ +/*! @name STATUS - Status */ /*! @{ */ #define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) #define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) -/*! OK_STATUS_3V - USB 3.3 V / 1.8 V supply status - * 0b0..One or both of the 1.8 V and 3.3 V supplies to the PHY are not powered - * 0b1..Both of the 1.8 V and 3.3 V supplies to the PHY are powered +/*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status + * 0b0..Not powered + * 0b1..Powered */ #define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS - Host disconnect status - * 0b0..USB cable disconnect has not been detected at the local Host - * 0b1..USB cable disconnect has been detected at the local Host +/*! HOSTDISCONDETECT_STATUS - Host Disconnect Status + * 0b0..Not detected + * 0b1..Detected */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection. - * 0b0..No attachment to a USB Host is detected - * 0b1..Cable attachment to a USB Host is detected +/*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection + * 0b0..No attachment detected + * 0b1..Cable attachment detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -/*! OTGID_STATUS - OTG ID status - * 0b0..False, when ID resistance to ground is less than Ra_Plug_ID, indicating Host (A) side - * 0b1..True, when ID resistance is greater than Rb_Plug_ID, indicating Device (B) side +/*! OTGID_STATUS - OTG ID Status + * 0b0..Host + * 0b1..Device */ #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -/*! RESUME_STATUS - Resume status */ +/*! RESUME_STATUS - Resume Status */ #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ -/*! @name DEBUG0 - Debug Register 0 */ +/*! @name DEBUG0 - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) @@ -92404,16 +86661,22 @@ typedef struct { #define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode + * 0b00..Disconnect + * 0b01..Connect + */ #define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode + * 0b00..Disable + * 0b01..Enable + */ #define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name DEBUG0_SET - Debug Register 0 */ +/*! @name DEBUG0_SET - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) @@ -92423,16 +86686,16 @@ typedef struct { #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name DEBUG0_CLR - Debug Register 0 */ +/*! @name DEBUG0_CLR - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) @@ -92442,16 +86705,16 @@ typedef struct { #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name DEBUG0_TOG - Debug Register 0 */ +/*! @name DEBUG0_TOG - Debug 0 */ /*! @{ */ #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) @@ -92461,181 +86724,181 @@ typedef struct { #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -/*! HSTPULLDOWN - Select DP/DM pulldown resistors in Host pulldown overdrive mode */ +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -/*! ENHSTPULLDOWN - Enable Host pulldown overdrive mode */ +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) /*! @} */ -/*! @name VERSION - Version Register */ +/*! @name VERSION - Version */ /*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) -/*! STEP - STEP */ +/*! STEP - Step */ #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) #define USBPHY_VERSION_MINOR_MASK (0xFF0000U) #define USBPHY_VERSION_MINOR_SHIFT (16U) -/*! MINOR - MINOR */ +/*! MINOR - Minor */ #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) -/*! MAJOR - MAJOR */ +/*! MAJOR - Major */ #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /*! @} */ -/*! @name IP - IP Block Register */ +/*! @name IP - IP Block */ /*! @{ */ #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name IP_SET - IP Block Register */ +/*! @name IP_SET - IP Block */ /*! @{ */ #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name IP_CLR - IP Block Register */ +/*! @name IP_CLR - IP Block */ /*! @{ */ #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name IP_TOG - IP Block Register */ +/*! @name IP_TOG - IP Block */ /*! @{ */ #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) -/*! POWER_CONTROL_SUSPEND_OPTION - Power control Suspend option */ +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ #define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK) /*! @} */ -/*! @name PLL_SIC - PLL SIC Register */ +/*! @name PLL_SIC - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend - * 0b0..Power up PLL without regard to state of UTMI_SUSPENDM - * 0b1..Power down PLL when in Suspend bus state +/*! MISC2_CONTROL0 - Miscellaneous Control + * 0b0..Power up PLL + * 0b1..Power down PLL */ #define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable - * 0b0..Disable PLL multi-phase 480 MHz clock outputs - * 0b1..Enable PLL multi-phase 480 MHz clock outputs +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control - * 0b0..Powers down the USB PLL - * 0b1..Allows powerup of USB PLL +/*! PLL_POWER - USB PLL Powerup Control + * 0b0..Power down + * 0b1..Allow powerup */ #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable - * 0b0..Disable PLL single phase 480 MHz clock output - * 0b1..Enable PLL single phase 480 MHz clock output +/*! PLL_ENABLE - PLL Output Clock Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) /*! PLL_BYPASS - Bypass USB PLL - * 0b0..Select PLL 480 MHz output clock for output mux - * 0b1..Select PLL input reference clock for output mux + * 0b0..480 MHz output clock + * 0b1..Input reference clock */ #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control - * 0b0..Control reference bias with PLL POWER internal state signal - * 0b1..Control reference bias with PLL_SIC[REFBIAS_PWD] +/*! REFBIAS_PWD_SEL - Reference Bias Power Control + * 0b0..PLL_POWER internal state signal + * 0b1..REFBIAS_PWD */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias - * 0b0..Enable master reference bias in direct power control mode - * 0b1..Power down master reference bias in direct power control mode +/*! REFBIAS_PWD - Power Down Reference Bias + * 0b0..Enable + * 0b1..Disable or power down */ #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator - * 0b0..Disable the local regulator for the PLL - * 0b1..Enable the local regulator for the PLL +/*! PLL_REG_ENABLE - Enable PLL Regulator + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration - * 0b000..Configure for 32 MHz input clock (Divide by 15) - * 0b001..Configure for 30 MHz input clock (Divide by 16) - * 0b010..Configure for 24 MHz input clock (Divide by 20) - * 0b011..Reserved, not usable for USB operation (Divide by 22) - * 0b100..Configure for 20 MHz input clock (Divide by 24) - * 0b101..Configure for 19.2 MHz input clock (Divide by 25) - * 0b110..Configure for 16 MHz input clock (Divide by 30) - * 0b111..Configure for 12 MHz input clock (Divide by 40) May give marginal jitter results. +/*! PLL_DIV_SEL - PLL Divider Value Configuration + * 0b000..Configure for a 32 MHz input clock (divide by 15) + * 0b001..Configure for a 30 MHz input clock (divide by 16) + * 0b010..Configure for a 24 MHz input clock (divide by 20) + * 0b011..Reserved, not usable for USB operation (divide by 22) + * 0b100..Configure for a 20 MHz input clock (divide by 24) + * 0b101..Configure for a 19.2 MHz input clock (divide by 25) + * 0b110..Configure for a 16 MHz input clock (divide by 30) + * 0b111..Configure for a 12 MHz input clock (divide by 40) */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator - * 0b0..The USB PLL is not currently locked - * 0b1..The USB PLL is currently locked +/*! PLL_LOCK - USB PLL Lock Status Indicator + * 0b0..Not locked + * 0b1..Locked */ #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) /*! @} */ -/*! @name PLL_SIC_SET - PLL SIC Register */ +/*! @name PLL_SIC_SET - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend */ +/*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable */ +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control */ +/*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable */ +/*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) @@ -92645,51 +86908,51 @@ typedef struct { #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control */ +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias */ +/*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator */ +/*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration */ +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator */ +/*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) /*! @} */ -/*! @name PLL_SIC_CLR - PLL SIC Register */ +/*! @name PLL_SIC_CLR - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend */ +/*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable */ +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control */ +/*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable */ +/*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) @@ -92699,51 +86962,51 @@ typedef struct { #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control */ +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias */ +/*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator */ +/*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration */ +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator */ +/*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) /*! @} */ -/*! @name PLL_SIC_TOG - PLL SIC Register */ +/*! @name PLL_SIC_TOG - PLL SIC */ /*! @{ */ #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) -/*! MISC2_CONTROL0 - Determines USB PLL operation status during Suspend */ +/*! MISC2_CONTROL0 - Miscellaneous Control */ #define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) -/*! PLL_EN_USB_CLKS - PLL multi-phase clock outputs enable */ +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) -/*! PLL_POWER - USB PLL powerup control */ +/*! PLL_POWER - USB PLL Powerup Control */ #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) -/*! PLL_ENABLE - PLL output clock enable */ +/*! PLL_ENABLE - PLL Output Clock Enable */ #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) @@ -92753,41 +87016,41 @@ typedef struct { #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - Reference bias power control */ +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) -/*! REFBIAS_PWD - Power down reference bias */ +/*! REFBIAS_PWD - Power Down Reference Bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) -/*! PLL_REG_ENABLE - Enable PLL regulator */ +/*! PLL_REG_ENABLE - Enable PLL Regulator */ #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - PLL divider value configuration */ +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - USB PLL lock status indicator */ +/*! PLL_LOCK - USB PLL Lock Status Indicator */ #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold +/*! VBUSVALID_THRESH - VBUS Comparator Threshold * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V - * 0b100..4.4 V (Default) + * 0b100..4.4 V * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V @@ -92796,1162 +87059,1162 @@ typedef struct { #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable + * 0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND + * 0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB subsystem - * 0b1..Use the VBUS_VALID_3V comparator results for signal reported to the USB subsystem +/*! VBUSVALID_SEL - VBUS_VALID Selection + * 0b0..VBUS_VALID comparator result + * 0b1..VBUS_VALID_3V comparator result */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB subsystem - * 0b01..Use the Session Valid comparator results for signal reported to the USB subsystem - * 0b10..Use the Session Valid comparator results for signal reported to the USB subsystem +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection + * 0b00..VBUS_VALID comparator result + * 0b01..Session valid comparator result + * 0b10..Session valid comparator result * 0b11.. */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override - * 0b0..Use PHY's ID pin detector or external override for ID status +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override + * 0b0..Use ID pin detector or external override * 0b1..Allow local override of ID pin detection status */ #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY - * 0b0..Determine the reported ID pin status results using the PHY's internal detector or local override - * 0b1..Determine the reported ID pin status results using the external ID signal value +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable + * 0b0..Internal detector or local override + * 0b1..External ID signal value */ #define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY - * 0b0..Determine the reported VBUS detection results using the PHY's internal comparators/detectors or local overrides - * 0b1..Determine the reported VBUS detection results using the external VBUS_VALID value +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable + * 0b0..Internal detector or local override + * 0b1..External VBUS_VALID value */ #define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session Valid detector for VBUS_VALID results. The Session Valid threshold is >= 0.8V and <= 4.0V. +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection + * 0b0..VBUS_VALID comparator + * 0b1..Session valid detector */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators - * 0bxx0..Power down the VBUS_VALID comparator +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable + * 0bxx0..Disable or power down the VBUS_VALID comparator * 0bxx1..Enable the VBUS_VALID comparator - * 0bx0x..Power down the Session Valid detector - * 0bx1x..Enable the Session Valid detector - * 0b0xx..Power down VBUS_VALID_3V detector + * 0bx0x..Disable or power down the session valid detector + * 0bx1x..Enable the session valid detector + * 0b0xx..Disable or power down the VBUS_VALID_3V detector * 0b1xx..Enable the VBUS_VALID_3V detector */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor - * 0b0..VBUS discharge resistor is disabled - * 0b1..VBUS discharge resistor is enabled +/*! DISCHARGE_VBUS - VBUS Discharge Resistor + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT_SET - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT_SET - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold */ +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override */ +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override */ +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY */ +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY */ +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID */ +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators */ +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */ +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold */ +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override */ +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override */ +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY */ +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY */ +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID */ +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators */ +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */ +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect Register */ +/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - VBUS comparator threshold */ +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) -/*! VBUS_OVERRIDE_EN - VBUS detect signal local override */ +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) -/*! SESSEND_OVERRIDE - Override value for SESSEND */ +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) -/*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) -/*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) -/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to the USB subsystem */ +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) -/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUSVALID_SEL - VBUS_VALID Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) -/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB subsystem */ +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) -/*! ID_OVERRIDE_EN - Enable local ID pin status override */ +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) -/*! ID_OVERRIDE - ID pin status local override value */ +/*! ID_OVERRIDE - ID Pin Status Local Override */ #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) -/*! EXT_ID_OVERRIDE_EN - Enable external ID pin status override using value supplied from outside the PHY */ +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) -/*! EXT_VBUS_OVERRIDE_EN - Enable external VBUS override using value supplied from outside the PHY */ +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U) -/*! VBUSVALID_TO_B - Selects the comparator used for VBUS_VALID */ +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -/*! VBUSVALID_PWRUP_CMPS - Individual enable controls for the VBUS detection comparators */ +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -/*! DISCHARGE_VBUS - Controls VBUS discharge resistor */ +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold +/*! SESSEND - Session End Indicator + * 0b0..Above threshold + * 0b1..Below threshold */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold +/*! BVALID - B-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold +/*! AVALID - A-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold +/*! VBUS_VALID - VBUS Voltage Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status - * 0b0..VBUS voltage is below the VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above the VBUS_VALID_3V threshold +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status + * 0b0..Below threshold + * 0b1..Above threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator */ +/*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status */ +/*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status */ +/*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status */ +/*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status */ +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator */ +/*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status */ +/*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status */ +/*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status */ +/*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status */ +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK) /*! @} */ -/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status Register */ +/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U) -/*! SESSEND - Session End indicator */ +/*! SESSEND - Session End Indicator */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U) -/*! BVALID - B-Device Session Valid status */ +/*! BVALID - B-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U) -/*! AVALID - A-Device Session Valid status */ +/*! AVALID - A-Device Session Valid Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - VBUS voltage status */ +/*! VBUS_VALID - VBUS Voltage Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - VBUS_VALID_3V detector status */ +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK) #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U) #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U) -/*! EXT_ID - OTG ID external override status */ +/*! EXT_ID - OTG ID External Override Status */ #define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) - * 0b0..Disables BC Secondary Detection function when controlled by this register - * 0b1..Enables BC Secondary Detection function when controlled by this register +/*! DETECT_SEC - Secondary Detection Function Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control - * 0b0..DP pullup resistor controlled only with UTMI bus signals - * 0b1..Force DP pullup resistor to be enabled +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - * 0b0..Disables CDP advertisement signaling VDM_SRC function when controlled by this register. - * 0b1..Enables CDP advertisement signaling VDM_SRC function when controlled by this register. +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) - * 0b0..Disables BC Data Contact Detect function when controlled by this register - * 0b1..Enables BC Data Contact Detect function when controlled by this register +/*! CHK_CONTACT - BC Data Contact Detect Function Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) - * 0b0..Enables BC Charger Detection function when controlled by this register - * 0b1..Disables BC Charger Detection function when controlled by this register +/*! CHK_CHRG_B - BC Charger Detection Function Enable + * 0b0..Enable + * 0b1..Disable */ #define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) - * 0b0..Enables BC v1.2 functions when controlled by this register - * 0b1..Disables BC v1.2 functions when controlled by this register +/*! EN_B - Selection of BC v1.2 Function Enable + * 0b0..Enable + * 0b1..Disable */ #define USBPHY_USB1_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits - * 0b0..Bit fields in USB1_CHRG_DETECT control BC 1.2 functionality - * 0b1..Bit fields and state machines in USBHSDCD module control BC 1.2 functionality +/*! DCDSEL - DCD Selection + * 0b0..Fields in USB1_CHRG_DETECT + * 0b1..Fields and state machines in the USBHSDCD module */ #define USBPHY_USB1_CHRG_DETECT_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT_SET - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT_SET - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) */ +/*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control */ +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - */ +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) */ +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) */ +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) */ +/*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits */ +/*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT_CLR - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT_CLR - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) */ +/*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control */ +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - */ +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) */ +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) */ +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) */ +/*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits */ +/*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DETECT_TOG - Charger Detect Register */ +/*! @name USB1_CHRG_DETECT_TOG - Charger Detect */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U) #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U) -/*! DETECT_SEC - Enables BC v1.2 Secondary Detection function for Charger Detect depending on other bit fields (active high) */ +/*! DETECT_SEC - Secondary Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) -/*! PULLUP_DP - DP pullup resistor enable override control */ +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U) #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U) -/*! VDM_SRC_ENABLE - Enables BC v1.2 Charging Downstream Port (CDP) advertisement signaling for - * Charger Detect depending on other bit fields (active high). - */ +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - Enables BC v1.2 Data Contact Detect function for Charger Detect depending on other bit fields (active high) */ +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - Enables BC v1.2 Primary Detection function for Charger Detect depending on other bit fields (active low) */ +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT (20U) -/*! EN_B - Enables selection of BC v1.2 functions depending on other bit fields (active low) */ +/*! EN_B - Selection of BC v1.2 Function Enable */ #define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK (0x80000000U) #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U) -/*! DCDSEL - Selects control source for Battery Charging Detection/Advertisement circuits */ +/*! DCDSEL - DCD Selection */ #define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output - * 0b0..No USB cable attachment has been detected - * 0b1..A USB cable attachment between the device and host has been detected +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output + * 0b0..Not detected + * 0b1..Detected */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output - * 0b0..Standard Downstream Port (SDP) has been detected - * 0b1..Charging Port has been detected +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output + * 0b0..SDP detected + * 0b1..Charging port detected */ #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage - * 0b0..USB_DM pin voltage is <= 0.8V - * 0b1..USB_DM pin voltage is >= 2.0V +/*! DM_STATE - DM Voltage + * 0b0..USB_DM pin voltage is <= 0.8 V + * 0b1..USB_DM pin voltage is >= 2.0 V */ #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage - * 0b0..USB_DP pin voltage is <= 0.8V - * 0b1..USB_DP pin voltage is >= 2.0V +/*! DP_STATE - DP Voltage + * 0b0..USB_DP pin voltage is <= 0.8 V + * 0b1..USB_DP pin voltage is >= 2.0 V */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output - * 0b0..Charging Downstream Port (CDP) has been detected - * 0b1..Downstream Charging Port (DCP) has been detected +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output + * 0b0..CDP detected + * 0b1..DCP detected */ #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output */ +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output */ +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage */ +/*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage */ +/*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output */ +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output */ +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output */ +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage */ +/*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage */ +/*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output */ +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK) /*! @} */ -/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status Register */ +/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output */ +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - Battery Charging Primary Detection phase output */ +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U) -/*! DM_STATE - DM voltage */ +/*! DM_STATE - DM Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U) -/*! DP_STATE - DP voltage */ +/*! DP_STATE - DP Voltage */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - Battery Charging Secondary Detection phase output */ +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ #define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK) /*! @} */ -/*! @name ANACTRL - Analog Control Register */ +/*! @name ANACTRL - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit - * 0b0..Disable the internal low voltage detector for the USB 3.3 V and 1.8 V domain - * 0b1..Enable the internal low voltage detector for the USB 3.3 V and 1.8 V domain +/*! LVI_EN - Internal Low Voltage Detector Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control - * 0b00..USB1PFDCLK is the same frequency as the USB PLL reference clock - * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4 - * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2 - * 0b11..USB1PFDCLK is the same as the pfd_clk frequency +/*! PFD_CLK_SEL - PFD Clock Selection + * 0b00..USB1PFDCLK = USB PLL reference clock + * 0b01..USB1PFDCLK = pfd_clk / 4 + * 0b10..USB1PFDCLK frequency = pfd_clk / 2 + * 0b11..USB1PFDCLK = pfd_clk */ #define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable - * 0b0..The 15 kohm nominal pulldowns on the USB_DP and USB_DM pins are disabled for Device mode - * 0b1..The 15 kohm nominal pulldowns on the USB_DP and USB_DM pins are enabled for Device mode +/*! DEV_PULLDOWN - Device Pulldown Enable + * 0b0..Disable + * 0b1..Enable */ #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name ANACTRL_SET - Analog Control Register */ +/*! @name ANACTRL_SET - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit */ +/*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control */ +/*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable */ +/*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name ANACTRL_CLR - Analog Control Register */ +/*! @name ANACTRL_CLR - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit */ +/*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control */ +/*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable */ +/*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name ANACTRL_TOG - Analog Control Register */ +/*! @name ANACTRL_TOG - Analog Control */ /*! @{ */ #define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) #define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) -/*! LVI_EN - LVI enable for USB 3.3 V monitor circuit */ +/*! LVI_EN - Internal Low Voltage Detector Enable */ #define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) -/*! PFD_CLK_SEL - PFD clock output mux control */ +/*! PFD_CLK_SEL - PFD Clock Selection */ #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - Device pulldown enable */ +/*! DEV_PULLDOWN - Device Pulldown Enable */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN - Trim Register */ +/*! @name TRIM_OVERRIDE_EN - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value - * 0b0..Use the TRIM_OVERRIDE_EN register values for the PLL divider value - * 0b1..Use the PLL_SIC register values for the PLL divider value +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value + * 0b0..TRIM_OVERRIDE_EN + * 0b1..PLL_SIC */ #define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim - * 0b0..Use the TRIM_OVERRIDE_EN register values for HS Tx output current trim - * 0b1..Use the Tx register values for HS Tx output current trim +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim - * 0b0..Use the TRIM_OVERRIDE_EN register values for DP resistance trim - * 0b1..Use the Tx register values for DP resistance trim +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim - * 0b0..Use the TRIM_OVERRIDE_EN register values for DM resistance trim - * 0b1..Use the Tx register values for DM resistance trim +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX */ #define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN_SET - Trim Register */ +/*! @name TRIM_OVERRIDE_EN_SET - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value */ +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim */ +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim */ +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim */ +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN_CLR - Trim Register */ +/*! @name TRIM_OVERRIDE_EN_CLR - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value */ +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim */ +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim */ +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim */ +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name TRIM_OVERRIDE_EN_TOG - Trim Register */ +/*! @name TRIM_OVERRIDE_EN_TOG - Trim */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U) -/*! DIV_SEL_OVERRIDE - Override enable for PLL divider value */ +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U) -/*! TX_D_CAL_OVERRIDE - Override enable for HS Tx output current trim */ +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U) -/*! TX_CAL45DP_OVERRIDE - Override enable for USB_DP series termination trim */ +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U) -/*! TX_CAL45DM_OVERRIDE - Override enable for USB_DM series termination trim */ +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U) -/*! PLL_CTRL0_DIV_SEL - PLL divider value configuration bits from outside USBPHY */ +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U) -/*! USBPHY_TX_D_CAL - HS Tx output current trim bits from outside USBPHY */ +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U) -/*! USBPHY_TX_CAL45DP - DP series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U) -/*! USBPHY_TX_CAL45DN - DM series termination resistance trim bits from outside USBPHY. */ +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK) /*! @} */ -/*! @name PFDA - PFD Register A */ +/*! @name PFDA - PFD A */ /*! @{ */ #define USBPHY_PFDA_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate - * 0b0..PFD0 clock output is enabled - * 0b1..PFD0 clock output is gated (Default) +/*! PFD0_CLKGATE - PFD0 Clock Gate + * 0b0..Enable + * 0b1..Disable */ #define USBPHY_PFDA_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK) #define USBPHY_PFDA_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal + * 0b0..Not stable + * 0b1..Stable + */ #define USBPHY_PFDA_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK) /*! @} */ -/*! @name PFDA_SET - PFD Register A */ +/*! @name PFDA_SET - PFD A */ /*! @{ */ #define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate */ +/*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_SET_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK) #define USBPHY_PFDA_SET_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK) /*! @} */ -/*! @name PFDA_CLR - PFD Register A */ +/*! @name PFDA_CLR - PFD A */ /*! @{ */ #define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate */ +/*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_CLR_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK) #define USBPHY_PFDA_CLR_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK) /*! @} */ -/*! @name PFDA_TOG - PFD Register A */ +/*! @name PFDA_TOG - PFD A */ /*! @{ */ #define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK (0x1U) #define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT (0U) -/*! PFD0_CLKGATE - PFD0 clock gate */ +/*! PFD0_CLKGATE - PFD0 Clock Gate */ #define USBPHY_PFDA_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK) #define USBPHY_PFDA_TOG_PFD0_FRAC_MASK (0x7EU) #define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT (1U) -/*! PFD0_FRAC - PFD0 fractional divider setting used to select the pfd_clk output frequency */ +/*! PFD0_FRAC - PFD0 Fractional Divider */ #define USBPHY_PFDA_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK) #define USBPHY_PFDA_TOG_PFD0_STABLE_MASK (0x80U) #define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT (7U) -/*! PFD0_STABLE - PFD0 stable signal from the Phase Fractional Divider */ +/*! PFD0_STABLE - PFD0 Stable Signal */ #define USBPHY_PFDA_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK) /*! @} */ @@ -94367,14 +88630,14 @@ typedef struct { #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level - * 0b00000111..Data 7 line signal level - * 0b00000110..Data 6 line signal level - * 0b00000101..Data 5 line signal level - * 0b00000100..Data 4 line signal level - * 0b00000011..Data 3 line signal level - * 0b00000010..Data 2 line signal level - * 0b00000001..Data 1 line signal level - * 0b00000000..Data 0 line signal level + * 0b10000000..Data 7 line signal level + * 0b01000000..Data 6 line signal level + * 0b00100000..Data 5 line signal level + * 0b00010000..Data 4 line signal level + * 0b00001000..Data 3 line signal level + * 0b00000100..Data 2 line signal level + * 0b00000010..Data 1 line signal level + * 0b00000001..Data 0 line signal level */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ @@ -94520,8 +88783,8 @@ typedef struct { #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value - * 0b1110..SDCLK x 2 30 recommend to use for SDR104 mode - * 0b1101..SDCLK x 2 29 recommend to use for other speed mode except SDR104 mode + * 0b1110..SDCLK x 2 30, recommend to use for SDR104 mode + * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except SDR104 mode * 0b0011..SDCLK x 2 19 * 0b0010..SDCLK x 2 18 * 0b0001..SDCLK x 2 33 @@ -94529,6 +88792,11 @@ typedef struct { */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) +#define USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) +/*! RST_FIFO - Reset the async FIFO */ +#define USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK) + #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ @@ -95714,15 +89982,15 @@ typedef struct { */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) -/*! TUNING_8bit_EN - Tuning 8bit enable */ -#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) - -#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) -#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) -/*! TUNING_1bit_EN - Tuning 1bit enable */ -#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) +/*! TUNING_BIT_EN - Tuning bit enable + * 0b00..Enable Tuning circuit for DATA[3:0] + * 0b01..Enable Tuning circuit for DATA[7:0] + * 0b10..Enable Tuning circuit for DATA[0] + * 0b11..Invalid + */ +#define USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) @@ -95739,6 +90007,14 @@ typedef struct { * 0b0..Disable */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) +#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) +/*! EN_32K_CLK - Select the clock source for host card detection. + * 0b0..Use the peripheral clock (ipg_clk) for card detection. + * 0b1..Use the low power clock (ipg_clk_lp) for card detection. + */ +#define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ @@ -96254,6 +90530,14 @@ typedef struct { */ #define VBAT_STATUSA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK) +#define VBAT_STATUSA_LIGHT_DET_MASK (0x400U) +#define VBAT_STATUSA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Light error not detected + * 0b1..Light error detected + */ +#define VBAT_STATUSA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK) + #define VBAT_STATUSA_SEC0_DET_MASK (0x1000U) #define VBAT_STATUSA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96387,6 +90671,14 @@ typedef struct { */ #define VBAT_IRQENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK) +#define VBAT_IRQENA_LIGHT_DET_MASK (0x400U) +#define VBAT_IRQENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK) + #define VBAT_IRQENA_SEC0_DET_MASK (0x1000U) #define VBAT_IRQENA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96520,6 +90812,14 @@ typedef struct { */ #define VBAT_WAKENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK) +#define VBAT_WAKENA_LIGHT_DET_MASK (0x400U) +#define VBAT_WAKENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK) + #define VBAT_WAKENA_SEC0_DET_MASK (0x1000U) #define VBAT_WAKENA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96613,6 +90913,14 @@ typedef struct { */ #define VBAT_TAMPERA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK) +#define VBAT_TAMPERA_LIGHT_DET_MASK (0x400U) +#define VBAT_TAMPERA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK) + #define VBAT_TAMPERA_SEC0_DET_MASK (0x1000U) #define VBAT_TAMPERA_SEC0_DET_SHIFT (12U) /*! SEC0_DET - Input 0 Detect @@ -96688,21 +90996,15 @@ typedef struct { #define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK (0xCU) #define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT (2U) -/*! COARSE_AMP_GAIN - Amplifier Gain Coarse Adjustment - * 0b00..0.5 uA/V - * 0b01..1.0 uA/V - * 0b10..1.8 uA/V - * 0b11..3.3 uA/V +/*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external + * crystal ESR values See the device datasheet for the ranges supported by this device + * 0b00..ESR Range 0 + * 0b01..ESR Range 1 + * 0b10..ESR Range 2 + * 0b11..ESR Range 3 */ #define VBAT_OSCCTLA_COARSE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) -#define VBAT_OSCCTLA_FINE_AMP_GAIN_MASK (0x30U) -#define VBAT_OSCCTLA_FINE_AMP_GAIN_SHIFT (4U) -/*! FINE_AMP_GAIN - Amplifier Gain Fine Adjustment - * 0b00..200 mV - */ -#define VBAT_OSCCTLA_FINE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_FINE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_FINE_AMP_GAIN_MASK) - #define VBAT_OSCCTLA_CAP_SEL_EN_MASK (0x80U) #define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT (7U) /*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable @@ -96758,15 +91060,18 @@ typedef struct { #define VBAT_OSCCTLA_MODE_EN_MASK (0x30000U) #define VBAT_OSCCTLA_MODE_EN_SHIFT (16U) /*! MODE_EN - Mode Enable - * 0b00..Transconductance Oscillator mode - * 0b01..Low-Power Backup mode - * 0b10..Low-Power Switched mode + * 0b00..Normal mode + * 0b01..Startup mode + * 0b11..Low power mode */ #define VBAT_OSCCTLA_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK) #define VBAT_OSCCTLA_SUPPLY_DET_MASK (0xC0000U) #define VBAT_OSCCTLA_SUPPLY_DET_SHIFT (18U) -/*! SUPPLY_DET - Supply Detector Trim */ +/*! SUPPLY_DET - Supply Detector Trim + * 0b00..VBAT supply is less than 3V + * 0b01..VBAT supply is greater than 3V + */ #define VBAT_OSCCTLA_SUPPLY_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK) /*! @} */ @@ -96782,19 +91087,43 @@ typedef struct { /*! @name OSCCFGA - Oscillator Configuration A */ /*! @{ */ -#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x7U) +#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x3U) #define VBAT_OSCCFGA_CMP_TRIM_SHIFT (0U) -/*! CMP_TRIM - Comparator Trim */ +/*! CMP_TRIM - Comparator Trim + * 0b00..760 mV + * 0b01..770 mV + * 0b11..740 mV + */ #define VBAT_OSCCFGA_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK) +#define VBAT_OSCCFGA_CAP2_TRIM_MASK (0x4U) +#define VBAT_OSCCFGA_CAP2_TRIM_SHIFT (2U) +/*! CAP2_TRIM - CAP2_TRIM */ +#define VBAT_OSCCFGA_CAP2_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK) + #define VBAT_OSCCFGA_DLY_TRIM_MASK (0x78U) #define VBAT_OSCCFGA_DLY_TRIM_SHIFT (3U) -/*! DLY_TRIM - Delay Trim */ +/*! DLY_TRIM - Delay Trim + * 0b0000..P current 9(nA) and N Current 6(nA) + * 0b0001..P current 13(nA) and N Current 6(nA) + * 0b0011..P current 4(nA) and N Current 6(nA) + * 0b0100..P current 9(nA) and N Current 4(nA) + * 0b0101..P current 13(nA) and N Current 4(nA) + * 0b0111..P current 4(nA) and N Current 4(nA) + * 0b1000..P current 9(nA) and N Current 2(nA) + * 0b1001..P current 13(nA) and N Current 2(nA) + * 0b1011..P current 4(nA) and N Current 2(nA) + */ #define VBAT_OSCCFGA_DLY_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK) #define VBAT_OSCCFGA_CAP_TRIM_MASK (0x180U) #define VBAT_OSCCFGA_CAP_TRIM_SHIFT (7U) -/*! CAP_TRIM - Capacitor Trim */ +/*! CAP_TRIM - Capacitor Trim + * 0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ) + * 0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01) + * 0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10) + * 0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11) + */ #define VBAT_OSCCFGA_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK) #define VBAT_OSCCFGA_INIT_TRIM_MASK (0xE00U) @@ -96930,8 +91259,8 @@ typedef struct { #define VBAT_LDOCTLA_REFRESH_EN_MASK (0x4U) #define VBAT_LDOCTLA_REFRESH_EN_SHIFT (2U) /*! REFRESH_EN - Refresh Enable - * 0b0..Disable - * 0b1..Enable + * 0b0..Refresh mode is disabled + * 0b1..Refresh mode is enabled for low power operation */ #define VBAT_LDOCTLA_REFRESH_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK) /*! @} */ @@ -96988,13 +91317,37 @@ typedef struct { */ #define VBAT_LDORAMC_SWI(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK) -#define VBAT_LDORAMC_RET_MASK (0xF00U) -#define VBAT_LDORAMC_RET_SHIFT (8U) -/*! RET - Retention - * 0b0000..Retained - * 0b0001..Not retained +#define VBAT_LDORAMC_RET0_MASK (0x100U) +#define VBAT_LDORAMC_RET0_SHIFT (8U) +/*! RET0 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes */ -#define VBAT_LDORAMC_RET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK) +#define VBAT_LDORAMC_RET0(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK) + +#define VBAT_LDORAMC_RET1_MASK (0x200U) +#define VBAT_LDORAMC_RET1_SHIFT (9U) +/*! RET1 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET1(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK) + +#define VBAT_LDORAMC_RET2_MASK (0x400U) +#define VBAT_LDORAMC_RET2_SHIFT (10U) +/*! RET2 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET2(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK) + +#define VBAT_LDORAMC_RET3_MASK (0x800U) +#define VBAT_LDORAMC_RET3_SHIFT (11U) +/*! RET3 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET3(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK) /*! @} */ /*! @name LDOTIMER0 - Bandgap Timer 0 */ @@ -97139,6 +91492,14 @@ typedef struct { * 0b1..Temperature detect is enabled */ #define VBAT_TAMCTLA_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK) + +#define VBAT_TAMCTLA_LIGHT_EN_MASK (0x4U) +#define VBAT_TAMCTLA_LIGHT_EN_SHIFT (2U) +/*! LIGHT_EN - Light Detect Enable + * 0b0..Light detect is disabled + * 0b1..Light detect is enabled + */ +#define VBAT_TAMCTLA_LIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK) /*! @} */ /*! @name TAMCTLB - TAMPER Control B */ @@ -97327,9 +91688,9 @@ typedef struct { /** VREF - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ - uint32_t PARAM; /**< Parameters, offset: 0x4 */ - __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ uint8_t RESERVED_0[4]; + __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ + uint8_t RESERVED_1[4]; __IO uint32_t UTRIM; /**< User Trim, offset: 0x10 */ } VREF_Type; @@ -97412,39 +91773,6 @@ typedef struct { */ #define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) -#define VREF_CSR_REFCHSELN_EN_MASK (0x40U) -#define VREF_CSR_REFCHSELN_EN_SHIFT (6U) -/*! REFCHSELN_EN - Reference Channel Select Negative Enable - * 0b0..Disables - * 0b1..Enables - */ -#define VREF_CSR_REFCHSELN_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELN_EN_SHIFT)) & VREF_CSR_REFCHSELN_EN_MASK) - -#define VREF_CSR_REFCHSELP_EN_MASK (0x80U) -#define VREF_CSR_REFCHSELP_EN_SHIFT (7U) -/*! REFCHSELP_EN - Reference Channel Select Positive Enable - * 0b0..Disables - * 0b1..Enables - */ -#define VREF_CSR_REFCHSELP_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELP_EN_SHIFT)) & VREF_CSR_REFCHSELP_EN_MASK) - -#define VREF_CSR_VRSEL_MASK (0x300U) -#define VREF_CSR_VRSEL_SHIFT (8U) -/*! VRSEL - Voltage Reference Selection - * 0b00..Internal bandgap - * 0b01..Low-power buffered 1v - * 0b10..Buffer 2.1v output - */ -#define VREF_CSR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VRSEL_SHIFT)) & VREF_CSR_VRSEL_MASK) - -#define VREF_CSR_REFL_GRD_SEL_MASK (0x400U) -#define VREF_CSR_REFL_GRD_SEL_SHIFT (10U) -/*! REFL_GRD_SEL - Ground Select - * 0b0..vrefl_3v - * 0b1..VSSA - */ -#define VREF_CSR_REFL_GRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFL_GRD_SEL_SHIFT)) & VREF_CSR_REFL_GRD_SEL_MASK) - #define VREF_CSR_HI_PWR_LV_MASK (0x800U) #define VREF_CSR_HI_PWR_LV_SHIFT (11U) /*! HI_PWR_LV - High-Power Level @@ -97475,7 +91803,7 @@ typedef struct { #define VREF_UTRIM_TRIM2V1_MASK (0xFU) #define VREF_UTRIM_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1V Trim */ +/*! TRIM2V1 - VREF 2.1 V Trim */ #define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) #define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) @@ -97574,6 +91902,7 @@ typedef struct { * 0b0000000000000000..Standard features implemented * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for * external pin/filter detection during all power modes enabled. + * *.. */ #define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) @@ -97921,21 +92250,21 @@ typedef struct { #define WUU_PE2_WUPE30_MASK (0x30000000U) #define WUU_PE2_WUPE30_SHIFT (28U) -/*! WUPE30 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported - * 0b11..Not supported +/*! WUPE30 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK) #define WUU_PE2_WUPE31_MASK (0xC0000000U) #define WUU_PE2_WUPE31_SHIFT (30U) -/*! WUPE31 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported - * 0b11..Not supported +/*! WUPE31 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) */ #define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK) /*! @} */ @@ -97945,81 +92274,81 @@ typedef struct { #define WUU_ME_WUME0_MASK (0x1U) #define WUU_ME_WUME0_SHIFT (0U) -/*! WUME0 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) #define WUU_ME_WUME1_MASK (0x2U) #define WUU_ME_WUME1_SHIFT (1U) -/*! WUME1 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) #define WUU_ME_WUME2_MASK (0x4U) #define WUU_ME_WUME2_SHIFT (2U) -/*! WUME2 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) #define WUU_ME_WUME3_MASK (0x8U) #define WUU_ME_WUME3_SHIFT (3U) -/*! WUME3 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME3 - Module Interrupt Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) #define WUU_ME_WUME4_MASK (0x10U) #define WUU_ME_WUME4_SHIFT (4U) -/*! WUME4 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME4 - Module Interrupt Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK) #define WUU_ME_WUME5_MASK (0x20U) #define WUU_ME_WUME5_SHIFT (5U) -/*! WUME5 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME5 - Module Interrupt Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK) #define WUU_ME_WUME6_MASK (0x40U) #define WUU_ME_WUME6_SHIFT (6U) -/*! WUME6 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) #define WUU_ME_WUME7_MASK (0x80U) #define WUU_ME_WUME7_SHIFT (7U) -/*! WUME7 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME7 - Module Interrupt Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK) #define WUU_ME_WUME8_MASK (0x100U) #define WUU_ME_WUME8_SHIFT (8U) -/*! WUME8 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) #define WUU_ME_WUME9_MASK (0x200U) #define WUU_ME_WUME9_SHIFT (9U) -/*! WUME9 - Module Interrupt Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUME9 - Module Interrupt Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable */ #define WUU_ME_WUME9(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK) /*! @} */ @@ -98029,81 +92358,81 @@ typedef struct { #define WUU_DE_WUDE0_MASK (0x1U) #define WUU_DE_WUDE0_SHIFT (0U) -/*! WUDE0 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK) #define WUU_DE_WUDE1_MASK (0x2U) #define WUU_DE_WUDE1_SHIFT (1U) -/*! WUDE1 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK) #define WUU_DE_WUDE2_MASK (0x4U) #define WUU_DE_WUDE2_SHIFT (2U) -/*! WUDE2 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK) #define WUU_DE_WUDE3_MASK (0x8U) #define WUU_DE_WUDE3_SHIFT (3U) -/*! WUDE3 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK) #define WUU_DE_WUDE4_MASK (0x10U) #define WUU_DE_WUDE4_SHIFT (4U) -/*! WUDE4 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) #define WUU_DE_WUDE5_MASK (0x20U) #define WUU_DE_WUDE5_SHIFT (5U) -/*! WUDE5 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK) #define WUU_DE_WUDE6_MASK (0x40U) #define WUU_DE_WUDE6_SHIFT (6U) -/*! WUDE6 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) #define WUU_DE_WUDE7_MASK (0x80U) #define WUU_DE_WUDE7_SHIFT (7U) -/*! WUDE7 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK) #define WUU_DE_WUDE8_MASK (0x100U) #define WUU_DE_WUDE8_SHIFT (8U) -/*! WUDE8 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) #define WUU_DE_WUDE9_MASK (0x200U) #define WUU_DE_WUDE9_SHIFT (9U) -/*! WUDE9 - DMA/Trigger Wake-up Enable for Module n - * 0b0..Disables - * 0b1..Enables +/*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable */ #define WUU_DE_WUDE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK) /*! @} */ @@ -98353,17 +92682,17 @@ typedef struct { #define WUU_PF_WUF30_MASK (0x40000000U) #define WUU_PF_WUF30_SHIFT (30U) -/*! WUF30 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUF30 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes */ #define WUU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK) #define WUU_PF_WUF31_MASK (0x80000000U) #define WUU_PF_WUF31_SHIFT (31U) -/*! WUF31 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUF31 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes */ #define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK) /*! @} */ @@ -98727,20 +93056,20 @@ typedef struct { #define WUU_PDC2_WUPDC30_MASK (0x30000000U) #define WUU_PDC2_WUPDC30_SHIFT (28U) -/*! WUPDC30 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported +/*! WUPDC30 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK) #define WUU_PDC2_WUPDC31_MASK (0xC0000000U) #define WUU_PDC2_WUPDC31_SHIFT (30U) -/*! WUPDC31 - Reserved - * 0b00..Not supported - * 0b01..Not supported - * 0b10..Not supported +/*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event * 0b11..Reserved */ #define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK) @@ -99045,17 +93374,19 @@ typedef struct { #define WUU_PMC_WUPMC30_MASK (0x40000000U) #define WUU_PMC_WUPMC30_SHIFT (30U) -/*! WUPMC30 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUPMC30 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK) #define WUU_PMC_WUPMC31_MASK (0x80000000U) #define WUU_PMC_WUPMC31_SHIFT (31U) -/*! WUPMC31 - Reserved - * 0b0..Not supported - * 0b1..Not supported +/*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). */ #define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK) /*! @} */ @@ -99377,8 +93708,30 @@ typedef struct { * @{ */ -/** High Speed SPI (Flexcomm 8) interrupt name */ -#define LSPI_HS_IRQn FLEXCOMM8_IRQn +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_MINOR_REVISION_MASK; + + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} /*! @@ -99386,5 +93739,5 @@ typedef struct { */ /* end of group SDK_Compatibility_Symbols */ -#endif /* _MCXN947_CM33_CORE1_H_ */ +#endif /* MCXN947_CM33_CORE1_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h index b64d71bb2c..eac6672de6 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h @@ -1,15 +1,13 @@ /* ** ################################################################### ** Version: rev. 1.0, 2021-08-03 -** Build: b230131 +** Build: b240410 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2023 NXP -** All rights reserved. -** +** Copyright 2016-2024 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -31,22 +29,20 @@ #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1) /* @brief CACHE64_POLSEL availability on the SoC. */ #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) /* @brief CMC availability on the SoC. */ #define FSL_FEATURE_SOC_CMC_COUNT (1) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief CTIMER availability on the SoC. */ #define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief CDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CDOG_COUNT (2) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (2) /* @brief EIM availability on the SoC. */ #define FSL_FEATURE_SOC_EIM_COUNT (1) /* @brief EMVSIM availability on the SoC. */ #define FSL_FEATURE_SOC_EMVSIM_COUNT (2) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (2) /* @brief EVTG availability on the SoC. */ #define FSL_FEATURE_SOC_EVTG_COUNT (1) /* @brief EWM availability on the SoC. */ @@ -65,12 +61,16 @@ #define FSL_FEATURE_SOC_GPIO_COUNT (12) /* @brief SPC availability on the SoC. */ #define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief HPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_HPDAC_COUNT (1) /* @brief I3C availability on the SoC. */ #define FSL_FEATURE_SOC_I3C_COUNT (2) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (2) /* @brief INPUTMUX availability on the SoC. */ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) /* @brief LPADC availability on the SoC. */ #define FSL_FEATURE_SOC_LPADC_COUNT (2) /* @brief LPCMP availability on the SoC. */ @@ -101,6 +101,8 @@ #define FSL_FEATURE_SOC_PDM_COUNT (1) /* @brief PINT availability on the SoC. */ #define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) /* @brief POWERQUAD availability on the SoC. */ #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) /* @brief PORT availability on the SoC. */ @@ -109,20 +111,24 @@ #define FSL_FEATURE_SOC_PWM_COUNT (2) /* @brief PUF availability on the SoC. */ #define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) /* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (2) +#define FSL_FEATURE_SOC_RTC_COUNT (1) /* @brief SCG availability on the SoC. */ #define FSL_FEATURE_SOC_SCG_COUNT (1) /* @brief SCT availability on the SoC. */ #define FSL_FEATURE_SOC_SCT_COUNT (1) /* @brief SEMA42 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA42_COUNT (1) +/* @brief SINC availability on the SoC. */ +#define FSL_FEATURE_SOC_SINC_COUNT (1) /* @brief SMARTDMA availability on the SoC. */ #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) /* @brief SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (2) /* @brief TSI availability on the SoC. */ #define FSL_FEATURE_SOC_TSI_COUNT (1) /* @brief USB availability on the SoC. */ @@ -178,6 +184,8 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) /* @brief Has Trigger status register. */ #define FSL_FEATURE_LPADC_HAS_TSTAT (1) /* @brief Has power select (bitfield CFG[PWRSEL]). */ @@ -192,6 +200,28 @@ #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) /* @brief Conversion averaged bitfiled width. */ #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) /* @brief Temperature sensor parameter A (slope). */ #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) /* @brief Temperature sensor parameter B (offset). */ @@ -212,6 +242,8 @@ /* FLEXCAN module features */ +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ @@ -232,18 +264,13 @@ #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) -/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a - * specific moment during the arbitration process). */ +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) -/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be - * transmitted in a specific moment during the arbitration process). */ +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) -/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus - * when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle - * state). */ +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) -/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode - * are entered during a Bus-Off state). */ +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) @@ -263,6 +290,8 @@ #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) /* CDOG module features */ @@ -271,10 +300,31 @@ /* CMC module features */ +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) /* @brief Has RSTCNT register */ -#define FSL_FEATURE_CMC_HAS_RSTCNT_REGISTER (1) -/* @brief Does not have SRAMCTL register */ -#define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1) +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1) /* SYSPM module features */ @@ -282,6 +332,8 @@ #define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) /* @brief Temperature sensor parameter B (offset). */ #define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) /* CTIMER module features */ @@ -295,6 +347,8 @@ #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) /* LPDAC module features */ @@ -310,59 +364,87 @@ #define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) /* @brief Has internal reference current options. */ #define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) +/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */ +#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1) /* EDMA module features */ -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid - * only for eDMA modules.) */ +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) /* @brief Has DMA_Error interrupt vector. */ #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) -/* @brief Has register access permission. */ -#define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) /* @brief If channel clock controlled independently */ #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) -/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference - * instance) */ +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) /* @brief Has no register bit fields MP_CSR[EBW]. */ #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) -/* @brief If dma has channel mux */ -#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) /* @brief If dma has common clock gate */ #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) /* @brief If dma channel IRQ support parameter */ #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) /* @brief Has no register bit fields CH_SBR[ATTR]. */ #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) -/* @brief If 8 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) -/* @brief If 16 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) -/* @brief If 64 bytes transfer supported. */ -#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) - -/* DMA_TCD module features */ - -/* @brief Has no supervisor access bit (CR). */ -#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_SUP (1) -/* @brief Has no oscillator enable bit (CR). */ -#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_OSCE (1) - -/* ENC module features */ - -/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ -#define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0) -/* @brief Has register CTRL3. */ -#define FSL_FEATURE_ENC_HAS_CTRL3 (1) -/* @brief Has register LASTEDGE or LASTEDGEH. */ -#define FSL_FEATURE_ENC_HAS_LASTEDGE (1) -/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ -#define FSL_FEATURE_ENC_HAS_POSDPER (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) /* EVTG module features */ @@ -375,6 +457,8 @@ #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ @@ -391,6 +475,8 @@ #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) /* @brief Reset value of the FLEXIO_PARAM register */ #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) /* FLEXSPI module features */ @@ -404,6 +490,8 @@ #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) /* @brief FlexSPI DMA needs multiple DES to transfer */ #define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) /* GPIO module features */ @@ -421,7 +509,7 @@ /* I3C module features */ /* @brief Has TERM bitfile in MERRWARN register. */ -#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1) /* @brief SOC has no reset driver. */ #define FSL_FEATURE_I3C_HAS_NO_RESET (0) /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ @@ -429,6 +517,13 @@ /* @brief Register SCONFIG do not have IDRAND bitfield. */ #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0) +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + /* INTM module features */ /* @brief Up to 4 programmable interrupt monitors */ @@ -449,6 +544,10 @@ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) /* @brief Has CCR1 (related to existence of registers CCR1). */ #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) /* LPTMR module features */ @@ -458,15 +557,20 @@ #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) /* @brief Do not has prescaler clock source 1. */ #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) /* LPUART module features */ /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the - * registers are 32-bit wide). */ +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) @@ -486,8 +590,7 @@ #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) /* @brief Baud rate fine adjustment is available. */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], - * BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) @@ -499,13 +602,11 @@ #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are - * 32-bit wide). */ +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit - * wide). */ +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) @@ -552,7 +653,7 @@ /* MRT module features */ /* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) /* OPAMP module features */ @@ -569,7 +670,7 @@ /* @brief Opamp has OPAMP_CTR TRIGMD bit */ #define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) /* @brief OPAMP support reference buffer */ -#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1) /* PDM module features */ @@ -580,7 +681,7 @@ /* @brief PDM FIFO WIDTH Size */ #define FSL_FEATURE_PDM_FIFO_WIDTH (4) /* @brief PDM FIFO DEPTH Size */ -#define FSL_FEATURE_PDM_FIFO_DEPTH (8) +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) /* @brief PDM has RANGE_CTRL register */ #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) /* @brief PDM Has Low Frequency */ @@ -591,6 +692,10 @@ #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) /* @brief PDM Has DC_OUT_CTRL */ #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) /* @brief PDM Has Fixed DC CTRL VALUE. */ @@ -642,6 +747,8 @@ #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ #define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Defines width of PCR[MUX] field. */ @@ -661,6 +768,13 @@ /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + /* PWM module features */ /* @brief If (e)FlexPWM has module A channels (outputs). */ @@ -674,11 +788,34 @@ /* @brief If (e)FlexPWM has mux trigger source select bit field. */ #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) /* @brief Number of submodules in each (e)FlexPWM module. */ -#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) /* @brief Number of fault channel in each (e)FlexPWM module. */ #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ #define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) /* RTC module features */ @@ -696,7 +833,7 @@ #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) /* @brief Has CLKO_DIS bitfile in CTRL register. */ #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) -/* @brief Has Tamper in RTC. */ +/* @brief Has No Tamper in RTC. */ #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) @@ -711,31 +848,26 @@ /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ #define FSL_FEATURE_SAI_HAS_FIFO (1) -/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], - * RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) -/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], - * RMR[RWM]). */ +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) -/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], - * TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) -/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], - * RCR4[FPACK]). */ +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) -/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields - * TCR4[FCONT], RCR4[FCONT]). */ +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) -/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning - * flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) -/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], - * RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) /* @brief Has bit field MICS of the MCR register. */ @@ -748,6 +880,8 @@ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) /* SCT module features */ @@ -765,20 +899,45 @@ /* @brief Gate counts */ #define FSL_FEATURE_SEMA42_GATE_COUNT (16) +/* SINC module features */ + +/* @brief SINC channel count. */ +#define FSL_FEATURE_SINC_CHANNEL_COUNT (5) +/* @brief SINC CACFR register has bitfield ADMASEL. */ +#define FSL_FEATURE_SINC_CACFR_HAS_ADMASEL (1) +/* @brief SINC CACFR register has no bitfield PTMUX. */ +#define FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX (1) + /* SPC module features */ -/* @brief Has 2P4G power domain. */ -#define FSL_FEATURE_SPC_HAS_2P4G_POWER_DOMAIN (1) -/* @brief Has SPC_CFG. */ -#define FSL_FEATURE_SPC_HAS_CFG_REGISTER (0) -/* @brief Has core ldo vdd driver strength (register bit ACTIVE_CFG[CORELDO_VDD_DS]). */ +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ #define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) -/* @brief Has bias enable (register bit LP_CFG[WBIAS_EN]). */ -#define FSL_FEATURE_SPC_HAS_WBIAS_EN (0) -/* @brief Set CORELDO_VDD_LVL to 0 then regulate to Under Drive Voltage (0.95v). */ -#define FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE (0) -/* @brief Set DCDC_VDD_LVL to 0 then regulate to Low Under Voltage (1.25v). */ -#define FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE (0) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) /* SYSCON module features */ @@ -795,28 +954,24 @@ /* @brief Powerlib API is different with other series devices.. */ #define FSL_FEATURE_POWERLIB_EXTEND (1) -/* TRNG module features */ +/* TRDC module features */ -/* @brief TRNG does not support SCR4L. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1) -/* @brief TRNG does not support SCR5L. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1) -/* @brief TRNG does not support SCR6L. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1) -/* @brief TRNG does not support PKRMAX. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1) -/* @brief TRNG does not support SAMP mode. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1) -/* @brief TRNG does not support ACC. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) -/* @brief TRNG does not support SBLIM. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1) -/* @brief TRNG supports reset control. */ -#define FSL_FEATURE_TRNG_HAS_RSTCTL (1) -/* @brief TRNG does not support FOR_CLK mode. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1) -/* @brief TRNG has two oscillators. */ -#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1) +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) /* TSI module features */ @@ -894,12 +1049,33 @@ #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) /* @brief Has no VSELECT bit in VEND_SPEC register */ #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) /* UTICK module features */ /* @brief UTICK does not support PD configure. */ #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + /* WWDT module features */ /* @brief Has no RESET register. */ @@ -908,3 +1084,4 @@ #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) #endif /* _MCXN947_cm33_core1_FEATURES_H_ */ + diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S index 07c66afdb8..eabf39e38c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S @@ -2,15 +2,13 @@ /* @file: startup_MCXN947_cm33_core0.s */ /* @purpose: CMSIS Cortex-M33 Core Device Startup File */ /* MCXN947_cm33_core0 */ -/* @version: 1.0 */ -/* @date: 2022-10-1 */ -/* @build: b230131 */ +/* @version: 2.0 */ +/* @date: 2023-2-1 */ +/* @build: b240410 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2023 NXP */ -/* All rights reserved. */ -/* */ +/* Copyright 2016-2024 NXP */ /* SPDX-License-Identifier: BSD-3-Clause */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ @@ -165,14 +163,14 @@ __Vectors: .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ - .long ENC0_COMPARE_IRQHandler /* ENC0_Compare interrupt*/ - .long ENC0_HOME_IRQHandler /* ENC0_Home interrupt*/ - .long ENC0_WDG_SAB_IRQHandler /* ENC0_WDG_IRQ/SAB interrupt*/ - .long ENC0_IDX_IRQHandler /* ENC0_IDX interrupt*/ - .long ENC1_COMPARE_IRQHandler /* ENC1_Compare interrupt*/ - .long ENC1_HOME_IRQHandler /* ENC1_Home interrupt*/ - .long ENC1_WDG_SAB_IRQHandler /* ENC1_WDG_IRQ/SAB interrupt*/ - .long ENC1_IDX_IRQHandler /* ENC1_IDX interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ .long BSP32_IRQHandler /* CoolFlux BSP32 interrupt*/ .long ELS_ERR_IRQHandler /* ELS error interrupt*/ @@ -191,8 +189,8 @@ __Vectors: .long WUU_IRQHandler /* Wake Up Unit interrupt*/ .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ .long ETB0_IRQHandler /* ETB counter expires interrupt*/ - .long SM3_IRQHandler /* Secure Generic Interface (SGI) SAFO interrupt */ - .long TRNG0_IRQHandler /* True Random Number Generator interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ @@ -1399,75 +1397,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler: .align 1 .thumb_func - .weak ENC0_COMPARE_IRQHandler - .type ENC0_COMPARE_IRQHandler, %function -ENC0_COMPARE_IRQHandler: - ldr r0,=ENC0_COMPARE_DriverIRQHandler + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler bx r0 - .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC0_HOME_IRQHandler - .type ENC0_HOME_IRQHandler, %function -ENC0_HOME_IRQHandler: - ldr r0,=ENC0_HOME_DriverIRQHandler + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler bx r0 - .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler .align 1 .thumb_func - .weak ENC0_WDG_SAB_IRQHandler - .type ENC0_WDG_SAB_IRQHandler, %function -ENC0_WDG_SAB_IRQHandler: - ldr r0,=ENC0_WDG_SAB_DriverIRQHandler + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler bx r0 - .size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC0_IDX_IRQHandler - .type ENC0_IDX_IRQHandler, %function -ENC0_IDX_IRQHandler: - ldr r0,=ENC0_IDX_DriverIRQHandler + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler bx r0 - .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler .align 1 .thumb_func - .weak ENC1_COMPARE_IRQHandler - .type ENC1_COMPARE_IRQHandler, %function -ENC1_COMPARE_IRQHandler: - ldr r0,=ENC1_COMPARE_DriverIRQHandler + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler bx r0 - .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC1_HOME_IRQHandler - .type ENC1_HOME_IRQHandler, %function -ENC1_HOME_IRQHandler: - ldr r0,=ENC1_HOME_DriverIRQHandler + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler bx r0 - .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler .align 1 .thumb_func - .weak ENC1_WDG_SAB_IRQHandler - .type ENC1_WDG_SAB_IRQHandler, %function -ENC1_WDG_SAB_IRQHandler: - ldr r0,=ENC1_WDG_SAB_DriverIRQHandler + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler bx r0 - .size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC1_IDX_IRQHandler - .type ENC1_IDX_IRQHandler, %function -ENC1_IDX_IRQHandler: - ldr r0,=ENC1_IDX_DriverIRQHandler + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler bx r0 - .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler .align 1 .thumb_func @@ -1633,21 +1631,21 @@ ETB0_IRQHandler: .align 1 .thumb_func - .weak SM3_IRQHandler - .type SM3_IRQHandler, %function -SM3_IRQHandler: - ldr r0,=SM3_DriverIRQHandler + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler bx r0 - .size SM3_IRQHandler, . - SM3_IRQHandler + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler .align 1 .thumb_func - .weak TRNG0_IRQHandler - .type TRNG0_IRQHandler, %function -TRNG0_IRQHandler: - ldr r0,=TRNG0_DriverIRQHandler + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler bx r0 - .size TRNG0_IRQHandler, . - TRNG0_IRQHandler + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler .align 1 .thumb_func @@ -1824,14 +1822,14 @@ CTI0_IRQHandler: def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler - def_irq_handler ENC0_COMPARE_DriverIRQHandler - def_irq_handler ENC0_HOME_DriverIRQHandler - def_irq_handler ENC0_WDG_SAB_DriverIRQHandler - def_irq_handler ENC0_IDX_DriverIRQHandler - def_irq_handler ENC1_COMPARE_DriverIRQHandler - def_irq_handler ENC1_HOME_DriverIRQHandler - def_irq_handler ENC1_WDG_SAB_DriverIRQHandler - def_irq_handler ENC1_IDX_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler def_irq_handler ITRC0_DriverIRQHandler def_irq_handler BSP32_DriverIRQHandler def_irq_handler ELS_ERR_DriverIRQHandler @@ -1850,8 +1848,8 @@ CTI0_IRQHandler: def_irq_handler WUU_DriverIRQHandler def_irq_handler PORT_EFT_DriverIRQHandler def_irq_handler ETB0_DriverIRQHandler - def_irq_handler SM3_DriverIRQHandler - def_irq_handler TRNG0_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler def_irq_handler WWDT0_DriverIRQHandler def_irq_handler WWDT1_DriverIRQHandler def_irq_handler CMC0_DriverIRQHandler diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S index d74e0a4a30..d73abf8602 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S @@ -2,15 +2,13 @@ /* @file: startup_MCXN947_cm33_core1.s */ /* @purpose: CMSIS Cortex-M33 Core Device Startup File */ /* MCXN947_cm33_core1 */ -/* @version: 1.0 */ -/* @date: 2022-10-1 */ -/* @build: b230131 */ +/* @version: 2.0 */ +/* @date: 2023-2-1 */ +/* @build: b240410 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2023 NXP */ -/* All rights reserved. */ -/* */ +/* Copyright 2016-2024 NXP */ /* SPDX-License-Identifier: BSD-3-Clause */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ @@ -165,14 +163,14 @@ __Vectors: .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ - .long ENC0_COMPARE_IRQHandler /* ENC0_Compare interrupt*/ - .long ENC0_HOME_IRQHandler /* ENC0_Home interrupt*/ - .long ENC0_WDG_SAB_IRQHandler /* ENC0_WDG_IRQ/SAB interrupt*/ - .long ENC0_IDX_IRQHandler /* ENC0_IDX interrupt*/ - .long ENC1_COMPARE_IRQHandler /* ENC1_Compare interrupt*/ - .long ENC1_HOME_IRQHandler /* ENC1_Home interrupt*/ - .long ENC1_WDG_SAB_IRQHandler /* ENC1_WDG_IRQ/SAB interrupt*/ - .long ENC1_IDX_IRQHandler /* ENC1_IDX interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ .long BSP32_IRQHandler /* CoolFlux BSP32 interrupt*/ .long ELS_ERR_IRQHandler /* ELS error interrupt*/ @@ -191,8 +189,8 @@ __Vectors: .long WUU_IRQHandler /* Wake Up Unit interrupt*/ .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ .long ETB0_IRQHandler /* ETB counter expires interrupt*/ - .long SM3_IRQHandler /* Secure Generic Interface (SGI) SAFO interrupt */ - .long TRNG0_IRQHandler /* True Random Number Generator interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ @@ -1391,75 +1389,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler: .align 1 .thumb_func - .weak ENC0_COMPARE_IRQHandler - .type ENC0_COMPARE_IRQHandler, %function -ENC0_COMPARE_IRQHandler: - ldr r0,=ENC0_COMPARE_DriverIRQHandler + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler bx r0 - .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC0_HOME_IRQHandler - .type ENC0_HOME_IRQHandler, %function -ENC0_HOME_IRQHandler: - ldr r0,=ENC0_HOME_DriverIRQHandler + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler bx r0 - .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler .align 1 .thumb_func - .weak ENC0_WDG_SAB_IRQHandler - .type ENC0_WDG_SAB_IRQHandler, %function -ENC0_WDG_SAB_IRQHandler: - ldr r0,=ENC0_WDG_SAB_DriverIRQHandler + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler bx r0 - .size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC0_IDX_IRQHandler - .type ENC0_IDX_IRQHandler, %function -ENC0_IDX_IRQHandler: - ldr r0,=ENC0_IDX_DriverIRQHandler + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler bx r0 - .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler .align 1 .thumb_func - .weak ENC1_COMPARE_IRQHandler - .type ENC1_COMPARE_IRQHandler, %function -ENC1_COMPARE_IRQHandler: - ldr r0,=ENC1_COMPARE_DriverIRQHandler + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler bx r0 - .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC1_HOME_IRQHandler - .type ENC1_HOME_IRQHandler, %function -ENC1_HOME_IRQHandler: - ldr r0,=ENC1_HOME_DriverIRQHandler + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler bx r0 - .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler .align 1 .thumb_func - .weak ENC1_WDG_SAB_IRQHandler - .type ENC1_WDG_SAB_IRQHandler, %function -ENC1_WDG_SAB_IRQHandler: - ldr r0,=ENC1_WDG_SAB_DriverIRQHandler + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler bx r0 - .size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC1_IDX_IRQHandler - .type ENC1_IDX_IRQHandler, %function -ENC1_IDX_IRQHandler: - ldr r0,=ENC1_IDX_DriverIRQHandler + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler bx r0 - .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler .align 1 .thumb_func @@ -1625,21 +1623,21 @@ ETB0_IRQHandler: .align 1 .thumb_func - .weak SM3_IRQHandler - .type SM3_IRQHandler, %function -SM3_IRQHandler: - ldr r0,=SM3_DriverIRQHandler + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler bx r0 - .size SM3_IRQHandler, . - SM3_IRQHandler + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler .align 1 .thumb_func - .weak TRNG0_IRQHandler - .type TRNG0_IRQHandler, %function -TRNG0_IRQHandler: - ldr r0,=TRNG0_DriverIRQHandler + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler bx r0 - .size TRNG0_IRQHandler, . - TRNG0_IRQHandler + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler .align 1 .thumb_func @@ -1816,14 +1814,14 @@ CTI0_IRQHandler: def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler - def_irq_handler ENC0_COMPARE_DriverIRQHandler - def_irq_handler ENC0_HOME_DriverIRQHandler - def_irq_handler ENC0_WDG_SAB_DriverIRQHandler - def_irq_handler ENC0_IDX_DriverIRQHandler - def_irq_handler ENC1_COMPARE_DriverIRQHandler - def_irq_handler ENC1_HOME_DriverIRQHandler - def_irq_handler ENC1_WDG_SAB_DriverIRQHandler - def_irq_handler ENC1_IDX_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler def_irq_handler ITRC0_DriverIRQHandler def_irq_handler BSP32_DriverIRQHandler def_irq_handler ELS_ERR_DriverIRQHandler @@ -1842,8 +1840,8 @@ CTI0_IRQHandler: def_irq_handler WUU_DriverIRQHandler def_irq_handler PORT_EFT_DriverIRQHandler def_irq_handler ETB0_DriverIRQHandler - def_irq_handler SM3_DriverIRQHandler - def_irq_handler TRNG0_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler def_irq_handler WWDT0_DriverIRQHandler def_irq_handler WWDT1_DriverIRQHandler def_irq_handler CMC0_DriverIRQHandler diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c index 6c88602925..995880fe84 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c @@ -1,5 +1,5 @@ /* - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -205,7 +205,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base) * brief Invalidates cache by range. * * param address The physical address of cache. - * param size_byte size of the memory to be invalidated. + * param size_byte size of the memory to be invalidated, should be larger than 0. * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if * startAddr is not aligned. For the size_byte, application should make sure the @@ -213,36 +213,39 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base) */ void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte) { - uint32_t endAddr = address + size_byte - 0x01U; - uint32_t pccReg = 0; - /* Align address to cache line size. */ - uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); - uint32_t instance = CACHE64_GetInstanceByAddr(address); - uint32_t endLim; - CACHE64_CTRL_Type *base; - - if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) + if (size_byte > 0UL) { - return; - } - base = s_cache64ctrlBases[instance]; - endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U; - endAddr = endAddr > endLim ? endLim : endAddr; + uint32_t endAddr = address + size_byte - 0x01U; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); + uint32_t instance = CACHE64_GetInstanceByAddr(address); + uint32_t endLim; + CACHE64_CTRL_Type *base; - /* Set the invalidate by line command and use the physical address. */ - pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK; - base->CLCR = pccReg; - - while (startAddr < endAddr) - { - /* Set the address and initiate the command. */ - base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) { + return; + } + base = s_cache64ctrlBases[instance]; + endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U; + endAddr = endAddr > endLim ? endLim : endAddr; + + /* Set the invalidate by line command and use the physical address. */ + pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK; + base->CLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + { + } + startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; } - startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; } } @@ -268,7 +271,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base) * brief Cleans cache by range. * * param address The physical address of cache. - * param size_byte size of the memory to be cleaned. + * param size_byte size of the memory to be cleaned, should be larger than 0. * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if * startAddr is not aligned. For the size_byte, application should make sure the @@ -276,36 +279,39 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base) */ void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte) { - uint32_t endAddr = address + size_byte - 0x01U; - uint32_t pccReg = 0; - /* Align address to cache line size. */ - uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); - uint32_t instance = CACHE64_GetInstanceByAddr(address); - uint32_t endLim; - CACHE64_CTRL_Type *base; - - if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) + if (size_byte > 0UL) { - return; - } - base = s_cache64ctrlBases[instance]; - endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U; - endAddr = endAddr > endLim ? endLim : endAddr; + uint32_t endAddr = address + size_byte - 0x01U; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); + uint32_t instance = CACHE64_GetInstanceByAddr(address); + uint32_t endLim; + CACHE64_CTRL_Type *base; - /* Set the push by line command. */ - pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK; - base->CLCR = pccReg; - - while (startAddr < endAddr) - { - /* Set the address and initiate the command. */ - base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) { + return; + } + base = s_cache64ctrlBases[instance]; + endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U; + endAddr = endAddr > endLim ? endLim : endAddr; + + /* Set the push by line command. */ + pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK; + base->CLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + { + } + startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; } - startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; } } @@ -333,7 +339,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base) * brief Cleans and invalidate cache by range. * * param address The physical address of cache. - * param size_byte size of the memory to be Cleaned and Invalidated. + * param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0. * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if * startAddr is not aligned. For the size_byte, application should make sure the @@ -341,36 +347,39 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base) */ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte) { - uint32_t endAddr = address + size_byte - 0x01U; - uint32_t pccReg = 0; - /* Align address to cache line size. */ - uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); - uint32_t instance = CACHE64_GetInstanceByAddr(address); - uint32_t endLim; - CACHE64_CTRL_Type *base; - - if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) + if (size_byte > 0UL) { - return; - } - base = s_cache64ctrlBases[instance]; - endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U; - endAddr = endAddr > endLim ? endLim : endAddr; + uint32_t endAddr = address + size_byte - 0x01U; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U); + uint32_t instance = CACHE64_GetInstanceByAddr(address); + uint32_t endLim; + CACHE64_CTRL_Type *base; - /* Set the push by line command. */ - pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK; - base->CLCR = pccReg; - - while (startAddr < endAddr) - { - /* Set the address and initiate the command. */ - base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; - - /* Wait until the cache command completes. */ - while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + if (instance >= ARRAY_SIZE(s_cache64ctrlBases)) { + return; + } + base = s_cache64ctrlBases[instance]; + endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U; + endAddr = endAddr > endLim ? endLim : endAddr; + + /* Set the push by line command. */ + pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK; + base->CLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U) + { + } + startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; } - startAddr += (uint32_t)CACHE64_LINESIZE_BYTE; } } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h index ee84ce2749..f95c9ce69c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h @@ -1,12 +1,12 @@ /* - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CACHE_H_ -#define _FSL_CACHE_H_ +#ifndef FSL_CACHE_H_ +#define FSL_CACHE_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief cache driver version. */ -#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) -/*@}*/ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*! @} */ /*! @brief cache line size. */ #define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE) @@ -138,7 +138,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base); * @brief Invalidates cache by range. * * @param address The physical address of cache. - * @param size_byte size of the memory to be invalidated. + * @param size_byte size of the memory to be invalidated, should be larger than 0. * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if * startAddr is not aligned. For the size_byte, application should make sure the @@ -158,7 +158,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base); * @brief Cleans cache by range. * * @param address The physical address of cache. - * @param size_byte size of the memory to be cleaned. + * @param size_byte size of the memory to be cleaned, should be larger than 0. * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if * startAddr is not aligned. For the size_byte, application should make sure the @@ -178,7 +178,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base); * @brief Cleans and invalidate cache by range. * * @param address The physical address of cache. - * @param size_byte size of the memory to be Cleaned and Invalidated. + * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0. * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE". * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if * startAddr is not aligned. For the size_byte, application should make sure the @@ -198,7 +198,7 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte); void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable); #endif -/*@}*/ +/*! @} */ /*! * @name Unified Cache Control for all caches @@ -209,7 +209,7 @@ void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable); * @brief Invalidates instruction cache by range. * * @param address The physical address. - * @param size_byte size of the memory to be invalidated. + * @param size_byte size of the memory to be invalidated, should be larger than 0. * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line * size if startAddr is not aligned. For the size_byte, application should make sure the @@ -224,7 +224,7 @@ static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte * @brief Invalidates data cache by range. * * @param address The physical address. - * @param size_byte size of the memory to be invalidated. + * @param size_byte size of the memory to be invalidated, should be larger than 0. * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line * size if startAddr is not aligned. For the size_byte, application should make sure the @@ -239,7 +239,7 @@ static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte * @brief Clean data cache by range. * * @param address The physical address. - * @param size_byte size of the memory to be cleaned. + * @param size_byte size of the memory to be cleaned, should be larger than 0. * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line * size if startAddr is not aligned. For the size_byte, application should make sure the @@ -254,7 +254,7 @@ static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) * @brief Cleans and Invalidates data cache by range. * * @param address The physical address. - * @param size_byte size of the memory to be Cleaned and Invalidated. + * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0. * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line * size if startAddr is not aligned. For the size_byte, application should make sure the @@ -265,7 +265,7 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size CACHE64_CleanInvalidateCacheByRange(address, size_byte); } -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -273,4 +273,4 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size /*! @}*/ -#endif /* _FSL_CACHE_H_*/ +#endif /* FSL_CACHE_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h index e480cdd422..54dd1fd840 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h @@ -1,11 +1,11 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CACHE_LPCAC_H_ -#define _FSL_CACHE_LPCAC_H_ +#ifndef FSL_CACHE_LPCAC_H_ +#define FSL_CACHE_LPCAC_H_ #include "fsl_common.h" @@ -21,7 +21,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief cache driver version */ -#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +#define FSL_CACHE_LPCAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*@}*/ /******************************************************************************* * API @@ -60,7 +60,7 @@ static inline void L1CACHE_DisableCodeCache(void) */ static inline void L1CACHE_InvalidateCodeCache(void) { - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; } /*! @@ -181,4 +181,4 @@ static inline void L1CACHE_DisableXOMControl(void) /*! @}*/ -#endif /* _FSL_CACHE_LPCAC_H_*/ +#endif /* FSL_CACHE_LPCAC_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c index 02aac54c8d..cd3ed6eaa3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c @@ -24,6 +24,14 @@ static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS; #endif /* CDOG_IRQS */ +#ifdef CDOG_CLOCKS +static const clock_ip_name_t s_CdogClocks[] = CDOG_CLOCKS; +#endif /* CDOG_CLOCKS */ + +#ifdef CDOG_BASE_PTRS +static const CDOG_Type* s_cdogBases[] = CDOG_BASE_PTRS; +#endif /* CDOG_BASE_PTRS */ + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -31,50 +39,24 @@ static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS; /******************************************************************************* * Code ******************************************************************************/ -#if defined(CDOG) -/*! - * Weak implementation of CDOG IRQ, should be re-defined by user when using CDOG IRQ - */ -__WEAK void CDOG_DriverIRQHandler(void) -{ - /* NVIC_DisableIRQ(CDOG_IRQn); - * CDOG_Stop(CDOG, s_start); - * CDOG->FLAGS = 0x0U; - * CDOG_Start(CDOG, 0xFFFFFFU, s_start); - * NVIC_EnableIRQ(CDOG_IRQn); - */ -} -#endif -#if defined(CDOG0) -/*! - * Weak implementation of CDOG0 IRQ, should be re-defined by user when using CDOG IRQ - */ -__WEAK void CDOG0_DriverIRQHandler(void) +static uint32_t CDOG_GetInstance(CDOG_Type *base) { - /* NVIC_DisableIRQ(CDOG0_IRQn); - * CDOG_Stop(CDOG0, s_start); - * CDOG0->FLAGS = 0x0U; - * CDOG_Start(CDOG0, 0xFFFFFFU, s_start); - * NVIC_EnableIRQ(CDOG0_IRQn); - */ -} -#endif - -#if defined(CDOG1) -/*! - * Weak implementation of CDOG1 IRQ, should be re-defined by user when using CDOG IRQ - */ -__WEAK void CDOG1_DriverIRQHandler(void) -{ - /* NVIC_DisableIRQ(CDOG1_IRQn); - * CDOG_Stop(CDOG1, s_start); - * CDOG1->FLAGS = 0x0U; - * CDOG_Start(CDOG1, 0xFFFFFFU, s_start); - * NVIC_EnableIRQ(CDOG1_IRQn); - */ -} -#endif + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_cdogBases); instance++) + { + if (s_cdogBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_cdogBases)); + + return instance; +} /*! * brief Sets the default configuration of CDOG @@ -256,7 +238,13 @@ void CDOG_Sub256(CDOG_Type *base) */ void CDOG_Check(CDOG_Type *base, uint32_t check) { +#if defined(FLS_FEATURE_CDOG_USE_RESTART) base->RESTART = check; +#else + base->STOP = check; + base->RELOAD = base->RELOAD; + base->START= check; +#endif } /*! @@ -295,7 +283,7 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) /* Ungate clock to CDOG engine and reset it */ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #ifdef CDOG_CLOCKS - CLOCK_EnableClock(kCLOCK_Cdog); + CLOCK_EnableClock(s_CdogClocks[CDOG_GetInstance(base)]); #endif /* CDOG_CLOCKS */ #endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -322,6 +310,25 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) } else { +/* load default values for CDOG->CONTROL before flags clear */ +#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0) + cdog_config_t default_conf; + + /* Initialize CDOG */ + CDOG_GetDefaultConfig(&default_conf); + + /* Write default value to CDOG->CONTROL*/ + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(default_conf.state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */ + CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ +#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */ + base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | CDOG_FLAGS_POR_FLAG(0U); @@ -338,11 +345,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ #if defined(CDOG_IRQS) - /* Enable peripheral IRQs, if defined in array */ - for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++) - { - NVIC_EnableIRQ(s_CdogIrqs[i]); - } + /* Enable peripheral IRQ */ + NVIC_EnableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]); #endif /* CDOG_IRQS */ return kStatus_Success; @@ -358,11 +362,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) void CDOG_Deinit(CDOG_Type *base) { #if defined(CDOG_IRQS) - /* Enable peripheral IRQs, if defined in array */ - for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++) - { - NVIC_DisableIRQ(s_CdogIrqs[i]); - } + /* Disable peripheral IRQ */ + NVIC_DisableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]); #endif /* CDOG_IRQS */ #if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) @@ -371,7 +372,7 @@ void CDOG_Deinit(CDOG_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #ifdef CDOG_CLOCKS - CLOCK_DisableClock(kCLOCK_Cdog); + CLOCK_DisableClock(s_CdogClocks[CDOG_GetInstance(base)]); #endif /* CDOG_CLOCKS */ #endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h index 33a66e47d3..7252eaccd8 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CDOG_H_ -#define _FSL_CDOG_H_ +#ifndef FSL_CDOG_H_ +#define FSL_CDOG_H_ #include "fsl_common.h" @@ -21,10 +21,13 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief Defines CDOG driver version 2.1.2. +/*! @{ */ +/*! @brief Defines CDOG driver version 2.1.3. * * Change log: + * - Version 2.1.3 + * - Re-design multiple instance IRQs and Clocks + * - Add fix for RESTART command errata * - Version 2.1.2 * - Support multiple IRQs * - Fix default CONTROL values @@ -39,8 +42,8 @@ * - Version 2.0.0 * - initial version */ -#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ +#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*! @} */ typedef struct { @@ -139,17 +142,6 @@ typedef uint32_t secure_counter_t; /******************************************************************************* * API *******************************************************************************/ -#if defined(CDOG) -extern void CDOG_DriverIRQHandler(void); -#endif - -#if defined(CDOG0) -extern void CDOG0_DriverIRQHandler(void); -#endif - -#if defined(CDOG1) -extern void CDOG1_DriverIRQHandler(void); -#endif #if defined(__cplusplus) extern "C" { @@ -334,4 +326,4 @@ uint32_t CDOG_ReadPersistent(CDOG_Type *base); /*! @}*/ /* end of group cdog */ -#endif /* _FSL_CDOG_H_ */ +#endif /* FSL_CDOG_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c index a994956814..3fef68439d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -207,6 +207,13 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq) return (status_t)kStatus_SCG_Busy; } + /* If sosc is used by PLL and PLL is used by system, return error. */ + if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_MASK) != 0U)) || + (((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0U))) + { + return (status_t)kStatus_SCG_Busy; + } + /* If configure register is locked, return error. */ if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) { @@ -238,6 +245,83 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq) return kStatus_Success; } +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If sosc is used by PLL and PLL is used by system, return error. */ + if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_MASK) != 0U)) || + (((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0U))) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /*Configure SOSC range */ + SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + /** * @brief Initialize the OSC 32K. * @param id : OSC 32 kHz output clock to specified modules @@ -250,8 +334,8 @@ status_t CLOCK_SetupOsc32KClocking(uint32_t id) VBAT0->OSCCTLA = (VBAT0->OSCCTLA & ~(VBAT_OSCCTLA_MODE_EN_MASK | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK)) | - VBAT_OSCCTLA_MODE_EN(0x2) | VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK; - VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xDFF7E); + VBAT_OSCCTLA_MODE_EN(0x0) | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK; + VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xFFF7E); /* Wait for STATUSA[OSC_RDY] to set. */ while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) { @@ -309,11 +393,11 @@ status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config) if (kSCG_FircTrimNonUpdate == config.trimMode) { - //SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); + SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); } /* Set trim mode. */ - // SCG0->FIRCCSR = (uint32_t)config.trimMode; + SCG0->FIRCCSR = (uint32_t)config.trimMode; if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) { @@ -444,6 +528,89 @@ void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode) SCG0->SPLLCSR = reg; } +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access + * time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode) +{ + uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */ + switch ((uint32_t)mode) + { + case (uint32_t)kMD_Mode: + { + if (system_freq_hz > 50000000U) + { + return kStatus_Fail; + } + if (system_freq_hz > 24000000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case (uint32_t)kSD_Mode: + { + if (system_freq_hz > 100000000U) + { + return kStatus_Fail; + } + if (system_freq_hz > 64000000U) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case (uint32_t)kOD_Mode: + { + if (system_freq_hz > 150000000U) + { + return kStatus_Fail; + } + if (system_freq_hz > 100000000U) + { + num_wait_states_added = 3U; + } + else if (system_freq_hz > 64000000U) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000U) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + default: + num_wait_states_added = 0U; + break; + } + + /* additional wait-states are added */ + FMU0->FCTRL = (FMU0->FCTRL & 0xFFFFFFF0UL) | (num_wait_states_added & 0xFUL); + + return kStatus_Success; +} + /*! * @brief Config 32k Crystal Oscillator. * @@ -677,11 +844,14 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) switch (clockName) { + case kCLOCK_MainClk: + freq = CLOCK_GetMainClkFreq(); + break; case kCLOCK_CoreSysClk: freq = CLOCK_GetCoreSysClkFreq(); break; case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetCoreSysClkFreq(); break; case kCLOCK_SystickClk0: freq = CLOCK_GetSystickClkFreq(0U); @@ -735,10 +905,10 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToMain); break; case kCLOCK_Pll0Out: - freq = CLOCK_GetPll1OutFreq(); + freq = CLOCK_GetPll0OutFreq(); break; case kCLOCK_Pll1Out: - freq = CLOCK_GetPll0OutFreq(); + freq = CLOCK_GetPll1OutFreq(); break; case kCLOCK_UsbPllOut: // freq = CLOCK_GetPll0OutFreq(); @@ -1568,6 +1738,9 @@ uint32_t CLOCK_GetWdtClkFreq(uint32_t id) case 2U: freq = CLOCK_GetClk1MFreq(); break; + case 3U: + freq = CLOCK_GetClk1MFreq(); + break; default: freq = 0U; break; @@ -2037,7 +2210,7 @@ pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) /* Unlock SPLLLOCK_CNFG register */ SCG0->TRIM_LOCK = 0x5a5a0001; - /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */ + /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */ inRate = CLOCK_GetPLL1InClockRate(); prediv = findPll1PreDiv(); /* Adjust input clock */ @@ -2160,10 +2333,10 @@ static uint32_t CLOCK_GetOsc32KFreq(uint32_t id) } /* Get MAIN Clk */ -/*! brief Return Frequency of Core System - * return Frequency of Core System +/*! @brief Return Frequency of main + * @return Frequency of the main */ -uint32_t CLOCK_GetCoreSysClkFreq(void) +uint32_t CLOCK_GetMainClkFreq(void) { uint32_t freq = 0U; @@ -2198,6 +2371,19 @@ uint32_t CLOCK_GetCoreSysClkFreq(void) return freq; } +/* Get cpu Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + freq = CLOCK_GetMainClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + + return freq; +} + /* Get Systick Clk */ /*! brief Return Frequency of SystickClock * return Frequency of Systick Clock @@ -2209,7 +2395,7 @@ static uint32_t CLOCK_GetSystickClkFreq(uint32_t id) switch ((id == 0U) ? SYSCON->SYSTICKCLKSEL0 : SYSCON->SYSTICKCLKSEL1) { case 0U: - freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U); + freq = CLOCK_GetMainClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U); break; case 1U: freq = CLOCK_GetClk1MFreq(); @@ -2236,7 +2422,7 @@ static uint32_t CLOCK_GetClockOutClkFreq(void) switch (SYSCON->CLKOUTSEL) { case 0U: - freq = CLOCK_GetCoreSysClkFreq(); + freq = CLOCK_GetMainClkFreq(); break; case 1U: freq = CLOCK_GetPll0OutFreq(); @@ -2276,12 +2462,12 @@ static uint32_t CLOCK_GetLposcFreq(void) switch ((RTC0->CTRL & RTC_CTRL_CLK_SEL_MASK) >> RTC_CTRL_CLK_SEL_SHIFT) { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; case 1U: freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); break; - case 2U: - freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); - break; default: freq = 0U; break; @@ -2928,3 +3114,23 @@ bool CLOCK_EnableUsbhsClock(void) } return true; } + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void) +{ + /* System OSC Clock Monitor is disabled */ + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); + + firc_trim_config_t fircAutoTrimConfig = { + .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ + .trimSrc = kSCG_FircTrimSrcUsb0, /* Trim source is USB0 start of frame (1kHz) */ + .trimDiv = 1U, /* Divided value */ + .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ + .trimFine = 0U, /* Trim value, see Reference Manual for more information */ + }; + + return CLOCK_FROHFTrimConfig(fircAutoTrimConfig); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h index 811240e86e..9e0ea282e3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 1.0.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief CLOCK driver version 1.0.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 1)) /*@}*/ /*! @brief Configure whether driver controls clock @@ -205,17 +205,17 @@ kCLOCK_Dac2 \ } /*! @brief Clock ip name array for PWM. */ -#define PWM_CLOCKS \ - { \ - {kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0, kCLOCK_Pwm0}, \ - { \ - kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \ - } \ +#define PWM_CLOCKS \ + { \ + {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \ + { \ + kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \ + } \ } -/*! @brief Clock ip name array for ENC. */ -#define ENC_CLOCKS \ +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS \ { \ - kCLOCK_Enc0, kCLOCK_Enc1 \ + kCLOCK_Qdc0, kCLOCK_Qdc1 \ } /*! @brief Clock ip name array for FLEXIO. */ #define FLEXIO_CLOCKS \ @@ -290,7 +290,17 @@ /*! @brief Clock ip name array for LPCMP. */ #define LPCMP_CLOCKS \ { \ - kCLOCK_None, kCLOCK_Cmp2, kCLOCK_None \ + kCLOCK_None, kCLOCK_None, kCLOCK_Cmp2 \ + } +/*! @brief Clock ip name array for SINC */ +#define SINC_CLOCKS \ + { \ + kCLOCK_Sinc \ + } +/*! @brief Clock ip name array for SEMA42 */ +#define SEMA42_CLOCKS \ + { \ + kCLOCK_Sema42 \ } /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ /*------------------------------------------------------------------------------ @@ -309,291 +319,169 @@ #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define AHB_CLK_CTRL2 2 -#define AHB_CLK_CTRL3 3 +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 +#define AHB_CLK_CTRL3 3 +#define REG_PWM0SUBCTL 250 +#define REG_PWM1SUBCTL 251 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ typedef enum _clock_ip_name { - kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_None = 0U, /*!< None clock gate. */ - kCLOCK_None = 0U, /*!< None clock gate. */ - - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ - - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 2), /*!< Clock gate name: Sram1. */ - - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram2. */ - - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram3. */ - - kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram4. */ - - kCLOCK_Sram5 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram5. */ - - kCLOCK_Sram6 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Sram6. */ - - kCLOCK_Sram7 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Sram7. */ - - kCLOCK_Fmu = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Fmu. */ - - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Fmc. */ - - kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: Flexspi. */ - - kCLOCK_InputMux0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ - - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ - - kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */ - - kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */ - - kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */ - - kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */ - - kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */ - - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */ - - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */ - - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */ - - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */ - - kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */ - - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 25), /*!< Clock gate name: Pint. */ - - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Dma0. */ - - kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Crc. */ - - kCLOCK_Wwdt0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28), /*!< Clock gate name: Wwdt0. */ - - kCLOCK_Wwdt1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29), /*!< Clock gate name: Wwdt1. */ - - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 31), /*!< Clock gate name: Mailbox. */ - - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ - - kCLOCK_OsTimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer. */ - - kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct. */ - - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 3), /*!< Clock gate name: Adc0. */ - - kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 4), /*!< Clock gate name: Adc1. */ - - kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 5), /*!< Clock gate name: Dac0. */ - - kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), /*!< Clock gate name: Rtc. */ - - kCLOCK_Evsim0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), /*!< Clock gate name: Evsim0. */ - - kCLOCK_Evsim1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 9), /*!< Clock gate name: Evsim1. */ - - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */ + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 2), /*!< Clock gate name: Sram1. */ + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram2. */ + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram3. */ + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram4. */ + kCLOCK_Sram5 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram5. */ + kCLOCK_Sram6 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Sram6. */ + kCLOCK_Sram7 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Sram7. */ + kCLOCK_Fmu = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Fmu. */ + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Fmc. */ + kCLOCK_Flexspi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: Flexspi. */ + kCLOCK_InputMux0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */ + kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */ + kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */ + kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */ + kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */ + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */ + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */ + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */ + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */ + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */ + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 25), /*!< Clock gate name: Pint. */ + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Dma0. */ + kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Crc. */ + kCLOCK_Wwdt0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28), /*!< Clock gate name: Wwdt0. */ + kCLOCK_Wwdt1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29), /*!< Clock gate name: Wwdt1. */ + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 31), /*!< Clock gate name: Mailbox. */ + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + kCLOCK_OsTimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer. */ + kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct. */ + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 3), /*!< Clock gate name: Adc0. */ + kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 4), /*!< Clock gate name: Adc1. */ + kCLOCK_Dac0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 5), /*!< Clock gate name: Dac0. */ + kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), /*!< Clock gate name: Rtc. */ + kCLOCK_Evsim0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), /*!< Clock gate name: Evsim0. */ + kCLOCK_Evsim1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 9), /*!< Clock gate name: Evsim1. */ + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */ kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPFlexComm0. */ - kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPFlexComm1. */ - kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPFlexComm2. */ - kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPFlexComm3. */ - kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPFlexComm4. */ - kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPFlexComm5. */ - kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPFlexComm6. */ - kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPFlexComm7. */ - kCLOCK_LPFlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPFlexComm8. */ - kCLOCK_LPFlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LPFlexComm9. */ - - kCLOCK_LPUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPUart0. */ - - kCLOCK_LPUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPUart1. */ - - kCLOCK_LPUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPUart2. */ - - kCLOCK_LPUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPUart3. */ - - kCLOCK_LPUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPUart4. */ - - kCLOCK_LPUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPUart5. */ - - kCLOCK_LPUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPUart6. */ - - kCLOCK_LPUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPUart7. */ - - kCLOCK_LPUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPUart8. */ - - kCLOCK_LPUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LPUart9. */ - - kCLOCK_LPSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPSpi0. */ - - kCLOCK_LPSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPSpi1. */ - - kCLOCK_LPSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPSpi2. */ - - kCLOCK_LPSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPSpi3. */ - - kCLOCK_LPSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPSpi4. */ - - kCLOCK_LPSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPSpi5. */ - - kCLOCK_LPSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPSpi6. */ - - kCLOCK_LPSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPSpi7. */ - - kCLOCK_LPSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPSpi8. */ - - kCLOCK_LPSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LSpi9. */ - - kCLOCK_LPI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPI2c0. */ - - kCLOCK_LPI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPI2c1. */ - - kCLOCK_LPI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPI2c2. */ - - kCLOCK_LPI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPI2c3. */ - - kCLOCK_LPI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPI2c4. */ - - kCLOCK_LPI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPI2c5. */ - - kCLOCK_LPI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPI2c6. */ - - kCLOCK_LPI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPI2c7. */ - - kCLOCK_LPI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPI2c8. */ - - kCLOCK_LPI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LPI2c9. */ - - kCLOCK_Micfil = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 21), /*!< Clock gate name: Micfil. */ - - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ - - kCLOCK_Usb0Ram = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 23), /*!< Clock gate name: Usb0Ram. */ - - kCLOCK_Usb0FsDcd = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 24), /*!< Clock gate name: Usb0FsDcd. */ - - kCLOCK_Usb0Fs = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usb0Fs. */ - - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ - - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ - - kCLOCK_PkcRam = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: PkcRam. */ - - kCLOCK_SmartDma = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: SmartDma. */ - - kCLOCK_Espi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 0), /*!< Clock gate name: Espi. */ - - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ - - kCLOCK_Enet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Enet. */ - - kCLOCK_uSdhc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: uSdhc. */ - - kCLOCK_Flexio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Flexio. */ - - kCLOCK_Sai0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Sai0. */ - - kCLOCK_Sai1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sai1. */ - - kCLOCK_Tro = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Tro. */ - - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ - - kCLOCK_Trng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Trng. */ - - kCLOCK_Flexcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: Flexcan0. */ - - kCLOCK_Flexcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Flexcan1. */ - - kCLOCK_UsbHs = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: UsbHs. */ - - kCLOCK_UsbHsPhy = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: UsbHsPhy. */ - - kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Css. */ - - kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ - - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ - - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ - - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ - - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ - - kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Pkc. */ - - kCLOCK_Scg = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 26), /*!< Clock gate name: Scg. */ - - kCLOCK_Gdet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Gdet. */ - - kCLOCK_Sm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30), /*!< Clock gate name: Sm3. */ - - kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0), /*!< Clock gate name: I3c0. */ - - kCLOCK_I3c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 1), /*!< Clock gate name: I3c1. */ - - kCLOCK_Sinc = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 2), /*!< Clock gate name: Sinc. */ - - kCLOCK_CoolFlux = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3), /*!< Clock gate name: CoolFlux. */ - - kCLOCK_Enc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4), /*!< Clock gate name: Enc0. */ - - kCLOCK_Enc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5), /*!< Clock gate name: Enc1. */ - - kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6), /*!< Clock gate name: Pwm0. */ - - kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7), /*!< Clock gate name: Pwm1. */ - - kCLOCK_Evtg = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8), /*!< Clock gate name: Evtg. */ - - kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11), /*!< Clock gate name: Dac1. */ - - kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12), /*!< Clock gate name: Dac2. */ - - kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13), /*!< Clock gate name: Opamp0. */ - - kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14), /*!< Clock gate name: Opamp1. */ - - kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15), /*!< Clock gate name: Opamp2. */ - - kCLOCK_Cmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18), /*!< Clock gate name: Cmp2. */ - - kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 19), /*!< Clock gate name: Vref. */ - + kCLOCK_LPUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPUart0. */ + kCLOCK_LPUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPUart1. */ + kCLOCK_LPUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPUart2. */ + kCLOCK_LPUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPUart3. */ + kCLOCK_LPUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPUart4. */ + kCLOCK_LPUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPUart5. */ + kCLOCK_LPUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPUart6. */ + kCLOCK_LPUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPUart7. */ + kCLOCK_LPUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPUart8. */ + kCLOCK_LPUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LPUart9. */ + kCLOCK_LPSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPSpi0. */ + kCLOCK_LPSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPSpi1. */ + kCLOCK_LPSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPSpi2. */ + kCLOCK_LPSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPSpi3. */ + kCLOCK_LPSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPSpi4. */ + kCLOCK_LPSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPSpi5. */ + kCLOCK_LPSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPSpi6. */ + kCLOCK_LPSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPSpi7. */ + kCLOCK_LPSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPSpi8. */ + kCLOCK_LPSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LSpi9. */ + kCLOCK_LPI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPI2c0. */ + kCLOCK_LPI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPI2c1. */ + kCLOCK_LPI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPI2c2. */ + kCLOCK_LPI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPI2c3. */ + kCLOCK_LPI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPI2c4. */ + kCLOCK_LPI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPI2c5. */ + kCLOCK_LPI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPI2c6. */ + kCLOCK_LPI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPI2c7. */ + kCLOCK_LPI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), /*!< Clock gate name: LPI2c8. */ + kCLOCK_LPI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), /*!< Clock gate name: LPI2c9. */ + kCLOCK_Micfil = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 21), /*!< Clock gate name: Micfil. */ + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + kCLOCK_Usb0Ram = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 23), /*!< Clock gate name: Usb0Ram. */ + kCLOCK_Usb0FsDcd = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 24), /*!< Clock gate name: Usb0FsDcd. */ + kCLOCK_Usb0Fs = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usb0Fs. */ + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + kCLOCK_PkcRam = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: PkcRam. */ + kCLOCK_Smartdma = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: SmartDma. */ + + kCLOCK_Espi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 0), /*!< Clock gate name: Espi. */ + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + kCLOCK_Enet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Enet. */ + kCLOCK_uSdhc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: uSdhc. */ + kCLOCK_Flexio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Flexio. */ + kCLOCK_Sai0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Sai0. */ + kCLOCK_Sai1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sai1. */ + kCLOCK_Tro = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Tro. */ + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + kCLOCK_Trng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Trng. */ + kCLOCK_Flexcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: Flexcan0. */ + kCLOCK_Flexcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Flexcan1. */ + kCLOCK_UsbHs = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: UsbHs. */ + kCLOCK_UsbHsPhy = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: UsbHsPhy. */ + kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Css. */ + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Pkc. */ + kCLOCK_Scg = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 26), /*!< Clock gate name: Scg. */ + kCLOCK_Gdet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Gdet. */ + kCLOCK_Sm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30), /*!< Clock gate name: Sm3. */ + + kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0), /*!< Clock gate name: I3c0. */ + kCLOCK_I3c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 1), /*!< Clock gate name: I3c1. */ + kCLOCK_Sinc = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 2), /*!< Clock gate name: Sinc. */ + kCLOCK_CoolFlux = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 3), /*!< Clock gate name: CoolFlux. */ + kCLOCK_Qdc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4), /*!< Clock gate name: Qdc0. */ + kCLOCK_Qdc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5), /*!< Clock gate name: Qdc1. */ + kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6), /*!< Clock gate name: Pwm0. */ + kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7), /*!< Clock gate name: Pwm1. */ + kCLOCK_Evtg = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8), /*!< Clock gate name: Evtg. */ + kCLOCK_Dac1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 11), /*!< Clock gate name: Dac1. */ + kCLOCK_Dac2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 12), /*!< Clock gate name: Dac2. */ + kCLOCK_Opamp0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 13), /*!< Clock gate name: Opamp0. */ + kCLOCK_Opamp1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 14), /*!< Clock gate name: Opamp1. */ + kCLOCK_Opamp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 15), /*!< Clock gate name: Opamp2. */ + kCLOCK_Cmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18), /*!< Clock gate name: Cmp2. */ + kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 19), /*!< Clock gate name: Vref. */ kCLOCK_CoolFluxApb = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 20), /*!< Clock gate name: CoolFluxApb. */ + kCLOCK_Neutron = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 21), /*!< Clock gate name: Neutron. */ + kCLOCK_Tsi = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 22), /*!< Clock gate name: Tsi. */ + kCLOCK_Ewm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Ewm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Eim = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 24), /*!< Clock gate name: Eim. */ + kCLOCK_Erm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 25), /*!< Clock gate name: Erm. */ + kCLOCK_Intm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 26), /*!< Clock gate name: Intm. */ + kCLOCK_Sema42 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 27), /*!< Clock gate name: Sema42. */ - kCLOCK_Neutron = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 21), /*!< Clock gate name: Neutron. */ + kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 0U), /*!< Clock gate name: PWM0 SM0. */ + kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 1U), /*!< Clock gate name: PWM0 SM1. */ + kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 2U), /*!< Clock gate name: PWM0 SM2. */ + kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 3U), /*!< Clock gate name: PWM0 SM3. */ - kCLOCK_Tsi = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 22), /*!< Clock gate name: Tsi. */ - - kCLOCK_Ewm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ - - kCLOCK_Ewm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ - - kCLOCK_Eim = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 24), /*!< Clock gate name: Eim. */ - - kCLOCK_Erm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 25), /*!< Clock gate name: Erm. */ - - kCLOCK_Intm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 26), /*!< Clock gate name: Intm. */ - - kCLOCK_Sema42 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 27), /*!< Clock gate name: Sema42. */ + kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 0U), /*!< Clock gate name: PWM1 SM0. */ + kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 1U), /*!< Clock gate name: PWM1 SM1. */ + kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 2U), /*!< Clock gate name: PWM1 SM2. */ + kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 3U) /*!< Clock gate name: PWM1 SM3. */ } clock_ip_name_t; @@ -605,7 +493,8 @@ typedef enum _clock_ip_name /*! @brief Clock name used to get clock frequency. */ typedef enum _clock_name { - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_MainClk, /*!< Main clock */ + kCLOCK_CoreSysClk, /*!< Core/system clock */ kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ kCLOCK_SystickClk0, /*!< Systick clock0 */ kCLOCK_SystickClk1, /*!< Systick clock1 */ @@ -714,329 +603,329 @@ typedef enum _clock_name */ typedef enum _clock_attach_id { - kCLK_IN_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 1), /*!< Attach clk_in to MAIN_CLK. */ - kFRO12M_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 2), /*!< Attach FRO_12M to MAIN_CLK. */ - kFRO_HF_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 3), /*!< Attach FRO_HF to MAIN_CLK. */ - kXTAL32K2_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 4), /*!< Attach xtal32k[2] to MAIN_CLK. */ - kPLL0_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 5), /*!< Attach PLL0 to MAIN_CLK. */ - kPLL1_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 6), /*!< Attach PLL1 to MAIN_CLK. */ - kUSB_PLL_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 7), /*!< Attach USB PLL to MAIN_CLK. */ - kNONE_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 15), /*!< Attach NONE to MAIN_CLK. */ + kCLK_IN_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 1), /*!< Attach clk_in to MAIN_CLK. */ + kFRO12M_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 2), /*!< Attach FRO_12M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 3), /*!< Attach FRO_HF to MAIN_CLK. */ + kXTAL32K2_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 4), /*!< Attach xtal32k[2] to MAIN_CLK. */ + kPLL0_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 5), /*!< Attach PLL0 to MAIN_CLK. */ + kPLL1_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 6), /*!< Attach PLL1 to MAIN_CLK. */ + kUSB_PLL_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 7), /*!< Attach USB PLL to MAIN_CLK. */ + kNONE_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 15), /*!< Attach NONE to MAIN_CLK. */ - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ - kCLK_1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach Clk 1 MHz to SYSTICK0. */ - kLPOSC_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach LP Oscillator to SYSTICK0. */ - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + kCLK_1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach Clk 1 MHz to SYSTICK0. */ + kLPOSC_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach LP Oscillator to SYSTICK0. */ + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ - kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ - kCLK_1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach Clk 1 MHz to SYSTICK1. */ - kLPOSC_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach LP Oscillator to SYSTICK1. */ - kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ + kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ + kCLK_1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach Clk 1 MHz to SYSTICK1. */ + kLPOSC_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach LP Oscillator to SYSTICK1. */ + kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ - kCLK_1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach Clk 1 MHz to TRACE. */ - kLPOSC_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach LP Oscillator to TRACE. */ - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + kCLK_1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach Clk 1 MHz to TRACE. */ + kLPOSC_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach LP Oscillator to TRACE. */ + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ - kCLK_1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach CLK_1M to CTIMER0. */ - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ - kPLL1_CLK0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1_clk0 to CTIMER0. */ - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ - kFRO12M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO 12MHz to CTIMER0. */ - kSAI0_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach SAI0 MCLK IN to CTIMER0. */ - kLPOSC_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach LP Oscillator to CTIMER0. */ - kSAI1_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 8), /*!< Attach SAI1 MCLK IN to CTIMER0. */ - kSAI0_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 9), /*!< Attach SAI0 TX_BCLK to CTIMER0. */ - kSAI0_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 10), /*!< Attach SAI0 RX_BCLK to CTIMER0. */ - kSAI1_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 11), /*!< Attach SAI1 TX_BCLK to CTIMER0. */ - kSAI1_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 12), /*!< Attach SAI1 RX_BCLK to CTIMER0. */ - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 15), /*!< Attach NONE to CTIMER0. */ + kCLK_1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach CLK_1M to CTIMER0. */ + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + kPLL1_CLK0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1_clk0 to CTIMER0. */ + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + kFRO12M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO 12MHz to CTIMER0. */ + kSAI0_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach SAI0 MCLK IN to CTIMER0. */ + kLPOSC_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach LP Oscillator to CTIMER0. */ + kSAI1_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 8), /*!< Attach SAI1 MCLK IN to CTIMER0. */ + kSAI0_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 9), /*!< Attach SAI0 TX_BCLK to CTIMER0. */ + kSAI0_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 10), /*!< Attach SAI0 RX_BCLK to CTIMER0. */ + kSAI1_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 11), /*!< Attach SAI1 TX_BCLK to CTIMER0. */ + kSAI1_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 12), /*!< Attach SAI1 RX_BCLK to CTIMER0. */ + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 15), /*!< Attach NONE to CTIMER0. */ - kCLK_1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach CLK_1M to CTIMER1. */ - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ - kPLL1_CLK0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1_clk0 to CTIMER1. */ - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ - kFRO12M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO 12MHz to CTIMER1. */ - kSAI0_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach SAI0 MCLK IN to CTIMER1. */ - kLPOSC_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach LP Oscillator to CTIMER1. */ - kSAI1_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 8), /*!< Attach SAI1 MCLK IN to CTIMER1. */ - kSAI0_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 9), /*!< Attach SAI0 TX_BCLK to CTIMER1. */ - kSAI0_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 10), /*!< Attach SAI0 RX_BCLK to CTIMER1. */ - kSAI1_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 11), /*!< Attach SAI1 TX_BCLK to CTIMER1. */ - kSAI1_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 12), /*!< Attach SAI1 RX_BCLK to CTIMER1. */ - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 15), /*!< Attach NONE to CTIMER1. */ + kCLK_1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach CLK_1M to CTIMER1. */ + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + kPLL1_CLK0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1_clk0 to CTIMER1. */ + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + kFRO12M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO 12MHz to CTIMER1. */ + kSAI0_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach SAI0 MCLK IN to CTIMER1. */ + kLPOSC_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach LP Oscillator to CTIMER1. */ + kSAI1_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 8), /*!< Attach SAI1 MCLK IN to CTIMER1. */ + kSAI0_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 9), /*!< Attach SAI0 TX_BCLK to CTIMER1. */ + kSAI0_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 10), /*!< Attach SAI0 RX_BCLK to CTIMER1. */ + kSAI1_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 11), /*!< Attach SAI1 TX_BCLK to CTIMER1. */ + kSAI1_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 12), /*!< Attach SAI1 RX_BCLK to CTIMER1. */ + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 15), /*!< Attach NONE to CTIMER1. */ - kCLK_1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach CLK_1M to CTIMER2. */ - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ - kPLL1_CLK0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1_clk0 to CTIMER2. */ - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ - kFRO12M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO 12MHz to CTIMER2. */ - kSAI0_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach SAI0 MCLK IN to CTIMER2. */ - kLPOSC_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach LP Oscillator to CTIMER2. */ - kSAI1_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 8), /*!< Attach SAI1 MCLK IN to CTIMER2. */ - kSAI0_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 9), /*!< Attach SAI0 TX_BCLK to CTIMER2. */ - kSAI0_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 10), /*!< Attach SAI0 RX_BCLK to CTIMER2. */ - kSAI1_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 11), /*!< Attach SAI1 TX_BCLK to CTIMER2. */ - kSAI1_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 12), /*!< Attach SAI1 RX_BCLK to CTIMER2. */ - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 15), /*!< Attach NONE to CTIMER2. */ + kCLK_1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach CLK_1M to CTIMER2. */ + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + kPLL1_CLK0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1_clk0 to CTIMER2. */ + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + kFRO12M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO 12MHz to CTIMER2. */ + kSAI0_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach SAI0 MCLK IN to CTIMER2. */ + kLPOSC_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach LP Oscillator to CTIMER2. */ + kSAI1_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 8), /*!< Attach SAI1 MCLK IN to CTIMER2. */ + kSAI0_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 9), /*!< Attach SAI0 TX_BCLK to CTIMER2. */ + kSAI0_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 10), /*!< Attach SAI0 RX_BCLK to CTIMER2. */ + kSAI1_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 11), /*!< Attach SAI1 TX_BCLK to CTIMER2. */ + kSAI1_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 12), /*!< Attach SAI1 RX_BCLK to CTIMER2. */ + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 15), /*!< Attach NONE to CTIMER2. */ - kCLK_1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach CLK_1M to CTIMER3. */ - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ - kPLL1_CLK0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1_clk0 to CTIMER3. */ - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ - kFRO12M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO 12MHz to CTIMER3. */ - kSAI0_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach SAI0 MCLK IN to CTIMER3. */ - kLPOSC_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach LP Oscillator to CTIMER3. */ - kSAI1_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 8), /*!< Attach SAI1 MCLK IN to CTIMER3. */ - kSAI0_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 9), /*!< Attach SAI0 TX_BCLK to CTIMER3. */ - kSAI0_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 10), /*!< Attach SAI0 RX_BCLK to CTIMER3. */ - kSAI1_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 11), /*!< Attach SAI1 TX_BCLK to CTIMER3. */ - kSAI1_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 12), /*!< Attach SAI1 RX_BCLK to CTIMER3. */ - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 15), /*!< Attach NONE to CTIMER3. */ + kCLK_1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach CLK_1M to CTIMER3. */ + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + kPLL1_CLK0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1_clk0 to CTIMER3. */ + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + kFRO12M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO 12MHz to CTIMER3. */ + kSAI0_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach SAI0 MCLK IN to CTIMER3. */ + kLPOSC_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach LP Oscillator to CTIMER3. */ + kSAI1_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 8), /*!< Attach SAI1 MCLK IN to CTIMER3. */ + kSAI0_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 9), /*!< Attach SAI0 TX_BCLK to CTIMER3. */ + kSAI0_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 10), /*!< Attach SAI0 RX_BCLK to CTIMER3. */ + kSAI1_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 11), /*!< Attach SAI1 TX_BCLK to CTIMER3. */ + kSAI1_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 12), /*!< Attach SAI1 RX_BCLK to CTIMER3. */ + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 15), /*!< Attach NONE to CTIMER3. */ - kCLK_1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach CLK_1M to CTIMER4. */ - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ - kPLL1_CLK0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1_clk0 to CTIMER4. */ - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ - kFRO12M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO 12MHz to CTIMER4. */ - kSAI0_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach SAI0 MCLK IN to CTIMER4. */ - kLPOSC_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach LP Oscillator to CTIMER4. */ - kSAI1_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 8), /*!< Attach SAI1 MCLK IN to CTIMER4. */ - kSAI0_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 9), /*!< Attach SAI0 TX_BCLK to CTIMER4. */ - kSAI0_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 10), /*!< Attach SAI0 RX_BCLK to CTIMER4. */ - kSAI1_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 11), /*!< Attach SAI1 TX_BCLK to CTIMER4. */ - kSAI1_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 12), /*!< Attach SAI1 RX_BCLK to CTIMER4. */ - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 15), /*!< Attach NONE to CTIMER4. */ + kCLK_1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach CLK_1M to CTIMER4. */ + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + kPLL1_CLK0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1_clk0 to CTIMER4. */ + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + kFRO12M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO 12MHz to CTIMER4. */ + kSAI0_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach SAI0 MCLK IN to CTIMER4. */ + kLPOSC_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach LP Oscillator to CTIMER4. */ + kSAI1_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 8), /*!< Attach SAI1 MCLK IN to CTIMER4. */ + kSAI0_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 9), /*!< Attach SAI0 TX_BCLK to CTIMER4. */ + kSAI0_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 10), /*!< Attach SAI0 RX_BCLK to CTIMER4. */ + kSAI1_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 11), /*!< Attach SAI1 TX_BCLK to CTIMER4. */ + kSAI1_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 12), /*!< Attach SAI1 RX_BCLK to CTIMER4. */ + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 15), /*!< Attach NONE to CTIMER4. */ - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - kCLK_IN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach Clk_in to CLKOUT. */ - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO 12 MHz to CLKOUT. */ - kPLL1_CLK0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1_clk0 to CLKOUT. */ - kLPOSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach LP Oscillator to CLKOUT. */ - kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach USB_PLL to CLKOUT. */ - kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 15), /*!< Attach NONE to CLKOUT. */ + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + kCLK_IN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach Clk_in to CLKOUT. */ + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO 12 MHz to CLKOUT. */ + kPLL1_CLK0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1_clk0 to CLKOUT. */ + kLPOSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach LP Oscillator to CLKOUT. */ + kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach USB_PLL to CLKOUT. */ + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 15), /*!< Attach NONE to CLKOUT. */ - kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ - kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ - kFRO12M_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 3), /*!< Attach FRO 12 MHz to ADC0. */ - kCLK_IN_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach Clk_in to ADC0. */ - kPLL1_CLK0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC0. */ - kUSB_PLL_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 6), /*!< Attach USB PLL to ADC0. */ - kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ + kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ + kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ + kFRO12M_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 3), /*!< Attach FRO 12 MHz to ADC0. */ + kCLK_IN_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach Clk_in to ADC0. */ + kPLL1_CLK0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC0. */ + kUSB_PLL_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 6), /*!< Attach USB PLL to ADC0. */ + kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ - kPLL0_to_USB0 = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0. */ - kCLK_48M_to_USB0 = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach Clk 48 MHz to USB0. */ - kCLK_IN_to_USB0 = MUX_A(CM_USB0CLKSEL, 4), /*!< Attach Clk_in to USB0. */ - kPLL1_CLK0_to_USB0 = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1_clk0 to USB0. */ - kUSB_PLL_to_USB0 = MUX_A(CM_USB0CLKSEL, 6), /*!< Attach USB PLL to USB0. */ - kNONE_to_USB0 = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0. */ + kPLL0_to_USB0 = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0. */ + kCLK_48M_to_USB0 = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach Clk 48 MHz to USB0. */ + kCLK_IN_to_USB0 = MUX_A(CM_USB0CLKSEL, 4), /*!< Attach Clk_in to USB0. */ + kPLL1_CLK0_to_USB0 = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1_clk0 to USB0. */ + kUSB_PLL_to_USB0 = MUX_A(CM_USB0CLKSEL, 6), /*!< Attach USB PLL to USB0. */ + kNONE_to_USB0 = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0. */ - kPLL_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 1), /*!< Attach PLL_DIV to FLEXCOMM0. */ - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ - kCLK_1M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 4), /*!< Attach CLK_1MHz to FLEXCOMM0. */ - kUSB_PLL_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 5), /*!< Attach USB_PLL to FLEXCOMM0. */ - kLPOSC_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 6), /*!< Attach LP Oscillator to FLEXCOMM0. */ - kNONE_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + kPLL_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 1), /*!< Attach PLL_DIV to FLEXCOMM0. */ + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + kCLK_1M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 4), /*!< Attach CLK_1MHz to FLEXCOMM0. */ + kUSB_PLL_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 5), /*!< Attach USB_PLL to FLEXCOMM0. */ + kLPOSC_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 6), /*!< Attach LP Oscillator to FLEXCOMM0. */ + kNONE_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ - kPLL_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 1), /*!< Attach PLL_DIV to FLEXCOMM1. */ - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ - kCLK_1M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 4), /*!< Attach CLK_1MHz to FLEXCOMM1. */ - kUSB_PLL_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 5), /*!< Attach USB_PLL to FLEXCOMM1. */ - kLPOSC_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 6), /*!< Attach LP Oscillator to FLEXCOMM1. */ - kNONE_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + kPLL_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 1), /*!< Attach PLL_DIV to FLEXCOMM1. */ + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + kCLK_1M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 4), /*!< Attach CLK_1MHz to FLEXCOMM1. */ + kUSB_PLL_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 5), /*!< Attach USB_PLL to FLEXCOMM1. */ + kLPOSC_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 6), /*!< Attach LP Oscillator to FLEXCOMM1. */ + kNONE_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ - kPLL_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 1), /*!< Attach PLL_DIV to FLEXCOMM2. */ - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ - kCLK_1M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 4), /*!< Attach CLK_1MHz to FLEXCOMM2. */ - kUSB_PLL_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 5), /*!< Attach USB_PLL to FLEXCOMM2. */ - kLPOSC_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 6), /*!< Attach LP Oscillator to FLEXCOMM2. */ - kNONE_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + kPLL_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 1), /*!< Attach PLL_DIV to FLEXCOMM2. */ + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + kCLK_1M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 4), /*!< Attach CLK_1MHz to FLEXCOMM2. */ + kUSB_PLL_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 5), /*!< Attach USB_PLL to FLEXCOMM2. */ + kLPOSC_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 6), /*!< Attach LP Oscillator to FLEXCOMM2. */ + kNONE_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ - kPLL_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 1), /*!< Attach PLL_DIV to FLEXCOMM3. */ - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ - kCLK_1M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 4), /*!< Attach CLK_1MHz to FLEXCOMM3. */ - kUSB_PLL_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 5), /*!< Attach USB_PLL to FLEXCOMM3. */ - kLPOSC_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 6), /*!< Attach LP Oscillator to FLEXCOMM3. */ - kNONE_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + kPLL_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 1), /*!< Attach PLL_DIV to FLEXCOMM3. */ + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + kCLK_1M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 4), /*!< Attach CLK_1MHz to FLEXCOMM3. */ + kUSB_PLL_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 5), /*!< Attach USB_PLL to FLEXCOMM3. */ + kLPOSC_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 6), /*!< Attach LP Oscillator to FLEXCOMM3. */ + kNONE_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ - kPLL_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 1), /*!< Attach PLL_DIV to FLEXCOMM4. */ - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ - kCLK_1M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 4), /*!< Attach CLK_1MHz to FLEXCOMM4. */ - kUSB_PLL_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 5), /*!< Attach USB_PLL to FLEXCOMM4. */ - kLPOSC_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 6), /*!< Attach LP Oscillator to FLEXCOMM4. */ - kNONE_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + kPLL_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 1), /*!< Attach PLL_DIV to FLEXCOMM4. */ + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + kCLK_1M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 4), /*!< Attach CLK_1MHz to FLEXCOMM4. */ + kUSB_PLL_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 5), /*!< Attach USB_PLL to FLEXCOMM4. */ + kLPOSC_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 6), /*!< Attach LP Oscillator to FLEXCOMM4. */ + kNONE_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ - kPLL_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 1), /*!< Attach PLL_DIV to FLEXCOMM5. */ - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ - kCLK_1M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 4), /*!< Attach CLK_1MHz to FLEXCOMM5. */ - kUSB_PLL_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 5), /*!< Attach USB_PLL to FLEXCOMM5. */ - kLPOSC_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 6), /*!< Attach LP Oscillator to FLEXCOMM5. */ - kNONE_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + kPLL_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 1), /*!< Attach PLL_DIV to FLEXCOMM5. */ + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + kCLK_1M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 4), /*!< Attach CLK_1MHz to FLEXCOMM5. */ + kUSB_PLL_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 5), /*!< Attach USB_PLL to FLEXCOMM5. */ + kLPOSC_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 6), /*!< Attach LP Oscillator to FLEXCOMM5. */ + kNONE_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ - kPLL_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 1), /*!< Attach PLL_DIV to FLEXCOMM6. */ - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ - kCLK_1M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 4), /*!< Attach CLK_1MHz to FLEXCOMM6. */ - kUSB_PLL_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 5), /*!< Attach USB_PLL to FLEXCOMM6. */ - kLPOSC_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 6), /*!< Attach LP Oscillator to FLEXCOMM6. */ - kNONE_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + kPLL_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 1), /*!< Attach PLL_DIV to FLEXCOMM6. */ + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + kCLK_1M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 4), /*!< Attach CLK_1MHz to FLEXCOMM6. */ + kUSB_PLL_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 5), /*!< Attach USB_PLL to FLEXCOMM6. */ + kLPOSC_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 6), /*!< Attach LP Oscillator to FLEXCOMM6. */ + kNONE_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ - kPLL_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 1), /*!< Attach PLL_DIV to FLEXCOMM7. */ - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ - kCLK_1M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 4), /*!< Attach CLK_1MHz to FLEXCOMM7. */ - kUSB_PLL_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 5), /*!< Attach USB_PLL to FLEXCOMM7. */ - kLPOSC_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 6), /*!< Attach LP Oscillator to FLEXCOMM7. */ - kNONE_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + kPLL_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 1), /*!< Attach PLL_DIV to FLEXCOMM7. */ + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + kCLK_1M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 4), /*!< Attach CLK_1MHz to FLEXCOMM7. */ + kUSB_PLL_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 5), /*!< Attach USB_PLL to FLEXCOMM7. */ + kLPOSC_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 6), /*!< Attach LP Oscillator to FLEXCOMM7. */ + kNONE_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ - kPLL_DIV_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 1), /*!< Attach PLL_DIV to FLEXCOMM8. */ - kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 2), /*!< Attach FRO12M to FLEXCOMM8. */ - kFRO_HF_DIV_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM8. */ - kCLK_1M_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 4), /*!< Attach CLK_1MHz to FLEXCOMM8. */ - kUSB_PLL_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 5), /*!< Attach USB_PLL to FLEXCOMM8. */ - kLPOSC_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 6), /*!< Attach LP Oscillator to FLEXCOMM8. */ - kNONE_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 7), /*!< Attach NONE to FLEXCOMM8. */ + kPLL_DIV_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 1), /*!< Attach PLL_DIV to FLEXCOMM8. */ + kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 2), /*!< Attach FRO12M to FLEXCOMM8. */ + kFRO_HF_DIV_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM8. */ + kCLK_1M_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 4), /*!< Attach CLK_1MHz to FLEXCOMM8. */ + kUSB_PLL_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 5), /*!< Attach USB_PLL to FLEXCOMM8. */ + kLPOSC_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 6), /*!< Attach LP Oscillator to FLEXCOMM8. */ + kNONE_to_FLEXCOMM8 = MUX_A(CM_FCCLKSEL8, 7), /*!< Attach NONE to FLEXCOMM8. */ - kPLL_DIV_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 1), /*!< Attach PLL_DIV to FLEXCOMM9. */ - kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 2), /*!< Attach FRO12M to FLEXCOMM9. */ - kFRO_HF_DIV_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM9. */ - kCLK_1M_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 4), /*!< Attach CLK_1MHz to FLEXCOMM9. */ - kUSB_PLL_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 5), /*!< Attach USB_PLL to FLEXCOMM9. */ - kLPOSC_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 6), /*!< Attach LP Oscillator to FLEXCOMM9. */ - kNONE_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 7), /*!< Attach NONE to FLEXCOMM9. */ + kPLL_DIV_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 1), /*!< Attach PLL_DIV to FLEXCOMM9. */ + kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 2), /*!< Attach FRO12M to FLEXCOMM9. */ + kFRO_HF_DIV_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM9. */ + kCLK_1M_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 4), /*!< Attach CLK_1MHz to FLEXCOMM9. */ + kUSB_PLL_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 5), /*!< Attach USB_PLL to FLEXCOMM9. */ + kLPOSC_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 6), /*!< Attach LP Oscillator to FLEXCOMM9. */ + kNONE_to_FLEXCOMM9 = MUX_A(CM_FCCLKSEL9, 7), /*!< Attach NONE to FLEXCOMM9. */ - kPLL0_to_SCT = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach NONE to SCT. */ - kCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach CLK_in to SCT. */ - kFRO_HF_to_SCT = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT. */ - kPLL1_CLK0_to_SCT = MUX_A(CM_SCTCLKSEL, 4), /*!< Attach PLL1_clk0 to SCT. */ - kSAI0_MCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach SAI0 MCLK_IN to SCT. */ - kUSB_PLL_to_SCT = MUX_A(CM_SCTCLKSEL, 6), /*!< Attach USB PLL to SCT. */ - kSAI1_MCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 8), /*!< Attach SAI1 MCLK_IN to SCT. */ - kNONE_to_SCT = MUX_A(CM_SCTCLKSEL, 15), /*!< Attach NONE to SCT. */ + kPLL0_to_SCT = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach NONE to SCT. */ + kCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach CLK_in to SCT. */ + kFRO_HF_to_SCT = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT. */ + kPLL1_CLK0_to_SCT = MUX_A(CM_SCTCLKSEL, 4), /*!< Attach PLL1_clk0 to SCT. */ + kSAI0_MCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach SAI0 MCLK_IN to SCT. */ + kUSB_PLL_to_SCT = MUX_A(CM_SCTCLKSEL, 6), /*!< Attach USB PLL to SCT. */ + kSAI1_MCLK_IN_to_SCT = MUX_A(CM_SCTCLKSEL, 8), /*!< Attach SAI1 MCLK_IN to SCT. */ + kNONE_to_SCT = MUX_A(CM_SCTCLKSEL, 15), /*!< Attach NONE to SCT. */ - kCLK_IN_to_TSI = MUX_A(CM_TSICLKSEL, 2), /*!< Attach clk_in to TSI. */ - kFRO12M_to_TSI = MUX_A(CM_TSICLKSEL, 4), /*!< Attach FRO_12Mhz to TSI. */ - kNONE_to_TSI = MUX_A(CM_TSICLKSEL, 7), /*!< Attach NONE to TSI. */ + kCLK_IN_to_TSI = MUX_A(CM_TSICLKSEL, 2), /*!< Attach clk_in to TSI. */ + kFRO12M_to_TSI = MUX_A(CM_TSICLKSEL, 4), /*!< Attach FRO_12Mhz to TSI. */ + kNONE_to_TSI = MUX_A(CM_TSICLKSEL, 7), /*!< Attach NONE to TSI. */ - kPLL0_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 1), /*!< Attach PLL0 to SINCFILT. */ - kCLK_IN_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 2), /*!< Attach clk_in to SINCFILT. */ - kFRO_HF_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 3), /*!< Attach FRO_HF to SINCFILT. */ - kFRO12M_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 4), /*!< Attach FRO_12Mhz to SINCFILT. */ - kPLL1_CLK0_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 5), /*!< Attach PLL1_clk0 to SINCFILT. */ - kUSB_PLL_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 6), /*!< Attach USB PLL to SINCFILT. */ - kNONE_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 7), /*!< Attach NONE to SINCFILT. */ + kPLL0_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 1), /*!< Attach PLL0 to SINCFILT. */ + kCLK_IN_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 2), /*!< Attach clk_in to SINCFILT. */ + kFRO_HF_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 3), /*!< Attach FRO_HF to SINCFILT. */ + kFRO12M_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 4), /*!< Attach FRO_12Mhz to SINCFILT. */ + kPLL1_CLK0_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 5), /*!< Attach PLL1_clk0 to SINCFILT. */ + kUSB_PLL_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 6), /*!< Attach USB PLL to SINCFILT. */ + kNONE_to_SINCFILT = MUX_A(CM_SINCFILTCLKSEL, 7), /*!< Attach NONE to SINCFILT. */ - kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ - kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ - kFRO12M_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 3), /*!< Attach FRO12M to ADC1. */ - kCLK_IN_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach clk_in to ADC1. */ - kPLL1_CLK0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC1. */ - kUSB_PLL_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 6), /*!< Attach USB PLL to ADC1. */ - kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ + kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ + kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ + kFRO12M_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 3), /*!< Attach FRO12M to ADC1. */ + kCLK_IN_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach clk_in to ADC1. */ + kPLL1_CLK0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC1. */ + kUSB_PLL_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 6), /*!< Attach USB PLL to ADC1. */ + kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ - kPLL0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 1), /*!< Attach PLL0 to DAC0. */ - kCLK_IN_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 2), /*!< Attach Clk_in to DAC0. */ - kFRO_HF_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 3), /*!< Attach FRO_HF to DAC0. */ - kFRO12M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 4), /*!< Attach FRO_12M to DAC0. */ - kPLL1_CLK0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 5), /*!< Attach PLL1_clk0 to DAC0. */ - kNONE_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 7), /*!< Attach NONE to DAC0. */ + kPLL0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 1), /*!< Attach PLL0 to DAC0. */ + kCLK_IN_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 2), /*!< Attach Clk_in to DAC0. */ + kFRO_HF_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 3), /*!< Attach FRO_HF to DAC0. */ + kFRO12M_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 4), /*!< Attach FRO_12M to DAC0. */ + kPLL1_CLK0_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 5), /*!< Attach PLL1_clk0 to DAC0. */ + kNONE_to_DAC0 = MUX_A(CM_DAC0CLKSEL, 7), /*!< Attach NONE to DAC0. */ - kPLL0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 1), /*!< Attach PLL0 to DAC1. */ - kCLK_IN_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 2), /*!< Attach Clk_in to DAC1. */ - kFRO_HF_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 3), /*!< Attach FRO_HF to DAC1. */ - kFRO12M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 4), /*!< Attach FRO_12M to DAC1. */ - kPLL1_CLK0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 5), /*!< Attach PLL1_clk0 to DAC1. */ - kNONE_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 7), /*!< Attach NONE to DAC1. */ + kPLL0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 1), /*!< Attach PLL0 to DAC1. */ + kCLK_IN_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 2), /*!< Attach Clk_in to DAC1. */ + kFRO_HF_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 3), /*!< Attach FRO_HF to DAC1. */ + kFRO12M_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 4), /*!< Attach FRO_12M to DAC1. */ + kPLL1_CLK0_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 5), /*!< Attach PLL1_clk0 to DAC1. */ + kNONE_to_DAC1 = MUX_A(CM_DAC1CLKSEL, 7), /*!< Attach NONE to DAC1. */ - kPLL0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 1), /*!< Attach PLL0 to DAC2. */ - kCLK_IN_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 2), /*!< Attach Clk_in to DAC2. */ - kFRO_HF_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 3), /*!< Attach FRO_HF to DAC2. */ - kFRO12M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 4), /*!< Attach FRO_12M to DAC2. */ - kPLL1_CLK0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 5), /*!< Attach PLL1_clk0 to DAC2. */ - kNONE_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 7), /*!< Attach NONE to DAC2. */ + kPLL0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 1), /*!< Attach PLL0 to DAC2. */ + kCLK_IN_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 2), /*!< Attach Clk_in to DAC2. */ + kFRO_HF_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 3), /*!< Attach FRO_HF to DAC2. */ + kFRO12M_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 4), /*!< Attach FRO_12M to DAC2. */ + kPLL1_CLK0_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 5), /*!< Attach PLL1_clk0 to DAC2. */ + kNONE_to_DAC2 = MUX_A(CM_DAC2CLKSEL, 7), /*!< Attach NONE to DAC2. */ - kPLL0_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 1), /*!< Attach PLL0 to FLEXSPI. */ - kFRO_HF_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 3), /*!< Attach FRO_HF to FLEXSPI. */ - kPLL1_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 5), /*!< Attach PLL1 to FLEXSPI. */ - kUSB_PLL_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 6), /*!< Attach USB PLL to FLEXSPI. */ - kNONE_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 15), /*!< Attach NONE to FLEXSPI. */ + kPLL0_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 1), /*!< Attach PLL0 to FLEXSPI. */ + kFRO_HF_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 3), /*!< Attach FRO_HF to FLEXSPI. */ + kPLL1_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 5), /*!< Attach PLL1 to FLEXSPI. */ + kUSB_PLL_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 6), /*!< Attach USB PLL to FLEXSPI. */ + kNONE_to_FLEXSPI = MUX_A(CM_FLEXSPICLKSEL, 15), /*!< Attach NONE to FLEXSPI. */ - kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ - kPLL1_CLK0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach pll1_clk0 to PLLCLKDIV. */ - kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach NONE to PLLCLKDIV. */ + kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ + kPLL1_CLK0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach pll1_clk0 to PLLCLKDIV. */ + kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach NONE to PLLCLKDIV. */ - kPLL0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLK. */ - kCLK_IN_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 2), /*!< Attach Clk_in to I3C0FCLK. */ - kFRO_HF_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLK. */ - kPLL1_CLK0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLK. */ - kUSB_PLL_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLK. */ - kNONE_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLK. */ + kPLL0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLK. */ + kCLK_IN_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 2), /*!< Attach Clk_in to I3C0FCLK. */ + kFRO_HF_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLK. */ + kPLL1_CLK0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLK. */ + kUSB_PLL_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLK. */ + kNONE_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLK. */ - kI3C0FCLK_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSTCSEL, 0), /*!< Attach I3C0FCLK to I3C0FCLKSTC. */ - kCLK_1M_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSTCSEL, 1), /*!< Attach CLK_1M to I3C0FCLKSTC. */ - kNONE_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSTCSEL, 7), /*!< Attach NONE to I3C0FCLKSTC. */ + kI3C0FCLK_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSTCSEL, 0), /*!< Attach I3C0FCLK to I3C0FCLKSTC. */ + kCLK_1M_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSTCSEL, 1), /*!< Attach CLK_1M to I3C0FCLKSTC. */ + kNONE_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSTCSEL, 7), /*!< Attach NONE to I3C0FCLKSTC. */ - kCLK_1M_to_I3C0FCLKS = MUX_A(CM_I3C0FCLKSSEL, 0), /*!< Attach CLK_1M to I3C0FCLKS. */ - kNONE_to_I3C0FCLKS = MUX_A(CM_I3C0FCLKSSEL, 7), /*!< Attach NONE to I3C0FCLKS. */ + kCLK_1M_to_I3C0FCLKS = MUX_A(CM_I3C0FCLKSSEL, 0), /*!< Attach CLK_1M to I3C0FCLKS. */ + kNONE_to_I3C0FCLKS = MUX_A(CM_I3C0FCLKSSEL, 7), /*!< Attach NONE to I3C0FCLKS. */ - kFRO12M_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 0), /*!< Attach FRO_12M to MICFILF. */ - kPLL0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 1), /*!< Attach PLL0 to MICFILF. */ - kCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 2), /*!< Attach Clk_in to MICFILF. */ - kFRO_HF_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 3), /*!< Attach FRO_HF to MICFILF. */ - kPLL1_CLK0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 4), /*!< Attach PLL1_clk0 to MICFILF. */ - kSAI0_MCLK_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 5), /*!< Attach SAI0_MCLK to MICFILF. */ - kUSB_PLL_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 6), /*!< Attach USB PLL to MICFILF. */ - kSAI1_MCLK_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 8), /*!< Attach SAI1_MCLK to MICFILF. */ - kNONE_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 15), /*!< Attach NONE to MICFILF. */ + kFRO12M_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 0), /*!< Attach FRO_12M to MICFILF. */ + kPLL0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 1), /*!< Attach PLL0 to MICFILF. */ + kCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 2), /*!< Attach Clk_in to MICFILF. */ + kFRO_HF_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 3), /*!< Attach FRO_HF to MICFILF. */ + kPLL1_CLK0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 4), /*!< Attach PLL1_clk0 to MICFILF. */ + kSAI0_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 5), /*!< Attach SAI0_MCLK to MICFILF. */ + kUSB_PLL_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 6), /*!< Attach USB PLL to MICFILF. */ + kSAI1_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 8), /*!< Attach SAI1_MCLK to MICFILF. */ + kNONE_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 15), /*!< Attach NONE to MICFILF. */ - kPLL0_to_ESPI = MUX_A(CM_ESPICLKSEL, 1), /*!< Attach PLL0 to ESPI. */ - kCLK_48M_to_ESPI = MUX_A(CM_ESPICLKSEL, 3), /*!< Attach CLK_48M to ESPI. */ - kPLL1_CLK0_to_ESPI = MUX_A(CM_ESPICLKSEL, 5), /*!< Attach PLL1_clk0 to ESPI. */ - kUSB_PLL_to_ESPI = MUX_A(CM_ESPICLKSEL, 6), /*!< Attach USB PLL to ESPI. */ - kNONE_to_ESPI = MUX_A(CM_ESPICLKSEL, 7), /*!< Attach NONE to ESPI. */ + kPLL0_to_ESPI = MUX_A(CM_ESPICLKSEL, 1), /*!< Attach PLL0 to ESPI. */ + kCLK_48M_to_ESPI = MUX_A(CM_ESPICLKSEL, 3), /*!< Attach CLK_48M to ESPI. */ + kPLL1_CLK0_to_ESPI = MUX_A(CM_ESPICLKSEL, 5), /*!< Attach PLL1_clk0 to ESPI. */ + kUSB_PLL_to_ESPI = MUX_A(CM_ESPICLKSEL, 6), /*!< Attach USB PLL to ESPI. */ + kNONE_to_ESPI = MUX_A(CM_ESPICLKSEL, 7), /*!< Attach NONE to ESPI. */ - kPLL0_to_USDHC = MUX_A(CM_USDHCCLKSEL, 1), /*!< Attach PLL0 to uSDHC. */ - kCLK_IN_to_USDHC = MUX_A(CM_USDHCCLKSEL, 2), /*!< Attach Clk_in to uSDHC. */ - kFRO_HF_to_USDHC = MUX_A(CM_USDHCCLKSEL, 3), /*!< Attach FRO_HF to uSDHC. */ - kFRO12M_to_USDHC = MUX_A(CM_USDHCCLKSEL, 4), /*!< Attach FRO_12M to uSDHC. */ - kPLL1_CLK1_to_USDHC = MUX_A(CM_USDHCCLKSEL, 5), /*!< Attach pll1_clk1 to uSDHC. */ - kUSB_PLL_to_USDHC = MUX_A(CM_USDHCCLKSEL, 6), /*!< Attach USB PLL to uSDHC. */ - kNONE_to_USDHC = MUX_A(CM_USDHCCLKSEL, 7), /*!< Attach NONE to uSDHC. */ + kPLL0_to_USDHC = MUX_A(CM_USDHCCLKSEL, 1), /*!< Attach PLL0 to uSDHC. */ + kCLK_IN_to_USDHC = MUX_A(CM_USDHCCLKSEL, 2), /*!< Attach Clk_in to uSDHC. */ + kFRO_HF_to_USDHC = MUX_A(CM_USDHCCLKSEL, 3), /*!< Attach FRO_HF to uSDHC. */ + kFRO12M_to_USDHC = MUX_A(CM_USDHCCLKSEL, 4), /*!< Attach FRO_12M to uSDHC. */ + kPLL1_CLK1_to_USDHC = MUX_A(CM_USDHCCLKSEL, 5), /*!< Attach pll1_clk1 to uSDHC. */ + kUSB_PLL_to_USDHC = MUX_A(CM_USDHCCLKSEL, 6), /*!< Attach USB PLL to uSDHC. */ + kNONE_to_USDHC = MUX_A(CM_USDHCCLKSEL, 7), /*!< Attach NONE to uSDHC. */ - kPLL0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 1), /*!< Attach PLL0 to FLEXIO. */ - kCLK_IN_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 2), /*!< Attach Clk_in to FLEXIO. */ - kFRO_HF_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 3), /*!< Attach FRO_HF to FLEXIO. */ - kFRO12M_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 4), /*!< Attach FRO_12M to FLEXIO. */ - kPLL1_CLK0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 5), /*!< Attach pll1_clk0 to FLEXIO. */ - kUSB_PLL_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 6), /*!< Attach USB PLL to FLEXIO. */ - kNONE_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 7), /*!< Attach NONE to FLEXIO. */ + kPLL0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 1), /*!< Attach PLL0 to FLEXIO. */ + kCLK_IN_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 2), /*!< Attach Clk_in to FLEXIO. */ + kFRO_HF_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 3), /*!< Attach FRO_HF to FLEXIO. */ + kFRO12M_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 4), /*!< Attach FRO_12M to FLEXIO. */ + kPLL1_CLK0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 5), /*!< Attach pll1_clk0 to FLEXIO. */ + kUSB_PLL_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 6), /*!< Attach USB PLL to FLEXIO. */ + kNONE_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 7), /*!< Attach NONE to FLEXIO. */ - kPLL0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN0. */ - kCLK_IN_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN0. */ - kFRO_HF_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN0. */ - kPLL1_CLK0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN0. */ - kUSB_PLL_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN0. */ - kNONE_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 7), /*!< Attach NONE to FLEXCAN0. */ + kPLL0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN0. */ + kCLK_IN_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN0. */ + kFRO_HF_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN0. */ + kPLL1_CLK0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN0. */ + kUSB_PLL_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN0. */ + kNONE_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 7), /*!< Attach NONE to FLEXCAN0. */ - kPLL0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN1. */ - kCLK_IN_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN1. */ - kFRO_HF_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN1. */ - kPLL1_CLK0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN1. */ - kUSB_PLL_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN1. */ - kNONE_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 7), /*!< Attach NONE to FLEXCAN1. */ + kPLL0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN1. */ + kCLK_IN_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN1. */ + kFRO_HF_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN1. */ + kPLL1_CLK0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN1. */ + kUSB_PLL_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN1. */ + kNONE_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 7), /*!< Attach NONE to FLEXCAN1. */ - kNONE_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 0), /*!< Attach NONE to ENETRMII. */ - kPLL0_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 1), /*!< Attach PLL0 to ENETRMII. */ - kCLK_IN_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 2), /*!< Attach Clk_in to ENETRMII. */ - kPLL1_CLK0_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 5), /*!< Attach pll1_clk0 to ENETRMII. */ + kNONE_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 0), /*!< Attach NONE to ENETRMII. */ + kPLL0_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 1), /*!< Attach PLL0 to ENETRMII. */ + kCLK_IN_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 2), /*!< Attach Clk_in to ENETRMII. */ + kPLL1_CLK0_to_ENETRMII = MUX_A(CM_ENETRMIICLKSEL, 5), /*!< Attach pll1_clk0 to ENETRMII. */ kPLL0_to_ENETPTPREF = MUX_A(CM_ENETPTPREFCLKSEL, 1), /*!< Attach PLL0 to ENETPTPREF. */ kCLK_IN_to_ENETPTPREF = MUX_A(CM_ENETPTPREFCLKSEL, 2), /*!< Attach Clk_in to ENETPTPREF. */ @@ -1044,110 +933,110 @@ typedef enum _clock_attach_id kPLL1_CLK1_to_ENETPTPREF = MUX_A(CM_ENETPTPREFCLKSEL, 5), /*!< Attach pll1_clk1 to ENETPTPREF. */ kNONE_to_ENETPTPREF = MUX_A(CM_ENETPTPREFCLKSEL, 7), /*!< Attach NONE to ENETPTPREF. */ - kCLK_16K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 0), /*!< Attach clk_16k[2] to EWM0. */ - kXTAL32K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 1), /*!< Attach xtal32k[2] to EWM0. */ + kCLK_16K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 0), /*!< Attach clk_16k[2] to EWM0. */ + kXTAL32K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 1), /*!< Attach xtal32k[2] to EWM0. */ - kCLK_16K2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 0), /*!< Attach FRO16K clock 2 to WDT1. */ - kFRO_HF_DIV_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 1), /*!< Attach FRO_HF_DIV to WDT1. */ - kCLK_1M_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 2), /*!< Attach clk_1m to WDT1. */ - kNONE_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 3), /*!< Attach NONE to WDT1. */ + kCLK_16K2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 0), /*!< Attach FRO16K clock 2 to WDT1. */ + kFRO_HF_DIV_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 1), /*!< Attach FRO_HF_DIV to WDT1. */ + kCLK_1M_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 2), /*!< Attach clk_1m to WDT1. */ + kCLK_1M_2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 3), /*!< Attach clk_1m to WDT1. */ - kCLK_16K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach clk_16k[2] to OSTIMER. */ - kXTAL32K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach xtal32k[2] to OSTIMER. */ - kCLK_1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach clk_1m to OSTIMER. */ - kNONE_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach NONE to OSTIMER. */ + kCLK_16K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach clk_16k[2] to OSTIMER. */ + kXTAL32K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach xtal32k[2] to OSTIMER. */ + kCLK_1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach clk_1m to OSTIMER. */ + kNONE_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach NONE to OSTIMER. */ - kPLL0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 1), /*!< Attach PLL0 to CMP0F. */ - kFRO_HF_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 2), /*!< Attach FRO_HF to CMP0F. */ - kFRO12M_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 3), /*!< Attach FRO_12M to CMP0F. */ - kCLK_IN_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 4), /*!< Attach Clk_in to CMP0F. */ - kPLL1_CLK0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0F. */ - kUSB_PLL_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 6), /*!< Attach USB PLL to CMP0F. */ - kNONE_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 7), /*!< Attach NONE to CMP0F. */ + kPLL0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 1), /*!< Attach PLL0 to CMP0F. */ + kFRO_HF_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 2), /*!< Attach FRO_HF to CMP0F. */ + kFRO12M_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 3), /*!< Attach FRO_12M to CMP0F. */ + kCLK_IN_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 4), /*!< Attach Clk_in to CMP0F. */ + kPLL1_CLK0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0F. */ + kUSB_PLL_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 6), /*!< Attach USB PLL to CMP0F. */ + kNONE_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 7), /*!< Attach NONE to CMP0F. */ - kPLL0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 1), /*!< Attach PLL0 to CMP0RR. */ - kFRO_HF_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 2), /*!< Attach FRO_HF to CMP0RR. */ - kFRO12M_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 3), /*!< Attach FRO_12M to CMP0RR. */ - kCLK_IN_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 4), /*!< Attach Clk_in to CMP0RR. */ - kPLL1_CLK0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0RR. */ - kUSB_PLL_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 6), /*!< Attach USB PLL to CMP0RR. */ - kNONE_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 7), /*!< Attach NONE to CMP0RR. */ + kPLL0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 1), /*!< Attach PLL0 to CMP0RR. */ + kFRO_HF_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 2), /*!< Attach FRO_HF to CMP0RR. */ + kFRO12M_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 3), /*!< Attach FRO_12M to CMP0RR. */ + kCLK_IN_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 4), /*!< Attach Clk_in to CMP0RR. */ + kPLL1_CLK0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0RR. */ + kUSB_PLL_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 6), /*!< Attach USB PLL to CMP0RR. */ + kNONE_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 7), /*!< Attach NONE to CMP0RR. */ - kPLL0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 1), /*!< Attach PLL0 to CMP1F. */ - kFRO_HF_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 2), /*!< Attach FRO_HF to CMP1F. */ - kFRO12M_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 3), /*!< Attach FRO_12M to CMP1F. */ - kCLK_IN_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 4), /*!< Attach Clk_in to CMP1F. */ - kPLL1_CLK0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1F. */ - kUSB_PLL_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 6), /*!< Attach USB PLL to CMP1F. */ - kNONE_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 7), /*!< Attach NONE to CMP1F. */ + kPLL0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 1), /*!< Attach PLL0 to CMP1F. */ + kFRO_HF_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 2), /*!< Attach FRO_HF to CMP1F. */ + kFRO12M_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 3), /*!< Attach FRO_12M to CMP1F. */ + kCLK_IN_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 4), /*!< Attach Clk_in to CMP1F. */ + kPLL1_CLK0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1F. */ + kUSB_PLL_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 6), /*!< Attach USB PLL to CMP1F. */ + kNONE_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 7), /*!< Attach NONE to CMP1F. */ - kPLL0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 1), /*!< Attach PLL0 to CMP1RR. */ - kFRO_HF_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 2), /*!< Attach FRO_HF to CMP1RR. */ - kFRO12M_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 3), /*!< Attach FRO_12M to CMP1RR. */ - kCLK_IN_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 4), /*!< Attach Clk_in to CMP1RR. */ - kPLL1_CLK0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1RR. */ - kUSB_PLL_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 6), /*!< Attach USB PLL to CMP1RR. */ - kNONE_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 7), /*!< Attach NONE to CMP1RR. */ + kPLL0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 1), /*!< Attach PLL0 to CMP1RR. */ + kFRO_HF_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 2), /*!< Attach FRO_HF to CMP1RR. */ + kFRO12M_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 3), /*!< Attach FRO_12M to CMP1RR. */ + kCLK_IN_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 4), /*!< Attach Clk_in to CMP1RR. */ + kPLL1_CLK0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1RR. */ + kUSB_PLL_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 6), /*!< Attach USB PLL to CMP1RR. */ + kNONE_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 7), /*!< Attach NONE to CMP1RR. */ - kPLL0_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 1), /*!< Attach PLL0 to CMP2F. */ - kFRO_HF_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 2), /*!< Attach FRO_HF to CMP2F. */ - kFRO12M_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 3), /*!< Attach FRO_12M to CMP2F. */ - kCLK_IN_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 4), /*!< Attach Clk_in to CMP2F. */ - kPLL1_CLK0_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP2F. */ - kUSB_PLL_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 6), /*!< Attach USB PLL to CMP2F. */ - kNONE_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 7), /*!< Attach NONE to CMP2F. */ + kPLL0_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 1), /*!< Attach PLL0 to CMP2F. */ + kFRO_HF_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 2), /*!< Attach FRO_HF to CMP2F. */ + kFRO12M_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 3), /*!< Attach FRO_12M to CMP2F. */ + kCLK_IN_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 4), /*!< Attach Clk_in to CMP2F. */ + kPLL1_CLK0_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP2F. */ + kUSB_PLL_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 6), /*!< Attach USB PLL to CMP2F. */ + kNONE_to_CMP2F = MUX_A(CM_CMP2FCLKSEL, 7), /*!< Attach NONE to CMP2F. */ - kPLL0_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 1), /*!< Attach PLL0 to CMP2RR. */ - kFRO_HF_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 2), /*!< Attach FRO_HF to CMP2RR. */ - kFRO12M_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 3), /*!< Attach FRO_12M to CMP2RR. */ - kCLK_IN_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 4), /*!< Attach Clk_in to CMP2RR. */ - kPLL1_CLK0_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP2RR. */ - kUSB_PLL_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 6), /*!< Attach USB PLL to CMP2RR. */ - kNONE_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 7), /*!< Attach NONE to CMP2RR. */ + kPLL0_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 1), /*!< Attach PLL0 to CMP2RR. */ + kFRO_HF_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 2), /*!< Attach FRO_HF to CMP2RR. */ + kFRO12M_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 3), /*!< Attach FRO_12M to CMP2RR. */ + kCLK_IN_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 4), /*!< Attach Clk_in to CMP2RR. */ + kPLL1_CLK0_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP2RR. */ + kUSB_PLL_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 6), /*!< Attach USB PLL to CMP2RR. */ + kNONE_to_CMP2RR = MUX_A(CM_CMP2RRCLKSEL, 7), /*!< Attach NONE to CMP2RR. */ - kPLL0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 1), /*!< Attach PLL0 to SAI0. */ - kCLK_IN_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 2), /*!< Attach Clk_in to SAI0. */ - kFRO_HF_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 3), /*!< Attach FRO_HF to SAI0. */ - kPLL1_CLK0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI0. */ - kUSB_PLL_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 6), /*!< Attach USB PLL to SAI0. */ - kNONE_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 7), /*!< Attach NONE to SAI0. */ + kPLL0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 1), /*!< Attach PLL0 to SAI0. */ + kCLK_IN_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 2), /*!< Attach Clk_in to SAI0. */ + kFRO_HF_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 3), /*!< Attach FRO_HF to SAI0. */ + kPLL1_CLK0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI0. */ + kUSB_PLL_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 6), /*!< Attach USB PLL to SAI0. */ + kNONE_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 7), /*!< Attach NONE to SAI0. */ - kPLL0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 1), /*!< Attach PLL0 to SAI1. */ - kCLK_IN_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 2), /*!< Attach Clk_in to SAI1. */ - kFRO_HF_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 3), /*!< Attach FRO_HF to SAI1. */ - kPLL1_CLK0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI1. */ - kUSB_PLL_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 6), /*!< Attach USB PLL to SAI1. */ - kNONE_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 7), /*!< Attach NONE to SAI1. */ + kPLL0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 1), /*!< Attach PLL0 to SAI1. */ + kCLK_IN_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 2), /*!< Attach Clk_in to SAI1. */ + kFRO_HF_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 3), /*!< Attach FRO_HF to SAI1. */ + kPLL1_CLK0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI1. */ + kUSB_PLL_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 6), /*!< Attach USB PLL to SAI1. */ + kNONE_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 7), /*!< Attach NONE to SAI1. */ - kPLL0_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 1), /*!< Attach PLL0 to EMVSIM0. */ - kCLK_IN_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 2), /*!< Attach Clk_in to EMVSIM0. */ - kFRO_HF_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 3), /*!< Attach FRO_HF to EMVSIM0. */ - kFRO12M_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 4), /*!< Attach FRO_12M to EMVSIM0. */ - kPLL1_CLK0_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 5), /*!< Attach PLL1_clk0 to EMVSIM0. */ - kNONE_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 7), /*!< Attach NONE to EMVSIM0. */ + kPLL0_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 1), /*!< Attach PLL0 to EMVSIM0. */ + kCLK_IN_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 2), /*!< Attach Clk_in to EMVSIM0. */ + kFRO_HF_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 3), /*!< Attach FRO_HF to EMVSIM0. */ + kFRO12M_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 4), /*!< Attach FRO_12M to EMVSIM0. */ + kPLL1_CLK0_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 5), /*!< Attach PLL1_clk0 to EMVSIM0. */ + kNONE_to_EMVSIM0 = MUX_A(CM_EMVSIM0CLKSEL, 7), /*!< Attach NONE to EMVSIM0. */ - kPLL0_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 1), /*!< Attach PLL0 to EMVSIM1. */ - kCLK_IN_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 2), /*!< Attach Clk_in to EMVSIM1. */ - kFRO_HF_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 3), /*!< Attach FRO_HF to EMVSIM1. */ - kFRO12M_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 4), /*!< Attach FRO_12M to EMVSIM1. */ - kPLL1_CLK0_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 5), /*!< Attach PLL1_clk0 to EMVSIM1. */ - kNONE_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 7), /*!< Attach NONE to EMVSIM1. */ + kPLL0_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 1), /*!< Attach PLL0 to EMVSIM1. */ + kCLK_IN_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 2), /*!< Attach Clk_in to EMVSIM1. */ + kFRO_HF_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 3), /*!< Attach FRO_HF to EMVSIM1. */ + kFRO12M_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 4), /*!< Attach FRO_12M to EMVSIM1. */ + kPLL1_CLK0_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 5), /*!< Attach PLL1_clk0 to EMVSIM1. */ + kNONE_to_EMVSIM1 = MUX_A(CM_EMVSIM1CLKSEL, 7), /*!< Attach NONE to EMVSIM1. */ - kPLL0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLK. */ - kCLK_IN_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 2), /*!< Attach Clk_in to I3C1FCLK. */ - kFRO_HF_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLK. */ - kPLL1_CLK0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLK. */ - kUSB_PLL_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLK. */ - kNONE_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLK. */ + kPLL0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLK. */ + kCLK_IN_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 2), /*!< Attach Clk_in to I3C1FCLK. */ + kFRO_HF_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLK. */ + kPLL1_CLK0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLK. */ + kUSB_PLL_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLK. */ + kNONE_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLK. */ - kI3C1FCLK_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSTCSEL, 0), /*!< Attach I3C1FCLK to I3C1FCLKSTC. */ - kCLK_1M_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSTCSEL, 1), /*!< Attach CLK_1M to I3C1FCLKSTC. */ - kNONE_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSTCSEL, 7), /*!< Attach NONE to I3C1FCLKSTC. */ + kI3C1FCLK_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSTCSEL, 0), /*!< Attach I3C1FCLK to I3C1FCLKSTC. */ + kCLK_1M_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSTCSEL, 1), /*!< Attach CLK_1M to I3C1FCLKSTC. */ + kNONE_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSTCSEL, 7), /*!< Attach NONE to I3C1FCLKSTC. */ - kCLK_1M_to_I3C1FCLKS = MUX_A(CM_I3C1FCLKSSEL, 0), /*!< Attach CLK_1M to I3C1FCLKS. */ - kNONE_to_I3C1FCLKS = MUX_A(CM_I3C1FCLKSSEL, 7), /*!< Attach NONE to I3C1FCLKS. */ + kCLK_1M_to_I3C1FCLKS = MUX_A(CM_I3C1FCLKSSEL, 0), /*!< Attach CLK_1M to I3C1FCLKS. */ + kNONE_to_I3C1FCLKS = MUX_A(CM_I3C1FCLKSSEL, 7), /*!< Attach NONE to I3C1FCLKS. */ - kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ } clock_attach_id_t; @@ -1242,16 +1131,16 @@ typedef enum _clock_ctrl_enable kCLOCK_PLU_DEGLITCH_CLK_ENA = SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK, /*!< Enables clocks FRO_1MHz and FRO_12MHz for PLU deglitching. */ kCLOCK_FRO1MHZ_CLK_ENA = - SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK, /*!< Enables FRO_1MHz clock for clock muxing in clock gen. */ + SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK, /*!< Enables FRO_1MHz clock for clock muxing in clock gen. */ kCLOCK_CLKIN_ENA = - SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK, /*!< Enables clk_in clock for MICD, EMVSIM0/1, CAN0/1, I3C0/1, SAI0/1, SINC - Filter (SINC), TSI, USBFS, SCT, uSDHC, clkout.. */ + SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK, /*!< Enables clk_in clock for MICD, EMVSIM0/1, CAN0/1, I3C0/1, SAI0/1, SINC + Filter (SINC), TSI, USBFS, SCT, uSDHC, clkout.. */ kCLOCK_FRO_HF_ENA = SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK, /*!< Enables FRO HF clock for the Frequency Measure module. */ kCLOCK_FRO12MHZ_ENA = SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK, /*!< Enables the FRO_12MHz clock for the Flash, LPTIMER0/1, and Frequency Measurement modules. */ kCLOCK_FRO1MHZ_ENA = - SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK, /*!< Enables the FRO_1MHz clock for RTC module and for UTICK. */ + SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK, /*!< Enables the FRO_1MHz clock for RTC module and for UTICK. */ kCLOCK_CLKIN_ENA_FM_USBH_LPT = SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK, /*!< Enables the clk_in clock for the Frequency Measurement, USB HS and LPTIMER0/1 modules. */ @@ -1307,8 +1196,8 @@ typedef struct _firc_trim_config firc_trim_src_t trimSrc; /*!< Trim source. */ uint16_t trimDiv; /*!< Divider of SOSC. */ - uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ - uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ } firc_trim_config_t; /*! @@ -1345,8 +1234,8 @@ typedef struct _sirc_trim_config sirc_trim_src_t trimSrc; /*!< Trim source. */ uint16_t trimDiv; /*!< Divider of SOSC. */ - uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ - uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ } sirc_trim_config_t; /*! @@ -1354,8 +1243,8 @@ typedef struct _sirc_trim_config */ typedef enum _scg_sosc_monitor_mode { - kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ - kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */ + kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */ kSCG_SysOscMonitorReset = SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */ } scg_sosc_monitor_mode_t; @@ -1365,8 +1254,8 @@ typedef enum _scg_sosc_monitor_mode */ typedef enum _scg_rosc_monitor_mode { - kSCG_RoscMonitorDisable = 0U, /*!< Monitor disabled. */ - kSCG_RoscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */ + kSCG_RoscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_RoscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */ kSCG_RoscMonitorReset = SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */ } scg_rosc_monitor_mode_t; @@ -1376,8 +1265,8 @@ typedef enum _scg_rosc_monitor_mode */ typedef enum _scg_upll_monitor_mode { - kSCG_UpllMonitorDisable = 0U, /*!< Monitor disabled. */ - kSCG_UpllMonitorInt = SCG_UPLLCSR_UPLLCM_MASK, /*!< Interrupt when the UPLL error is detected. */ + kSCG_UpllMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_UpllMonitorInt = SCG_UPLLCSR_UPLLCM_MASK, /*!< Interrupt when the UPLL error is detected. */ kSCG_UpllMonitorReset = SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK /*!< Reset when the UPLL error is detected. */ } scg_upll_monitor_mode_t; @@ -1387,8 +1276,8 @@ typedef enum _scg_upll_monitor_mode */ typedef enum _scg_pll0_monitor_mode { - kSCG_Pll0MonitorDisable = 0U, /*!< Monitor disabled. */ - kSCG_Pll0MonitorInt = SCG_APLLCSR_APLLCM_MASK, /*!< Interrupt when the PLL0 Clock error is detected. */ + kSCG_Pll0MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll0MonitorInt = SCG_APLLCSR_APLLCM_MASK, /*!< Interrupt when the PLL0 Clock error is detected. */ kSCG_Pll0MonitorReset = SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detected. */ } scg_pll0_monitor_mode_t; @@ -1398,8 +1287,8 @@ typedef enum _scg_pll0_monitor_mode */ typedef enum _scg_pll1_monitor_mode { - kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */ - kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */ + kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */ kSCG_Pll1MonitorReset = SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the PLL1 Clock error is detected. */ } scg_pll1_monitor_mode_t; @@ -1467,18 +1356,28 @@ typedef enum _vbat_osc_fine_adjustment_value */ typedef struct _vbat_osc_config { - bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */ + bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */ bool enableCrystalOscillatorBypass; /*!< enable/disable the crystal oscillator bypass. */ - vbat_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank, - only useful when the internal capacitance bank is enabled. */ + vbat_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank, + only useful when the internal capacitance bank is enabled. */ vbat_osc_extal_cap_t extalCap; /*!< The internal capacitance for the OSC EXTAL pin from the capacitor bank, only useful when the internal capacitance bank is enabled. */ vbat_osc_coarse_adjustment_value_t - coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */ + coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */ } vbat_osc_config_t; +/*! + * @brief The active run mode (voltage level). + */ +typedef enum _run_mode +{ + kMD_Mode, /*!< Midvoltage (1.0 V). */ + kSD_Mode, /*!< Normal voltage (1.1 V). */ + kOD_Mode, /*!< Overdrive voltage (1.2 V). */ +} run_mode_t; + /******************************************************************************* * API ******************************************************************************/ @@ -1494,10 +1393,23 @@ extern "C" { */ static inline void CLOCK_EnableClock(clock_ip_name_t clk) { - if (clk == kCLOCK_None) - return; - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x40U; + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x80U; + } + else + { + SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); + } } /** @@ -1507,10 +1419,29 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk) */ static inline void CLOCK_DisableClock(clock_ip_name_t clk) { - if (clk == kCLOCK_None) - return; - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x20U; + } + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x40U; + } + } + else + { + SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); + } } /** @@ -1528,6 +1459,13 @@ status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); */ status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + /** * @brief Initialize the XTAL32/EXTAL32 input clock to given frequency. * @param id : OSC 32 kHz output clock to specified modules, it should use osc32k_clk_gate_id_t value @@ -1614,6 +1552,15 @@ void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode); */ void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config); +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access + * time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode); + /** * @brief Configure the clock selection muxes. * @param connection : Clock to be configured. @@ -1664,6 +1611,11 @@ void CLOCK_SetupClockCtrl(uint32_t mask); */ uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of main + * @return Frequency of the main + */ +uint32_t CLOCK_GetMainClkFreq(void); + /*! @brief Return Frequency of core * @return Frequency of the core */ @@ -1888,8 +1840,8 @@ __STATIC_INLINE bool CLOCK_IsPLL0Locked(void) return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); } -/*! @brief Check if PLL1 is locked or not - * @return true if the PLL1 is locked, false if not locked +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked */ __STATIC_INLINE bool CLOCK_IsPLL1Locked(void) { @@ -2085,6 +2037,12 @@ void CLOCK_DisableUsbhsPhyPllClock(void); */ bool CLOCK_EnableUsbhsClock(void); +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c index 25ba867682..4e388d9e73 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -107,6 +107,7 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config) base->RPC = reg; } +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) /*! * brief Power off the selected system SRAM always. * @@ -119,10 +120,11 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config) */ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask) { - uint32_t reg = base->SRAMDIS[0]; + uint32_t reg = base->SRAMDIS[0]; + uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays); - reg &= ~CMC_SRAMDIS_DIS_MASK; - reg |= CMC_SRAMDIS_DIS(mask); + reg &= ~((uint32_t)kCMC_AllSramArrays); + reg |= CMC_SRAMDIS_DIS(maskToSet); base->SRAMDIS[0] = reg; } @@ -137,13 +139,36 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask) */ void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) { - uint32_t reg = base->SRAMRET[0]; + uint32_t reg = base->SRAMRET[0]; + uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays); - reg &= ~CMC_SRAMRET_RET_MASK; - reg |= CMC_SRAMRET_RET(mask); + reg &= ~((uint32_t)kCMC_AllSramArrays); + reg |= CMC_SRAMRET_RET(maskToSet); base->SRAMRET[0] = reg; } +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param doze true: Flash is disabled while core is sleeping + * false: No effect. + * param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)); + base->FLASHCR = reg; +} +#else /*! * brief Configs the low power mode of the on-chip flash memory. * @@ -169,6 +194,7 @@ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable) (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U)); base->FLASHCR = reg; } +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ /*! * brief Prepares to enter stop modes. @@ -233,8 +259,11 @@ void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMo void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config) { assert(config != NULL); + +#if (CMC_PMCTRL_COUNT > 1U) /* The WAKE domain must never be configured to a lower power mode compared with main power mode. */ assert(config->wake_domain <= config->main_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode) { @@ -243,7 +272,9 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf CMC_SetClockMode(base, config->clock_mode); CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode); +#if (CMC_PMCTRL_COUNT > 1U) CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ /* Before executing WFI instruction read back the last register to * ensure all registers writes have completed. */ @@ -258,16 +289,22 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf /* Note: unlock the register if this API will be reinvoked later. */ CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); CMC_SetMAINPowerMode(base, config->main_domain); +#if (CMC_PMCTRL_COUNT > 1U) CMC_SetWAKEPowerMode(base, config->wake_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ /* Before execute WFI instruction read back the last register to * ensure all registers writes have completed. */ +#if (CMC_PMCTRL_COUNT > 1U) if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain)) { +#endif /* (CMC_PMCTRL_COUNT > 1U) */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __DSB(); __WFI(); __ISB(); +#if (CMC_PMCTRL_COUNT > 1U) } +#endif /* (CMC_PMCTRL_COUNT > 1U) */ } } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h index b97812007b..6dbe8e974b 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h @@ -1,11 +1,11 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CMC_H_ -#define _FSL_CMC_H_ +#ifndef FSL_CMC_H_ +#define FSL_CMC_H_ #include "fsl_common.h" /*! @@ -17,8 +17,8 @@ ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief CMC driver version 2.0.0. */ -#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief CMC driver version 2.2.2. */ +#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /* @} */ /*! @@ -34,6 +34,8 @@ enum _cmc_power_mode_protection /*! * @brief Wake up sources from the previous low power mode entry. + * + * @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family. */ enum _cmc_wakeup_sources { @@ -59,14 +61,25 @@ enum _cmc_system_reset_interrupt_enable Reset interrupt enable. */ kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK, /*!< Windowed Watchdog 0 reset interrupt enable. */ - kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */ - kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */ - kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */ - kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */ + kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */ + kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */ +#if defined(CMC_SRIE_CPU1_MASK) + kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */ +#endif /* CMC_SRIE_CPU1_MASK */ +#if defined(CMC_SRIE_ADVC_MASK) + kCMC_AdvcResetInterruptEnable = CMC_SRIE_ADVC_MASK, /*!< ADVC Reset interrupt enable. */ +#endif /* CMC_SRIE_ADVC_MASK */ +#if defined(CMC_SRIE_VBAT_MASK) + kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */ +#endif /* CMC_SRIE_VBAT_MASK */ +#if defined(CMC_SRIE_WWDT1_MASK) kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK, /*!< Windowed Watchdog 1 reset interrupt enable. */ +#endif /* CMC_SRIE_WWDT1_MASK */ kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */ +#if defined(CMC_SRIE_CDOG1_MASK) kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */ +#endif /* CMC_SRIE_CDOG1_MASK */ }; /*! @@ -81,13 +94,25 @@ enum _cmc_system_reset_interrupt_flag kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK, /*!< Windowned Watchdog 0 Reset interrupt flag. */ kCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */ kCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */ - kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */ - kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */ +#if defined(CMC_SRIF_CPU1_MASK) + kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */ +#endif /* CMC_SRIF_CPU1_MASK */ +#if defined(CMC_SRIF_ADVC_MASK) + kCMC_AdvcResetInterruptFlag = CMC_SRIF_ADVC_MASK, /*!< ADVC Reset interrupt flag. */ +#endif /* CMC_SRIF_ADVC_MASK */ +#if defined(CMC_SRIF_VBAT_MASK) + kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */ +#endif /* CMC_SRIF_VBAT_MASK */ +#if defined(CMC_SRIF_WWDT1_MASK) kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK, /*!< Windowned Watchdog 1 Reset interrupt flag. */ - kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */ - kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */ +#endif /* CMC_SRIF_WWDT1_MASK */ + kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */ +#if defined(CMC_SRIF_CDOG1_MASK) + kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */ +#endif /* CMC_SRIF_CDOG1_MASK */ }; +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) /*! * @brief CMC System SRAM arrays low power mode enable enumeration. */ @@ -114,7 +139,13 @@ enum _cmc_system_sram_arrays kCMC_PQ = 1UL << 27UL, /*!< Used to control PQ. */ kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */ kCMC_FlexSPI = 1UL << 29UL, /*!< Used to control FlexSPI. */ + + kCMC_AllSramArrays = (kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | + kCMC_RAMD1 | kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | + kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | + kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI), /*!< Mask of all System SRAM arrays. */ }; +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ /*! * @brief System reset sources enumeration. @@ -137,14 +168,29 @@ enum _cmc_system_reset_sources kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */ kCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */ kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */ - kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */ - kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */ +#if defined(CMC_SRS_CPU1_MASK) + kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */ +#endif /* CMC_SRS_CPU1_MASK */ +#if defined(CMC_SRS_ADVC_MASK) + kCMC_AdvcReset = CMC_SRS_ADVC_MASK, /*!< The reset caused by ADVC critical reset. */ +#endif /* CMC_SRS_ADVC_MASK */ +#if defined(CMC_SRS_VBAT_MASK) + kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */ +#endif /* CMC_SRS_VBAT_MASK */ +#if defined(CMC_SRS_WWDT1_MASK) kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK, /*!< The reset caused by the Windowed WatchDog 1 timeout. */ - kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */ - kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */ - kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */ +#endif /* CMC_SRS_WWDT1_MASK */ + kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */ +#if defined(CMC_SRS_CDOG1_MASK) + kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */ +#endif /* CMC_SRS_CDOG1_MASK */ + kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */ +#if defined(CMC_SRS_SECVIO_MASK) kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */ - kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */ +#endif /* CMC_SRS_SECVIO_MASK */ +#if defined(CMC_SRS_TAMPER_MASK) + kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */ +#endif /* CMC_SRS_TAMPER_MASK */ }; /*! @@ -197,7 +243,9 @@ typedef struct _cmc_power_domain_config { cmc_clock_mode_t clock_mode; /*!< Clock mode for each power domain. */ cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */ +#if (CMC_PMCTRL_COUNT > 1U) cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */ +#endif /* (CMC_PMCTRL_COUNT > 1U) */ } cmc_power_domain_config_t; /******************************************************************************* @@ -335,8 +383,9 @@ static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mas base->SSRS = mask; } +#if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) /*! - * @brief Gets the number of reset sequences completed since the last WAKE Cold Reset. + * @brief Gets the number of reset sequences completed since the last Cold Reset. * * @param base CMC peripheral base address. * @return The number of reset sequences. @@ -345,6 +394,7 @@ static inline uint8_t CMC_GetResetCount(CMC_Type *base) { return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK); } +#endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */ /* @} */ @@ -422,6 +472,7 @@ static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base) return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK); } +#if (CMC_PMCTRL_COUNT > 1U) /*! * @brief Configure entry into low power mode for the WAKE Power domain. * @@ -451,6 +502,7 @@ static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base) { return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK); } +#endif /* CMC_PMCTRL_COUNT > 1U */ /* @} */ @@ -626,6 +678,7 @@ static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert) * @{ */ +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG) /*! * @brief Gets the status information written by the BootROM. * @@ -649,7 +702,9 @@ static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue) { base->BSR = CMC_BSR_STAT(statValue); } +#endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */ +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG) /*! * @brief Check if BootROM status and lock registers is writtable. * @@ -682,9 +737,11 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base) { base->BLR = CMC_BLR_LOCK(0x2U); } +#endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */ /* @} */ +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) /*! * @name System SRAM Configuration. * @{ @@ -693,10 +750,12 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base) /*! * @brief Power off the selected system SRAM always. * - * This function power off the selected system SRAM always. The SRAM arrays should + * @note This function power off the selected system SRAM always. The SRAM arrays should * not be accessed while they are shut down. SRAM array contents are not retained * if they are powered off. * + * @note Once invoked, the previous settings will be overwritten. + * * @param base CMC peripheral base address. * @param mask Bitmap of the SRAM arrays to be powered off all modes. * See @ref _cmc_system_sram_arrays for details. @@ -707,6 +766,8 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask); /*! * @brief Power on SRAM during all mode. * + * @note Once invoked, the previous settings will be overwritten. + * * @param base CMC peripheral base address. * @param mask Bitmap of the SRAM arrays to be powered on all modes. * See @ref _cmc_system_sram_arrays for details. @@ -747,11 +808,27 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) } /* @} */ +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ /*! * @name Flash Low Power Mode configuration. * @{ */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable); +#else /*! * @brief Configs the low power mode of the on-chip flash memory. * @@ -766,7 +843,7 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) * false: No effect. */ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable); - +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ /* @} */ /*! @@ -849,4 +926,4 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf #endif /* __cplusplus */ /*! @}*/ -#endif /* _FSL_CMC_H_ */ +#endif /* FSL_CMC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h index d2ae4209ef..e6d5cce719 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ #include #include @@ -57,12 +57,13 @@ #define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) -/*@}*/ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*! @} */ -/* Debug console type definition. */ +/*! @name Debug console type definition. */ +/*! @{ */ #define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ #define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ @@ -74,6 +75,7 @@ #define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ #define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ #define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ +/*! @} */ /*! @brief Status group numbers. */ enum _status_groups @@ -156,6 +158,9 @@ enum _status_groups kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */ + kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */ + kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ @@ -166,6 +171,7 @@ enum _status_groups kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ @@ -188,15 +194,18 @@ enum _status_groups kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ - kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ - kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ - kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ - kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ - kStatusGroup_NETC = 165, /*!< Group number for NETC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ + kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */ }; /*! \public @@ -220,48 +229,66 @@ enum /*! @brief Type used for all status and error return values. */ typedef int32_t status_t; +#ifdef __ZEPHYR__ +#include +#else /*! * @name Min/max macros * @{ */ #if !defined(MIN) +/*! Computes the minimum of \a a and \a b. */ #define MIN(a, b) (((a) < (b)) ? (a) : (b)) #endif #if !defined(MAX) +/*! Computes the maximum of \a a and \a b. */ #define MAX(a, b) (((a) > (b)) ? (a) : (b)) #endif -/* @} */ +/*! @} */ /*! @brief Computes the number of elements in an array. */ #if !defined(ARRAY_SIZE) #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #endif +#endif /* __ZEPHYR__ */ /*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ +/*! @{ */ #if !defined(UINT16_MAX) +/*! Max value of uint16_t type. */ #define UINT16_MAX ((uint16_t)-1) #endif #if !defined(UINT32_MAX) +/*! Max value of uint32_t type. */ #define UINT32_MAX ((uint32_t)-1) #endif -/* @} */ +/*! @} */ -/*! @name Suppress fallthrough warning macro */ -/* For switch case code block, if case section ends without "break;" statement, there wil be - fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. - To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each - case section which misses "break;"statement. +/*! Macro to get upper 32 bits of a 64-bit value */ +#if !defined(UINT64_H) +#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL)) +#endif + +/*! Macro to get lower 32 bits of a 64-bit value */ +#if !defined(UINT64_L) +#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL)) +#endif + +/*! + * @def SUPPRESS_FALL_THROUGH_WARNING() + * + * For switch case code block, if case section ends without "break;" statement, there wil be + * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + * case section which misses "break;"statement. */ -/* @{ */ #if defined(__GNUC__) && !defined(__ARMCC_VERSION) #define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) #else #define SUPPRESS_FALL_THROUGH_WARNING() #endif -/* @} */ /******************************************************************************* * API @@ -309,10 +336,10 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); #if (defined(__DSC__) && defined(__CW__)) #include "fsl_common_dsc.h" -#elif defined(__XCC__) +#elif defined(__XTENSA__) #include "fsl_common_dsp.h" #else #include "fsl_common_arm.h" #endif -#endif /* _FSL_COMMON_H_ */ +#endif /* FSL_COMMON_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c index 241005e922..e9f32aadf4 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[]; #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base #define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) #elif defined(__ICCARM__) extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; extern uint32_t __VECTOR_TABLE[]; @@ -159,11 +159,11 @@ static void DelayLoop(uint32_t count) { __ASM volatile(" MOV X0, %0" : : "r"(count)); __ASM volatile( - "loop: \n" + "loop%=: \n" " SUB X0, X0, #1 \n" " CMP X0, #0 \n" - " BNE loop \n" + " BNE loop%= \n" : : : "r0"); @@ -176,7 +176,7 @@ static void DelayLoop(uint32_t count) { __ASM volatile(" MOV R0, %0" : : "r"(count)); __ASM volatile( - "loop: \n" + "loop%=: \n" #if defined(__GNUC__) && !defined(__ARMCC_VERSION) " SUB R0, R0, #1 \n" #else @@ -184,7 +184,7 @@ static void DelayLoop(uint32_t count) #endif " CMP R0, #0 \n" - " BNE loop \n" + " BNE loop%= \n" : : : "r0"); @@ -232,13 +232,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) { } #else +#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55)) + /* + * Cortex-A53/A55 execution throughput: + * - SUB/CMP: 2 instructions per cycle + * - BNE: 1 instruction per cycle + * So, each loop takes 2 CPU cycles. + */ + count = count / 2U; +#elif (__CORTEX_M == 7) /* Divide value may be different in various environment to ensure delay is precise. * Every loop count includes three instructions, due to Cortex-M7 sometimes executes * two instructions in one period, through test here set divide 1.5. Other M cores use * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does * not matter because other instructions outside while loop is enough to fill the time. */ -#if (__CORTEX_M == 7) count = count / 3U * 2U; #else count = count / 4U; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h index 1da9dff8d5..3d35d76f81 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_COMMON_ARM_H_ -#define _FSL_COMMON_ARM_H_ +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ /* * For CMSIS pack RTE. @@ -28,13 +28,7 @@ * These macros are used for atomic access, such as read-modify-write * to the peripheral registers. * - * - SDK_ATOMIC_LOCAL_ADD - * - SDK_ATOMIC_LOCAL_SET - * - SDK_ATOMIC_LOCAL_CLEAR - * - SDK_ATOMIC_LOCAL_TOGGLE - * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET - * - * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr * means the address of the peripheral register or variable you want to modify * atomically, the parameter @c clearBits is the bits to clear, the parameter * @c setBits it the bits to set. @@ -59,6 +53,27 @@ * @{ */ +/*! + * @def SDK_ATOMIC_LOCAL_ADD(addr, val) + * Add value \a val from the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SUB(addr, val) + * Subtract value \a val to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SET(addr, bits) + * Set the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits) + * Clear the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) + * Toggle the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) + * For the variable at address \a address, clear the bits specifiled by \a clearBits + * and set the bits specifiled by \a setBits. + */ + /* clang-format off */ #if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ @@ -220,6 +235,12 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + #define SDK_ATOMIC_LOCAL_SET(addr, bits) \ ((1UL == sizeof(*(addr))) ? \ _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ @@ -255,7 +276,16 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) += (val); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) #define SDK_ATOMIC_LOCAL_SET(addr, bits) \ do \ @@ -264,7 +294,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) |= (bits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ do \ @@ -273,7 +303,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) &= ~(bits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ do \ @@ -282,7 +312,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) ^= (bits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ do \ @@ -291,13 +321,13 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin s_atomicOldInt = DisableGlobalIRQ(); \ *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ EnableGlobalIRQ(s_atomicOldInt); \ - } while (0) + } while (false) #endif -/* @} */ +/*! @} */ /*! @name Timer utilities */ -/* @{ */ +/*! @{ */ /*! Macro to convert a microsecond period to raw count value */ #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) /*! Macro to convert a raw count value to microsecond */ @@ -307,7 +337,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) /*! Macro to convert a raw count value to millisecond */ #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) -/* @} */ +/*! @} */ /*! @name ISR exit barrier * @{ @@ -324,10 +354,10 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin #define SDK_ISR_EXIT_BARRIER #endif -/* @} */ +/*! @} */ /*! @name Alignment variable definition macros */ -/* @{ */ +/*! @{ */ #if (defined(__ICCARM__)) /* * Workaround to disable MISRA C message suppress warnings for IAR compiler. @@ -341,7 +371,7 @@ _Pragma("diag_suppress=Pm120") #elif defined(__CC_ARM) || defined(__ARMCC_VERSION) /*! Macro to define a variable with alignbytes alignment */ #define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#elif defined(__GNUC__) +#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT) /*! Macro to define a variable with alignbytes alignment */ #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) #else @@ -360,15 +390,37 @@ _Pragma("diag_suppress=Pm120") /*! Macro to change a value to a given size aligned value */ #define SDK_SIZEALIGN(var, alignbytes) \ ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) -/* @} */ +/*! @} */ -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable - * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, +/*! + * @name Non-cacheable region definition macros + * + * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable + * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, * these zero-inited variables will be initialized to zero in system startup. + * + * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + * + * @{ + */ + +/*! + * @def AT_NONCACHEABLE_SECTION(var) + * Define a variable \a var, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) + * Define a variable \a var, and place it in non-cacheable section, the start address + * of the variable is aligned to \a alignbytes. + * + * @def AT_NONCACHEABLE_SECTION_INIT(var) + * Define a variable \a var with initial value, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) + * Define a variable \a var with initial value, and place it in non-cacheable section, + * the start address of the variable is aligned to \a alignbytes. */ -/* @{ */ #if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) @@ -394,7 +446,7 @@ _Pragma("diag_suppress=Pm120") __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var #endif -#elif (defined(__GNUC__)) +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" * in your projects to make sure the non-cacheable section variables will be initialized in system startup. */ @@ -417,12 +469,24 @@ _Pragma("diag_suppress=Pm120") #endif -/* @} */ +/*! @} */ /*! * @name Time sensitive region * @{ */ + +/*! + * @def AT_QUICKACCESS_SECTION_CODE(func) + * Place function in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA(var) + * Place data in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) + * Place data in a section which can be accessed quickly by core, and the variable + * address is set to align with \a alignbytes. + */ #if (defined(__ICCARM__)) #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" #define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" @@ -433,7 +497,7 @@ _Pragma("diag_suppress=Pm120") #define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var #define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var -#elif (defined(__GNUC__)) +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func #define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var #define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ @@ -441,18 +505,25 @@ _Pragma("diag_suppress=Pm120") #else #error Toolchain not supported. #endif /* defined(__ICCARM__) */ +/*! @} */ -/*! @name Ram Function */ +/*! + * @name Ram Function + * @{ + * + * @def RAMFUNCTION_SECTION_CODE(func) + * Place function in ram. + */ #if (defined(__ICCARM__)) #define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" #elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif (defined(__GNUC__)) +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func #else #error Toolchain not supported. #endif /* defined(__ICCARM__) */ -/* @} */ +/*! @} */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) void DefaultISR(void); @@ -824,4 +895,4 @@ uint32_t MSDK_GetCpuCycleCount(void); /*! @} */ -#endif /* _FSL_COMMON_ARM_H_ */ +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c index 037dd41689..f4e303be95 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c @@ -40,6 +40,10 @@ /*< Default is resutl type is final checksum */ #endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ +#if defined(CRC_RSTS) +#define CRC_RESETS_ARRAY CRC_RSTS +#endif + /*! @brief CRC type of transpose of read write data */ typedef enum _crc_transpose_type { @@ -65,9 +69,49 @@ typedef struct _crc_module_config crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ } crc_module_config_t; +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +/*! + * @brief Get instance number for CRC module. + * + * @param base CRC peripheral base address + */ +static uint32_t CRC_GetInstance(CRC_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static uint32_t CRC_GetInstance(CRC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++) + { + if (s_crcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_crcBases)); + + return instance; +} +#endif /*! * @brief Returns transpose type for CRC protocol reflect in parameter. @@ -191,6 +235,11 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) /* ungate clock */ CLOCK_EnableClock(kCLOCK_Crc0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(CRC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]); +#endif + /* configure CRC module and write the seed */ if (config->crcResult == kCrcFinalChecksum) { diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h index 04270b83dc..487e9f1095 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ +#ifndef FSL_CRC_H_ +#define FSL_CRC_H_ #include "fsl_common.h" @@ -21,13 +21,16 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.3. +/*! @{ */ +/*! @brief CRC driver version. Version 2.0.4. * - * Current version: 2.0.3 + * Current version: 2.0.4 * * Change log: * + * - Version 2.0.4 + * - Release peripheral from reset if necessary in init function. + * * - Version 2.0.3 * - Fix MISRA issues * @@ -37,8 +40,8 @@ * - Version 2.0.1 * - move DATA and DATALL macro definition from header file to source file */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*! @} */ #ifndef CRC_DRIVER_CUSTOM_DEFAULTS /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ @@ -175,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base); *@} */ -#endif /* _FSL_CRC_H_ */ +#endif /* FSL_CRC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c index e53bebdd01..3317157fde 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c @@ -575,3 +575,30 @@ void CTIMER4_DriverIRQHandler(void) SDK_ISR_EXIT_BARRIER; } #endif + +#if defined(CTIMER5) +void CTIMER5_DriverIRQHandler(void); +void CTIMER5_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(5); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER6) +void CTIMER6_DriverIRQHandler(void); +void CTIMER6_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(6); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER7) +void CTIMER7_DriverIRQHandler(void); +void CTIMER7_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(7); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h index 27b6906f02..0ec7286e6c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ +#ifndef FSL_CTIMER_H_ +#define FSL_CTIMER_H_ #include "fsl_common.h" @@ -22,9 +22,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ #define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */ -/*@}*/ +/*! @} */ /*! @brief List of Timer capture channels */ typedef enum _ctimer_capture_channel @@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match /*! @}*/ -#endif /* _FSL_CTIMER_H_ */ +#endif /* FSL_CTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c index e981a08ee1..09845018de 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c @@ -8,11 +8,20 @@ #include "fsl_dac.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.dac_1" #endif +#if defined(DAC_RSTS) +#define DAC_RESETS_ARRAY DAC_RSTS +#elif defined(DAC_RSTS_N) +#define DAC_RESETS_ARRAY DAC_RSTS_N +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -34,6 +43,11 @@ static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS; static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(DAC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_dacResets[] = DAC_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -74,6 +88,10 @@ void DAC_Init(LPDAC_Type *base, const dac_config_t *config) CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(DAC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_dacResets[DAC_GetInstance(base)]); +#endif + /* Reset the logic. */ DAC_SetReset(base, kDAC_ResetLogic); DAC_ClearReset(base, kDAC_ResetLogic); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h index f7146bd60d..5dcecf2db5 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_DAC_H_ -#define _FSL_DAC_H_ +#ifndef FSL_DAC_H_ +#define FSL_DAC_H_ #include "fsl_common.h" @@ -23,10 +23,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief DAC driver version 2.1.1. */ -#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ +/*! @{ */ +/*! @brief DAC driver version 2.1.2. */ +#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @} */ /*! * @brief DAC reset control. @@ -293,7 +293,7 @@ static inline void DAC_Enable(LPDAC_Type *base, bool enable) } } -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -322,7 +322,7 @@ static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask) base->IER &= ~mask; } -/* @} */ +/*! @} */ /*! * @name DMA control @@ -348,7 +348,7 @@ static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable) } } -/* @} */ +/*! @} */ /*! * @name Status flags @@ -377,7 +377,7 @@ static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags) base->FSR = flags; } -/* @} */ +/*! @} */ /*! * @name Functional feature @@ -430,7 +430,7 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base) base->TCR = LPDAC_TCR_SWTRG_MASK; } -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -439,4 +439,4 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base) /*! * @} */ -#endif /* _FSL_DAC12_H_ */ +#endif /* FSL_DAC12_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h index 4754c3ee7c..a50fad8d1a 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_DAC14_H_ -#define _FSL_DAC14_H_ +#ifndef FSL_DAC14_H_ +#define FSL_DAC14_H_ #include "fsl_common.h" @@ -22,10 +22,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief DAC14 driver version 2.0.0. */ #define FSL_DAC14_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +/*! @} */ /*! * @brief DAC14 interrupts enumeration. @@ -209,7 +209,7 @@ static inline void DAC14_AbortPeriodTriggerConvSequence(HPDAC_Type *base) { base->GCR &= ~HPDAC_GCR_PTGEN_MASK; } -/* @} */ +/*! @} */ /*! * @name DAC Control Interface @@ -233,7 +233,7 @@ static inline void DAC14_Enable(HPDAC_Type *base, bool enable) base->GCR &= ~HPDAC_GCR_DACEN_MASK; } } -/* @} */ +/*! @} */ /*! * @name Swing Back Mode Control Interface @@ -256,7 +256,7 @@ static inline void DAC14_EnableSwingBackMode(HPDAC_Type *base, bool enable) base->GCR &= ~HPDAC_GCR_SWMD_MASK; } } -/* @} */ +/*! @} */ /*! * @name FIFO Mode Control Interface @@ -279,7 +279,7 @@ static inline void DAC14_EnableFIFOMode(HPDAC_Type *base, bool enable) base->GCR &= ~HPDAC_GCR_FIFOEN_MASK; } } -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -306,7 +306,7 @@ static inline void DAC14_DisableInterrupts(HPDAC_Type *base, uint32_t mask) { base->IER &= ~mask; } -/* @} */ +/*! @} */ /*! * @name DMA Control Interface @@ -330,7 +330,7 @@ static inline void DAC14_EnableDMA(HPDAC_Type *base, uint32_t mask, bool enable) base->DER &= ~mask; } } -/* @} */ +/*! @} */ /*! * @name Status @@ -357,7 +357,7 @@ static inline void DAC14_ClearStatusFlags(HPDAC_Type *base, uint32_t flags) { base->FSR = flags; } -/* @} */ +/*! @} */ /*! * @name Functional Feature @@ -407,7 +407,7 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base) { base->TCR = HPDAC_TCR_SWTRG_MASK; } -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -416,4 +416,4 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base) /*! * @} */ -#endif /* _FSL_DAC14_H_ */ +#endif /* FSL_DAC14_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c index e1ffe8058c..b444faac9b 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c @@ -16,7 +16,15 @@ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.edma" +#define FSL_COMPONENT_ID "platform.drivers.edma4" +#endif +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#define CONVERT_TO_DMA_ADDRESS(addr) (MEMORY_ConvertMemoryMapAddress((uint32_t)(addr), kMEMORY_Local2DMA)) +#else +#define CONVERT_TO_DMA_ADDRESS(addr) ((uint32_t)(addr)) +#endif +#if defined(DMA_RSTS_N) +#define EDMA_RESETS_ARRAY DMA_RSTS_N #endif /******************************************************************************* * Prototypes @@ -27,6 +35,16 @@ * @param width transfer width. */ static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width); + +/*! + * @brief validate edma errata. + * + * @param base edma base address. + * @param tcd edma transfer content descriptor. + */ +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, edma_tcd_t *tcd); +#endif /******************************************************************************* * Variables ******************************************************************************/ @@ -38,11 +56,16 @@ static EDMA_Type *const s_edmaBases[] = EDMA_BASE_PTRS; static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(EDMA_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_edmaResets[] = EDMA_RESETS_ARRAY; +#endif + /*! @brief Array to map EDMA instance number to IRQ number. */ -static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL] = EDMA_CHN_IRQS; +static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; /*! @brief Pointers to transfer handle for each EDMA channel. */ -static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_COUNT][FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL]; +static edma_handle_t *s_EDMAHandle[FSL_FEATURE_SOC_EDMA_COUNT][FSL_FEATURE_EDMA_MODULE_CHANNEL]; /******************************************************************************* * Code ******************************************************************************/ @@ -64,6 +87,24 @@ static uint32_t EDMA_GetInstance(EDMA_Type *base) return instance; } +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, edma_tcd_t *tcd) +{ + status_t status = kStatus_Success; + /* errata 51327: to use scatter gather feature, NBYTES must be multiple of 8 */ + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(base) == 1U) + { + if ((EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) % 8U) != 0U) + { + assert(false); + status = kStatus_InvalidArgument; + } + } + + return status; +} +#endif + /*! * brief Push content of TCD structure into hardware TCD register. * @@ -73,30 +114,34 @@ static uint32_t EDMA_GetInstance(EDMA_Type *base) */ void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); edma_tcd_t *tcdRegs = EDMA_TCD_BASE(base, channel); -#if FSL_EDMA_SOC_IP_DMA3 || FSL_EDMA_SOC_IP_DMA4 - EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if ((EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) != 0U) && + ((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (uint16_t)DMA_CSR_ESG_MASK) != 0U) && + (EDMA_CheckErrata(base, tcd) != kStatus_Success)) + { + assert(false); + } #endif - /* Push tcd into hardware TCD register */ - tcdRegs->SADDR = tcd->SADDR; - tcdRegs->SOFF = tcd->SOFF; - tcdRegs->ATTR = tcd->ATTR; - tcdRegs->NBYTES = tcd->NBYTES; - tcdRegs->SLAST = (int32_t)tcd->SLAST; - tcdRegs->DADDR = tcd->DADDR; - tcdRegs->DOFF = tcd->DOFF; - tcdRegs->CITER = tcd->CITER; - tcdRegs->DLAST_SGA = (int32_t)tcd->DLAST_SGA; /* Clear DONE bit first, otherwise ESG cannot be set */ - tcdRegs->CSR = 0; - tcdRegs->CSR = tcd->CSR; - tcdRegs->BITER = tcd->BITER; + DMA_CLEAR_DONE_STATUS(base, channel); + /* Push tcd into hardware TCD register */ + EDMA_TCD_SADDR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_SOFF(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_ATTR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_NBYTES(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_SLAST(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_DADDR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_DOFF(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)); } /*! @@ -112,6 +157,7 @@ void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd) void EDMA_Init(EDMA_Type *base, const edma_config_t *config) { assert(config != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); uint32_t tmpreg, i = 0U; @@ -120,7 +166,11 @@ void EDMA_Init(EDMA_Type *base, const edma_config_t *config) CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if FSL_EDMA_SOC_IP_EDMA +#if defined(EDMA_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_edmaResets[EDMA_GetInstance(base)]); +#endif + +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA /* clear all the enabled request, status to make sure EDMA status is in normal condition */ EDMA_BASE(base)->ERQ = 0U; EDMA_BASE(base)->INT = 0xFFFFFFFFU; @@ -146,8 +196,10 @@ void EDMA_Init(EDMA_Type *base, const edma_config_t *config) DMA_MP_CSR_EDBG(config->enableDebugMode) | DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); #endif EDMA_MP_BASE(base)->MP_CSR = tmpreg; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG /* channel transfer configuration */ - for (i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base); i++) + for (i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base); i++) { if (config->channelConfig[i] != NULL) { @@ -155,6 +207,7 @@ void EDMA_Init(EDMA_Type *base, const edma_config_t *config) } } #endif +#endif } /*! @@ -190,7 +243,7 @@ void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t * EDMA_SetChannelSwapSize(base, channel, channelConfig->channelSwapSize); #endif -#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE EDMA_SetChannelMemoryAttribute(base, channel, channelConfig->channelWriteMemoryAttribute, channelConfig->channelReadMemoryAttribute); #endif @@ -200,15 +253,22 @@ void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t * #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE EDMA_SetChannelAccessType(base, channel, channelConfig->channelAccessType); #endif - if (kDmaRequestDisabled != channelConfig->channelRequestSource) + +#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || \ + (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX) + if (0U != (uint32_t)channelConfig->channelRequestSource) { /* dma request source */ - EDMA_SetChannelMux(base, channel, channelConfig->channelRequestSource); + EDMA_SetChannelMux(base, channel, (int32_t)channelConfig->channelRequestSource); } +#endif + /* master ID replication */ EDMA_EnableChannelMasterIDReplication(base, channel, channelConfig->enableMasterIDReplication); +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) /* dma transfer security level */ EDMA_SetChannelSecurityLevel(base, channel, channelConfig->securityLevel); +#endif /* dma transfer protection level */ EDMA_SetChannelProtectionLevel(base, channel, channelConfig->protectionLevel); } @@ -265,12 +325,12 @@ void EDMA_GetDefaultConfig(edma_config_t *config) */ void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); /* reset channel CSR */ EDMA_ClearChannelStatusFlags(base, channel, (uint32_t)kEDMA_DoneFlag | (uint32_t)kEDMA_ErrorFlag); /* reset channel TCD */ - EDMA_TcdReset(EDMA_TCD_BASE(base, channel)); + EDMA_TcdResetExt(base, EDMA_TCD_BASE(base, channel)); } /*! @@ -303,16 +363,11 @@ void EDMA_SetTransferConfig(EDMA_Type *base, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0U); -/* If there is address offset, convert the address */ -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - nextTcd = (edma_tcd_t *)(MEMORY_ConvertMemoryMapAddress((uint32_t)nextTcd, kMEMORY_Local2DMA)); -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - - EDMA_TcdSetTransferConfig(EDMA_TCD_BASE(base, channel), config, nextTcd); + EDMA_TcdSetTransferConfigExt(base, EDMA_TCD_BASE(base, channel), config, + (edma_tcd_t *)CONVERT_TO_DMA_ADDRESS(nextTcd)); } /*! @@ -327,17 +382,17 @@ void EDMA_SetTransferConfig(EDMA_Type *base, */ void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); assert(config != NULL); uint32_t tmpreg; - tmpreg = EDMA_TCD_BASE(base, channel)->NBYTES; + tmpreg = EDMA_TCD_NBYTES(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)); tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); tmpreg |= (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - EDMA_TCD_BASE(base, channel)->NBYTES = tmpreg; + EDMA_TCD_NBYTES(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = tmpreg; } /*! @@ -352,10 +407,10 @@ void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_min */ void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - EDMA_TCD_BASE(base, channel)->SLAST = sourceOffset; - EDMA_TCD_BASE(base, channel)->DLAST_SGA = destOffset; + EDMA_TCD_SLAST(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = (uint32_t)sourceOffset; + EDMA_TCD_DLAST_SGA(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = (uint32_t)destOffset; } /*! @@ -369,14 +424,14 @@ void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t source */ void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); assert(config != NULL); bool tmpEnablePreemptAbility = config->enablePreemptAbility; bool tmpEnablchannelPreemption = config->enableChannelPreemption; uint8_t tmpChannelPriority = config->channelPriority; -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA volatile uint8_t *tmpReg = &EDMA_BASE(base)->DCHPRI3; @@ -408,10 +463,10 @@ void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const ed */ void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); - assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - EDMA_TcdSetChannelLink(EDMA_TCD_BASE(base, channel), type, linkedChannel); + EDMA_TcdSetChannelLinkExt(base, EDMA_TCD_BASE(base, channel), type, linkedChannel); } #if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH @@ -431,10 +486,11 @@ void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_ty */ void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - EDMA_BASE(base)->TCD[channel].CSR = - (uint16_t)((EDMA_BASE(base)->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = + (uint16_t)((EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & (~DMA_CSR_BWC_MASK)) | + DMA_CSR_BWC(bandWidth)); } #endif @@ -452,85 +508,390 @@ void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandW */ void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - uint16_t tmpreg = EDMA_TCD_BASE(base, channel)->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - EDMA_TCD_BASE(base, channel)->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); + uint16_t tmpreg = EDMA_TCD_ATTR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & + (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = + tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } /*! - * brief Enables the interrupt source for the eDMA transfer. + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. * * param base eDMA peripheral base address. - * param channel eDMA channel number. + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ +void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + /* Reset channel TCD */ + EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = 0U; + /* Enable auto disable request feature */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = DMA_CSR_DREQ(1U); + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = 0U; +} + +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param base eDMA peripheral base address. + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, + edma_tcd_t *tcd, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(config != NULL); + + EDMA_ConfigChannelSoftwareTCDExt(base, tcd, config); + + if (nextTcd != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * brief Sets TCD fields according to the user's channel transfer configuration structure, see + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * param base eDMA peripheral base address. + * param tcd Pointer to the TCD structure. + * param transfer channel transfer configuration pointer. + * + */ +void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer) +{ + assert(transfer != NULL); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert(((uint32_t)transfer->srcOffset % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert(((uint32_t)transfer->destOffset % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcAddrModulo))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->dstAddrModulo))) == 0U); + + uint16_t tmpreg; + + EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS(transfer->srcAddr); + /* destination address */ + EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS(transfer->destAddr); + /* Source data and destination data transfer size */ + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = + DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); + + /* Source address signed offset */ + EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->srcOffset); + /* Destination address signed offset */ + EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->destOffset); + + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | + DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | + DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); + } + else + { + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); + } + + /* Current major iteration count */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->majorLoopCounts); + /* Starting major iteration count */ + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->majorLoopCounts); + /* reset CSR firstly */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (transfer->linkTCD != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS((uint32_t)((uint8_t *)transfer->linkTCD)); + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + else + { + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_ESG_MASK; + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)transfer->dstMajorLoopOffset; + } + + /* configure interrupt/auto disable channel request */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); + + /* Minor link config */ + if (transfer->enableChannelMinorLoopLink) + { + /* Enable minor link */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + } + /* Major link config */ + if (transfer->enableChannelMajorLoopLink) + { + /* Enable major link */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); + } + + /* clear link relate field if no channel link enabled */ + if ((!transfer->enableChannelMajorLoopLink) && (!transfer->enableChannelMinorLoopLink)) + { + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } + + /* major loop offset */ + EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)transfer->srcMajorLoopOffset; + /* modulo feature */ + tmpreg = EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = + tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); +} + +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint32_t tmpreg; + + tmpreg = EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = tmpreg; +} + +/*! + * brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param base eDMA peripheral base address. + * param tcd A point to the TCD structure. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)sourceOffset; + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)destOffset; +} + +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param base eDMA peripheral base address. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint16_t tmpreg; + + /* Enable minor link */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint16_t tmpreg; + + /* Enable major link */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint16_t tmpreg; + + tmpreg = EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param base eDMA peripheral base address. + * param tcd Point to the TCD structure. * param mask The mask of interrupt source to be set. Users need to use * the defined edma_interrupt_enable_t type. */ -void EDMA_EnablchannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); - - /* Enable error interrupt */ - if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) - { -#if FSL_EDMA_SOC_IP_EDMA - EDMA_BASE(base)->EEI |= ((uint32_t)0x1U << channel); -#else - EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK; -#endif - } + assert(tcd != NULL); /* Enable Major interrupt */ if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTMAJOR_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK; } /* Enable Half major interrupt */ if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTHALF_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK; } } /*! - * brief Disables the interrupt source for the eDMA transfer. + * brief Disables the interrupt source for the eDMA TCD. * * param base eDMA peripheral base address. - * param channel eDMA channel number. - * param mask The mask of the interrupt source to be set. Use + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use * the defined edma_interrupt_enable_t type. */ -void EDMA_DisablchannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); - - /* Disable error interrupt */ - if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) - { -#if FSL_EDMA_SOC_IP_EDMA - EDMA_BASE(base)->EEI &= (~((uint32_t)0x1U << channel)); -#else - EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK; -#endif - } + assert(tcd != NULL); /* Disable Major interrupt */ if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; } /* Disable Half major interrupt */ if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; } } /*! * brief Sets all fields to default values for the TCD structure. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdResetExt + * * This function sets all fields for this TCD structure to default value. * * param tcd Pointer to the TCD structure. @@ -539,26 +900,28 @@ void EDMA_DisablchannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t ma void EDMA_TcdReset(edma_tcd_t *tcd) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); /* Reset channel TCD */ - tcd->SADDR = 0U; - tcd->SOFF = 0U; - tcd->ATTR = 0U; - tcd->NBYTES = 0U; - tcd->SLAST = 0U; - tcd->DADDR = 0U; - tcd->DOFF = 0U; - tcd->CITER = 0U; - tcd->DLAST_SGA = 0U; + EDMA_TCD_SADDR(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_SOFF(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_SLAST(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_DADDR(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_DOFF(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = 0U; /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); - tcd->BITER = 0U; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = DMA_CSR_DREQ(1U); + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = 0U; } /*! * brief Configures the eDMA TCD transfer attribute. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetTransferConfigExt + * * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. * The TCD is used in the scatter-gather mode. * This function configures the TCD transfer attribute, including source address, destination address, @@ -586,18 +949,13 @@ void EDMA_TcdReset(edma_tcd_t *tcd) void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); assert(config != NULL); EDMA_ConfigChannelSoftwareTCD(tcd, config); if (nextTcd != NULL) { -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - tcd->DLAST_SGA = MEMORY_ConvertMemoryMapAddress((uint32_t)nextTcd, kMEMORY_Local2DMA); -#else - tcd->DLAST_SGA = (uint32_t)nextTcd; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS(nextTcd); /* Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, user must call EDMA_TcdReset or EDMA_ResetChannel which will set @@ -607,13 +965,17 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co previous transfer is not the last transfer, and channel request should be enabled at the next transfer(the next TCD). */ - tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = + (EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; } } /*! * brief Sets TCD fields according to the user's channel transfer configuration structure, see - * edma4_channel_transfer_config_t. + * edma_transfer_config_t. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_ConfigChannelSoftwareTCDExt * * Application should be careful about the TCD pool buffer storage class, * - For the platform has cache, the software TCD should be put in non cache section @@ -637,106 +999,98 @@ void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t uint16_t tmpreg; -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - tcd->SADDR = MEMORY_ConvertMemoryMapAddress(transfer->srcAddr, kMEMORY_Local2DMA); + EDMA_TCD_SADDR(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS(transfer->srcAddr); /* destination address */ - tcd->DADDR = MEMORY_ConvertMemoryMapAddress(transfer->destAddr, kMEMORY_Local2DMA); -#else - tcd->SADDR = transfer->srcAddr; - /* destination address */ - tcd->DADDR = transfer->destAddr; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + EDMA_TCD_DADDR(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS(transfer->destAddr); /* Source data and destination data transfer size */ - tcd->ATTR = DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = + DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); /* Source address signed offset */ - tcd->SOFF = (uint16_t)(transfer->srcOffset); + EDMA_TCD_SOFF(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->srcOffset); /* Destination address signed offset */ - tcd->DOFF = (uint16_t)(transfer->destOffset); + EDMA_TCD_DOFF(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->destOffset); if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) { - tcd->NBYTES = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | - DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | - DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | + DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | + DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); } else { - tcd->NBYTES = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); } /* Current major iteration count */ - tcd->CITER = (uint16_t)(transfer->majorLoopCounts); + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->majorLoopCounts); /* Starting major iteration count */ - tcd->BITER = (uint16_t)(transfer->majorLoopCounts); + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->majorLoopCounts); /* reset CSR firstly */ - tcd->CSR = DMA_CSR_DREQ(true); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = DMA_CSR_DREQ(1U); /* Enable scatter/gather processing */ if (transfer->linkTCD != NULL) { -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - tcd->DLAST_SGA = MEMORY_ConvertMemoryMapAddress((uint32_t)transfer->linkTCD, kMEMORY_Local2DMA); -#else - tcd->DLAST_SGA = (uint32_t)((uint8_t *)transfer->linkTCD); -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - tcd->CSR |= (uint16_t)DMA_CSR_ESG_MASK; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS((uint32_t)((uint8_t *)transfer->linkTCD)); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = + (EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; } else { - tcd->CSR &= ~(uint16_t)DMA_CSR_ESG_MASK; - tcd->DLAST_SGA = (uint32_t)transfer->dstMajorLoopOffset; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_ESG_MASK; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = (uint32_t)transfer->dstMajorLoopOffset; } /* configure interrupt/auto disable channel request */ - tcd->CSR |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); /* Minor link config */ if (transfer->enableChannelMinorLoopLink) { - uint16_t tmpreg; - /* Enable minor link */ - tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) |= DMA_BITER_ELINKYES_ELINK_MASK; /* Set linked channel */ - tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg = EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_CITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); - tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_BITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); - tcd->BITER = tmpreg; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = tmpreg; } /* Major link config */ if (transfer->enableChannelMajorLoopLink) { - uint16_t tmpreg; - /* Enable major link */ - tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_MAJORELINK_MASK; /* Set major linked channel */ - tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); - tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); + tmpreg = EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); } /* clear link relate field if no channel link enabled */ if ((!transfer->enableChannelMajorLoopLink) && (!transfer->enableChannelMinorLoopLink)) { - tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; } /* major loop offset */ - tcd->SLAST = (uint32_t)transfer->srcMajorLoopOffset; + EDMA_TCD_SLAST(tcd, kEDMA_EDMA4Flag) = (uint32_t)transfer->srcMajorLoopOffset; /* modulo feature */ - tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - tcd->ATTR = tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); + tmpreg = EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = + tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); } /*! * brief Configures the eDMA TCD minor offset feature. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetMinorOffsetConfigExt + * * A minor offset is a signed-extended value added to the source address or a destination * address after each minor loop. * @@ -746,21 +1100,23 @@ void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); uint32_t tmpreg; - tmpreg = tcd->NBYTES & + tmpreg = EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) & ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); tmpreg |= (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - tcd->NBYTES = tmpreg; + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = tmpreg; } /*! * brief Configures the eDMA TCD major offset feature. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetMajorOffsetConfigExt + * * Adjustment value added to the source address at the completion of the major iteration count * * param tcd A point to the TCD structure. @@ -770,15 +1126,17 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); - tcd->SLAST = (uint32_t)sourceOffset; - tcd->DLAST_SGA = (uint32_t)destOffset; + EDMA_TCD_SLAST(tcd, kEDMA_EDMA4Flag) = (uint32_t)sourceOffset; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = (uint32_t)destOffset; } /*! * brief Sets the channel link for the eDMA TCD. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetChannelLinkExt + * * This function configures either a minor link or a major link. The minor link means the channel link is * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is * exhausted. @@ -794,45 +1152,47 @@ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); - assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); if (type == kEDMA_MinorLink) /* Minor link config */ { uint16_t tmpreg; /* Enable minor link */ - tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) |= DMA_BITER_ELINKYES_ELINK_MASK; /* Set linked channel */ - tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg = EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); - tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); - tcd->BITER = tmpreg; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = tmpreg; } else if (type == kEDMA_MajorLink) /* Major link config */ { uint16_t tmpreg; /* Enable major link */ - tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_MAJORELINK_MASK; /* Set major linked channel */ - tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); - tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + tmpreg = EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); } else /* Link none */ { - tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; } } /*! * brief Sets the source modulo and the destination modulo for the eDMA TCD. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetModuloExt + * * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) * calculation is performed or the original register value. It provides the ability to implement a circular data * queue easily. @@ -844,17 +1204,19 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); uint16_t tmpreg; - tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); + tmpreg = EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } /*! * brief Enables the interrupt source for the eDMA TCD. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdEnableInterruptsExt + * * param tcd Point to the TCD structure. * param mask The mask of interrupt source to be set. Users need to use * the defined edma_interrupt_enable_t type. @@ -866,19 +1228,22 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) /* Enable Major interrupt */ if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_INTMAJOR_MASK; } /* Enable Half major interrupt */ if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - tcd->CSR |= DMA_CSR_INTHALF_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_INTHALF_MASK; } } /*! * brief Disables the interrupt source for the eDMA TCD. * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdDisableInterruptsExt + * * param tcd Point to the TCD structure. * param mask The mask of interrupt source to be set. Users need to use * the defined edma_interrupt_enable_t type. @@ -890,13 +1255,13 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) /* Disable Major interrupt */ if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - tcd->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; } /* Disable Half major interrupt */ if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; } } @@ -923,29 +1288,27 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) */ uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); uint32_t remainingCount = 0; -#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA - if (0U != (DMA_CSR_DONE_MASK & EDMA_TCD_BASE(base, channel)->CSR)) -#else - if ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U) -#endif + if (0U != DMA_GET_DONE_STATUS(base, channel)) { remainingCount = 0; } else { /* Calculate the unfinished bytes */ - if (0U != (EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKNO_ELINK_MASK)) + if (0U != (EDMA_TCD_CITER(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & DMA_CITER_ELINKNO_ELINK_MASK)) { - remainingCount = (((uint32_t)EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKYES_CITER_MASK) >> + remainingCount = (((uint32_t)EDMA_TCD_CITER(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & + DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT); } else { - remainingCount = (((uint32_t)EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKNO_CITER_MASK) >> + remainingCount = (((uint32_t)EDMA_TCD_CITER(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & + DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT); } } @@ -963,32 +1326,24 @@ uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel) */ void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA /* Enable error interrupt */ if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) { - base->EEI |= ((uint32_t)0x1U << channel); + DMA_ENABLE_ERROR_INT(base, channel); } -#else - /* Enable error interrupt */ - if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) - { - EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK; - } -#endif /* Enable Major interrupt */ if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTMAJOR_MASK; + DMA_ENABLE_MAJOR_INT(base, channel); } /* Enable Half major interrupt */ if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTHALF_MASK; + DMA_ENABLE_HALF_INT(base, channel); } } @@ -1002,32 +1357,24 @@ void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t ma */ void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA /* Disable error interrupt */ if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) { - base->EEI &= (~((uint32_t)0x1U << channel)); + DMA_DISABLE_ERROR_INT(base, channel); } -#else - /* Enable error interrupt */ - if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) - { - EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK; - } -#endif /* Disable Major interrupt */ if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + DMA_DISABLE_MAJOR_INT(base, channel); } /* Disable Half major interrupt */ if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + DMA_DISABLE_HALF_INT(base, channel); } } @@ -1041,25 +1388,17 @@ void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t m */ uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); uint32_t retval = 0; -#if FSL_EDMA_SOC_IP_EDMA /* Get DONE bit flag */ - retval |= (((uint32_t)EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + retval |= DMA_GET_DONE_STATUS(base, channel); /* Get ERROR bit flag */ - retval |= ((((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U) << 1U); + retval |= (DMA_GET_ERROR_STATUS(base, channel) << 1U); /* Get INT bit flag */ - retval |= ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U) << 2U); -#else - /* Get DONE bit flag */ - retval |= (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT); - /* Get ERROR bit flag */ - retval |= ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U) << 1U); - /* Get INT bit flag */ - retval |= ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U) << 2U); -#endif + retval |= (DMA_GET_INT_STATUS(base, channel) << 2U); + return retval; } @@ -1073,41 +1412,23 @@ uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel) */ void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA /* Clear DONE bit flag */ if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) { - EDMA_BASE(base)->CDNE = (uint8_t)channel; + DMA_CLEAR_DONE_STATUS(base, channel); } /* Clear ERROR bit flag */ if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) { - EDMA_BASE(base)->CERR = (uint8_t)channel; + DMA_CLEAR_ERROR_STATUS(base, channel); } /* Clear INT bit flag */ if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) { - EDMA_BASE(base)->CINT = (uint8_t)channel; + DMA_CLEAR_INT_STATUS(base, channel); } -#else - /* Clear DONE bit flag */ - if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) - { - EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK; - } - /* Clear ERROR bit flag */ - else if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) - { - EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK; - } - /* Clear INT bit flag */ - if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) - { - EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK; - } -#endif } /*! @@ -1124,7 +1445,8 @@ void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t ma void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) { assert(handle != NULL); - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); uint32_t edmaInstance; edma_tcd_t *tcdRegs; @@ -1148,18 +1470,18 @@ void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) CSR will be 0. Because in order to suit EDMA busy check mechanism in EDMA_SubmitTransfer, CSR must be set 0. */ - tcdRegs = handle->tcdBase; - tcdRegs->SADDR = 0; - tcdRegs->SOFF = 0; - tcdRegs->ATTR = 0; - tcdRegs->NBYTES = 0; - tcdRegs->SLAST = 0; - tcdRegs->DADDR = 0; - tcdRegs->DOFF = 0; - tcdRegs->CITER = 0; - tcdRegs->DLAST_SGA = 0; - tcdRegs->CSR = 0; - tcdRegs->BITER = 0; + tcdRegs = handle->tcdBase; + EDMA_TCD_SADDR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_SOFF(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_ATTR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_NBYTES(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_SLAST(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_DADDR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_DOFF(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(base)) = 0; } /*! @@ -1286,6 +1608,8 @@ static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width) * note The data address and the data width must be consistent. For example, if the SRC * is 4 bytes, the source address must be 4 bytes aligned, or it results in * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. */ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, @@ -1323,19 +1647,14 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, assert(srcWidth != 64U); #endif assert((transferBytes % bytesEachRequest) == 0U); - assert((((uint32_t)(uint32_t *)srcAddr) % srcWidth) == 0U); - assert((((uint32_t)(uint32_t *)destAddr) % destWidth) == 0U); + assert((((uint32_t)(uint8_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint8_t *)destAddr) % destWidth) == 0U); /* Initializes the configure structure to zero. */ (void)memset(config, 0, sizeof(*config)); -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - config->srcAddr = MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcAddr, kMEMORY_Local2DMA); - config->destAddr = MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)destAddr, kMEMORY_Local2DMA); -#else - config->destAddr = (uint32_t)(uint32_t *)destAddr; - config->srcAddr = (uint32_t)(uint32_t *)srcAddr; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + config->destAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)destAddr); + config->srcAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)srcAddr); config->minorLoopBytes = bytesEachRequest; config->majorLoopCounts = transferBytes / bytesEachRequest; config->srcTransferSize = EDMA_TransferWidthMapping(srcWidth); @@ -1343,7 +1662,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, config->destOffset = destOffset; config->srcOffset = srcOffset; /* enable major interrupt by default */ - config->enabledInterruptMask = kEDMA_MajorInterruptEnable; + config->enabledInterruptMask = (uint16_t)kEDMA_MajorInterruptEnable; } /*! @@ -1405,22 +1724,179 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, } /*! - * brief Submits the eDMA transfer request. + * brief Prepares the eDMA transfer content descriptor. * - * This function submits the eDMA transfer request according to the transfer configuration structure. + * This function prepares the transfer content descriptor structure according to the user input. + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param nextTcd eDMA transfer linked TCD address. + * + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint32_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint32_t *)destAddr) % destWidth) == 0U); + + edma_transfer_size_t srcTransferSize = EDMA_TransferWidthMapping(srcWidth), + destTransferSize = EDMA_TransferWidthMapping(srcWidth); + + /* Initializes the configure structure to zero. */ + EDMA_TcdResetExt(handle->base, tcd); + assert((bytesEachRequest % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert((bytesEachRequest % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)srcOffset % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)destOffset % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)srcAddr % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)destAddr % (1UL << ((uint32_t)destTransferSize))) == 0U); + + EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(handle->base)) = CONVERT_TO_DMA_ADDRESS((uint32_t *)srcAddr); + /* destination address */ + EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(handle->base)) = CONVERT_TO_DMA_ADDRESS((uint32_t *)destAddr); + /* Source data and destination data transfer size */ + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(handle->base)) = DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize); + + /* Source address signed offset */ + EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(srcOffset); + /* Destination address signed offset */ + EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(destOffset); + + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(handle->base)) = DMA_NBYTES_MLOFFNO_NBYTES(bytesEachRequest); + + /* Current major iteration count */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(transferBytes / bytesEachRequest); + /* Starting major iteration count */ + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(transferBytes / bytesEachRequest); + /* reset CSR firstly */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(handle->base)) = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) = + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + + /* configure interrupt/auto disable channel request, enable major interrupt by default */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) |= + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) & (~(uint16_t)kEDMA_ErrorInterruptEnable)) | + (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. * The tcd pools is setup by call function EDMA_InstallTCDMemory before. * + * Typical user case: + * 1. submit single transfer + * code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 2. submit static link transfer, + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * 3. submit dynamic link transfer + * code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 4. submit loop transfer + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * * param handle eDMA handle pointer. - * param config Pointer to eDMA transfer configuration structure. + * param tcd Pointer to eDMA transfer content descriptor structure. + * * retval kStatus_EDMA_Success It means submit transfer request succeed. * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. */ -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd) { assert(handle != NULL); - assert(config != NULL); assert(handle->tcdBase != NULL); edma_tcd_t *tcdRegs = handle->tcdBase; @@ -1444,17 +1920,206 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t #else if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || #endif - (((tcdRegs->CITER & DMA_CITER_ELINKNO_CITER_MASK) != (tcdRegs->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + (((EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CITER_ELINKNO_CITER_MASK) != + (EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_BITER_ELINKNO_BITER_MASK)))) { return kStatus_EDMA_Busy; } else { - EDMA_TcdSetTransferConfig(tcdRegs, config, NULL); + EDMA_InstallTCD(handle->base, handle->channel, tcd); /* Enable auto disable request feature */ - tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + EDMA_EnableAutoStopRequest(handle->base, handle->channel, true); /* Enable major interrupt */ - tcdRegs->CSR |= DMA_CSR_INTMAJOR_MASK; + EDMA_EnableChannelInterrupts(handle->base, handle->channel, kEDMA_MajorInterruptEnable); + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + + /* Configure current TCD block. */ + EDMA_TcdResetExt(handle->base, &handle->tcdPool[currentTcd]); + (void)memcpy(&handle->tcdPool[currentTcd], tcd, sizeof(edma_tcd_t)); + + /* Enable major interrupt */ + EDMA_TCD_CSR((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_INTMAJOR_MASK; + + if ((EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(handle->base)) == 0U) || + ((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) == 0U)) + { + /* Link current TCD with next TCD for identification of current TCD */ + EDMA_TCD_DLAST_SGA((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) = + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + } + + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) | + ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK)) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(handle->base)) != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(handle->tcdBase != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert(((config->srcTransferSize != kEDMA_TransferSize128Bytes) && + (config->destTransferSize != kEDMA_TransferSize128Bytes)) || + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#endif + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CITER_ELINKNO_CITER_MASK) != + (EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_TcdSetTransferConfigExt(handle->base, tcdRegs, config, NULL); + /* Enable auto disable request feature */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_INTMAJOR_MASK; return kStatus_Success; } @@ -1493,43 +2158,42 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t /* Calculate index of previous TCD */ previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); /* Configure current TCD block. */ - EDMA_TcdReset(&handle->tcdPool[currentTcd]); - EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + EDMA_TcdResetExt(handle->base, &handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfigExt(handle->base, &handle->tcdPool[currentTcd], config, NULL); /* Enable major interrupt */ - handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + EDMA_TCD_CSR((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_INTMAJOR_MASK; /* Link current TCD with next TCD for identification of current TCD */ -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - handle->tcdPool[currentTcd].DLAST_SGA = - MEMORY_ConvertMemoryMapAddress((uint32_t)&handle->tcdPool[nextTcd], kMEMORY_Local2DMA); -#else - handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + EDMA_TCD_DLAST_SGA((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) = + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ if (currentTcd != previousTcd) { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif /* Enable scatter/gather feature in the previous TCD block. */ - csr = handle->tcdPool[previousTcd].CSR | ((uint16_t)DMA_CSR_ESG_MASK); + csr = EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) | + ((uint16_t)DMA_CSR_ESG_MASK); csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); - handle->tcdPool[previousTcd].CSR = csr; + EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) = csr; /* Check if the TCD block in the registers is the previous one (points to current TCD block). It is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to link the TCD register in case link the current TCD with the dead chain when TCD loading occurs before link the previous TCD block. */ -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - if (tcdRegs->DLAST_SGA == - MEMORY_ConvertMemoryMapAddress((uint32_t)&handle->tcdPool[currentTcd], kMEMORY_Local2DMA)) -#else - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) { /* Clear the DREQ bits for the dynamic scatter gather */ - tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_DREQ_MASK; /* Enable scatter/gather also in the TCD registers. */ - csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + csr = EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) | DMA_CSR_ESG_MASK; /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ - tcdRegs->CSR = csr; + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) = csr; /* It is very important to check the ESG bit! Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can @@ -1540,9 +2204,9 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic link succeed. */ - if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + if (0U != (EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK)) { - tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK; return kStatus_Success; } /* @@ -1550,12 +2214,8 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t condition when ESG bit is not set: it means the dynamic TCD link succeed and the current TCD block has been loaded into TCD registers. */ -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - if (tcdRegs->DLAST_SGA == - MEMORY_ConvertMemoryMapAddress((uint32_t)&handle->tcdPool[nextTcd], kMEMORY_Local2DMA)) -#else - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) { return kStatus_Success; } @@ -1564,7 +2224,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t So shall configure TCD registers. */ } - else if (tcdRegs->DLAST_SGA != 0UL) + else if (EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) != 0UL) { /* The current TCD block has been linked successfully. */ return kStatus_Success; @@ -1607,8 +2267,8 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t * itself. * * retval #kStatus_Success It means submit transfer request succeed - * retval #kStatus_EDMA_ChannelBusy channel is in busy status - * retval #kStatus_EDMA_ChannelQueueFull It means TCD pool is not len enough for the ring transfer request + * retval #kStatus_EDMA_Busy channel is in busy status + * retval #kStatus_InvalidArgument Invalid Argument */ status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount) { @@ -1618,7 +2278,7 @@ status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t * uint32_t i = 0U; - if (handle->tcdSize < transferLoopCount) + if (handle->tcdSize < (int8_t)transferLoopCount) { return kStatus_InvalidArgument; } @@ -1640,24 +2300,30 @@ status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t * #else if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || #endif - (((handle->tcdBase->CITER & DMA_CITER_ELINKNO_CITER_MASK) != - (handle->tcdBase->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + (((EDMA_TCD_CITER(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_CITER_ELINKNO_CITER_MASK) != + (EDMA_TCD_BITER(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_BITER_ELINKNO_BITER_MASK)))) { return kStatus_EDMA_Busy; } - (void)memset(handle->tcdPool, 0, handle->tcdSize * sizeof(edma_tcd_t)); + (void)memset(handle->tcdPool, 0, (uint32_t)handle->tcdSize * sizeof(edma_tcd_t)); for (i = 0U; i < transferLoopCount - 1UL; i++) { transfer[i].linkTCD = &handle->tcdPool[i + 1UL]; - EDMA_ConfigChannelSoftwareTCD(&(handle->tcdPool[i]), &transfer[i]); + EDMA_ConfigChannelSoftwareTCDExt(handle->base, &(handle->tcdPool[i]), &transfer[i]); +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &(handle->tcdPool[i])) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif } /* prepare last one in the ring and link it to the HEAD of the ring */ transfer[i].linkTCD = &handle->tcdPool[0]; - EDMA_ConfigChannelSoftwareTCD(&(handle->tcdPool[i]), &transfer[i]); + EDMA_ConfigChannelSoftwareTCDExt(handle->base, &(handle->tcdPool[i]), &transfer[i]); -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) { EDMA_EnableMinorLoopMapping(handle->psBase, true); @@ -1668,7 +2334,7 @@ status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t * /* enable interrupt */ EDMA_EnableChannelInterrupts(handle->base, handle->channel, - transfer->enabledInterruptMask & ~((uint16_t)kEDMA_ErrorInterruptEnable)); + ((uint32_t)transfer->enabledInterruptMask & ~((uint32_t)kEDMA_ErrorInterruptEnable))); return kStatus_Success; } @@ -1687,7 +2353,7 @@ void EDMA_StartTransfer(edma_handle_t *handle) edma_tcd_t *tcdRegs = handle->tcdBase; -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA if (handle->tcdPool == NULL) { handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); @@ -1718,11 +2384,31 @@ void EDMA_StartTransfer(edma_handle_t *handle) } } #else - if (handle->channelBase->CH_MUX == 0U) +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX +#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX + if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && + (EDMA_MP_BASE(handle->base)->MP_REGS.EDMA5_REG.CH_MUX[handle->channel] == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(handle->base) == 1U)) { - tcdRegs->CSR |= DMA_CSR_START_MASK; + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_START_MASK; } - else if (handle->tcdPool == NULL) + else if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && + handle->channelBase->CH_REGS.EDMA4_REG.CH_MUX == 0U && + !(FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(handle->base) == 1U)) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_START_MASK; + } + else +#else + if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && + handle->channelBase->CH_REGS.EDMA4_REG.CH_MUX == 0U) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_START_MASK; + } + else +#endif +#endif + if (handle->tcdPool == NULL) { handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; } @@ -1733,7 +2419,7 @@ void EDMA_StartTransfer(edma_handle_t *handle) { /* Check if transfer is paused. */ if ((!((handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U)) || - ((tcdRegs->CSR & DMA_CSR_ESG_MASK) != 0U)) + ((EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) != 0U)) { /* Re-enable channel request must be as soon as possible, so must put it into @@ -1757,7 +2443,7 @@ void EDMA_StartTransfer(edma_handle_t *handle) void EDMA_StopTransfer(edma_handle_t *handle) { assert(handle != NULL); -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); #else handle->channelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_ERQ_MASK)); @@ -1780,7 +2466,7 @@ void EDMA_AbortTransfer(edma_handle_t *handle) CSR will be not zero. Because if it is the last transfer, DREQ will be set. If not, ESG will be set. */ - EDMA_TcdReset(handle->tcdBase); + EDMA_TcdResetExt(handle->base, handle->tcdBase); /* Handle the tcd */ if (handle->tcdPool != NULL) @@ -1825,14 +2511,14 @@ void EDMA_HandleIRQ(edma_handle_t *handle) bool transfer_done; -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA /* Check if transfer is already finished. */ transfer_done = ((handle->tcdBase->CSR & DMA_CSR_DONE_MASK) != 0U); #else - transfer_done = handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK; + transfer_done = (bool)(handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK); #endif -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA if ((handle->base->INT >> channel) != 0U) { handle->base->CINT = channel; @@ -1853,18 +2539,14 @@ void EDMA_HandleIRQ(edma_handle_t *handle) } else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ { - uint32_t sga = (uint32_t)((edma_tcd_t *)(handle->tcdBase))->DLAST_SGA; + uint32_t sga = (uint32_t)EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)); uint32_t sga_index; int32_t tcds_done; uint8_t new_header; - bool esg = ((handle->tcdBase->CSR & DMA_CSR_ESG_MASK) != 0U); + bool esg = ((EDMA_TCD_CSR(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) != 0U); /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ -#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - sga -= MEMORY_ConvertMemoryMapAddress((uint32_t)handle->tcdPool, kMEMORY_Local2DMA); -#else - sga -= (uint32_t)handle->tcdPool; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + sga -= CONVERT_TO_DMA_ADDRESS((uint32_t)handle->tcdPool); /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ sga_index = sga / sizeof(edma_tcd_t); /* Adjust header positions. */ @@ -1913,7 +2595,7 @@ void EDMA_HandleIRQ(edma_handle_t *handle) */ if (transfer_done) { -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA handle->base->CDNE = handle->channel; #else handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; @@ -1942,9 +2624,9 @@ void EDMA_HandleIRQ(edma_handle_t *handle) */ if (transfer_done) { - if ((handle->tcdBase->CSR & DMA_CSR_ESG_MASK) != 0U) + if ((EDMA_TCD_CSR(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) != 0U) { -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA handle->base->CDNE = handle->channel; #else handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; @@ -1957,7 +2639,7 @@ void EDMA_HandleIRQ(edma_handle_t *handle) void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel) { -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA if ((s_edmaBases[instance]->INT >> channel) != 0U) { EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h index 62a0a72401..aafd8603ee 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h @@ -1,12 +1,12 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_EDMA_H_ -#define _FSL_EDMA_H_ +#ifndef FSL_EDMA_H_ +#define FSL_EDMA_H_ #include "fsl_common.h" #include "fsl_edma_core.h" @@ -20,10 +20,18 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) /*!< Version 2.5.1. */ -/*@}*/ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 0)) /*!< Version 2.10.0. */ +/*! @} */ + +/*! @brief eDMA driver name */ +#ifndef FSL_EDMA_DRIVER_EDMA4 +#define FSL_EDMA_DRIVER_EDMA4 (1) +#endif + +/*!@brief Macro used for allocate edma TCD */ +#define EDMA_ALLOCATE_TCD(name, number) AT_NONCACHEABLE_SECTION_ALIGN(edma_tcd_t name[number], EDMA_TCD_ALIGN_SIZE) /*! @brief _edma_transfer_status eDMA transfer status */ enum @@ -120,32 +128,30 @@ enum kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ }; -#if FSL_EDMA_SOC_IP_EDMA /*! @brief _edma_error_status_flags eDMA channel error status flags. */ enum { - kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ - kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ - kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ - kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ - kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ - kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ - kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ - kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ - kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ - kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ - kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ + kEDMA_DestinationBusErrorFlag = DMA_ERR_DBE_FLAG, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ERR_SBE_FLAG, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ERR_SGE_FLAG, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ERR_NCE_FLAG, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ERR_DOE_FLAG, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ERR_DAE_FLAG, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ERR_SOE_FLAG, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ERR_SAE_FLAG, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ERR_ERRCHAN_FLAG, /*!< Error channel number of the cancelled channel number */ +#if defined(FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR) && (FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR > 1) + kEDMA_ChannelPriorityErrorFlag = DMA_ERR_CPE_FLAG, /*!< Channel priority is not unique. */ +#endif + kEDMA_TransferCanceledFlag = DMA_ERR_ECX_FLAG, /*!< Transfer cancelled */ #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) - kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ + kEDMA_GroupPriorityErrorFlag = DMA_ERR_GPE_FLAG, /*!< Group priority is not unique. */ #endif - kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ + kEDMA_ValidFlag = (int)DMA_ERR_FLAG, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ }; -#endif -/*! @brief eDMA interrupt source - * @anchor edma_interrupt_enable_t - */ -enum _edma_interrupt_enable +/*! @brief _edma_interrupt_enable eDMA interrupt source */ +enum { kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ @@ -178,7 +184,7 @@ typedef struct _edma_minor_offset_config } edma_minor_offset_config_t; #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG -#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE /*! @brief eDMA channel memory attribute */ typedef enum edma_channel_memory_attribute { @@ -240,24 +246,29 @@ typedef enum _edma_channel_access_type } edma_channel_access_type_t; #endif +/*! @brief eDMA4 channel protection level */ typedef enum _edma_channel_protection_level { kEDMA_ChannelProtectionLevelUser = 0x0U, /*!< user protection level for eDMA transfers. */ kEDMA_ChannelProtectionLevelPrivileged = 0x1U, /*!< Privileged protection level eDMA transfers. */ } edma_channel_protection_level_t; +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + +/*! @brief eDMA4 channel security level */ typedef enum _edma_channel_security_level { kEDMA_ChannelSecurityLevelNonSecure = 0x0U, /*!< non secure level for eDMA transfers. */ kEDMA_ChannelSecurityLevelSecure = 0x1U, /*!< secure level for eDMA transfers. */ } edma_channel_security_level_t; +#endif /*! @brief eDMA4 channel configuration*/ typedef struct _edma_channel_config { edma_channel_Preemption_config_t channelPreemptionConfig; /*!< channel preemption configuration */ -#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE edma_channel_memory_attribute_t channelReadMemoryAttribute; /*!< channel memory read attribute configuration */ edma_channel_memory_attribute_t channelWriteMemoryAttribute; /*!< channel memory write attribute configuration */ #endif @@ -272,10 +283,14 @@ typedef struct _edma_channel_config uint8_t channelDataSignExtensionBitPosition; /*!< channel data sign extension bit psition configuration */ - dma_request_source_t channelRequestSource; /*!< hardware service request source for the channel */ +#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX) + int channelRequestSource; /*!< hardware service request source for the channel */ +#endif bool enableMasterIDReplication; /*!< enable master ID replication */ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) edma_channel_security_level_t securityLevel; /*!< security level */ +#endif edma_channel_protection_level_t protectionLevel; /*!< protection level */ } edma_channel_config_t; @@ -331,33 +346,32 @@ typedef struct _edma_transfer_config edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ int16_t srcOffset; /*!< Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed */ - int16_t destOffset; /*!< Sign-extended offset value in byte unit applied to the current destination - address to form the next-state value as each destination write is completed. */ - uint32_t minorLoopBytes; /*!< bytes in each minor loop or each request - * range: 1 - (2^30 -1) when minor loop mapping is enabled - * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor - * loop offset is enabled - * range: 1 - (2^32 - 1) when minor loop mapping is disabled - */ - uint32_t majorLoopCounts; /*!< minor loop counts in each major loop, should be 1 at least for each - * transfer range: (0 - (2^15 - 1)) when minor loop channel link is - * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled - * total bytes in a transfer = minorLoopCountsEachMajorLoop * - * bytesEachMinorLoop - */ + int16_t destOffset; /*!< Sign-extended offset value in byte unit applied to the current destination + address to form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< bytes in each minor loop or each request + * range: 1 - (2^30 -1) when minor loop mapping is enabled + * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor + * loop offset is enabled + * range: 1 - (2^32 - 1) when minor loop mapping is disabled + */ + uint32_t majorLoopCounts; /*!< minor loop counts in each major loop, should be 1 at least for each + * transfer range: (0 - (2^15 - 1)) when minor loop channel link is + * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled + * total bytes in a transfer = minorLoopCountsEachMajorLoop * + * bytesEachMinorLoop + */ - uint16_t enabledInterruptMask; /*!< channel interrupt to enable, can be OR'ed value of @ref - _edma_channel_interrupt_enable */ + uint16_t enabledInterruptMask; /*!< channel interrupt to enable, can be OR'ed value of _edma_interrupt_enable */ - edma_modulo_t srcAddrModulo; /*!< source circular data queue range */ - int32_t srcMajorLoopOffset; /*!< source major loop offset */ + edma_modulo_t srcAddrModulo; /*!< source circular data queue range */ + int32_t srcMajorLoopOffset; /*!< source major loop offset */ - edma_modulo_t dstAddrModulo; /*!< destination circular data queue range */ - int32_t dstMajorLoopOffset; /*!< destination major loop offset */ + edma_modulo_t dstAddrModulo; /*!< destination circular data queue range */ + int32_t dstMajorLoopOffset; /*!< destination major loop offset */ - bool enableSrcMinorLoopOffset; /*!< enable source minor loop offset */ - bool enableDstMinorLoopOffset; /*!< enable dest minor loop offset */ - int32_t minorLoopOffset; /*!< burst offset, the offset will be applied after minor loop update */ + bool enableSrcMinorLoopOffset; /*!< enable source minor loop offset */ + bool enableDstMinorLoopOffset; /*!< enable dest minor loop offset */ + int32_t minorLoopOffset; /*!< burst offset, the offset will be applied after minor loop update */ bool enableChannelMajorLoopLink; /*!< channel link when major loop complete */ uint32_t majorLoopLinkChannel; /*!< major loop link channel number */ @@ -365,9 +379,7 @@ typedef struct _edma_transfer_config bool enableChannelMinorLoopLink; /*!< channel link when minor loop complete */ uint32_t minorLoopLinkChannel; /*!< minor loop link channel number */ - bool enableChannelRequest; /*!< enable the channel request signal */ - - edma_tcd_t *linkTCD; /*!< pointer to the link transfer control descriptor */ + edma_tcd_t *linkTCD; /*!< pointer to the link transfer control descriptor */ } edma_transfer_config_t; /*! @brief eDMA global configuration structure.*/ @@ -387,16 +399,16 @@ typedef struct _edma_config bool enableGlobalChannelLink; /*!< Enable(true) channel linking is available and controlled by each channel's link settings. */ - bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. - Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ - bool enableDebugMode; /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of - a new channel. Executing channels are allowed to complete. */ + bool enableDebugMode; /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of + a new channel. Executing channels are allowed to complete. */ bool enableRoundRobinArbitration; /*!< Enable(true) channel linking is available and controlled by each channel's link settings. */ #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG - edma_channel_config_t *channelConfig[FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL]; /*!< channel preemption configuration */ + edma_channel_config_t *channelConfig[FSL_FEATURE_EDMA_MODULE_CHANNEL]; /*!< channel preemption configuration */ #endif } edma_config_t; @@ -432,11 +444,11 @@ typedef struct _edma_handle #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG EDMA_ChannelType *channelBase; /*!< eDMA peripheral channel base address. */ #endif - EDMA_Type *base; /*!< eDMA peripheral base address*/ - EDMA_TCDType *tcdBase; /*!< eDMA peripheral tcd base address. */ + EDMA_Type *base; /*!< eDMA peripheral base address*/ + EDMA_TCDType *tcdBase; /*!< eDMA peripheral tcd base address. */ - edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ - uint32_t channel; /*!< eDMA channel number. */ + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint32_t channel; /*!< eDMA channel number. */ volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ @@ -550,7 +562,7 @@ static inline void EDMA_EnableMinorLoopMapping(EDMA_Type *base, bool enable) } #endif -/* @} */ +/*! @} */ /*! * @name eDMA Channel Operation * @{ @@ -566,7 +578,7 @@ static inline void EDMA_EnableMinorLoopMapping(EDMA_Type *base, bool enable) */ void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig); -#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE /*! * @brief Set channel memory attribute. * @@ -580,12 +592,22 @@ static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (0U != (uint32_t)FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base)) + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(base)) { - EDMA_CHANNEL_BASE(base, channel)->CH_MATTR = - DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); +#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(base) == 1U) + { + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA5_REG.CH_MATTR = + DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); + } + else +#endif + { + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MATTR = + DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); + } } } #endif @@ -601,13 +623,13 @@ static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, */ static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (0U != (uint32_t)FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base)) + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(base)) { EDMA_CHANNEL_BASE(base, channel)->CH_CSR = (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SIGNEXT_MASK)) | - (position << DMA_CH_CSR_SIGNEXT_SHIFT); + ((uint32_t)position << DMA_CH_CSR_SIGNEXT_SHIFT); } } #endif @@ -623,12 +645,13 @@ static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channe */ static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (0U != (uint32_t)FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base)) + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(base)) { EDMA_CHANNEL_BASE(base, channel)->CH_CSR = - (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | (swapSize << DMA_CH_CSR_SWAP_SHIFT); + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | + ((uint32_t)swapSize << DMA_CH_CSR_SWAP_SHIFT); } } #endif @@ -645,29 +668,64 @@ static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (0U != (uint32_t)FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base)) + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(base)) { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR = - (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) | - (channelAccessType << DMA_CH_SBR_INSTR_SHIFT); +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] = + (EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] & (~DMA_CH_SBR_INSTR_MASK)) | + ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT); + } + else +#endif + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR = + (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) | + ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT); + } } } #endif + +#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || \ + (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX) /*! * @brief Set channel request source. * * @param base eDMA peripheral base address. * @param channel eDMA channel number. - * @param channelRequestSource eDMA hardware service request source for the channel. + * @param channelRequestSource eDMA hardware service request source for the channel. User need to use + * the dma_request_source_t type as the input parameter. Note that devices + * may use other enum type to express dma request source and User can fined it in + * SOC header or fsl_edma_soc.h. */ -static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, dma_request_source_t channelRequestSource) +static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, int32_t channelRequestSource) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - EDMA_CHANNEL_BASE(base, channel)->CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource); + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(base) == 1U) + { + /* Reset channel mux */ +#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(base) == 1U) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_MUX[channel] = DMA_CH_MUX_SOURCE(0); + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_MUX[channel] = DMA_CH_MUX_SOURCE(channelRequestSource); + } + else +#endif + { +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MUX = DMA_CH_MUX_SOURCE(0); + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource); +#endif + } + } } +#endif /*! * @brief Gets the channel identification and attribute information on the system bus interface. @@ -679,7 +737,7 @@ static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, dma_req */ static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); return EDMA_CHANNEL_BASE(base, channel)->CH_SBR; } @@ -693,18 +751,35 @@ static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint */ static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (enable) +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK; + if (enable) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_EMI_MASK; + } + else + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_EMI_MASK; + } } else +#endif { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK; + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK; + } } } +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) /*! * @brief Set channel security level. * @@ -714,17 +789,34 @@ static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32 */ static inline void EDMA_SetChannelSecurityLevel(EDMA_Type *base, uint32_t channel, edma_channel_security_level_t level) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (level == kEDMA_ChannelSecurityLevelSecure) +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK; + if (level == kEDMA_ChannelSecurityLevelSecure) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_SEC_MASK; + } + else + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_SEC_MASK; + } } else +#endif { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK; + if (level == kEDMA_ChannelSecurityLevelSecure) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK; + } } } +#endif /*! * @brief Set channel security level. @@ -737,15 +829,31 @@ static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); - if (level == kEDMA_ChannelProtectionLevelPrivileged) +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK; + if (level == kEDMA_ChannelProtectionLevelPrivileged) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_PAL_MASK; + } + else + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_PAL_MASK; + } } else +#endif { - EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK; + if (level == kEDMA_ChannelProtectionLevelPrivileged) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK; + } } } @@ -866,6 +974,7 @@ void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandW */ void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT /*! * @brief Enables an async request for the eDMA transfer. * @@ -875,9 +984,9 @@ void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, */ static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA EDMA_BASE(base)->EARS &= ~((uint32_t)1U << channel); EDMA_BASE(base)->EARS |= ((uint32_t)(true == enable ? 1U : 0U) << channel); #else @@ -891,6 +1000,7 @@ static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bo } #endif } +#endif /*! * @brief Enables an auto stop request for the eDMA transfer. @@ -903,15 +1013,15 @@ static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bo */ static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); if (enable) { - EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_DREQ_MASK; + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_DREQ_MASK; } else { - EDMA_TCD_BASE(base, channel)->CSR &= ~DMA_CSR_DREQ_MASK; + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK; } } @@ -947,14 +1057,17 @@ void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t m */ void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset); -/* @} */ +/*! @} */ /*! * @name eDMA TCD Operation * @{ */ /*! * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref - * edma4_channel_transfer_config_t. + * edma_transfer_config_t. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_ConfigChannelSoftwareTCDExt * * Application should be careful about the TCD pool buffer storage class, * - For the platform has cache, the software TCD should be put in non cache section @@ -970,6 +1083,9 @@ void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t /*! * @brief Sets all fields to default values for the TCD structure. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdResetExt + * * This function sets all fields for this TCD structure to default value. * * @param tcd Pointer to the TCD structure. @@ -980,6 +1096,9 @@ void EDMA_TcdReset(edma_tcd_t *tcd); /*! * @brief Configures the eDMA TCD transfer attribute. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetTransferConfigExt + * * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. * The TCD is used in the scatter-gather mode. * This function configures the TCD transfer attribute, including source address, destination address, @@ -1009,6 +1128,9 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co /*! * @brief Configures the eDMA TCD minor offset feature. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetMinorOffsetConfigExt + * * A minor offset is a signed-extended value added to the source address or a destination * address after each minor loop. * @@ -1020,6 +1142,9 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi /*! * @brief Sets the channel link for the eDMA TCD. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetChannelLinkExt + * * This function configures either a minor link or a major link. The minor link means the channel link is * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is * exhausted. @@ -1038,6 +1163,9 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint /*! * @brief Sets the bandwidth for the eDMA TCD. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetBandWidthExt + * * Because the eDMA processes the minor loop, it continuously generates read/write sequences * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of * each read/write access to control the bus request bandwidth seen by the crossbar switch. @@ -1050,15 +1178,18 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); - tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = + (uint16_t)((EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); } #endif /*! * @brief Sets the source modulo and the destination modulo for the eDMA TCD. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetModuloExt + * * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) * calculation is performed or the original register value. It provides the ability to implement a circular data * queue easily. @@ -1072,6 +1203,9 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d /*! * @brief Sets the auto stop request for the eDMA TCD. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdEnableAutoStopRequestExt + * * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. * * @param tcd A pointer to the TCD structure. @@ -1080,14 +1214,17 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0U); - tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = (uint16_t)((EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~DMA_CSR_DREQ_MASK)) | + DMA_CSR_DREQ((true == enable ? 1U : 0U))); } /*! * @brief Enables the interrupt source for the eDMA TCD. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdEnableInterruptsExt + * * @param tcd Point to the TCD structure. * @param mask The mask of interrupt source to be set. Users need to use * the defined edma_interrupt_enable_t type. @@ -1097,6 +1234,9 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); /*! * @brief Disables the interrupt source for the eDMA TCD. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdDisableInterruptsExt + * * @param tcd Point to the TCD structure. * @param mask The mask of interrupt source to be set. Users need to use * the defined edma_interrupt_enable_t type. @@ -1106,6 +1246,9 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); /*! * @brief Configures the eDMA TCD major offset feature. * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetMajorOffsetConfigExt + * * Adjustment value added to the source address at the completion of the major iteration count * * @param tcd A point to the TCD structure. @@ -1114,6 +1257,184 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); */ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset); +/*! + * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * @param base eDMA peripheral base address. + * @param tcd Pointer to the TCD structure. + * @param transfer channel transfer configuration pointer. + * + * @note This function enables the auto stop request feature. + */ +void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer); + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param base eDMA peripheral base address. + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, + edma_tcd_t *tcd, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param base eDMA peripheral base address. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param base eDMA peripheral base address. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = + (uint16_t)((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~DMA_CSR_DREQ_MASK)) | + DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param base eDMA peripheral base address. + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param base eDMA peripheral base address. + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param base eDMA peripheral base address. + * @param tcd A point to the TCD structure. + * @param sourceOffset source address offset wiil be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset); + /*! @} */ /*! * @name eDMA Channel Transfer Operation @@ -1130,9 +1451,9 @@ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t */ static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA EDMA_BASE(base)->SERQ = DMA_SERQ_SERQ(channel); #else EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; @@ -1149,9 +1470,9 @@ static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel) */ static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA EDMA_BASE(base)->CERQ = DMA_CERQ_CERQ(channel); #else EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; @@ -1168,12 +1489,12 @@ static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel) */ static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel) { - assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL(base)); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA EDMA_BASE(base)->SSRT = DMA_SSRT_SSRT(channel); #else - EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_START_MASK; + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_START_MASK; #endif } @@ -1215,7 +1536,7 @@ uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel); */ static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base) { -#if FSL_EDMA_SOC_IP_EDMA +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA return EDMA_BASE(base)->ES; #else return EDMA_MP_BASE(base)->MP_ES; @@ -1303,6 +1624,8 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD * @note The data address and the data width must be consistent. For example, if the SRC * is 4 bytes, the source address must be 4 bytes aligned, or it results in * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. */ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, @@ -1340,6 +1663,94 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, uint32_t transferBytes, edma_transfer_type_t type); +/*! + * @brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param nextTcd eDMA transfer linked TCD address. + * + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd); + +/*! + * @brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * @code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 2. submit static link transfer, + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * 3. submit dynamic link transfer + * @code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 4. submit loop transfer + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd); + /*! * @brief Submits the eDMA transfer request. * @@ -1372,18 +1783,16 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t * @note Application should check the return value of this function to avoid transfer request * submit failed * - * @param psHandle eDMA handle pointer - * @param psTransfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * @param handle eDMA handle pointer + * @param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail * @param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to * itself. * * @retval #kStatus_Success It means submit transfer request succeed - * @retval #kStatus_EDMA_ChannelBusy channel is in busy status - * @retval #kStatus_EDMA_ChannelQueueFull It means TCD pool is not len enough for the ring transfer request + * @retval #kStatus_EDMA_Busy channel is in busy status + * @retval #kStatus_InvalidArgument Invalid Argument */ -status_t EDMA_SubmitLoopTransfer(edma_handle_t *psHandle, - edma_transfer_config_t *psTransfer, - uint32_t transferLoopCount); +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount); /*! * @brief eDMA starts transfer. @@ -1440,7 +1849,7 @@ static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) */ static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) { - return (uint32_t)(handle->tcdBase->DLAST_SGA); + return (uint32_t)(EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base))); } /*! @@ -1473,12 +1882,12 @@ static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) */ void EDMA_HandleIRQ(edma_handle_t *handle); -/* @} */ +/*! @} */ #if defined(__cplusplus) } #endif /* __cplusplus */ -/* @} */ +/*! @} */ -#endif /*_FSL_EDMA_H_*/ +#endif /*FSL_EDMA_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h index 49c6c1fc42..482f4e1988 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_EDMA_CORE_H_ -#define _FSL_EDMA_CORE_H_ +#ifndef FSL_EDMA_CORE_H_ +#define FSL_EDMA_CORE_H_ #include "fsl_edma_soc.h" @@ -17,163 +17,209 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4 -#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK -#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK -#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK -#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK -#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK -#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK -#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK -#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT -#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK -#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT -#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK -#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK -#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK -#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK -#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK -#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK -#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK -#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK -#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK -#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x) -#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X) -#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x) -#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) -#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) -#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) -#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x) -#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x) -#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x) -#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x) -#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x) -#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x) -#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK -#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT -#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK -#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT -#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK -#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT -#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x) -#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \ - (!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4)) -#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK -#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK -#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK -#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK -#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK -#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK -#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK -#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT -#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK -#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT -#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK -#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK -#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK -#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK -#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK -#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK -#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK -#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK -#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK -#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x) -#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X) -#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x) -#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) -#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) -#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) -#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x) -#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x) -#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x) -#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x) -#define DMA_CH_MUX_SOURCE(x) DMA_CH_MUX_SRC(x) -#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \ - (!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3)) -#define DMA_CSR_INTMAJOR_MASK DMA4_CSR_INTMAJOR_MASK -#define DMA_CSR_INTHALF_MASK DMA4_CSR_INTHALF_MASK -#define DMA_CSR_DREQ_MASK DMA4_CSR_DREQ_MASK -#define DMA_CSR_ESG_MASK DMA4_CSR_ESG_MASK -#define DMA_CSR_START_MASK DMA4_CSR_START_MASK -#define DMA_CITER_ELINKNO_CITER_MASK DMA4_CITER_ELINKNO_CITER_MASK -#define DMA_BITER_ELINKNO_BITER_MASK DMA4_BITER_ELINKNO_BITER_MASK -#define DMA_CITER_ELINKNO_CITER_SHIFT DMA4_CITER_ELINKNO_CITER_SHIFT -#define DMA_CITER_ELINKYES_CITER_MASK DMA4_CITER_ELINKYES_CITER_MASK -#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT -#define DMA_ATTR_SMOD_MASK DMA4_ATTR_SMOD_MASK -#define DMA_ATTR_DMOD_MASK DMA4_ATTR_DMOD_MASK -#define DMA_CITER_ELINKNO_ELINK_MASK DMA4_CITER_ELINKNO_ELINK_MASK -#define DMA_CSR_MAJORELINK_MASK DMA4_CSR_MAJORELINK_MASK -#define DMA_BITER_ELINKYES_ELINK_MASK DMA4_BITER_ELINKYES_ELINK_MASK -#define DMA_CITER_ELINKYES_ELINK_MASK DMA4_CITER_ELINKYES_ELINK_MASK -#define DMA_CSR_MAJORLINKCH_MASK DMA4_CSR_MAJORLINKCH_MASK -#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK -#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK -#define DMA_ATTR_DMOD(x) DMA4_ATTR_DMOD(x) -#define DMA_ATTR_SMOD(X) DMA4_ATTR_SMOD(X) -#define DMA_BITER_ELINKYES_LINKCH(x) DMA4_BITER_ELINKYES_LINKCH(x) -#define DMA_CITER_ELINKYES_LINKCH(x) DMA4_CITER_ELINKYES_LINKCH(x) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA4_NBYTES_MLOFFYES_MLOFF(x) -#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA4_NBYTES_MLOFFYES_DMLOE(x) -#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA4_NBYTES_MLOFFYES_SMLOE(x) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA4_NBYTES_MLOFFNO_NBYTES(x) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA4_NBYTES_MLOFFYES_NBYTES(x) -#define DMA_ATTR_DSIZE(x) DMA4_ATTR_DSIZE(x) -#define DMA_ATTR_SSIZE(x) DMA4_ATTR_SSIZE(x) -#define DMA_CSR_DREQ(x) DMA4_CSR_DREQ(x) -#define DMA_CSR_MAJORLINKCH(x) DMA4_CSR_MAJORLINKCH(x) -#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x) -#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x) -#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK -#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT -#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK -#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT -#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK -#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT -#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x) -#define DMA_CH_CSR_DONE_MASK DMA4_CH_CSR_DONE_MASK -#define DMA_CH_CSR_ERQ_MASK DMA4_CH_CSR_ERQ_MASK -#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA -/*! intentional empty */ +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << (14U))) & (0xC000U)) +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0xF8U)) +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << (11U))) & (0xF800U)) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U)) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U)) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << (10U))) & (0x3FFFFC00U)) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << (30U))) & (0x40000000U)) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << (31U))) & (0x80000000U)) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFFFFFFU)) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFU)) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0x7U)) +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x700U)) +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0x8U)) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x1F00U)) +#define DMA_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << (4U))) & (0xF0U)) +#define DMA_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0xFU)) +#define DMA_CH_CSR_SIGNEXT_MASK (0x3F0000U) +#define DMA_CH_CSR_SIGNEXT_SHIFT (16U) +#define DMA_CH_CSR_SWAP_MASK (0xF000U) +#define DMA_CH_CSR_SWAP_SHIFT (12U) +#define DMA_CH_SBR_INSTR_MASK (0x2000U) +#define DMA_CH_SBR_INSTR_SHIFT (13U) +#define DMA_CH_MUX_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0xFFU)) + +/*! @brief DMA error flag */ +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA +#define DMA_ERR_DBE_FLAG DMA_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK +#define DMA_ERR_CPE_FLAG DMA_ES_CPE_MASK +#define DMA_ERR_ECX_FLAG DMA_ES_ECX_MASK +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) +#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK #endif +#define DMA_ERR_FLAG DMA_ES_VLD_MASK + +/*! @brief get/clear DONE status*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT) +/*! @brief enable/disable error interrupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (base->EEI |= ((uint32_t)0x1U << channel)) +#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel))) +/*! @brief get/clear error status*/ +#define DMA_GET_ERROR_STATUS(base, channel) (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U) +#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel) +/*! @brief get/clear int status*/ +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U)) +#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel) + +#else + +#define DMA_ERR_DBE_FLAG DMA_MP_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_MP_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_MP_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_MP_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_MP_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_MP_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_MP_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_MP_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_MP_ES_ERRCHN_MASK +#define DMA_ERR_ECX_FLAG DMA_MP_ES_ECX_MASK +#define DMA_ERR_FLAG DMA_MP_ES_VLD_MASK + +/*! @brief get/clear DONE bit*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT) +/*! @brief enable/disable error interupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK) +#define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK) +/*! @brief get/clear error status*/ +#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK) +#define DMA_GET_ERROR_STATUS(base, channel) \ + (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U) +/*! @brief get/clear INT status*/ +#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK) +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U)) +#endif /*FSL_EDMA_SOC_IP_EDMA*/ + +/*! @brief enable/dsiable MAJOR/HALF INT*/ +#define DMA_ENABLE_MAJOR_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK) +#define DMA_ENABLE_HALF_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK) +#define DMA_DISABLE_MAJOR_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK) +#define DMA_DISABLE_HALF_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK) + +/*!@brief EDMA tcd align size */ +#define EDMA_TCD_ALIGN_SIZE (32U) /*!@brief edma core channel struture definition */ typedef struct _edma_core_mp { __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ + union + { + struct + { + __IO uint32_t MP_INT_LOW; /**< Channel Control and Status, array offset: 0x10008, array step: 0x10000 */ + __I uint32_t MP_INT_HIGH; /**< Channel Control and Status, array offset: 0x1000C, array step: 0x10000 */ + __I uint32_t MP_HRS_LOW; /**< Channel Control and Status, array offset: 0x10010, array step: 0x10000 */ + __I uint32_t MP_HRS_HIGH; /**< Channel Control and Status, array offset: 0x10014, array step: 0x10000 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MP_STOPCH; /**< Channel Control and Status, array offset: 0x10020, array step: 0x10000 */ + uint8_t RESERVED_1[12]; + __I uint32_t MP_SSR_LOW; /**< Channel Control and Status, array offset: 0x10030, array step: 0x10000 */ + __I uint32_t MP_SSR_HIGH; /**< Channel Control and Status, array offset: 0x10034, array step: 0x10000 */ + uint8_t RESERVED_2[200]; + __IO uint32_t CH_GRPRI[64]; /**< Channel Control and Status, array offset: 0x10100, array step: 0x10000 */ + __IO uint32_t CH_MUX[64]; /**< Channel Control and Status, array offset: 0x10200, array step: 0x10000 */ + uint8_t RESERVED_3[256]; + __IO uint32_t CH_PROT[64]; /**< Channel Control and Status, array offset: 0x10400, array step: 0x10000 */ + } EDMA5_REG; + } MP_REGS; } edma_core_mp_t; /*!@brief edma core channel struture definition */ typedef struct _edma_core_channel { - __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ - __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ - __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ - __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ - __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ - __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ - __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ + union + { + struct + { + __IO uint8_t RESERVED_1[4]; + __IO uint32_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ + } EDMA5_REG; + struct + { + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ + __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ + } EDMA4_REG; + } CH_REGS; } edma_core_channel_t; -/*!@brief edma core TCD struture definition */ -typedef struct _edma_core_tcd +/*! @brief eDMA tcd flag type */ +typedef enum _edma_tcd_type +{ + kEDMA_EDMA4Flag = 0x0U, /*!< Data access for eDMA4 transfers. */ + kEDMA_EDMA5Flag = 0x1U, /*!< Instruction access for eDMA4 transfers. */ +} edma_tcd_type_t; + +/*!@brief edma5 core TCD struture definition */ +typedef struct _edma5_core_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint32_t SADDR_HIGH; /*!< SADDR HIGH register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t SLAST_SDA_HIGH; /*!< SLAST SDA HIGH register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint32_t DADDR_HIGH; /*!< DADDR HIGH register, used for destination address */ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ + __IO uint32_t DLAST_SGA_HIGH; /*!< DLASTSGA HIGH register, next tcd address used in scatter-gather mode */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ + uint8_t RESERVED[16]; /*!< Aligned 64 bytes */ +} edma5_core_tcd_t; + +/*!@brief edma4 core TCD struture definition */ +typedef struct _edma4_core_tcd { __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ @@ -186,6 +232,18 @@ typedef struct _edma_core_tcd __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ __IO uint16_t CSR; /*!< CSR register, for TCD control status */ __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma4_core_tcd_t; + +/*!@brief edma core TCD struture definition */ +typedef struct _edma_core_tcd +{ + union + { + edma4_core_tcd_t edma4_tcd; +#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5 + edma5_core_tcd_t edma5_tcd; +#endif /* FSL_EDMA_SOC_IP_DMA5 */ + } TCD_REGS; } edma_core_tcd_t; /*!@brief EDMA typedef */ @@ -195,12 +253,91 @@ typedef void EDMA_Type; /*!@brief EDMA base address convert macro */ #define EDMA_BASE(base) -#define EDMA_CHANNEL_BASE(base, channel) \ - ((edma_core_channel_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base))) -#define EDMA_TCD_BASE(base, channel) \ - ((edma_core_tcd_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U)) -#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)base)) +#define EDMA_CHANNEL_BASE(base, channel) \ + ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base))) +#define EDMA_TCD_BASE(base, channel) \ + ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U)) +#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base))) +/*!@brief EDMA TCD type macro */ +#if defined FSL_FEATURE_EDMA_TCD_TYPEn +#define EDMA_TCD_TYPE(x) FSL_FEATURE_EDMA_TCD_TYPEn(x) +#else +#define EDMA_TCD_TYPE(x) (0) +#endif + +#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5 +/*!@brief EDMA TCD address convert macro */ +#define EDMA_TCD_SADDR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SADDR)))) + +#define EDMA_TCD_SOFF(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SOFF)))) + +#define EDMA_TCD_ATTR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->ATTR)))) + +#define EDMA_TCD_NBYTES(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->NBYTES)))) + +#define EDMA_TCD_SLAST(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SLAST)))) + +#define EDMA_TCD_DADDR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DADDR)))) + +#define EDMA_TCD_DOFF(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DOFF)))) + +#define EDMA_TCD_CITER(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CITER)))) + +#define EDMA_TCD_DLAST_SGA(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? \ + (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DLAST_SGA)))) + +#define EDMA_TCD_CSR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR)))) + +#define EDMA_TCD_BITER(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->BITER)))) +#else +/*!@brief EDMA TCD address convert macro */ +#define EDMA_TCD_SADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR) + +#define EDMA_TCD_SOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF) + +#define EDMA_TCD_ATTR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR) + +#define EDMA_TCD_NBYTES(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES) + +#define EDMA_TCD_SLAST(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST) + +#define EDMA_TCD_DADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR) + +#define EDMA_TCD_DOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF) + +#define EDMA_TCD_CITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER) + +#define EDMA_TCD_DLAST_SGA(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA) + +#define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR) + +#define EDMA_TCD_BITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER) +#endif /* FSL_EDMA_SOC_IP_DMA5 */ /******************************************************************************* * API ******************************************************************************/ @@ -217,4 +354,4 @@ extern "C" { * @} */ -#endif /* _FSL_EDMA_CORE_H_ */ +#endif /* FSL_EDMA_CORE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h index 7ae04eb48f..f955260e7a 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h @@ -45,151 +45,6 @@ } \ } -/*!@brief dma request source */ -typedef enum _dma_request_source -{ - kDmaRequestDisabled = 0U, /**< DSisabled*/ - kDmaRequestMuxFlexSpi0Rx = 1 | 0x100U, /**< FlexSPI0 Receive event */ - kDmaRequestMuxFlexSpi0Tx = 2 | 0x100U, /**< FlexSPI0 Transmit event */ - kDmaRequestMuxPinInt0 = 3 | 0x100U, /**< PinInt0 */ - kDmaRequestMuxPinInt1 = 4 | 0x100U, /**< PinInt1 */ - kDmaRequestMuxPinInt2 = 5 | 0x100U, /**< PinInt2 */ - kDmaRequestMuxPinInt3 = 6 | 0x100U, /**< PinInt3 */ - kDmaRequestMuxCtimer0M0 = 7 | 0x100U, /**< Ctimer0_M0 */ - kDmaRequestMuxCtimer0M1 = 8 | 0x100U, /**< Ctimer0_M1 */ - kDmaRequestMuxCtimer1M0 = 9 | 0x100U, /**< Ctimer1_M0 */ - kDmaRequestMuxCtimer1M1 = 10 | 0x100U, /**< Ctimer1_M1 */ - kDmaRequestMuxCtimer2M0 = 11 | 0x100U, /**< Ctimer2_M0 */ - kDmaRequestMuxCtimer2M1 = 12 | 0x100U, /**< Ctimer2_M1 */ - kDmaRequestMuxCtimer3M0 = 13 | 0x100U, /**< Ctimer3_M0 */ - kDmaRequestMuxCtimer3M1 = 14 | 0x100U, /**< Ctimer3_M1 */ - kDmaRequestMuxCtimer4M0 = 15 | 0x100U, /**< Ctimer4_M0 */ - kDmaRequestMuxCtimer5M1 = 16 | 0x100U, /**< Ctimer4_M1 */ - kDmaRequestMuxWuu0 = 17 | 0x100U, /**< Wake up event */ - kDmaRequestMuxMicfil0FifoRequest = 18 | 0x100U, /**< MICFIL0 FIFO_request */ - kDmaRequestMuxSct0Dma0 = 19 | 0x100U, /**< SCT0 DMA0 */ - kDmaRequestMuxSct0Dma1 = 20 | 0x100U, /**< SCT0 DMA1 */ - kDmaRequestMuxAdc0FifoARequest = 21 | 0x100U, /**< ADC0 FIFO A request */ - kDmaRequestMuxAdc0FifoBRequest = 22 | 0x100U, /**< ADC0 FIFO B request */ - kDmaRequestMuxAdc1FifoARequest = 23 | 0x100U, /**< ADC1 FIFO A request */ - kDmaRequestMuxAdc1FifoBRequest = 24 | 0x100U, /**< ADC1 FIFO B request */ - kDmaRequestMuxDac0FifoRequest = 25 | 0x100U, /**< DAC0 FIFO_request */ - kDmaRequestMuxDac1FifoRequest = 26 | 0x100U, /**< DAC1 FIFO_request */ - kDmaRequestMuxHpDac0FifoRequest = 27 | 0x100U, /**< HP DAC0 FIFO_request */ - kDmaRequestMuxHsCmp0DmaRequest = 28 | 0x100U, /**< HS CMP0 DMA_request */ - kDmaRequestMuxHsCmp1DmaRequest = 29 | 0x100U, /**< HS CMP0 DMA_request */ - kDmaRequestMuxHsCmp2DmaRequest = 30 | 0x100U, /**< HS CMP0 DMA_request */ - kDmaRequestMuxEvtg0Out0A = 31 | 0x100U, /**< EVTG0 OUT0A */ - kDmaRequestMuxEvtg0Out0B = 32 | 0x100U, /**< EVTG0 OUT0B */ - kDmaRequestMuxEvtg0Out1A = 33 | 0x100U, /**< EVTG0 OUT1A */ - kDmaRequestMuxEvtg0Out1B = 34 | 0x100U, /**< EVTG0 OUT1B */ - kDmaRequestMuxEvtg0Out2A = 35 | 0x100U, /**< EVTG0 OUT2A */ - kDmaRequestMuxEvtg0Out2B = 36 | 0x100U, /**< EVTG0 OUT2B */ - kDmaRequestMuxEvtg0Out3A = 37 | 0x100U, /**< EVTG0 OUT3A */ - kDmaRequestMuxEvtg0Out3B = 38 | 0x100U, /**< EVTG0 OUT3B */ - kDmaRequestMuxFlexPwm0ReqCapt0 = 39 | 0x100U, /**< FlexPWM0 Req_capt0 */ - kDmaRequestMuxFlexPwm0ReqCapt1 = 40 | 0x100U, /**< FlexPWM0 Req_capt1 */ - kDmaRequestMuxFlexPwm0ReqCapt2 = 41 | 0x100U, /**< FlexPWM0 Req_capt2 */ - kDmaRequestMuxFlexPwm0ReqCapt3 = 42 | 0x100U, /**< FlexPWM0 Req_capt3 */ - kDmaRequestMuxFlexPwm0ReqVal0 = 43 | 0x100U, /**< FlexPWM0 Req_val0 */ - kDmaRequestMuxFlexPwm0ReqVal1 = 44 | 0x100U, /**< FlexPWM0 Req_val1 */ - kDmaRequestMuxFlexPwm0ReqVal2 = 45 | 0x100U, /**< FlexPWM0 Req_val2 */ - kDmaRequestMuxFlexPwm0ReqVal3 = 46 | 0x100U, /**< FlexPWM0 Req_val3 */ - kDmaRequestMuxFlexPwm1ReqCapt0 = 47 | 0x100U, /**< FlexPWM1 Req_capt0 */ - kDmaRequestMuxFlexPwm1ReqCapt1 = 48 | 0x100U, /**< FlexPWM1 Req_capt1 */ - kDmaRequestMuxFlexPwm1ReqCapt2 = 49 | 0x100U, /**< FlexPWM1 Req_capt2 */ - kDmaRequestMuxFlexPwm1ReqCapt3 = 50 | 0x100U, /**< FlexPWM1 Req_capt3 */ - kDmaRequestMuxFlexPwm1ReqVal0 = 51 | 0x100U, /**< FlexPWM1 Req_val0 */ - kDmaRequestMuxFlexPwm1ReqVal1 = 52 | 0x100U, /**< FlexPWM1 Req_val1 */ - kDmaRequestMuxFlexPwm1ReqVal2 = 53 | 0x100U, /**< FlexPWM1 Req_val2 */ - kDmaRequestMuxFlexPwm1ReqVal3 = 54 | 0x100U, /**< FlexPWM1 Req_val3 */ - kDmaRequestMuxItrc0TmprOut0 = 55 | 0x100U, /**< ITRC0 TMPR_OUT0 */ - kDmaRequestMuxItrc0TmprOut1 = 56 | 0x100U, /**< ITRC0 TMPR_OUT1 */ - kDmaRequestMuxLptmr0 = 57 | 0x100U, /**< LPTMR0 Counter match event */ - kDmaRequestMuxLptmr1 = 58 | 0x100U, /**< LPTMR1 Counter match event */ - kDmaRequestMuxFlexCan0DmaRequest = 59 | 0x100U, /**< FlexCAN0 DMA request */ - kDmaRequestMuxFlexCan1DmaRequest = 60 | 0x100U, /**< FlexCAN1 DMA request */ - kDmaRequestMuxFlexIO0ShiftRegister0Request = 61 | 0x100U, /**< FlexIO0 Shift Register 0 request */ - kDmaRequestMuxFlexIO0ShiftRegister1Request = 62 | 0x100U, /**< FlexIO0 Shift Register 1 request */ - kDmaRequestMuxFlexIO0ShiftRegister2Request = 63 | 0x100U, /**< FlexIO0 Shift Register 2 request */ - kDmaRequestMuxFlexIO0ShiftRegister3Request = 64 | 0x100U, /**< FlexIO0 Shift Register 3 request */ - kDmaRequestMuxFlexIO0ShiftRegister4Request = 65 | 0x100U, /**< FlexIO0 Shift Register 4 request */ - kDmaRequestMuxFlexIO0ShiftRegister5Request = 66 | 0x100U, /**< FlexIO0 Shift Register 5 request */ - kDmaRequestMuxFlexIO0ShiftRegister6Request = 67 | 0x100U, /**< FlexIO0 Shift Register 6 request */ - kDmaRequestMuxFlexIO0ShiftRegister7Request = 68 | 0x100U, /**< FlexIO0 Shift Register 7 request */ - kDmaRequestMuxLpFlexcomm0Rx = 69 | 0x100U, /**< LP_FLEXCOMM0 Receive request */ - kDmaRequestMuxLpFlexcomm0Tx = 70 | 0x100U, /**< LP_FLEXCOMM0 Transmit request */ - kDmaRequestMuxLpFlexcomm1Rx = 71 | 0x100U, /**< LP_FLEXCOMM1 Receive request */ - kDmaRequestMuxLpFlexcomm1Tx = 72 | 0x100U, /**< LP_FLEXCOMM1 Transmit request */ - kDmaRequestMuxLpFlexcomm2Rx = 73 | 0x100U, /**< LP_FLEXCOMM2 Receive request */ - kDmaRequestMuxLpFlexcomm2Tx = 74 | 0x100U, /**< LP_FLEXCOMM2 Transmit request */ - kDmaRequestMuxLpFlexcomm3Rx = 75 | 0x100U, /**< LP_FLEXCOMM3 Receive request */ - kDmaRequestMuxLpFlexcomm3Tx = 76 | 0x100U, /**< LP_FLEXCOMM3 Transmit request */ - kDmaRequestMuxLpFlexcomm4Rx = 77 | 0x100U, /**< LP_FLEXCOMM4 Receive request */ - kDmaRequestMuxLpFlexcomm4Tx = 78 | 0x100U, /**< LP_FLEXCOMM4 Transmit request */ - kDmaRequestMuxLpFlexcomm5Rx = 79 | 0x100U, /**< LP_FLEXCOMM5 Receive request */ - kDmaRequestMuxLpFlexcomm5Tx = 80 | 0x100U, /**< LP_FLEXCOMM5 Transmit request */ - kDmaRequestMuxLpFlexcomm6Rx = 81 | 0x100U, /**< LP_FLEXCOMM6 Receive request */ - kDmaRequestMuxLpFlexcomm6Tx = 82 | 0x100U, /**< LP_FLEXCOMM6 Transmit request */ - kDmaRequestMuxLpFlexcomm7Rx = 83 | 0x100U, /**< LP_FLEXCOMM7 Receive request */ - kDmaRequestMuxLpFlexcomm7Tx = 84 | 0x100U, /**< LP_FLEXCOMM7 Transmit request */ - kDmaRequestMuxLpFlexcomm8Rx = 85 | 0x100U, /**< LP_FLEXCOMM8 Receive request */ - kDmaRequestMuxLpFlexcomm8Tx = 86 | 0x100U, /**< LP_FLEXCOMM8 Transmit request */ - kDmaRequestMuxLpFlexcomm9Rx = 87 | 0x100U, /**< LP_FLEXCOMM9 Receive request */ - kDmaRequestMuxLpFlexcomm9Tx = 88 | 0x100U, /**< LP_FLEXCOMM9 Transmit request */ - kDmaRequestMuxESpi0Ch0 = 89 | 0x100U, /**< eSPI0 channel 0 */ - kDmaRequestMuxESpi0Ch1 = 90 | 0x100U, /**< eSPI0 channel 1 */ - kDmaRequestMuxEmvSim0Rx = 91 | 0x100U, /**< EMVSIM0 Receive request */ - kDmaRequestMuxEmvSim0Tx = 92 | 0x100U, /**< EMVSIM0 Transmit request */ - kDmaRequestMuxEmvSim1Rx = 93 | 0x100U, /**< EMVSIM1 Receive request */ - kDmaRequestMuxEmvSim1Tx = 94 | 0x100U, /**< EMVSIM1 Transmit request */ - kDmaRequestMuxI3c0Rx = 95 | 0x100U, /**< I3C0 Receive request */ - kDmaRequestMuxI3c0Tx = 96 | 0x100U, /**< I3C0 Transmit request */ - kDmaRequestMuxI3c1Rx = 97 | 0x100U, /**< I3C0 Receive request */ - kDmaRequestMuxI3c1Tx = 98 | 0x100U, /**< I3C0 Transmit request */ - kDmaRequestMuxSai0Rx = 99 | 0x100U, /**< SAI0 Receive request */ - kDmaRequestMuxSai0Tx = 100 | 0x100U, /**< SAI0 Receive request */ - kDmaRequestMuxSai1Rx = 101 | 0x100U, /**< SAI1 Receive request */ - kDmaRequestMuxSai1Tx = 102 | 0x100U, /**< SAI1 Receive request */ - kDmaRequestMuxSinc0IpdReqSincAlt0 = 103 | 0x100U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */ - kDmaRequestMuxSinc0IpdReqSincAlt1 = 104 | 0x100U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */ - kDmaRequestMuxSinc0IpdReqSincAlt2 = 105 | 0x100U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */ - kDmaRequestMuxSinc0IpdReqSincAlt3 = 106 | 0x100U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */ - kDmaRequestMuxSinc0IpdReqSincAlt4 = 107 | 0x100U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */ - kDmaRequestMuxGpio0PinEventRequest0 = 108 | 0x100U, /**< GPIO0 Pin event request 0 */ - kDmaRequestMuxGpio0PinEventRequest1 = 109 | 0x100U, /**< GPIO0 Pin event request 1 */ - kDmaRequestMuxGpio1PinEventRequest0 = 110 | 0x100U, /**< GPIO1 Pin event request 0 */ - kDmaRequestMuxGpio1PinEventRequest1 = 111 | 0x100U, /**< GPIO1 Pin event request 1 */ - kDmaRequestMuxGpio2PinEventRequest0 = 112 | 0x100U, /**< GPIO2 Pin event request 0 */ - kDmaRequestMuxGpio2PinEventRequest1 = 113 | 0x100U, /**< GPIO2 Pin event request 1 */ - kDmaRequestMuxGpio3PinEventRequest0 = 114 | 0x100U, /**< GPIO3 Pin event request 0 */ - kDmaRequestMuxGpio3PinEventRequest1 = 115 | 0x100U, /**< GPIO3 Pin event request 1 */ - kDmaRequestMuxGpio4PinEventRequest0 = 116 | 0x100U, /**< GPIO4 Pin event request 0 */ - kDmaRequestMuxGpio4PinEventRequest1 = 117 | 0x100U, /**< GPIO4 Pin event request 1 */ - kDmaRequestMuxGpio5PinEventRequest0 = 118 | 0x100U, /**< GPIO5 Pin event request 0 */ - kDmaRequestMuxGpio5PinEventRequest1 = 119 | 0x100U, /**< GPIO5 Pin event request 1 */ - kDmaRequestMuxTsi0EndOfScan = 120 | 0x100U, /**< TSI0 End of Scan */ - kDmaRequestMuxTsi0OutOfRange = 121 | 0x100U, /**< TSI0 Out of Range */ -} dma_request_source_t; - -/*!< Verify dma base and request source */ -#define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((source)&0x100U) - -#define FSL_FEATURE_EDMA_MODULE_CHANNEL(base) (16U) -#define FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL (16) -#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) -#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0) -#define FSL_FEATURE_EDMA_MODULE_COUNT (2) -#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) -#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) -#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) -#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE (0) -#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) -#define FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base) (0U) -#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base) (0U) -#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base) (0U) -#define FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base) (0U) - /*!@brief EDMA base address convert macro */ #define EDMA_CHANNEL_OFFSET 0x1000U #define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c index d913454788..bae11683f4 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c @@ -82,44 +82,52 @@ void EIM_Deinit(EIM_Type *base) void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) { - switch (channel) + switch ((uint8_t)channel) { - case kEIM_MemoryChannelRAMX: + case 0U: base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelRAMA: +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask); break; +#endif - case kEIM_MemoryChannelRAMB: +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelRAMC: +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelRAMD: +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelRAME: +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelRAMF: +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelLPCACRAM: +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask); break; - - case kEIM_MemoryChannelPKCRAM: +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask); break; - +#endif default: assert(NULL); break; @@ -130,53 +138,60 @@ uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel) { uint8_t mask = 0x00U; - switch (channel) + switch ((uint8_t)channel) { - case kEIM_MemoryChannelRAMX: + case 0U: mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelRAMA: +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelRAMB: +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelRAMC: +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelRAMD: +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelRAME: +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelRAMF: +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelLPCACRAM: +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT); break; - - case kEIM_MemoryChannelPKCRAM: +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >> EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT); break; - +#endif default: assert(NULL); break; @@ -187,44 +202,51 @@ uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel) void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) { - switch (channel) + switch ((uint8_t)channel) { - case kEIM_MemoryChannelRAMX: + case 0U: base->EICHD0_WORD1 = mask; break; - - case kEIM_MemoryChannelRAMA: +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: base->EICHD1_WORD1 = mask; break; - - case kEIM_MemoryChannelRAMB: +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: base->EICHD2_WORD1 = mask; break; - +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK case kEIM_MemoryChannelRAMC: base->EICHD3_WORD1 = mask; break; - +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK case kEIM_MemoryChannelRAMD: base->EICHD4_WORD1 = mask; break; - +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK case kEIM_MemoryChannelRAME: base->EICHD5_WORD1 = mask; break; - +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK case kEIM_MemoryChannelRAMF: base->EICHD6_WORD1 = mask; break; - +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK case kEIM_MemoryChannelLPCACRAM: base->EICHD7_WORD1 = mask; break; - +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK case kEIM_MemoryChannelPKCRAM: base->EICHD8_WORD1 = mask; break; - +#endif default: assert(NULL); break; @@ -235,44 +257,52 @@ uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel) { uint32_t mask = 0x00U; - switch (channel) + switch ((uint8_t)channel) { - case kEIM_MemoryChannelRAMX: + case 0U: mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT; break; - case kEIM_MemoryChannelRAMA: +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelRAMB: +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelRAMC: +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelRAMD: +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelRAME: +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelRAMF: +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelLPCACRAM: +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT; break; - - case kEIM_MemoryChannelPKCRAM: +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT; break; - +#endif default: assert(NULL); break; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h index c1afbf59b4..799ff3f20a 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_EIM_H_ -#define _FSL_EIM_H_ +#ifndef FSL_EIM_H_ +#define FSL_EIM_H_ #include "fsl_common.h" @@ -21,10 +21,10 @@ *****************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief Driver version. */ -#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) -/*@}*/ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*! @} */ /******************************************************************************* * APIs @@ -47,7 +47,7 @@ void EIM_Init(EIM_Type *base); */ void EIM_Deinit(EIM_Type *base); -/* @} */ +/*! @} */ /*! * @name functional diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c deleted file mode 100644 index aab9a505d8..0000000000 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_enc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.enc" -#endif - -#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) -#if (defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) -#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) -#else -#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ENC module. - * - * @param base ENC peripheral base address - */ -static uint32_t ENC_GetInstance(ENC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ENC bases for each instance. */ -static ENC_Type *const s_encBases[] = ENC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ENC clocks for each instance. */ -static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ENC_GetInstance(ENC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++) - { - if (s_encBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_encBases)); - - return instance; -} - -/*! - * brief Initialization for the ENC module. - * - * This function is to make the initialization for the ENC module. It should be called firstly before any operation to - * the ENC with the operations like: - * - Enable the clock for ENC module. - * - Configure the ENC's working attributes. - * - * param base ENC peripheral base address. - * param config Pointer to configuration structure. See to "enc_config_t". - */ -void ENC_Init(ENC_Type *base, const enc_config_t *config) -{ - assert(NULL != config); - - uint16_t tmp16; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* ENC_CTRL. */ - tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK | - ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK)); - /* For HOME trigger. */ - if (kENC_HOMETriggerDisabled != config->HOMETriggerMode) - { - tmp16 |= ENC_CTRL_HIP_MASK; - if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) - { - tmp16 |= ENC_CTRL_HNE_MASK; - } - } - /* For encoder work mode. */ - if (config->enableReverseDirection) - { - tmp16 |= ENC_CTRL_REV_MASK; - } - if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) - { - tmp16 |= ENC_CTRL_PH1_MASK; - } - /* For INDEX trigger. */ - if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode) - { - tmp16 |= ENC_CTRL_XIP_MASK; - if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) - { - tmp16 |= ENC_CTRL_XNE_MASK; - } - } - /* Watchdog. */ - if (config->enableWatchdog) - { - tmp16 |= ENC_CTRL_WDE_MASK; - base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ - } - base->CTRL = tmp16; - - /* ENC_FILT. */ - base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod); - - /* ENC_CTRL2. */ - tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK | - ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK)); - if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) - { - tmp16 |= ENC_CTRL2_OUTCTL_MASK; - } - if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) - { - tmp16 |= ENC_CTRL2_REVMOD_MASK; - } - if (config->enableModuloCountMode) - { - tmp16 |= ENC_CTRL2_MOD_MASK; - /* Set modulus value. */ - base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ - base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ - } - if (config->enableTRIGGERClearPositionCounter) - { - tmp16 |= ENC_CTRL2_UPDPOS_MASK; - } - if (config->enableTRIGGERClearHoldPositionCounter) - { - tmp16 |= ENC_CTRL2_UPDHLD_MASK; - } - base->CTRL2 = tmp16; - -#if (defined(FSL_FEATURE_ENC_HAS_CTRL3) && FSL_FEATURE_ENC_HAS_CTRL3) - /* ENC_CTRL3. */ - tmp16 = base->CTRL3 & (uint16_t)(~(ENC_CTRL3_PMEN_MASK | ENC_CTRL3_PRSC_MASK)); - if (config->enablePeriodMeasurementFunction) - { - tmp16 |= ENC_CTRL3_PMEN_MASK; - /* Set prescaler value. */ - tmp16 |= ((uint16_t)config->prescalerValue << ENC_CTRL3_PRSC_SHIFT); - } - base->CTRL3 = tmp16; -#endif - - /* ENC_UCOMP & ENC_LCOMP. */ - base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ - base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ - - /* ENC_UINIT & ENC_LINIT. */ - base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ - base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ -} - -/*! - * brief De-initialization for the ENC module. - * - * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with - * the operations like: - * - Disable the clock for ENC module. - * - * param base ENC peripheral base address. - */ -void ENC_Deinit(ENC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * brief Get an available pre-defined settings for ENC's configuration. - * - * This function initializes the ENC configuration structure with an available settings, the default value are: - * code - * config->enableReverseDirection = false; - * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - * config->HOMETriggerMode = kENC_HOMETriggerDisabled; - * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - * config->enableTRIGGERClearPositionCounter = false; - * config->enableTRIGGERClearHoldPositionCounter = false; - * config->enableWatchdog = false; - * config->watchdogTimeoutValue = 0U; - * config->filterCount = 0U; - * config->filterSamplePeriod = 0U; - * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - * config->positionCompareValue = 0xFFFFFFFFU; - * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - * config->enableModuloCountMode = false; - * config->positionModulusValue = 0U; - * config->positionInitialValue = 0U; - * config->prescalerValue = kENC_ClockDiv1; - * config->enablePeriodMeasurementFunction = true; - * endcode - * param config Pointer to a variable of configuration structure. See to "enc_config_t". - */ -void ENC_GetDefaultConfig(enc_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->enableReverseDirection = false; - config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - config->HOMETriggerMode = kENC_HOMETriggerDisabled; - config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - config->enableTRIGGERClearPositionCounter = false; - config->enableTRIGGERClearHoldPositionCounter = false; - config->enableWatchdog = false; - config->watchdogTimeoutValue = 0U; - config->filterCount = 0U; - config->filterSamplePeriod = 0U; - config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - config->positionCompareValue = 0xFFFFFFFFU; - config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - config->enableModuloCountMode = false; - config->positionModulusValue = 0U; - config->positionInitialValue = 0U; -#if (defined(FSL_FEATURE_ENC_HAS_CTRL3) && FSL_FEATURE_ENC_HAS_CTRL3) - config->prescalerValue = kENC_ClockDiv1; - config->enablePeriodMeasurementFunction = true; -#endif -} - -/*! - * brief Load the initial position value to position counter. - * - * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and - * LPOS), so that to provide the consistent operation the position counter registers. - * - * param base ENC peripheral base address. - */ -void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) -{ - uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); - - tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ - base->CTRL = tmp16; -} - -/*! - * brief Enable and configure the self test function. - * - * This function is to enable and configuration the self test function. It controls and sets the frequency of a - * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. - * It is a factory test feature; however, it may be useful to customers' software development and testing. - * - * param base ENC peripheral base address. - * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. - */ -void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) -{ - uint16_t tmp16 = 0U; - - if (NULL == config) /* Pass "NULL" to disable the feature. */ - { - tmp16 = 0U; - } - else - { - tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) | - ENC_TST_TEST_COUNT(config->signalCount); - if (kENC_SelfTestDirectionNegative == config->signalDirection) - { - tmp16 |= ENC_TST_QDN_MASK; - } - } - - base->TST = tmp16; -} - -/*! - * brief Enable watchdog for ENC module. - * - * param base ENC peripheral base address - * param enable Enables or disables the watchdog - */ -void ENC_EnableWatchdog(ENC_Type *base, bool enable) -{ - uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); - - if (enable) - { - tmp16 |= ENC_CTRL_WDE_MASK; - } - base->CTRL = tmp16; -} - -/*! - * brief Get the status flags. - * - * param base ENC peripheral base address. - * - * return Mask value of status flags. For available mask, see to "_enc_status_flags". - */ -uint32_t ENC_GetStatusFlags(ENC_Type *base) -{ - uint32_t ret32 = 0U; - - /* ENC_CTRL. */ - if (0U != (ENC_CTRL_HIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_HOMETransitionFlag; - } - if (0U != (ENC_CTRL_XIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_INDEXPulseFlag; - } - if (0U != (ENC_CTRL_DIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_WatchdogTimeoutFlag; - } - if (0U != (ENC_CTRL_CMPIRQ_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_PositionCompareFlag; - } - - /* ENC_CTRL2. */ -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - if (0U != (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_SimultBothPhaseChangeFlag; - } -#endif - if (0U != (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollOverFlag; - } - if (0U != (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollUnderFlag; - } - if (0U != (ENC_CTRL2_DIR_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_LastCountDirectionFlag; - } - - return ret32; -} - -/*! - * brief Clear the status flags. - * - * param base ENC peripheral base address. - * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". - */ -void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) -{ - uint32_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (0U != ((uint32_t)kENC_HOMETransitionFlag & mask)) - { - tmp16 |= ENC_CTRL_HIRQ_MASK; - } - if (0U != ((uint32_t)kENC_INDEXPulseFlag & mask)) - { - tmp16 |= ENC_CTRL_XIRQ_MASK; - } - if (0U != ((uint32_t)kENC_WatchdogTimeoutFlag & mask)) - { - tmp16 |= ENC_CTRL_DIRQ_MASK; - } - if (0U != ((uint32_t)kENC_PositionCompareFlag & mask)) - { - tmp16 |= ENC_CTRL_CMPIRQ_MASK; - } - if (0U != tmp16) - { - base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16); - } - - /* ENC_CTRL2. */ - tmp16 = 0U; -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - if (0U != ((uint32_t)kENC_SimultBothPhaseChangeFlag & mask)) - { - tmp16 |= ENC_CTRL2_SABIRQ_MASK; - } -#endif - if (0U != ((uint32_t)kENC_PositionRollOverFlag & mask)) - { - tmp16 |= ENC_CTRL2_ROIRQ_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollUnderFlag & mask)) - { - tmp16 |= ENC_CTRL2_RUIRQ_MASK; - } - if (0U != tmp16) - { - base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); - } -} - -/*! - * brief Enable the interrupts. - * - * param base ENC peripheral base address. - * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) -{ - uint32_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_HIE_MASK; - } - if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_XIE_MASK; - } - if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_DIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask)) - { - tmp16 |= ENC_CTRL_CMPIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16); - } - /* ENC_CTRL2. */ - tmp16 = 0U; -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_SABIE_MASK; - } -#endif - if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_ROIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_RUIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); - } -} - -/*! - * brief Disable the interrupts. - * - * param base ENC peripheral base address. - * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) -{ - uint16_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_HIE_MASK; - } - if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_XIE_MASK; - } - if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_DIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask)) - { - tmp16 |= ENC_CTRL_CMPIE_MASK; - } - if (0U != tmp16) - { - base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); - } - /* ENC_CTRL2. */ - tmp16 = 0U; -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_SABIE_MASK; - } -#endif - if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_ROIE_MASK; - } - if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_RUIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); - } -} - -/*! - * brief Get the enabled interrupts' flags. - * - * param base ENC peripheral base address. - * - * return Mask value of enabled interrupts. - */ -uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) -{ - uint32_t ret32 = 0U; - - /* ENC_CTRL. */ - if (0U != (ENC_CTRL_HIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_HOMETransitionInterruptEnable; - } - if (0U != (ENC_CTRL_XIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_INDEXPulseInterruptEnable; - } - if (0U != (ENC_CTRL_DIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_WatchdogTimeoutInterruptEnable; - } - if (0U != (ENC_CTRL_CMPIE_MASK & base->CTRL)) - { - ret32 |= (uint32_t)kENC_PositionCompareInerruptEnable; - } - /* ENC_CTRL2. */ -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - if (0U != (ENC_CTRL2_SABIE_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_SimultBothPhaseChangeInterruptEnable; - } -#endif - if (0U != (ENC_CTRL2_ROIE_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollOverInterruptEnable; - } - if (0U != (ENC_CTRL2_RUIE_MASK & base->CTRL2)) - { - ret32 |= (uint32_t)kENC_PositionRollUnderInterruptEnable; - } - return ret32; -} - -/*! - * brief Set initial position value for ENC module. - * - * param base ENC peripheral base address - * param value Positive initial value - */ -void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) -{ - base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ - base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ -} - -/*! - * brief Get the current position counter's value. - * - * param base ENC peripheral base address. - * - * return Current position counter's value. - */ -uint32_t ENC_GetPositionValue(ENC_Type *base) -{ - uint32_t ret32; - - ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ - ret32 <<= 16U; - ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ - - return ret32; -} - -/*! - * brief Get the hold position counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * param base ENC peripheral base address. - * - * return Hold position counter's value. - */ -uint32_t ENC_GetHoldPositionValue(ENC_Type *base) -{ - uint32_t ret32; - - ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ - ret32 <<= 16U; - ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ - - return ret32; -} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c index e7b00eedd2..03b479913a 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c @@ -1,9 +1,10 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include "fsl_enet.h" /******************************************************************************* @@ -41,7 +42,7 @@ #define ENET_HEAD_AVBTYPE_OFFSET (16) /*! @brief Binary rollover mode count convert */ -#define ENET_BINARY_ROLLOVER_SCALE(x) (uint32_t)((uint64_t)(x)*46566U / 100000U) +#define ENET_BINARY_ROLLOVER_SCALE(x) (uint32_t)((uint64_t)(x) * 46566U / 100000U) /******************************************************************************* * Prototypes @@ -302,7 +303,8 @@ static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uin /* Set the speed and duplex. */ reg = ENET_MAC_CONFIGURATION_ECRSFD_MASK | ENET_MAC_CONFIGURATION_PS_MASK | ENET_MAC_CONFIGURATION_DM(config->miiDuplex) | ENET_MAC_CONFIGURATION_FES(config->miiSpeed) | - ENET_MAC_CONFIGURATION_S2KP(!((config->specialControl & (uint16_t)kENET_8023AS2KPacket) == 0U)); + ENET_MAC_CONFIGURATION_S2KP((config->specialControl & (uint16_t)kENET_8023AS2KPacket) != 0U) | + ENET_MAC_CONFIGURATION_IPC((config->specialControl & (uint16_t)kENET_RxChecksumOffloadEnable) != 0U); if (config->miiDuplex == kENET_MiiHalfDuplex) { reg |= ENET_MAC_CONFIGURATION_IPG(ENET_HALFDUPLEX_DEFAULTIPG); @@ -751,7 +753,7 @@ void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) base->DMA_CH[index].DMA_CHX_INT_EN = interrupt; } } - interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET; + interrupt = mask >> ENET_MACINT_ENUM_OFFSET; if (interrupt != 0U) { /* MAC interrupt */ @@ -829,7 +831,7 @@ void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt; } } - interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET; + interrupt = mask >> ENET_MACINT_ENUM_OFFSET; if (interrupt != 0U) { /* MAC interrupt */ @@ -867,6 +869,8 @@ void ENET_CreateHandler(ENET_Type *base, uint8_t count = 0; uint8_t rxIntEnable = 0; enet_buffer_config_t *buffConfig = bufferConfig; + uint32_t txFifoSize; + uint32_t pbl; /* Store transfer parameters in handle pointer. */ (void)memset(handle, 0, sizeof(enet_handle_t)); @@ -901,10 +905,24 @@ void ENET_CreateHandler(ENET_Type *base, /* Check if the Rx interrrupt is enabled. */ rxIntEnable |= (uint8_t)(uint32_t)(base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK); + + /* Calculate the reserved space for Tx in certain cases. */ + if (0U != (base->MTL_QUEUE[count].MTL_TXQX_OP_MODE & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)) + { + pbl = (base->DMA_CH[count].DMA_CHX_TX_CTRL & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) >> + ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT; + pbl = ((base->DMA_CH[count].DMA_CHX_CTRL & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) != 0U) ? (8U * pbl) : pbl; + txFifoSize = (uint32_t)pow((double)2, + (double)(uint32_t)(((base->MAC_HW_FEAT[1] & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) >> + ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT) + + 7U)); + handle->txLenLimitation[count] = txFifoSize - (pbl + 6U) * (32U / 8U); + } + buffConfig++; } - handle->rxintEnable = (rxIntEnable != 0U) ? true : false; + handle->rxintEnable = (rxIntEnable != 0U); /* Save the handle pointer in the global variables. */ s_ENETHandle[ENET_GetInstance(base)] = handle; @@ -1135,6 +1153,127 @@ void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter) base->MAC_CONFIGURATION |= ENET_MAC_CONFIGURATION_RE_MASK; } +/*! + * brief Set VLAN control. + * + * param base ENET peripheral base address. + * param control VLAN control configuration. + */ +status_t ENET_SetVlanCtrl(ENET_Type *base, enet_vlan_ctrl_t *control) +{ + uint32_t vl = (((uint32_t)control->rxVlanTag.pcp) << 13U) | (((uint32_t)control->rxVlanTag.dei) << 12U) | + (uint32_t)control->rxVlanTag.vid; + uint32_t vlanCtrl; + + if ((control->innerVlanFilterMatch) && (!control->doubleVlanEnable)) + { + return kStatus_Fail; + } + + vlanCtrl = ENET_MAC_VLAN_TAG_CTRL_VL(vl) | ENET_MAC_VLAN_TAG_CTRL_ETV(control->vidComparison) | + ENET_MAC_VLAN_TAG_CTRL_VTIM(control->vlanInverseMatch) | + ENET_MAC_VLAN_TAG_CTRL_ESVL(control->svlanEnable) | + ENET_MAC_VLAN_TAG_CTRL_DOVLTC(control->disableVlanTypeCheck) | + ENET_MAC_VLAN_TAG_CTRL_EVLS(control->rxOuterVlanStrip) | + ENET_MAC_VLAN_TAG_CTRL_EIVLS(control->rxInnerVlanStrip) | + ENET_MAC_VLAN_TAG_CTRL_EDVLP(control->doubleVlanEnable) | + ENET_MAC_VLAN_TAG_CTRL_ERIVLT(control->innerVlanFilterMatch) | + ENET_MAC_VLAN_TAG_CTRL_EVLRXS(control->outerTagInRxStatus) | + ENET_MAC_VLAN_TAG_CTRL_EIVLRXS(control->innerTagInRxStatus); + + if (control->rxVlanTag.tpid == kENET_StanSvlan) + { + vlanCtrl |= ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK; + } + base->MAC_VLAN_TAG_CTRL = vlanCtrl; + + return kStatus_Success; +} + +/*! + * brief Set Tx outer VLAN configuration. + * + * param base ENET peripheral base address. + * param config Tx VLAN operation configuration. + * param channel The channel to apply this configuration. + */ +status_t ENET_SetTxOuterVlan(ENET_Type *base, enet_vlan_tx_config_t *config, enet_vlan_tx_channel_t channel) +{ + uint32_t vlt = + (((uint32_t)config->tag.pcp) << 13U) | (((uint32_t)config->tag.dei) << 12U) | (uint32_t)config->tag.vid; + uint32_t vlanConfig = ENET_MAC_VLAN_INCL_VLTI(config->txDescVlan) | ENET_MAC_VLAN_INCL_CSVL(config->tag.tpid) | + ENET_MAC_VLAN_INCL_VLC(config->ops) | ENET_MAC_VLAN_INCL_VLT(vlt); + + if ((config->tag.tpid == kENET_StanSvlan) && ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) == 0U)) + { + return kStatus_Fail; + } + + if (config->ops != kENET_NoOps) + { + vlanConfig |= ENET_MAC_VLAN_INCL_VLP(1); + } + + if (channel != kENET_VlanTagAllChannels) + { + while ((base->MAC_VLAN_INCL & ENET_MAC_VLAN_INCL_BUSY_MASK) != 0U) + { + } + + /* Clear and status ans reset the power down. */ + base->MAC_VLAN_INCL |= + ENET_MAC_VLAN_INCL_CBTI_MASK | ENET_MAC_VLAN_INCL_RDWR_MASK | ENET_MAC_VLAN_INCL_ADDR(channel) | vlanConfig; + + while ((base->MAC_VLAN_INCL & ENET_MAC_VLAN_INCL_BUSY_MASK) != 0U) + { + } + + /* Clear set channel bits. */ + base->MAC_VLAN_INCL &= ~(ENET_MAC_VLAN_INCL_RDWR_MASK | ENET_MAC_VLAN_INCL_CBTI_MASK); + } + else + { + base->MAC_VLAN_INCL = vlanConfig; + } + + return kStatus_Success; +} + +/*! + * brief Set Tx inner VLAN configuration. + * + * param base ENET peripheral base address. + * param config Tx VLAN operation configuration. + */ +status_t ENET_SetTxInnerVlan(ENET_Type *base, enet_vlan_tx_config_t *config) +{ + uint32_t vlt = + (((uint32_t)config->tag.pcp) << 13U) | (((uint32_t)config->tag.dei) << 12U) | (uint32_t)config->tag.vid; + uint32_t vlanConfig = ENET_MAC_INNER_VLAN_INCL_VLTI(config->txDescVlan) | + ENET_MAC_INNER_VLAN_INCL_CSVL(config->tag.tpid) | ENET_MAC_INNER_VLAN_INCL_VLC(config->ops) | + ENET_MAC_INNER_VLAN_INCL_VLT(vlt); + + /* S-VLAN should be enabled first. */ + if ((config->tag.tpid == kENET_StanSvlan) && ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) == 0U)) + { + return kStatus_Fail; + } + + /* Double VLAN should be enabled first for inner VLAN. */ + if ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK) == 0U) + { + return kStatus_Fail; + } + + if (config->ops != kENET_NoOps) + { + vlanConfig |= ENET_MAC_INNER_VLAN_INCL_VLP(1); + } + base->MAC_INNER_VLAN_INCL = vlanConfig; + + return kStatus_Success; +} + /*! * brief Gets the size of the read frame. * This function gets a received frame size from the ENET buffer descriptors. @@ -1551,7 +1690,6 @@ void ENET_RxBufferFreeAll(ENET_Type *base, enet_handle_t *handle) static inline void ENET_GetRxFrameErr(enet_rx_bd_struct_t *rxDesc, enet_rx_frame_error_t *rxFrameError) { - uint32_t rdes3 = rxDesc->rdes3; union _frame_error { uint32_t data; @@ -1559,9 +1697,8 @@ static inline void ENET_GetRxFrameErr(enet_rx_bd_struct_t *rxDesc, enet_rx_frame }; union _frame_error error; - (void)memset((void *)&error.frameError, 0, sizeof(enet_rx_frame_error_t)); - - error.data = ENET_FRAME_RX_ERROR_BITS(rdes3); + error.data = ENET_FRAME_RX_ERROR_BITS(rxDesc->rdes3); + *rxFrameError = error.frameError; } static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t channel) @@ -1573,23 +1710,29 @@ static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t chann bool tsAvailable = false; uint32_t buff1Addr = 0; uint32_t buff2Addr = 0; + uint32_t rdes1; #endif /* ENET_PTP1588FEATURE_REQUIRED */ + uint32_t rdes3; /* Not check DMA ownership here, assume there's at least one valid frame left in BD ring */ do { /* Update the BD to idle status. */ rxDesc = &rxBdRing->rxBdBase[rxBdRing->rxGenIdx]; +#ifdef ENET_PTP1588FEATURE_REQUIRED + rdes1 = rxDesc->rdes1; +#endif + rdes3 = rxDesc->rdes3; ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); /* Find the last buffer descriptor for the frame. */ - if ((rxDesc->rdes3 & ENET_RXDESCRIP_WR_LD_MASK) != 0U) + if ((rdes3 & ENET_RXDESCRIP_WR_LD_MASK) != 0U) { #ifdef ENET_PTP1588FEATURE_REQUIRED - if ((rxDesc->rdes3 & ENET_RXDESCRIP_WR_RS1V_MASK) != 0U) + if ((rdes3 & ENET_RXDESCRIP_WR_RS1V_MASK) != 0U) { - if ((rxDesc->rdes1 & ENET_RXDESCRIP_WR_PTPTSA_MASK) != 0U) + if ((rdes1 & ENET_RXDESCRIP_WR_PTPTSA_MASK) != 0U) { tsAvailable = true; } @@ -1631,10 +1774,7 @@ static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t chann * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application. * note This function will drop current frame and update related BDs as available for DMA if new buffers allocating * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer) - * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this - * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's - * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according - * to specific design in this case. + * to make this function work normally. * * param base ENET peripheral base address. * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. @@ -1739,17 +1879,16 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s if (rxFrame->totLen - offset > (uint16_t)rxBdRing->rxBuffSizeAlign) { + /* Here must be double buffer. */ + assert(handle->doubleBuffEnable); + buff1Len = (uint16_t)rxBdRing->rxBuffSizeAlign; - if (handle->doubleBuffEnable) - { - buff2Len = rxFrame->totLen - offset - (uint16_t)rxBdRing->rxBuffSizeAlign - ENET_FCS_LEN; - } + buff2Len = rxFrame->totLen - offset - (uint16_t)rxBdRing->rxBuffSizeAlign; } else { - buff1Len = rxFrame->totLen - offset - ENET_FCS_LEN; + buff1Len = rxFrame->totLen - offset; } - rxFrame->totLen -= ENET_FCS_LEN; } else { @@ -1896,7 +2035,7 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s /* Free the incomplete frame buffers. */ while (index-- != 0U) { - handle->rxBuffFree(base, &rxFrame->rxBuffArray[index].buffer, handle->userData, channel); + handle->rxBuffFree(base, rxFrame->rxBuffArray[index].buffer, handle->userData, channel); } /* Update all left BDs of this frame from current index. */ @@ -1907,6 +2046,27 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s } } while (!isLastBuff); + /* Remove 4 bytes FCS. */ + if (result == kStatus_Success) + { + /* Find the last 4 bytes in the linked buffers and remove these FCS data. */ + buff1Len = rxFrame->rxBuffArray[--index].length; + if (buff1Len > ENET_FCS_LEN) + { + rxFrame->rxBuffArray[index].length -= ENET_FCS_LEN; + } + else + { + rxFrame->rxBuffArray[index].length = 0; + handle->rxBuffFree(base, rxFrame->rxBuffArray[index].buffer, handle->userData, channel); + if (buff1Len < ENET_FCS_LEN) + { + rxFrame->rxBuffArray[--index].length -= (ENET_FCS_LEN - buff1Len); + } + } + rxFrame->totLen -= ENET_FCS_LEN; + } + return result; } @@ -1977,6 +2137,58 @@ void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc, txDesc->tdes3 = control; } +/*! + * brief Configure a given Tx descriptor. + * This function is a low level functional API to setup or prepare + * a given Tx descriptor. + * + * param txDesc The given Tx descriptor. + * param config The Tx descriptor configuration. + * + * note This must be called after all the ENET initilization. + * And should be called when the ENET receive/transmit is required. + * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in + * memory until the packet has been fully transmitted. The buffers + * should be free or requeued in the transmit interrupt irq handler. + */ +static void ENET_ConfigTxDescriptor(enet_tx_bd_struct_t *txDesc, enet_tx_bd_config_struct_t *config) +{ + uint32_t control = ENET_TXDESCRIP_RD_BL1(config->bytes1) | ENET_TXDESCRIP_RD_BL2(config->bytes2); + enet_tx_offload_t txOffloadMode = kENET_TxOffloadDisable; + + if ((config->flag == kENET_FirstFlagOnly) || (config->flag == kENET_FirstLastFlag)) + { + if (config->tsEnable) + { + control |= ENET_TXDESCRIP_RD_TTSE_MASK; + } + else + { + control &= ~ENET_TXDESCRIP_RD_TTSE_MASK; + } + txOffloadMode = config->txOffloadOps; + } + + if (config->intEnable) + { + control |= ENET_TXDESCRIP_RD_IOC_MASK; + } + else + { + control &= ~ENET_TXDESCRIP_RD_IOC_MASK; + } + + /* Preare the descriptor for transmit. */ + txDesc->tdes0 = (uint32_t)(uint32_t *)config->buffer1; + txDesc->tdes1 = (uint32_t)(uint32_t *)config->buffer2; + txDesc->tdes2 = control; + + control = ENET_TXDESCRIP_RD_SLOT(config->slotNum) | ENET_TXDESCRIP_RD_FL(config->framelen) | + ENET_TXDESCRIP_RD_CIC(txOffloadMode) | ENET_TXDESCRIP_RD_LDFD(config->flag) | ENET_TXDESCRIP_RD_OWN_MASK; + + txDesc->tdes3 = control; +} + /*! * brief Reclaim Tx descriptors. * This function is used to update the Tx descriptor status and @@ -2090,6 +2302,15 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_st return kStatus_ENET_TxFrameOverLen; } + /* Check Tx FIFO whether can store enough frame data. */ + if (0U != handle->txLenLimitation[channel]) + { + if (frameLen > handle->txLenLimitation[channel]) + { + return kStatus_ENET_TxFrameOverLen; + } + } + /* Check whether the available BD number is enough for Tx data buffer. */ if (txFrame->txBuffNum > (((uint32_t)txBdRing->txRingLen - (uint32_t)txBdRing->txDescUsed) * 2U)) { @@ -2116,22 +2337,32 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_st descFlag = (leftBuffNum > 2U) ? kENET_MiddleFlag : kENET_LastFlagOnly; } + enet_tx_bd_config_struct_t txDescConfig = {0}; + + txDescConfig.framelen = frameLen; + txDescConfig.intEnable = (bool)txFrame->txConfig.intEnable; + txDescConfig.tsEnable = (bool)txFrame->txConfig.tsEnable; + txDescConfig.txOffloadOps = txFrame->txConfig.txOffloadOps; + txDescConfig.flag = descFlag; + txDescConfig.slotNum = txFrame->txConfig.slotNum; + /* Fill the descriptor. */ + txDescConfig.buffer1 = txBuff[index].buffer; + txDescConfig.bytes1 = txBuff[index].length; if (leftBuffNum < 2U) { - ENET_SetupTxDescriptor(txDesc, txBuff[index].buffer, txBuff[index].length, NULL, 0, frameLen, - (bool)txFrame->txConfig.intEnable, (bool)txFrame->txConfig.tsEnable, descFlag, - txFrame->txConfig.slotNum); + txDescConfig.buffer2 = NULL; + txDescConfig.bytes2 = 0; leftBuffNum--; } else { - ENET_SetupTxDescriptor(txDesc, txBuff[index].buffer, txBuff[index].length, txBuff[index + 1U].buffer, - txBuff[index + 1U].length, frameLen, (bool)txFrame->txConfig.intEnable, - (bool)txFrame->txConfig.tsEnable, descFlag, txFrame->txConfig.slotNum); + txDescConfig.buffer2 = txBuff[index + 1U].buffer; + txDescConfig.bytes2 = txBuff[index + 1U].length; index += 2U; leftBuffNum -= 2U; } + ENET_ConfigTxDescriptor(txDesc, &txDescConfig); /* Increase the index. */ txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h index 7028babd70..1514e6479c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h @@ -1,10 +1,10 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_ENET_H_ -#define _FSL_ENET_H_ +#ifndef FSL_ENET_H_ +#define FSL_ENET_H_ #include "fsl_common.h" @@ -20,7 +20,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*@}*/ /*! @name Control and status region bit masks of the receive buffer descriptor. */ @@ -58,19 +58,19 @@ /*! @brief Defines for read format. */ #define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU) #define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16) -#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n)&ENET_TXDESCRIP_RD_BL1_MASK) -#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n)&ENET_TXDESCRIP_RD_BL1_MASK) << 16) +#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) +#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16) #define ENET_TXDESCRIP_RD_TTSE_MASK (1UL << 30) #define ENET_TXDESCRIP_RD_IOC_MASK (1UL << 31) #define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU) -#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n)&ENET_TXDESCRIP_RD_FL_MASK) -#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n)&0x3U) << 16) +#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK) +#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3U) << 16) #define ENET_TXDESCRIP_RD_TSE_MASK (1UL << 18) -#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n)&0x0fU) << 19) -#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n)&0x07U) << 23) -#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n)&0x03U) << 26) -#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n)&0x03U) << 28) +#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0fU) << 19) +#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07U) << 23) +#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03U) << 26) +#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03U) << 28) #define ENET_TXDESCRIP_RD_LD_MASK (1UL << 28) #define ENET_TXDESCRIP_RD_FD_MASK (1UL << 29) #define ENET_TXDESCRIP_RD_CTXT_MASK (1UL << 30) @@ -198,11 +198,12 @@ typedef enum _enet_special_config /**************************MTL************************************/ kENET_StoreAndForward = 0x0002U, /*!< The Rx/Tx store and forward enable. */ /***********************MAC****************************************/ - kENET_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */ - kENET_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */ - kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */ - kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */ - kENET_8023AS2KPacket = 0x0040U /*!< 8023as support for 2K packets. */ + kENET_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */ + kENET_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */ + kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */ + kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */ + kENET_8023AS2KPacket = 0x0040U, /*!< 8023as support for 2K packets. */ + kENET_RxChecksumOffloadEnable = 0x0080U, /*!< The Rx checksum offload enabled. */ } enet_special_config_t; /*! @brief List of DMA interrupts supported by the ENET interrupt. This @@ -282,6 +283,48 @@ typedef enum _enet_ptp_event_type kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ } enet_ptp_event_type_t; +/*! @brief Define the Tx checksum offload options. */ +typedef enum _enet_tx_offload +{ + kENET_TxOffloadDisable = 0U, /*!< Disable Tx checksum offload. */ + kENET_TxOffloadIPHeader = 1U, /*!< Enable IP header checksum calculation and insertion. */ + kENET_TxOffloadIPHeaderPlusPayload = 2U, /*!< Enable IP header and payload checksum calculation and insertion. */ + kENET_TxOffloadAll = 3U, /*!< Enable IP header, payload and pseudo header checksum calculation and insertion. */ +} enet_tx_offload_t; + +/*! @brief Ethernet VLAN Tag protocol identifiers. */ +typedef enum _enet_vlan_tpid +{ + kENET_StanCvlan = 0x0U, /*!< C-VLAN 0x8100. */ + kENET_StanSvlan, /*!< S-VLAN 0x88A8. */ +} enet_vlan_tpid_t; + +/*! @brief Ethernet VLAN operations. */ +typedef enum _enet_vlan_ops +{ + kENET_NoOps = 0x0U, /*!< Not do anything. */ + kENET_VlanRemove, /*!< Remove VLAN Tag. */ + kENET_VlanInsert, /*!< Insert VLAN Tag. */ + kENET_VlanReplace, /*!< Replace VLAN Tag. */ +} enet_vlan_ops_t; + +/*! @brief Ethernet VLAN strip setting. */ +typedef enum _enet_vlan_strip +{ + kENET_VlanNotStrip = 0x0U, /*!< Not strip frame. */ + kENET_VlanFilterPassStrip, /*!< Strip if VLAN filter passes. */ + kENET_VlanFilterFailStrip, /*!< Strip if VLAN filter fails. */ + kENET_VlanAlwaysStrip, /*!< Always strip. */ +} enet_vlan_strip_t; + +/*! @brief Ethernet VLAN Tx channels. */ +typedef enum _enet_vlan_tx_channel +{ + kENET_VlanTagAllChannels = 0xFFU, /*!< VLAN tag is inserted for every packets transmitted by the MAC. */ + kENET_VlanTagChannel0 = 0x0U, /*!< VLAN tag is inserted for the frames transmitted by channel 0. */ + kENET_VlanTagChannel1, /*!< VLAN tag is inserted for the frames transmitted by channel 1. */ +} enet_vlan_tx_channel_t; + /*! @brief Defines the receive descriptor structure * It has the read-format and write-back format structures. They both * have the same size with different region definition. So we define @@ -314,6 +357,21 @@ typedef struct _enet_tx_bd_struct __IO uint32_t tdes3; /*!< Transmit descriptor 3 */ } enet_tx_bd_struct_t; +/*! @brief Defines the Tx BD configuration structure. */ +typedef struct _enet_tx_bd_config_struct +{ + void *buffer1; /*!< The first buffer address in the descriptor. */ + uint32_t bytes1; /*!< The bytes in the fist buffer. */ + void *buffer2; /*!< The second buffer address in the descriptor. */ + uint32_t bytes2; /*!< The bytes in the second buffer. */ + uint32_t framelen; /*!< The length of the frame to be transmitted. */ + bool intEnable; /*!< Interrupt enable flag. */ + bool tsEnable; /*!< The timestamp enable. */ + enet_tx_offload_t txOffloadOps; /*!< The Tx checksum offload option, only vaild for Queue 0. */ + enet_desc_flag_t flag; /*!< The flag of this tx desciriptor, see "enet_qos_desc_flag". */ + uint8_t slotNum; /*!< The slot number used for AV mode only. */ +} enet_tx_bd_config_struct_t; + #ifdef ENET_PTP1588FEATURE_REQUIRED /*! @brief Defines the ENET PTP configuration structure. */ typedef struct _enet_ptp_config @@ -322,7 +380,7 @@ typedef struct _enet_ptp_config bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */ enet_ts_rollover_type_t tsRollover; /*!< 1588 time nanosecond rollover. */ } enet_ptp_config_t; -#endif /* ENET_PTP1588FEATURE_REQUIRED */ +#endif /* ENET_PTP1588FEATURE_REQUIRED */ /*! @brief Defines the ENET PTP time stamp structure. */ typedef struct _enet_ptp_time @@ -472,6 +530,7 @@ struct _enet_handle enet_tx_dirty_ring_t txDirtyRing[ENET_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses. */ uint32_t *rxBufferStartAddr[ENET_RING_NUM_MAX]; /*!< The Init-Rx buffers used for reinit corrupted BD due to write-back operation. */ + uint32_t txLenLimitation[ENET_RING_NUM_MAX]; /*!< Tx frame length limitation. */ enet_callback_t callback; /*!< Callback function. */ void *userData; /*!< Callback function parameter.*/ enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */ @@ -513,9 +572,10 @@ typedef struct _enet_rx_frame_struct typedef struct _enet_tx_config_struct { - uint8_t intEnable : 1; /*!< Enable interrupt every time one BD is completed. */ - uint8_t tsEnable : 1; /*!< Transmit timestamp enable. */ - uint8_t slotNum : 4; /*!< Slot number control bits in AV mode. */ + uint8_t intEnable : 1; /*!< Enable interrupt every time one BD is completed. */ + uint8_t tsEnable : 1; /*!< Transmit timestamp enable. */ + uint8_t slotNum : 4; /*!< Slot number control bits in AV mode. */ + enet_tx_offload_t txOffloadOps; /*!< Tx checksum offload option. */ } enet_tx_config_struct_t; typedef struct _enet_tx_frame_struct @@ -526,6 +586,39 @@ typedef struct _enet_tx_frame_struct void *context; /*!< Driver reclaims and gives it in Tx over callback. */ } enet_tx_frame_struct_t; +/*! @brief Ethernet VLAN Tag. */ +typedef struct _enet_vlan_tag +{ + enet_vlan_tpid_t tpid; /*!< VLAN TPID. */ + uint16_t pcp : 3; /*!< VLAN Priority. */ + uint16_t dei : 1; /*!< Drop Eligible indicator. */ + uint16_t vid : 12; /*!< VLAN Identifier. */ +} enet_vlan_tag_t; + +/*! @brief Ethernet VLAN configuration for Tx. */ +typedef struct _enet_vlan_tx_config +{ + bool txDescVlan; /*!< Use VLAN configuration in Tx descriptor. */ + enet_vlan_tag_t tag; /*!< VLAN Tag. */ + enet_vlan_ops_t ops; /*!< VLAN operations. */ +} enet_vlan_tx_config_t; + +/*! @brief Ethernet VLAN control. */ +typedef struct _enet_vlan_ctrl +{ + bool svlanEnable : 1; /*!< The MAC transmitter and receiver consider the S-VLAN packets. */ + bool vlanInverseMatch : 1; /*!< True: Marks frames without matching as match, False: Marks matched frames. */ + bool vidComparison : 1; /*!< Only takes VLAN VID as match. */ + bool disableVlanTypeCheck : 1; /*!< Not check C-VLAN and S-VLAN. */ + bool doubleVlanEnable : 1; /*!< Enable the inner VLAN operations. */ + bool innerVlanFilterMatch : 1; /*!< Takes Inner VLAN as match. */ + bool outerTagInRxStatus : 1; /*!< Set outer VLAN in Rx Status. */ + bool innerTagInRxStatus : 1; /*!< Set inner VLAN in Rx Status. */ + enet_vlan_tag_t rxVlanTag; /*!< VLAN tag for Rx match. */ + enet_vlan_strip_t rxOuterVlanStrip; /*!< Outer VLAN Rx strip operation. */ + enet_vlan_strip_t rxInnerVlanStrip; /*!< Inner VLAN Rx strip operation. */ +} enet_vlan_ctrl_t; + /* Typedef for interrupt handler. */ typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); @@ -853,6 +946,31 @@ static inline void ENET_ExitPowerDown(ENET_Type *base) base->MAC_CONFIGURATION |= ENET_MAC_CONFIGURATION_TE_MASK; } +/*! + * @brief Set VLAN control. + * + * @param base ENET peripheral base address. + * @param control VLAN control configuration. + */ +status_t ENET_SetVlanCtrl(ENET_Type *base, enet_vlan_ctrl_t *control); + +/*! + * @brief Set Tx outer VLAN configuration. + * + * @param base ENET peripheral base address. + * @param config Tx VLAN operation configuration. + * @param channel The channel to apply this configuration. + */ +status_t ENET_SetTxOuterVlan(ENET_Type *base, enet_vlan_tx_config_t *config, enet_vlan_tx_channel_t channel); + +/*! + * @brief Set Tx inner VLAN configuration. + * + * @param base ENET peripheral base address. + * @param config Tx VLAN operation configuration. + */ +status_t ENET_SetTxInnerVlan(ENET_Type *base, enet_vlan_tx_config_t *config); + /* @} */ /*! @@ -1169,10 +1287,7 @@ status_t ENET_ReadFrame(ENET_Type *base, * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application. * @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer) - * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this - * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's - * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according - * to specific design in this case. + * to make this function work normally. * * @param base ENET peripheral base address. * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. @@ -1302,4 +1417,4 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecon /*! @}*/ -#endif /* _FSL_ENET_H_ */ +#endif /* FSL_ENET_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c index 4e558ec7f0..cdd35b56b0 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c @@ -65,9 +65,13 @@ void ERM_Init(ERM_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ base->CR0 = 0x00U; +#ifdef ERM_CR1_ENCIE8_MASK base->CR1 = 0x00U; +#endif base->SR0 = 0xFFFFFFFFU; +#ifdef ERM_SR1_SBC8_MASK base->SR1 = 0xFFFFFFFFU; +#endif } /*! @@ -86,66 +90,41 @@ uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel) { uint32_t absoluteErrorAddress = 0x00U; - switch (channel) + switch ((uint8_t)channel) { - case kERM_MemoryChannelRAMX: - /* Total RAMX size: 96KB - RAMX0: 32KB(0x04000000 ~ 0x04007FFF) - RAMX1: 32KB(0x04008000 ~ 0x0400FFFF) - RAMX2: 32KB(0x04100000 ~ 0x04017FFF) - */ + case 0U: absoluteErrorAddress = base->EAR0; break; - - case kERM_MemoryChannelRAMA: - /* Total RAMA size: 32KB - RAMA0: 8KB(0x20000000 ~ 0x20001FFF) - RAMA1: 8KB(0x20002000 ~ 0x20003FFF) - RAMA2: 8KB(0x20004000 ~ 0x20005FFF) - RAMA3: 8KB(0x20006000 ~ 0x20007FFF) - */ +#ifdef ERM_EAR1_EAR_MASK + case 1U: absoluteErrorAddress = base->EAR1; break; - - case kERM_MemoryChannelRAMB: - /* Total RAMB size: 32KB - RAMB0: 32KB(0x20008000 ~ 0x2000FFFF) - */ +#endif +#ifdef ERM_EAR2_EAR_MASK + case 2U: absoluteErrorAddress = base->EAR2; break; - - case kERM_MemoryChannelRAMC: - /* Total RAMC size: 64KB - RAMC0: 32KB(0x20010000 ~ 0x20017FFF) - RAMC0: 32KB(0x20018000 ~ 0x2001FFFF) - */ +#endif +#ifdef ERM_EAR3_EAR_MASK + case 3U: absoluteErrorAddress = base->EAR3; break; - - case kERM_MemoryChannelRAMD: - /* Total RAMD size: 64KB - RAMD0: 32KB(0x20020000 ~ 0x20027FFF) - RAMD0: 32KB(0x20028000 ~ 0x2002FFFF) - */ +#endif +#ifdef ERM_EAR4_EAR_MASK + case 4U: absoluteErrorAddress = base->EAR4; break; - - case kERM_MemoryChannelRAME: - /* Total RAME size: 64KB - RAME0: 32KB(0x20030000 ~ 0x20037FFF) - RAME0: 32KB(0x20038000 ~ 0x2003FFFF) - */ +#endif +#ifdef ERM_EAR5_EAR_MASK + case 5U: absoluteErrorAddress = base->EAR5; break; - - case kERM_MemoryChannelRAMF: - /* Total RAMF size: 64KB - RAMF0: 32KB(0x20040000 ~ 0x20047FFF) - RAMF0: 32KB(0x20048000 ~ 0x2004FFFF) - */ +#endif +#ifdef ERM_EAR6_EAR_MASK + case 6U: absoluteErrorAddress = base->EAR6; break; - +#endif default: assert(NULL); break; @@ -158,48 +137,56 @@ uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel) { uint32_t syndrome = 0x00U; - switch (channel) + switch ((uint8_t)channel) { - case kERM_MemoryChannelRAMX: + case 0U: syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelRAMA: +#ifdef ERM_SYN1_SYNDROME_MASK + case 1U: syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelRAMB: +#endif +#ifdef ERM_SYN2_SYNDROME_MASK + case 2U: syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelRAMC: +#endif +#ifdef ERM_SYN3_SYNDROME_MASK + case 3U: syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelRAMD: +#endif +#ifdef ERM_SYN4_SYNDROME_MASK + case 4U: syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelRAME: +#endif +#ifdef ERM_SYN5_SYNDROME_MASK + case 5U: syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelRAMF: +#endif +#ifdef ERM_SYN6_SYNDROME_MASK + case 6U: syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelLPCACRAM: - assert(NULL); +#endif +#ifdef ERM_SYN7_SYNDROME_MASK + case 7U: + syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelPKCRAM: +#endif +#ifdef ERM_SYN8_SYNDROME_MASK + case 8U: syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT; break; - - case kERM_MemoryChannelFLASH: - assert(NULL); +#endif +#ifdef ERM_SYN9_SYNDROME_MASK + case 8U: + syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT; break; - +#endif default: assert(NULL); break; @@ -212,48 +199,56 @@ uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel) { uint32_t count = 0x00U; - switch (channel) + switch ((uint8_t)channel) { - case kERM_MemoryChannelRAMX: + case 0U: count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT; break; - - case kERM_MemoryChannelRAMA: +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT; break; - - case kERM_MemoryChannelRAMB: +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT; break; - - case kERM_MemoryChannelRAMC: +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT; break; - - case kERM_MemoryChannelRAMD: +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT; break; - - case kERM_MemoryChannelRAME: +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT; break; - - case kERM_MemoryChannelRAMF: +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT; break; - - case kERM_MemoryChannelLPCACRAM: +#endif +#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK + case 7U: count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT; break; - - case kERM_MemoryChannelPKCRAM: +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT; break; - - case kERM_MemoryChannelFLASH: +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT; break; - +#endif default: assert(NULL); break; @@ -264,48 +259,57 @@ uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel) void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel) { - switch (channel) + switch ((uint8_t)channel) { - case kERM_MemoryChannelRAMX: + case 0U: base->CORR_ERR_CNT0 = 0x00U; break; - case kERM_MemoryChannelRAMA: +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: base->CORR_ERR_CNT1 = 0x00U; break; - - case kERM_MemoryChannelRAMB: +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: base->CORR_ERR_CNT2 = 0x00U; break; - - case kERM_MemoryChannelRAMC: +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: base->CORR_ERR_CNT3 = 0x00U; break; - - case kERM_MemoryChannelRAMD: +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: base->CORR_ERR_CNT4 = 0x00U; break; - - case kERM_MemoryChannelRAME: +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: base->CORR_ERR_CNT5 = 0x00U; break; - - case kERM_MemoryChannelRAMF: +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: base->CORR_ERR_CNT6 = 0x00U; break; - - case kERM_MemoryChannelLPCACRAM: +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 7U: base->CORR_ERR_CNT7 = 0x00U; break; - - case kERM_MemoryChannelPKCRAM: +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: base->CORR_ERR_CNT8 = 0x00U; break; - - case kERM_MemoryChannelFLASH: +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: base->CORR_ERR_CNT9 = 0x00U; break; - +#endif default: assert(NULL); break; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h index 5dd34b162e..45303523e7 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_ERM_H_ -#define _FSL_ERM_H_ +#ifndef FSL_ERM_H_ +#define FSL_ERM_H_ #include "fsl_common.h" @@ -21,10 +21,10 @@ *****************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief Driver version. */ -#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) -/*@}*/ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*! @} */ /*! * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable. @@ -78,7 +78,7 @@ void ERM_Init(ERM_Type *base); */ void ERM_Deinit(ERM_Type *base); -/* @} */ +/*! @} */ /*! * @name Interrupt @@ -101,12 +101,14 @@ static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t cha base->CR0 = (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U)); } +#ifdef ERM_CR1_ESCIE8_MASK else { temp = base->CR1; base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) | (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); } +#endif } /*! @@ -123,10 +125,12 @@ static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t ch { base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U)); } +#ifdef ERM_CR1_ESCIE8_MASK else { base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); } +#endif } /*! @@ -141,10 +145,16 @@ static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel { return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U); } +#ifdef ERM_SR1_SBC8_MASK else { return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U)); } +#else + { + return 0; + } +#endif } /*! @@ -159,13 +169,15 @@ static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t { base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U); } +#ifdef ERM_SR1_SBC8_MASK else { base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U); } +#endif } -/* @} */ +/*! @} */ /*! * @name functional diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h index a51d0bef1a..106cd53bab 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_EVTG_H_ -#define _FSL_EVTG_H_ +#ifndef FSL_EVTG_H_ +#define FSL_EVTG_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief EVTG driver version. */ #define FSL_EVTG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ -/*@}*/ +/*! @} */ /*! @brief EVTG instance index. */ typedef enum _evtg_index @@ -247,7 +247,7 @@ static inline void EVTG_ForceFlipflopInitOutput(EVTG_Type *base, evtg_index_t evtgIndex, evtg_flipflop_init_output_t flipflopInitOutputValue) { - base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~(uint16_t)EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK); base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_FF_INIT((uint16_t)flipflopInitOutputValue); /* INIT_EN bit should be set after FF_INIT is set. */ @@ -284,20 +284,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base, if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1)) { base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 &= - (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 |= - (((uint16_t)(((uint16_t)(input)) - << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) & - (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); } else { base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 &= - (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 |= - (((uint16_t)(((uint16_t)(input)) - << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) & - (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); } } else if (kEVTG_AOI1 == aoiIndex) @@ -305,20 +305,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base, if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1)) { base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 &= - (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 |= - (((uint16_t)(((uint16_t)(input)) - << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) & - (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); } else { base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 &= - (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 |= - (((uint16_t)(((uint16_t)(input)) - << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) & - (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); } } else @@ -352,4 +352,4 @@ void EVTG_ConfigAOIProductTerm(EVTG_Type *base, /*! @} */ -#endif /* _FSL_EVTG_H_ */ +#endif /* FSL_EVTG_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h index dbef1b3d07..2d62fcdda3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_EWM_H_ -#define _FSL_EWM_H_ +#ifndef FSL_EWM_H_ +#define FSL_EWM_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief EWM driver version 2.0.3. */ #define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ +/*! @} */ /*! @brief Describes EWM clock source. */ #if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT @@ -141,7 +141,7 @@ void EWM_Deinit(EWM_Type *base); */ void EWM_GetDefaultConfig(ewm_config_t *config); -/* @} */ +/*! @} */ /*! * @name EWM functional Operation @@ -207,7 +207,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) */ void EWM_Refresh(EWM_Type *base); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -215,4 +215,4 @@ void EWM_Refresh(EWM_Type *base); /*! @}*/ -#endif /* _FSL_EWM_H_ */ +#endif /* FSL_EWM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.c index 37663a6971..8717791e18 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -8,6 +8,17 @@ #include "fsl_flexcan.h" +/* + * $Coverage Justification Reference$ + * + * $Justification flexcan_c_ref_1$ + * The FLEXCAN_ReadRxFifo() return fail only when Rx FIFO is diabled. But in IRQ handler, will first check whether the + * FIFO is enabled, and only call FLEXCAN_ReadRxFifo if the FIFO is enabled. So to cover this line/branch, need to + * interrupt the current execution by a high priority IRQ after confirming that the FIFO is enabled, and disabled the + * FIFO in the high priority interrupt. It is difficult to simulate this situation in unit test, so add Justification. + * + */ + /******************************************************************************* * Definitions ******************************************************************************/ @@ -87,7 +98,11 @@ #define MIN_TIME_SEGMENT2 (2U) /* Define maximum CAN and CAN FD bit rate supported by FLEXCAN. */ -#define MAX_CANFD_BITRATE (10000000U) +#if (defined(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#define MAX_CANFD_BITRATE ((uint32_t)(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#else +#define MAX_CANFD_BITRATE (8000000U) +#endif #define MAX_CAN_BITRATE (1000000U) #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) @@ -110,6 +125,12 @@ #endif /* CAN_CLOCK_CHECK_NO_AFFECTS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXCAN_RSTS) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS +#elif defined(FLEXCAN_RSTS_N) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS_N +#endif + /*! @brief FlexCAN Internal State. */ enum _flexcan_state { @@ -309,6 +330,11 @@ static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; #endif /* FLEXCAN_PERIPH_CLOCKS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXCAN_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexcanResets[] = FLEXCAN_RESETS_ARRAY; +#endif + /* FlexCAN ISR for transactional APIs. */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR; @@ -323,7 +349,7 @@ static flexcan_isr_t s_flexcanIsr; static void flexcan_memset(void *s, uint32_t c, size_t n) { size_t m; - uint32_t *ptr = s; + volatile uint32_t *ptr = s; m = n / sizeof(*ptr); @@ -336,6 +362,46 @@ static void flexcan_memset(void *s, uint32_t c, size_t n) /******************************************************************************* * Code ******************************************************************************/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Determine whether the FlexCAN instance support CAN FD mode at run time. + * + * note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part + * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. + * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be + * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, + * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode. + * + * param base FlexCAN peripheral base address. + * return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode. + */ +bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + /* Enable CAN FD operation. */ + base->MCR |= CAN_MCR_FDEN_MASK; + + /* There are some SoC parts that don't support CAN FD. + * Checking if FDEN bit is really set to 1 is a way to ensure that CAN FD is supported. + * When SoC parts don't support CAN FD, FDEN bit stuck at 0 and can't be set to 1. */ + if (0U == (base->MCR & CAN_MCR_FDEN_MASK)) + { + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + return false; + } + else + { + /* Clear CAN FD operation. */ + base->MCR &= ~CAN_MCR_FDEN_MASK; + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + return true; + } +} +#endif + /*! * brief Get the FlexCAN instance from peripheral base address. * @@ -396,6 +462,7 @@ void FLEXCAN_EnterFreezeMode(CAN_Type *base) /* Step4: to check FLTCONF in ESR1 register */ if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF)) { + /* Error Active and Error Passive state */ /* Step5B: Set Halt bits. */ base->MCR |= CAN_MCR_HALT_MASK; @@ -406,9 +473,40 @@ void FLEXCAN_EnterFreezeMode(CAN_Type *base) { u32TimeoutCount--; } + + /* Merge ERRATA_9595 and ERRATA_8341 because both errata exist on some platform. */ + if (0U == u32TimeoutCount) + { + /* backup MCR and IMASK register. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + /* Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared, timeout need more than 178 + * CAN bit length, so 20 multiply timeout is enough. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U; + while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } } else { + /* Bus Off state */ /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ u32TempMCR = base->MCR; u32TempIMASK1 = base->IMASK1; @@ -838,6 +936,10 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sour #endif /* FLEXCAN_PERIPH_CLOCKS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXCAN_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexcanResets[FLEXCAN_GetInstance(base)]); +#endif + #if defined(CAN_CTRL1_CLKSRC_MASK) #if (defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) && FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) @@ -990,7 +1092,7 @@ void FLEXCAN_FDInit( uint16_t maxDivider; /* Check bit rate value. */ - assert((pConfig->bitRateFD <= 10000000U) && (tqFre <= sourceClock_Hz)); + assert((pConfig->bitRateFD <= MAX_CANFD_BITRATE) && (tqFre <= sourceClock_Hz)); #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) assert((tqFre * MAX_EDPRESDIV) >= sourceClock_Hz); maxDivider = MAX_EDPRESDIV; @@ -2801,7 +2903,7 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra cs_temp |= CAN_CS_RTR_MASK; } - cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length) | CAN_CS_EDL(1) | + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length) | CAN_CS_EDL(pTxFrame->edl) | CAN_CS_BRS(pTxFrame->brs); /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 @@ -2969,6 +3071,12 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *p pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : (uint8_t)kFLEXCAN_FrameFormatStandard; + /* Get Bit Rate Switch flag. */ + pRxFrame->brs = (cs_temp & CAN_CS_BRS_MASK) != 0U ? 1U : 0U; + + /* Get Extended Data Length flag. */ + pRxFrame->edl = (cs_temp & CAN_CS_EDL_MASK) != 0U ? 1U : 0U; + /* Get the message type. */ pRxFrame->type = (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; @@ -3143,23 +3251,34 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame)) { -/* Wait until CAN Message send out. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) -#else - uint32_t u32flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) -#endif + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) { } - -/* Clean Tx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); #else - FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); #endif + /*After TX MB tranfered success, update the Timestamp from MB[mbIdx].CS register*/ pTxFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); @@ -3188,21 +3307,31 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) { /* Wait until Rx Message Buffer non-empty. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) -#else - uint32_t u32flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) -#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) { } - -/* Clean Rx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); #else - FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); #endif /* Read Received CAN Message. */ @@ -3228,22 +3357,32 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame)) { -/* Wait until CAN Message send out. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) -#else - uint32_t u32flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) -#endif + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) { } - -/* Clean Tx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); #else - FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); #endif /*After TX MB tranfered success, update the Timestamp from base->MB[offset for CAN FD].CS register*/ volatile uint32_t *mbAddr = &(base->MB[0].CS); @@ -3275,21 +3414,31 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) { /* Wait until Rx Message Buffer non-empty. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) -#else - uint32_t u32flag = 1; - while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) -#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) { } - -/* Clean Rx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); #else - FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); #endif /* Read Received CAN Message. */ @@ -3477,13 +3626,20 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl if (kStatus_Success == FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame)) { -/* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); #endif status = kStatus_Success; } @@ -3533,13 +3689,20 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha /* Register Message Buffer. */ handle->mbFrameBuf[pMbXfer->mbIdx] = pMbXfer->frame; -/* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); #endif status = kStatus_Success; @@ -3594,13 +3757,20 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd)) { -/* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); #endif status = kStatus_Success; @@ -3651,13 +3821,20 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t * /* Register Message Buffer. */ handle->mbFDFrameBuf[pMbXfer->mbIdx] = pMbXfer->framefd; -/* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); #endif status = kStatus_Success; @@ -3830,14 +4007,20 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t #if !defined(NDEBUG) assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); #endif - -/* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); #endif /* Update the TX frame 's time stamp by MB[mbIdx].cs. */ @@ -3873,13 +4056,20 @@ void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); #endif -/* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); #endif /* Update the TX frame 's time stamp by base->MB[offset for CAN FD].CS. */ @@ -3912,13 +4102,20 @@ void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, ui assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); #endif -/* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); #endif /* Un-register handle. */ @@ -3945,13 +4142,20 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); #endif -/* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64mask = 1; - FLEXCAN_DisableMbInterrupts(base, (u64mask << mbIdx)); + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); #else - uint32_t u32mask = 1; - FLEXCAN_DisableMbInterrupts(base, (u32mask << mbIdx)); + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); #endif /* Un-register handle. */ @@ -4073,6 +4277,18 @@ static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base) tempflag |= ((uint64_t)base->IFLAG2) << 32; #endif fgRet = (0U != (tempmask & tempflag)); +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + if (0U != (base->IMASK3 & base->IFLAG3)) + { + fgRet = true; + } +#endif +#if defined(CAN_IMASK4_BUF127TO96M_MASK) + if (0U != (base->IMASK4 & base->IFLAG4)) + { + fgRet = true; + } +#endif } #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) else if (0U != (FLEXCAN_GetStatusFlags(base) & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG)) @@ -4092,6 +4308,219 @@ static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base) return fgRet; } +/*! + * brief Sub Handler Legacy Rx FIFO Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param result The MB flag number. + * + * return the status after handle transfered event. + */ +static status_t FLEXCAN_SubHandlerForLegacyRxFIFO(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) +{ + uint32_t u32mask = 1; + status_t status = kStatus_FLEXCAN_UnHandled; + + switch (u32mask << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + if ((handle->rxFifoFrameNum > 5U) && (0U != (base->IFLAG1 & (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag))) + { + for (uint32_t i = 0; i < 5UL; i++) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + /* + * $Branch Coverage Justification$ + * (kStatus_Success != status) not covered. $ref flexcan_c_ref_1$. + */ + if (kStatus_Success == status) + { + /* Align the current rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[i] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + /* Clean Rx Fifo available flag to discard the frame that has been read. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + else + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum < 5UL) + { + /* Enable data avaliable interrupt. */ + FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Should enter case kFLEXCAN_RxFifoFrameAvlFlag but not, means previous transfer may have + * overflow*/ + status = kStatus_FLEXCAN_RxFifoWarning; + } + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + /* Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + /* + * $Branch Coverage Justification$ + * (kStatus_Success != status) not covered. $ref flexcan_c_ref_1$. + */ + if (kStatus_Success == status) + { + /* Align the current (index 0) rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[0] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + + return status; +} + +/*! + * brief Sub Handler Message Buffer Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param result The MB flag number. + * + * return the status after handle transfered event. + */ +static status_t FLEXCAN_SubHandlerForMB(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) +{ + status_t status = kStatus_FLEXCAN_UnHandled; + + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case (uint8_t)kFLEXCAN_StateRxData: +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + } + } + else +#endif + { + status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + } + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Sove Rx Remote Frame. User need to Read the frame in Mail box in time by Read from MB API. */ + case (uint8_t)kFLEXCAN_StateRxRemote: + status = kStatus_FLEXCAN_RxRemote; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Data Frame. */ + case (uint8_t)kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Remote Frame. */ + case (uint8_t)kFLEXCAN_StateTxRemote: + handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + + return status; +} + /*! * brief Sub Handler Data Trasfered Events * @@ -4107,23 +4536,43 @@ static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_hand uint32_t result = 0xFFU; #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t intflag = (((uint64_t)base->IMASK2 & base->IFLAG2) << 32UL) | (base->IMASK1 & base->IFLAG1); + uint32_t intflag[4] = {(base->IMASK1 & base->IFLAG1), (base->IMASK2 & base->IFLAG2), 0U, 0U}; +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + intflag[2] = base->IMASK3 & base->IFLAG3; +#endif +#if defined(CAN_IMASK4_BUF127TO96M_MASK) + intflag[3] = base->IMASK4 & base->IFLAG4; +#endif #else uint32_t intflag = base->IMASK1 & base->IFLAG1; #endif + /* For this implementation, we solve the Message with lowest MB index first. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + for (uint32_t i = 0U; i < 4U; i++) + { + if (intflag[i] != 0U) + { + for (uint32_t j = 0U; j < 32U; j++) + { + if (0UL != (intflag[i] & ((uint32_t)1UL << j))) + { + result = i * 32U + j; + break; + } + } + break; + } + } +#else for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) { - /* Find the lowest unhandled Message Buffer */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - if (0UL != (intflag & ((uint64_t)1UL << result))) -#else if (0UL != (intflag & ((uint32_t)1UL << result))) -#endif { break; } } +#endif /* find Message to deal with. */ if (result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) @@ -4132,174 +4581,39 @@ static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_hand if (((uint8_t)kFLEXCAN_StateIdle != handle->rxFifoState) && (result <= (uint32_t)CAN_IFLAG1_BUF7I_SHIFT) && ((base->MCR & CAN_MCR_RFEN_MASK) != 0U)) { - uint32_t u32mask = 1; - switch (u32mask << result) + status = FLEXCAN_SubHandlerForLegacyRxFIFO(base, handle, result); + /* + * $Branch Coverage Justification$ + * (status == kStatus_FLEXCAN_RxFifoDisabled) not covered. $ref flexcan_c_ref_1$. + */ + if (status == kStatus_FLEXCAN_RxFifoDisabled) { - case kFLEXCAN_RxFifoOverflowFlag: - status = kStatus_FLEXCAN_RxFifoOverflow; - break; - - case kFLEXCAN_RxFifoWarningFlag: - if ((handle->rxFifoFrameNum > 5U) && (0U != (base->IFLAG1 & (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag))) - { - for (uint32_t i = 0; i < 5UL; i++) - { - status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); - - if (kStatus_Success == status) - { - /* Align the current rxfifo timestamp to the timestamp array by handle. */ - handle->timestamp[i] = handle->rxFifoFrameBuf->timestamp; - handle->rxFifoFrameBuf++; - handle->rxFifoFrameNum--; - /* Clean Rx Fifo available flag to discard the frame that has been read. */ - FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); - } - else - { - return kStatus_FLEXCAN_RxFifoDisabled; - } - } - if (handle->rxFifoFrameNum < 5UL) - { - /* Enable data avaliable interrupt. */ - FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); - } - status = kStatus_FLEXCAN_RxFifoBusy; - } - else - { - /* Should enter case kFLEXCAN_RxFifoFrameAvlFlag but not, means previous transfer may have - * overflow*/ - status = kStatus_FLEXCAN_RxFifoWarning; - } - break; - - case kFLEXCAN_RxFifoFrameAvlFlag: - /* Whether still has CAN messages remaining to be received. */ - if (handle->rxFifoFrameNum > 0U) - { - status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); - if (kStatus_Success == status) - { - /* Align the current (index 0) rxfifo timestamp to the timestamp array by handle. */ - handle->timestamp[0] = handle->rxFifoFrameBuf->timestamp; - handle->rxFifoFrameBuf++; - handle->rxFifoFrameNum--; - } - else - { - return kStatus_FLEXCAN_RxFifoDisabled; - } - } - if (handle->rxFifoFrameNum == 0U) - { - /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ - FLEXCAN_TransferAbortReceiveFifo(base, handle); - status = kStatus_FLEXCAN_RxFifoIdle; - } - else - { - /* Continue use data avaliable interrupt. */ - status = kStatus_FLEXCAN_RxFifoBusy; - } - break; - - default: - status = kStatus_FLEXCAN_UnHandled; - break; + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return status; } } else { - /* Get current State of Message Buffer. */ - switch (handle->mbState[result]) - { - /* Solve Rx Data Frame. */ - case (uint8_t)kFLEXCAN_StateRxData: -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) - { - status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); - if (kStatus_Success == status) - { - /* Align the current index of RX MB timestamp to the timestamp array by handle. */ - handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; - status = kStatus_FLEXCAN_RxIdle; - } - } - else -#endif - { - status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); - if (kStatus_Success == status) - { - /* Align the current index of RX MB timestamp to the timestamp array by handle. */ - handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; - status = kStatus_FLEXCAN_RxIdle; - } - } -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) - { - FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); - } - else -#endif - { - FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); - } - break; - - /* Sove Rx Remote Frame. User need to Read the frame in Mail box in time by Read from MB API. */ - case (uint8_t)kFLEXCAN_StateRxRemote: - status = kStatus_FLEXCAN_RxRemote; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) - { - FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); - } - else -#endif - { - FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); - } - break; - - /* Solve Tx Data Frame. */ - case (uint8_t)kFLEXCAN_StateTxData: - status = kStatus_FLEXCAN_TxIdle; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) - { - FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); - } - else -#endif - { - FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); - } - break; - - /* Solve Tx Remote Frame. */ - case (uint8_t)kFLEXCAN_StateTxRemote: - handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote; - status = kStatus_FLEXCAN_TxSwitchToRx; - break; - - default: - status = kStatus_FLEXCAN_UnHandled; - break; - } + status = FLEXCAN_SubHandlerForMB(base, handle, result); } /* Clear resolved Message Buffer IRQ. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - uint64_t u64flag = 1; - FLEXCAN_ClearMbStatusFlags(base, u64flag << result); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (result >= 64U) + { + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (result - 64U)); + } + else + { + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); #else - uint32_t u32flag = 1; - FLEXCAN_ClearMbStatusFlags(base, u32flag << result); + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << result); #endif } @@ -4607,7 +4921,7 @@ void CAN_FD2_DriverIRQHandler(void) { assert(NULL != s_flexcanHandle[2]); - s_flexcanIsr(FLEXCAN1, s_flexcanHandle[2]); + s_flexcanIsr(FLEXCAN2, s_flexcanHandle[2]); SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h index b3d1c46a33..9170938afe 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXCAN_H_ -#define _FSL_FLEXCAN_H_ +#ifndef FSL_FLEXCAN_H_ +#define FSL_FLEXCAN_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ *****************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexCAN driver version. */ -#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 9, 2)) -/*@}*/ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 6)) +/*! @} */ #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) /* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ @@ -231,7 +231,7 @@ #endif /*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) -#define E_RX_FIFO(base) ((uint32_t)(base) + 0x2000U) +#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U) #else #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U) #endif @@ -339,7 +339,7 @@ enum _flexcan_fd_frame_length kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */ kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */ kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */ - kFLEXCAN_24Bperrame, /*!< Frame contains 24 valid data bytes. */ + kFLEXCAN_24BperFrame, /*!< Frame contains 24 valid data bytes. */ kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */ kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */ kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */ @@ -1025,6 +1025,22 @@ extern "C" { * @{ */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Determine whether the FlexCAN instance support CAN FD mode at run time. + * + * @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part + * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. + * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be + * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, + * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode. + * + * @param base FlexCAN peripheral base address. + * @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode. + */ +bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base); +#endif + /*! * @brief Enter FlexCAN Freeze Mode. * @@ -1185,7 +1201,7 @@ void FLEXCAN_Deinit(CAN_Type *base); */ void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig); -/* @} */ +/*! @} */ /*! * @name Configuration. @@ -1394,7 +1410,7 @@ void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_f */ void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig); #endif -/* @} */ +/*! @} */ /*! * @name Status @@ -1518,6 +1534,29 @@ static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) #endif } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Gets the FlexCAN High 64 Message Buffer interrupt flags. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) +{ + uint64_t tempflag = 0U; +#if defined(CAN_IFLAG3_BUF95TO64_MASK) + tempflag |= (uint64_t)base->IFLAG3; +#endif +#if defined(CAN_IFLAG4_BUF127TO96_MASK) + tempflag |= (uint64_t)base->IFLAG4; +#endif + return (tempflag & mask); +} +#endif + /*! * @brief Clears the FlexCAN Message Buffer interrupt flags. * @@ -1540,6 +1579,26 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) #endif } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Clears the FlexCAN High 64 Message Buffer interrupt flags. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) +{ +#if defined(CAN_IFLAG3_BUF95TO64_MASK) + base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU); +#endif +#if defined(CAN_IFLAG4_BUF127TO96_MASK) + base->IFLAG4 = (uint32_t)(mask >> 32U); +#endif +} +#endif + #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) /*! * @brief Gets the FlexCAN Memory Error Report registers status. @@ -1582,7 +1641,7 @@ static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base) return (base->ERFSR & CAN_ERFSR_ERFEL_MASK); } #endif -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -1606,6 +1665,8 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask) static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) #endif { + uint32_t primask = DisableGlobalIRQ(); + /* Solve Self Wake Up interrupt. */ base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); @@ -1636,6 +1697,8 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) base->CTRL1 |= (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); + + EnableGlobalIRQ(primask); } /*! @@ -1654,6 +1717,8 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask) static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) #endif { + uint32_t primask = DisableGlobalIRQ(); + /* Solve Wake Up Interrupt. */ base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); @@ -1684,6 +1749,8 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) base->CTRL1 &= ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); + + EnableGlobalIRQ(primask); } /*! @@ -1700,14 +1767,40 @@ static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) #endif { + uint32_t primask = DisableGlobalIRQ(); + #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); base->IMASK2 |= (uint32_t)(mask >> 32); #else base->IMASK1 |= mask; #endif + EnableGlobalIRQ(primask); } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Enables FlexCAN high 64 Message Buffer interrupts. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) +{ + uint32_t primask = DisableGlobalIRQ(); + +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU); +#endif +#if defined(CAN_IMASK4_BUF127TO96_MASK) + base->IMASK4 |= (uint32_t)(mask >> 32U); +#endif + EnableGlobalIRQ(primask); +} +#endif + /*! * @brief Disables FlexCAN Message Buffer interrupts. * @@ -1722,15 +1815,41 @@ static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) #endif { + uint32_t primask = DisableGlobalIRQ(); + #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); base->IMASK2 &= ~((uint32_t)(mask >> 32)); #else base->IMASK1 &= ~mask; #endif + EnableGlobalIRQ(primask); } -/* @} */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Disables FlexCAN high 64 Message Buffer interrupts. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) +{ + uint32_t primask = DisableGlobalIRQ(); + +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); +#endif +#if defined(CAN_IMASK4_BUF127TO96_MASK) + base->IMASK4 &= ~((uint32_t)(mask >> 32U)); +#endif + EnableGlobalIRQ(primask); +} +#endif + +/*! @} */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) /*! @@ -1761,7 +1880,7 @@ static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) return (uintptr_t) & (base->MB[0].CS); } -/* @} */ +/*! @} */ #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ /*! @@ -1907,7 +2026,7 @@ status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame */ status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); #endif -/* @} */ +/*! @} */ /*! * @name Transactional @@ -2230,7 +2349,7 @@ void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t * */ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -2238,4 +2357,4 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); /*! @}*/ -#endif /* _FSL_FLEXCAN_H_ */ +#endif /* FSL_FLEXCAN_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.c new file mode 100644 index 0000000000..a5f68487f3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan_edma" +#endif + +/*base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + framefd = flexcanPrivateHandle->handle->framefd; + for (uint32_t i = 0; i < flexcanPrivateHandle->handle->frameNum; i++) + { + /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ + idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U; + framefd->idhit = framefd->dataWord[idHitIndex]; + /* Clear the unused frame data. */ + for (uint32_t j = idHitIndex; j < 16U; j++) + { + framefd->dataWord[j] = 0x0U; + } + framefd++; + } + } +#endif + /* Disable transfer. */ + FLEXCAN_TransferAbortReceiveFifoEDMA(flexcanPrivateHandle->base, flexcanPrivateHandle->handle); + + if (NULL != flexcanPrivateHandle->handle->callback) + { + flexcanPrivateHandle->handle->callback(flexcanPrivateHandle->base, flexcanPrivateHandle->handle, + kStatus_FLEXCAN_RxFifoIdle, flexcanPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = FLEXCAN_GetInstance(base); + s_flexcanEdmaPrivateHandle[instance].base = base; + s_flexcanEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(flexcan_edma_handle_t)); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle; + handle->rxFifoEdmaHandle = rxFifoEdmaHandle; + + /* Register Callback. */ + handle->callback = callback; + handle->userData = userData; + + /* Configure Legacy/Enhanced Rx FIFO DMA callback. */ + EDMA_SetCallback(handle->rxFifoEdmaHandle, FLEXCAN_ReceiveFifoEDMACallback, &s_flexcanEdmaPrivateHandle[instance]); +} + +/*! + * brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * param base FlexCAN peripheral base address. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig) +{ + assert(NULL != pFifoXfer); + assert(NULL != pFifoXfer->frame); + assert(NULL != pEdmaConfig); + + flexcan_frame_t *fifoAddr = (flexcan_frame_t *)FLEXCAN_GetRxFifoHeadAddr(base); + +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, sizeof(flexcan_frame_t), (void *)pFifoXfer->frame, + sizeof(uint32_t), sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, + kEDMA_PeripheralToMemory); +#else + /* The Data Size of FLEXCAN Legacy RX FIFO output port is 16 Bytes, but lots of chips not support 16Bytes width DMA + * transfer. These chips always support 4Byte width memory transfer, so we need prepare Memory to Memory mode by 4 + * Bytes width mode. + */ + EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, 4U, (void *)pFifoXfer->frame, sizeof(uint32_t), + sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, kEDMA_MemoryToMemory); +#endif +} + +/*! + * brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pEdmaConfig The user configuration structure of type edma_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pEdmaConfig); + status_t status; + + /* If previous Rx FIFO receive not finished. */ + if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + + /* Submit configuration. */ + (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, (const edma_transfer_config_t *)pEdmaConfig); + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo16bytes, + kEDMA_ModuloDisable); + /* Start transfer. */ + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives the CAN Messages from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pFifoXfer->frame); + + edma_transfer_config_t dmaXferConfig = {0}; + status_t status; + + handle->frameNum = pFifoXfer->frameNum; + /* Prepare transfer. */ + FLEXCAN_PrepareTransfConfiguration(base, pFifoXfer, &dmaXferConfig); + + /* Submit configuration and start edma transfer. */ + status = FLEXCAN_StartTransferDatafromRxFIFO(base, handle, &dmaXferConfig); + + return status; +} + +/*! + * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param count Number of CAN messages receive so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->rxFifoState == (uint32_t)KFLEXCAN_RxFifoIdle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->frameNum - + EDMA_GetRemainingMajorLoopCount(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel); + } + + return result; +} + +/*! + * brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle) +{ + assert(NULL != handle->rxFifoEdmaHandle); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxFifoEdmaHandle); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + handle->framefd = NULL; +#endif + handle->frameNum = 0U; + /* Disable FlexCAN Legacy/Enhanced Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, false); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark need be set to + 1 to do successfully EDMA transfer with this API. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pFifoXfer->framefd); + + edma_transfer_config_t dmaXferConfig; + edma_minor_offset_config_t dmaMinorOffsetConfig; + status_t status; + flexcan_fd_frame_t *fifoAddr = (flexcan_fd_frame_t *)E_RX_FIFO(base); + uint32_t perReadWords = ((base->ERFCR & CAN_ERFCR_DMALW_MASK) >> CAN_ERFCR_DMALW_SHIFT) + 1U; + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + + /* If previous Rx FIFO receive not finished. */ + if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->frameNum = pFifoXfer->frameNum; + handle->framefd = pFifoXfer->framefd; + /*!< To reduce the complexity of DMA software configuration, need to set watermark to 1 to make that each DMA + request read once Rx FIFO. Because a DMA transfer cannot be dynamically changed, Number of words read per + transfer (ERFCR[DMALW] + 1) should be programmed so that the Enhanced Rx FIFO element can store the largest + CAN message present on the CAN bus. */ + if ((watermark != 1U) || ((sizeof(uint32_t) * perReadWords) != sizeof(flexcan_fd_frame_t))) + { + return kStatus_InvalidArgument; + } + + /* Prepare transfer. */ + EDMA_PrepareTransfer( + &dmaXferConfig, (void *)fifoAddr, sizeof(uint32_t), (void *)pFifoXfer->framefd, sizeof(uint32_t), + sizeof(uint32_t) * perReadWords, /* minor loop bytes : 4* perReadWords */ + sizeof(uint32_t) * perReadWords * handle->frameNum, /* major loop counts : handle->frameNum */ + kEDMA_MemoryToMemory); + /* Submit configuration. */ + (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig); + + dmaMinorOffsetConfig.enableDestMinorOffset = false; + dmaMinorOffsetConfig.enableSrcMinorOffset = true; + dmaMinorOffsetConfig.minorOffset = 128U - sizeof(uint32_t) * perReadWords; + EDMA_SetMinorOffsetConfig(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, + &dmaMinorOffsetConfig); + + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo128bytes, + kEDMA_ModuloDisable); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + /* Start transfer. */ + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + status = kStatus_Success; + } + + return status; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.h new file mode 100644 index 0000000000..90d78ef669 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCAN_EDMA_H_ +#define FSL_FLEXCAN_EDMA_H_ + +#include "fsl_flexcan.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexcan_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexCAN EDMA driver version. */ +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexcan_edma_handle flexcan_edma_handle_t; + +/*! @brief FlexCAN transfer callback function. */ +typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, + flexcan_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief FlexCAN eDMA handle + */ +struct _flexcan_edma_handle +{ + flexcan_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA handler for Rx FIFO. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + size_t frameNum; /*!< The number of messages that need to be received. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle); + +/*! + * @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count); +/*! + * @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, + flexcan_edma_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count); +} +#endif + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FLEXCAN_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c index 18531f7743..52741f2a4d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c @@ -20,6 +20,12 @@ /*< @brief user configurable flexio handle count. */ #define FLEXIO_HANDLE_COUNT 2 +#if defined(FLEXIO_RSTS) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS +#elif defined(FLEXIO_RSTS_N) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -43,6 +49,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; /* FlexIO common IRQ Handler. */ static void FLEXIO_CommonIRQHandler(void); +#if defined(FLEXIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY; +#endif + /******************************************************************************* * Codes ******************************************************************************/ @@ -96,6 +107,10 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FLEXIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]); +#endif + FLEXIO_Reset(base); ctrlReg = base->CTRL; @@ -396,6 +411,69 @@ static void FLEXIO_CommonIRQHandler(void) SDK_ISR_EXIT_BARRIER; } +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER +/*! + * brief Configure a FLEXIO pin used by the board. + * + * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. + * Then, call the FLEXIO_SetPinConfig() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalInput, + * 0U, + * kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, + * } + * Define a digital output pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalOutput, + * 0U, + * 0U + * } + * endcode + * param base FlexIO peripheral base address + * param pin FLEXIO pin number. + * param config FLEXIO pin configuration pointer. + */ +void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config) +{ + assert(NULL != config); + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + if (config->pinDirection == kFLEXIO_DigitalInput) + { + base->PINOUTE &= ~(1UL << pin); + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable)) + { + base->PINIEN = 1UL << pin; + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]); + } + + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable)) + { + base->PINREN = 1UL << pin; + } + + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable)) + { + base->PINFEN = 1UL << pin; + } + } + else + { + FLEXIO_EnablePinOutput(base, pin); + FLEXIO_PinWrite(base, pin, config->outputLogic); + } +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + void FLEXIO_DriverIRQHandler(void); void FLEXIO_DriverIRQHandler(void) { diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h index c851d5e5d7..1e1bc6278d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_H_ -#define _FSL_FLEXIO_H_ +#ifndef FSL_FLEXIO_H_ +#define FSL_FLEXIO_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexIO driver version. */ -#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @} */ /*! @brief Calculate FlexIO timer trigger.*/ #define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) @@ -294,6 +294,38 @@ typedef struct _flexio_shifter_config flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ } flexio_shifter_config_t; +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER +/*! @brief FLEXIO gpio direction definition */ +typedef enum _flexio_gpio_direction +{ + kFLEXIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kFLEXIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} flexio_gpio_direction_t; + +/*! @brief FLEXIO gpio input config */ +typedef enum _flexio_pin_input_config +{ + kFLEXIO_InputInterruptDisabled = 0x0U, /*!< Interrupt request is disabled. */ + kFLEXIO_InputInterruptEnable = 0x1U, /*!< Interrupt request is enable. */ + kFLEXIO_FlagRisingEdgeEnable = 0x2U, /*!< Input pin flag on rising edge. */ + kFLEXIO_FlagFallingEdgeEnable = 0x4U, /*!< Input pin flag on falling edge. */ +} flexio_pin_input_config_t; + +/*! + * @brief The FLEXIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, use inputConfig param. + * If configured as an output pin, use outputLogic. + */ +typedef struct _flexio_gpio_config +{ + flexio_gpio_direction_t pinDirection; /*!< FLEXIO pin direction, input or output */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + uint8_t inputConfig; /*!< Set an input config */ +} flexio_gpio_config_t; +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + /*! @brief typedef for FlexIO simulated driver interrupt handler.*/ typedef void (*flexio_isr_t)(void *base, void *handle); @@ -370,7 +402,7 @@ void FLEXIO_Deinit(FLEXIO_Type *base); */ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); -/* @} */ +/*! @} */ /*! * @name FlexIO Basic Operation @@ -490,6 +522,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_ * @brief This function set the value of the prescaler on flexio channels * * @param base Pointer to the FlexIO simulated peripheral type. + * @param index Timer index * @param clocksource Set clock value */ static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource) @@ -503,7 +536,7 @@ static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_ base->TIMCFG[index] = reg; } -/* @} */ +/*! @} */ /*! * @name FlexIO Interrupt Operation @@ -588,7 +621,7 @@ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32 base->TIMIEN &= ~mask; } -/* @} */ +/*! @} */ /*! * @name FlexIO Status Operation @@ -667,7 +700,7 @@ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask base->TIMSTAT = mask; } -/* @} */ +/*! @} */ /*! * @name FlexIO DMA Operation @@ -725,11 +758,160 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. */ status_t FLEXIO_UnregisterHandleIRQ(void *base); -/* @} */ +/*! @} */ + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER + +/*! + * @brief Configure a FLEXIO pin used by the board. + * + * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. + * Then, call the FLEXIO_SetPinConfig() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalInput, + * 0U, + * kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, + * } + * Define a digital output pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalOutput, + * 0U, + * 0U + * } + * @endcode + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @param config FLEXIO pin configuration pointer. + */ +void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config); + +/*! + * @name GPIO Output Operations + * @{ + */ + +/*! + * @brief Sets the output level of the multiple FLEXIO pins to the logic 0. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTCLR = mask; +} + +/*! + * @brief Sets the output level of the multiple FLEXIO pins to the logic 1. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTSET = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FLEXIO pins. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTTOG = mask; +} + +/*! + * @brief Sets the output level of the FLEXIO pins to the logic 1 or 0. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @param output FLEXIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + FLEXIO_ClearPortOutput(base, 1UL << pin); + } + else + { + FLEXIO_SetPortOutput(base, 1UL << pin); + } +} + +/*! + * @brief Enables the FLEXIO output pin function. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + */ +static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin) +{ + base->PINOUTE |= (1UL << pin); +} +/*! @} */ + +/*! + * @name FLEXIO PIN Input Operations + * @{ + */ + +/*! + * @brief Reads the current input value of the FLEXIO pin. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @retval FLEXIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin) +{ + return (((base->PIN) >> pin) & 0x01U); +} + +/*! + * @brief Gets the FLEXIO input pin status. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @retval FLEXIO port input status + * - 0: corresponding pin input capture no status. + * - 1: corresponding pin input capture rising or falling edge. + */ +static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin) +{ + return (((base->PINSTAT) >> pin) & 0x01U); +} + +/*! + * @brief Clears the multiple FLEXIO input pins status. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask) +{ + base->PINSTAT = mask; +} +/*! @} */ + +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ #if defined(__cplusplus) } #endif /*_cplusplus*/ -/*@}*/ +/*! @} */ -#endif /*_FSL_FLEXIO_H_*/ +#endif /*FSL_FLEXIO_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h index 8bf4707c8b..6b33abe22c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_I2C_MASTER_H_ -#define _FSL_FLEXIO_I2C_MASTER_H_ +#ifndef FSL_FLEXIO_I2C_MASTER_H_ +#define FSL_FLEXIO_I2C_MASTER_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -21,9 +21,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ #define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ +/*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef I2C_RETRY_TIMES @@ -207,7 +207,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) } } -/* @} */ +/*! @} */ /*! * @name Status @@ -235,7 +235,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); -/*@}*/ +/*! @} */ /*! * @name Interrupts @@ -260,7 +260,7 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); */ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); -/*@}*/ +/*! @} */ /*! * @name Bus Operations @@ -402,7 +402,7 @@ status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, u * @return status of status_t. */ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); -/*@}*/ +/*! @} */ /*Transactional APIs*/ @@ -475,11 +475,11 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han */ void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } #endif /*_cplusplus*/ -/*@}*/ +/*! @} */ -#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ +#endif /*FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c index b31163e02b..217b6595a3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021, 2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -117,7 +117,7 @@ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config) * brief Set desired baud rate. * * param base Pointer to the FLEXIO_MCULCD_Type structure. - * param baudRate_Bps Desired baud rate. + * param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined. * param srcClock_Hz FLEXIO clock frequency in Hz. * retval kStatus_Success Set successfully. * retval kStatus_InvalidArgument Could not set the baud rate. @@ -125,12 +125,13 @@ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config) status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { uint32_t baudRateDiv; + uint32_t baudRatePerDataLine; uint32_t timerCompare; status_t status; - uint8_t baudRatio; - baudRatio = (FLEXIO_MCULCD_DATA_BUS_WIDTH == 16) ? 2 : 1; - baudRateDiv = (srcClock_Hz + 1) / (baudRate_Bps * baudRatio); + baudRatePerDataLine = baudRate_Bps / (uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH; + + baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2U); if ((0U == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U))) { @@ -138,6 +139,8 @@ status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_B } else { + baudRateDiv--; + timerCompare = base->flexioBase->TIMCMP[base->timerIndex]; timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv; @@ -296,7 +299,7 @@ uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base) } /*! - * brief Configures the FLEXIO MCULCD to multiple beats write mode. + * brief Configures the FLEXIO MCULCD to single beats write mode. * * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to * multiple beats write mode using this function. After write operation, the configuration @@ -315,7 +318,7 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) */ uint32_t timerCompare; - uint32_t tempValue; + uint32_t timerControl; /* Enable the TX Shifter output. */ base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = @@ -343,27 +346,23 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); - /* FlexIO bug workaround, see RM register description. */ + /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus. + Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the + issue. */ + timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); - tempValue = - base->flexioBase->TIMCTL[base->timerIndex] = - FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) | - FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | - FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | - FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | - FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | - FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); - - base->flexioBase->TIMCTL[base->timerIndex] = tempValue; - - tempValue &= ~(FLEXIO_TIMCTL_PINCFG_MASK); - tempValue |= FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); - - base->flexioBase->TIMCTL[base->timerIndex] = tempValue; + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; + timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; } /*! - * brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * brief Clear the FLEXIO MCULCD single beats write mode configuration. * * Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. * @@ -374,12 +373,10 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) { /* Disable the timer. */ - uint32_t tempValue = base->flexioBase->TIMCTL[base->timerIndex]; - - tempValue &= ~(FLEXIO_TIMCTL_PINCFG_MASK); - tempValue |= FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); - - base->flexioBase->TIMCTL[base->timerIndex] = tempValue; + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); base->flexioBase->TIMCTL[base->timerIndex] = 0U; base->flexioBase->TIMCFG[base->timerIndex] = 0U; /* Clear the timer flag. */ @@ -392,7 +389,7 @@ void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) } /*! - * brief Configures the FLEXIO MCULCD to multiple beats read mode. + * brief Configures the FLEXIO MCULCD to single beats read mode. * * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured * to multiple beats read mode using this function. After read operation, the configuration @@ -461,7 +458,7 @@ void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) } /*! - * brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * brief Clear the FLEXIO MCULCD single beats read mode configuration. * * Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig. * @@ -472,6 +469,10 @@ void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) { /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); base->flexioBase->TIMCTL[base->timerIndex] = 0U; base->flexioBase->TIMCFG[base->timerIndex] = 0U; /* Clear the timer flag. */ @@ -503,6 +504,7 @@ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) */ uint32_t timerCompare; + uint32_t timerControl; uint8_t beats; uint8_t i; @@ -548,12 +550,19 @@ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); - base->flexioBase->TIMCTL[base->timerIndex] = - FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) | - FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | - FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | - FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | - FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); + /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus. + Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the + issue. */ + timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); + + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; + timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; } /*! @@ -571,6 +580,10 @@ void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) uint32_t statusFlags = 0U; /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); base->flexioBase->TIMCTL[base->timerIndex] = 0U; base->flexioBase->TIMCFG[base->timerIndex] = 0U; /* Clear the timer flag. */ @@ -688,6 +701,10 @@ void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) uint32_t statusFlags = 0U; /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); base->flexioBase->TIMCTL[base->timerIndex] = 0U; base->flexioBase->TIMCFG[base->timerIndex] = 0U; /* Clear the timer flag. */ @@ -975,7 +992,10 @@ void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_tran { FLEXIO_MCULCD_StartTransfer(base); - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + if (!xfer->dataOnly) + { + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } if (xfer->dataSize > 0U) { @@ -1076,8 +1096,11 @@ status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, /* Assert the nCS. */ FLEXIO_MCULCD_StartTransfer(base); - /* Send the command. */ - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } /* If transfer count is 0 (only to send command), return directly. */ if (0U == xfer->dataSize) @@ -1308,4 +1331,4 @@ void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle) statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); } } -} +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h index f5f1e4ecb7..298287b48d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021, 2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_MCULCD_H_ -#define _FSL_FLEXIO_MCULCD_H_ +#ifndef FSL_FLEXIO_MCULCD_H_ +#define FSL_FLEXIO_MCULCD_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -22,10 +22,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexIO MCULCD driver version. */ -#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) -/*@}*/ +#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @} */ #ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME /*! @@ -129,7 +129,7 @@ typedef struct _flexio_mculcd_config bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + uint32_t baudRate_Bps; /*!< Baud rate in bit-per-second for all data lines combined. */ } flexio_mculcd_config_t; /*! @brief Transfer mode.*/ @@ -144,11 +144,12 @@ typedef enum _flexio_mculcd_transfer_mode typedef struct _flexio_mculcd_transfer { uint32_t command; /*!< Command to send. */ - flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, this is the value to send. When writing or reading array, this is the address of the data array. */ size_t dataSize; /*!< How many bytes to transfer. */ + flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ + bool dataOnly; /*!< Send data only when tx without the command. */ } flexio_mculcd_transfer_t; /*! @brief typedef for flexio_mculcd_handle_t in advance. */ @@ -229,7 +230,7 @@ void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base); */ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config); -/*@}*/ +/*! @} */ /*! * @name Status @@ -257,7 +258,7 @@ uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base); */ void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask); -/*@}*/ +/*! @} */ /*! * @name Interrupts @@ -286,7 +287,7 @@ void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); */ void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); -/*@}*/ +/*! @} */ /*! * @name DMA Control @@ -343,7 +344,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]); } -/*@}*/ +/*! @} */ /*! * @name Bus Operations @@ -354,7 +355,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type * @brief Set desired baud rate. * * @param base Pointer to the FLEXIO_MCULCD_Type structure. - * @param baudRate_Bps Desired baud rate. + * @param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined. * @param srcClock_Hz FLEXIO clock frequency in Hz. * @retval kStatus_Success Set successfully. * @retval kStatus_InvalidArgument Could not set the baud rate. @@ -602,7 +603,7 @@ void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sam * @param xfer pointer to flexio_mculcd_transfer_t structure. */ void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer); -/*@}*/ +/*! @} */ /*! * @name Transactional @@ -675,11 +676,11 @@ status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_ */ void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } #endif /*_cplusplus*/ -/*@}*/ +/*! @} */ -#endif /*_FSL_FLEXIO_MCULCD_H_*/ +#endif /*FSL_FLEXIO_MCULCD_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c index 8b1462594a..0c52c4e8c0 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2019,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -460,8 +460,12 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, /* Setup DMA to transfer data. */ /* Assert the nCS. */ FLEXIO_MCULCD_StartTransfer(base); - /* Send the command. */ - FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } /* Setup the DMA configuration. */ FLEXIO_MCULCD_EDMAConfig(base, handle); @@ -494,102 +498,6 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, return kStatus_Success; } -/*! - * brief Performs a non-blocking FlexIO MCULCD data write using eDMA. - * - * This function returns immediately after transfer initiates. To check whether - * the transfer is completed, user could: - * 1. Use the transfer completed callback; - * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA - * - * param base pointer to FLEXIO_MCULCD_Type structure. - * param handle pointer to flexio_mculcd_edma_handle_t structure to store the - * transfer state. - * param data Pointer to data. - * param size Size(in bytes) of the data - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another - * transfer. - */ -status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base, - flexio_mculcd_edma_handle_t *handle, - const void *data, size_t size) -{ - assert(NULL != handle); - assert(NULL != data); - - /* - * The data transfer mechanism: - * - * Read: - * Assume the data length is Lr = (n1 * minorLoopBytes + n2), where - * n2 < minorLoopBytes. - * If (n1 <= 1), then all data are sent using blocking method. - * If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read - * using DMA, the left (minorLoopBytes + n2) are read using blocking method. - * - * Write: - * Assume the data length is Lw = (n1 * minorLoopBytes + n2), where - * n2 < minorLoopBytes. - * If (n1 = 0), then all data are sent using blocking method. - * If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent - * using DMA, the left n2 are sent using blocking method. - */ - - /* Check if the device is busy. */ - if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) - { - return kStatus_FLEXIO_MCULCD_Busy; - } - - /* Set the state in handle. */ - handle->minorLoopBytes = handle->txShifterNum * 4UL; - handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; - - /* - * For TX, if data is less than one minor loop, then use polling method. - * For RX, if data is less than two minor loop, then use polling method. - */ - if (size < handle->minorLoopBytes) - { - FLEXIO_MCULCD_WriteDataArrayBlocking(base, data, size); - - handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; - - /* Callback to inform upper layer. */ - if (NULL != handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); - } - } - else - { - handle->dataCount = size; - handle->remainingCount = size; - handle->dataAddrOrSameValue = (uint32_t)data; - - /* Setup DMA to transfer data. */ - /* Assert the nCS. */ - FLEXIO_MCULCD_StartTransfer(base); - - /* Setup the DMA configuration. */ - FLEXIO_MCULCD_EDMAConfig(base, handle); - - /* Start the transfer. */ - /* For 6800, de-assert the RDWR pin. */ - if (kFLEXIO_MCULCD_6800 == base->busType) - { - base->setRDWRPin(false); - } - FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base); - FLEXIO_MCULCD_EnableTxDMA(base, true); - EDMA_StartTransfer(handle->txDmaHandle); - } - - return kStatus_Success; -} - /*! * brief Aborts a FlexIO MCULCD transfer using eDMA. * diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h index 2771134efe..98da16eef9 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020,2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_ -#define _FSL_FLEXIO_MCULCD_EDMA_H_ +#ifndef FSL_FLEXIO_MCULCD_EDMA_H_ +#define FSL_FLEXIO_MCULCD_EDMA_H_ #include "fsl_edma.h" #include "fsl_flexio_mculcd.h" @@ -21,10 +21,10 @@ * Definitions ******************************************************************************/ -/*@{*/ +/*! @{ */ /*! @brief FlexIO MCULCD EDMA driver version. */ -#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) -/*@}*/ +#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*! @} */ /*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */ typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t; @@ -119,27 +119,6 @@ status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle, flexio_mculcd_transfer_t *xfer); -/*! - * brief Performs a non-blocking FlexIO MCULCD data write using eDMA. - * - * This function returns immediately after transfer initiates. To check whether - * the transfer is completed, user could: - * 1. Use the transfer completed callback; - * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA - * - * param base pointer to FLEXIO_MCULCD_Type structure. - * param handle pointer to flexio_mculcd_edma_handle_t structure to store the - * transfer state. - * param data Pointer to data. - * param size Size(in bytes) of the data - * retval kStatus_Success Successfully start a transfer. - * retval kStatus_InvalidArgument Input argument is invalid. - * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another - * transfer. - */ -status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base, - flexio_mculcd_edma_handle_t *handle, - const void *data, size_t size); /*! * @brief Aborts a FlexIO MCULCD transfer using eDMA. @@ -171,4 +150,4 @@ status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, /*! * @} */ -#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */ +#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.c new file mode 100644 index 0000000000..3ca5315052 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.c @@ -0,0 +1,407 @@ +/* + * Copyright 2019-2021,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd_smartdma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_smartdma" +#endif + +#define FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER 0U +#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 7U +#define FLEXIO_MCULCD_SMARTDMA_TX_SHIFTER_NUM \ + (FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER - FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER + 1) + +enum _MCULCD_transfer_state +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. + */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the TX chunk size. + * + * The SMARTDMA TX transfer memory must be 4Byte aligned, the transfer size must + * be multiple of 64Byte. So the transfer data is devided in to three part: + * part1 + part2 + part3. + * The part2 is transfered using SMARTDMA, it should be 4Byte aligned, multiple + * of 64Byte. + * The part1 and part3 are transfered using blocking method, each of them is + * less than 64Byte, and total of them is less than (64 + 4) bytes. + * + * This function gets the size of each part. + * + * @param totalLen The total TX size in byte. + * @param startAddr The start address of the TX data. + * @param part1Len Length of the part 1 in byte. + * @param part2Len Length of the part 2 in byte. + * @param part3Len Length of the part 3 in byte. + */ +static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen( + uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len); + +/*! + * @brief Convert RGB565 to RGB888. + * + * @param rgb565 Input RGB565. + * @param pixelCount Pixel count. + * @param rgb888 Output RGB888. + */ +static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888); + +/*! + * @brief Callback function registered to SMARTDMA driver. + */ +static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen( + uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len) +{ + if (totalLen < FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN) + { + *part1Len = totalLen; + *part2Len = 0; + *part3Len = 0; + } + else + { + *part3Len = (startAddr + totalLen) & (FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN - 1U); + *part2Len = ((uint32_t)(totalLen - *part3Len)) & (~(FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN - 1U)); + + if (FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN > *part2Len) + { + *part1Len = totalLen; + *part2Len = 0; + *part3Len = 0; + } + else + { + *part1Len = totalLen - *part2Len - *part3Len; + } + } +} + +static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888) +{ + while ((pixelCount--) != 0U) + { + *rgb888 = (uint8_t)(((*rgb565) & 0x001FU) << 3U); + rgb888++; + *rgb888 = (uint8_t)(((*rgb565) & 0x07E0U) >> 3U); + rgb888++; + *rgb888 = (uint8_t)(((*rgb565) & 0xF800U) >> 8U); + rgb888++; + + rgb565++; + } +} + +/*! + * brief Initializes the FLEXO MCULCD master SMARTDMA handle. + * + * This function initializes the FLEXO MCULCD master SMARTDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_MCULCD_Type structure. + * param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * param config Pointer to the configuration. + * param callback MCULCD transfer complete callback, NULL means no callback. + * param userData callback function parameter. + * retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + const flexio_mculcd_smartdma_config_t *config, + flexio_mculcd_smartdma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* The SMARTDMA firmware only support TX using shifter 0 to shifter 7 */ + if (base->txShifterStartIndex != FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER) + { + return kStatus_InvalidArgument; + } + + if (base->txShifterEndIndex != FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER) + { + return kStatus_InvalidArgument; + } + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + if (NULL == config) + { + handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA; + } + else + { + if (config->inputPixelFormat == config->outputPixelFormat) + { + handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA; + } + else if (((config->inputPixelFormat == kFLEXIO_MCULCD_RGB565) && + (config->outputPixelFormat == kFLEXIO_MCULCD_RGB888)) || + ((config->inputPixelFormat == kFLEXIO_MCULCD_BGR565) && + (config->outputPixelFormat == kFLEXIO_MCULCD_BGR888))) + { + handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA_RGB565To888; + handle->needColorConvert = true; + } + else + { + return kStatus_InvalidArgument; + } + } + + /* Initialize the state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + handle->base = base; + + SMARTDMA_InstallFirmware(SMARTDMA_DISPLAY_MEM_ADDR, s_smartdmaDisplayFirmware, SMARTDMA_DISPLAY_FIRMWARE_SIZE); + + SMARTDMA_InstallCallback(FLEXIO_MCULCD_SMARTDMA_Callback, handle); + + /* The shifter interrupt is used by the SMARTDMA. */ + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, (1UL << FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER)); + +#if (defined(SMARTDMA_USE_FLEXIO_SHIFTER_DMA) && SMARTDMA_USE_FLEXIO_SHIFTER_DMA) + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL, true); +#endif + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA. + * + * This function returns immediately after transfer initiates. Use the callback + * function to check whether the transfer is completed. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * param xfer Pointer to FlexIO MCULCD transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t part1Len, part2Len, part3Len; + + /* Check if the device is busy. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Only support write array. */ + if (kFLEXIO_MCULCD_WriteArray != xfer->mode) + { + return kStatus_InvalidArgument; + } + + FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(xfer->dataSize, xfer->dataAddrOrSameValue, &part1Len, &part2Len, &part3Len); + + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; + + /* Start transfer. */ + handle->remainingCount = xfer->dataSize; + handle->dataCount = xfer->dataSize; + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + if (part1Len > 0U) + { + if (handle->needColorConvert) + { + FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part1Len >> 1U, + handle->blockingXferBuffer); + FLEXIO_MCULCD_WriteDataArrayBlocking(base, handle->blockingXferBuffer, (part1Len >> 1U) * 3U); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(base, (void *)(uint8_t *)xfer->dataAddrOrSameValue, (size_t)part1Len); + } + handle->remainingCount -= part1Len; + handle->dataAddrOrSameValue += part1Len; + } + + if (0U == part2Len) + { + /* In this case, all data are sent out as part 1. Only notify upper layer here. */ + FLEXIO_MCULCD_StopTransfer(base); + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base); + + /* Save the part 3 information. */ + handle->dataCountUsingEzh = part2Len; + handle->dataAddrOrSameValue += part2Len; + + /* The part 3 is transfered using blocking method in ISR, convert the color + to save time in ISR. */ + if ((0U != part3Len) && (handle->needColorConvert)) + { + FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part3Len >> 1U, + handle->blockingXferBuffer); + } + + handle->smartdmaParam.p_buffer = (uint32_t *)(xfer->dataAddrOrSameValue + part1Len); + handle->smartdmaParam.buffersize = part2Len; + handle->smartdmaParam.smartdma_stack = handle->smartdmaStack; + + SMARTDMA_Reset(); + SMARTDMA_Boot(handle->smartdmaApi, &(handle->smartdmaParam), 0); + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO MCULCD transfer using SMARTDMA. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD SMARTDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle) +{ + assert(handle != NULL); + + SMARTDMA_Reset(); + + /* Set the handle state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + handle->dataCount = 0; +} + +/*! + * brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD SMARTDMA handle pointer. + * param count Number of count transferred so far by the SMARTDMA transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + uint32_t state = handle->state; + + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == state) + { + return kStatus_NoTransferInProgress; + } + else + { + *count = handle->dataCount - handle->remainingCount; + } + + return kStatus_Success; +} + +static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param) +{ + flexio_mculcd_smartdma_handle_t *flexioMculcdSmartDmaHandle = (flexio_mculcd_smartdma_handle_t *)param; + + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioMculcdSmartDmaHandle->base; + + FLEXIO_MCULCD_WaitTransmitComplete(); + + /* Disable the TX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase); + + flexioMculcdSmartDmaHandle->remainingCount -= flexioMculcdSmartDmaHandle->dataCountUsingEzh; + + /* Send the part 3 */ + if (0U != flexioMculcdSmartDmaHandle->remainingCount) + { + if (flexioMculcdSmartDmaHandle->needColorConvert) + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, flexioMculcdSmartDmaHandle->blockingXferBuffer, + (flexioMculcdSmartDmaHandle->remainingCount >> 1U) * 3U); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, + (void *)(uint8_t *)flexioMculcdSmartDmaHandle->dataAddrOrSameValue, + flexioMculcdSmartDmaHandle->remainingCount); + } + } + + flexioMculcdSmartDmaHandle->remainingCount = 0; + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + flexioMculcdSmartDmaHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (NULL != flexioMculcdSmartDmaHandle->completionCallback) + { + flexioMculcdSmartDmaHandle->completionCallback(flexioLcdMcuBase, flexioMculcdSmartDmaHandle, + kStatus_FLEXIO_MCULCD_Idle, + flexioMculcdSmartDmaHandle->userData); + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.h new file mode 100644 index 0000000000..3500aaaed0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.h @@ -0,0 +1,158 @@ +/* + * Copyright 2019,2021,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_MCULCD_SMARTDMA_H_ +#define FSL_FLEXIO_MCULCD_SMARTDMA_H_ + +#include "fsl_smartdma.h" +#include "fsl_flexio_mculcd.h" + +/*! + * @addtogroup flexio_smartdma_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*@{*/ +/*! @brief FlexIO MCULCD SMARTDMA driver version. */ +#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief SMARTDMA transfer size should be multiple of 64 bytes. */ +#define FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN 64U + +/*! @brief SMARTDMA transfer memory address should be 4 byte aligned. */ +#define FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN 4U + +/*! @brief typedef for flexio_mculcd_smartdma_handle_t in advance. */ +typedef struct _flexio_mculcd_smartdma_handle flexio_mculcd_smartdma_handle_t; + +/*! @brief FlexIO MCULCD master callback for transfer complete. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_smartdma_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO MCULCD SMARTDMA transfer handle, users should not touch the + * content of the handle.*/ +struct _flexio_mculcd_smartdma_handle +{ + FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */ + size_t dataCount; /*!< Total count to be transferred. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataCountUsingEzh; /*!< Data transfered using SMARTDMA. */ + volatile size_t remainingCount; /*!< Remaining count to transfer. */ + volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */ + uint8_t smartdmaApi; /*!< The SMARTDMA API used during transfer. */ + bool needColorConvert; /*!< Need color convert or not. */ + uint8_t blockingXferBuffer[FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN * 3 / + 2]; /*!< Used for blocking method color space convet. */ + flexio_mculcd_smartdma_transfer_callback_t completionCallback; /*!< Callback for MCULCD SMARTDMA transfer */ + void *userData; /*!< User Data for MCULCD SMARTDMA callback */ + smartdma_flexio_mculcd_param_t smartdmaParam; /*!< SMARTDMA function parameters. */ + uint32_t smartdmaStack[1]; /*!< SMARTDMA function stack. */ +}; + +/*! @brief FlexIO MCULCD SMARTDMA configuration. */ +typedef struct _flexio_mculcd_smartdma_config +{ + flexio_mculcd_pixel_format_t inputPixelFormat; /*!< The pixel format in the frame buffer. */ + flexio_mculcd_pixel_format_t outputPixelFormat; /*!< The pixel format on the 8080/68k bus. */ +} flexio_mculcd_smartdma_config_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SMARTDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXO MCULCD master SMARTDMA handle. + * + * This function initializes the FLEXO MCULCD master SMARTDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_MCULCD_Type structure. + * @param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * @param config Pointer to the configuration. + * @param callback MCULCD transfer complete callback, NULL means no callback. + * @param userData callback function parameter. + * @retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + const flexio_mculcd_smartdma_config_t *config, + flexio_mculcd_smartdma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA. + * + * This function returns immediately after transfer initiates. Use the callback + * function to check whether the transfer is completed. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * @param xfer Pointer to FlexIO MCULCD transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO MCULCD transfer using SMARTDMA. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD SMARTDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD SMARTDMA handle pointer. + * @param count Number of count transferred so far by the SMARTDMA transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_FLEXIO_MCULCD_SMARTDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.c index 06542d9120..96c9a7c0ac 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.c @@ -1229,7 +1229,12 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, /* Enable transmit and receive interrupt to handle rx. */ FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); - + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + } + return kStatus_Success; } @@ -1307,8 +1312,15 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) base = (FLEXIO_SPI_Type *)spiType; status = FLEXIO_SPI_GetStatusFlags(base); + /* Receive interrupt. */ + if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + return; + } + /* Handle rx. */ - if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U)) + if (handle->rxRemainingBytes != 0U) { FLEXIO_SPI_TransferReceiveTransaction(base, handle); } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.h index 61c1034fc2..cae17a802c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_SPI_H_ -#define _FSL_FLEXIO_SPI_H_ +#ifndef FSL_FLEXIO_SPI_H_ +#define FSL_FLEXIO_SPI_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -22,14 +22,14 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexIO SPI driver version. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) +/*! @} */ #ifndef FLEXIO_SPI_DUMMYDATA /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ -#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU) +#define FLEXIO_SPI_DUMMYDATA (0x00U) #endif /*! @brief Retry times for waiting flag. */ @@ -152,7 +152,7 @@ typedef struct _flexio_spi_slave_config /*! @brief Define FlexIO SPI transfer structure. */ typedef struct _flexio_spi_transfer { - uint8_t *txData; /*!< Send buffer. */ + const uint8_t *txData; /*!< Send buffer. */ uint8_t *rxData; /*!< Receive buffer. */ size_t dataSize; /*!< Transfer bytes. */ uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ @@ -179,7 +179,7 @@ typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, /*! @brief Define FlexIO SPI handle structure. */ struct _flexio_spi_master_handle { - uint8_t *txData; /*!< Transfer buffer. */ + const uint8_t *txData; /*!< Transfer buffer. */ uint8_t *rxData; /*!< Receive buffer. */ size_t transferSize; /*!< Total bytes to be transferred. */ volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ @@ -323,7 +323,7 @@ void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); */ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); -/*@}*/ +/*! @} */ /*! * @name Status @@ -353,7 +353,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); -/*@}*/ +/*! @} */ /*! * @name Interrupts @@ -384,7 +384,7 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); */ void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); -/*@}*/ +/*! @} */ /*! * @name DMA Control @@ -447,7 +447,7 @@ static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base } } -/*@}*/ +/*! @} */ /*! * @name Bus Operations @@ -548,7 +548,6 @@ status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, * @param direction Shift direction of MSB first or LSB first. * @param buffer The buffer to store the received bytes. * @param size The number of data bytes to be received. - * @param direction Shift direction of MSB first or LSB first. * @retval kStatus_Success Successfully create the handle. * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. */ @@ -575,7 +574,7 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra * @param base Pointer to the FLEXIO_SPI_Type structure. */ void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base); -/*@}*/ +/*! @} */ /*Transactional APIs*/ @@ -709,11 +708,11 @@ static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, */ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } #endif /*_cplusplus*/ -/*@}*/ +/*! @} */ -#endif /*_FSL_FLEXIO_SPI_H_*/ +#endif /*FSL_FLEXIO_SPI_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi_edma.h index c71a1b1fda..7e98f19910 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_SPI_EDMA_H_ -#define _FSL_FLEXIO_SPI_EDMA_H_ +#ifndef FSL_FLEXIO_SPI_EDMA_H_ +#define FSL_FLEXIO_SPI_EDMA_H_ #include "fsl_flexio_spi.h" #include "fsl_edma.h" @@ -21,10 +21,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexIO SPI EDMA driver version. */ #define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) -/*@}*/ +/*! @} */ /*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.c index 0d308b16a7..13890caee7 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.c @@ -1007,3 +1007,17 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) } } } + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.h index 783c31885e..d6f36bf323 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_UART_H_ -#define _FSL_FLEXIO_UART_H_ +#ifndef FSL_FLEXIO_UART_H_ +#define FSL_FLEXIO_UART_H_ #include "fsl_common.h" #include "fsl_flexio.h" @@ -22,10 +22,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexIO UART driver version. */ -#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) -/*@}*/ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef UART_RETRY_TIMES @@ -208,7 +208,7 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); */ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); -/* @} */ +/*! @} */ /*! * @name Status @@ -237,7 +237,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -264,7 +264,7 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); */ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); -/* @} */ +/*! @} */ /*! * @name DMA Control @@ -323,7 +323,7 @@ static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable); } -/* @} */ +/*! @} */ /*! * @name Bus Operations @@ -399,7 +399,7 @@ status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData */ status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); -/* @} */ +/*! @} */ /*! * @name Transactional @@ -571,11 +571,18 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart */ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); -/*@}*/ +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base); + +/*! @} */ #if defined(__cplusplus) } #endif /*_cplusplus*/ -/*@}*/ +/*! @} */ -#endif /*_FSL_FLEXIO_UART_H_*/ +#endif /*FSL_FLEXIO_UART_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h index 3f145ea6a4..c8d0a04369 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXIO_UART_EDMA_H_ -#define _FSL_FLEXIO_UART_EDMA_H_ +#ifndef FSL_FLEXIO_UART_EDMA_H_ +#define FSL_FLEXIO_UART_EDMA_H_ #include "fsl_flexio_uart.h" #include "fsl_edma.h" @@ -21,10 +21,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexIO UART EDMA driver version. */ #define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) -/*@}*/ +/*! @} */ /* Forward declaration of the handle typedef. */ typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; @@ -167,7 +167,7 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -175,4 +175,4 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, /*! @}*/ -#endif /* _FSL_UART_EDMA_H_ */ +#endif /* FSL_UART_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.c index 466a68e97b..a4266b8c53 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2022, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -118,7 +118,7 @@ static flexspi_isr_t s_flexspiIsr; static void FLEXSPI_Memset(void *src, uint8_t value, size_t length) { assert(src != NULL); - uint8_t *p = src; + uint8_t *p = (uint8_t *)src; for (uint32_t i = 0U; i < length; i++) { @@ -192,6 +192,9 @@ static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t /* DLLEN = 1, SLVDLYTARGET = 0xF, */ flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F); #endif +#if (defined(FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP) && FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP) + flexspiDllValue |= FLEXSPI_DLLCR_REFPHASEGAP(2U); +#endif /* FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP */ } else { @@ -235,10 +238,6 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) /* Clear the flags. */ FLEXSPI_ClearInterruptStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; } return result; @@ -712,7 +711,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size) } /* Push a watermark level data into IP TX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; + base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; } return result; @@ -819,7 +818,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size) } /* Pop out a watermark level datas from IP RX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; } return result; @@ -843,8 +842,8 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; /* Clear former pending status before start this transfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; + base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK; /* Configure base address. */ base->IPCR0 = xfer->deviceAddress; @@ -880,12 +879,13 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) /* Empty else. */ } - /* Wait for bus to be idle before changing flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) + /* Wait until the IP command execution finishes */ + while (0UL == (base->INTR & FLEXSPI_INTR_IPCMDDONE_MASK)) { } - if (xfer->cmdType == kFLEXSPI_Command) + /* Unless there is an error status already set, capture the latest one */ + if (result == kStatus_Success) { result = FLEXSPI_CheckAndClearError(base, base->INTR); } @@ -966,8 +966,8 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; /* Clear former pending status before start this transfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; + base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK; /* Configure base address. */ base->IPCR0 = xfer->deviceAddress; @@ -1067,7 +1067,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) uint32_t intEnableStatus; uint32_t txWatermark; uint32_t rxWatermark; - uint8_t i = 0; + uint32_t i = 0; status = base->INTR; intEnableStatus = base->INTEN; @@ -1130,12 +1130,12 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) handle->dataSize = 0; } /* Pop out a watermark level data from IP RX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; } if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag)) { - base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; + base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; FLEXSPI_TransferAbort(base, handle); @@ -1192,7 +1192,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) } /* Push a watermark level data into IP TX FIFO. */ - base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; + base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; } } else @@ -1233,6 +1233,14 @@ void FLEXSPI1_DriverIRQHandler(void) SDK_ISR_EXIT_BARRIER; } #endif +#if defined(FLEXSPI2) +void FLEXSPI2_DriverIRQHandler(void); +void FLEXSPI2_DriverIRQHandler(void) +{ + s_flexspiIsr(FLEXSPI2, s_flexspiHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif #if defined(LSIO__FLEXSPI0) void LSIO_OCTASPI0_INT_DriverIRQHandler(void); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.h index f4d869645c..5d65cd41ae 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __FSL_FLEXSPI_H_ -#define __FSL_FLEXSPI_H_ +#ifndef FSL_FLEXSPI_H_ +#define FSL_FLEXSPI_H_ #include #include "fsl_device_registers.h" @@ -23,10 +23,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FLEXSPI driver version. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) -/*@}*/ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) @@ -242,8 +242,10 @@ typedef struct _flexspi_config #if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF bool rxSampleClockDiff; /*!< Sample Clock source or source_b selection for Flash Reading. */ #endif - bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock - output, when enable, Port B flash access is not available. */ +#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) + bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock + output, when enable, Port B flash access is not available. */ +#endif bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices when enabled, same configuration in FLASHA1CRx is applied to all. */ uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, @@ -452,7 +454,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) } } -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -480,10 +482,10 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) base->INTEN &= ~mask; } -/* @} */ +/*! @} */ /*! @name DMA control */ -/*@{*/ +/*! @{ */ /*! * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. @@ -543,10 +545,10 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) return (uint32_t)&base->RFDR[0]; } -/*@}*/ +/*! @} */ /*! @name FIFO control */ -/*@{*/ +/*! @{ */ /*! @brief Clears the FLEXSPI IP FIFO logic. * @@ -587,7 +589,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si } } -/*@}*/ +/*! @} */ /*! * @name Status @@ -612,7 +614,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) */ static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) { - base->INTR |= mask; + base->INTR = mask; } #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) @@ -685,7 +687,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) { return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)); } -/*@}*/ +/*! @} */ /*! * @name Bus Operations @@ -737,6 +739,22 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable } #endif +#if (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) +/*! + * @brief Set AHB Memory-Mapped Flash base address. + * + * @note The length of base address may be different for differnt instance, please refer to the reference manual. + * @note This function should be called when FLEXSPI is in stop mode. + * + * @param base FLEXSPI peripheral base address. + * @param address AHB Memory-Mapped Flash base address. + */ +static inline void FLEXSPI_SetAHBFlashBaseAddress(FLEXSPI_Type *base, uint8_t address) +{ + base->AHBCR = (base->AHBCR & (~FLEXSPI_AHBCR_AFLASHBASE_MASK)) | FLEXSPI_AHBCR_AFLASHBASE(address); +} +#endif /* (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) */ + /*! @brief Updates the LUT table. * * @param base FLEXSPI peripheral base address. @@ -879,6 +897,6 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); #if defined(__cplusplus) } #endif /*_cplusplus. */ -/*@}*/ +/*! @} */ -#endif /* __FSL_FLEXSPI_H_ */ +#endif /* FSL_FLEXSPI_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.c index 4cc752b955..ece9ed4728 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -288,7 +288,7 @@ status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, /* Submit transfer. */ (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); - EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, (edma_modulo_t)power, + EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, (edma_modulo_t)power, kEDMA_ModuloDisable); EDMA_SetCallback(handle->rxDmaHandle, FLEXSPI_TransferEDMACallback, &s_edmaPrivateHandle[instance]); EDMA_StartTransfer(handle->rxDmaHandle); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h index c0491c2073..3782d9aed1 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h @@ -1,12 +1,12 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FLEXSPI_EDMA_H_ -#define _FSL_FLEXSPI_EDMA_H_ +#ifndef FSL_FLEXSPI_EDMA_H_ +#define FSL_FLEXSPI_EDMA_H_ #include "fsl_flexspi.h" #include "fsl_edma.h" @@ -21,10 +21,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FLEXSPI EDMA driver. */ -#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @} */ typedef struct _flexspi_edma_handle flexspi_edma_handle_t; @@ -135,12 +135,12 @@ void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle */ status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count); -/* @} */ +/*! @} */ #if defined(__cplusplus) } #endif -/* @} */ +/*! @} */ -#endif /* _FSL_FLEXSPI_EDMA_H_ */ +#endif /* FSL_FLEXSPI_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c index f6536d2559..459bbb6f3a 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c @@ -15,6 +15,10 @@ #define FSL_COMPONENT_ID "platform.drivers.lpc_freqme" #endif +#if defined(FREQME_RSTS_N) +#define FREQME_RESETS_ARRAY FREQME_RSTS_N +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -31,6 +35,10 @@ static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS; static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FREQME_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY; +#endif /******************************************************************************* * Code ******************************************************************************/ @@ -69,12 +77,16 @@ void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config) CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FREQME_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]); +#endif + if (config->startMeasurement) { tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; } - tmp32 |= - FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | FREQME_CTRL_W_PULSE_MODE(config->operateMode); + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | + FREQME_CTRL_W_PULSE_MODE(config->operateMode); if (config->operateMode == kFREQME_FreqMeasurementMode) { tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.h index f6e5a1b230..dd1ee29d66 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_FREQME_ -#define _FSL_FREQME_ +#ifndef FSL_FREQME_H_ +#define FSL_FREQME_H_ #include "fsl_common.h" @@ -19,10 +19,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief FREQME driver version 2.0.0. */ -#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ +/*! @{ */ +/*! @brief FREQME driver version 2.1.2. */ +#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @} */ /*! * @brief The enumeration of interrupt status flags. @@ -51,10 +51,10 @@ enum _freqme_interrupt_status_flags */ enum _freqme_interrupt_enable { - kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is - less than minimum value. */ - kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is - greater than maximum value. */ + kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is + less than minimum value. */ + kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is + greater than maximum value. */ kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a measurement completes and the result is ready. */ @@ -223,8 +223,8 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_ uint32_t tmp32; tmp32 = base->CTRLSTAT; - tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | - FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); if (operateMode == kFREOME_PulseWidthMeasurementMode) { tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK; @@ -243,6 +243,7 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_ static inline bool FREQME_CheckOperateMode(FREQME_Type *base) { return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL); + } /*! @@ -275,7 +276,7 @@ static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxVal */ /*! - * @brief Calculate the frequency of selected target clock。 + * @brief Calculate the frequency of selected target clock。 * * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. * @@ -317,8 +318,8 @@ static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polar uint32_t tmp32; tmp32 = base->CTRLSTAT; - tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | - FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); if (pulsePolarity != kFREQME_PulseHighPeriod) { @@ -437,4 +438,4 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) /*! * @} */ -#endif /* __FSL_FREQME_H__ */ +#endif /* FSL_FREQME_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c index 8be9501bc0..25a44ee918 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c @@ -141,7 +141,7 @@ status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltag uint32_t tmp0 = 0; status_t status = kStatus_Fail; - if (voltage != (kGDET_MidVoltage || kGDET_NormalVoltage || kGDET_OverDriveVoltage)) + if ((voltage != kGDET_MidVoltage) && (voltage != kGDET_NormalVoltage) && (voltage != kGDET_OverDriveVoltage)) { return kStatus_InvalidArgument; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h index 271c1cb373..ec20645431 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_GDET_H_ -#define _FSL_GDET_H_ +#ifndef FSL_GDET_H_ +#define FSL_GDET_H_ #include "fsl_common.h" @@ -21,7 +21,7 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief Defines GDET driver version 2.0.0. * * Change log: @@ -29,7 +29,7 @@ * - initial version */ #define FSL_GDET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +/*! @} */ /*! * @brief GDET Core Voltage. @@ -37,12 +37,12 @@ * These constants are used to define core voltage argument to be used with * GDET_ReconfigureVoltageMode(). */ -typedef enum _gdet_core_voltage -{ - kGDET_MidVoltage = 0U, /*!< Mid Voltage (1.0V) */ - kGDET_NormalVoltage = 1U, /*!< Normal Voltage (1.1V) */ - kGDET_OverDriveVoltage = 2U, /*!< Over Drive Voltage (1.2V) */ -} gdet_core_voltage_t; + +typedef uint32_t gdet_core_voltage_t; +#define kGDET_MidVoltage ((gdet_core_voltage_t)0x0u) /*!< Mid Voltage (1.0V) */ +#define kGDET_NormalVoltage ((gdet_core_voltage_t)0x1u) /*!< Normal Voltage (1.1V) */ +#define kGDET_OverDriveVoltage ((gdet_core_voltage_t)0x2u) /*!< Over Drive Voltage (1.2V) */ + /******************************************************************************* * API *******************************************************************************/ @@ -109,8 +109,8 @@ status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltag #if defined(__cplusplus) } -#endif /* __cplusplus */ +#endif /* __cplusplus */ /*! @}*/ /* end of group gdet */ -#endif /* _FSL_GDET_H_ */ +#endif /* FSL_GDET_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.c index 08d504e760..3e32730d1c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2019, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -8,18 +8,30 @@ #include "fsl_gpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.gpio" #endif +#if defined(GPIO_RSTS) +#define GPIO_RESETS_ARRAY GPIO_RSTS +#endif + /******************************************************************************* * Variables ******************************************************************************/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#else +#if defined(GPIO_RESETS_ARRAY) +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#endif #endif #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT @@ -35,10 +47,16 @@ static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ +#if defined(GPIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY; +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * @brief Gets the GPIO instance according to the GPIO base * @@ -50,7 +68,8 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base); /******************************************************************************* * Code ******************************************************************************/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY) static uint32_t GPIO_GetInstance(GPIO_Type *base) { uint32_t instance; @@ -99,6 +118,10 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config { assert(NULL != config); +#if defined(GPIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]); +#endif + if (config->pinDirection == kGPIO_DigitalInput) { base->PDDR &= GPIO_FIT_REG(~(1UL << pin)); @@ -119,7 +142,8 @@ void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info) } #endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * brief Reads the GPIO port interrupt status flag. * @@ -183,7 +207,8 @@ uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin) } #endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * brief Clears multiple GPIO pin interrupt status flags. * @@ -262,13 +287,15 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut /******************************************************************************* * Variables ******************************************************************************/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; #endif /******************************************************************************* * Prototypes ******************************************************************************/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * @brief Gets the FGPIO instance according to the GPIO base * @@ -280,7 +307,8 @@ static uint32_t FGPIO_GetInstance(FGPIO_Type *base); /******************************************************************************* * Code ******************************************************************************/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) static uint32_t FGPIO_GetInstance(FGPIO_Type *base) { uint32_t instance; @@ -356,7 +384,8 @@ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *conf base->PDDR |= (1UL << pin); } } -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * brief Reads the FGPIO port interrupt status flag. * diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.h index 5dd23fc6b6..a91fa403ef 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_GPIO_H_ -#define _FSL_GPIO_H_ +#ifndef FSL_GPIO_H_ +#define FSL_GPIO_H_ #include "fsl_common.h" @@ -21,10 +21,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief GPIO driver version. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 1)) -/*@}*/ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3)) +/*! @} */ #if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U) #define GPIO_FIT_REG(value) \ @@ -79,7 +79,8 @@ typedef struct _gpio_pin_config uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ } gpio_pin_config_t; -#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \ + !(defined(FSL_FEATURE_SOC_PORT_COUNT)) /*! @brief Configures the interrupt generation condition. */ typedef enum _gpio_interrupt_config { @@ -104,8 +105,8 @@ typedef enum _gpio_interrupt_config /*! @brief Configures the selection of interrupt/DMA request/trigger output. */ typedef enum _gpio_interrupt_selection { - kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */ - kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */ + kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */ + kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */ } gpio_interrupt_selection_t; #endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ @@ -146,7 +147,7 @@ extern "C" { */ /*! @name GPIO Configuration */ -/*@{*/ +/*! @{ */ /*! * @brief Initializes a GPIO pin used by the board. @@ -311,10 +312,10 @@ static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask) } #endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */ -/*@}*/ +/*! @} */ /*! @name GPIO Output Operations */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. @@ -393,10 +394,10 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) #endif } -/*@}*/ +/*! @} */ /*! @name GPIO Input Operations */ -/*@{*/ +/*! @{ */ /*! * @brief Reads the current input value of the GPIO port. @@ -412,11 +413,12 @@ static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) return (((uint32_t)(base->PDIR) >> pin) & 0x01UL); } -/*@}*/ +/*! @} */ /*! @name GPIO Interrupt */ -/*@{*/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @{ */ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * @brief Reads the GPIO port interrupt status flag. * @@ -602,7 +604,7 @@ static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); #endif -/*@}*/ +/*! @} */ /*! @} */ /*! @@ -621,7 +623,7 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT /*! @name FGPIO Configuration */ -/*@{*/ +/*! @{ */ #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL /*! @@ -662,10 +664,10 @@ void FGPIO_PortInit(FGPIO_Type *base); */ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); -/*@}*/ +/*! @} */ /*! @name FGPIO Output Operations */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. @@ -720,10 +722,10 @@ static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) { base->PTOR = mask; } -/*@}*/ +/*! @} */ /*! @name FGPIO Input Operations */ -/*@{*/ +/*! @{ */ /*! * @brief Reads the current input value of the FGPIO port. @@ -738,11 +740,12 @@ static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) { return (((base->PDIR) >> pin) & 0x01U); } -/*@}*/ +/*! @} */ /*! @name FGPIO Interrupt */ -/*@{*/ -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @{ */ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) /*! * @brief Reads the FGPIO port interrupt status flag. @@ -781,7 +784,7 @@ void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); #endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */ -/*@}*/ +/*! @} */ #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ @@ -793,4 +796,4 @@ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attrib * @} */ -#endif /* _FSL_GPIO_H_*/ +#endif /* FSL_GPIO_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.c index 8b0837f93c..dc10970b5a 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.c @@ -1,6 +1,5 @@ /* - * Copyright 2018-2022 NXP - * All rights reserved. + * Copyright 2018-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -432,7 +431,7 @@ status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status) return result; } -static status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) { status_t result = kStatus_Success; uint32_t status, errStatus; @@ -768,8 +767,10 @@ void I3C_GetDefaultConfig(i3c_config_t *config) config->baudRate_Hz.i2cBaud = 400000U; config->baudRate_Hz.i3cPushPullBaud = 12500000U; config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; - config->masterDynamicAddress = 0x0AU; /* Default master dynamic address. */ - config->slowClock_Hz = 1000000U; /* Default slow timer clock 1MHz. */ + config->masterDynamicAddress = 0x0AU; /* Default master dynamic address. */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + config->slowClock_Hz = 0; /* Not update the Soc default setting. */ +#endif config->enableSlave = true; config->vendorID = 0x11BU; #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) @@ -796,7 +797,10 @@ void I3C_GetDefaultConfig(i3c_config_t *config) */ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz) { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \ + !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) uint32_t instance = I3C_GetInstance(base); +#endif uint32_t configValue; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -819,14 +823,30 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) | I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh); +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(config->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(config->restartSclDelay); +#endif + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz); #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + assert((config->slowClock_Hz >= 1000000U) || (config->slowClock_Hz == 0U)); + uint8_t matchCount; - /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ - matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL); + /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle. Controller uses it to count 100us timeout. Target uses it as IBI request to drive SDA low. + Note: Use BAMATCH = 1 to generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */ + if (config->slowClock_Hz != 0U) + { + matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL) - 1U; + matchCount = (matchCount == 0U) ? 1U : matchCount; + } + else + { + /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */ + matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT); + } #endif configValue = base->SCONFIG; @@ -905,6 +925,8 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H */ void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig) { + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + masterConfig->enableMaster = kI3C_MasterOn; masterConfig->disableTimeout = false; masterConfig->hKeep = kI3C_MasterHighKeeperNone; @@ -929,7 +951,11 @@ void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig) */ void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz) { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \ + !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) uint32_t instance = I3C_GetInstance(base); +#endif + #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Ungate the clock. */ CLOCK_EnableClock(kI3cClocks[instance]); @@ -943,9 +969,33 @@ void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uin I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) | I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh); +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(masterConfig->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(masterConfig->restartSclDelay); +#endif + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + assert((masterConfig->slowClock_Hz >= 1000000U) || (masterConfig->slowClock_Hz == 0U)); + + uint32_t configValue; + uint8_t matchCount; + + /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */ + if (masterConfig->slowClock_Hz != 0U) + { + /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for 100us timeout. Note: Use BAMATCH = 1 to generate 1us clock cycle + if slow clock is 1MHz. The value of 0 would not give a correct match indication. */ + matchCount = (uint8_t)(masterConfig->slowClock_Hz / 1000000UL) - 1U; + matchCount = (matchCount == 0U) ? 1U : matchCount; + + configValue = base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK; + configValue |= I3C_SCONFIG_BAMATCH(matchCount); + base->SCONFIG = configValue; + } +#endif } /*! @@ -1125,6 +1175,36 @@ void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, I3C_MCONFIG_PPBAUD(ppBaud) | I3C_MCONFIG_ODBAUD(odBaud) | I3C_MCONFIG_I2CBAUD(i2cBaud); } +/*! + * brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) +{ + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, rxSize); +} + /*! * brief Sends a START signal and slave address on the I2C/I3C bus. * @@ -1150,43 +1230,7 @@ status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i return kStatus_I3C_Busy; } - return I3C_MasterRepeatedStart(base, type, address, dir); -} - -/*! - * brief Sends a repeated START signal and slave address on the I2C/I3C bus. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * I3C_MasterStart(), it also sends the specified 7-bit address. - * - * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * param base The I3C peripheral base address. - * param type The bus type to use in this transaction. - * param address 7-bit slave device address, in bits [6:0]. - * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * param rxSize if dir is #kI3C_Read, this assigns bytes to read. Otherwise set to 0. - * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - */ -status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) -{ - uint32_t mctrlVal; - - /* Clear all flags. */ - I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); - - /* Issue start command. */ - mctrlVal = base->MCTRL; - mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | - I3C_MCTRL_RDTERM_MASK); - mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | - I3C_MCTRL_ADDR(address); - - base->MCTRL = mctrlVal; - - return kStatus_Success; + return I3C_MasterStartWithRxSize(base, type, address, dir, 0); } /*! @@ -1218,6 +1262,21 @@ status_t I3C_MasterRepeatedStartWithRxSize( /* Clear all flags. */ I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_051617) && (FSL_FEATURE_I3C_HAS_ERRATA_051617) + /* ERRATA051617: When used as I2C controller generates repeated START randomly before the STOP under PVT condition. + This issue is caused by a glitch at the output of an internal clock MUX. The glitch when generates acts as a clock + pulse which causes the SDA line to fall early during SCL high period and creates the unintended Repeated START before + actual STOP. */ + if (type == kI3C_TypeI2C) + { + base->MCONFIG |= I3C_MCONFIG_SKEW(1); + } + else + { + base->MCONFIG &= ~I3C_MCONFIG_SKEW_MASK; + } +#endif + /* Issue start command. */ mctrlVal = base->MCTRL; mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | @@ -1332,9 +1391,10 @@ void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) */ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) { - status_t result = kStatus_Success; + status_t result = kStatus_Success; + bool isRxAutoTerm = ((flags & (uint32_t)kI3C_TransferRxAutoTermFlag) != 0UL); + bool completed = false; uint32_t status; - bool completed = false; uint8_t *buf; assert(NULL != rxBuff); @@ -1382,6 +1442,7 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) { I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); } else { @@ -1400,9 +1461,12 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t { *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); rxSize--; - if (rxSize == 1U) + if ((flags & (uint32_t)kI3C_TransferDisableRxTermFlag) == 0UL) { - base->MCTRL |= I3C_MCTRL_RDTERM(1U); + if ((!isRxAutoTerm) && (rxSize == 1U)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1U); + } } } } @@ -1497,6 +1561,7 @@ status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint3 if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) { I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); } else { @@ -1525,15 +1590,19 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint32_t count, i3c_master_daa_baudrate_t *daaBaudRate) { - status_t result = kStatus_Success; - uint32_t status; - uint32_t errStatus; - uint32_t masterConfig; + assert(addressList != NULL); + assert(count != 0U); + + status_t result = kStatus_Success; + uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; + uint32_t masterConfig = 0; + uint32_t devCount = 0; + uint8_t rxSize = 0; + bool mctrlDone = false; i3c_baudrate_hz_t baudRate_Hz; + uint32_t errStatus; + uint32_t status; size_t rxCount; - uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; - uint8_t rxSize = 0; - uint32_t devCount = 0; /* Return an error if the bus is already in use not by us. */ result = I3C_CheckForBusyBus(base); @@ -1566,66 +1635,81 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, do { - do + status = I3C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + break; + } + + if ((!mctrlDone) || (rxSize < 8U)) { - status = I3C_MasterGetStatusFlags(base); I3C_MasterGetFifoCounts(base, &rxCount, NULL); - /* Check for error flags. */ - errStatus = I3C_MasterGetErrorStatusFlags(base); - result = I3C_MasterCheckAndClearError(base, errStatus); - if (kStatus_Success != result) - { - if (daaBaudRate != NULL) - { - base->MCONFIG = masterConfig; - } - return result; - } - - if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U)) + if (rxCount != 0U) { rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); } - } while ((status & (uint32_t)kI3C_MasterControlDoneFlag) != (uint32_t)kI3C_MasterControlDoneFlag); - I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); - - if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && - (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) - { - rxSize = 0; - if ((devCount > (count - 1UL)) || ((devCount + 1UL) > I3C_MAX_DEVCNT)) + if ((status & (uint32_t)kI3C_MasterControlDoneFlag) != 0U) { - if (daaBaudRate != NULL) - { - base->MCONFIG = masterConfig; - } - return kStatus_I3C_SlaveCountExceed; + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + mctrlDone = true; + } + } + else if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && + (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) + { + if (((devCount + 1UL) > count) || ((devCount + 1UL) > I3C_MAX_DEVCNT)) + { + result = kStatus_I3C_SlaveCountExceed; + break; } + /* Assign the dynamic address from address list. */ devList[devCount].dynamicAddr = *addressList++; - devList[devCount].vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; - devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | - (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); - devList[devCount].bcr = rxBuffer[6]; - devList[devCount].dcr = rxBuffer[7]; base->MWDATAB = devList[devCount].dynamicAddr; + /* Emit process DAA again. */ I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + devList[devCount].vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; + devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | + (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); + devList[devCount].bcr = rxBuffer[6]; + devList[devCount].dcr = rxBuffer[7]; devCount++; usedDevCount++; + + /* Ready to handle next device. */ + mctrlDone = false; + rxSize = 0; + } + else + { + /* Intentional empty */ } } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); + /* Master stops DAA if slave device number exceeds the prepared address number. */ + if (result == kStatus_I3C_SlaveCountExceed) + { + /* Send the STOP signal */ + base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | + I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); + } + /* Set back initial baud rate after DAA is over. */ if (daaBaudRate != NULL) { base->MCONFIG = masterConfig; } - I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); /* Enable I3C IRQ sources while we configure stuff. */ @@ -1718,6 +1802,7 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans i3c_direction_t direction = transfer->direction; i3c_master_state_t masterState = I3C_MasterGetState(base); bool checkDdrState = false; + i3c_rx_term_ops_t rxTermOps; /* Return an error if the bus is already in use not by us. */ checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; @@ -1740,14 +1825,81 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans direction = (0UL != transfer->subaddressSize) ? kI3C_Write : transfer->direction; } + /* True: Set Rx termination bytes at start point, False: Set Rx termination one bytes in advance. */ + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + rxTermOps = kI3C_RxAutoTerm; + } + else + { + rxTermOps = kI3C_RxTermLastByte; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, transfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) { - result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); + if ((direction == kI3C_Read) && (rxTermOps == kI3C_RxAutoTerm)) + { + result = I3C_MasterStartWithRxSize(base, transfer->busType, transfer->slaveAddress, direction, + (uint8_t)transfer->dataSize); + } + else + { + result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); + } + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + if (true == I3C_MasterTransferNoStartFlag(base, transfer)) { return kStatus_I3C_IBIWon; } } + else + { + if ((direction == kI3C_Read) && (rxTermOps != kI3C_RxTermDisable)) + { + /* Can't set Rx termination more than one bytes in advance without START. */ + rxTermOps = kI3C_RxTermLastByte; + } + } /* Subaddress, MSB first. */ if (0U != transfer->subaddressSize) @@ -1782,15 +1934,39 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans /* Need to send repeated start if switching directions to read. */ if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read)) { - result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read); + if (rxTermOps == kI3C_RxAutoTerm) + { + result = I3C_MasterRepeatedStartWithRxSize(base, transfer->busType, transfer->slaveAddress, kI3C_Read, + (uint8_t)transfer->dataSize); + } + else + { + result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read); + } + if (kStatus_Success != result) { I3C_MasterClearFlagsAndEnableIRQ(base); return result; } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } } } + if (rxTermOps == kI3C_RxAutoTerm) + { + transfer->flags |= (uint32_t)kI3C_TransferRxAutoTermFlag; + } + else + { + transfer->flags &= ~(uint32_t)kI3C_TransferRxAutoTermFlag; + } + /* Transmit data. */ if ((transfer->direction == kI3C_Write) && (transfer->dataSize > 0UL)) { @@ -1800,10 +1976,6 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans /* Receive Data. */ else if ((transfer->direction == kI3C_Read) && (transfer->dataSize > 0UL)) { - if (transfer->dataSize == 1U) - { - base->MCTRL |= I3C_MCTRL_RDTERM(1U); - } result = I3C_MasterReceive(base, transfer->data, transfer->dataSize, transfer->flags); } else @@ -1952,14 +2124,21 @@ static void I3C_TransferStateMachineSendCommandState(I3C_Type *base, { base->MWDATABE = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); - if (0UL == handle->transfer.dataSize) + if (handle->transfer.busType != kI3C_TypeI3CDdr) { - handle->state = (uint8_t)kWaitForCompletionState; + if (0UL == handle->transfer.dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } } else { - /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ - handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + handle->state = (uint8_t)kTransferDataState; } } else @@ -1988,7 +2167,7 @@ static void I3C_TransferStateMachineWaitRepeatedStartCompleteState(I3C_Type *bas if (handle->remainingBytes < 256U) { - handle->isReadTerm = true; + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; stateParams->result = I3C_MasterRepeatedStartWithRxSize(base, handle->transfer.busType, handle->transfer.slaveAddress, kI3C_Read, (uint8_t)handle->remainingBytes); @@ -2057,11 +2236,10 @@ static void I3C_TransferStateMachineTransferDataState(I3C_Type *base, /* Move to stop when the transfer is done. */ if (--handle->remainingBytes == 0UL) { - handle->isReadTerm = false; - handle->state = (uint8_t)kWaitForCompletionState; + handle->state = (uint8_t)kWaitForCompletionState; } - if (!handle->isReadTerm && (handle->remainingBytes == 1UL)) + if ((handle->rxTermOps == kI3C_RxTermLastByte) && (handle->remainingBytes == 1UL)) { base->MCTRL |= I3C_MCTRL_RDTERM(1UL); } @@ -2218,6 +2396,32 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction; } + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + /* Handle no start option. */ if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) { @@ -2256,14 +2460,18 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t { handle->state = (uint8_t)kSendCommandState; } - else + else if (xfer->dataSize != 0U) { handle->state = (uint8_t)kTransferDataState; } + else + { + handle->state = (uint8_t)kStopState; + } if ((handle->remainingBytes < 256U) && (direction == kI3C_Read)) { - handle->isReadTerm = true; + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); } @@ -2318,6 +2526,19 @@ status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *hand /* Reset fifos. These flags clear automatically. */ base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + handle->rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + handle->rxTermOps = kI3C_RxAutoTerm; + } + else + { + handle->rxTermOps = kI3C_RxTermLastByte; + } + /* Generate commands to send. */ (void)I3C_InitTransferStateMachine(base, handle); @@ -2425,14 +2646,14 @@ void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle) * note This function does not need to be called unless you are reimplementing the * nonblocking API's interrupt handler routines to add special functionality. * param base The I3C peripheral base address. - * param handle Pointer to the I3C master driver handle. + * param intHandle Pointer to the I3C master driver handle. */ void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle) { - bool isDone; - status_t result; - i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle; + status_t result; + bool isDone; + /* Don't do anything if we don't have a valid handle. */ if (NULL == handle) { @@ -2498,7 +2719,9 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig) (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); slaveConfig->enableSlave = true; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) slaveConfig->isHotJoin = false; +#endif slaveConfig->vendorID = 0x11BU; #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) slaveConfig->enableRandomPart = false; @@ -2529,14 +2752,19 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig) * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of * defaults that you can override. * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. */ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz) { assert(NULL != slaveConfig); - assert(0UL != slowClock_Hz); + assert((slowClock_Hz >= 1000000U) || (slowClock_Hz == 0U)); uint32_t configValue; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \ + !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) uint32_t instance = I3C_GetInstance(base); +#endif + #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Ungate the clock. */ CLOCK_EnableClock(kI3cClocks[instance]); @@ -2549,8 +2777,18 @@ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) uint8_t matchCount; - /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ - matchCount = (uint8_t)(slowClock_Hz / 1000000UL); + /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for IBI request to drive SDA low. Note: Use BAMATCH = 1 to + generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */ + if (slowClock_Hz != 0U) + { + matchCount = (uint8_t)(slowClock_Hz / 1000000UL) - 1U; + matchCount = (matchCount == 0U) ? 1U : matchCount; + } + else + { + /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */ + matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT); + } #endif configValue = base->SCONFIG; @@ -2605,10 +2843,12 @@ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32 base->SMAXLIMITS |= (I3C_SMAXLIMITS_MAXRD(slaveConfig->maxReadLength) | I3C_SMAXLIMITS_MAXWR(slaveConfig->maxWriteLength)); +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) if (slaveConfig->isHotJoin) { I3C_SlaveRequestEvent(base, kI3C_SlaveEventHotJoinReq); } +#endif base->SCONFIG = configValue; } @@ -2670,6 +2910,7 @@ i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base) return returnCode; } +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) /*! * brief I3C slave request event. * @@ -2689,10 +2930,11 @@ void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event) /*! * brief I3C slave request event. + * deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData. * * param base The I3C peripheral base address. * param data IBI data - * param dataSize IBI data length + * param dataSize IBI data size. */ void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize) { @@ -2705,24 +2947,64 @@ void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t data } /*! - * brief I3C slave request event. + * brief I3C slave request IBI event with data payload(mandatory and extended). * * param base The I3C peripheral base address. - * param data IBI data pointer - * param dataSize IBI data length + * param data Pointer to IBI data to be sent in the request. + * param dataSize IBI data size. */ -void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize) +void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize) { - uint32_t ctrlValue = base->SCTRL; + assert((dataSize > 0U) && (dataSize <= 8U)); + uint32_t ctrlValue; + +#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK) + if (dataSize > 1U) + { + ctrlValue = I3C_IBIEXT1_EXT1(data[1]); + if (dataSize > 2U) + { + ctrlValue |= I3C_IBIEXT1_EXT2(data[2]); + } + if (dataSize > 3U) + { + ctrlValue |= I3C_IBIEXT1_EXT3(data[3]); + } + ctrlValue |= I3C_IBIEXT1_CNT(dataSize - 1U); + base->IBIEXT1 = ctrlValue; + } + + if (dataSize > 4U) + { + ctrlValue = I3C_IBIEXT2_EXT4(data[4]); + if (dataSize > 5U) + { + ctrlValue |= I3C_IBIEXT2_EXT5(data[5]); + } + if (dataSize > 6U) + { + ctrlValue |= I3C_IBIEXT2_EXT6(data[6]); + } + if (dataSize > 7U) + { + ctrlValue |= I3C_IBIEXT2_EXT7(data[7]); + } + base->IBIEXT2 = ctrlValue; + } +#endif + + ctrlValue = base->SCTRL; +#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK) + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK | I3C_SCTRL_EXTDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]) | I3C_SCTRL_EXTDATA(dataSize > 1U); +#else ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); - ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(*data); - - handle->ibiData = &data[1]; - handle->ibiDataSize = dataSize - 1U; - + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]); +#endif base->SCTRL = ctrlValue; } +#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */ /*! * brief Performs a polling send transfer on the I3C bus. @@ -3013,20 +3295,6 @@ static void I3C_SlaveTransferHandleBusStart(I3C_Type *base, i3c_slave_transfer_t static void I3C_SlaveTransferHandleEventSent(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) { xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; - if (handle->ibiData != NULL) - { - size_t count = 0U; - while (count < handle->ibiDataSize) - { - base->SCTRL = (base->SCTRL & ~I3C_SCTRL_IBIDATA_MASK) | I3C_SCTRL_IBIDATA(handle->ibiData[count]) | - I3C_SCTRL_EVENT(1U); - count++; - } - } - - /* Reset IBI data buffer. */ - handle->ibiData = NULL; - if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) { handle->callback(base, xfer, handle->userData); @@ -3051,7 +3319,7 @@ static void I3C_SlaveTransferHandleBusStop(I3C_Type *base, I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); stateParams->pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; - if (handle->isBusy == true) + if (handle->isBusy) { handle->transfer.event = (uint32_t)kI3C_SlaveCompletionEvent; handle->transfer.completionStatus = kStatus_Success; @@ -3102,6 +3370,7 @@ static void I3C_SlaveTransferHandleTxReady(I3C_Type *base, if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) { handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; } if (NULL != handle->callback) { @@ -3148,6 +3417,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base, if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) { handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; } if (NULL != handle->callback) { @@ -3170,7 +3440,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base, * note This function does not need to be called unless you are reimplementing the * non blocking API's interrupt handler routines to add special functionality. * param base The I3C peripheral base address. - * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * param intHandle Pointer to #i3c_slave_handle_t structure which stores the transfer state. */ void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle) { @@ -3291,3 +3561,12 @@ void I3C2_DriverIRQHandler(void) I3C_CommonIRQHandler(I3C2, 2); } #endif + +#if defined(I3C3) +/* Implementation of I3C3 handler named in startup code. */ +void I3C3_DriverIRQHandler(void); +void I3C3_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C3, 3); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.h index 70668cccdb..2a3b5dae82 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.h @@ -1,11 +1,10 @@ /* - * Copyright 2018-2022 NXP - * All rights reserved. + * Copyright 2018-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_I3C_H_ -#define _FSL_I3C_H_ +#ifndef FSL_I3C_H_ +#define FSL_I3C_H_ #include "fsl_common.h" @@ -19,10 +18,10 @@ */ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief I3C driver version */ -#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 8, 1)) -/*@}*/ +#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 12, 0)) +/*! @} */ /*! @brief Timeout times for waiting flag. */ #ifndef I3C_RETRY_TIMES @@ -255,6 +254,23 @@ typedef enum _i3c_rx_trigger_level kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */ } i3c_rx_trigger_level_t; +/*! @brief I3C master read termination operations. */ +typedef enum _i3c_rx_term_ops +{ + kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */ + kI3C_RxAutoTerm = 1U, /*!< Master auto terminate read after receiving specified bytes(<=255). */ + kI3C_RxTermLastByte = 2U, /*!< Master terminates read at any time after START, no length limitation. */ +} i3c_rx_term_ops_t; + +/*! @brief I3C start SCL delay options. */ +typedef enum _i3c_start_scl_delay +{ + kI3C_NoDelay = 0U, /*!< No delay. */ + kI3C_IncreaseSclHalfPeriod = 1U, /*!< Increases SCL clock period by 1/2. */ + kI3C_IncreaseSclOnePeriod = 2U, /*!< Increases SCL clock period by 1. */ + kI3C_IncreaseSclOneAndHalfPeriod = 3U, /*!< Increases SCL clock period by 1 1/2 */ +} i3c_start_scl_delay_t; + /*! @brief Structure with setting master IBI rules and slave registry. */ typedef struct _i3c_register_ibi_addr { @@ -295,6 +311,13 @@ typedef struct _i3c_master_config bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */ bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */ i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + uint32_t slowClock_Hz; /*!< Slow clock frequency. */ +#endif +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */ + i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */ +#endif } i3c_master_config_t; /* Forward declaration of the transfer descriptor and handle typedefs. */ @@ -327,6 +350,10 @@ enum _i3c_master_transfer_flags kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */ + kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */ + kI3C_TransferRxAutoTermFlag = + 0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */ + kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */ }; /*! @@ -356,7 +383,7 @@ struct _i3c_master_handle { uint8_t state; /*!< Transfer state machine current state. */ uint32_t remainingBytes; /*!< Remaining byte count in current state. */ - bool isReadTerm; /*!< Is readterm configured. */ + i3c_rx_term_ops_t rxTermOps; /*!< Read termination operation. */ i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ uint8_t ibiAddress; /*!< Slave address which request IBI. */ uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ @@ -487,7 +514,9 @@ typedef enum _i3c_slave_activity_state typedef struct _i3c_slave_config { bool enableSlave; /*!< Whether to enable slave. */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) bool isHotJoin; /*!< Whether to enable slave hotjoin before enable slave. */ +#endif uint8_t staticAddr; /*!< Static address. */ uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */ #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) @@ -578,8 +607,6 @@ struct _i3c_slave_handle uint32_t transferredCount; /*!< Count of bytes transferred. */ i3c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ void *userData; /*!< Callback parameter passed to callback. */ - uint8_t *ibiData; /*!< IBI data buffer */ - size_t ibiDataSize; /*!< IBI data size */ uint8_t txFifoSize; /*!< Tx Fifo size */ }; @@ -609,8 +636,14 @@ typedef struct _i3c_config bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */ bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */ i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */ +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */ + i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */ +#endif uint8_t masterDynamicAddress; /*!< Main master dynamic address configuration. */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) uint32_t slowClock_Hz; /*!< Slow clock frequency for time control. */ +#endif uint32_t maxWriteLength; /*!< Maximum write length. */ uint32_t maxReadLength; /*!< Maximum read length. */ bool enableSlave; /*!< Whether to enable slave. */ @@ -725,7 +758,7 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H */ /*! @name Initialization and deinitialization */ -/*@{*/ +/*! @{ */ /*! * @brief Provides a default configuration for the I3C master peripheral. @@ -775,6 +808,9 @@ void I3C_MasterDeinit(I3C_Type *base); /* Not static so it can be used from fsl_i3c_dma.c. */ status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status); +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle); + /* Not static so it can be used from fsl_i3c_dma.c. */ status_t I3C_CheckForBusyBus(I3C_Type *base); @@ -789,10 +825,10 @@ static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable) base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable); } -/*@}*/ +/*! @} */ /*! @name Status */ -/*@{*/ +/*! @{ */ /*! * @brief Gets the I3C master status flags. @@ -876,10 +912,10 @@ static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t stat */ i3c_master_state_t I3C_MasterGetState(I3C_Type *base); -/*@}*/ +/*! @} */ /*! @name Interrupts */ -/*@{*/ +/*! @{ */ /*! * @brief Enables the I3C master interrupt requests. @@ -935,10 +971,10 @@ static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base) return base->MINTMASKED; } -/*@}*/ +/*! @} */ /*! @name DMA control */ -/*@{*/ +/*! @{ */ /*! * @brief Enables or disables I3C master DMA requests. @@ -981,10 +1017,10 @@ static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB); } -/*@}*/ +/*! @} */ /*! @name FIFO control */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the watermarks for I3C master FIFOs. @@ -1025,10 +1061,10 @@ static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size } } -/*@}*/ +/*! @} */ /*! @name Bus operations */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the I3C bus frequency for master transactions. @@ -1056,6 +1092,27 @@ static inline bool I3C_MasterGetBusIdleState(I3C_Type *base) return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false); } +/*! + * @brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); + /*! * @brief Sends a START signal and slave address on the I2C/I3C bus. * @@ -1074,24 +1131,6 @@ static inline bool I3C_MasterGetBusIdleState(I3C_Type *base) */ status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); -/*! - * @brief Sends a repeated START signal and slave address on the I2C/I3C bus. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * I3C_MasterStart(), it also sends the specified 7-bit address. - * - * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * @param base The I3C peripheral base address. - * @param type The bus type to use in this transaction. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - */ -status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); - /*! * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified * in the call. @@ -1116,6 +1155,30 @@ status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t ad status_t I3C_MasterRepeatedStartWithRxSize( I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, + i3c_bus_type_t type, + uint8_t address, + i3c_direction_t dir) +{ + return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, 0); +} + /*! * @brief Performs a polling send transfer on the I2C/I3C bus. * @@ -1294,10 +1357,10 @@ i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *coun */ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer); -/*@}*/ +/*! @} */ /*! @name Non-blocking */ -/*@{*/ +/*! @{ */ /*! * @brief Creates a new handle for the I3C master non-blocking APIs. @@ -1356,21 +1419,21 @@ status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, */ void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle); -/*@}*/ +/*! @} */ /*! @name IRQ handler */ -/*@{*/ +/*! @{ */ /*! * @brief Reusable routine to handle master interrupts. * @note This function does not need to be called unless you are reimplementing the * nonblocking API's interrupt handler routines to add special functionality. * @param base The I3C peripheral base address. - * @param handle Pointer to the I3C master driver handle. + * @param intHandle Pointer to the I3C master driver handle. */ void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle); -/*@}*/ +/*! @} */ /*! @} */ @@ -1380,7 +1443,7 @@ void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle); */ /*! @name Initialization and deinitialization */ -/*@{*/ +/*! @{ */ /*! * @brief Provides a default configuration for the I3C slave peripheral. @@ -1407,6 +1470,7 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig); * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of * defaults that you can override. * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. */ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz); @@ -1430,10 +1494,10 @@ static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable) base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable); } -/*@}*/ +/*! @} */ /*! @name Status */ -/*@{*/ +/*! @{ */ /*! * @brief Gets the I3C slave status flags. @@ -1514,10 +1578,10 @@ i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base); /* Not static so it can be used from fsl_i3c_dma.c. */ status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status); -/*@}*/ +/*! @} */ /*! @name Interrupts */ -/*@{*/ +/*! @{ */ /*! * @brief Enables the I3C slave interrupt requests. @@ -1593,10 +1657,10 @@ static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base) return base->SINTMASKED; } -/*@}*/ +/*! @} */ /*! @name DMA control */ -/*@{*/ +/*! @{ */ /*! * @brief Enables or disables I3C slave DMA requests. @@ -1639,10 +1703,10 @@ static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width) return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB); } -/*@}*/ +/*! @} */ /*! @name FIFO control */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the watermarks for I3C slave FIFOs. @@ -1683,11 +1747,12 @@ static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_ } } -/*@}*/ +/*! @} */ /*! @name Bus operations */ -/*@{*/ +/*! @{ */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) /*! * @brief I3C slave request event. * @@ -1695,6 +1760,7 @@ static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_ * @param event I3C slave event of type #i3c_slave_event_t */ void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event); +#endif /*! * @brief Performs a polling send transfer on the I3C bus. @@ -1716,10 +1782,10 @@ status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize); */ status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize); -/*@}*/ +/*! @} */ /*! @name Slave non-blocking */ -/*@{*/ +/*! @{ */ /*! * @brief Creates a new handle for the I3C slave non-blocking APIs. @@ -1789,42 +1855,45 @@ status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, s */ void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle); -/*@}*/ +/*! @} */ /*! @name Slave IRQ handler */ -/*@{*/ +/*! @{ */ /*! * @brief Reusable routine to handle slave interrupts. * @note This function does not need to be called unless you are reimplementing the * non blocking API's interrupt handler routines to add special functionality. * @param base The I3C peripheral base address. - * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @param intHandle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. */ void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle); +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) /*! - * @brief I3C slave request IBI event with multiple data payload. + * @brief I3C slave request IBI event with data payload(mandatory and extended). * * @param base The I3C peripheral base address. - * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. * @param data Pointer to IBI data to be sent in the request. * @param dataSize IBI data size. */ -void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize); +void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize); /*! * @brief I3C slave request IBI event with single data. + * @deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData. * * @param base The I3C peripheral base address. * @param data IBI data to be sent in the request. * @param dataSize IBI data size. */ void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize); -/*@}*/ +#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */ + +/*! @} */ /*! @} */ #if defined(__cplusplus) } #endif -#endif /* _FSL_I3C_H_ */ +#endif /* FSL_I3C_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.c new file mode 100644 index 0000000000..7ff5e8a6d0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.c @@ -0,0 +1,1057 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c_edma" +#endif + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_edma_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransmitDataState, + kReceiveDataState, + kStopState, + kWaitForCompletionState, + kAddressMatchState, +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_edma_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterDMAIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveDMAIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | + kI3C_SlaveBusStopFlag | /*kI3C_SlaveRxReadyFlag |*/ + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map I3C instance number to base pointer. */ +static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS; + +/*! @brief Array to store the END byte of I3C teransfer. */ +static uint8_t i3cEndByte[ARRAY_SIZE(kI3cBases)] = {0}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void I3C_MasterTransferEDMACallbackRx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + + if (transferDone) + { + /* Terminate following data if present. */ + i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U); + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.dataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.data + i3cHandle->transfer.dataSize - 1U) = + (uint8_t)i3cHandle->base->MRDATAB; + } +#endif + + /* Disable I3C Rx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMAFB_MASK; + } +} + +static void I3C_MasterTransferEDMACallbackTx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + uint32_t instance; + + if (transferDone) + { + /* Disable I3C Tx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMATB_MASK; + + if (i3cHandle->transferCount != 1U) + { + instance = I3C_GetInstance(i3cHandle->base); + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->MDATACTRL & I3C_MDATACTRL_TXFULL_MASK) != 0U) + { + } + i3cHandle->base->MWDATABE = i3cEndByte[instance]; + } + } +} +/*! + * brief Prepares the transfer state machine and fills in the command buffer. + * param handle Master nonblocking driver handle. + */ +static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + /* Calculate command count and put into command buffer. */ + handle->subaddressCount = 0U; + if (xfer->subaddressSize != 0U) + { + for (uint32_t i = xfer->subaddressSize; i > 0U; i--) + { + handle->subaddressBuffer[handle->subaddressCount++] = (uint8_t)((xfer->subaddress) >> (8U * (i - 1U))); + } + } + + /* Start condition shall be ommited, switch directly to next phase */ + if (xfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransmitDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + } + else + { + if (xfer->subaddressSize != 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (handle->transfer.direction == kI3C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI3C_Read) + { + handle->state = (uint8_t)kReceiveDataState; + } + else + { + return kStatus_InvalidArgument; + } + } + + if (handle->transfer.direction == kI3C_Read) + { + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Read); + } + + if (handle->state != (uint8_t)kStopState) + { + /* If repeated start is requested, send repeated start. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + } + } + + I3C_MasterTransferEDMAHandleIRQ(base, handle); + return result; +} + +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction) +{ + bool isEnableTxDMA = false; + bool isEnableRxDMA = false; + edma_transfer_config_t xferConfig; + uint32_t instance; + uint32_t address; + uint32_t width; + + handle->transferCount = dataSize; + + switch (direction) + { + case kI3C_Write: + if (dataSize != 1U) + { + address = (uint32_t)&base->MWDATAB1; + /* Cause controller sends command and data with same interface, need special buffer to store the END byte. */ + instance = I3C_GetInstance(base); + i3cEndByte[instance] = *(uint8_t *)((uint32_t)(uint32_t *)data + dataSize - 1U); + dataSize--; + } + else + { + address = (uint32_t)&base->MWDATABE; + } + EDMA_PrepareTransfer(&xferConfig, data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), 1, dataSize, + kEDMA_MemoryToPeripheral); + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txDmaHandle); + isEnableTxDMA = true; + width = 1U; + break; + + case kI3C_Read: +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + address = (uint32_t)&base->MRDATAB; + EDMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), data, sizeof(uint8_t), 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxDmaHandle); + isEnableRxDMA = true; + width = 1U; + break; + + default: + /* This should never happen */ + assert(false); + break; + } + + I3C_MasterEnableDMA(base, isEnableTxDMA, isEnableRxDMA, width); +} + +static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t errStatus; + status_t result = kStatus_Success; + i3c_master_transfer_t *xfer; + size_t rxCount = 0; + bool state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, status); + + i3c_master_state_t masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } + + if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return result; + } + + if (handle->state == (uint8_t)kIBIWonState) + { + /* Get fifo counts and compute room in tx fifo. */ + rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + state_complete = true; + break; + + case (uint8_t)kIBIWonState: + if (masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + rxCount--; + break; + } + else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + state_complete = true; + result = kStatus_I3C_IBIWon; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kSendCommandState: + I3C_MasterRunEDMATransfer(base, handle, handle->subaddressBuffer, handle->subaddressCount, kI3C_Write); + + if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize)) + { + if (0UL == xfer->dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + /* Next state, transfer data. */ + handle->state = (uint8_t)kTransmitDataState; + } + + state_complete = true; + break; + + case (uint8_t)kWaitRepeatedStartCompleteState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kReceiveDataState; + /* Send repeated start and slave address. */ + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read); + } + + state_complete = true; + break; + + case (uint8_t)kTransmitDataState: + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Write); + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kReceiveDataState: + /* Do DMA read. */ + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kWaitForCompletionState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + if (xfer->busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + result = I3C_MasterWaitForCtrlDone(base, false); + } + } + *isDone = true; + state_complete = true; + break; + + default: + assert(false); + break; + } + } + return result; +} + +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_MasterTransferEDMACallbackRx, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_MasterTransferEDMACallbackTx, handle); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterDMAIrqFlags); +} + +/*! + * brief Performs a non-blocking DMA transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts( + base, ((uint32_t)kMasterDMAIrqFlags | (uint32_t)kI3C_MasterRxReadyFlag | (uint32_t)kI3C_MasterTxReadyFlag)); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Generate commands to send. */ + (void)I3C_MasterInitTransferStateMachineEDMA(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)(kMasterDMAIrqFlags)); + + if (transfer->busType == kI3C_TypeI2C) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterSlaveStartFlag); + } + + return kStatus_Success; +} + +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + i3c_master_edma_handle_t *handle = (i3c_master_edma_handle_t *)i3cHandle; + + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_MasterRunTransferStateMachineEDMA(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + (void)I3C_MasterWaitForCtrlDone(base, false); + } + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + i3c_direction_t dir = handle->transfer.direction; + + if (dir == kI3C_Read) + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + + return kStatus_Success; +} + +/*! + * brief Abort a master edma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_MasterEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +static void I3C_SlaveTransferEDMACallback(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_slave_edma_handle_t *i3cHandle = (i3c_slave_edma_handle_t *)param; + + if (transferDone) + { + /* Simply disable dma enablement */ + if (i3cHandle->txDmaHandle == dmaHandle) + { + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMATB_MASK; + + if (i3cHandle->transfer.txDataSize > 1U) + { + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->SDATACTRL & I3C_SDATACTRL_TXFULL_MASK) != 0U) + { + } + /* Send the last byte. */ + i3cHandle->base->SWDATABE = *(uint8_t *)((uintptr_t)i3cHandle->transfer.txData + i3cHandle->transfer.txDataSize - 1U); + } + } + else + { +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.rxDataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_SlaveGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uintptr_t)i3cHandle->transfer.rxData + i3cHandle->transfer.rxDataSize - 1U) = + (uint8_t)i3cHandle->base->SRDATAB; + } +#endif + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMAFB_MASK; + } + } +} + +/*! + * brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + * param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_SlaveTransferEDMACallback, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_SlaveTransferEDMACallback, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Enable IRQ. */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); +} + +static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + edma_transfer_config_t txConfig; + uint32_t *txFifoBase; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + + if (xfer->txDataSize == 1U) + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATABE; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize, + kEDMA_MemoryToPeripheral); + } + else + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB1; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize - 1U, + kEDMA_MemoryToPeripheral); + } + + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &txConfig); + EDMA_StartTransfer(handle->txDmaHandle); +} + +static void I3C_SlavePrepareRxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + uint32_t *rxFifoBase = (uint32_t *)(uintptr_t)&base->SRDATAB; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + size_t dataSize = xfer->rxDataSize; + edma_transfer_config_t rxConfig; + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + + EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &rxConfig); + EDMA_StartTransfer(handle->rxDmaHandle); +} + +/*! + * brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param transfer The pointer to the transfer descriptor. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask) +{ + assert(NULL != handle); + assert(NULL != transfer); + + bool txDmaEn = false, rxDmaEn = false; + uint32_t width; + + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + /* Clear all flags. */ + I3C_SlaveClearErrorStatusFlags(base, (uint32_t)kSlaveErrorFlags); + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + + handle->transfer = *transfer; + + /* Set up event mask. */ + handle->eventMask = eventMask; + + if ((transfer->txData != NULL) && (transfer->txDataSize != 0U)) + { + I3C_SlavePrepareTxEDMA(base, handle); + txDmaEn = true; + width = 1U; + } + + if ((transfer->rxData != NULL) && (transfer->rxDataSize != 0U)) + { + I3C_SlavePrepareRxEDMA(base, handle); + rxDmaEn = true; + width = 1U; + } + + if (txDmaEn || rxDmaEn) + { + I3C_SlaveEnableDMA(base, txDmaEn, rxDmaEn, width); + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + uint32_t flags; + uint32_t errFlags; + i3c_slave_edma_transfer_t *xfer; + + i3c_slave_edma_handle_t *handle = (i3c_slave_edma_handle_t *)i3cHandle; + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, flags); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + if (handle->isBusy == true) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + I3C_SlaveTransferAbortEDMA(base, handle); + } + else + { + return; + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } +} + +/*! + * brief Abort a slave dma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + if (handle->isBusy != false) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_SlaveEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.h new file mode 100644 index 0000000000..8396e350d3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.h @@ -0,0 +1,279 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I3C_EDMA_H_ +#define FSL_I3C_EDMA_H_ + +#include "fsl_i3c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief I3C EDMA driver version. */ +#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 9)) +/*! @} */ + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_edma_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} i3c_master_edma_callback_t; +/*! + * @brief Driver handle for master EDMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint8_t subaddressBuffer[4]; /*!< Saving subaddress command. */ + uint8_t subaddressCount; /*!< Saving command count. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i3c_master_edma_callback_t callback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ +}; + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t; + +/*! @brief I3C slave transfer structure */ +typedef struct _i3c_slave_edma_transfer +{ + uint32_t event; /*!< Reason the callback is being invoked. */ + uint8_t *txData; /*!< Transfer buffer */ + size_t txDataSize; /*!< Transfer size */ + uint8_t *rxData; /*!< Transfer buffer */ + size_t rxDataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI3C_SlaveCompletionEvent. */ +} i3c_slave_edma_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave DMA transfer API. + * + * @param base Base address for the I3C instance on which the event occurred. + * @param handle Pointer to slave DMA transfer handle. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData); +/*! + * @brief I3C slave edma handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_slave_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + i3c_slave_edma_transfer_t transfer; /*!< I3C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i3c_slave_edma_callback_t callback; /*!< Callback function called at transfer event. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; +/*! @} */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*! @{ */ + +/*! + * @brief Create a new handle for the I3C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I3C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * DMA peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param i3cHandle Pointer to the I3C master DMA driver handle. + */ +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*! @} */ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ + +/*! @name Slave DMA */ +/*! @{ */ +/*! + * @brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param transfer The pointer to the transfer descriptor. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * @retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask); +/*! + * @brief Abort a slave edma non-blocking transfer in a early time + * + * @param base I3C peripheral base address + * @param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param i3cHandle Pointer to the I3C slave DMA driver handle. + */ +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*! @} */ + +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I3C_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c index bb188eb815..1f2ce0bcd2 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,12 +17,57 @@ #define FSL_COMPONENT_ID "platform.drivers.inputmux" #endif +#if defined(INPUTMUX_RSTS) +#define INPUTMUX_RESETS_ARRAY INPUTMUX_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! + * @brief Get instance number for INPUTMUX module. + * + * @param base INPUTMUX peripheral base address + */ +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! @brief Pointers to INPUTMUX bases for each instance. */ +static INPUTMUX_Type *const s_inputmuxBases[] = INPUTMUX_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_inputmuxResets[] = INPUTMUX_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_inputmuxBases); instance++) + { + if (s_inputmuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_inputmuxBases)); + + return instance; +} +#endif /*! - * brief Initialize INPUTMUX peripheral. + * brief Initialize INPUTMUX peripheral. * This function enables the INPUTMUX clock. * @@ -42,16 +87,26 @@ void INPUTMUX_Init(INPUTMUX_Type *base) CLOCK_EnableClock(kCLOCK_InputMux); #endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(INPUTMUX_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_inputmuxResets[INPUTMUX_GetInstance(base)]); +#endif } /*! * brief Attaches a signal * - * This function gates the INPUTPMUX clock. + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter p index specified as 2, this function configures register PINT_SEL2. * * param base Base address of the INPUTMUX peripheral. - * param index Destination peripheral to attach the signal to. - * param connection Selects connection. + * param index The serial number of destination register in the group of INPUTMUX registers with same name. + * param connection Applies signal from source signals collection to target signal. * * retval None. */ @@ -116,7 +171,7 @@ void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool e #endif /*! - * brief Deinitialize INPUTMUX peripheral. + * brief Deinitialize INPUTMUX peripheral. * This function disables the INPUTMUX clock. * diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h index cf30517d83..a8d5db82ec 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h @@ -1,13 +1,13 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2016-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_INPUTMUX_H_ -#define _FSL_INPUTMUX_H_ +#ifndef FSL_INPUTMUX_H_ +#define FSL_INPUTMUX_H_ #include "fsl_inputmux_connections.h" #include "fsl_common.h" @@ -25,10 +25,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*! @} */ /******************************************************************************* * API @@ -39,7 +39,7 @@ extern "C" { #endif /*! - * @brief Initialize INPUTMUX peripheral. + * @brief Initialize INPUTMUX peripheral. * This function enables the INPUTMUX clock. * @@ -52,11 +52,17 @@ void INPUTMUX_Init(INPUTMUX_Type *base); /*! * @brief Attaches a signal * - * This function gates the INPUTPMUX clock. + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * @code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * @endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter @p index specified as 2, this function configures register PINT_SEL2. * * @param base Base address of the INPUTMUX peripheral. - * @param index Destination peripheral to attach the signal to. - * @param connection Selects connection. + * @param index The serial number of destination register in the group of INPUTMUX registers with same name. + * @param connection Applies signal from source signals collection to target signal. * * @retval None. */ @@ -78,7 +84,7 @@ void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool e #endif /*! - * @brief Deinitialize INPUTMUX peripheral. + * @brief Deinitialize INPUTMUX peripheral. * This function disables the INPUTMUX clock. * @@ -92,6 +98,6 @@ void INPUTMUX_Deinit(INPUTMUX_Type *base); } #endif -/*@}*/ +/*! @} */ -#endif /* _FSL_INPUTMUX_H_ */ +#endif /* FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux_connections.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux_connections.h index f9b1819d37..5ee2d9b275 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux_connections.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux_connections.h @@ -48,16 +48,16 @@ #define DAC0_TRIG_REG 0x300U #define DAC1_TRIG_REG 0x320U #define DAC2_TRIG_REG 0x340U -#define ENC0_TRIG_REG 0x360U -#define ENC0_HOME_REG 0x364U -#define ENC0_INDEX_REG 0x368U -#define ENC0_PHASEB_REG 0x36CU -#define ENC0_PHASEA_REG 0x370U -#define ENC1_TRIG_REG 0x380U -#define ENC1_HOME_REG 0x384U -#define ENC1_INDEX_REG 0x388U -#define ENC1_PHASEB_REG 0x38CU -#define ENC1_PHASEA_REG 0x390U +#define QDC0_TRIG_REG 0x360U +#define QDC0_HOME_REG 0x364U +#define QDC0_INDEX_REG 0x368U +#define QDC0_PHASEB_REG 0x36CU +#define QDC0_PHASEA_REG 0x370U +#define QDC1_TRIG_REG 0x380U +#define QDC1_HOME_REG 0x384U +#define QDC1_INDEX_REG 0x388U +#define QDC1_PHASEB_REG 0x38CU +#define QDC1_PHASEA_REG 0x390U #define FlexPWM0_SM0_EXTSYNC_REG 0x3A0U #define FlexPWM0_SM1_EXTSYNC_REG 0x3A4U #define FlexPWM0_SM2_EXTSYNC_REG 0x3A8U @@ -168,8 +168,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToSct0 = 41U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToSct0 = 42U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToSct0 = 43U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToSct0 = 44U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToSct0 = 45U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToSct0 = 44U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToSct0 = 45U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToSct0 = 46U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToSct0 = 47U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToSct0 = 48U + (SCT0_INMUX0 << PMUX_SHIFT), @@ -223,6 +223,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), @@ -238,8 +239,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), @@ -287,6 +288,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), @@ -302,8 +304,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), @@ -351,6 +353,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), @@ -366,8 +369,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), @@ -415,6 +418,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), @@ -430,8 +434,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), @@ -479,6 +483,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), @@ -494,8 +499,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), @@ -543,6 +548,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), @@ -558,8 +564,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), @@ -607,6 +613,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), @@ -622,8 +629,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), @@ -671,6 +678,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), @@ -686,8 +694,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), @@ -735,6 +743,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), @@ -750,8 +759,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), @@ -799,6 +808,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_CtimerInp19ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Usb1StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0TxSyncOutToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Sai0RxSyncOutToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Adc0IrqToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), @@ -814,8 +824,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), @@ -841,6 +851,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_Sai1RxSyncOutToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), /*!< SMARTDMA arch B inputs. */ + kINPUTMUX_FlexioToSmartDma = 0U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin0ToSmartDma = 0U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin1ToSmartDma = 1U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin2ToSmartDma = 2U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), @@ -871,7 +882,6 @@ typedef enum _inputmux_connection_t kINPUTMUX_Wdt0IrqToSmartDma = 29U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Adc0IrqToSmartDma = 30U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Cmp0IrqToSmartDma = 31U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), - kINPUTMUX_LspiHsIrqToSmartDma = 32U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_LpFlexcomm7IrqToSmartDma = 33U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_LpFlexcomm6IrqToSmartDma = 34U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_LpFlexcomm5IrqToSmartDma = 35U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), @@ -896,10 +906,10 @@ typedef enum _inputmux_connection_t kINPUTMUX_Dac12IrqToSmartDma = 56U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Pwm0IrqToSmartDma = 57U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Pwm1IrqToSmartDma = 58U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Enc0IrqToSmartDma = 59U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Enc1IrqToSmartDma = 60U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc0IrqToSmartDma = 59U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc1IrqToSmartDma = 60U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToSmartDma = 61U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToSmartDma = 62U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToSmartDma = 62U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Gpio1PinEventTrig0ToSmartDma = 65U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Gpio1PinEventTrig1ToSmartDma = 66U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), kINPUTMUX_Gpio2PinEventTrig0ToSmartDma = 67U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), @@ -1012,8 +1022,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToCmp0Trigger = 23U + (CMP0_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToCmp0Trigger = 24U + (CMP0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), @@ -1052,8 +1062,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToCmp1Trigger = 23U + (CMP1_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToCmp1Trigger = 24U + (CMP1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), @@ -1092,8 +1102,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToCmp2Trigger = 22U + (CMP2_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToCmp2Trigger = 23U + (CMP2_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToCmp2Trigger = 24U + (CMP2_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToCmp2Trigger = 25U + (CMP2_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToCmp2Trigger = 26U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp2Trigger = 25U + (CMP2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp2Trigger = 26U + (CMP2_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToCmp2Trigger = 27U + (CMP2_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToCmp2Trigger = 28U + (CMP2_TRIG_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToCmp2Trigger = 29U + (CMP2_TRIG_REG << PMUX_SHIFT), @@ -1150,8 +1160,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToAdc0Trigger = 37U + (ADC0_TRIG0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToAdc0Trigger = 38U + (ADC0_TRIG0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToAdc0Trigger = 39U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToAdc0Trigger = 42U + (ADC0_TRIG0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToAdc0Trigger = 43U + (ADC0_TRIG0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToAdc0Trigger = 44U + (ADC0_TRIG0 << PMUX_SHIFT), @@ -1218,8 +1228,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToAdc1Trigger = 37U + (ADC1_TRIG0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToAdc1Trigger = 38U + (ADC1_TRIG0 << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToAdc1Trigger = 39U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToAdc1Trigger = 42U + (ADC1_TRIG0 << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToAdc1Trigger = 43U + (ADC1_TRIG0 << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToAdc1Trigger = 44U + (ADC1_TRIG0 << PMUX_SHIFT), @@ -1344,535 +1354,535 @@ typedef enum _inputmux_connection_t kINPUTMUX_Gpio3PinEventTrig0ToDac2Trigger = 30U + (DAC2_TRIG_REG << PMUX_SHIFT), kINPUTMUX_Gpio3PinEventTrig1ToDac2Trigger = 31U + (DAC2_TRIG_REG << PMUX_SHIFT), - /*!< ENC0 Trigger Input Connections. */ - kINPUTMUX_PinInt0ToEnc0Trigger = 0U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Trigger = 1U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Trigger = 2U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Trigger = 3U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Trigger = 4U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Trigger = 5U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Trigger = 6U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Trigger = 7U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Trigger = 8U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Trigger = 9U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Trigger = 11U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc0Trigger = 12U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Trigger = 13U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Trigger = 14U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Trigger = 15U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Trigger = 16U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Trigger = 17U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Trigger = 18U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Trigger = 19U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Trigger = 20U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc0Trigger = 21U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc0Trigger = 22U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc0Trigger = 23U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc0Trigger = 24U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc0Trigger = 25U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc0Trigger = 26U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc0Trigger = 27U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc0Trigger = 28U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc0Trigger = 29U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc0Trigger = 30U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc0Trigger = 31U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Trigger = 32U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Trigger = 33U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc0Trigger = 34U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc0Trigger = 35U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc0Trigger = 36U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc0Trigger = 37U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc0Trigger = 38U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc0Trigger = 39U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc0Trigger = 40U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc0Trigger = 41U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc0Trigger = 42U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc0Trigger = 43U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc0Trigger = 44U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc0Trigger = 45U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc0Trigger = 46U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc0Trigger = 47U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc0Trigger = 48U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc0Trigger = 49U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc0Trigger = 50U + (ENC0_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc0Trigger = 51U + (ENC0_TRIG_REG << PMUX_SHIFT), + /*!< QDC0 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Trigger = 0U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc0Trigger = 2U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc0Trigger = 3U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc0Trigger = 4U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Trigger = 8U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Trigger = 15U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 22U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Trigger = 23U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 45U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 46U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 47U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 48U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), - /*!< ENC0 Home Input Connections. */ - kINPUTMUX_PinInt0ToEnc0Home = 0U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Home = 1U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Home = 2U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Home = 3U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Home = 4U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Home = 5U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Home = 6U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Home = 7U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Home = 8U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Home = 9U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Home = 11U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc0Home = 12U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Home = 13U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Home = 14U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Home = 15U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Home = 16U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Home = 17U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Home = 18U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Home = 19U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Home = 20U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc0Home = 21U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc0Home = 22U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc0Home = 23U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc0Home = 24U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc0Home = 25U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc0Home = 26U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc0Home = 27U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc0Home = 28U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc0Home = 29U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc0Home = 30U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc0Home = 31U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Home = 32U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Home = 33U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc0Home = 34U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc0Home = 35U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc0Home = 36U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc0Home = 37U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc0Home = 38U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc0Home = 39U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc0Home = 40U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc0Home = 41U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc0Home = 42U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc0Home = 43U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc0Home = 44U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc0Home = 45U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc0Home = 46U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc0Home = 47U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc0Home = 48U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc0Home = 49U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc0Home = 50U + (ENC0_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc0Home = 51U + (ENC0_HOME_REG << PMUX_SHIFT), + /*!< QDC0 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Home = 0U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc0Home = 2U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc0Home = 3U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc0Home = 4U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Home = 8U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Home = 15U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 22U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Home = 23U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 45U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 46U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 47U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 48U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), - /*!< ENC0 Index Input Connections. */ - kINPUTMUX_PinInt0ToEnc0Index = 0U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Index = 1U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Index = 2U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Index = 3U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Index = 4U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Index = 5U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Index = 6U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Index = 7U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Index = 8U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Index = 9U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Index = 11U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc0Index = 12U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Index = 13U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Index = 14U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Index = 15U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Index = 16U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Index = 17U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Index = 18U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Index = 19U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Index = 20U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc0Index = 21U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc0Index = 22U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc0Index = 23U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc0Index = 24U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc0Index = 25U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc0Index = 26U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc0Index = 27U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc0Index = 28U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc0Index = 29U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc0Index = 30U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc0Index = 31U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Index = 32U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Index = 33U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc0Index = 34U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc0Index = 35U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc0Index = 36U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc0Index = 37U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc0Index = 38U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc0Index = 39U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc0Index = 40U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc0Index = 41U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc0Index = 42U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc0Index = 43U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc0Index = 44U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc0Index = 45U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc0Index = 46U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc0Index = 47U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc0Index = 48U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc0Index = 49U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc0Index = 50U + (ENC0_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc0Index = 51U + (ENC0_INDEX_REG << PMUX_SHIFT), + /*!< QDC0 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Index = 0U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc0Index = 2U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc0Index = 3U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc0Index = 4U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Index = 8U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Index = 15U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 22U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Index = 23U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 45U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 46U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 47U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 48U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), - /*!< ENC0 Phaseb Input Connections. */ - kINPUTMUX_PinInt0ToEnc0Phaseb = 0U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Phaseb = 1U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Phaseb = 2U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Phaseb = 3U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Phaseb = 4U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Phaseb = 5U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Phaseb = 6U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Phaseb = 7U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Phaseb = 8U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Phaseb = 9U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Phaseb = 11U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc0Phaseb = 12U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Phaseb = 13U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Phaseb = 14U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Phaseb = 15U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Phaseb = 16U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Phaseb = 17U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Phaseb = 18U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Phaseb = 19U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Phaseb = 20U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc0Phaseb = 21U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc0Phaseb = 22U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc0Phaseb = 23U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc0Phaseb = 24U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc0Phaseb = 25U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc0Phaseb = 26U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc0Phaseb = 27U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc0Phaseb = 28U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc0Phaseb = 29U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc0Phaseb = 30U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc0Phaseb = 31U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Phaseb = 32U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Phaseb = 33U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc0Phaseb = 34U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc0Phaseb = 35U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc0Phaseb = 36U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc0Phaseb = 37U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc0Phaseb = 38U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc0Phaseb = 39U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc0Phaseb = 40U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc0Phaseb = 41U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc0Phaseb = 42U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc0Phaseb = 43U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc0Phaseb = 44U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc0Phaseb = 45U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc0Phaseb = 46U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc0Phaseb = 47U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc0Phaseb = 48U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc0Phaseb = 49U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc0Phaseb = 50U + (ENC0_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc0Phaseb = 51U + (ENC0_PHASEB_REG << PMUX_SHIFT), + /*!< QDC0 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phaseb = 0U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc0Phaseb = 2U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc0Phaseb = 3U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc0Phaseb = 4U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phaseb = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phaseb = 15U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Phaseb = 23U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 45U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 46U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 47U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 48U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), - /*!< ENC0 Phasea Input Connections. */ - kINPUTMUX_PinInt0ToEnc0Phasea = 0U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_PinInt4ToEnc0Phasea = 1U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc0Phasea = 2U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc0Phasea = 3U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc0Phasea = 4U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc0Phasea = 5U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc0Phasea = 6U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc0Phasea = 7U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToEnc0Phasea = 8U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToEnc0Phasea = 9U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc0Phasea = 11U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc0Phasea = 12U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc0Phasea = 13U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc0Phasea = 14U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc0Phasea = 15U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc0Phasea = 16U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc0Phasea = 17U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc0Phasea = 18U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc0Phasea = 19U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc0Phasea = 20U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc0Phasea = 21U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc0Phasea = 22U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc0Phasea = 23U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc0Phasea = 24U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc0Phasea = 25U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc0Phasea = 26U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc0Phasea = 27U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc0Phasea = 28U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc0Phasea = 29U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc0Phasea = 30U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc0Phasea = 31U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc0Phasea = 32U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc0Phasea = 33U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc0Phasea = 34U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc0Phasea = 35U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc0Phasea = 36U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc0Phasea = 37U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc0Phasea = 38U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc0Phasea = 39U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc0Phasea = 40U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc0Phasea = 41U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc0Phasea = 42U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc0Phasea = 43U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc0Phasea = 44U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc0Phasea = 45U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc0Phasea = 46U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc0Phasea = 47U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc0Phasea = 48U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc0Phasea = 49U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc0Phasea = 50U + (ENC0_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc0Phasea = 51U + (ENC0_PHASEA_REG << PMUX_SHIFT), + /*!< QDC0 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phasea = 0U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc0Phasea = 2U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc0Phasea = 3U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc0Phasea = 4U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phasea = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phasea = 15U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc0Phasea = 23U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 45U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 46U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 47U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 48U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), - /*!< ENC1 Trigger Input Connections. */ - kINPUTMUX_PinInt0ToEnc1Trigger = 0U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Trigger = 1U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Trigger = 2U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Trigger = 3U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc1Trigger = 4U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Trigger = 5U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Trigger = 6U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Trigger = 7U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Trigger = 8U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Trigger = 9U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Trigger = 11U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc1Trigger = 12U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Trigger = 13U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Trigger = 14U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Trigger = 15U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Trigger = 16U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Trigger = 17U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Trigger = 18U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Trigger = 19U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Trigger = 20U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc1Trigger = 21U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc1Trigger = 22U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc1Trigger = 23U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc1Trigger = 24U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc1Trigger = 25U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc1Trigger = 26U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc1Trigger = 27U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc1Trigger = 28U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc1Trigger = 29U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc1Trigger = 30U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc1Trigger = 31U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Trigger = 32U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Trigger = 33U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc1Trigger = 34U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc1Trigger = 35U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc1Trigger = 36U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc1Trigger = 37U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc1Trigger = 38U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc1Trigger = 39U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc1Trigger = 40U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc1Trigger = 41U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc1Trigger = 42U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc1Trigger = 43U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc1Trigger = 44U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc1Trigger = 45U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc1Trigger = 46U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc1Trigger = 47U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc1Trigger = 48U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc1Trigger = 49U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc1Trigger = 50U + (ENC1_TRIG_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc1Trigger = 51U + (ENC1_TRIG_REG << PMUX_SHIFT), + /*!< QDC1 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Trigger = 0U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc1Trigger = 2U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc1Trigger = 3U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc1Trigger = 4U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Trigger = 8U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Trigger = 15U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 22U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Trigger = 23U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 45U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 46U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 47U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 48U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), - /*!< ENC1 Home Input Connections. */ - kINPUTMUX_PinInt0ToEnc1Home = 0U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Home = 1U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Home = 2U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Home = 3U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc1Home = 4U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Home = 5U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Home = 6U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Home = 7U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Home = 8U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Home = 9U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Home = 11U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc1Home = 12U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Home = 13U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Home = 14U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Home = 15U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Home = 16U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Home = 17U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Home = 18U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Home = 19U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Home = 20U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc1Home = 21U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc1Home = 22U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc1Home = 23U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc1Home = 24U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc1Home = 25U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc1Home = 26U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc1Home = 27U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc1Home = 28U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc1Home = 29U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc1Home = 30U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc1Home = 31U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Home = 32U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Home = 33U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc1Home = 34U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc1Home = 35U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc1Home = 36U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc1Home = 37U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc1Home = 38U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc1Home = 39U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc1Home = 40U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc1Home = 41U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc1Home = 42U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc1Home = 43U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc1Home = 44U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc1Home = 45U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc1Home = 46U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc1Home = 47U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc1Home = 48U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc1Home = 49U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc1Home = 50U + (ENC1_HOME_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc1Home = 51U + (ENC1_HOME_REG << PMUX_SHIFT), + /*!< QDC1 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Home = 0U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc1Home = 2U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc1Home = 3U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc1Home = 4U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Home = 8U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Home = 15U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 22U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Home = 23U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 45U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 46U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 47U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 48U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), - /*!< ENC1 Index Input Connections. */ - kINPUTMUX_PinInt0ToEnc1Index = 0U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Index = 1U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Index = 2U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Index = 3U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc1Index = 4U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Index = 5U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Index = 6U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Index = 7U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Index = 8U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Index = 9U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Index = 11U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc1Index = 12U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Index = 13U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Index = 14U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Index = 15U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Index = 16U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Index = 17U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Index = 18U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Index = 19U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Index = 20U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc1Index = 21U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc1Index = 22U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc1Index = 23U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc1Index = 24U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc1Index = 25U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc1Index = 26U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc1Index = 27U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc1Index = 28U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc1Index = 29U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc1Index = 30U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc1Index = 31U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Index = 32U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Index = 33U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc1Index = 34U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc1Index = 35U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc1Index = 36U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc1Index = 37U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc1Index = 38U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc1Index = 39U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc1Index = 40U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc1Index = 41U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc1Index = 42U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc1Index = 43U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc1Index = 44U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc1Index = 45U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc1Index = 46U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc1Index = 47U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc1Index = 48U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc1Index = 49U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc1Index = 50U + (ENC1_INDEX_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc1Index = 51U + (ENC1_INDEX_REG << PMUX_SHIFT), + /*!< QDC1 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Index = 0U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc1Index = 2U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc1Index = 3U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc1Index = 4U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Index = 8U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Index = 15U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 22U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Index = 23U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 45U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 46U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 47U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 48U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), - /*!< ENC1 Phaseb Input Connections. */ - kINPUTMUX_PinInt0ToEnc1Phaseb = 0U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Phaseb = 1U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Phaseb = 2U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Phaseb = 3U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc1Phaseb = 4U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Phaseb = 5U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Phaseb = 6U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Phaseb = 7U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Phaseb = 8U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Phaseb = 9U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Phaseb = 11U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc1Phaseb = 12U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Phaseb = 13U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Phaseb = 14U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Phaseb = 15U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Phaseb = 16U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Phaseb = 17U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Phaseb = 18U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Phaseb = 19U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Phaseb = 20U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc1Phaseb = 21U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc1Phaseb = 22U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc1Phaseb = 23U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc1Phaseb = 24U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc1Phaseb = 25U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc1Phaseb = 26U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc1Phaseb = 27U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc1Phaseb = 28U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc1Phaseb = 29U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc1Phaseb = 30U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc1Phaseb = 31U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Phaseb = 32U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Phaseb = 33U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc1Phaseb = 34U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc1Phaseb = 35U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc1Phaseb = 36U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc1Phaseb = 37U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc1Phaseb = 38U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc1Phaseb = 39U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc1Phaseb = 40U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc1Phaseb = 41U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc1Phaseb = 42U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc1Phaseb = 43U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc1Phaseb = 44U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc1Phaseb = 45U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc1Phaseb = 46U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc1Phaseb = 47U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc1Phaseb = 48U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc1Phaseb = 49U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc1Phaseb = 50U + (ENC1_PHASEB_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc1Phaseb = 51U + (ENC1_PHASEB_REG << PMUX_SHIFT), + /*!< QDC1 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phaseb = 0U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc1Phaseb = 2U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc1Phaseb = 3U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc1Phaseb = 4U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phaseb = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phaseb = 15U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Phaseb = 23U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 45U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 46U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 47U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 48U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), - /*!< ENC1 Phasea Input Connections. */ - kINPUTMUX_PinInt0ToEnc1Phasea = 0U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_PinInt5ToEnc1Phasea = 1U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut4ToEnc1Phasea = 2U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut5ToEnc1Phasea = 3U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut1ToEnc1Phasea = 4U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer0M3ToEnc1Phasea = 5U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M3ToEnc1Phasea = 6U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer2M3ToEnc1Phasea = 7U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToEnc1Phasea = 8U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToEnc1Phasea = 9U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_ArmTxevToEnc1Phasea = 11U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_GpioIntBmatchToEnc1Phasea = 12U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp0ToEnc1Phasea = 13U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp1ToEnc1Phasea = 14U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp2ToEnc1Phasea = 15U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc0Tcomp3ToEnc1Phasea = 16U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp0ToEnc1Phasea = 17U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp1ToEnc1Phasea = 18U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp2ToEnc1Phasea = 19U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Adc1Tcomp3ToEnc1Phasea = 20U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Cmp0OutToEnc1Phasea = 21U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Cmp1OutToEnc1Phasea = 22U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Cmp2OutToEnc1Phasea = 23U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToEnc1Phasea = 24U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToEnc1Phasea = 25U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToEnc1Phasea = 26U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToEnc1Phasea = 27U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToEnc1Phasea = 28U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToEnc1Phasea = 29U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToEnc1Phasea = 30U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToEnc1Phasea = 31U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEnc1Phasea = 32U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEnc1Phasea = 33U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0AToEnc1Phasea = 34U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut0BToEnc1Phasea = 35U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1AToEnc1Phasea = 36U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut1BToEnc1Phasea = 37U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2AToEnc1Phasea = 38U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut2BToEnc1Phasea = 39U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3AToEnc1Phasea = 40U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_EvtgOut3BToEnc1Phasea = 41U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn0ToEnc1Phasea = 42U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn1ToEnc1Phasea = 43U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn2ToEnc1Phasea = 44U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn3ToEnc1Phasea = 45U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn4ToEnc1Phasea = 46U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn5ToEnc1Phasea = 47U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn6ToEnc1Phasea = 48U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn7ToEnc1Phasea = 49U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn8ToEnc1Phasea = 50U + (ENC1_PHASEA_REG << PMUX_SHIFT), - kINPUTMUX_TrigIn9ToEnc1Phasea = 51U + (ENC1_PHASEA_REG << PMUX_SHIFT), + /*!< QDC1 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phasea = 0U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut4ToQdc1Phasea = 2U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut5ToQdc1Phasea = 3U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut1ToQdc1Phasea = 4U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phasea = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phasea = 15U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp2OutToQdc1Phasea = 23U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 45U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 46U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 47U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 48U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), /*!< FlexPWM0_SM0_EXTSYNC input trigger connections. */ kINPUTMUX_PinInt0ToFlexPwm0Sm0ExtSync = 0U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), @@ -1906,8 +1916,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0ExtSync = 29U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0ExtSync = 30U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0ExtSync = 31U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm0ExtSync = 32U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm0ExtSync = 33U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0ExtSync = 32U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0ExtSync = 33U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm0ExtSync = 34U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm0ExtSync = 35U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm0ExtSync = 36U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), @@ -1968,8 +1978,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1ExtSync = 29U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1ExtSync = 30U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1ExtSync = 31U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm1ExtSync = 32U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm1ExtSync = 33U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1ExtSync = 32U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1ExtSync = 33U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm1ExtSync = 34U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm1ExtSync = 35U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm1ExtSync = 36U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), @@ -2030,8 +2040,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2ExtSync = 29U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2ExtSync = 30U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2ExtSync = 31U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm2ExtSync = 32U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm2ExtSync = 33U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2ExtSync = 32U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2ExtSync = 33U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm2ExtSync = 34U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm2ExtSync = 35U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm2ExtSync = 36U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), @@ -2092,8 +2102,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3ExtSync = 29U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3ExtSync = 30U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3ExtSync = 31U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm3ExtSync = 32U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm3ExtSync = 33U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3ExtSync = 32U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3ExtSync = 33U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm3ExtSync = 34U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm3ExtSync = 35U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm3ExtSync = 36U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), @@ -2154,8 +2164,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0Exta = 29U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0Exta = 30U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0Exta = 31U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm0Exta = 32U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm0Exta = 33U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0Exta = 32U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0Exta = 33U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm0Exta = 34U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm0Exta = 35U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm0Exta = 36U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), @@ -2216,8 +2226,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1Exta = 29U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1Exta = 30U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1Exta = 31U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm1Exta = 32U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm1Exta = 33U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1Exta = 32U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1Exta = 33U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm1Exta = 34U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm1Exta = 35U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm1Exta = 36U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), @@ -2278,8 +2288,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2Exta = 29U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2Exta = 30U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2Exta = 31U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm2Exta = 32U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm2Exta = 33U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2Exta = 32U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2Exta = 33U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm2Exta = 34U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm2Exta = 35U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm2Exta = 36U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), @@ -2340,8 +2350,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3Exta = 29U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3Exta = 30U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3Exta = 31U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Sm3Exta = 32U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Sm3Exta = 33U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3Exta = 32U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3Exta = 33U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Sm3Exta = 34U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Sm3Exta = 35U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Sm3Exta = 36U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), @@ -2402,8 +2412,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0ExtForce = 29U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0ExtForce = 30U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0ExtForce = 31U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0ExtForce = 32U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0ExtForce = 33U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0ExtForce = 32U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0ExtForce = 33U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0ExtForce = 34U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0ExtForce = 35U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0ExtForce = 36U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), @@ -2464,8 +2474,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault0 = 29U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault0 = 30U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault0 = 31U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Fault0 = 32U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Fault0 = 33U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault0 = 32U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault0 = 33U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Fault0 = 34U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Fault0 = 35U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Fault0 = 36U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), @@ -2526,8 +2536,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault1 = 29U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault1 = 30U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault1 = 31U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Fault1 = 32U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Fault1 = 33U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault1 = 32U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault1 = 33U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Fault1 = 34U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Fault1 = 35U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Fault1 = 36U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), @@ -2588,8 +2598,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault2 = 29U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault2 = 30U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault2 = 31U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Fault2 = 32U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Fault2 = 33U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault2 = 32U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault2 = 33U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Fault2 = 34U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Fault2 = 35U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Fault2 = 36U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), @@ -2650,8 +2660,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault3 = 29U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault3 = 30U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault3 = 31U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm0Fault3 = 32U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm0Fault3 = 33U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault3 = 32U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault3 = 33U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm0Fault3 = 34U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm0Fault3 = 35U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm0Fault3 = 36U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), @@ -2685,7 +2695,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm0ExtSync = 1U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm0ExtSync = 2U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm0ExtSync = 3U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm0ExtSync = 4U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm0ExtSync = 4U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0ExtSync = 5U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0ExtSync = 6U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0ExtSync = 7U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), @@ -2704,16 +2714,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm0ExtSync = 21U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm0ExtSync = 22U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm0ExtSync = 23U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm0ExtSync = 24U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm0ExtSync = 25U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm0ExtSync = 26U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm0ExtSync = 27U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm0ExtSync = 28U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm0ExtSync = 29U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm0ExtSync = 30U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm0ExtSync = 31U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm0ExtSync = 32U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm0ExtSync = 33U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0ExtSync = 24U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0ExtSync = 25U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0ExtSync = 26U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0ExtSync = 27U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0ExtSync = 28U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0ExtSync = 29U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0ExtSync = 30U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0ExtSync = 31U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0ExtSync = 32U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0ExtSync = 33U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm0ExtSync = 34U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm0ExtSync = 35U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm0ExtSync = 36U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), @@ -2747,7 +2757,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm1ExtSync = 1U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm1ExtSync = 2U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm1ExtSync = 3U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm1ExtSync = 4U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm1ExtSync = 4U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1ExtSync = 5U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1ExtSync = 6U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1ExtSync = 7U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), @@ -2766,16 +2776,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm1ExtSync = 21U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm1ExtSync = 22U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm1ExtSync = 23U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm1ExtSync = 24U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm1ExtSync = 25U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm1ExtSync = 26U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm1ExtSync = 27U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm1ExtSync = 28U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm1ExtSync = 29U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm1ExtSync = 30U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm1ExtSync = 31U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm1ExtSync = 32U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm1ExtSync = 33U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1ExtSync = 24U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1ExtSync = 25U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1ExtSync = 26U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1ExtSync = 27U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1ExtSync = 28U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1ExtSync = 29U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1ExtSync = 30U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1ExtSync = 31U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1ExtSync = 32U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1ExtSync = 33U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm1ExtSync = 34U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm1ExtSync = 35U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm1ExtSync = 36U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), @@ -2809,7 +2819,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm2ExtSync = 1U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm2ExtSync = 2U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm2ExtSync = 3U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm2ExtSync = 4U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm2ExtSync = 4U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2ExtSync = 5U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2ExtSync = 6U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2ExtSync = 7U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), @@ -2828,16 +2838,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm2ExtSync = 21U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm2ExtSync = 22U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm2ExtSync = 23U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm2ExtSync = 24U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm2ExtSync = 25U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm2ExtSync = 26U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm2ExtSync = 27U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm2ExtSync = 28U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm2ExtSync = 29U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm2ExtSync = 30U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm2ExtSync = 31U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm2ExtSync = 32U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm2ExtSync = 33U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2ExtSync = 24U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2ExtSync = 25U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2ExtSync = 26U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2ExtSync = 27U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2ExtSync = 28U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2ExtSync = 29U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2ExtSync = 30U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2ExtSync = 31U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2ExtSync = 32U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2ExtSync = 33U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm2ExtSync = 34U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm2ExtSync = 35U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm2ExtSync = 36U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), @@ -2871,7 +2881,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm3ExtSync = 1U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm3ExtSync = 2U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm3ExtSync = 3U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm3ExtSync = 4U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm3ExtSync = 4U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3ExtSync = 5U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3ExtSync = 6U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3ExtSync = 7U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), @@ -2890,16 +2900,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm3ExtSync = 21U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm3ExtSync = 22U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm3ExtSync = 23U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm3ExtSync = 24U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm3ExtSync = 25U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm3ExtSync = 26U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm3ExtSync = 27U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm3ExtSync = 28U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm3ExtSync = 29U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm3ExtSync = 30U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm3ExtSync = 31U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm3ExtSync = 32U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm3ExtSync = 33U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3ExtSync = 24U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3ExtSync = 25U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3ExtSync = 26U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3ExtSync = 27U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3ExtSync = 28U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3ExtSync = 29U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3ExtSync = 30U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3ExtSync = 31U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3ExtSync = 32U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3ExtSync = 33U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm3ExtSync = 34U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm3ExtSync = 35U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm3ExtSync = 36U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), @@ -2933,7 +2943,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm0Exta = 1U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm0Exta = 2U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm0Exta = 3U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm0Exta = 4U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm0Exta = 4U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta = 5U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta = 6U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta = 7U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), @@ -2952,16 +2962,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta = 21U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta = 22U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm0Exta = 23U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm0Exta = 24U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm0Exta = 25U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm0Exta = 26U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm0Exta = 27U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm0Exta = 28U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm0Exta = 29U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm0Exta = 30U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm0Exta = 31U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm0Exta = 32U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm0Exta = 33U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0Exta = 24U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0Exta = 25U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0Exta = 26U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0Exta = 27U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0Exta = 28U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0Exta = 29U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0Exta = 30U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0Exta = 31U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0Exta = 32U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0Exta = 33U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm0Exta = 34U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm0Exta = 35U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm0Exta = 36U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), @@ -2995,7 +3005,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm1Exta = 1U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm1Exta = 2U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm1Exta = 3U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm1Exta = 4U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm1Exta = 4U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta = 5U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta = 6U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta = 7U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), @@ -3014,16 +3024,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta = 21U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta = 22U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm1Exta = 23U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm1Exta = 24U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm1Exta = 25U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm1Exta = 26U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm1Exta = 27U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm1Exta = 28U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm1Exta = 29U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm1Exta = 30U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm1Exta = 31U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm1Exta = 32U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm1Exta = 33U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1Exta = 24U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1Exta = 25U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1Exta = 26U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1Exta = 27U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1Exta = 28U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1Exta = 29U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1Exta = 30U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1Exta = 31U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1Exta = 32U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1Exta = 33U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm1Exta = 34U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm1Exta = 35U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm1Exta = 36U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), @@ -3057,7 +3067,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm2Exta = 1U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm2Exta = 2U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm2Exta = 3U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm2Exta = 4U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm2Exta = 4U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta = 5U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta = 6U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta = 7U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), @@ -3076,16 +3086,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta = 21U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta = 22U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm2Exta = 23U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm2Exta = 24U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm2Exta = 25U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm2Exta = 26U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm2Exta = 27U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm2Exta = 28U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm2Exta = 29U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm2Exta = 30U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm2Exta = 31U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm2Exta = 32U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm2Exta = 33U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2Exta = 24U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2Exta = 25U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2Exta = 26U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2Exta = 27U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2Exta = 28U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2Exta = 29U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2Exta = 30U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2Exta = 31U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2Exta = 32U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2Exta = 33U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm2Exta = 34U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm2Exta = 35U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm2Exta = 36U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), @@ -3119,7 +3129,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Sm3Exta = 1U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Sm3Exta = 2U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Sm3Exta = 3U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Sm3Exta = 4U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Sm3Exta = 4U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta = 5U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta = 6U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta = 7U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), @@ -3138,16 +3148,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta = 21U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta = 22U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Sm3Exta = 23U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Sm3Exta = 24U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Sm3Exta = 25U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Sm3Exta = 26U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Sm3Exta = 27U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Sm3Exta = 28U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Sm3Exta = 29U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Sm3Exta = 30U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Sm3Exta = 31U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Sm3Exta = 32U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Sm3Exta = 33U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3Exta = 24U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3Exta = 25U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3Exta = 26U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3Exta = 27U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3Exta = 28U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3Exta = 29U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3Exta = 30U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3Exta = 31U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3Exta = 32U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3Exta = 33U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Sm3Exta = 34U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Sm3Exta = 35U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Sm3Exta = 36U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), @@ -3181,7 +3191,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1ExtForce = 1U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1ExtForce = 2U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1ExtForce = 3U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1ExtForce = 4U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1ExtForce = 4U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1ExtForce = 5U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1ExtForce = 6U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1ExtForce = 7U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), @@ -3200,16 +3210,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1ExtForce = 21U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1ExtForce = 22U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1ExtForce = 23U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1ExtForce = 24U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1ExtForce = 25U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1ExtForce = 26U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1ExtForce = 27U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1ExtForce = 28U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1ExtForce = 29U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1ExtForce = 30U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1ExtForce = 31U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1ExtForce = 32U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1ExtForce = 33U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1ExtForce = 24U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1ExtForce = 25U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1ExtForce = 26U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1ExtForce = 27U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1ExtForce = 28U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1ExtForce = 29U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1ExtForce = 30U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1ExtForce = 31U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1ExtForce = 32U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1ExtForce = 33U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1ExtForce = 34U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1ExtForce = 35U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1ExtForce = 36U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), @@ -3243,7 +3253,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Fault0 = 1U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Fault0 = 2U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Fault0 = 3U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Fault0 = 4U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Fault0 = 4U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Fault0 = 5U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Fault0 = 6U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Fault0 = 7U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), @@ -3262,16 +3272,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Fault0 = 21U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Fault0 = 22U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Fault0 = 23U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Fault0 = 24U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Fault0 = 25U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Fault0 = 26U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Fault0 = 27U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Fault0 = 28U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Fault0 = 29U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Fault0 = 30U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Fault0 = 31U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Fault0 = 32U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Fault0 = 33U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault0 = 24U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault0 = 25U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault0 = 26U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault0 = 27U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault0 = 28U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault0 = 29U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault0 = 30U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault0 = 31U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault0 = 32U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault0 = 33U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Fault0 = 34U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Fault0 = 35U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Fault0 = 36U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), @@ -3305,7 +3315,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Fault1 = 1U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Fault1 = 2U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Fault1 = 3U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Fault1 = 4U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Fault1 = 4U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Fault1 = 5U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Fault1 = 6U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Fault1 = 7U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), @@ -3324,16 +3334,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Fault1 = 21U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Fault1 = 22U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Fault1 = 23U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Fault1 = 24U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Fault1 = 25U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Fault1 = 26U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Fault1 = 27U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Fault1 = 28U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Fault1 = 29U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Fault1 = 30U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Fault1 = 31U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Fault1 = 32U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Fault1 = 33U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault1 = 24U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault1 = 25U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault1 = 26U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault1 = 27U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault1 = 28U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault1 = 29U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault1 = 30U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault1 = 31U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault1 = 32U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault1 = 33U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Fault1 = 34U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Fault1 = 35U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Fault1 = 36U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), @@ -3367,7 +3377,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Fault2 = 1U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Fault2 = 2U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Fault2 = 3U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Fault2 = 4U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Fault2 = 4U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Fault2 = 5U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Fault2 = 6U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Fault2 = 7U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), @@ -3386,16 +3396,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Fault2 = 21U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Fault2 = 22U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Fault2 = 23U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Fault2 = 24U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Fault2 = 25U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Fault2 = 26U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Fault2 = 27U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Fault2 = 28U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Fault2 = 29U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Fault2 = 30U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Fault2 = 31U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Fault2 = 32U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Fault2 = 33U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault2 = 24U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault2 = 25U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault2 = 26U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault2 = 27U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault2 = 28U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault2 = 29U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault2 = 30U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault2 = 31U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault2 = 32U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault2 = 33U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Fault2 = 34U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Fault2 = 35U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Fault2 = 36U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), @@ -3429,7 +3439,7 @@ typedef enum _inputmux_connection_t kINPUTMUX_PinInt2ToFlexPwm1Fault3 = 1U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_SctOut4ToFlexPwm1Fault3 = 2U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_SctOut5ToFlexPwm1Fault3 = 3U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_SctOut2ToFlexPwm1Fault3 = 4U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_SctOut3ToFlexPwm1Fault3 = 4U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Ctimer0M3ToFlexPwm1Fault3 = 5U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Ctimer1M3ToFlexPwm1Fault3 = 6U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Ctimer2M3ToFlexPwm1Fault3 = 7U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), @@ -3448,16 +3458,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_Cmp0OutToFlexPwm1Fault3 = 21U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Cmp1OutToFlexPwm1Fault3 = 22U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_Cmp2OutToFlexPwm1Fault3 = 23U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig0ToFlexPwm1Fault3 = 24U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A0Trig1ToFlexPwm1Fault3 = 25U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig0ToFlexPwm1Fault3 = 26U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A1Trig1ToFlexPwm1Fault3 = 27U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig0ToFlexPwm1Fault3 = 28U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A2Trig1ToFlexPwm1Fault3 = 29U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig0ToFlexPwm1Fault3 = 30U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Pwm1A3Trig1ToFlexPwm1Fault3 = 31U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToFlexPwm1Fault3 = 32U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToFlexPwm1Fault3 = 33U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault3 = 24U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault3 = 25U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault3 = 26U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault3 = 27U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault3 = 28U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault3 = 29U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault3 = 30U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault3 = 31U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault3 = 32U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault3 = 33U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToFlexPwm1Fault3 = 34U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToFlexPwm1Fault3 = 35U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToFlexPwm1Fault3 = 36U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), @@ -3545,8 +3555,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToEvtgTrigger = 40U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToEvtgTrigger = 41U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToEvtgTrigger = 42U + (EVTG_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToEvtgTrigger = 43U + (EVTG_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToEvtgTrigger = 44U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToEvtgTrigger = 43U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToEvtgTrigger = 44U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_TrigIn0ToEvtgTrigger = 45U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_TrigIn1ToEvtgTrigger = 46U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_TrigIn2ToEvtgTrigger = 47U + (EVTG_TRIG0_REG << PMUX_SHIFT), @@ -3558,8 +3568,6 @@ typedef enum _inputmux_connection_t kINPUTMUX_SincFilterCh2ToEvtgTrigger = 53U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_SincFilterCh3ToEvtgTrigger = 54U + (EVTG_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_SincFilterCh4ToEvtgTrigger = 55U + (EVTG_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_TmprOut0ToEvtgTrigger = 56U + (EVTG_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_TmprOut1ToEvtgTrigger = 57U + (EVTG_TRIG0_REG << PMUX_SHIFT), /*!< USB-FS trigger input connections. */ kINPUTMUX_Lpflexcomm0Trig3ToUsbfsTrigger = 0U + (USBFS_TRIG_REG << PMUX_SHIFT), @@ -3592,8 +3600,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A1Trig01ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A2Trig01ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig01ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToExtTrigger = 18U + (EXT_TRIG0_REG << PMUX_SHIFT), @@ -3602,8 +3610,6 @@ typedef enum _inputmux_connection_t kINPUTMUX_EvtgOut2BToExtTrigger = 21U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut3AToExtTrigger = 22U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut3BToExtTrigger = 23U + (EXT_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_TmprOut0ToExtTrigger = 24U + (EXT_TRIG0_REG << PMUX_SHIFT), - kINPUTMUX_TmprOut1ToExtTrigger = 25U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_Lptmr0ToExtTrigger = 26U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_Lptmr1ToExtTrigger = 27U + (EXT_TRIG0_REG << PMUX_SHIFT), kINPUTMUX_SctOut0ToExtTrigger = 28U + (EXT_TRIG0_REG << PMUX_SHIFT), @@ -3667,8 +3673,8 @@ typedef enum _inputmux_connection_t kINPUTMUX_Pwm1A2Trig1ToSincFilterChTrigger = 37U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig0ToSincFilterChTrigger = 38U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), kINPUTMUX_Pwm1A3Trig1ToSincFilterChTrigger = 39U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), - kINPUTMUX_Enc0CmpPosMatchToSincFilterChTrigger = 40U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), - kINPUTMUX_Enc1CmpPosMatchToSincFilterChTrigger = 41U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToSincFilterChTrigger = 40U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToSincFilterChTrigger = 41U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0AToSincFilterChTrigger = 42U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut0BToSincFilterChTrigger = 43U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), kINPUTMUX_EvtgOut1AToSincFilterChTrigger = 44U + (SINC_FILTER_CH0_REG << PMUX_SHIFT), diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.h index a74291255f..4aeb5bd492 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_INTM_H_ -#define _FSL_INTM_H_ +#ifndef FSL_INTM_H_ +#define FSL_INTM_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief INTM driver version. */ #define FSL_INTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ +/*! @} */ /*! @brief Interrupt monitors. */ typedef enum _intm_monitor @@ -204,4 +204,4 @@ static inline bool INTM_GetStatusFlags(INTM_Type *base, intm_monitor_t intms) } /*! @} */ -#endif /* _FSL_INTM_H_*/ +#endif /* FSL_INTM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.c index 477f5145c7..de5f292bfe 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2019, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,6 +21,22 @@ #define YEAR_RANGE_START (1984U) /* Valid values for year range from -128 to 127; 2112 - 128 */ #define YEAR_RANGE_END (2239U) /* Valid values for year range from -128 to 127; 2112 + 127 */ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \ + (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET) +/*! @brief Array to map IRTC instance number to base pointer. */ +static RTC_Type *const kIrtcBases[] = RTC_BASE_PTRS; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map IRTC instance number to clock gate enum. */ +static clock_ip_name_t const kIrtcClocks[] = RTC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET +/*! @brief Pointers to IRTC resets for each instance. */ +static const reset_ip_name_t kIrtcResets[] = RTC_RSTS; +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -33,6 +49,18 @@ */ static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime); +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \ + (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET) +/*! + * @brief Returns an instance number given a base address. + * + * @param base The IRTC peripheral base address. + * @return IRTC instance number starting from 0. If cannot the base address is + * not a valid address, this function returns -1. + */ +static int32_t IRTC_GetInstance(RTC_Type *base); +#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -70,6 +98,29 @@ static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime) return fgRet; } +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \ + (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET) +static int32_t IRTC_GetInstance(RTC_Type *base) +{ + int32_t instance; + + for (instance = 0; instance < (int32_t)ARRAY_SIZE(kIrtcBases); ++instance) + { + if (kIrtcBases[instance] == base) + { + break; + } + } + + if (instance >= (int32_t)ARRAY_SIZE(kIrtcBases)) + { + instance = -1; + } + + return instance; +} +#endif + /*! * brief Ungates the IRTC clock and configures the peripheral for basic operation. * @@ -90,12 +141,21 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) uint16_t reg; status_t status = kStatus_Success; +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \ + (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET) + int32_t instance = IRTC_GetInstance(base); + if (instance < 0) + { + return kStatus_InvalidArgument; + } +#endif + #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rtc0); + CLOCK_EnableClock(kIrtcClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET - RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); + RESET_ReleasePeripheralReset(kIrtcResets[instance]); #endif /* Unlock to allow register write operation */ @@ -123,7 +183,7 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) #endif #if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT (uint16_t)RTC_CTRL_CLK_SEL_MASK | -#endif +#endif #if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (uint16_t)RTC_CTRL_CLKO_DIS_MASK | #endif @@ -149,6 +209,26 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) return status; } +/* + * brief Gate the IRTC clock + * + * param base IRTC peripheral base address + */ +status_t IRTC_Deinit(RTC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + int32_t instance = IRTC_GetInstance(base); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + CLOCK_DisableClock(kIrtcClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + return kStatus_Success; +} + /*! * brief Fill in the IRTC config struct with the default settings * @@ -172,7 +252,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config) config->wakeupSelect = true; #endif -#if !defined(FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) || (!FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) +#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) /* Sampling clock are not gated when in standby mode */ config->timerStdMask = false; #endif @@ -191,6 +271,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config) #endif } +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) /*! * brief Sets the IRTC date and time according to the given time structure. * @@ -239,6 +320,7 @@ status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime) return status; } +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ /*! * brief Gets the IRTC time and stores it in the given time structure. @@ -395,6 +477,7 @@ status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock) return status; } +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) /*! * brief Sets the IRTC daylight savings start and stop date and time. * @@ -423,6 +506,7 @@ void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime) /* Enable daylight saving time */ base->CTRL |= RTC_CTRL_DST_EN_MASK; } +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ /*! * brief Gets the IRTC daylight savings time and stores it in the given time structure. @@ -452,6 +536,7 @@ void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime) datetime->endHour = (uint8_t)((temp & RTC_DST_HOUR_DST_END_HOUR_MASK) >> RTC_DST_HOUR_DST_END_HOUR_SHIFT); } +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) /*! * brief Enables the coarse compensation and sets the value in the IRTC compensation register. * @@ -497,6 +582,7 @@ void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fra /* Enable fine compensation */ base->CTRL |= (RTC_CTRL_COMP_EN_MASK | RTC_CTRL_FINEEN_MASK); } +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) @@ -676,6 +762,8 @@ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut) ctrlVal &= (uint16_t)(~RTC_CTRL_CLKOUT_MASK); ctrlVal |= RTC_CTRL_CLKOUT((uint16_t)clkOut); + +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) if (clkOut == kIRTC_ClkoutCoarse1Hz) { ctrlVal |= RTC_CTRL_COMP_EN_MASK; @@ -688,6 +776,7 @@ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut) { /* empty else */ } +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ base->CTRL = ctrlVal; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.h index ce025033bf..da9ba42f0f 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019, 2022 NXP + * Copyright 2016-2019, 2022-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_IRTC_H_ -#define _FSL_IRTC_H_ +#ifndef FSL_IRTC_H_ +#define FSL_IRTC_H_ #include "fsl_common.h" @@ -20,9 +20,15 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version. */ -/*@}*/ +/*! @{ */ +#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*! @} */ + +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) +#define IRTC_STATUS_W1C_BITS ((uint16_t)(RTC_STATUS_BUS_ERR_MASK) | (uint16_t)(RTC_STATUS_CMP_DONE_MASK)) +#else +#define IRTC_STATUS_W1C_BITS ((uint16_t)(RTC_STATUS_BUS_ERR_MASK)) +#endif #if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT /*! @brief IRTC clock select. */ @@ -114,9 +120,11 @@ typedef enum _irtc_status_flags #if !defined(FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG) || (!FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG) kIRTC_ResetSrcFlag = (RTC_STATUS_RST_SRC_MASK << 16U), /*!< Reset source flag */ #endif +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) kIRTC_CmpIntFlag = (RTC_STATUS_CMP_INT_MASK << 16U), /*!< Compensation interval status flag */ - kIRTC_BusErrFlag = (RTC_STATUS_BUS_ERR_MASK << 16U), /*!< Bus error flag */ kIRTC_CmpDoneFlag = (RTC_STATUS_CMP_DONE_MASK << 16U), /*!< Compensation done flag */ +#endif + kIRTC_BusErrFlag = (RTC_STATUS_BUS_ERR_MASK << 16U), /*!< Bus error flag */ #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM kIRTC_WakeTimerFlag = (RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK << 28U) /*!< Wake timer status flag */ #endif @@ -131,7 +139,7 @@ typedef enum _irtc_alarm_match kRTC_MatchSecMinHrDayMnthYr = 3U /*!< Only match second, minute, hour, day, month and year */ } irtc_alarm_match_t; -#if !defined(FSL_FEATURE_RTC_HAS_NO_OSC_CAP_LOAD) || (!FSL_FEATURE_RTC_HAS_NO_OSC_CAP_LOAD) +#if !defined(FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) || (!FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) /*! @brief List of RTC Oscillator capacitor load settings */ typedef enum _irtc_osc_cap_load { @@ -205,7 +213,7 @@ typedef struct _irtc_config bool wakeupSelect; /*!< true: Tamper pin 0 is used to wakeup the chip; false: Tamper pin 0 is used as the tamper pin */ #endif -#if !defined(FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) || (!FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) +#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) bool timerStdMask; /*!< true: Sampling clocks gated in standby mode; false: Sampling clocks not gated */ #endif @@ -243,7 +251,9 @@ extern "C" { * @param base IRTC peripheral base address * @param config Pointer to user's IRTC config structure. * + * @return kStatus_Success If the driver is initialized successfully. * @return kStatus_Fail if we cannot disable register write protection + * @return kStatus_InvalidArgument If the input parameters are wrong. */ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config); @@ -251,13 +261,10 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config); * @brief Gate the IRTC clock * * @param base IRTC peripheral base address + * @return kStatus_Success If the driver is initialized successfully. + * @return kStatus_InvalidArgument If the input parameters are wrong. */ -static inline void IRTC_Deinit(RTC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} +status_t IRTC_Deinit(RTC_Type *base); /*! * @brief Fill in the IRTC config struct with the default settings @@ -279,6 +286,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config); * @{ */ +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) /*! * @brief Sets the IRTC date and time according to the given time structure. * @@ -291,6 +299,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config); * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. */ status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime); +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ /*! * @brief Gets the IRTC time and stores it in the given time structure. @@ -346,7 +355,7 @@ static inline void IRTC_EnableInterrupts(RTC_Type *base, uint32_t mask) #endif #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) + if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable)) { base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; } @@ -367,14 +376,14 @@ static inline void IRTC_DisableInterrupts(RTC_Type *base, uint32_t mask) #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM if (0U != (mask & (uint32_t)kIRTC_WakeTimerInterruptEnable)) { - base->WAKE_TIMER_CTRL &= ~RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; + base->WAKE_TIMER_CTRL &= ~(uint16_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; } #endif #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable)) + if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable)) { - base->TAMPER_QSCR &= ~RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; + base->TAMPER_QSCR &= ~(uint16_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; } #endif #endif @@ -392,11 +401,11 @@ static inline uint32_t IRTC_GetEnabledInterrupts(RTC_Type *base) { uint32_t intsEnabled = base->IER; #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM - intsEnabled |= (base->WAKE_TIMER_CTRL & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; + intsEnabled |= (base->WAKE_TIMER_CTRL & (uint32_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; #endif #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) - intsEnabled |= (base->TAMPER_QSCR & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; + intsEnabled |= (base->TAMPER_QSCR & (uint32_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; #endif #endif @@ -437,7 +446,7 @@ static inline uint32_t IRTC_GetStatusFlags(RTC_Type *base) static inline void IRTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) { base->ISR = (uint16_t)mask; - base->STATUS = (base->STATUS & ~((uint16_t)RTC_STATUS_BUS_ERR_MASK | (uint16_t)RTC_STATUS_CMP_DONE_MASK)) | + base->STATUS = (base->STATUS & ~IRTC_STATUS_W1C_BITS) | ((uint16_t)(mask >> 16U)); #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) /* TAMPER flag need clear TAMPER_SCR[TMPR_STS] filed */ @@ -541,7 +550,7 @@ static inline void IRTC_Enable32kClkDuringRegisterWrite(RTC_Type *base, bool ena * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. * * @param base IRTC peripheral base address - * @param cloOut select clock to use for output, + * @param clkOut select clock to use for output, */ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut); @@ -632,6 +641,7 @@ static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base) * @{ */ +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) /*! * @brief Sets the IRTC daylight savings start and stop date and time. * @@ -641,6 +651,7 @@ static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base) * @param datetime Pointer to a structure where the date and time details are stored. */ void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime); +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ /*! * @brief Gets the IRTC daylight savings time and stores it in the given time structure. @@ -652,6 +663,7 @@ void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime); /*! @}*/ +#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U)) /*! * @name Time Compensation Interface * @{ @@ -680,6 +692,7 @@ void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8 void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional); /*! @}*/ +#endif /* FSL_FEATURE_RTC_IS_SLAVE */ #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) @@ -756,6 +769,7 @@ static inline void IRTC_ClearTamperQueueFullStatus(RTC_Type *base) * @{ */ +#if !(defined(FSL_FEATURE_RTC_HAS_SUBSECOND) && (FSL_FEATURE_RTC_HAS_SUBSECOND == 0)) /*! * @brief Enable the RTC wake-up timer. * @@ -799,6 +813,8 @@ static inline uint32_t IRTC_GetSubsecondCount(RTC_Type *base) return b; } +#endif /* FSL_FEATURE_RTC_HAS_SUBSECOND */ + /*! * @brief Set countdown value to the RTC wake timer counter register. * @@ -849,4 +865,4 @@ static inline uint32_t IRTC_GetWakeupCount(RTC_Type *base) /*! @}*/ -#endif /* _FSL_IRTC_H_ */ +#endif /* FSL_IRTC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_itrc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_itrc.h index b2e06c1d9d..53664bb391 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_itrc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_itrc.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_ITRC_H_ -#define _FSL_ITRC_H_ +#ifndef FSL_ITRC_H_ +#define FSL_ITRC_H_ #include "fsl_common.h" @@ -21,10 +21,12 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief Defines ITRC driver version 2.2.0. +/*! @{ */ +/*! @brief Defines ITRC driver version 2.3.0. * * Change log: + * - Version 2.3.0 + * - Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM * - Version 2.2.0 * - Update driver to new version and input events * - Version 2.1.0 @@ -32,8 +34,8 @@ * - Version 2.0.0 * - initial version */ -#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ +#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*! @} */ typedef enum _itrc_input_signals { @@ -59,8 +61,8 @@ typedef enum _itrc_input_signals #if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) kITRC_Freqme = 13u, #endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK */ - kITRC_SwEvent1 = 14u, - kITRC_SwEvent2 = 15u, + kITRC_SwEvent0 = 14u, + kITRC_SwEvent1 = 15u, #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) kITRC_VddSysLow = 16u, #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK */ @@ -317,4 +319,4 @@ void ITRC_Deinit(ITRC_Type *base); /*! @}*/ /* end of group itrc */ -#endif /* _FSL_ITRC_H_ */ +#endif /* FSL_ITRC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.c index 5d0a0ef196..c22741c4f5 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -8,11 +8,47 @@ #include "fsl_lpadc.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.lpadc" #endif +#ifndef ADC_VERID_DIFFEN_MASK +#define ADC_VERID_DIFFEN_MASK (0x2U) +#endif /* ADC_VERID_DIFFEN_MASK */ + +#ifndef ADC_VERID_NUM_SEC_MASK +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#endif /* ADC_VERID_NUM_SEC_MASK */ + +#define ADC_CMDL_CHANNEL_MODE_MASK (0x60U) +#define ADC_CMDL_CHANNEL_MODE_SHIFT (5U) +#define ADC_CMDL_CHANNEL_MODE(x) \ + (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK) + +#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U) + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES +#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES +#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI +#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + +#if defined(LPADC_RSTS) +#define LPADC_RESETS_ARRAY LPADC_RSTS +#elif defined(ADC_RSTS) +#define LPADC_RESETS_ARRAY ADC_RSTS +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -23,14 +59,14 @@ */ static uint32_t LPADC_GetInstance(ADC_Type *base); -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ /*! * @brief Get gain conversion result . * * @param gainAdjustment gain adjustment value. */ static uint32_t LPADC_GetGainConvResult(float gainAdjustment); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ /******************************************************************************* * Variables @@ -41,6 +77,10 @@ static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; /*! @brief Pointers to LPADC clocks for each instance. */ static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(LPADC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpadcResets[] = LPADC_RESETS_ARRAY; +#endif /******************************************************************************* * Code @@ -50,8 +90,18 @@ static uint32_t LPADC_GetInstance(ADC_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpadcBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) { + /* + * $Branch Coverage Justification$ + * (s_lpadcBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ if (s_lpadcBases[instance] == base) { break; @@ -63,7 +113,7 @@ static uint32_t LPADC_GetInstance(ADC_Type *base) return instance; } -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) /*! * brief Get gain conversion Result . * @@ -71,27 +121,27 @@ static uint32_t LPADC_GetInstance(ADC_Type *base) */ static uint32_t LPADC_GetGainConvResult(float gainAdjustment) { - int8_t i = 0; + uint16_t i = 0U; uint32_t tmp32 = 0U; uint32_t GCRa[17] = {0}; uint32_t GCALR = 0U; - for (i = 0x10; i >= 0; i--) + for (i = 0x11U; i > 0U; i--) { - tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (0x01 << (0x10 - i))))); - GCRa[i] = tmp32; - gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (0x01 << (0x10 - i)))); + tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))))); + GCRa[i - 1U] = tmp32; + gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U))))); } /* Get GCALR value calculated */ - for (i = 0x10; i >= 0; i--) + for (i = 0x11U; i > 0U; i--) { - GCALR += GCRa[i] * (0x01 << i); + GCALR += GCRa[i - 1U] * ((uint32_t)(1UL << (uint32_t)(i - 1UL))); } /* to return GCALR value calculated */ return GCALR; } -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ /*! * brief Initializes the LPADC module. @@ -111,6 +161,10 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(LPADC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]); +#endif + /* Reset the module. */ LPADC_DoResetConfig(base); #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) @@ -155,13 +209,27 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) { tmp32 |= ADC_CFG_PWREN_MASK; } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ + tmp32 |= (ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + ); + + tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy)); + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES) + tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) + tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) + tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) - | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ - | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ base->CFG = tmp32; /* ADCx_PAUSE. */ @@ -227,9 +295,9 @@ void LPADC_GetDefaultConfig(lpadc_config_t *config) config->enableAnalogPreliminary = false; config->powerUpDelay = 0x80; config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; -#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && FSL_FEATURE_LPADC_HAS_CFG_PWRSEL +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) config->powerLevelMode = kLPADC_PowerLevelAlt1; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; config->enableConvPause = false; config->convPauseDelay = 0U; @@ -271,11 +339,11 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in { assert(result != NULL); /* Check if the input pointer is available. */ - uint32_t tmp32; + uint32_t tmp32 = 0U; tmp32 = base->RESFIFO[index]; - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) { return false; /* FIFO is empty. Discard any read from RESFIFO. */ } @@ -287,6 +355,31 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in return true; } +/*! + * brief Get the result in conversion FIFOn using blocking method. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO[index]; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} #else /*! * brief Get the result in conversion FIFO. @@ -300,22 +393,46 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) { assert(result != NULL); /* Check if the input pointer is available. */ - uint32_t tmp32; + uint32_t tmp32 = 0U; tmp32 = base->RESFIFO; - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) { return false; /* FIFO is empty. Discard any read from RESFIFO. */ } result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); return true; } +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ /*! @@ -324,7 +441,7 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) * Each programmable trigger can launch the conversion command in command buffer. * * param base LPADC peripheral base address. - * param triggerId ID for each trigger. Typically, the available value range is from 0. + * param triggerId ID for each trigger. Typically, the available value range is from 0 to 3. * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. */ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) @@ -357,12 +474,12 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_ * * This function initializes the trigger's configuration structure with an available settings. The default values are: * code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * config->channelAFIFOSelect = 0U; - * config->channelBFIFOSelect = 0U; + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; * endcode * param config Pointer to configuration structure. */ @@ -386,6 +503,9 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) /*! * brief Configure conversion command. * + * note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. + * * param base LPADC peripheral base address. * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. @@ -400,36 +520,35 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH tmp32 |= ADC_CMDL_ALTB_ADCH(config->channelBNumber); /* Alternate channel B number. */ #endif #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE tmp32 |= ADC_CMDL_ALTB_CSCALE(config->channelBScaleMode); /* Alternate channel B full/Part scale input voltage. */ #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); -#else - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; + +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ + assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + assert(((config->sampleChannelMode == kLPADC_SampleChannelDiffBothSide) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) && + (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + + tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode); + #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ @@ -455,7 +574,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ { tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ } -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ if (config->enableAutoChannelIncrement) { @@ -465,16 +584,15 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ /* Hardware compare settings. * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. + * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be + * made before setting the CV register. */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); + if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT)) + { /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ + base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */ } } @@ -486,10 +604,10 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ * code * config->sampleScaleMode = kLPADC_SampleFullScale; * config->channelBScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; * config->channelNumber = 0U; - * config ->alternateChannelNumber = 0U; - * config->chainedNextCmdNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; * config->enableAutoChannelIncrement = false; * config->loopCount = 0U; * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; @@ -534,7 +652,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG config->enableWaitTrigger = false; -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN config->enableChannelB = false; /* Enable alternate channel B.*/ #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ @@ -622,8 +740,8 @@ void LPADC_DoAutoCalibration(ADC_Type *base) base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ } -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS /*! @@ -647,8 +765,35 @@ void LPADC_DoOffsetCalibration(ADC_Type *base) */ void LPADC_DoAutoCalibration(ADC_Type *base) { - assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); + LPADC_PrepareAutoCalibration(base); + LPADC_FinishAutoCalibration(base); +} +/*! + * brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base) +{ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + assert((0U == LPADC_GetConvResultCount(base, 0)) && (0U == LPADC_GetConvResultCount(base, 1))); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ + assert(LPADC_GetConvResultCount(base) == 0U); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; +} + +/*! + * brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base) +{ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE int32_t GCCa; int32_t GCCb; @@ -656,53 +801,177 @@ void LPADC_DoAutoCalibration(ADC_Type *base) float GCRb; #else uint32_t GCCa; + float GCRa; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) uint32_t GCCb; - uint32_t GCRa; - uint32_t GCRb; + float GCRb; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ - /* Request gain calibration. */ - base->CTRL |= ADC_CTRL_CAL_REQ_MASK; - while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || - (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + || (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)) +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + ) { } - /* Calculate gain offset. */ - GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); - GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); - #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE - if (((base->GCC[0]) & 0x8000U)) + GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + if (0U != ((base->GCC[0]) & 0x8000U)) { - GCCa = GCCa - 0x10000; - GCRa = - (float)((131072.0) / (0x20000 - GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + GCCa = GCCa - 0x10000; + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ } - if (((base->GCC[1]) & 0x8000U)) + if (0U != ((base->GCC[1]) & 0x8000U)) { - GCCb = GCCb - 0x10000; - GCRb = - (float)((131072.0) / (0x20000 - GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + GCCb = GCCb - 0x10000; + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ } #else - GCRa = (uint16_t)((GCCa << 16U) / - (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ - GCRb = (uint16_t)((GCCb << 16U) / - (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ - base->GCR[0] = ADC_GCR_GCALR(GCRa); - base->GCR[1] = ADC_GCR_GCALR(GCRb); + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ /* Indicate the values are valid. */ base->GCR[0] |= ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) base->GCR[1] |= ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) { } } #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +/*! + * brief Get calibration value into the memory which is defined by invoker. + * + * note Please note the ADC will be disabled temporary. + * note This function should be used after finish calibration. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure, this memory block should be always powered + * on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + uint32_t i; + for (i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR0))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR0))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#else + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +/*! + * brief Set calibration value into ADC calibration registers. + * + * note Please note the ADC will be disabled temporary. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure which contains ADC's calibration value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + for (uint32_t i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + *(((volatile uint32_t *)(&(base->CAL_GAR0))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR0))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#else + *(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + /* + * $Branch Coverage Justification$ + * while ((base->STAT & ADC_STAT_CAL_RDY_MASK) == ADC_STAT_CAL_RDY_MASK) not covered. Test unfeasible, + * the calibration ready state is too short not to catch. + */ + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.h index b251ac731b..e0d2f4b6ee 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ +#ifndef FSL_LPADC_H_ +#define FSL_LPADC_H_ #include "fsl_common.h" @@ -22,10 +22,21 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.6.0. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) -/*@}*/ +/*! @{ */ +/*! @brief LPADC driver version 2.8.4. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) +/*! @} */ + +#if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1)) +#define ADC_OFSTRIM_OFSTRIM_MAX (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_SIGN ((ADC_OFSTRIM_OFSTRIM_MAX + 1U) >> 1U) + +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2)) +#define ADC_OFSTRIM_OFSTRIM_A_MAX (ADC_OFSTRIM_OFSTRIM_A_MASK >> ADC_OFSTRIM_OFSTRIM_A_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_B_MAX (ADC_OFSTRIM_OFSTRIM_B_MASK >> ADC_OFSTRIM_OFSTRIM_B_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_A_SIGN ((ADC_OFSTRIM_OFSTRIM_A_MAX + 1U) >> 1U) +#define ADC_OFSTRIM_OFSTRIM_B_SIGN ((ADC_OFSTRIM_OFSTRIM_B_MAX + 1U) >> 1U) +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ /*! * @brief Define the MACRO function to get command status from status value. @@ -41,7 +52,39 @@ */ #define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/* Map macros to the unified name. */ +#if !defined(ADC_STAT_FOF0_MASK) +#ifdef ADC_STAT_FOF_MASK +#define ADC_STAT_FOF0_MASK ADC_STAT_FOF_MASK +#else +#error "ADC_STAT_FOF0_MASK not defined" +#endif /* ifdef(ADC_STAT_FOF_MASK) */ +#endif /* !defined(ADC_STAT_FOF0_MASK) */ + +#if !defined(ADC_STAT_RDY0_MASK) +#ifdef ADC_STAT_RDY_MASK +#define ADC_STAT_RDY0_MASK ADC_STAT_RDY_MASK +#else +#error "ADC_STAT_RDY0_MASK not defined" +#endif /* ifdef ADC_STAT_RDY_MASK */ +#endif /* !defined(ADC_STAT_RDY0_MASK) */ + +#if !defined(ADC_IE_FOFIE0_MASK) +#ifdef ADC_IE_FOFIE_MASK +#define ADC_IE_FOFIE0_MASK ADC_IE_FOFIE_MASK +#else +#error "ADC_IE_FOFIE0_MASK not defined" +#endif /* ifdef ADC_IE_FOFIE_MASK */ +#endif /* !defined(ADC_IE_FOFIE0_MASK) */ + +#if !defined(ADC_IE_FWMIE0_MASK) +#ifdef ADC_IE_FWMIE_MASK +#define ADC_IE_FWMIE0_MASK ADC_IE_FWMIE_MASK +#else +#error "ADC_IE_FWMIE0_MASK not defined" +#endif /* ifdef ADC_IE_FWMIE_MASK */ +#endif /* !defined(ADC_IE_FWMIE0_MASK) */ + /*! * @brief Define hardware flags of the module. */ @@ -51,14 +94,45 @@ enum _lpadc_status_flags FIFO 0 than it can hold. */ kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result FIFO 1 than it can hold. */ kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result FIFO 1 is greater than the setting watermark level. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) + kLPADC_TriggerExceptionFlag = ADC_STAT_TEXC_INT_MASK, /*!< Indicates that a trigger exception event has occurred. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) + kLPADC_TriggerCompletionFlag = ADC_STAT_TCOMP_INT_MASK, /*!< Indicates that a trigger completion event has occurred. + */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) + kLPADC_CalibrationReadyFlag = ADC_STAT_CAL_RDY_MASK, /*!< Indicates that the calibration process is done. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) + kLPADC_ActiveFlag = ADC_STAT_ADC_ACTIVE_MASK, /*!< Indicates that the ADC is in active state. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) */ + + kLPADC_ResultFIFOOverflowFlag = kLPADC_ResultFIFO0OverflowFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0OverflowFlag as instead. */ + + kLPADC_ResultFIFOReadyFlag = kLPADC_ResultFIFO0ReadyFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0ReadyFlag as instead. */ }; /*! * @brief Define interrupt switchers of the module. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. */ enum _lpadc_interrupt_enable { @@ -66,13 +140,30 @@ enum _lpadc_interrupt_enable requests when FOF0 flag is asserted. */ kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFOOverflowInterruptEnable = kLPADC_ResultFIFO0OverflowInterruptEnable, /*!< To compilitable with old + version, do not recommend using this, + please use + #kLPADC_ResultFIFO0OverflowInterruptEnable + as instead. */ + kLPADC_FIFOWatermarkInterruptEnable = kLPADC_FIFO0WatermarkInterruptEnable, /*!< To compilitable with old version, + do not recommend using this, please + use + #kLPADC_FIFO0WatermarkInterruptEnable + as instead. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt requests when FOF1 flag is asserted. */ kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception interrupt. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt when trigger 0 completion. */ kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt @@ -105,35 +196,15 @@ enum _lpadc_interrupt_enable when trigger 14 completion. */ kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ }; -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) /*! * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. */ enum _lpadc_trigger_status_flags { @@ -154,40 +225,40 @@ enum _lpadc_trigger_status_flags kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ }; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) */ /*! * @brief Define enumeration of sample scale mode. @@ -199,8 +270,8 @@ enum _lpadc_trigger_status_flags */ typedef enum _lpadc_sample_scale_mode { - kLPADC_SamplePartScale = - 0U, /*!< Use divided input voltage signal. (For scale select,please refer to the reference manual). */ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. + (For scale select,please refer to the reference manual). */ kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ } lpadc_sample_scale_mode_t; @@ -211,16 +282,19 @@ typedef enum _lpadc_sample_scale_mode */ typedef enum _lpadc_sample_channel_mode { - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ + kLPADC_SampleChannelSingleEndSideA = 0x0U, /*!< Single-end mode, only A-side channel is converted. */ +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + kLPADC_SampleChannelSingleEndSideB = 0x1U, /*!< Single-end mode, only B-side channel is converted. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif + kLPADC_SampleChannelDiffBothSideAB = 0x2U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side + channels are converted independently. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ } lpadc_sample_channel_mode_t; /*! @@ -228,6 +302,9 @@ typedef enum _lpadc_sample_channel_mode * * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to * capture temporary results while the averaging iterations are executed. + * + * @note Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH + * register. */ typedef enum _lpadc_hardware_average_mode { @@ -240,11 +317,12 @@ typedef enum _lpadc_hardware_average_mode kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ - (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4)) + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) kLPADC_HardwareAverageCount256 = 8U, /*!< 256 conversions averaged. */ kLPADC_HardwareAverageCount512 = 9U, /*!< 512 conversions averaged. */ kLPADC_HardwareAverageCount1024 = 10U, /*!< 1024 conversions averaged. */ -#endif /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ } lpadc_hardware_average_mode_t; /*! @@ -294,13 +372,15 @@ typedef enum _lpadc_conversion_resolution_mode kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. */ } lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE */ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS /*! * @brief Define enumeration of conversion averages mode. * * Configure the converion average number for auto-calibration. + * @note Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL + * register. */ typedef enum _lpadc_conversion_average_mode { @@ -313,13 +393,14 @@ typedef enum _lpadc_conversion_average_mode kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ - (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4)) + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) kLPADC_ConversionAverage256 = 8U, /*!< 256 conversions averaged. */ kLPADC_ConversionAverage512 = 9U, /*!< 512 conversions averaged. */ kLPADC_ConversionAverage1024 = 10U, /*!< 1024 conversions averaged. */ -#endif /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ } lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ /*! * @brief Define enumeration of reference voltage source. @@ -357,29 +438,111 @@ typedef enum _lpadc_offset_calibration_mode kLPADC_OffsetCalibration12bitMode = 0U, /*!< 12 bit offset calibration mode. */ kLPADC_OffsetCalibration16bitMode = 1U, /*!< 16 bit offset calibration mode. */ } lpadc_offset_calibration_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ /*! * @brief Define enumeration of trigger priority policy. * * This selection controls how higher priority triggers are handled. + * @note \b kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of + * TPRICTRL field in CFG register. */ typedef enum _lpadc_trigger_priority_policy { - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command + kLPADC_ConvPreemptImmediatelyNotAutoResumed = 0x0U, /*!< If a higher priority trigger is detected during command processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion is not + automatically resumed or restarted. */ + kLPADC_ConvPreemptSoftlyNotAutoResumed = 0x1U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion is not + resumed or restarted. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptImmediatelyAutoRestarted = 0x4U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be restarted. */ + kLPADC_ConvPreemptSoftlyAutoRestarted = 0x5U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + automatically be restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptImmediatelyAutoResumed = 0xCU, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be resumed. */ + kLPADC_ConvPreemptSoftlyAutoResumed = 0xDU, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + be automatically be resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptImmediately = + kLPADC_ConvPreemptImmediatelyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ + kLPADC_TriggerPriorityPreemptSoftly = + kLPADC_ConvPreemptSoftlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures compatibility + with older versions. */ + +#if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) + kLPADC_ConvPreemptSubsequentlyNotAutoResumed = 0x2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + not automatically be restarted or resumed. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptSubsequentlyAutoRestarted = 0x6U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptSubsequentlyAutoResumed = 0xEU, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptSubsequently = + kLPADC_ConvPreemptSubsequentlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI + kLPADC_TriggerPriorityExceptionDisabled = 0x10U, /*!< High priority trigger exception disabled. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ } lpadc_trigger_priority_policy_t; +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Define enumeration of tune value. + */ +typedef enum _lpadc_tune_value +{ + kLPADC_TuneValue0 = 0U, /*!< Tune value 0. */ + kLPADC_TuneValue1 = 1U, /*!< Tune value 1. */ + kLPADC_TuneValue2 = 2U, /*!< Tune value 2. */ + kLPADC_TuneValue3 = 3U, /*!< Tune value 3. */ +} lpadc_tune_value_t; +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + /*! * @brief LPADC global configuration. * @@ -388,9 +551,9 @@ typedef enum _lpadc_trigger_priority_policy typedef struct { #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ #if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". If voltage reference option1 input is above 1.8V, it should be "false". */ @@ -412,9 +575,9 @@ typedef struct lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for conversions.*/ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to lpadc_trigger_priority_policy_t. */ bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during @@ -437,7 +600,10 @@ typedef struct uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored in the ADC Result FIFO is greater than the value in this field, the ready flag would be asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) + +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ } lpadc_config_t; /*! @@ -446,15 +612,15 @@ typedef struct typedef struct { #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE lpadc_sample_scale_mode_t channelBScaleMode; /*!< Alternate channe B Scale mode. */ #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH - uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ + uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ #endif uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. 1-15 is available, 0 is to terminate the chain after this command. */ @@ -479,8 +645,8 @@ typedef struct executing this command. */ #endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN - bool enableChannelB; /*! Enable alternate Channel B */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ + bool enableChannelB; /*! Enable alternate Channel B */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ } lpadc_conv_command_config_t; /*! @@ -516,6 +682,27 @@ typedef struct uint16_t convValue; /*!< Data result. */ } lpadc_conv_result_t; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * @brief A structure of calibration value. + */ +typedef struct _lpadc_calibration_value +{ + /* gain calibration result. */ + uint16_t gainCalibrationResultA; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + uint16_t gainCalibrationResultB; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + /* general calibration value. */ + uint16_t generalCalibrationValueA[33U]; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + uint16_t generalCalibrationValueB[33U]; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +} lpadc_calibration_value_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + #if defined(__cplusplus) extern "C" { #endif @@ -601,6 +788,10 @@ static inline void LPADC_DoResetFIFO1(ADC_Type *base) base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; } #else + +#if defined(ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#endif /* defined(ADC_CTRL_RSTFIFO0_MASK) */ /*! * @brief Do reset the conversion FIFO. * @@ -625,7 +816,7 @@ static inline void LPADC_DoResetConfig(ADC_Type *base) base->CTRL &= ~ADC_CTRL_RST_MASK; } -/* @} */ +/*! @} */ /*! * @name Status @@ -678,11 +869,14 @@ static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) */ static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) { + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert(((mask & 0xFFFFU) == (mask & ADC_TSTAT_TEXC_NUM_MASK)) && + ((mask & 0xFFFF0000U) == (mask & ADC_TSTAT_TCOMP_FLAG_MASK))); base->TSTAT = mask; } -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */ -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -697,6 +891,10 @@ static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) */ static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) { +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ base->IE |= mask; } @@ -708,6 +906,10 @@ static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) */ static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) { +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ base->IE &= ~mask; } @@ -753,6 +955,9 @@ static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) } } #else +#if defined(ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#endif /* defined(ADC_DE_FWMDE0_MASK) */ /*! * @brief Switch on/off the DMA trigger for FIFO watermark event. * @@ -770,8 +975,8 @@ static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) base->DE &= ~ADC_DE_FWMDE_MASK; } } -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ +/*! @} */ /*! * @name Trigger and conversion with FIFO. @@ -792,16 +997,25 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) } /*! - * brief Get the result in conversion FIFOn. + * @brief Get the result in conversion FIFOn. * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. * - * return Status whether FIFOn entry is valid. + * @return Status whether FIFOn entry is valid. */ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else + +/*! + * @brief Get the result in conversion FIFOn using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ /*! * @brief Get the count of result kept in conversion FIFO. * @@ -822,7 +1036,15 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) * @return Status whether FIFO entry is valid. */ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ /*! * @brief Configure the conversion trigger source. @@ -840,10 +1062,12 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_ * * This function initializes the trigger's configuration structure with an available settings. The default values are: * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; * @endcode * @param config Pointer to configuration structure. */ @@ -883,10 +1107,13 @@ static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, u base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK; } } -#endif /* FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ +#endif /* defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ /*! * @brief Configure conversion command. + + * @note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. * * @param base LPADC peripheral base address. * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. @@ -902,9 +1129,10 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ * @code * config->sampleScaleMode = kLPADC_SampleFullScale; * config->channelBScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; * config->enableAutoChannelIncrement = false; * config->loopCount = 0U; * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; @@ -960,11 +1188,48 @@ static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) * @param base LPADC peripheral base address. */ void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +#if defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1U) +/*! + * @brief Set trim value for offset. + * + * @note For 16-bit conversions, each increment is 1/2 LSB resulting in a programmable offset range of -256 LSB to 255.5 + * LSB; For 12-bit conversions, each increment is 1/32 LSB resulting in a programmable offset range of -16 LSB to + * 15.96875 LSB. + * + * @param base LPADC peripheral base address. + * @param value Offset trim value, is a 10-bit signed value between -512 and 511. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value); +} + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValue Pointer to the variable in type of int16_t to store offset value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue) +{ + assert(pValue != NULL); + + uint16_t ofstrim = (uint16_t)((base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_MASK)) >> ADC_OFSTRIM_OFSTRIM_SHIFT); + + if ((ofstrim & ADC_OFSTRIM_OFSTRIM_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrim |= (uint16_t)(~ADC_OFSTRIM_OFSTRIM_MAX); + } + + *pValue = (int16_t)ofstrim; +} +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2U)) /*! * @brief Set proper offset value to trim ADC. * @@ -975,11 +1240,42 @@ void LPADC_DoAutoCalibration(ADC_Type *base); * @param valueB Setting offset value B. * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB) { base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); } -#else + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValueA Pointer to the variable in type of int32_t to store offset A value. + * @param pValueB Pointer to the variable in type of int32_t to store offset B value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int32_t *pValueA, int32_t *pValueB) +{ + assert(pValueA != NULL); + assert(pValueB != NULL); + + uint32_t ofstrimA = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_A_MASK)) >> ADC_OFSTRIM_OFSTRIM_A_SHIFT; + uint32_t ofstrimB = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_B_MASK)) >> ADC_OFSTRIM_OFSTRIM_B_SHIFT; + + if ((ofstrimA & ADC_OFSTRIM_OFSTRIM_A_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimA |= (~ADC_OFSTRIM_OFSTRIM_A_MAX); + } + if ((ofstrimB & ADC_OFSTRIM_OFSTRIM_B_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimB |= (~ADC_OFSTRIM_OFSTRIM_B_MAX); + } + + *pValueA = (int32_t)ofstrimA; + *pValueB = (int32_t)ofstrimB; +} +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ +#else /* !(defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM) */ /*! * @brief Set proper offset value to trim 12 bit ADC conversion. * @@ -1040,7 +1336,7 @@ static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_c base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode); } -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ /*! * @brief Do offset calibration. @@ -1051,15 +1347,178 @@ void LPADC_DoOffsetCalibration(ADC_Type *base); #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ /*! - * brief Do auto calibration. + * @brief Do auto calibration. * - * param base LPADC peripheral base address. + * @param base LPADC peripheral base address. */ void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ -/* @} */ +/*! + * @brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * @param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base); + +/*! + * @brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base); + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * @brief Get calibration value into the memory which is defined by invoker. + * + * @note Please note the ADC will be disabled temporary. + * @note This function should be used after finish calibration. + * + * @param base LPADC peripheral base address. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure, this memory block should be always + * powered on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue); + +/*! + * @brief Set calibration value into ADC calibration registers. + * + * @note Please note the ADC will be disabled temporary. + * + * @param base LPADC peripheral base address. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure which contains ADC's calibration + * value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue); + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Request high speed mode trim calculation. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_RequestHighSpeedModeTrim(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_CALHS_MASK; +} + +/*! + * @brief Get high speed mode trim value, the result is a 5-bit signed value between -16 and 15. + * + * @note The high speed mode trim value is used to minimize offset for high speed conversion. + * + * @param base LPADC peripheral base address. + * @return The calculated high speed mode trim value. + */ +static inline int8_t LPADC_GetHighSpeedTrimValue(ADC_Type *base) +{ + return (int8_t)(base->HSTRIM); +} + +/*! + * @brief Set high speed mode trim value. + * + * @note If is possible to set the trim value manually, but it is recommended to use the LPADC_RequestHighSpeedModeTrim. + * + * @param base LPADC peripheral base address. + * @param trimValue The trim value to be set. + */ +static inline void LPADC_SetHighSpeedTrimValue(ADC_Type *base, int8_t trimValue) +{ + base->HSTRIM = ADC_HSTRIM_HSTRIM(trimValue); +} + +/*! + * @brief Enable/disable high speed conversion mode, if enabled conversions complete 2 or 3 ADCK cycles sooner compared + * to conversion cycle counts when high speed mode is disabled. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable high speed conversion mode: + * - \b true Enable high speed conversion mode; + * - \b false Disable high speed conversion mode. + */ +static inline void LPADC_EnableHighSpeedConversionMode(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HS_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HS_MASK; + } +} + +/*! + * @brief Enable/disable an additional ADCK cycle to conversion. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable an additional ADCK cycle to conversion: + * - \b true Enable an additional ADCK cycle to conversion; + * - \b false Disable an additional ADCK cycle to conversion. + */ +static inline void LPADC_EnableExtraCycle(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HSEXTRA_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HSEXTRA_MASK; + } +} + +/*! + * @brief Set tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @param tuneValue The tune value to be set, please refer to @ref lpadc_tune_value_t. + */ +static inline void LPADC_SetTuneValue(ADC_Type *base, lpadc_tune_value_t tuneValue) +{ + base->CFG2 = (base->CFG2 & ~ADC_CFG2_TUNE_MASK) | ADC_CFG2_TUNE(tuneValue); +} + +/*! + * @brief Get tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @return The tune value, please refer to @ref lpadc_tune_value_t. + */ +static inline lpadc_tune_value_t LPADC_GetTuneValue(ADC_Type *base) +{ + return (lpadc_tune_value_t)((base->CFG2 & ADC_CFG2_TUNE_MASK) >> ADC_CFG2_TUNE_SHIFT); +} +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) +/*! + * @brief Enable/disable left-justify format in 12-bit single-end mode. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable left-justify format in 12-bit single-end mode: + * - \b true Enable left-justify format in 12-bit single-end mode; + * - \b false Disable left-justify format in 12-bit single-end mode. + */ +static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_JLEFT_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_JLEFT_MASK; + } +} +#endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */ + +/*! @} */ #if defined(__cplusplus) } @@ -1067,4 +1526,4 @@ void LPADC_DoAutoCalibration(ADC_Type *base); /*! * @} */ -#endif /* _FSL_LPADC_H_ */ +#endif /* FSL_LPADC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.c index c81a194286..4ed2d921db 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2019, 2023 NXP * All rights reserved. * * @@ -9,11 +9,18 @@ #include "fsl_lpcmp.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.lpcmp" #endif +#if defined(LPCMP_RSTS) +#define LPCMP_RESETS_ARRAY LPCMP_RSTS +#endif + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -39,6 +46,11 @@ static const clock_ip_name_t s_lpcmpClocks[] = LPCMP_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* LPCMP_CLOCKS */ +#if defined(LPCMP_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpcmpResets[] = LPCMP_RESETS_ARRAY; +#endif + /******************************************************************************* * Codes ******************************************************************************/ @@ -48,8 +60,18 @@ static uint32_t LPCMP_GetInstance(LPCMP_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpcmpBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ for (instance = 0; instance < ARRAY_SIZE(s_lpcmpBases); instance++) { + /* + * $Branch Coverage Justification$ + * (s_lpcmpBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ if (s_lpcmpBases[instance] == base) { break; @@ -88,19 +110,37 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* LPCMP_CLOCKS */ +#if defined(LPCMP_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpcmpResets[LPCMP_GetInstance(base)]); +#endif + /* Configure. */ LPCMP_Enable(base, false); + +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) /* CCR0 register. */ - if (config->enableStopMode) +#if defined(FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn) + if (1U == FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(base)) +#endif /* FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn */ { - base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; - } - else - { - base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; + if (config->enableStopMode) + { + base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; + } + else + { + base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; + } } +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + /* CCR1 register. */ - tmp32 = base->CCR1 & ~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK); + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + | LPCMP_CCR1_FUNC_CLK_SEL_MASK +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + ))); + if (config->enableOutputPin) { tmp32 |= LPCMP_CCR1_COUT_PEN_MASK; @@ -113,6 +153,9 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) { tmp32 |= LPCMP_CCR1_COUT_INV_MASK; } +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + tmp32 |= LPCMP_CCR1_FUNC_CLK_SEL(config->functionalSourceClock); +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ base->CCR1 = tmp32; /* CCR2 register. */ tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MASK); @@ -159,6 +202,7 @@ void LPCMP_Deinit(LPCMP_Type *base) * config->enableInvertOutput = false; * config->hysteresisMode = kLPCMP_HysteresisLevel0; * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; * endcode * param config Pointer to "lpcmp_config_t" structure. */ @@ -166,13 +210,17 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config) { /* Initializes the configure structure to zero. */ (void)memset(config, 0, sizeof(*config)); - - config->enableStopMode = false; +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + config->enableStopMode = false; +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ config->enableOutputPin = false; config->useUnfilteredOutput = false; config->enableInvertOutput = false; config->hysteresisMode = kLPCMP_HysteresisLevel0; config->powerMode = kLPCMP_LowSpeedPowerMode; +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + config->functionalSourceClock = kLPCMP_FunctionalClockSource0; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ } /*! @@ -180,8 +228,8 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config) * is selected for the negative and positive mux. * * param base LPCMP peripheral base address. - * param positiveChannel Positive side input channel number. Available range is 0-7. - * param negativeChannel Negative side input channel number. Available range is 0-7. + * param positiveChannel Positive side input channel number. + * param negativeChannel Negative side input channel number. */ void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) { @@ -237,3 +285,88 @@ void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config) } base->DCR = tmp32; } + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUTA_CFG_MASK | LPCMP_CCR1_EVT_SEL_CFG_MASK | LPCMP_CCR1_WINDOW_INV_MASK))); + + if (config->enableInvertWindowSignal) + { + tmp32 |= LPCMP_CCR1_WINDOW_INV_MASK; + } + + /* Set COUT event, which can close the active window in window mode. */ + tmp32 |= LPCMP_CCR1_EVT_SEL_CFG(config->closeWindowEvent); + + /* Set the COUTA signal value when the window is closed. */ + tmp32 |= LPCMP_CCR1_COUTA_CFG(config->COUTASignal); + + base->CCR1 = tmp32; +} +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + /* LPCMPx_RRCR0 register, Configuration options for the round-robin operation. */ + tmp32 = (base->RRCR0 & + (~(LPCMP_RRCR0_RR_TRG_SEL_MASK | LPCMP_RRCR0_RR_NSAM_MASK | LPCMP_RRCR0_RR_CLK_SEL_MASK | + LPCMP_RRCR0_RR_INITMOD_MASK | LPCMP_RRCR0_RR_SAMPLE_CNT_MASK | LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK))); + + tmp32 |= + (LPCMP_RRCR0_RR_TRG_SEL(config->roundrobinTriggerSource) | LPCMP_RRCR0_RR_NSAM(config->sampleClockNumbers) | + LPCMP_RRCR0_RR_CLK_SEL(config->roundrobinClockSource) | LPCMP_RRCR0_RR_INITMOD(config->initDelayModules) | + LPCMP_RRCR0_RR_SAMPLE_CNT(config->channelSampleNumbers) | + LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(config->sampleTimeThreshhold)); + + base->RRCR0 = tmp32; + + /* LPCMPx_RRCR1 register, Configure the fix port, fix channel and checker channel. */ + tmp32 = + (base->RRCR1 & (~(LPCMP_RRCR1_FIXP_MASK | LPCMP_RRCR1_FIXCH_MASK | (0xFFUL << LPCMP_RRCR1_RR_CH0EN_SHIFT)))); + tmp32 |= (LPCMP_RRCR1_FIXP(config->fixedMuxPort) | LPCMP_RRCR1_FIXCH(config->fixedChannel) | + ((uint32_t)(config->checkerChannelMask) << LPCMP_RRCR1_RR_CH0EN_SHIFT)); + + base->RRCR1 = tmp32; +} + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value) +{ + uint32_t tmp32 = 0UL; + + tmp32 = (base->RRCR2 & (~LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)); + tmp32 |= LPCMP_RRCR2_RR_TIMER_RELOAD(value); + + base->RRCR2 = tmp32; +} + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.h index e4ef16218a..5105c98fcc 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.h @@ -1,14 +1,14 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP + * Copyright 2016-2020, 2023-2024 NXP * All rights reserved. * * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPCMP_H_ -#define _FSL_LPCMP_H_ +#ifndef FSL_LPCMP_H_ +#define FSL_LPCMP_H_ #include "fsl_common.h" @@ -20,22 +20,35 @@ /******************************************************************************* * Definitions ******************************************************************************/ - /*! @name Driver version */ -/*@{*/ -/*! @brief LPCMP driver version 2.0.3. */ -#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) -/*@}*/ +/*! @{ */ +/*! @brief LPCMP driver version 2.1.3. */ +#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*! @} */ + +#define LPCMP_CCR1_COUTA_CFG_MASK (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK) +#define LPCMP_CCR1_COUTA_CFG_SHIFT LPCMP_CCR1_COUTA_OWEN_SHIFT +#define LPCMP_CCR1_COUTA_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_CFG_SHIFT)) & LPCMP_CCR1_COUTA_CFG_MASK) + +#define LPCMP_CCR1_EVT_SEL_CFG_MASK (LPCMP_CCR1_EVT_SEL_MASK | LPCMP_CCR1_WINDOW_CLS_MASK) +#define LPCMP_CCR1_EVT_SEL_CFG_SHIFT LPCMP_CCR1_WINDOW_CLS_SHIFT +#define LPCMP_CCR1_EVT_SEL_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_CFG_SHIFT)) & LPCMP_CCR1_EVT_SEL_CFG_MASK) /*! * @brief LPCMP status falgs mask. */ enum _lpcmp_status_flags { - kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ - kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ - kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. - The flag does not support W1C. */ + kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CSR_RRF) && FSL_FEATURE_LPCMP_HAS_CSR_RRF + kLPCMP_OutputRoundRobinEventFlag = LPCMP_CSR_RRF_MASK, /*!< Detects when any channel's last comparison result is + different from the pre-set value in trigger mode. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CSR_RRF */ + kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. + The flag does not support W1C. */ }; /*! @@ -45,7 +58,12 @@ enum _lpcmp_interrupt_enable { kLPCMP_OutputRisingInterruptEnable = LPCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ kLPCMP_OutputFallingInterruptEnable = LPCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ +#if defined(FSL_FEATURE_LPCMP_HAS_IER_RRF_IE) && FSL_FEATURE_LPCMP_HAS_IER_RRF_IE + kLPCMP_RoundRobinInterruptEnable = LPCMP_IER_RRF_IE_MASK, /*!< Comparator round robin mode interrupt + occurred when the comparison result changes for a given channel. */ +#endif /* FSL_FEATURE_LPCMP_HAS_IER_RRF_IE */ }; + /*! * @brief LPCMP hysteresis mode. See chip data sheet to get the actual hystersis * value with each level @@ -77,6 +95,79 @@ typedef enum _lpcmp_dac_reference_voltage_source kLPCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ } lpcmp_dac_reference_voltage_source_t; +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL +/*! + * @brief LPCMP functional mode clock source selection. + * + * Note: In different devices, the functional mode clock source selection is different, + * please refer to specific device Reference Manual for details. + */ +typedef enum _lpcmp_functional_source_clock +{ + kLPCMP_FunctionalClockSource0 = 0U, /*!< Select functional mode clock source0. */ + kLPCMP_FunctionalClockSource1 = 1U, /*!< Select functional mode clock source1. */ + kLPCMP_FunctionalClockSource2 = 2U, /*!< Select functional mode clock source2. */ + kLPCMP_FunctionalClockSource3 = 3U, /*!< Select functional mode clock source3. */ +} lpcmp_functional_source_clock_t; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Set the COUTA signal value when the window is closed. + */ +typedef enum _lpcmp_couta_signal +{ + kLPCMP_COUTASignalNoSet = 0U, /*!< NO set the COUTA signal value when the window is closed. */ + kLPCMP_COUTASignalLow = 1U, /*!< Set COUTA signal low(0) when the window is closed. */ + kLPCMP_COUTASignalHigh = 3U, /*!< Set COUTA signal high(1) when the window is closed. */ +} lpcmp_couta_signal_t; + +/*! + * @brief Set COUT event, which can close the active window in window mode. + */ +typedef enum _lpcmp_close_window_event +{ + kLPCMP_CLoseWindowEventNoSet = 0U, /*!< No Set COUT event, which can close the active window in window mode. */ + kLPCMP_CloseWindowEventRisingEdge = 1U, /*!< Set rising edge COUT signal as COUT event. */ + kLPCMP_CloseWindowEventFallingEdge = 3U, /*!< Set falling edge COUT signal as COUT event. */ + kLPCMP_CLoseWindowEventBothEdge = 5U, /*!< Set both rising and falling edge COUT signal as COUT event. */ +} lpcmp_close_window_event_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief LPCMP round robin mode fixed mux port. + */ +typedef enum _lpcmp_roundrobin_fixedmuxport +{ + kLPCMP_FixedPlusMuxPort = 0U, /*!< Fixed plus mux port. */ + kLPCMP_FixedMinusMuxPort = 1U, /*!< Fixed minus mux port. */ +} lpcmp_roundrobin_fixedmuxport_t; + +/*! + * @brief LPCMP round robin mode clock source selection. + * + * Note: In different devices,the round robin mode clock source selection is different, + * please refer to the specific device Reference Manual for details. + */ +typedef enum _lpcmp_roundrobin_clock_source +{ + kLPCMP_RoundRobinClockSource0 = 0U, /*!< Select roundrobin mode clock source0. */ + kLPCMP_RoundRobinClockSource1 = 1U, /*!< Select roundrobin mode clock source1. */ + kLPCMP_RoundRobinClockSource2 = 2U, /*!< Select roundrobin mode clock source2. */ + kLPCMP_RoundRobinClockSource3 = 3U, /*!< Select roundrobin mode clock source3. */ +} lpcmp_roundrobin_clock_source_t; + +/*! + * @brief LPCMP round robin mode trigger source. + */ +typedef enum _lpcmp_roundrobin_trigger_source +{ + kLPCMP_TriggerSourceExternally = 0U, /*!< Select external trigger source. */ + kLPCMP_TriggerSourceInternally = 1U, /*!< Select internal trigger source. */ +} lpcmp_roundrobin_trigger_source_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + /*! * @brief Configure the filter. */ @@ -85,8 +176,8 @@ typedef struct _lpcmp_filter_config bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The - sampling clock must be at least 4 times slower than the system clock to the comparator. - So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ + sampling clock must be at least 4 times slower than the system clock to the comparator. + So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ } lpcmp_filter_config_t; /*! @@ -96,7 +187,8 @@ typedef struct _lpcmp_dac_config { bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ lpcmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ - uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Different devices has different available range, + for specific values, please refer to the reference manual.*/ } lpcmp_dac_config_t; /*! @@ -104,19 +196,71 @@ typedef struct _lpcmp_dac_config */ typedef struct _lpcmp_config { - bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ - lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ - lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ + lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ + lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + lpcmp_functional_source_clock_t functionalSourceClock; /*!< Select LPCMP functional mode clock source. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ } lpcmp_config_t; + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window mode control. + */ +typedef struct _lpcmp_window_control_config +{ + bool enableInvertWindowSignal; /*!< True: enable invert window signal, False: disable invert window signal. */ + lpcmp_couta_signal_t COUTASignal; /*!< Decide whether to define the COUTA signal value when the window is closed. */ + lpcmp_close_window_event_t closeWindowEvent; /*!< Decide whether to select COUT event signal edge defines + a COUT event to close window. */ +} lpcmp_window_control_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the round robin mode. + */ +typedef struct _lpcmp_roundrobin_config +{ + uint8_t initDelayModules; /*!< Comparator and DAC initialization delay modulus, See Reference Manual and DataSheet + for specific value. */ + uint8_t sampleClockNumbers; /*!< Specify the number of the round robin clock cycles(0~3) to wait after scanning the + active channel before sampling the channel's comparison result. */ + uint8_t channelSampleNumbers; /*!< Specify the number of samples for one channel, note that channelSampleNumbers + must not smaller than sampleTimeThreshhold. */ + uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are + "1",the final result is "1", otherwise the final result is "0", note that the + sampleTimeThreshhold must not be larger than channelSampleNumbers. */ + lpcmp_roundrobin_clock_source_t roundrobinClockSource; /*!< Decide which clock source to + choose in round robin mode. */ + lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to + choose in round robin mode. */ + lpcmp_roundrobin_fixedmuxport_t fixedMuxPort; /*!< Decide which mux port to choose as + fixed channel in round robin mode. */ + uint8_t fixedChannel; /*!< Indicate which channel of the fixed mux port is used in round robin mode. */ + uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in + round robin mode, for example, if checkerChannelMask set to 0x11U means select + channel 0 and channel 4 as checker channel.*/ +} lpcmp_roundrobin_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + /******************************************************************************* * API ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + /*! - * @name Initialization + * @name Initialization and configuration * @{ */ @@ -161,6 +305,7 @@ void LPCMP_Deinit(LPCMP_Type *base); * config->enableInvertOutput = false; * config->hysteresisMode = kLPCMP_HysteresisLevel0; * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; * @endcode * @param config Pointer to "lpcmp_config_t" structure. */ @@ -215,27 +360,6 @@ static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable) } } -/*! - * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by - * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. - * The optionally inverted comparator output COUT_RAW is sampled on every bus clock - * when WINDOW=1 to generate COUTA. - * - * @param base LPCMP peripheral base address. - * @param enable "true" means enable window mode, and "false" means disable window mode. - */ -static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; - } - else - { - base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; - } -} - /*! * @brief Configures the filter. * @@ -297,8 +421,165 @@ static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask) base->CSR = mask; } -/*@}*/ +/*! @} */ -/*@}*/ +/*! + * @name Window mode + * @{ + */ -#endif /* _FSL_LPCMP_H_ */ +/*! + * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by + * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. + * The optionally inverted comparator output COUT_RAW is sampled on every bus clock + * when WINDOW=1 to generate COUTA. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable window mode, and "false" means disable window mode. + */ +static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; + } + else + { + base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; + } +} + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config); +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +/*! @} */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @name RoundRobin mode + * @{ + */ + +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config); + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value); + +/*! + * @brief Enable/Disable roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin mode, and "false" means disable roundrobin mode. + */ +static inline void LPCMP_EnableRoundRobinMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR0 |= LPCMP_RRCR0_RR_EN_MASK; + } + else + { + base->RRCR0 &= ~LPCMP_RRCR0_RR_EN_MASK; + } +} + +/*! + * @brief Enable/Disable roundrobin internal timer, note that this function is only valid + * when using the internal trigger source. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin internal timer, and "false" means disable roundrobin internal timer. + */ +static inline void LPCMP_EnableRoundRobinInternalTimer(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR2 |= LPCMP_RRCR2_RR_TIMER_EN_MASK; + } + else + { + base->RRCR2 &= ~LPCMP_RRCR2_RR_TIMER_EN_MASK; + } +} + +/*! + * @brief Set preset value for all channels, users can set all channels' preset vaule through this API, + * for example, if the mask set to 0x03U means channel0 and channel2's preset value set to 1U and other + * channels' preset value set to 0U. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_SetPreSetValue(LPCMP_Type *base, uint8_t mask) +{ + base->RRCSR = (uint32_t)mask; +} + +/*! + * @brief Get comparison results for all channels, users can get all channels' comparison + * results through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' comparison result. + */ +static inline uint8_t LPCMP_GetComparisonResult(LPCMP_Type *base) +{ + return (uint8_t)base->RRCSR; +} + +/*! + * @brief Clear input changed flags for single channel or multiple channels, users can clear + * input changed flag of a single channel or multiple channels through this API, for example, + * if the mask set to 0x03U means clear channel0 and channel2's input changed flags. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_ClearInputChangedFlags(LPCMP_Type *base, uint8_t mask) +{ + base->RRSR = (uint32_t)mask; +} + +/*! + * @brief Get input changed flags for all channels, Users can get all channels' input changed + * flags through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' changed flag. + */ +static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base) +{ + return (uint8_t)base->RRSR; +} + +/*! @} */ + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_LPCMP_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.c index 099f335de2..b494aa8d96 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.c @@ -32,6 +32,11 @@ typedef union pvoid_to_u32 /*! @brief check whether lpflexcomm supports peripheral type */ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph); +/*! @brief Changes LP_FLEXCOMM mode. */ +static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief Common LPFLEXCOMM IRQhandle. */ +static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance); /******************************************************************************* * Variables ******************************************************************************/ @@ -39,6 +44,9 @@ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_ /*! @brief Array to map LP_FLEXCOMM instance number to base address. */ static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS; +/*! @brief Array to map LP_FLEXCOMM instance PTRS. */ +static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS; + /*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)]; @@ -57,7 +65,6 @@ static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS; /*! @brief Pointers to LP_FLEXCOMM resets for each instance. */ static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS; #endif - /******************************************************************************* * Code ******************************************************************************/ @@ -83,10 +90,20 @@ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_ } } +/*! @brief Returns for LP_FLEXCOMM base address. */ +uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance) +{ + if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)) + { + return s_lpflexcommBaseAddrs[instance]; + } + return 0U; +} + /*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */ uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance) { - LP_FLEXCOMM_Type *base = (LP_FLEXCOMM_Type *)s_lpflexcommBaseAddrs[instance]; + LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance]; return base->ISTAT; } @@ -114,8 +131,7 @@ uint32_t LP_FLEXCOMM_GetInstance(void *base) static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock) { assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART); - assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)); - LP_FLEXCOMM_Type *base = (LP_FLEXCOMM_Type *)s_lpflexcommBaseAddrs[instance]; + LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance]; /* Check whether peripheral type is present */ if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph)) @@ -146,15 +162,15 @@ static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T pe /*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */ status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph) { - assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)); + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the peripheral clock */ CLOCK_EnableClock(s_lpflexcommClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) - /* Reset the LP_FLEXCOMM module */ - RESET_PeripheralReset(s_lpflexcommResets[instance]); + /* Reset the LP_FLEXCOMM module before configuring it.*/ + RESET_ClearPeripheralReset(s_lpflexcommResets[instance]); #endif /* Set the LP_FLEXCOMM to given peripheral */ return LP_FLEXCOMM_SetPeriph(instance, periph, 0); @@ -163,11 +179,12 @@ status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph) /*! brief Deinitializes LP_FLEXCOMM. */ void LP_FLEXCOMM_Deinit(uint32_t instance) { - assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)); + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the peripheral clock */ CLOCK_DisableClock(s_lpflexcommClocks[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + RESET_SetPeripheralReset(s_lpflexcommResets[instance]); } /*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to @@ -177,7 +194,7 @@ void LP_FLEXCOMM_SetIRQHandler(uint32_t instance, void *lpflexcommHandle, LP_FLEXCOMM_PERIPH_T periph) { - assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)); + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); /* Clear handler first to avoid execution of the handler with wrong handle */ s_lpflexcommIrqHandler[periph][instance] = NULL; s_lpflexcommHandle[periph][instance] = lpflexcommHandle; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.h index 0636ec451b..919f720618 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LP_FLEXCOMM_H_ -#define _FSL_LP_FLEXCOMM_H_ +#ifndef FSL_LP_FLEXCOMM_H_ +#define FSL_LP_FLEXCOMM_H_ #include "fsl_common.h" @@ -15,10 +15,10 @@ */ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief FlexCOMM driver version. */ -#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ +#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*! @} */ /*! @brief LP_FLEXCOMM peripheral modes. */ typedef enum @@ -60,6 +60,9 @@ extern "C" { /*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */ uint32_t LP_FLEXCOMM_GetInstance(void *base); +/*! @brief Returns for LP_FLEXCOMM base address. */ +uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance); + /*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */ uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance); @@ -80,6 +83,6 @@ void LP_FLEXCOMM_SetIRQHandler(uint32_t instance, } #endif -/*@}*/ +/*! @} */ -#endif /* _FSL_LP_FLEXCOMM_H_*/ +#endif /* FSL_LP_FLEXCOMM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.c index 74934d1fb3..ccd881b21b 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.c @@ -87,6 +87,31 @@ static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; transactional APIs. */ IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map LPI2C instance number to clock gate enum. */ +static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; + +#if defined(LPI2C_PERIPH_CLOCKS) +/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ +static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +void *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; + /******************************************************************************* * Code ******************************************************************************/ @@ -343,16 +368,36 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi uint32_t cycles; uint32_t cfgr2; uint32_t value; - -#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) - /* initialize flexcomm to LPI2C mode */ - status_t status = LP_FLEXCOMM_Init(LPI2C_GetInstance(base), LP_FLEXCOMM_PERIPH_LPI2C); - if (kStatus_Success != status) + uint32_t instance = LPI2C_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) { - assert(false); - } + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPI2C mode */ + status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + if (kStatus_Success != status) + { + assert(false); + } #endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + /* Reset peripheral before configuring it. */ LPI2C_MasterReset(base); @@ -438,12 +483,28 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi */ void LPI2C_MasterDeinit(LPI2C_Type *base) { + uint32_t instance = LPI2C_GetInstance(base); + /* Restore to reset state. */ LPI2C_MasterReset(base); - + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) - LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base)); + LP_FLEXCOMM_Deinit(instance); #endif + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } } /*! @@ -957,6 +1018,15 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t } } } + + /* Transmit fail */ + if (kStatus_Success != result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + (void)LPI2C_MasterStop(base); + } + } } return result; @@ -987,10 +1057,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, uint32_t instance; assert(NULL != handle); - - lpi2c_to_lpflexcomm_t handler; - (void)memset(&handler, 0, sizeof(handler)); - + /* Clear out the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -1001,9 +1068,23 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, handle->completionCallback = callback; handle->userData = userData; - /* Save the handle in global variables to support the double weak mechanism. */ - handler.lpi2c_master_handler = LPI2C_MasterTransferHandleIRQ; - LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_t handler; + (void)memset(&handler, 0, sizeof(handler)); + + /* Save the handle in global variables to support the double weak mechanism. */ + handler.lpi2c_master_handler = LPI2C_MasterTransferHandleIRQ; + LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + } /* Clear internal IRQ enables and enable NVIC IRQ. */ LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); @@ -1598,15 +1679,35 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, { uint32_t tmpReg; uint32_t tmpCycle; + uint32_t instance = LPI2C_GetInstance(base); -#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) - /* initialize flexcomm to LPI2C mode */ - status_t status = LP_FLEXCOMM_Init(LPI2C_GetInstance(base), LP_FLEXCOMM_PERIPH_LPI2C); - if (kStatus_Success != status) + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) { - assert(false); - } + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPI2C mode */ + status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + if (kStatus_Success != status) + { + assert(false); + } #endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } /* Restore to reset conditions. */ LPI2C_SlaveReset(base); @@ -1664,11 +1765,28 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, */ void LPI2C_SlaveDeinit(LPI2C_Type *base) { - LPI2C_SlaveReset(base); + uint32_t instance = LPI2C_GetInstance(base); + /* Restore to reset state. */ + LPI2C_SlaveReset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) - LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base)); + LP_FLEXCOMM_Deinit(instance); #endif + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } } /*! @@ -1908,10 +2026,7 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, uint32_t instance; assert(NULL != handle); - - lpi2c_to_lpflexcomm_t handler; - (void)memset(&handler, 0, sizeof(handler)); - + /* Clear out the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -1922,9 +2037,23 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, handle->callback = callback; handle->userData = userData; - /* Save the handle in global variables to support the double weak mechanism. */ - handler.lpi2c_slave_handler = LPI2C_SlaveTransferHandleIRQ; - LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_t handler; + (void)memset(&handler, 0, sizeof(handler)); + + /* Save the handle in global variables to support the double weak mechanism. */ + handler.lpi2c_slave_handler = LPI2C_SlaveTransferHandleIRQ; + LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + } /* Clear internal IRQ enables and enable NVIC IRQ. */ LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); @@ -2076,7 +2205,7 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) * note This function does not need to be called unless you are reimplementing the * non blocking API's interrupt handler routines to add special functionality. * param instance The LPI2C instance. - * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * param lpi2cSlaveHandle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. */ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle) { @@ -2221,7 +2350,7 @@ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle) *xfer->data++ = (uint8_t)base->SRDR; --xfer->dataSize; ++handle->transferredCount; - if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK)) + if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK)) { if (((0U == (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) || (NULL == handle->callback))) @@ -2246,3 +2375,43 @@ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle) } } } + +#if !(defined(FSL_FEATURE_I2C_HAS_NO_IRQ) && FSL_FEATURE_I2C_HAS_NO_IRQ) +/*! + * @brief Shared IRQ handler that can call both master and slave ISRs. + * + * The master and slave ISRs are called through function pointers in order to decouple + * this code from the ISR functions. Without this, the linker would always pull in both + * ISRs and every function they call, even if only the functional API was used. + * + * @param base The LPI2C peripheral base address. + * @param instance The LPI2C peripheral instance number. + */ +void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); +void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((0U != (base->MCR & LPI2C_MCR_MEN_MASK)) && (NULL != s_lpi2cMasterIsr)) + { + /* Master mode. */ + s_lpi2cMasterIsr(instance, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((0U != (base->SCR & LPI2C_SCR_SEN_MASK)) && (NULL != s_lpi2cSlaveIsr)) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(instance, s_lpi2cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(LPI2C15) +/* Implementation of LPI2C15 handler named in startup code. */ +void LPI2C15_DriverIRQHandler(void); +void LPI2C15_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C15, 15U); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.h index b2777ca419..96afc6d448 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPI2C_H_ -#define _FSL_LPI2C_H_ +#ifndef FSL_LPI2C_H_ +#define FSL_LPI2C_H_ #include #include "fsl_device_registers.h" @@ -22,10 +22,10 @@ */ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief LPI2C driver version. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) +/*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef I2C_RETRY_TIMES @@ -375,7 +375,7 @@ typedef enum _lpi2c_slave_transfer_event (slave-transmitter role). */ kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received data (slave-receiver role). */ - kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. When this event is set, the driver will no longer decide to reply to ack/nack. */ kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ @@ -436,6 +436,14 @@ struct _lpi2c_slave_handle APIs. */ extern IRQn_Type const kLpi2cIrqs[]; +/*! Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern void *s_lpi2cMasterHandle[]; + /******************************************************************************* * API ******************************************************************************/ @@ -461,7 +469,7 @@ uint32_t LPI2C_GetInstance(LPI2C_Type *base); */ /*! @name Initialization and deinitialization */ -/*@{*/ +/*! @{ */ /*! * @brief Provides a default configuration for the LPI2C master peripheral. @@ -552,10 +560,10 @@ static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); } -/*@}*/ +/*! @} */ /*! @name Status */ -/*@{*/ +/*! @{ */ /*! * @brief Gets the LPI2C master status flags. @@ -599,10 +607,10 @@ static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statu base->MSR = statusMask; } -/*@}*/ +/*! @} */ /*! @name Interrupts */ -/*@{*/ +/*! @{ */ /*! * @brief Enables the LPI2C master interrupt requests. @@ -646,10 +654,10 @@ static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) return base->MIER; } -/*@}*/ +/*! @} */ /*! @name DMA control */ -/*@{*/ +/*! @{ */ /*! * @brief Enables or disables LPI2C master DMA requests. @@ -685,10 +693,10 @@ static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) return (uint32_t)&base->MRDR; } -/*@}*/ +/*! @} */ /*! @name FIFO control */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the watermarks for LPI2C master FIFOs. @@ -727,10 +735,10 @@ static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, } } -/*@}*/ +/*! @} */ /*! @name Bus operations */ -/*@{*/ +/*! @{ */ /*! * @brief Sets the I2C bus frequency for master transactions. @@ -866,10 +874,10 @@ status_t LPI2C_MasterStop(LPI2C_Type *base); */ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); -/*@}*/ +/*! @} */ /*! @name Non-blocking */ -/*@{*/ +/*! @{ */ /*! * @brief Creates a new handle for the LPI2C master non-blocking APIs. @@ -930,10 +938,10 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h */ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); -/*@}*/ +/*! @} */ /*! @name IRQ handler */ -/*@{*/ +/*! @{ */ /*! * @brief Reusable routine to handle master interrupts. @@ -944,7 +952,7 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); */ void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle); -/*@}*/ +/*! @} */ /*! @} */ @@ -954,7 +962,7 @@ void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle); */ /*! @name Slave initialization and deinitialization */ -/*@{*/ +/*! @{ */ /*! * @brief Provides a default configuration for the LPI2C slave peripheral. @@ -1035,10 +1043,10 @@ static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); } -/*@}*/ +/*! @} */ /*! @name Slave status */ -/*@{*/ +/*! @{ */ /*! * @brief Gets the LPI2C slave status flags. @@ -1079,10 +1087,10 @@ static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t status base->SSR = statusMask; } -/*@}*/ +/*! @} */ /*! @name Slave interrupts */ -/*@{*/ +/*! @{ */ /*! * @brief Enables the LPI2C slave interrupt requests. @@ -1125,10 +1133,10 @@ static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) return base->SIER; } -/*@}*/ +/*! @} */ /*! @name Slave DMA control */ -/*@{*/ +/*! @{ */ /*! * @brief Enables or disables the LPI2C slave peripheral DMA requests. @@ -1145,10 +1153,10 @@ static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressVali LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); } -/*@}*/ +/*! @} */ /*! @name Slave bus operations */ -/*@{*/ +/*! @{ */ /*! * @brief Returns whether the bus is idle. @@ -1236,10 +1244,10 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t * */ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); -/*@}*/ +/*! @} */ /*! @name Slave non-blocking */ -/*@{*/ +/*! @{ */ /*! * @brief Creates a new handle for the LPI2C slave non-blocking APIs. @@ -1309,21 +1317,21 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han */ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); -/*@}*/ +/*! @} */ /*! @name Slave IRQ handler */ -/*@{*/ +/*! @{ */ /*! * @brief Reusable routine to handle slave interrupts. * @note This function does not need to be called unless you are reimplementing the * non blocking API's interrupt handler routines to add special functionality. * @param instance The LPI2C instance. - * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @param lpi2cSlaveHandle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. */ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle); -/*@}*/ +/*! @} */ /*! @} */ @@ -1331,4 +1339,4 @@ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle); } #endif -#endif /* _FSL_LPI2C_H_ */ +#endif /* FSL_LPI2C_H_ */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.c index c7839520b4..eca6f9aac9 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.c @@ -41,9 +41,6 @@ enum _lpi2c_transfer_states kWaitForCompletionState, }; -/*! @brief Typedef for interrupt handler. */ -typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); - /*! * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t` */ @@ -126,7 +123,6 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, /* Look up instance number */ uint32_t instance = LPI2C_GetInstance(base); - lpi2c_to_lpflexcomm_edma_t handler; /* Clear out the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -139,9 +135,21 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, handle->rx = rxDmaHandle; handle->tx = (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) > 0) ? txDmaHandle : rxDmaHandle; - handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ; + if (LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_edma_t handler; + handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ; - LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set LPI2C_MasterTransferEdmaHandleIRQ as LPI2C DMA IRQ handler */ + s_lpi2cMasterIsr = LPI2C_MasterTransferEdmaHandleIRQ; + } /* Enable interrupt in NVIC. */ (void)EnableIRQ(kLpi2cIrqs[instance]); @@ -330,10 +338,17 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, if (commandCount != 0U) { +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdResetExt(handle->tx->base, tcd); + EDMA_TcdSetTransferConfigExt(handle->tx->base, tcd, &transferConfig, NULL); + EDMA_TcdEnableInterruptsExt(handle->tx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#else /* Create a software TCD, which will be chained after the commands. */ EDMA_TcdReset(tcd); EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#endif linkTcd = tcd; } else @@ -371,9 +386,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, enabling rx dma and disabling tx dma, which will be chained onto the commands transfer, and create another software TCD of transfering data and chain it onto the last TCD. Notice that in this situation assume tx/rx uses same channel */ +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->rx->base, tcd); + EDMA_TcdSetTransferConfigExt(handle->rx->base, tcd, &transferConfig, NULL); + EDMA_TcdEnableInterruptsExt(handle->rx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#else EDMA_TcdReset(tcd); EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#endif transferConfig.srcAddr = (uint32_t)&lpi2c_edma_RecSetting; transferConfig.destAddr = (uint32_t) & (base->MDER); @@ -386,8 +407,13 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK)); +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->rx->base, tcdSetRxClearTxDMA); + EDMA_TcdSetTransferConfigExt(handle->rx->base, tcdSetRxClearTxDMA, &transferConfig, tcd); +#else EDMA_TcdReset(tcdSetRxClearTxDMA); EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd); +#endif linkTcd = tcdSetRxClearTxDMA; } } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.h index 0a63adb09b..3c771447c1 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPI2C_EDMA_H_ -#define _FSL_LPI2C_EDMA_H_ +#ifndef FSL_LPI2C_EDMA_H_ +#define FSL_LPI2C_EDMA_H_ #include "fsl_lpi2c.h" #include "fsl_edma.h" @@ -16,10 +16,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief LPI2C EDMA driver version. */ -#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @} */ /*! * @addtogroup lpi2c_master_edma_driver @@ -80,7 +80,7 @@ extern "C" { */ /*! @name Master DMA */ -/*@{*/ +/*! @{ */ /*! * @brief Create a new handle for the LPI2C master DMA APIs. @@ -147,7 +147,7 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha */ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); -/*@}*/ +/*! @} */ /*! @} */ @@ -155,4 +155,4 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl } #endif -#endif /* _FSL_LPI2C_EDMA_H_ */ +#endif /* FSL_LPI2C_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.c index 8f01abd443..818c23801b 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.c @@ -15,7 +15,7 @@ static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData) { lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData; - BaseType_t reschedule; + BaseType_t reschedule = pdFALSE; handle->async_status = status; (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); portYIELD_FROM_ISR(reschedule); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.h index de2abdf0a1..029e16a351 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.h @@ -25,8 +25,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPI2C FreeRTOS driver version 2.0.8. */ -#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief LPI2C FreeRTOS driver version 2.0.0. */ +#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*@}*/ /*! @brief LPI2C FreeRTOS handle */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.c index 64922fca23..442a84c157 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -67,7 +67,7 @@ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, * @brief Combine the write data for 1 byte to 4 bytes. * This is not a public API. */ -static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap); +static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap); /*! * @brief Separate the read data for 1 byte to 4 bytes. @@ -122,9 +122,27 @@ static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; /*! @brief Pointers to lpspi IRQ number for each instance. */ static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to lpspi clocks for each instance. */ +static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; + +#if defined(LPSPI_PERIPH_CLOCKS) +static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to lpspi handles for each instance. */ +static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)]; + /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpspi_master_isr_t s_lpspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpspi_slave_isr_t s_lpspiSlaveIsr; + /********************************************************************************************************************** * Code *********************************************************************************************************************/ @@ -179,17 +197,37 @@ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) { assert(masterConfig != NULL); - + uint32_t tcrPrescaleValue = 0; + uint32_t instance = LPSPI_GetInstance(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) /* initialize flexcomm to LPSPI mode */ - status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); - if (kStatus_Success != status) - { - assert(false); - } + status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); + if (kStatus_Success != status) + { + assert(false); + } #endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } + + /* Disable LPSPI first */ + LPSPI_Enable(base, false); /* Set LPSPI to master */ LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); @@ -199,9 +237,9 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi /* Set Configuration Register 1 related setting.*/ base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK | - LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK)) | + LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK )) | LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | - LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay) | + LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay )| LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc); /* Set baudrate and delay times*/ @@ -251,12 +289,13 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; masterConfig->direction = kLPSPI_MsbFirst; - masterConfig->pcsToSckDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U; - masterConfig->lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U; - masterConfig->betweenTransferDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U; + masterConfig->pcsToSckDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->lastSckToPcsDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->betweenTransferDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; masterConfig->whichPcs = kLPSPI_Pcs0; masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + masterConfig->pcsFunc = kLPSPI_PcsAsCs; masterConfig->pinCfg = kLPSPI_SdiInSdoOut; masterConfig->dataOutConfig = kLpspiDataOutRetained; @@ -273,23 +312,40 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) { assert(slaveConfig != NULL); + + uint32_t instance = LPSPI_GetInstance(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) /* initialize flexcomm to LPSPI mode */ - status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); - if (kStatus_Success != status) - { - assert(false); - } + status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); + if (kStatus_Success != status) + { + assert(false); + } #endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } + LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | - LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg)| - LPSPI_CFGR1_PCSCFG(slaveConfig->pcsFunc); + LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); @@ -358,12 +414,28 @@ void LPSPI_Reset(LPSPI_Type *base) */ void LPSPI_Deinit(LPSPI_Type *base) { + uint32_t instance = LPSPI_GetInstance(base); + /* Reset to default value */ LPSPI_Reset(base); - + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) - LP_FLEXCOMM_Deinit(LPSPI_GetInstance(base)); + LP_FLEXCOMM_Deinit(instance); #endif + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable LPSPI clock */ + (void)CLOCK_DisableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } } static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, @@ -715,9 +787,8 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, void *userData) { assert(handle != NULL); - - lpspi_to_lpflexcomm_t handler; - handler.lpspi_master_handler = LPSPI_MasterTransferHandleIRQ; + + uint32_t instance = LPSPI_GetInstance(base); /* Zero the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -725,8 +796,21 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, handle->callback = callback; handle->userData = userData; - /* Save the handle in global variables to support the double weak mechanism. */ - LP_FLEXCOMM_SetIRQHandler(LPSPI_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpspi_to_lpflexcomm_t handler; + handler.lpspi_master_handler = LPSPI_MasterTransferHandleIRQ; + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + } + else + { + s_lpspiHandle[instance] = handle; + + /* Set irq handler. */ + s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; + } } /*! @@ -847,7 +931,7 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); uint8_t bytesEachWrite; uint8_t bytesEachRead; - uint8_t *txData = transfer->txData; + const uint8_t *txData = transfer->txData; uint8_t *rxData = transfer->rxData; uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; uint32_t readData = 0U; @@ -882,9 +966,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf /* Configure transfer control register. */ base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | - LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK | LPSPI_TCR_WIDTH_MASK)) | - LPSPI_TCR_PCS(whichPcs) | - LPSPI_TCR_WIDTH(width); + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_PCS(whichPcs) | LPSPI_TCR_WIDTH(width); /*TCR is also shared the FIFO, so wait for TCR written.*/ if (!LPSPI_TxFifoReady(base)) @@ -1118,6 +1201,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t /* Variables */ bool isRxMask = false; + handle->isTxMask = false; uint8_t txWatermark; uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; uint32_t tmpTimes; @@ -1566,10 +1650,7 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, assert(handle != NULL); /* Get instance from peripheral base address. */ - // uint32_t instance = LPSPI_GetInstance(base); - - lpspi_to_lpflexcomm_t handler; - handler.lpspi_slave_handler = LPSPI_SlaveTransferHandleIRQ; + uint32_t instance = LPSPI_GetInstance(base); /* Zero the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -1577,8 +1658,21 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, handle->callback = callback; handle->userData = userData; - /* Save the handle in global variables to support the double weak mechanism. */ - LP_FLEXCOMM_SetIRQHandler(LPSPI_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpspi_to_lpflexcomm_t handler; + handler.lpspi_slave_handler = LPSPI_SlaveTransferHandleIRQ; + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + } + else + { + s_lpspiHandle[instance] = handle; + + /* Set irq handler. */ + s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; + } } /*! @@ -1627,7 +1721,6 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * uint32_t readRegRemainingTimes; uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; - uint32_t width = (transfer->configFlags & LPSPI_SLAVE_WIDTH_MASK) >> LPSPI_SLAVE_WIDTH_SHIFT; /* Assign the original value for members of transfer handle. */ handle->state = (uint8_t)kLPSPI_Busy; @@ -1684,8 +1777,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs) | - LPSPI_TCR_WIDTH(width); + LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs); /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , * and you should also enable the INTMUX interupt in your application. @@ -1862,7 +1954,7 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) * * This function processes the LPSPI transmit and receives an IRQ. * - * param base LPSPI instance. + * param instance LPSPI instance index. * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. */ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle) @@ -1962,7 +2054,9 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl { handle->state = (uint8_t)kLPSPI_Error; } - handle->errorCount++; + handle->errorCount++; + /* ERR051588: Clear FIFO after underrun occurs */ + LPSPI_FlushFifo(base, true, false); } /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U) && @@ -1978,7 +2072,7 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl } } -static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap) +static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap) { assert(txData != NULL); @@ -2160,3 +2254,34 @@ static bool LPSPI_TxFifoReady(LPSPI_Type *base) #endif return true; } + +void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance); +void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance) +{ + assert(s_lpspiHandle[instance] != NULL); + if (LPSPI_IsMaster(base)) + { + s_lpspiMasterIsr(instance, (lpspi_master_handle_t *)s_lpspiHandle[instance]); + } + else + { + s_lpspiSlaveIsr(instance, (lpspi_slave_handle_t *)s_lpspiHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(LPSPI14) +void LPSPI14_DriverIRQHandler(void); +void LPSPI14_DriverIRQHandler(void) +{ + LPSPI_CommonIRQHandler(LPSPI14, 14); +} +#endif + +#if defined(LPSPI16) +void LPSPI16_DriverIRQHandler(void); +void LPSPI16_DriverIRQHandler(void) +{ + LPSPI_CommonIRQHandler(LPSPI16, 16); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.h index 498f88e415..877b7f65cd 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPSPI_H_ -#define _FSL_LPSPI_H_ +#ifndef FSL_LPSPI_H_ +#define FSL_LPSPI_H_ #include "fsl_common.h" #include "fsl_lpflexcomm.h" @@ -21,10 +21,10 @@ *********************************************************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief LPSPI driver version. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) +/*! @} */ #ifndef LPSPI_DUMMY_DATA /*! @brief LPSPI dummy data if no Tx data.*/ @@ -180,10 +180,11 @@ typedef enum _lpspi_data_out_config kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ } lpspi_data_out_config_t; +/*! @brief LPSPI cs function configuration. */ typedef enum _lpspi_pcs_function_config { - kLPSPI_PcsAsCs = 0U, - kLPSPI_PcsAsData = 1U, + kLPSPI_PcsAsCs = 0U, /*!< PCS pin select as cs function */ + kLPSPI_PcsAsData = 1U, /*!< PCS pin select as date function */ } lpspi_pcs_function_config_t; /*! @brief LPSPI transfer width configuration. */ @@ -206,7 +207,7 @@ typedef enum _lpspi_delay_type #define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ #define LPSPI_MASTER_WIDTH_SHIFT (16U) /*!< LPSPI master width shift macro, internal used */ -#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift macro, internal used */ +#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift mask, internal used */ /*! @brief Use this enumeration for LPSPI master transfer configFlags. */ enum _lpspi_transfer_config_flag_for_master @@ -219,7 +220,7 @@ enum _lpspi_transfer_config_flag_for_master kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */ kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */ kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */ - + kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ kLPSPI_MasterByteSwap = @@ -240,9 +241,6 @@ enum _lpspi_transfer_config_flag_for_master #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ #define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ -#define LPSPI_SLAVE_WIDTH_SHIFT (16U) /*!< LPSPI slave width shift macro, internal used */ -#define LPSPI_SLAVE_WIDTH_MASK (0x30000U) /*!< LPSPI slave width shift macro, internal used */ - /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ enum _lpspi_transfer_config_flag_for_slave { @@ -251,10 +249,6 @@ enum _lpspi_transfer_config_flag_for_slave kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ - kLPSPI_SlaveWidth1 = 0U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 1bit */ - kLPSPI_SlaveWidth2 = 1U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 2bit */ - kLPSPI_SlaveWidth4 = 2U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 4bit */ - kLPSPI_SlaveByteSwap = 1U << 22 /*!< Is slave swap the byte. * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set @@ -299,8 +293,8 @@ typedef struct _lpspi_master_config lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data *during single bit transfers.*/ - - lpspi_pcs_function_config_t pcsFunc; + + lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/ lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated * between accesses (LPSPI_PCS is negated). */ @@ -322,8 +316,6 @@ typedef struct _lpspi_slave_config lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data *during single bit transfers.*/ - lpspi_pcs_function_config_t pcsFunc; - lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated * between accesses (LPSPI_PCS is negated). */ } lpspi_slave_config_t; @@ -367,7 +359,7 @@ typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, /*! @brief LPSPI master/slave transfer structure.*/ typedef struct _lpspi_transfer { - uint8_t *txData; /*!< Send buffer. */ + const uint8_t *txData; /*!< Send buffer. */ uint8_t *rxData; /*!< Receive buffer. */ volatile size_t dataSize; /*!< Transfer bytes. */ @@ -393,7 +385,7 @@ struct _lpspi_master_handle volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ - uint8_t *volatile txData; /*!< Send buffer. */ + const uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ @@ -423,7 +415,7 @@ struct _lpspi_slave_handle volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ - uint8_t *volatile txData; /*!< Send buffer. */ + const uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ @@ -1165,7 +1157,7 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); * * This function processes the LPSPI transmit and receives an IRQ. * - * @param base LPSPI instance. + * @param instance LPSPI instance index. * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. */ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle); @@ -1180,4 +1172,4 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl /*! @}*/ -#endif /*_FSL_LPSPI_H_*/ +#endif /*FSL_LPSPI_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.c index 1799a02696..dcfcd4d982 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.c @@ -181,26 +181,20 @@ static void LPSPI_PrepareTransferEDMA(LPSPI_Type *base) } /*! - * brief LPSPI master transfer data using eDMA. + * brief LPSPI master config transfer parameter using eDMA. * - * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data - * is transferred, the callback function is called. - * - * Note: - * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * This function is preparing to transfers data using eDMA. * * param base LPSPI peripheral base address. * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. - * param transfer pointer to lpspi_transfer_t structure. - * return status of status_t. + * param configFlags transfer configuration flags. ref _lpspi_transfer_config_flag_for_master. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. */ -status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags) { assert(handle != NULL); - assert(transfer != NULL); /* Check that we're not busy.*/ if (handle->state == (uint8_t)kLPSPI_Busy) @@ -210,41 +204,17 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * /* Disable module before configuration */ LPSPI_Enable(base, false); - /* Check arguements */ - if (!LPSPI_CheckTransferArgument(base, transfer, true)) - { - return kStatus_InvalidArgument; - } LPSPI_PrepareTransferEDMA(base); - /* Variables */ - bool isThereExtraTxBytes = false; - bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); - bool isPcsContinuous = ((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U); - uint32_t instance = LPSPI_GetInstance(base); - uint8_t dummyData = g_lpspiDummyData[instance]; - uint8_t bytesLastWrite = 0; + bool isByteSwap = ((configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + bool isPcsContinuous = ((configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U); + uint32_t instance = LPSPI_GetInstance(base); + uint8_t dummyData = g_lpspiDummyData[instance]; /*Used for byte swap*/ - uint32_t addrOffset = 0; - uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); - uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - uint32_t width = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT; + uint32_t whichPcs = (configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; - edma_transfer_config_t transferConfigRx = {0}; - edma_transfer_config_t transferConfigTx = {0}; - edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); - handle->state = (uint8_t)kLPSPI_Busy; - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; handle->txBuffIfNull = ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); /*The TX and RX FIFO sizes are always the same*/ @@ -265,16 +235,13 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is * hard to controlled by software. */ base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs) | - LPSPI_TCR_WIDTH(width); - + LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); /*Calculate the bytes for write/read the TX/RX register each time*/ if (bytesPerFrame <= 4U) { handle->bytesEachWrite = (uint8_t)bytesPerFrame; handle->bytesEachRead = (uint8_t)bytesPerFrame; - - handle->bytesLastRead = (uint8_t)bytesPerFrame; + handle->bytesLastRead = (uint8_t)bytesPerFrame; } else { @@ -282,7 +249,77 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * handle->bytesEachRead = 4U; handle->bytesLastRead = 4U; + } + return kStatus_Success; +} +/*! + * brief LPSPI master transfer data using eDMA without configs. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * This API is only for transfer through DMA without configuration. + * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure, config field is not working. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + * retval kStatus_InvalidArgument The transfer structure is invalid. + */ +status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + /* Variables */ + bool isThereExtraTxBytes = false; + uint8_t bytesLastWrite = 0; + uint32_t instance = LPSPI_GetInstance(base); + /*Used for byte swap*/ + uint32_t addrOffset = 0; + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame > 4U) + { if ((transfer->dataSize % 4U) != 0U) { bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); @@ -412,8 +449,20 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; transferConfigTx.majorLoopCounts = 1; +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes); + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes, + &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes, + &transferConfigTx, NULL); + } +#else EDMA_TcdReset(softwareTCD_extraBytes); - if (handle->isPcsContinuous) { EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); @@ -422,6 +471,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * { EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); } +#endif } if (handle->isPcsContinuous) @@ -439,8 +489,14 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * transferConfigTx.minorLoopBytes = 4; transferConfigTx.majorLoopCounts = 1; +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous, + &transferConfigTx, NULL); +#else EDMA_TcdReset(softwareTCD_pcsContinuous); EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); +#endif } if (handle->txData != NULL) @@ -519,6 +575,34 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * return kStatus_Success; } +/*! + * brief LPSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status = kStatus_Fail; + status = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags); + if (kStatus_Success != status) + { + return status; + } + return LPSPI_MasterTransferEDMALite(base, handle, transfer); +} + static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, void *g_lpspiEdmaPrivateHandle, bool transferDone, @@ -715,7 +799,6 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - uint32_t width = (transfer->configFlags & LPSPI_SLAVE_WIDTH_MASK) >> LPSPI_SLAVE_WIDTH_SHIFT; uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; edma_transfer_config_t transferConfigRx = {0}; edma_transfer_config_t transferConfigTx = {0}; @@ -750,8 +833,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha any time since we use rx dma transfer finish cllback to indicate transfer finish. */ base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_MASK)) | - LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs) | - LPSPI_TCR_WIDTH(width); + LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); /*Calculate the bytes for write/read the TX/RX register each time*/ if (bytesPerFrame <= 4U) @@ -890,8 +972,14 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; transferConfigTx.majorLoopCounts = 1; +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->edmaTxDataToTxRegHandle->base, softwareTCD_extraBytes); + EDMA_TcdSetTransferConfigExt(handle->edmaTxDataToTxRegHandle->base, softwareTCD_extraBytes, + &transferConfigTx, NULL); +#else EDMA_TcdReset(softwareTCD_extraBytes); EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); +#endif } transferConfigTx.srcAddr = (uint32_t)(handle->txData); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.h index b28de0b693..06a2dd4e71 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPSPI_EDMA_H_ -#define _FSL_LPSPI_EDMA_H_ +#ifndef FSL_LPSPI_EDMA_H_ +#define FSL_LPSPI_EDMA_H_ #include "fsl_lpspi.h" #include "fsl_edma.h" @@ -20,10 +20,10 @@ * Definitions **********************************************************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief LPSPI EDMA driver version. */ -#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @} */ /*! * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. @@ -77,7 +77,7 @@ struct _lpspi_master_edma_handle volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */ - uint8_t *volatile txData; /*!< Send buffer. */ + const uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ @@ -122,7 +122,7 @@ struct _lpspi_slave_edma_handle uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t *volatile txData; /*!< Send buffer. */ + const uint8_t *volatile txData; /*!< Send buffer. */ uint8_t *volatile rxData; /*!< Receive buffer. */ volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ @@ -202,6 +202,46 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, */ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer); +/*! + * @brief LPSPI master config transfer parameter while using eDMA. + * + * This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite. + * + * @param base LPSPI peripheral base address. + * @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * @param configFlags transfer configuration flags. @ref _lpspi_transfer_config_flag_for_master. + * @return Indicates whether LPSPI master transfer was successful or not. + * @retval kStatus_Success Execution successfully. + * @retval kStatus_LPSPI_Busy The LPSPI device is busy. + */ +status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + uint32_t configFlags); + +/*! + * @brief LPSPI master transfer data using eDMA without configs. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * This API is only for transfer through DMA without configuration. + * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral base address. + * @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure, config field is not uesed. + * @return Indicates whether LPSPI master transfer was successful or not. + * @retval kStatus_Success Execution successfully. + * @retval kStatus_LPSPI_Busy The LPSPI device is busy. + * @retval kStatus_InvalidArgument The transfer structure is invalid. + */ +status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer); + /*! * @brief LPSPI master aborts a transfer which is using eDMA. * @@ -298,4 +338,4 @@ status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_hand /*! @}*/ -#endif /*_FSL_LPSPI_EDMA_H_*/ +#endif /*FSL_LPSPI_EDMA_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.c index 99e2ba2373..a5e2ef0a50 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.c @@ -15,7 +15,7 @@ static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData) { lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData; - BaseType_t reschedule; + BaseType_t reschedule = pdFALSE; handle->async_status = status; (void)xSemaphoreGiveFromISR(handle->event, &reschedule); portYIELD_FROM_ISR(reschedule); diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.h index 6d22b5ac2b..f9e91108bf 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.h @@ -25,8 +25,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPSPI FreeRTOS driver version 2.1.0. */ -#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief LPSPI FreeRTOS driver version 2.0.0. */ +#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*@}*/ /*! @brief LPSPI FreeRTOS handle */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.c index 4741e22a65..9e501e7a51 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.c @@ -165,9 +165,19 @@ void LPTMR_GetDefaultConfig(lptmr_config_t *config) #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \ FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) config->prescalerClockSource = kLPTMR_PrescalerClock_1; -#else +#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) config->prescalerClockSource = kLPTMR_PrescalerClock_0; -#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */ +#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_2; +#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_3; +#else +#error No valid source +#endif + /* Divide the prescaler clock by 2 */ config->value = kLPTMR_Prescale_Glitch_0; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.h index dcff41f343..b8e473120c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPTMR_H_ -#define _FSL_LPTMR_H_ +#ifndef FSL_LPTMR_H_ +#define FSL_LPTMR_H_ #include "fsl_common.h" @@ -20,9 +20,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ -/*@}*/ +/*! @{ */ +/*! Driver Version */ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @} */ /*! @brief LPTMR pin selection used in pulse counter mode.*/ typedef enum _lptmr_pin_select @@ -74,12 +75,21 @@ typedef enum _lptmr_prescaler_glitch_value */ typedef enum _lptmr_prescaler_clock_select { +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ +#endif + #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \ FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ #endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */ + +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ +#endif + #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \ FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ @@ -371,4 +381,4 @@ static inline void LPTMR_StopTimer(LPTMR_Type *base) /*! @}*/ -#endif /* _FSL_LPTMR_H_ */ +#endif /* FSL_LPTMR_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.c index b007be5d51..9c81efa55c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -62,6 +62,17 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t */ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); +/*! + * @brief Write to TX register using non-blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + /*! * @brief Read RX register using non-blocking method. * @@ -74,6 +85,17 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size */ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); +/*! + * @brief Read RX register using non-blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + /******************************************************************************* * Variables ******************************************************************************/ @@ -168,6 +190,20 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size } } +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) { assert(NULL != data); @@ -198,6 +234,18 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng } } +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = (uint16_t)(base->DATA & 0x03FFU); + } +} /*! * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. * @@ -249,16 +297,24 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { /* calculate the temporary sbr value */ - sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ if (sbrTemp == 0U) { sbrTemp = 1U; } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* For MISRA 15.7 */ + } /* Calculate the baud rate based on the temporary OSR and SBR values */ calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : - (config->baudRate_Bps - calculatedBaud); + (config->baudRate_Bps - calculatedBaud); if (tempDiff <= baudDiff) { @@ -579,12 +635,21 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { /* calculate the temporary sbr value */ - sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ if (sbrTemp == 0U) { sbrTemp = 1U; } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* For MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); @@ -703,6 +768,7 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address) */ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) { + uint32_t s_atomicOldInt; /* Only consider the real interrupt enable bits. */ mask &= (uint32_t)kLPUART_AllInterruptEnable; @@ -715,27 +781,36 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) base->TOSR |= ((mask >> 2U) & 0xF00UL); #endif /* Check int enable bits in base->BAUD */ - uint32_t tempReg = base->BAUD; + uint32_t baudRegMask = 0UL; #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - tempReg |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); /* Clear bit 7 from mask */ mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; #endif - tempReg |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); /* Clear bit 6 from mask */ mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; - base->BAUD = tempReg; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD |= baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO /* Check int enable bits in base->FIFO */ - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + /* Clear bit 9 and bit 8 from mask */ mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); #endif /* Check int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); base->CTRL |= mask; + EnableGlobalIRQ(s_atomicOldInt); } /*! @@ -753,6 +828,7 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) */ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) { + uint32_t s_atomicOldInt; /* Only consider the real interrupt enable bits. */ mask &= (uint32_t)kLPUART_AllInterruptEnable; @@ -764,28 +840,37 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) /* Timeout interrupt enables. */ base->TOSR &= ~((mask >> 2U) & 0xF00UL); #endif - /* Check int enable bits in base->BAUD */ - uint32_t tempReg = base->BAUD; + + /* Clear int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - tempReg &= ~((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); /* Clear bit 7 from mask */ mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; #endif - tempReg &= ~((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); /* Clear bit 6 from mask */ mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; - base->BAUD = tempReg; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD &= ~baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO /* Check int enable bits in base->FIFO */ - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); /* Clear bit 9 and bit 8 from mask */ mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); #endif - /* Check int enable bits in base->CTRL */ + /* Clear int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); base->CTRL &= ~mask; + EnableGlobalIRQ(s_atomicOldInt); } /*! @@ -918,8 +1003,8 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case they are written 1 accidentally. */ temp = (uint32_t)base->FIFO; - temp &= (uint32_t)( - ~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); + temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | + LPUART_FIFO_RXUF_MASK)); temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); base->FIFO = temp; } @@ -1003,6 +1088,67 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len return kStatus_Success; } +/*! + * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + const uint16_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + /*! * brief Reads the receiver data register using a blocking method. * @@ -1120,6 +1266,118 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) return status; } +/*! + * brief Reads the receiver data register in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint16_t *dataAddress = data; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + if (kStatus_Success == status) + { + *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); + dataAddress++; + } + else + { + break; + } + } + + return status; +} + /*! * brief Initializes the LPUART handle. * @@ -1172,6 +1430,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base, /* Initial seven data bits flag */ handle->isSevenDataBits = isSevenDataBits; #endif + handle->is16bitData = false; /* Save the handle in global variables to support the double weak mechanism. */ LP_FLEXCOMM_SetIRQHandler(LPUART_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPUART); @@ -1206,8 +1465,15 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base, assert(NULL != ringBuffer); /* Setup the ring buffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBuffer = ringBuffer; + if (!handle->is16bitData) + { + handle->rxRingBufferSize = ringBufferSize; + } + else + { + handle->rxRingBufferSize = ringBufferSize / 2U; + } handle->rxRingBufferHead = 0U; handle->rxRingBufferTail = 0U; @@ -1280,7 +1546,14 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand } else { - handle->txData = xfer->txData; + if (!handle->is16bitData) + { + handle->txData = xfer->txData; + } + else + { + handle->txData16 = xfer->txData16; + } handle->txDataSize = xfer->dataSize; handle->txDataSizeAll = xfer->dataSize; handle->txState = (uint8_t)kLPUART_TxBusy; @@ -1451,7 +1724,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, /* Copy data from ring buffer to user memory. */ for (i = 0U; i < bytesToCopy; i++) { - xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + if (!handle->is16bitData) + { + xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + } + else + { + xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail]; + } bytesCurrentReceived++; /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ @@ -1470,7 +1750,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, if (0U != bytesToReceive) { /* No data in ring buffer, save the request to LPUART handle. */ - handle->rxData = &xfer->rxData[bytesCurrentReceived]; + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = xfer->dataSize; handle->rxState = (uint8_t)kLPUART_RxBusy; @@ -1495,7 +1782,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, /* Ring buffer not used. */ else { - handle->rxData = &xfer->rxData[bytesCurrentReceived]; + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = bytesToReceive; handle->rxState = (uint8_t)kLPUART_RxBusy; @@ -1627,8 +1921,16 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle) tempCount = (uint8_t)MIN(handle->rxDataSize, count); /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData = &handle->rxData[tempCount]; + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } handle->rxDataSize -= tempCount; count -= tempCount; @@ -1687,8 +1989,16 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle) #endif /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData = &handle->rxData[tempCount]; + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } handle->rxDataSize -= tempCount; count -= tempCount; @@ -1742,10 +2052,24 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle) } else { - handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } } #else - handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } #endif /* Increase handle->rxRingBufferHead. */ @@ -1794,8 +2118,16 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle) #endif /* Using non block API to write the data to the registers. */ - LPUART_WriteNonBlocking(base, handle->txData, tempCount); - handle->txData = &handle->txData[tempCount]; + if (!handle->is16bitData) + { + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + } + else + { + LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount); + handle->txData16 = &handle->txData16[tempCount]; + } handle->txDataSize -= tempCount; count -= tempCount; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.h index 67861d0111..39974bde07 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.h @@ -1,11 +1,11 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_LPUART_H_ -#define _FSL_LPUART_H_ +#ifndef FSL_LPUART_H_ +#define FSL_LPUART_H_ #include "fsl_common.h" #include "fsl_lpflexcomm.h" @@ -20,10 +20,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief LPUART driver version. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +/*! @} */ /*! @brief Retry times for waiting flag. */ #ifndef UART_RETRY_TIMES @@ -124,23 +124,23 @@ typedef enum _lpuart_idle_config enum _lpuart_interrupt_enable { #if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR - kLPUART_CtsStateChangeInterruptEnable = LPUART_MCR_CTS_MASK, /*!< Change of state on CTS_B pin. bit 0 */ - kLPUART_DsrStateChangeInterruptEnable = LPUART_MCR_DSR_MASK, /*!< Change of state on DSR_B pin. bit 1 */ - kLPUART_RinStateChangeInterruptEnable = LPUART_MCR_RIN_MASK, /*!< Change of state on RIN_B pin. bit 2 */ - kLPUART_DcdStateChangeInterruptEnable = LPUART_MCR_DCD_MASK, /*!< Change of state on DCD_B pin. bit 3 */ + kLPUART_CtsStateChangeInterruptEnable = LPUART_MCR_CTS_MASK, /*!< Change of state on CTS_B pin. bit 0 */ + kLPUART_DsrStateChangeInterruptEnable = LPUART_MCR_DSR_MASK, /*!< Change of state on DSR_B pin. bit 1 */ + kLPUART_RinStateChangeInterruptEnable = LPUART_MCR_RIN_MASK, /*!< Change of state on RIN_B pin. bit 2 */ + kLPUART_DcdStateChangeInterruptEnable = LPUART_MCR_DCD_MASK, /*!< Change of state on DCD_B pin. bit 3 */ #endif kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */ #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ #endif #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */ kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */ #endif - kLPUART_RxCounter0TimeoutInterruptEnable = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ - kLPUART_RxCounter1TimeoutInterruptEnable = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ - kLPUART_TxCounter0TimeoutInterruptEnable = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ - kLPUART_TxCounter1TimeoutInterruptEnable = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ + kLPUART_RxCounter0TimeoutInterruptEnable = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ + kLPUART_RxCounter1TimeoutInterruptEnable = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ + kLPUART_TxCounter0TimeoutInterruptEnable = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ + kLPUART_TxCounter1TimeoutInterruptEnable = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING kLPUART_DataMatch2InterruptEnable = (LPUART_CTRL_MA2IE_MASK), /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ @@ -185,9 +185,9 @@ enum _lpuart_flags { #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO kLPUART_RxFifoUnderflowFlag = - (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ kLPUART_TxFifoOverflowFlag = - (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */ kLPUART_TxFifoEmptyFlag = @@ -200,10 +200,10 @@ enum _lpuart_flags kLPUART_RinStateChangeFlag = LPUART_MCR_RIN_MASK << 2U, /*!< Change of state on RIN_B pin. bit 4 */ kLPUART_DcdStateChangeFlag = LPUART_MCR_DCD_MASK << 2U, /*!< Change of state on DCD_B pin. bit 5 */ #endif - kLPUART_RxCounter0TimeoutFlag = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ - kLPUART_RxCounter1TimeoutFlag = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ - kLPUART_TxCounter0TimeoutFlag = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ - kLPUART_TxCounter1TimeoutFlag = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ + kLPUART_RxCounter0TimeoutFlag = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ + kLPUART_RxCounter1TimeoutFlag = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ + kLPUART_TxCounter0TimeoutFlag = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ + kLPUART_TxCounter1TimeoutFlag = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ @@ -221,16 +221,16 @@ enum _lpuart_flags kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full. bit 21 */ kLPUART_TransmissionCompleteFlag = - (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ kLPUART_TxDataRegEmptyFlag = (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */ kLPUART_RxActiveFlag = - (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected. bit 30 */ #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break - char detected and LIN circuit enabled. bit 31 */ + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled. bit 31 */ #endif kLPUART_AllClearFlags = @@ -299,7 +299,8 @@ typedef struct _lpuart_timeout_config { uint16_t rxExtendedTimeoutValue; /*!< The number of bits since the last stop bit that is required for an idle condition to be detected. Enable this will disable rxIdleType and rxIdleConfig. Set to 0 to disable. */ - uint16_t txExtendedTimeoutValue; /*!< . */ + uint16_t txExtendedTimeoutValue; /*!< The transmitter idle time in number of bits (baud rate) whenever an + idle character is queued through the transmit FIFO. */ lpuart_timeout_counter_config_t rxCounter0; /*!< Rx counter 0 configuration. */ lpuart_timeout_counter_config_t rxCounter1; /*!< Rx counter 1 configuration. */ lpuart_timeout_counter_config_t txCounter0; /*!< Tx counter 0 configuration. */ @@ -309,10 +310,10 @@ typedef struct _lpuart_timeout_config /*! @brief LPUART configuration structure. */ typedef struct _lpuart_config { - uint32_t baudRate_Bps; /*!< LPUART baud rate */ - lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ - bool isMsb; /*!< Data bits order, LSB (default), MSB */ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ #endif @@ -326,9 +327,9 @@ typedef struct _lpuart_config lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ #endif - lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ - lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ - lpuart_timeout_config_t timeoutConfig; /*!< Timeout configuration. */ + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + lpuart_timeout_config_t timeoutConfig; /*!< Timeout configuration. */ bool enableSingleWire; /*!< Use TXD pin as the source for the receiver. When enabled the TXD pin should be configured as open drain. */ uint8_t rtsDelay; /*!< Delay the negation of RTS by the configured number of bit clocks. */ @@ -345,11 +346,13 @@ typedef struct _lpuart_transfer */ union { - uint8_t *data; /*!< The buffer of data to be transfer.*/ - uint8_t *rxData; /*!< The buffer to receive data. */ - const uint8_t *txData; /*!< The buffer of data to be sent. */ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + uint16_t *rxData16; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + const uint16_t *txData16; /*!< The buffer of data to be sent. */ }; - size_t dataSize; /*!< The byte count to be transfer. */ + size_t dataSize; /*!< The byte count to be transfer. */ } lpuart_transfer_t; /* Forward declaration of the handle typedef. */ @@ -361,27 +364,40 @@ typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *h /*! @brief LPUART handle structure. */ struct _lpuart_handle { - const uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ + union + { + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + const uint16_t *volatile txData16; /*!< Address of remaining data to send. */ + }; + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + union + { + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */ + }; + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + union + { + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + uint16_t *rxRingBuffer16; /*!< Start address of the receiver ring buffer. */ + }; + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ lpuart_transfer_callback_t callback; /*!< Callback function. */ void *userData; /*!< LPUART callback function parameter.*/ - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state. */ + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT bool isSevenDataBits; /*!< Seven data bits flag. */ #endif + bool is16bitData; /*!< 16bit data bits flag, only used for 9bit or 10bit data */ }; /* Typedef for interrupt handler. */ @@ -421,7 +437,7 @@ static inline void LPUART_SoftwareReset(LPUART_Type *base) base->GLOBAL |= LPUART_GLOBAL_RST_MASK; base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; } -/* @} */ +/*! @} */ #endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ /*! @@ -484,7 +500,7 @@ void LPUART_Deinit(LPUART_Type *base); * @param config Pointer to a configuration structure. */ void LPUART_GetDefaultConfig(lpuart_config_t *config); -/* @} */ +/*! @} */ /*! * @name Module configuration @@ -595,7 +611,20 @@ static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water) base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water); } #endif -/* @} */ + +/*! + * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. + * + * This function Enable 16bit Data transmit in lpuart_handle_t. + * + * @param handle LPUART handle pointer. + * @param enable true to enable, false to disable. + */ +static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable) +{ + handle->is16bitData = enable; +} +/*! @} */ /*! * @name Status @@ -641,7 +670,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base); * @retval kStatus_Success Status in the mask are cleared. */ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -699,7 +728,7 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. */ uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); -/* @} */ +/*! @} */ #if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE /*! @@ -758,7 +787,7 @@ static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; } } -/* @} */ +/*! @} */ #endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ /*! @@ -907,6 +936,20 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address); */ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); +/*! + * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + /*! * @brief Reads the receiver data register using a blocking method. * @@ -925,7 +968,24 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len */ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); -/* @} */ +/*! + * @brief Reads the receiver data register in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/*! @} */ /*! * @name Transactional @@ -1117,7 +1177,7 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle); */ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -1125,4 +1185,4 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); /*! @}*/ -#endif /* _FSL_LPUART_H_ */ +#endif /* FSL_LPUART_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart_edma.c index 3df4bb190c..ec858aed8c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart_edma.c @@ -44,6 +44,12 @@ typedef union lpuart_to_lpflexcomm_edma static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; /* Array of LPUART handle. */ +#if (defined(LPUART20)) +#define LPUART_HANDLE_ARRAY_SIZE 21 +#else /* LPUART20 */ +#if (defined(LPUART13)) +#define LPUART_HANDLE_ARRAY_SIZE 14 +#else /* LPUART13 */ #if (defined(LPUART12)) #define LPUART_HANDLE_ARRAY_SIZE 13 #else /* LPUART12 */ @@ -97,6 +103,8 @@ static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; #endif /* LPUART 10 */ #endif /* LPUART 11 */ #endif /* LPUART 12 */ +#endif /* LPUART 13 */ +#endif /* LPUART 20 */ /*enable) | OPAMP_OPAMP_CTR_MODE(config->mode) | OPAMP_OPAMP_CTR_BIASC(config->trimOption) | OPAMP_OPAMP_CTR_INTREF(config->intRefVoltage) | OPAMP_OPAMP_CTR_PREF(config->posRefVoltage) | diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_opamp.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_opamp.h index 2c02d3b7da..c9767193d0 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_opamp.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_opamp.h @@ -1,11 +1,11 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2022, 2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_OPAMP_H_ -#define _FSL_OPAMP_H_ +#ifndef FSL_OPAMP_H_ +#define FSL_OPAMP_H_ #include "fsl_common.h" @@ -19,10 +19,10 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief OPAMP driver version. */ -#define FSL_OPAMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ +#define FSL_OPAMP_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @} */ /*! * @brief The enumeration of OPAMP mode, including low noise mode and high speed mode. @@ -138,31 +138,31 @@ typedef struct _opamp_config opamp_negative_gain_t negGain; /*!< Negative part programmable gain, please refer to @ref opamp_negative_gain_t. */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW - bool enableOutputSwitch; /*!< OPAMP out to negative gain resistor ladder switch.*/ -#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW */ + bool enableOutputSwitch; /*!< OPAMP out to negative gain resistor ladder switch.*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 - bool enablePosADCSw1; /*!< Positive part reference voltage switch to ADC channel or not. - - \b true Positive part reference voltage switch to ADC channel. - - \b false Positive part reference voltage do not switch to ADC channel. */ + bool enablePosADCSw1; /*!< Positive part reference voltage switch to ADC channel or not. + - \b true Positive part reference voltage switch to ADC channel. + - \b false Positive part reference voltage do not switch to ADC channel. */ #else bool enablePosADCSw; /*!< Positive part reference voltage switch to ADC channel or not. - \b true Positive part reference voltage switch to ADC channel. - \b false Positive part reference voltage do not switch to ADC channel. */ -#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 */ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 - bool enablePosADCSw2; /*!< Positive part reference voltage switch to ADC channel or not. - - \b true Positive part reference voltage switch to ADC channel. - - \b false Positive part reference voltage do not switch to ADC channel. */ -#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 */ + bool enablePosADCSw2; /*!< Positive part reference voltage switch to ADC channel or not. + - \b true Positive part reference voltage switch to ADC channel. + - \b false Positive part reference voltage do not switch to ADC channel. */ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN - bool enableRefBuffer; /*!< Reference buffer enable.*/ -#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN */ + bool enableRefBuffer; /*!< Reference buffer enable.*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL opamp_positive_input_channel_selection_t PosInputChannelSelection; /*!< Positive Input Channel Selection*/ #endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD - bool enableTriggerMode; /*!< Trigger Mode Enable.*/ -#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ + bool enableTriggerMode; /*!< Trigger Mode Enable.*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ } opamp_config_t; /******************************************************************************* @@ -211,7 +211,34 @@ void OPAMP_Deinit(OPAMP_Type *base); */ void OPAMP_GetDefaultConfig(opamp_config_t *config); -/* @} */ +/*! @} */ + +/*! + * @name Positive port gain and negative gain configuration. + * @{ + */ +/*! + * @brief Configure OPAMP positive port gain. + * + * @param base OPAMP peripheral base address. + * @param option OPAMP positive port gain. + */ +static inline void OPAMP_DoPosGainConfig(OPAMP_Type *base, opamp_positive_gain_t option) +{ + base->OPAMP_CTR = (((base->OPAMP_CTR) & (~OPAMP_OPAMP_CTR_PGAIN_MASK)) | OPAMP_OPAMP_CTR_PGAIN(option)); +} + +/*! + * @brief Configure OPAMP negative port gain. + * + * @param base OPAMP peripheral base address. + * @param option OPAMP negative port gain. + */ +static inline void OPAMP_DoNegGainConfig(OPAMP_Type *base, opamp_negative_gain_t option) +{ + base->OPAMP_CTR = (((base->OPAMP_CTR) & (~OPAMP_OPAMP_CTR_NGAIN_MASK)) | OPAMP_OPAMP_CTR_NGAIN(option)); +} +/*! @} */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN /*! @@ -236,7 +263,7 @@ static inline void OPAMP_EnableRefBuffer(OPAMP_Type *base, bool enable) base->OPAMP_CTR &= ~(uint32_t)OPAMP_OPAMP_CTR_BUFEN_MASK; } } -/* @} */ +/*! @} */ #endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN */ #if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD @@ -262,7 +289,7 @@ static inline void OPAMP_EnableTriggerMode(OPAMP_Type *base, bool enable) base->OPAMP_CTR &= ~(uint32_t)OPAMP_OPAMP_CTR_TRIGMD_MASK; } } -/* @} */ +/*! @} */ #endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ #if defined(__cplusplus) @@ -271,4 +298,4 @@ static inline void OPAMP_EnableTriggerMode(OPAMP_Type *base, bool enable) /*! @} */ -#endif /* _FSL_OPAMP_H_ */ +#endif /* FSL_OPAMP_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.c index c3acfb0e48..d978556afb 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2021 NXP + * Copyright 2018-2021, 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -16,6 +16,10 @@ #define FSL_COMPONENT_ID "platform.drivers.ostimer" #endif +#if defined(OSTIMER_RSTS) +#define OSTIMER_RESETS_ARRAY OSTIMER_RSTS +#endif + /* Typedef for interrupt handler. */ typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); @@ -62,6 +66,11 @@ static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; static ostimer_isr_t s_ostimerIsr; #endif +#if defined(OSTIMER_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_ostimerResets[] = OSTIMER_RESETS_ARRAY; +#endif + /******************************************************************************* * Code ******************************************************************************/ @@ -177,6 +186,10 @@ void OSTIMER_Init(OSTIMER_Type *base) CLOCK_EnableClock(kCLOCK_Sysctl); #endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(OSTIMER_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_ostimerResets[OSTIMER_GetInstance(base)]); +#endif } /*! @@ -362,20 +375,10 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) } } -#if defined(OSTIMER0) void OS_EVENT_DriverIRQHandler(void); void OS_EVENT_DriverIRQHandler(void) { - s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); + s_ostimerIsr(s_ostimerBases[0], s_ostimerHandle[0]); SDK_ISR_EXIT_BARRIER; } -#endif -#if defined(OSTIMER) -void OS_EVENT_DriverIRQHandler(void); -void OS_EVENT_DriverIRQHandler(void) -{ - s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); - SDK_ISR_EXIT_BARRIER; -} -#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.h index c74a793136..51b1f45503 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ostimer.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_OSTIMER_H_ -#define _FSL_OSTIMER_H_ +#ifndef FSL_OSTIMER_H_ +#define FSL_OSTIMER_H_ #include "fsl_common.h" @@ -21,10 +21,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief OSTIMER driver version. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @} */ /*! * @brief OSTIMER status flags. @@ -149,7 +149,7 @@ status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callb * value to gray code. * * @param base OSTIMER peripheral base address. - * @param count OSTIMER timer match value (Value is gray-code format). + * @param value OSTIMER timer match value (Value is gray-code format). */ static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) { @@ -262,7 +262,7 @@ uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); * @return none */ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -270,4 +270,4 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); /*! @}*/ -#endif /* _FSL_OSTIMER_H_ */ +#endif /* FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.c index bfdc89384c..2132ed2a1d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.c @@ -227,7 +227,7 @@ status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32 uint32_t regDiv = 0U; /* get divider */ - osr = 16U - osr; + osr = (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT) + 1U - osr; pdmClockRate = sampleRate_HZ * osr * 8U; regDiv = sourceClock_HZ / pdmClockRate; @@ -262,7 +262,8 @@ status_t PDM_SetSampleRate( PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv) { #if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) - uint8_t realOsr = 16U - (osr & (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT)); + uint8_t realOsr = (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT) + 1U - + (osr & (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT)); #endif uint32_t regDiv = clkDiv >> 1U; @@ -336,11 +337,15 @@ void PDM_Init(PDM_Type *base, const pdm_config_t *config) base->CTRL_1 |= PDM_CTRL_1_SRES_MASK; /* Set the configure settings */ - base->CTRL_1 = (base->CTRL_1 & (~PDM_CTRL_1_DOZEN_MASK)) | PDM_CTRL_1_DOZEN(config->enableDoze); - +#if !(defined(FSL_FEATURE_PDM_HAS_NO_DOZEN) && FSL_FEATURE_PDM_HAS_NO_DOZEN) + PDM_EnableDoze(base, config->enableDoze); +#endif base->CTRL_2 = (base->CTRL_2 & (~(PDM_CTRL_2_CICOSR_MASK | PDM_CTRL_2_QSEL_MASK))) | PDM_CTRL_2_CICOSR(config->cicOverSampleRate) | PDM_CTRL_2_QSEL(config->qualityMode); +#if defined(FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS) && FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS + base->CTRL_2 = (base->CTRL_2 & ~PDM_CTRL_2_DEC_BYPASS_MASK) | PDM_CTRL_2_DEC_BYPASS(config->enableFilterBypass); +#endif /* Set the watermark */ base->FIFO_CTRL = PDM_FIFO_CTRL_FIFOWMK(config->fifoWatermark); } @@ -356,6 +361,7 @@ void PDM_Init(PDM_Type *base, const pdm_config_t *config) void PDM_Deinit(PDM_Type *base) { /* disable PDM interface */ + PDM_DisableInterrupts(base, (uint32_t)kPDM_FIFOInterruptEnable | (uint32_t)kPDM_ErrorInterruptEnable); PDM_Enable(base, false); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.h index f7c263a188..d66a0585e4 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PDM_H_ -#define _FSL_PDM_H_ +#ifndef FSL_PDM_H_ +#define FSL_PDM_H_ #include "fsl_common.h" @@ -21,9 +21,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 8, 0)) /*!< Version 2.8.0 */ -/*@}*/ +/*! @{ */ +#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) /*!< Version 2.9.1 */ +/*! @} */ /*! @brief PDM XFER QUEUE SIZE */ #define PDM_XFER_QUEUE_SIZE (4U) @@ -31,9 +31,9 @@ /*! @brief PDM return status*/ enum { - kStatus_PDM_Busy = MAKE_STATUS(kStatusGroup_PDM, 0), /*!< PDM is busy. */ + kStatus_PDM_Busy = MAKE_STATUS(kStatusGroup_PDM, 0), /*!< PDM is busy. */ #if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) - kStatus_PDM_CLK_LOW = MAKE_STATUS(kStatusGroup_PDM, 1), /*!< PDM clock frequency low */ + kStatus_PDM_CLK_LOW = MAKE_STATUS(kStatusGroup_PDM, 1), /*!< PDM clock frequency low */ #endif kStatus_PDM_FIFO_ERROR = MAKE_STATUS(kStatusGroup_PDM, 2), /*!< PDM FIFO underrun or overflow */ kStatus_PDM_QueueFull = MAKE_STATUS(kStatusGroup_PDM, 3), /*!< PDM FIFO underrun or overflow */ @@ -41,8 +41,8 @@ enum kStatus_PDM_Output_ERROR = MAKE_STATUS(kStatusGroup_PDM, 5), /*!< PDM is output error */ kStatus_PDM_ChannelConfig_Failed = MAKE_STATUS(kStatusGroup_PDM, 6), /*!< PDM channel config failed */ #if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) - kStatus_PDM_HWVAD_VoiceDetected = MAKE_STATUS(kStatusGroup_PDM, 7), /*!< PDM hwvad voice detected */ - kStatus_PDM_HWVAD_Error = MAKE_STATUS(kStatusGroup_PDM, 8), /*!< PDM hwvad error */ + kStatus_PDM_HWVAD_VoiceDetected = MAKE_STATUS(kStatusGroup_PDM, 7), /*!< PDM hwvad voice detected */ + kStatus_PDM_HWVAD_Error = MAKE_STATUS(kStatusGroup_PDM, 8), /*!< PDM hwvad error */ #endif }; @@ -58,10 +58,10 @@ enum _pdm_internal_status { kPDM_StatusDfBusyFlag = (int)PDM_STAT_BSY_FIL_MASK, /*!< Decimation filter is busy processing data */ #if !(defined(FSL_FEATURE_PDM_HAS_NO_FIR_RDY) && FSL_FEATURE_PDM_HAS_NO_FIR_RDY) - kPDM_StatusFIRFilterReady = PDM_STAT_FIR_RDY_MASK, /*!< FIR filter data is ready */ + kPDM_StatusFIRFilterReady = PDM_STAT_FIR_RDY_MASK, /*!< FIR filter data is ready */ #endif #if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) - kPDM_StatusFrequencyLow = PDM_STAT_LOWFREQF_MASK, /*!< Mic app clock frequency not high enough */ + kPDM_StatusFrequencyLow = PDM_STAT_LOWFREQF_MASK, /*!< Mic app clock frequency not high enough */ #endif kPDM_StatusCh0FifoDataAvaliable = PDM_STAT_CH0F_MASK, /*!< channel 0 fifo data reached watermark level */ kPDM_StatusCh1FifoDataAvaliable = PDM_STAT_CH1F_MASK, /*!< channel 1 fifo data reached watermark level */ @@ -135,15 +135,15 @@ enum _pdm_range_status kPDM_RangeStatusUnderFlowCh6 = PDM_RANGE_STAT_RANGEUNF6_MASK, /*!< channel6 range status underflow */ kPDM_RangeStatusUnderFlowCh7 = PDM_RANGE_STAT_RANGEUNF7_MASK, /*!< channel7 range status underflow */ #endif - kPDM_RangeStatusOverFlowCh0 = PDM_RANGE_STAT_RANGEOVF0_MASK, /*!< channel0 range status overflow */ - kPDM_RangeStatusOverFlowCh1 = PDM_RANGE_STAT_RANGEOVF1_MASK, /*!< channel1 range status overflow */ - kPDM_RangeStatusOverFlowCh2 = PDM_RANGE_STAT_RANGEOVF2_MASK, /*!< channel2 range status overflow */ - kPDM_RangeStatusOverFlowCh3 = PDM_RANGE_STAT_RANGEOVF3_MASK, /*!< channel3 range status overflow */ + kPDM_RangeStatusOverFlowCh0 = PDM_RANGE_STAT_RANGEOVF0_MASK, /*!< channel0 range status overflow */ + kPDM_RangeStatusOverFlowCh1 = PDM_RANGE_STAT_RANGEOVF1_MASK, /*!< channel1 range status overflow */ + kPDM_RangeStatusOverFlowCh2 = PDM_RANGE_STAT_RANGEOVF2_MASK, /*!< channel2 range status overflow */ + kPDM_RangeStatusOverFlowCh3 = PDM_RANGE_STAT_RANGEOVF3_MASK, /*!< channel3 range status overflow */ #if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) - kPDM_RangeStatusOverFlowCh4 = PDM_RANGE_STAT_RANGEOVF4_MASK, /*!< channel4 range status overflow */ - kPDM_RangeStatusOverFlowCh5 = PDM_RANGE_STAT_RANGEOVF5_MASK, /*!< channel5 range status overflow */ - kPDM_RangeStatusOverFlowCh6 = PDM_RANGE_STAT_RANGEOVF6_MASK, /*!< channel6 range status overflow */ - kPDM_RangeStatusOverFlowCh7 = PDM_RANGE_STAT_RANGEOVF7_MASK, /*!< channel7 range status overflow */ + kPDM_RangeStatusOverFlowCh4 = PDM_RANGE_STAT_RANGEOVF4_MASK, /*!< channel4 range status overflow */ + kPDM_RangeStatusOverFlowCh5 = PDM_RANGE_STAT_RANGEOVF5_MASK, /*!< channel5 range status overflow */ + kPDM_RangeStatusOverFlowCh6 = PDM_RANGE_STAT_RANGEOVF6_MASK, /*!< channel6 range status overflow */ + kPDM_RangeStatusOverFlowCh7 = PDM_RANGE_STAT_RANGEOVF7_MASK, /*!< channel7 range status overflow */ #endif }; #else @@ -160,15 +160,15 @@ enum _pdm_output_status kPDM_OutputStatusUnderFlowCh6 = PDM_OUT_STAT_OUTUNF6_MASK, /*!< channel6 output status underflow */ kPDM_OutputStatusUnderFlowCh7 = PDM_OUT_STAT_OUTUNF7_MASK, /*!< channel7 output status underflow */ #endif - kPDM_OutputStatusOverFlowCh0 = PDM_OUT_STAT_OUTOVF0_MASK, /*!< channel0 output status overflow */ - kPDM_OutputStatusOverFlowCh1 = PDM_OUT_STAT_OUTOVF1_MASK, /*!< channel1 output status overflow */ - kPDM_OutputStatusOverFlowCh2 = PDM_OUT_STAT_OUTOVF2_MASK, /*!< channel2 output status overflow */ - kPDM_OutputStatusOverFlowCh3 = PDM_OUT_STAT_OUTOVF3_MASK, /*!< channel3 output status overflow */ + kPDM_OutputStatusOverFlowCh0 = PDM_OUT_STAT_OUTOVF0_MASK, /*!< channel0 output status overflow */ + kPDM_OutputStatusOverFlowCh1 = PDM_OUT_STAT_OUTOVF1_MASK, /*!< channel1 output status overflow */ + kPDM_OutputStatusOverFlowCh2 = PDM_OUT_STAT_OUTOVF2_MASK, /*!< channel2 output status overflow */ + kPDM_OutputStatusOverFlowCh3 = PDM_OUT_STAT_OUTOVF3_MASK, /*!< channel3 output status overflow */ #if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) - kPDM_OutputStatusOverFlowCh4 = PDM_OUT_STAT_OUTOVF4_MASK, /*!< channel4 output status overflow */ - kPDM_OutputStatusOverFlowCh5 = PDM_OUT_STAT_OUTOVF5_MASK, /*!< channel5 output status overflow */ - kPDM_OutputStatusOverFlowCh6 = PDM_OUT_STAT_OUTOVF6_MASK, /*!< channel6 output status overflow */ - kPDM_OutputStatusOverFlowCh7 = PDM_OUT_STAT_OUTOVF7_MASK, /*!< channel7 output status overflow */ + kPDM_OutputStatusOverFlowCh4 = PDM_OUT_STAT_OUTOVF4_MASK, /*!< channel4 output status overflow */ + kPDM_OutputStatusOverFlowCh5 = PDM_OUT_STAT_OUTOVF5_MASK, /*!< channel5 output status overflow */ + kPDM_OutputStatusOverFlowCh6 = PDM_OUT_STAT_OUTOVF6_MASK, /*!< channel6 output status overflow */ + kPDM_OutputStatusOverFlowCh7 = PDM_OUT_STAT_OUTOVF7_MASK, /*!< channel7 output status overflow */ #endif }; #endif @@ -186,10 +186,10 @@ typedef enum _pdm_dc_remover /*! @brief PDM DC remover configurations */ typedef enum _pdm_dc_remover { - kPDM_DcRemoverCutOff21Hz = 0U, /*!< DC remover cut off 21HZ */ - kPDM_DcRemoverCutOff83Hz = 1U, /*!< DC remover cut off 83HZ */ + kPDM_DcRemoverCutOff21Hz = 0U, /*!< DC remover cut off 21HZ */ + kPDM_DcRemoverCutOff83Hz = 1U, /*!< DC remover cut off 83HZ */ kPDM_DcRemoverCutOff152Hz = 2U, /*!< DC remover cut off 152HZ */ - kPDM_DcRemoverBypass = 3U, /*!< DC remover bypass */ + kPDM_DcRemoverBypass = 3U, /*!< DC remover bypass */ } pdm_dc_remover_t; #endif @@ -241,7 +241,7 @@ enum _pdm_data_width kPDM_DataWwidth24 = 3U, /*!< PDM data width 24bit */ kPDM_DataWwidth32 = 4U, /*!< PDM data width 32bit */ #else - kPDM_DataWdith16 = 2U, /*!< PDM data width 16bit */ + kPDM_DataWdith16 = 2U, /*!< PDM data width 16bit */ #endif }; @@ -264,6 +264,9 @@ typedef struct _pdm_config { bool enableDoze; /*!< This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted */ +#if defined(FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS) && FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS + bool enableFilterBypass; /*!< Switchable bypass path for the decimation filter */ +#endif uint8_t fifoWatermark; /*!< Watermark value for FIFO */ pdm_df_quality_mode_t qualityMode; /*!< Quality mode */ uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ @@ -303,9 +306,9 @@ typedef enum _pdm_hwvad_filter_status /*! @brief PDM voice activity detector user configuration structure */ typedef struct _pdm_hwvad_config { - uint8_t channel; /*!< Which channel uses voice activity detector */ - uint8_t initializeTime; /*!< Number of frames or samples to initialize voice activity detector. */ - uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ + uint8_t channel; /*!< Which channel uses voice activity detector */ + uint8_t initializeTime; /*!< Number of frames or samples to initialize voice activity detector. */ + uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ uint8_t inputGain; /*!< Voice activity detector input gain */ uint32_t frameTime; /*!< Voice activity frame time */ @@ -371,19 +374,19 @@ typedef struct _pdm_hwvad_notification /*! @brief PDM handle structure */ struct _pdm_handle { - uint32_t state; /*!< Transfer status */ - pdm_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ + uint32_t state; /*!< Transfer status */ + pdm_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ pdm_transfer_t pdmQueue[PDM_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ size_t transferSize[PDM_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ volatile uint8_t queueUser; /*!< Index for user to queue transfer */ volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ - uint32_t format; /*!< data format */ - uint8_t watermark; /*!< Watermark value */ - uint8_t startChannel; /*!< end channel */ - uint8_t channelNums; /*!< Enabled channel number */ + uint32_t format; /*!< data format */ + uint8_t watermark; /*!< Watermark value */ + uint8_t startChannel; /*!< end channel */ + uint8_t channelNums; /*!< Enabled channel number */ }; /******************************************************************************* @@ -453,6 +456,7 @@ static inline void PDM_Enable(PDM_Type *base, bool enable) } } +#if !(defined(FSL_FEATURE_PDM_HAS_NO_DOZEN) && FSL_FEATURE_PDM_HAS_NO_DOZEN) /*! * @brief Enables/disables DOZE. * @@ -471,7 +475,7 @@ static inline void PDM_EnableDoze(PDM_Type *base, bool enable) base->CTRL_1 &= ~PDM_CTRL_1_DOZEN_MASK; } } - +#endif /*! * @brief Enables/disables debug mode for PDM. * The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode. @@ -1210,4 +1214,4 @@ void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle); /*! @} */ -#endif /* _FSL_PDM_H_ */ +#endif /* FSL_PDM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.c index 3c8104b5f3..2081057c63 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.c @@ -15,8 +15,8 @@ /******************************************************************************* * Definitations ******************************************************************************/ -/* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) +/* Used for edma_tcd_t size aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + sizeof(edma_tcd_t)) & ~(sizeof(edma_tcd_t) - 1U)) /*tcd[pdmHandle->tcdDriver], 0, sizeof(edma_tcd_t)); pdmHandle->tcdDriver = (pdmHandle->tcdDriver + 1U) % pdmHandle->tcdNum; } - +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + pdmHandle->receivedBytes += + EDMA_TCD_BITER((&pdmHandle->tcd[pdmHandle->tcdDriver]), EDMA_TCD_TYPE(handle->base)) * + (EDMA_TCD_NBYTES((&pdmHandle->tcd[pdmHandle->tcdDriver]), EDMA_TCD_TYPE(handle->base)) & 0x3FFU); +#else pdmHandle->receivedBytes += pdmHandle->tcd[pdmHandle->tcdDriver].BITER * (pdmHandle->tcd[pdmHandle->tcdDriver].NBYTES & 0x3FFU); - +#endif /* If finished a block, call the callback function */ if (pdmHandle->callback != NULL) { @@ -216,6 +220,8 @@ void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, * note This interface returns immediately after the transfer initiates. Call * the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished. * + * Mcaro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL can control whether PDM is enabled internally or externally. + * * 1. Scatter gather case: * This functio support dynamic scatter gather and staic scatter gather, * a. for the dynamic scatter gather case: @@ -345,7 +351,25 @@ status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_ FSL_FEATURE_PDM_FIFO_WIDTH, (int16_t)destOffset, mappedChannel * (uint32_t)FSL_FEATURE_PDM_FIFO_WIDTH, currentTransfer->dataSize); } +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, (edma_tcd_t *)&handle->tcd[handle->tcdUser], &config, + (edma_tcd_t *)&handle->tcd[nextTcdIndex]); + if (mappedChannel > 1U) + { + EDMA_TcdSetMinorOffsetConfigExt(handle->dmaHandle->base, (edma_tcd_t *)&handle->tcd[handle->tcdUser], + &minorOffset); + + if (handle->interleaveType == kPDM_EDMAMultiChannelInterleavePerChannelBlock) + { + EDMA_TcdSetModuloExt(handle->dmaHandle->base, (edma_tcd_t *)&handle->tcd[handle->tcdUser], modulo, + kEDMA_ModuloDisable); + } + } + + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, (edma_tcd_t *)&handle->tcd[handle->tcdUser], + (uint32_t)kEDMA_MajorInterruptEnable); +#else EDMA_TcdSetTransferConfig((edma_tcd_t *)&handle->tcd[handle->tcdUser], &config, (edma_tcd_t *)&handle->tcd[nextTcdIndex]); @@ -360,6 +384,7 @@ status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_ } EDMA_TcdEnableInterrupts((edma_tcd_t *)&handle->tcd[handle->tcdUser], (uint32_t)kEDMA_MajorInterruptEnable); +#endif handle->tcdUser = nextTcdIndex; @@ -380,8 +405,10 @@ status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_ /* Enable DMA enable bit */ PDM_EnableDMA(base, true); +#if defined(MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL) && MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL /* enable PDM */ PDM_Enable(base, true); +#endif handle->state = (uint32_t)kPDM_Busy; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.h index 4da78192f9..b3d363f1ce 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pdm_edma.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PDM_EDMA_H_ -#define _FSL_PDM_EDMA_H_ +#ifndef FSL_PDM_EDMA_H_ +#define FSL_PDM_EDMA_H_ #include "fsl_edma.h" #include "fsl_pdm.h" @@ -21,9 +21,14 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_PDM_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) /*!< Version 2.6.1 */ -/*@}*/ +/*! @{ */ +#define FSL_PDM_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 3)) /*!< Version 2.6.3 */ +/*! @} */ + +/*! @brief the PDM enable position When calling PDM_TransferReceiveEDMA */ +#ifndef MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL +#define MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL 1U +#endif /*! @brief PDM edma handler */ typedef struct _pdm_edma_handle pdm_edma_handle_t; @@ -147,6 +152,8 @@ void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, * @note This interface returns immediately after the transfer initiates. Call * the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished. * + * Mcaro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL can control whether PDM is enabled internally or externally. + * * 1. Scatter gather case: * This functio support dynamic scatter gather and staic scatter gather, * a. for the dynamic scatter gather case: diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.c index 8ade9bcb1a..ece6c66243 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. + * Copyright 2016-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,18 +12,45 @@ #define FSL_COMPONENT_ID "platform.drivers.pint" #endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef FSL_FEATURE_PINT_NUMBER_OF_INSTANCE +#define FSL_FEATURE_PINT_NUMBER_OF_INSTANCE (1U) +#endif + +#if defined(GPIOINT_RSTS_N) +#define PINT_RESETS_ARRAY GPIOINT_RSTS_N +#elif defined(PINT_RSTS) +#define PINT_RESETS_ARRAY PINT_RSTS +#elif defined(GPIO_RSTS_N) +#define PINT_RESETS_ARRAY GPIO_RSTS_N +#endif + /******************************************************************************* * Variables ******************************************************************************/ +/*! @brief Array to map PINT instance number to base pointer. */ +static PINT_Type *const s_pintBases[] = PINT_BASE_PTRS; + +#if defined(PINT_RESETS_ARRAY) +/*! @brief Reset array */ +static const reset_ip_name_t s_pintResets[] = PINT_RESETS_ARRAY; +#endif + #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; /*! @brief Callback function array for SECPINT(s). */ static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - +#else /*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[] = PINT_IRQS; +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /*! @brief Callback function array for PINT(s). */ static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; @@ -32,9 +58,33 @@ static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; /******************************************************************************* * Code ******************************************************************************/ +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The PINT peripheral base address. + * @return PINT instance number starting from 0. + */ +static uint32_t PINT_GetInstance(PINT_Type *base) +{ + uint32_t instance; + for (instance = 0; instance < ARRAY_SIZE(s_pintBases); ++instance) + { + if (s_pintBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pintBases)); + + return instance; +} /*! - * brief Initialize PINT peripheral. + * brief Initialize PINT peripheral. * This function initializes the PINT peripheral and enables the clock. * @@ -44,15 +94,18 @@ static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; */ void PINT_Init(PINT_Type *base) { - uint32_t i; uint32_t pmcfg = 0; uint8_t pintcount = 0; + uint32_t instance; + uint32_t i; assert(base != NULL); - if (base == PINT) + instance = PINT_GetInstance(base); + + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear PINT callback array*/ + /* Clear PINT callback array */ for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) { s_pintCallback[i] = NULL; @@ -62,7 +115,7 @@ void PINT_Init(PINT_Type *base) { #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; - /* clear SECPINT callback array*/ + /* Clear SECPINT callback array */ for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) { s_secpintCallback[i] = NULL; @@ -82,65 +135,53 @@ void PINT_Init(PINT_Type *base) /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_GpioInt); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#if defined(PINT_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pintResets[instance]); +#endif /* PINT_RESETS_ARRAY */ #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_Gpio0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ } else { #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_Gpio_Sec); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } +#if defined(PINT_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pintResets[instance]); +#endif /* PINT_RESETS_ARRAY */ + #else - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_Pint); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ } else { /* if need config SECURE PINT device,then enable secure pint interrupt clock */ #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } + +#if defined(PINT_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pintResets[instance]); +#endif /* PINT_RESETS_ARRAY */ + #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ /* Disable all pattern match bit slices */ @@ -148,7 +189,7 @@ void PINT_Init(PINT_Type *base) } /*! - * brief Configure PINT peripheral pin interrupt. + * brief Configure PINT peripheral pin interrupt. * This function configures a given pin interrupt. * @@ -162,13 +203,14 @@ void PINT_Init(PINT_Type *base) void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) { assert(base != NULL); + uint32_t instance = PINT_GetInstance(base); /* Clear Rise and Fall flags first */ PINT_PinInterruptClrRiseFlag(base, intr); PINT_PinInterruptClrFallFlag(base, intr); /* Security PINT uses additional callback array */ - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { s_pintCallback[intr] = callback; } @@ -205,7 +247,7 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab } /*! - * brief Get PINT peripheral pin interrupt configuration. + * brief Get PINT peripheral pin interrupt configuration. * This function returns the configuration of a given pin interrupt. * @@ -218,6 +260,7 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab */ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) { + uint32_t instance = PINT_GetInstance(base); uint32_t mask; bool level; @@ -271,7 +314,7 @@ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_ } /* Security PINT uses additional callback array */ - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { *callback = s_pintCallback[pintr]; } @@ -284,7 +327,7 @@ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_ } /*! - * brief Configure PINT pattern match. + * brief Configure PINT pattern match. * This function configures a given pattern match bit slice. * @@ -301,6 +344,7 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ uint32_t pmcfg; uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + uint32_t instance = PINT_GetInstance(base); assert(base != NULL); @@ -330,7 +374,7 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ base->PMCFG = pmcfg; /* Save callback pointer */ - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) { @@ -349,7 +393,7 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ } /*! - * brief Get PINT pattern match configuration. + * brief Get PINT pattern match configuration. * This function returns the configuration of a given pattern match bit slice. * @@ -365,6 +409,7 @@ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pi uint32_t cfg_shift; uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + uint32_t instance = PINT_GetInstance(base); assert(base != NULL); @@ -383,7 +428,7 @@ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pi cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; } - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) { @@ -402,7 +447,7 @@ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pi } /*! - * brief Reset pattern match detection logic. + * brief Reset pattern match detection logic. * This function resets the pattern match detection logic if any of the product term is matching. * @@ -429,7 +474,7 @@ uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) } /*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. * This function clears the selected pin interrupt status. * @@ -451,7 +496,7 @@ void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) } /*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. * This function clears the status of all pin interrupts. * @@ -461,13 +506,14 @@ void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) */ void PINT_PinInterruptClrStatusAll(PINT_Type *base) { + uint32_t instance = PINT_GetInstance(base); uint32_t pinIntMode = 0; uint32_t pinIntStatus = 0; uint32_t pinIntCount = 0; uint32_t mask = 0; uint32_t i; - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; } @@ -494,7 +540,7 @@ void PINT_PinInterruptClrStatusAll(PINT_Type *base) } /*! - * brief Enable callback. + * brief Enable callback. * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored * as soon as they are enabled, the callback function is not enabled until this function is called. @@ -505,11 +551,12 @@ void PINT_PinInterruptClrStatusAll(PINT_Type *base) */ void PINT_EnableCallback(PINT_Type *base) { + uint32_t instance = PINT_GetInstance(base); uint32_t i; assert(base != NULL); - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) @@ -541,7 +588,7 @@ void PINT_EnableCallback(PINT_Type *base) } /*! - * brief enable callback by pin index. + * brief enable callback by pin index. * This function enables callback by pin index instead of enabling all pins. * @@ -558,7 +605,7 @@ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) /* Get the right security pint irq index in array */ - if (base == SECPINT) + if ((base == SECPINT) && ((uint32_t)pintIdx < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)) { pintIdx = (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); @@ -575,7 +622,7 @@ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) } /*! - * brief Disable callback. + * brief Disable callback. * This function disables the interrupt for the selected PINT peripheral. Although the pins are still * being monitored but the callback function is not called. @@ -586,11 +633,12 @@ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) */ void PINT_DisableCallback(PINT_Type *base) { + uint32_t instance = PINT_GetInstance(base); uint32_t i; assert(base != NULL); - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) (void)DisableIRQ(s_pintIRQ[0]); @@ -633,9 +681,11 @@ void PINT_DisableCallback(PINT_Type *base) */ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) { + uint32_t instance = PINT_GetInstance(base); + assert(base != NULL); - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) (void)DisableIRQ(s_pintIRQ[0]); @@ -658,7 +708,7 @@ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) } /*! - * brief Deinitialize PINT peripheral. + * brief Deinitialize PINT peripheral. * This function disables the PINT clock. * @@ -668,15 +718,16 @@ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) */ void PINT_Deinit(PINT_Type *base) { + uint32_t instance = PINT_GetInstance(base); uint32_t i; assert(base != NULL); /* Cleanup */ PINT_DisableCallback(base); - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { - /* clear PINT callback array*/ + /* Clear PINT callback array */ for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) { s_pintCallback[i] = NULL; @@ -685,7 +736,7 @@ void PINT_Deinit(PINT_Type *base) else { #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) - /* clear SECPINT callback array */ + /* Clear SECPINT callback array */ for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) { s_secpintCallback[i] = NULL; @@ -696,66 +747,41 @@ void PINT_Deinit(PINT_Type *base) #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_DisableClock(kCLOCK_GpioInt); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_DisableClock(kCLOCK_Gpio0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ } else { #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_DisableClock(kCLOCK_Gpio_Sec); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } #else - if (base == PINT) + if (instance < FSL_FEATURE_PINT_NUMBER_OF_INSTANCE) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_DisableClock(kCLOCK_Pint); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ } else { /* if need config SECURE PINT device,then enable secure pint interrupt clock */ #if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ @@ -765,19 +791,20 @@ void PINT_Deinit(PINT_Type *base) void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) { + uint32_t secPintIndex = FSL_FEATURE_PINT_NUMBER_OF_INSTANCE; uint32_t pmstatus = 0; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[secPintIndex]); /* Call user function */ if (s_secpintCallback[kPINT_SecPinInt0] != NULL) { s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); } - if ((SECPINT->ISEL & 0x1U) == 0x0U) + if ((s_pintBases[secPintIndex]->ISEL & 0x1U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); + PINT_PinInterruptClrStatus(s_pintBases[secPintIndex], kPINT_PinInt0); } SDK_ISR_EXIT_BARRIER; } @@ -787,19 +814,20 @@ void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) { + uint32_t secPintIndex = FSL_FEATURE_PINT_NUMBER_OF_INSTANCE; uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[secPintIndex]); /* Call user function */ if (s_secpintCallback[kPINT_SecPinInt1] != NULL) { s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); } - if ((SECPINT->ISEL & 0x1U) == 0x0U) + if ((s_pintBases[secPintIndex]->ISEL & 0x1U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); + PINT_PinInterruptClrStatus(s_pintBases[secPintIndex], kPINT_PinInt1); } SDK_ISR_EXIT_BARRIER; } @@ -809,24 +837,24 @@ void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) void PINT0_DriverIRQHandler(void); void PINT0_DriverIRQHandler(void) { - uint32_t flags = (PINT->IST & PINT_IST_PSTAT_MASK) | PINT_PatternMatchGetStatusAll(PINT); + uint32_t flags = (s_pintBases[0]->IST & PINT_IST_PSTAT_MASK) | PINT_PatternMatchGetStatusAll(s_pintBases[0]); uint32_t pmstatus; - for (uint32_t i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + for (uint8_t i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) { - if ((flags & (1UL << i)) != 0U) + if ((flags & (1UL << i)) != 0UL) { /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[i] != NULL) { s_pintCallback[i]((pint_pin_int_t)i, pmstatus); } - if ((PINT->ISEL & (1UL << i)) == 0x0U) + if ((s_pintBases[0]->ISEL & (1UL << i)) == 0x0UL) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)i); + PINT_PinInterruptClrStatus(s_pintBases[0], (pint_pin_int_t)i); } } } @@ -841,16 +869,16 @@ void PIN_INT0_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt0] != NULL) { s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); } - if ((PINT->ISEL & 0x1U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x1U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt0); } SDK_ISR_EXIT_BARRIER; } @@ -862,16 +890,16 @@ void PIN_INT1_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt1] != NULL) { s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); } - if ((PINT->ISEL & 0x2U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x2U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt1); } SDK_ISR_EXIT_BARRIER; } @@ -884,16 +912,16 @@ void PIN_INT2_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt2] != NULL) { s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); } - if ((PINT->ISEL & 0x4U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x4U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt2); } SDK_ISR_EXIT_BARRIER; } @@ -906,16 +934,16 @@ void PIN_INT3_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt3] != NULL) { s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); } - if ((PINT->ISEL & 0x8U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x8U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt3); } SDK_ISR_EXIT_BARRIER; } @@ -928,16 +956,16 @@ void PIN_INT4_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt4] != NULL) { s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); } - if ((PINT->ISEL & 0x10U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x10U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt4); } SDK_ISR_EXIT_BARRIER; } @@ -955,16 +983,16 @@ void PIN_INT5_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt5] != NULL) { s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); } - if ((PINT->ISEL & 0x20U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x20U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt5); } SDK_ISR_EXIT_BARRIER; } @@ -982,16 +1010,16 @@ void PIN_INT6_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt6] != NULL) { s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); } - if ((PINT->ISEL & 0x40U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x40U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt6); } SDK_ISR_EXIT_BARRIER; } @@ -1009,16 +1037,16 @@ void PIN_INT7_DriverIRQHandler(void) uint32_t pmstatus; /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + pmstatus = PINT_PatternMatchResetDetectLogic(s_pintBases[0]); /* Call user function */ if (s_pintCallback[kPINT_PinInt7] != NULL) { s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); } - if ((PINT->ISEL & 0x80U) == 0x0U) + if ((s_pintBases[0]->ISEL & 0x80U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + PINT_PinInterruptClrStatus(s_pintBases[0], kPINT_PinInt7); } SDK_ISR_EXIT_BARRIER; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.h index ede539cfaf..c3a3771f52 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pint.h @@ -1,13 +1,12 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP - * All rights reserved. + * Copyright 2016-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ +#ifndef FSL_PINT_H_ +#define FSL_PINT_H_ #include "fsl_common.h" @@ -23,18 +22,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 11)) -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U +/*! @{ */ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 13)) +/*! @} */ /* PININT Bit slice source register bits */ #define PININT_BITSLICE_SRC_START 8U @@ -180,7 +170,7 @@ extern "C" { #endif /*! - * @brief Initialize PINT peripheral. + * @brief Initialize PINT peripheral. * This function initializes the PINT peripheral and enables the clock. * @@ -191,7 +181,7 @@ extern "C" { void PINT_Init(PINT_Type *base); /*! - * @brief Configure PINT peripheral pin interrupt. + * @brief Configure PINT peripheral pin interrupt. * This function configures a given pin interrupt. * @@ -205,7 +195,7 @@ void PINT_Init(PINT_Type *base); void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); /*! - * @brief Get PINT peripheral pin interrupt configuration. + * @brief Get PINT peripheral pin interrupt configuration. * This function returns the configuration of a given pin interrupt. * @@ -219,7 +209,7 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); /*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. * This function clears the selected pin interrupt status. * @@ -231,7 +221,7 @@ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_ void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); /*! - * @brief Get Selected pin interrupt status. + * @brief Get Selected pin interrupt status. * This function returns the selected pin interrupt status. * @@ -246,7 +236,7 @@ static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_ } /*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. * This function clears the status of all pin interrupts. * @@ -257,7 +247,7 @@ static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_ void PINT_PinInterruptClrStatusAll(PINT_Type *base); /*! - * @brief Get all pin interrupts status. + * @brief Get all pin interrupts status. * This function returns the status of all pin interrupts. * @@ -272,7 +262,7 @@ static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) } /*! - * @brief Clear Selected pin interrupt fall flag. + * @brief Clear Selected pin interrupt fall flag. * This function clears the selected pin interrupt fall flag. * @@ -287,7 +277,7 @@ static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t } /*! - * @brief Get selected pin interrupt fall flag. + * @brief Get selected pin interrupt fall flag. * This function returns the selected pin interrupt fall flag. * @@ -302,7 +292,7 @@ static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_in } /*! - * @brief Clear all pin interrupt fall flags. + * @brief Clear all pin interrupt fall flags. * This function clears the fall flag for all pin interrupts. * @@ -316,7 +306,7 @@ static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) } /*! - * @brief Get all pin interrupt fall flags. + * @brief Get all pin interrupt fall flags. * This function returns the fall flag of all pin interrupts. * @@ -331,7 +321,7 @@ static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) } /*! - * @brief Clear Selected pin interrupt rise flag. + * @brief Clear Selected pin interrupt rise flag. * This function clears the selected pin interrupt rise flag. * @@ -346,7 +336,7 @@ static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t } /*! - * @brief Get selected pin interrupt rise flag. + * @brief Get selected pin interrupt rise flag. * This function returns the selected pin interrupt rise flag. * @@ -361,7 +351,7 @@ static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_in } /*! - * @brief Clear all pin interrupt rise flags. + * @brief Clear all pin interrupt rise flags. * This function clears the rise flag for all pin interrupts. * @@ -375,7 +365,7 @@ static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) } /*! - * @brief Get all pin interrupt rise flags. + * @brief Get all pin interrupt rise flags. * This function returns the rise flag of all pin interrupts. * @@ -390,7 +380,7 @@ static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) } /*! - * @brief Configure PINT pattern match. + * @brief Configure PINT pattern match. * This function configures a given pattern match bit slice. * @@ -403,7 +393,7 @@ static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); /*! - * @brief Get PINT pattern match configuration. + * @brief Get PINT pattern match configuration. * This function returns the configuration of a given pattern match bit slice. * @@ -416,7 +406,7 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); /*! - * @brief Get pattern match bit slice status. + * @brief Get pattern match bit slice status. * This function returns the status of selected bit slice. * @@ -431,7 +421,7 @@ static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_b } /*! - * @brief Get status of all pattern match bit slices. + * @brief Get status of all pattern match bit slices. * This function returns the status of all bit slices. * @@ -446,7 +436,7 @@ static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) } /*! - * @brief Reset pattern match detection logic. + * @brief Reset pattern match detection logic. * This function resets the pattern match detection logic if any of the product term is matching. * @@ -458,13 +448,13 @@ static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); /*! - * @brief Enable pattern match function. + * @brief Enable pattern match function. * This function enables the pattern match function. * * @param base Base address of the PINT peripheral. * - * @retval None. + * @retval None. */ static inline void PINT_PatternMatchEnable(PINT_Type *base) { @@ -472,13 +462,13 @@ static inline void PINT_PatternMatchEnable(PINT_Type *base) } /*! - * @brief Disable pattern match function. + * @brief Disable pattern match function. * This function disables the pattern match function. * * @param base Base address of the PINT peripheral. * - * @retval None. + * @retval None. */ static inline void PINT_PatternMatchDisable(PINT_Type *base) { @@ -486,13 +476,13 @@ static inline void PINT_PatternMatchDisable(PINT_Type *base) } /*! - * @brief Enable RXEV output. + * @brief Enable RXEV output. * This function enables the pattern match RXEV output. * * @param base Base address of the PINT peripheral. * - * @retval None. + * @retval None. */ static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) { @@ -500,13 +490,13 @@ static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) } /*! - * @brief Disable RXEV output. + * @brief Disable RXEV output. * This function disables the pattern match RXEV output. * * @param base Base address of the PINT peripheral. * - * @retval None. + * @retval None. */ static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) { @@ -514,7 +504,7 @@ static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) } /*! - * @brief Enable callback. + * @brief Enable callback. * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored * as soon as they are enabled, the callback function is not enabled until this function is called. @@ -526,7 +516,7 @@ static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) void PINT_EnableCallback(PINT_Type *base); /*! - * @brief Disable callback. + * @brief Disable callback. * This function disables the interrupt for the selected PINT peripheral. Although the pins are still * being monitored but the callback function is not called. @@ -538,7 +528,7 @@ void PINT_EnableCallback(PINT_Type *base); void PINT_DisableCallback(PINT_Type *base); /*! - * @brief Deinitialize PINT peripheral. + * @brief Deinitialize PINT peripheral. * This function disables the PINT clock. * @@ -549,7 +539,7 @@ void PINT_DisableCallback(PINT_Type *base); void PINT_Deinit(PINT_Type *base); /*! - * @brief enable callback by pin index. + * @brief enable callback by pin index. * This function enables callback by pin index instead of enabling all pins. * @@ -576,6 +566,6 @@ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); } #endif -/*@}*/ +/*! @} */ -#endif /* _FSL_PINT_H_ */ +#endif /* FSL_PINT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_plu.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_plu.h index 0c94d49091..9335bc6c0c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_plu.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_plu.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PLU_H_ -#define _FSL_PLU_H_ +#ifndef FSL_PLU_H_ +#define FSL_PLU_H_ #include "fsl_common.h" @@ -19,9 +19,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ #define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ - /*@}*/ + /*! @} */ /*! @brief Index of LUT */ typedef enum _plu_lut_index @@ -371,4 +371,4 @@ void PLU_ClearLatchedInterrupt(PLU_Type *base); /*! @}*/ -#endif /* _FSL_PLU_H_ */ +#endif /* FSL_PLU_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_port.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_port.h index cbc0bb464c..8eb512969d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_port.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_port.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2020, 2022 NXP + * Copyright 2016-2022, 2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PORT_H_ -#define _FSL_PORT_H_ +#ifndef FSL_PORT_H_ +#define FSL_PORT_H_ #include "fsl_common.h" @@ -25,10 +25,10 @@ #endif /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief PORT driver version. */ -#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) -/*@}*/ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*! @} */ #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE /*! @brief Internal resistor pull feature selection */ @@ -125,8 +125,12 @@ enum _port_lock_register /*! @brief Pin mux selection */ typedef enum _port_mux { +#if defined(FSL_FEATURE_PORT_PCR_MUX_GPIO) && (FSL_FEATURE_PORT_PCR_MUX_GPIO == 0) + kPORT_MuxAsGpio = 0U, /*!< Corresponding pin is configured as GPIO. */ +#else kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ +#endif kPORT_MuxAlt0 = 0U, /*!< Chip-specific */ kPORT_MuxAlt1 = 1U, /*!< Chip-specific */ kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ @@ -295,9 +299,10 @@ typedef enum _port_voltage_range extern "C" { #endif -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH /*! @name Configuration */ -/*@{*/ +/*! @{ */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER /*! @@ -423,14 +428,14 @@ static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t { assert(config); - if (mask & 0xffffU) + if (0U != ((uint32_t)mask & 0xffffU)) { - base->GICLR = ((uint32_t)(config << 16)) | (mask & 0xffffU); + base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU); } mask = mask >> 16; if (0U != mask) { - base->GICHR = ((uint32_t)(config << 16)) | (mask & 0xffffU); + base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU); } } #endif @@ -497,10 +502,10 @@ static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digit } #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ -/*@}*/ +/*! @} */ /*! @name Interrupt */ -/*@{*/ +/*! @{ */ #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) /*! @@ -668,7 +673,7 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base) } #endif /* FSL_FEATURE_PORT_SUPPORT_EFT */ -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -676,4 +681,4 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base) /*! @}*/ -#endif /* _FSL_PORT_H_ */ +#endif /* FSL_PORT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad.h index 18c122bb62..c4f2805468 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad.h @@ -1,12 +1,12 @@ /* - * Copyright 2018-2022 NXP + * Copyright 2018-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_POWERQUAD_H_ -#define _FSL_POWERQUAD_H_ +#ifndef FSL_POWERQUAD_H_ +#define FSL_POWERQUAD_H_ #if defined(__CC_ARM) @@ -29,9 +29,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version. */ -/*@}*/ +/*! @{ */ +#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version. */ +/*! @} */ /* For backword compatibility. */ #define PQ_VectorBiqaudDf2F32 PQ_VectorBiquadDf2F32 @@ -2465,11 +2465,13 @@ void PQ_VectorBiquadCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t leng /*! * @brief Processing function for the fixed inverse trigonometric. * + * Get the inverse tangent, the behavior is like c function atan. + * * @param base POWERQUAD peripheral base address * @param x value of opposite * @param y value of adjacent * @param iteration iteration times - * @return The return value is in the range of -2^27 to 2^27, which means -pi to pi. + * @return The return value is in the range of -2^26 to 2^26, which means -pi/2 to pi/2. * @note The sum of x and y should not exceed the range of int32_t. * @note Larger input number gets higher output accuracy, for example the arctan(0.5), * the result of PQ_ArctanFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more @@ -2484,7 +2486,7 @@ int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_ite * @param x value of opposite * @param y value of adjacent * @param iteration iteration times - * @return The return value is in the range of -2^27 to 2^27, which means -1 to 1. + * @return The return value is radians, 2^27 means pi. The range is -1.118 to 1.118 radians. * @note The sum of x and y should not exceed the range of int32_t. * @note Larger input number gets higher output accuracy, for example the arctanh(0.5), * the result of PQ_ArctanhFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more @@ -2492,6 +2494,24 @@ int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_ite */ int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); +/*! + * @brief Processing function for the fixed inverse trigonometric. + * + * Get the inverse tangent, it calculates the angle in radians for the quadrant. + * The behavior is like c function atan2. + * + * @param base POWERQUAD peripheral base address + * @param x value of opposite + * @param y value of adjacent + * @param iteration iteration times + * @return The return value is in the range of -2^27 to 2^27, which means -pi to pi. + * @note The sum of x and y should not exceed the range of int32_t. + * @note Larger input number gets higher output accuracy, for example the arctan(0.5), + * the result of PQ_Arctan2Fixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more + * accurate than PQ_Arctan2Fixed(POWERQUAD, 1, 2, kPQ_Iteration_24). + */ +int32_t PQ_Arctan2Fixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); + /*! * @brief Processing function for the fixed biquad. * @@ -2774,7 +2794,7 @@ void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void */ void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, const void *pData, void *pResult); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -2782,4 +2802,4 @@ void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, const voi /*! @}*/ -#endif /* _FSL_POWERQUAD_H_ */ +#endif /* FSL_POWERQUAD_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_data.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_data.h index e0bbb5b675..494a4549bf 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_data.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_data.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_POWERQUAD_DATA_H_ -#define _FSL_POWERQUAD_DATA_H_ +#ifndef FSL_POWERQUAD_DATA_H_ +#define FSL_POWERQUAD_DATA_H_ #include @@ -45,4 +45,4 @@ extern "C" { } #endif /* __cplusplus */ -#endif /* _FSL_POWERQUAD_DATA_H_ */ +#endif /* FSL_POWERQUAD_DATA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_math.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_math.c index 19d39f2e63..c9233bb073 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_math.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_powerquad_math.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2022 NXP + * Copyright 2018-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -872,7 +872,6 @@ int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_ite base->CORDIC_Z = 0U; base->CONTROL = (CP_CORDIC << 4U) | CORDIC_ARCTAN | CORDIC_ITER(iteration); - PQ_WaitDone(base); return (int32_t)base->CORDIC_Z; } @@ -883,6 +882,26 @@ int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_it base->CORDIC_Z = 0U; base->CONTROL = (CP_CORDIC << 4U) | CORDIC_ARCTANH | CORDIC_ITER(iteration); - PQ_WaitDone(base); return (int32_t)base->CORDIC_Z; } + +int32_t PQ_Arctan2Fixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) +{ + int32_t result; + + result = PQ_ArctanFixed(base, x, y, iteration); + + if (x < 0) + { + if (y < 0) + { + result -= 0x08000000; + } + else + { + result += 0x08000000; + } + } + + return result; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.c index 43cfb60f1d..de5ff296b3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.c @@ -1,5 +1,5 @@ /* - * Copyright 2020 NXP + * Copyright 2020,2023 NXP * All rights reserved. * * @@ -134,6 +134,10 @@ status_t PUF_Init(PUF_Type *base, puf_config_t *conf) /* Enable PUF clock */ CLOCK_EnableClock(kCLOCK_Puf); + + /* Clear the PUF peripheral reset */ + RESET_ClearPeripheralReset(kPUF_RST_SHIFT_RSTn); + /* Reset PUF */ #if defined(FSL_FEATURE_PUF_HAS_RESET) && FSL_FEATURE_PUF_HAS_RESET RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); @@ -193,7 +197,7 @@ void PUF_Deinit(PUF_Type *base, puf_config_t *conf) * * @param base PUF peripheral base address * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the enroll operation. * @return Status of enroll operation. */ @@ -203,7 +207,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo uint32_t *activationCodeAligned = NULL; register uint32_t temp32 = 0; - /* check that activation code buffer size is at least 996 bytes */ + /* check that activation code buffer size is at least FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) { return kStatus_InvalidArgument; @@ -267,7 +271,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo * * @param base PUF peripheral base address * @param[in] activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the start operation. * return Status of start operation. */ @@ -277,13 +281,13 @@ status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activat const uint32_t *activationCodeAligned = NULL; register uint32_t temp32 = 0; - /* check that activation code size is at least 996 bytes */ + /* check that activation code size is at least FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) { return kStatus_InvalidArgument; } - /* Set activationCodeSize to 996 bytes */ + /* Set activationCodeSize to FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ activationCodeSize = PUF_ACTIVATION_CODE_SIZE; /* only work with aligned activationCode */ @@ -964,10 +968,10 @@ status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel) sec_lock_option = SEC_LOCK_PATTERN | securityLevel; /* Apply setings */ - PUF_CTRL->SEC_LOCK = sec_lock_option; + base->SEC_LOCK = sec_lock_option; /* Check if the security level is same as the level written */ - if (securityLevel != PUF_CTRL->SEC_LOCK) + if (securityLevel != base->SEC_LOCK) { return kStatus_Fail; } @@ -988,7 +992,7 @@ status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel) * @param appCtxMask Value of the Application defined context mask. * @return Status of the test operation. */ -status_t PUF_SetCtxMask(PUF_CTRL_Type *base, uint32_t appCtxMask) +status_t PUF_SetCtxMask(PUF_Type *base, uint32_t appCtxMask) { base->APP_CTX_MASK = appCtxMask; diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.h index 1865de0a4b..de4ea12e54 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_puf_v3.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018,2023 NXP * All rights reserved. * * @@ -22,17 +22,21 @@ * @{ */ /*! @name Driver version */ -/*@{*/ -/*! @brief PUFv3 driver version. Version 2.0.0. +/*! @{ */ +/*! @brief PUFv3 driver version. Version 2.0.2. * - * Current version: 2.0.0 + * Current version: 2.0.2 * * Change log: + * - 2.0.2 + * - Fix MISRA issue in driver. + * - 2.0.1 + * - Fix PUF initialization issue and update driver to reflect SoC header changes. * - 2.0.0 * - Initial version. */ -#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @} */ #define kPUF_EndianLittle (0x0u) #define kPUF_EndianBig (0x1u) @@ -81,7 +85,7 @@ typedef struct uint32_t userCtx1; } puf_key_ctx_t; -#define PUF_ACTIVATION_CODE_SIZE 1000u +#define PUF_ACTIVATION_CODE_SIZE (size_t)(FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE) #define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((0x34u + (x)) + 0x10u * ((x) / 0x32u)) #define SEC_LOCK_PATTERN 0xAC50u @@ -145,7 +149,7 @@ void PUF_Deinit(PUF_Type *base, puf_config_t *conf); * * @param base PUF peripheral base address * @param[out] activationCode Word aligned address of the resulting activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the enroll operation. * @return Status of enroll operation. */ @@ -160,7 +164,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo * * @param base PUF peripheral base address * @param[in] activationCode Word aligned address of the input activation code. - * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 996 bytes. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. * @param score Value of the PUF Score that was obtained during the start operation. * return Status of start operation. */ @@ -281,7 +285,7 @@ status_t PUF_Test(PUF_Type *base, uint8_t *score); * @param mask Mask of parameters which should be blocked until power-cycle. * @return Status of the test operation. */ -static inline void PUF_BlockCommand(PUF_CTRL_Type *base, uint32_t mask) +static inline void PUF_BlockCommand(PUF_Type *base, uint32_t mask) { base->CONFIG |= mask; } @@ -312,7 +316,7 @@ status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel); * @param appCtxMask Value of the Application defined context mask. * @return Status of the test operation. */ -status_t PUF_SetCtxMask(PUF_CTRL_Type *base, uint32_t appCtxMask); +status_t PUF_SetCtxMask(PUF_Type *base, uint32_t appCtxMask); #if defined(__cplusplus) } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.c index 22dc817c30..7fe51bcc77 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.c @@ -25,6 +25,14 @@ */ static uint32_t PWM_GetInstance(PWM_Type *base); +#if defined(PWM_RSTS) +#define PWM_RESETS_ARRAY PWM_RSTS +#elif defined(FLEXPWM_RSTS) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS +#elif defined(FLEXPWM_RSTS_N) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS_N +#endif + /******************************************************************************* * Variables ******************************************************************************/ @@ -36,6 +44,11 @@ static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(PWM_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_pwmResets[] = PWM_RESETS_ARRAY; +#endif + /*! @brief Temporary PWM duty cycle. */ static uint8_t s_pwmGetPwmDutyCycle[FSL_FEATURE_PWM_SUBMODULE_COUNT][PWM_SUBMODULE_CHANNEL] = {{0}}; @@ -80,6 +93,165 @@ static uint32_t PWM_GetInstance(PWM_Type *base) return instance; } +/*! + * brief Set register about period on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + */ +static void PWM_SetPeriodRegister(PWM_Type *base, pwm_submodule_t subModule, pwm_mode_t mode, uint16_t pulseCnt) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + default: + assert(false); + break; + } +} + +/*! + * brief Set register about dutycycle on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + */ +static void PWM_SetDutycycleRegister(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t mode, + uint16_t pulseCnt, + uint16_t pwmHighPulse) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM dutycycle for a signed center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL3 = (pwmHighPulse / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL5 = (pwmHighPulse / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_CenterAligned: + /* Setup the PWM dutycycle for an unsigned center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_SignedEdgeAligned: + modulo = (pulseCnt >> 1U); + + /* Setup the PWM dutycycle for a signed edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM dutycycle for a unsigned edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + default: + assert(false); + break; + } +} + /*! * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. * @@ -114,6 +286,10 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(PWM_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pwmResets[PWM_GetInstance(base)]); +#endif + /* Clear the fault status flags */ base->FSTS |= PWM_FSTS_FFLAG_MASK; @@ -184,7 +360,12 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t base->SM[subModule].CTRL = reg; /* Set PWM output normal */ +#if defined(PWM_MASK_UPDATE_MASK) + base->MASK &= (uint16_t)(~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK | + PWM_MASK_UPDATE_MASK_MASK)); +#else base->MASK &= ~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK); +#endif base->DTSRCSEL = 0U; @@ -280,7 +461,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config) * Array size should not be more than 2 as each submodule has 2 pins to output PWM * param mode PWM operation mode, options available in enumeration ::pwm_mode_t * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz PWM main counter clock in Hz. + * param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. * * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise */ @@ -299,7 +482,6 @@ status_t PWM_SetupPwm(PWM_Type *base, uint32_t pwmClock; uint16_t pulseCnt = 0, pwmHighPulse = 0; - uint16_t modulo = 0; uint8_t i, polarityShift = 0, outputEnableShift = 0; for (i = 0; i < numOfChnls; i++) @@ -322,114 +504,15 @@ status_t PWM_SetupPwm(PWM_Type *base, pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U; /* Setup the different match registers to generate the PWM signal */ - switch (mode) + if (i == 0U) { - case kPWM_SignedCenterAligned: - /* Setup the PWM period for a signed center aligned signal */ - if (i == 0U) - { - modulo = (pulseCnt >> 1U); - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = PWM_GetComplementU16(modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = modulo - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL3 = (pwmHighPulse / 2U); - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL5 = (pwmHighPulse / 2U); - } - break; - case kPWM_CenterAligned: - /* Setup the PWM period for an unsigned center aligned signal */ - /* Indicates the start of the PWM period */ - if (i == 0U) - { - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2U); - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = pulseCnt - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); - } - else - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); - } - break; - case kPWM_SignedEdgeAligned: - /* Setup the PWM period for a signed edge aligned signal */ - if (i == 0U) - { - modulo = (pulseCnt >> 1U); - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = PWM_GetComplementU16(modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = modulo - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - break; - case kPWM_EdgeAligned: - /* Setup the PWM period for a unsigned edge aligned signal */ - /* Indicates the start of the PWM period */ - if (i == 0U) - { - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2U); - /* Indicates the end of the PWM period */ - /* The change during the end to start of the PWM period requires a count time */ - base->SM[subModule].VAL1 = pulseCnt - 1U; - } - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - break; - default: - assert(false); - break; + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, mode, pulseCnt); } + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, chnlParams->pwmChannel, mode, pulseCnt, pwmHighPulse); + /* Setup register shift values based on the channel being configured. * Also setup the deadtime value */ @@ -636,98 +719,96 @@ void PWM_UpdatePwmDutycycleHighAccuracy( pulseCnt = modulo * 2U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL3 = (pwmHighPulse / 2U); - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); - base->SM[subModule].VAL5 = (pwmHighPulse / 2U); - } - else - { - assert(false); - } break; case kPWM_CenterAligned: pulseCnt = base->SM[subModule].VAL1 + 1U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); - } - else - { - assert(false); - } break; case kPWM_SignedEdgeAligned: modulo = base->SM[subModule].VAL1 + 1U; pulseCnt = modulo * 2U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); - base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; - } - else - { - assert(false); - } break; case kPWM_EdgeAligned: pulseCnt = base->SM[subModule].VAL1 + 1U; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else if (pwmSignal == kPWM_PwmB) - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - else - { - assert(false); - } break; default: assert(false); break; } + + /* Update register about dutycycle */ + if (kPWM_PwmA == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmA, currPwmMode, pulseCnt, pwmHighPulse); + } + else if (kPWM_PwmB == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmB, currPwmMode, pulseCnt, pwmHighPulse); + } + else + { + ; /* Intentional empty */ + } + if (kPWM_PwmX != pwmSignal) { /* Get the pwm duty cycle */ - s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle / 65535U); + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle * 100U / 65535U); } } +/*! + * brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original dutycycle or update new dutycycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle) +{ + uint16_t pwmHighPulse = 0; + + assert(pwmSignal != kPWM_PwmX); + + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, currPwmMode, pulseCnt); + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, pwmSignal, currPwmMode, pulseCnt, pwmHighPulse); + + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)((dutyCycle * 100U) / 65535U); +} + /*! * brief Sets up the PWM input capture * @@ -747,6 +828,7 @@ void PWM_SetupInputCapture(PWM_Type *base, uint16_t reg = 0; switch (pwmChannel) { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA case kPWM_PwmA: /* Setup the capture paramters for PWM A pin */ reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | @@ -768,6 +850,8 @@ void PWM_SetupInputCapture(PWM_Type *base, /* Setup PWM A pin for input capture */ base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB case kPWM_PwmB: /* Setup the capture paramters for PWM B pin */ reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | @@ -789,6 +873,8 @@ void PWM_SetupInputCapture(PWM_Type *base, /* Setup PWM B pin for input capture */ base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX case kPWM_PwmX: reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | @@ -809,6 +895,7 @@ void PWM_SetupInputCapture(PWM_Type *base, /* Setup PWM X pin for input capture */ base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ default: assert(false); break; @@ -1213,7 +1300,9 @@ void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_presc */ void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero) { +#if !defined(PWM_MASK_UPDATE_MASK) uint16_t reg = base->SM[subModule].CTRL2; +#endif uint16_t mask; if (kPWM_PwmA == pwmChannel) @@ -1240,12 +1329,17 @@ void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_ base->MASK &= ~mask; } +#if defined(PWM_MASK_UPDATE_MASK) + /* Update output mask bits immediately with UPDATE_MASK bit */ + base->MASK |= PWM_MASK_UPDATE_MASK(0x01UL << (uint8_t)subModule); +#else /* Select local force signal */ base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; /* Issue a local Force trigger event */ base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; /* Restore the source of FORCE OUTPUT signal */ base->SM[subModule].CTRL2 = reg; +#endif } /*! @@ -1326,3 +1420,72 @@ void PWM_SetChannelOutput(PWM_Type *base, /* Restore the source of FORCE OUTPUT signal */ base->SM[subModule].CTRL2 = reg; } + +#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY +/*! + * brief This function set the phase delay from the master sync signal of submodule 0. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param delayCycles Number of cycles delayed from submodule 0. + * + * return kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; + * kStatus_Success if set phase delay success + */ +status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles) +{ + assert(subModule != kPWM_Module_0); + uint16_t reg = base->SM[subModule].CTRL2; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + if (base->SM[kPWM_Module_0].VAL1 < delayCycles) + { + return kStatus_Fail; + } + else + { + /* + * ERR051989: When the value of the phase delay register SMxPHASEDLY is reduced from a + * non-zero value to 0 and submodule x reload source is from submodule0, the submodule + * x may output an unexpected wide PWM pulse. The workaround is set SMxPHASEDLY=1, + * SMxINIT=SM0INIT-1, SMxVALy=SM0VALy-1 (x=1,2,3, y=0,1,2,3,4,5). + */ +#if defined(FSL_FEATURE_PWM_HAS_ERRATA_51989) && FSL_FEATURE_PWM_HAS_ERRATA_51989 + if (delayCycles == 0 && + ((base->SM[subModule].CTRL2 & PWM_CTRL2_RELOAD_SEL_MASK) >> PWM_CTRL2_RELOAD_SEL_SHIFT) == 1U) + { + base->SM[subModule].PHASEDLY = 1U; + base->SM[subModule].INIT = base->SM[0].INIT - 1U; + base->SM[subModule].VAL0 = base->SM[0].VAL0 - 1U; + base->SM[subModule].VAL1 = base->SM[0].VAL1 - 1U; + base->SM[subModule].VAL2 = base->SM[0].VAL2 - 1U; + base->SM[subModule].VAL3 = base->SM[0].VAL3 - 1U; + base->SM[subModule].VAL4 = base->SM[0].VAL4 - 1U; + base->SM[subModule].VAL5 = base->SM[0].VAL5 - 1U; + } + else + { + base->SM[subModule].PHASEDLY = delayCycles; + } +#else + base->SM[subModule].PHASEDLY = delayCycles; +#endif + } + + /* Select the master sync signal as the source for initialization */ + reg = (reg & ~(uint16_t)PWM_CTRL2_INIT_SEL_MASK) | PWM_CTRL2_INIT_SEL(2); + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore the source of phase delay register intialization */ + base->SM[subModule].CTRL2 = reg; + return kStatus_Success; +} +#endif /* FSL_FEATURE_PWM_HAS_PHASE_DELAY */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.h index f90f384a4a..9e0b12ba65 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_pwm.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_PWM_H_ -#define _FSL_PWM_H_ +#ifndef FSL_PWM_H_ +#define FSL_PWM_H_ #include "fsl_common.h" @@ -19,9 +19,9 @@ * Definitions ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) /*!< Version 2.5.1 */ -/*@}*/ +/*! @{ */ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) /*!< Version 2.8.4 */ +/*! @} */ /*! Number of bits per submodule for software output control */ #define PWM_SUBMODULE_SWCONTROL_WIDTH 2 @@ -34,7 +34,9 @@ typedef enum _pwm_submodule kPWM_Module_0 = 0U, /*!< Submodule 0 */ kPWM_Module_1, /*!< Submodule 1 */ kPWM_Module_2, /*!< Submodule 2 */ +#if defined(FSL_FEATURE_PWM_SUBMODULE_COUNT) && (FSL_FEATURE_PWM_SUBMODULE_COUNT > 3U) kPWM_Module_3 /*!< Submodule 3 */ +#endif /* FSL_FEATURE_PWM_SUBMODULE_COUNT */ } pwm_submodule_t; /*! @brief List of PWM channels in each module */ @@ -220,12 +222,18 @@ typedef enum _pwm_interrupt_enable kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ @@ -243,12 +251,18 @@ typedef enum _pwm_status_flags kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ @@ -261,12 +275,18 @@ typedef enum _pwm_status_flags /*! @brief List of PWM DMA options */ typedef enum _pwm_dma_enable { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX kPWM_CaptureX0DMAEnable = (1U << 0), /*!< PWM capture X0 DMA */ kPWM_CaptureX1DMAEnable = (1U << 1), /*!< PWM capture X1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB kPWM_CaptureB0DMAEnable = (1U << 2), /*!< PWM capture B0 DMA */ kPWM_CaptureB1DMAEnable = (1U << 3), /*!< PWM capture B1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA kPWM_CaptureA0DMAEnable = (1U << 4), /*!< PWM capture A0 DMA */ kPWM_CaptureA1DMAEnable = (1U << 5) /*!< PWM capture A1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ } pwm_dma_enable_t; /*! @brief List of PWM capture DMA enable source select */ @@ -488,7 +508,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config); * Array size should not be more than 2 as each submodule has 2 pins to output PWM * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz PWM main counter clock in Hz. + * @param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. * * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise */ @@ -501,14 +523,14 @@ status_t PWM_SetupPwm(PWM_Type *base, uint32_t srcClock_Hz); /*! - * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.. + * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle. * * @param base PWM peripheral base address * @param subModule PWM submodule to configure * @param pwmChannel PWM channel to configure * @param pwmFreq_Hz PWM signal frequency in Hz * @param srcClock_Hz PWM main counter clock in Hz. - * @param shiftvalue Phase shift value + * @param shiftvalue Phase shift value, range in 0 ~ 50 * @param doSync true: Set LDOK bit for the submodule list; * false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update. * @@ -561,6 +583,36 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base, void PWM_UpdatePwmDutycycleHighAccuracy( PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle); +/*! + * @brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * @param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * @param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original duty cycle or update new duty cycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle); + /*! @}*/ /*! @@ -1216,10 +1268,105 @@ void PWM_SetChannelOutput(PWM_Type *base, pwm_channels_t pwmChannel, pwm_output_state_t outputstate); +#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY +/*! + * @brief This function set the phase delay from the master sync signal of submodule 0. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param delayCycles Number of cycles delayed from submodule 0. + * + * @return kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; + * kStatus_Success if set phase delay success + */ +status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles); +#endif + +#if defined(FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE) && FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE +/*! + * @brief This function set the number of consecutive samples that must agree prior to the input filter. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param filterSampleCount Number of consecutive samples. + */ +static inline void PWM_SetFilterSampleCount(PWM_Type *base, + pwm_channels_t pwmChannel, + pwm_submodule_t subModule, + uint8_t filterSampleCount) +{ + switch(pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} + +/*! + * @brief This function set the sampling period of the fault pin input filter. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param filterSamplePeriod Sampling period of input filter. + */ +static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, + pwm_channels_t pwmChannel, + pwm_submodule_t subModule, + uint8_t filterSamplePeriod) +{ + switch(pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_PER_MASK); + base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_PER_MASK); + base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_PER_MASK); + base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} +#endif + #if defined(__cplusplus) } #endif /*! @}*/ -#endif /* _FSL_PWM_H_ */ +#endif /* FSL_PWM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_qdc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_qdc.c new file mode 100644 index 0000000000..75158b976c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_qdc.c @@ -0,0 +1,645 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_qdc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.qdc" +#endif + +#define QDC_CTRL_W1C_FLAGS (QDC_CTRL_HIRQ_MASK | QDC_CTRL_XIRQ_MASK | QDC_CTRL_DIRQ_MASK | QDC_CTRL_CMPIRQ_MASK) +#if (defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) +#define QDC_CTRL2_W1C_FLAGS (QDC_CTRL2_ROIRQ_MASK | QDC_CTRL2_RUIRQ_MASK) +#else +#define QDC_CTRL2_W1C_FLAGS (QDC_CTRL2_SABIRQ_MASK | QDC_CTRL2_ROIRQ_MASK | QDC_CTRL2_RUIRQ_MASK) +#endif + +#if defined(QDC_RSTS) +#define QDC_RESETS_ARRAY QDC_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for QDC module. + * + * @param base QDC peripheral base address + */ +static uint32_t QDC_GetInstance(QDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to QDC bases for each instance. */ +static QDC_Type *const s_qdcBases[] = QDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to QDC clocks for each instance. */ +static const clock_ip_name_t s_qdcClocks[] = QDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(QDC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_qdcResets[] = QDC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t QDC_GetInstance(QDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_qdcBases); instance++) + { + if (s_qdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_qdcBases)); + + return instance; +} + +/*! + * brief Initialization for the QDC module. + * + * This function is to make the initialization for the QDC module. It should be called firstly before any operation to + * the QDC with the operations like: + * - Enable the clock for QDC module. + * - Configure the QDC's working attributes. + * + * param base QDC peripheral base address. + * param config Pointer to configuration structure. See to "qdc_config_t". + */ +void QDC_Init(QDC_Type *base, const qdc_config_t *config) +{ + assert(NULL != config); + + uint16_t tmp16; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_qdcClocks[QDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(QDC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_qdcResets[QDC_GetInstance(base)]); +#endif + + /* QDC_CTRL. */ + tmp16 = base->CTRL & (uint16_t)(~(QDC_CTRL_W1C_FLAGS | QDC_CTRL_HIP_MASK | QDC_CTRL_HNE_MASK | QDC_CTRL_REV_MASK | + QDC_CTRL_PH1_MASK | QDC_CTRL_XIP_MASK | QDC_CTRL_XNE_MASK | QDC_CTRL_WDE_MASK)); + /* For HOME trigger. */ + if (kQDC_HOMETriggerDisabled != config->HOMETriggerMode) + { + tmp16 |= QDC_CTRL_HIP_MASK; + if (kQDC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) + { + tmp16 |= QDC_CTRL_HNE_MASK; + } + } + /* For encoder work mode. */ + if (config->enableReverseDirection) + { + tmp16 |= QDC_CTRL_REV_MASK; + } + if (kQDC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) + { + tmp16 |= QDC_CTRL_PH1_MASK; + } + /* For INDEX trigger. */ + if (kQDC_INDEXTriggerDisabled != config->INDEXTriggerMode) + { + tmp16 |= QDC_CTRL_XIP_MASK; + if (kQDC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) + { + tmp16 |= QDC_CTRL_XNE_MASK; + } + } + /* Watchdog. */ + if (config->enableWatchdog) + { + tmp16 |= QDC_CTRL_WDE_MASK; + base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ + } + base->CTRL = tmp16; + + /* QDC_FILT. */ + base->FILT = QDC_FILT_FILT_CNT(config->filterCount) | QDC_FILT_FILT_PER(config->filterSamplePeriod) +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + | QDC_FILT_FILT_PRSC(config->filterPrescaler) +#endif + ; + + /* QDC_CTRL2. */ + tmp16 = base->CTRL2 & (uint16_t)(~(QDC_CTRL2_W1C_FLAGS | QDC_CTRL2_OUTCTL_MASK | QDC_CTRL2_REVMOD_MASK | + QDC_CTRL2_MOD_MASK | QDC_CTRL2_UPDPOS_MASK | QDC_CTRL2_UPDHLD_MASK)); + if (kQDC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) + { + tmp16 |= QDC_CTRL2_OUTCTL_MASK; + } + if (kQDC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) + { + tmp16 |= QDC_CTRL2_REVMOD_MASK; + } + if (config->enableModuloCountMode) + { + tmp16 |= QDC_CTRL2_MOD_MASK; + /* Set modulus value. */ + base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ + base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ + } + if (config->enableTRIGGERClearPositionCounter) + { + tmp16 |= QDC_CTRL2_UPDPOS_MASK; + } + if (config->enableTRIGGERClearHoldPositionCounter) + { + tmp16 |= QDC_CTRL2_UPDHLD_MASK; + } + base->CTRL2 = tmp16; + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + /* QDC_CTRL3. */ + tmp16 = base->CTRL3 & (uint16_t)(~(QDC_CTRL3_PMEN_MASK | QDC_CTRL3_PRSC_MASK)); + if (config->enablePeriodMeasurementFunction) + { + tmp16 |= QDC_CTRL3_PMEN_MASK; + /* Set prescaler value. */ + tmp16 |= ((uint16_t)config->prescalerValue << QDC_CTRL3_PRSC_SHIFT); + } + base->CTRL3 = tmp16; +#endif + + /* QDC_UCOMP & QDC_LCOMP. */ + base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ + base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ + + /* QDC_UINIT & QDC_LINIT. */ + base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ + base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ +} + +/*! + * brief De-initialization for the QDC module. + * + * This function is to make the de-initialization for the QDC module. It could be called when QDC is no longer used with + * the operations like: + * - Disable the clock for QDC module. + * + * param base QDC peripheral base address. + */ +void QDC_Deinit(QDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_qdcClocks[QDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get an available pre-defined settings for QDC's configuration. + * + * This function initializes the QDC configuration structure with an available settings, the default value are: + * code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * config->prescalerValue = kQDC_ClockDiv1; + * config->enablePeriodMeasurementFunction = true; + * endcode + * param config Pointer to a variable of configuration structure. See to "qdc_config_t". + */ +void QDC_GetDefaultConfig(qdc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableReverseDirection = false; + config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; + config->enableTRIGGERClearHoldPositionCounter = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + config->prescalerValue = kQDC_ClockDiv1; + config->enablePeriodMeasurementFunction = true; +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + config->filterPrescaler = kQDC_FilterPrescalerDiv1; +#endif +} + +/*! + * brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * param base QDC peripheral base address. + */ +void QDC_DoSoftwareLoadInitialPositionValue(QDC_Type *base) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~QDC_CTRL_W1C_FLAGS); + + tmp16 |= QDC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ + base->CTRL = tmp16; +} + +/*! + * brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * param base QDC peripheral base address. + * param config Pointer to configuration structure. See to "qdc_self_test_config_t". Pass "NULL" to disable. + */ +void QDC_SetSelfTestConfig(QDC_Type *base, const qdc_self_test_config_t *config) +{ + uint16_t tmp16 = 0U; + + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + tmp16 = 0U; + } + else + { + tmp16 = QDC_TST_TEN_MASK | QDC_TST_TCE_MASK | QDC_TST_TEST_PERIOD(config->signalPeriod) | + QDC_TST_TEST_COUNT(config->signalCount); + if (kQDC_SelfTestDirectionNegative == config->signalDirection) + { + tmp16 |= QDC_TST_QDN_MASK; + } + } + + base->TST = tmp16; +} + +/*! + * brief Enable watchdog for QDC module. + * + * param base QDC peripheral base address + * param enable Enables or disables the watchdog + */ +void QDC_EnableWatchdog(QDC_Type *base, bool enable) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~(QDC_CTRL_W1C_FLAGS | QDC_CTRL_WDE_MASK)); + + if (enable) + { + tmp16 |= QDC_CTRL_WDE_MASK; + } + base->CTRL = tmp16; +} + +/*! + * brief Get the status flags. + * + * param base QDC peripheral base address. + * + * return Mask value of status flags. For available mask, see to "_qdc_status_flags". + */ +uint32_t QDC_GetStatusFlags(QDC_Type *base) +{ + uint32_t ret32 = 0U; + + /* QDC_CTRL. */ + if (0U != (QDC_CTRL_HIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_HOMETransitionFlag; + } + if (0U != (QDC_CTRL_XIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_INDEXPulseFlag; + } + if (0U != (QDC_CTRL_DIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_WatchdogTimeoutFlag; + } + if (0U != (QDC_CTRL_CMPIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_PositionCompareFlag; + } + + /* QDC_CTRL2. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != (QDC_CTRL2_SABIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_SimultBothPhaseChangeFlag; + } +#endif + if (0U != (QDC_CTRL2_ROIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollOverFlag; + } + if (0U != (QDC_CTRL2_RUIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollUnderFlag; + } + if (0U != (QDC_CTRL2_DIR_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_LastCountDirectionFlag; + } + + return ret32; +} + +/*! + * brief Clear the status flags. + * + * param base QDC peripheral base address. + * param mask Mask value of status flags to be cleared. For available mask, see to "_qdc_status_flags". + */ +void QDC_ClearStatusFlags(QDC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionFlag & mask)) + { + tmp16 |= QDC_CTRL_HIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseFlag & mask)) + { + tmp16 |= QDC_CTRL_XIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutFlag & mask)) + { + tmp16 |= QDC_CTRL_DIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareFlag & mask)) + { + tmp16 |= QDC_CTRL_CMPIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~QDC_CTRL_W1C_FLAGS)) | tmp16); + } + + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeFlag & mask)) + { + tmp16 |= QDC_CTRL2_SABIRQ_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverFlag & mask)) + { + tmp16 |= QDC_CTRL2_ROIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderFlag & mask)) + { + tmp16 |= QDC_CTRL2_RUIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Enable the interrupts. + * + * param base QDC peripheral base address. + * param mask Mask value of interrupts to be enabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_EnableInterrupts(QDC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= QDC_CTRL_CMPIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~QDC_CTRL_W1C_FLAGS)) | tmp16); + } + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_SABIE_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Disable the interrupts. + * + * param base QDC peripheral base address. + * param mask Mask value of interrupts to be disabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_DisableInterrupts(QDC_Type *base, uint32_t mask) +{ + uint16_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= QDC_CTRL_CMPIE_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~QDC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); + } + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_SABIE_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~QDC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); + } +} + +/*! + * brief Get the enabled interrupts' flags. + * + * param base QDC peripheral base address. + * + * return Mask value of enabled interrupts. + */ +uint32_t QDC_GetEnabledInterrupts(QDC_Type *base) +{ + uint32_t ret32 = 0U; + + /* QDC_CTRL. */ + if (0U != (QDC_CTRL_HIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_HOMETransitionInterruptEnable; + } + if (0U != (QDC_CTRL_XIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_INDEXPulseInterruptEnable; + } + if (0U != (QDC_CTRL_DIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_WatchdogTimeoutInterruptEnable; + } + if (0U != (QDC_CTRL_CMPIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_PositionCompareInerruptEnable; + } + /* QDC_CTRL2. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != (QDC_CTRL2_SABIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable; + } +#endif + if (0U != (QDC_CTRL2_ROIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollOverInterruptEnable; + } + if (0U != (QDC_CTRL2_RUIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollUnderInterruptEnable; + } + return ret32; +} + +/*! + * brief Set initial position value for QDC module. + * + * param base QDC peripheral base address + * param value Positive initial value + */ +void QDC_SetInitialPositionValue(QDC_Type *base, uint32_t value) +{ + base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ + base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ +} + +/*! + * brief Get the current position counter's value. + * + * param base QDC peripheral base address. + * + * return Current position counter's value. + */ +uint32_t QDC_GetPositionValue(QDC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} + +/*! + * brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * param base QDC peripheral base address. + * + * return Hold position counter's value. + */ +uint32_t QDC_GetHoldPositionValue(QDC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_qdc.h similarity index 55% rename from bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.h rename to bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_qdc.h index 28ce466ce3..5a79f3de11 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_qdc.h @@ -1,40 +1,39 @@ /* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP + * Copyright 2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_ENC_H_ -#define _FSL_ENC_H_ +#ifndef FSL_QDC_H_ +#define FSL_QDC_H_ #include "fsl_common.h" /*! - * @addtogroup enc + * @addtogroup qdc * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ -#define FSL_ENC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +#define FSL_QDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*! * @brief Interrupt enable/disable mask. */ -enum _enc_interrupt_enable +enum _qdc_interrupt_enable { - kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ - kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ - kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ - kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - kENC_SimultBothPhaseChangeInterruptEnable = + kQDC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kQDC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kQDC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ + kQDC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + kQDC_SimultBothPhaseChangeInterruptEnable = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ #endif - kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ - kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ + kQDC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kQDC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ }; /*! @@ -42,18 +41,18 @@ enum _enc_interrupt_enable * * These flags indicate the counter's events. */ -enum _enc_status_flags +enum _qdc_status_flags { - kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ - kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ - kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ - kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ -#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) - kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ + kQDC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kQDC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kQDC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kQDC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + kQDC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ #endif - kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ - kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ - kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ + kQDC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kQDC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kQDC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ }; /*! @@ -61,41 +60,41 @@ enum _enc_status_flags * * These flags indicate the counter's signal. */ -enum _enc_signal_status_flags +enum _qdc_signal_status_flags { - kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ - kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ - kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ - kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ - kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ - kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ - kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ - kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ + kQDC_RawHOMEStatusFlag = QDC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kQDC_RawINDEXStatusFlag = QDC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kQDC_RawPHBStatusFlag = QDC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kQDC_RawPHAEXStatusFlag = QDC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kQDC_FilteredHOMEStatusFlag = QDC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kQDC_FilteredINDEXStatusFlag = QDC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kQDC_FilteredPHBStatusFlag = QDC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kQDC_FilteredPHAStatusFlag = QDC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ }; /*! * @brief Define HOME signal's trigger mode. * - * The ENC would count the trigger from HOME signal line. + * The QDC would count the trigger from HOME signal line. */ -typedef enum _enc_home_trigger_mode +typedef enum _qdc_home_trigger_mode { - kENC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ - kENC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ - kENC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ -} enc_home_trigger_mode_t; + kQDC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ + kQDC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kQDC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} qdc_home_trigger_mode_t; /*! * @brief Define INDEX signal's trigger mode. * - * The ENC would count the trigger from INDEX signal line. + * The QDC would count the trigger from INDEX signal line. */ -typedef enum _enc_index_trigger_mode +typedef enum _qdc_index_trigger_mode { - kENC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ - kENC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ - kENC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ -} enc_index_trigger_mode_t; + kQDC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ + kQDC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kQDC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} qdc_index_trigger_mode_t; /*! * @brief Define type for decoder work mode. @@ -105,82 +104,102 @@ typedef enum _enc_index_trigger_mode * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 * means counting down. Otherwise, the direction is reversed. */ -typedef enum _enc_decoder_work_mode +typedef enum _qdc_decoder_work_mode { - kENC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ - kENC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the + kQDC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ + kQDC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the direction. */ -} enc_decoder_work_mode_t; +} qdc_decoder_work_mode_t; /*! * @brief Define type for the condition of POSMATCH pulses. */ -typedef enum _enc_position_match_mode +typedef enum _qdc_position_match_mode { - kENC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the + kQDC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). */ - kENC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ -} enc_position_match_mode_t; + kQDC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ +} qdc_position_match_mode_t; /*! * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. */ -typedef enum _enc_revolution_count_condition +typedef enum _qdc_revolution_count_condition { - kENC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ - kENC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + kQDC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kQDC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution counter. */ -} enc_revolution_count_condition_t; +} qdc_revolution_count_condition_t; /*! * @brief Define type for direction of self test generated signal. */ -typedef enum _enc_self_test_direction +typedef enum _qdc_self_test_direction { - kENC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ - kENC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ -} enc_self_test_direction_t; + kQDC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ + kQDC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ +} qdc_self_test_direction_t; -#if (defined(FSL_FEATURE_ENC_HAS_CTRL3) && FSL_FEATURE_ENC_HAS_CTRL3) +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) /*! * @brief Define prescaler value for clock in CTRL3. * * The clock is prescaled by a value of 2^PRSC which means that the prescaler logic * can divide the clock by a minimum of 1 and a maximum of 32,768. */ -typedef enum _enc_prescaler +typedef enum _qdc_prescaler { - kENC_ClockDiv1 = 0, - kENC_ClockDiv2 = 1, - kENC_ClockDiv4 = 2, - kENC_ClockDiv8 = 3, - kENC_ClockDiv16 = 4, - kENC_ClockDiv32 = 5, - kENC_ClockDiv64 = 6, - kENC_ClockDiv128 = 7, - kENC_ClockDiv256 = 8, - kENC_ClockDiv512 = 9, - kENC_ClockDiv1024 = 10, - kENC_ClockDiv2048 = 11, - kENC_ClockDiv4096 = 12, - kENC_ClockDiv8192 = 13, - kENC_ClockDiv16384 = 14, - kENC_ClockDiv32768 = 15, -} enc_prescaler_t; + kQDC_ClockDiv1 = 0, + kQDC_ClockDiv2 = 1, + kQDC_ClockDiv4 = 2, + kQDC_ClockDiv8 = 3, + kQDC_ClockDiv16 = 4, + kQDC_ClockDiv32 = 5, + kQDC_ClockDiv64 = 6, + kQDC_ClockDiv128 = 7, + kQDC_ClockDiv256 = 8, + kQDC_ClockDiv512 = 9, + kQDC_ClockDiv1024 = 10, + kQDC_ClockDiv2048 = 11, + kQDC_ClockDiv4096 = 12, + kQDC_ClockDiv8192 = 13, + kQDC_ClockDiv16384 = 14, + kQDC_ClockDiv32768 = 15, +} qdc_prescaler_t; +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) +/*! + * @brief Define input filter prescaler value. + * + * The input filter prescaler value is to prescale the IPBus clock. + * (Frequency of FILT clock) = (Frequency of IPBus clock) / 2^FILT_PRSC. + */ +typedef enum _qdc_filter_prescaler +{ + kQDC_FilterPrescalerDiv1 = 0U, /*!< Input filter prescaler is 1. */ + kQDC_FilterPrescalerDiv2 = 1U, /*!< Input filter prescaler is 2. */ + kQDC_FilterPrescalerDiv4 = 2U, /*!< Input filter prescaler is 4. */ + kQDC_FilterPrescalerDiv8 = 3U, /*!< Input filter prescaler is 8. */ + kQDC_FilterPrescalerDiv16 = 4U, /*!< Input filter prescaler is 16. */ + kQDC_FilterPrescalerDiv32 = 5U, /*!< Input filter prescaler is 32. */ + kQDC_FilterPrescalerDiv64 = 6U, /*!< Input filter prescaler is 64. */ + kQDC_FilterPrescalerDiv128 = 7U, /*!< Input filter prescaler is 128. */ +} qdc_filter_prescaler_t; #endif /*! - * @brief Define user configuration structure for ENC module. + * @brief Define user configuration structure for QDC module. */ -typedef struct _enc_config +typedef struct _qdc_config { /* Basic counter. */ bool enableReverseDirection; /*!< Enable reverse direction counting. */ - enc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ + qdc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ /* Signal detection. */ - enc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ - enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ + qdc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ + qdc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. */ @@ -191,6 +210,10 @@ typedef struct _enc_config decoder module watchdog timer. This field is only available when "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + qdc_filter_prescaler_t filterPrescaler; /*!< Input filter prescaler. */ +#endif + /* Filter for PHASEA, PHASEB, INDEX and HOME. */ uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the @@ -203,22 +226,22 @@ typedef struct _enc_config The available range is 0 - 255. */ /* Position compare. */ - enc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ + qdc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ /* Modulus counting. */ - enc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ + qdc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ bool enableModuloCountMode; /*!< Enable Modulo Counting. */ uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when "enableModuloCountMode" = true. The available value is a 32-bit number. */ uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ -#if (defined(FSL_FEATURE_ENC_HAS_CTRL3) && FSL_FEATURE_ENC_HAS_CTRL3) +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) /* Prescaler. */ bool enablePeriodMeasurementFunction; /*!< Enable period measurement function. */ - enc_prescaler_t prescalerValue; /*!< The value of prescaler. */ + qdc_prescaler_t prescalerValue; /*!< The value of prescaler. */ #endif -} enc_config_t; +} qdc_config_t; /*! * @brief Define configuration structure for self test module. @@ -226,13 +249,13 @@ typedef struct _enc_config * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. * This is a factory test feature. It is also useful to customers' software development and testing. */ -typedef struct _enc_self_test_config +typedef struct _qdc_self_test_config { - enc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ + qdc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. The available range is 0 - 31. */ -} enc_self_test_config_t; +} qdc_self_test_config_t; #if defined(__cplusplus) extern "C" { @@ -248,56 +271,56 @@ extern "C" { */ /*! - * @brief Initialization for the ENC module. + * @brief Initialization for the QDC module. * - * This function is to make the initialization for the ENC module. It should be called firstly before any operation to - * the ENC with the operations like: - * - Enable the clock for ENC module. - * - Configure the ENC's working attributes. + * This function is to make the initialization for the QDC module. It should be called firstly before any operation to + * the QDC with the operations like: + * - Enable the clock for QDC module. + * - Configure the QDC's working attributes. * - * @param base ENC peripheral base address. - * @param config Pointer to configuration structure. See to "enc_config_t". + * @param base QDC peripheral base address. + * @param config Pointer to configuration structure. See to "qdc_config_t". */ -void ENC_Init(ENC_Type *base, const enc_config_t *config); +void QDC_Init(QDC_Type *base, const qdc_config_t *config); /*! - * @brief De-initialization for the ENC module. + * @brief De-initialization for the QDC module. * - * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * This function is to make the de-initialization for the QDC module. It could be called when QDC is no longer used with * the operations like: - * - Disable the clock for ENC module. + * - Disable the clock for QDC module. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. */ -void ENC_Deinit(ENC_Type *base); +void QDC_Deinit(QDC_Type *base); /*! - * @brief Get an available pre-defined settings for ENC's configuration. + * @brief Get an available pre-defined settings for QDC's configuration. * - * This function initializes the ENC configuration structure with an available settings, the default value are: + * This function initializes the QDC configuration structure with an available settings, the default value are: * @code * config->enableReverseDirection = false; - * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - * config->HOMETriggerMode = kENC_HOMETriggerDisabled; - * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; * config->enableTRIGGERClearPositionCounter = false; * config->enableTRIGGERClearHoldPositionCounter = false; * config->enableWatchdog = false; * config->watchdogTimeoutValue = 0U; * config->filterCount = 0U; * config->filterSamplePeriod = 0U; - * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; * config->positionCompareValue = 0xFFFFFFFFU; - * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; * config->enableModuloCountMode = false; * config->positionModulusValue = 0U; * config->positionInitialValue = 0U; - * config->prescalerValue = kENC_ClockDiv1; + * config->prescalerValue = kQDC_ClockDiv1; * config->enablePeriodMeasurementFunction = true; * @endcode - * @param config Pointer to a variable of configuration structure. See to "enc_config_t". + * @param config Pointer to a variable of configuration structure. See to "qdc_config_t". */ -void ENC_GetDefaultConfig(enc_config_t *config); +void QDC_GetDefaultConfig(qdc_config_t *config); /*! * @brief Load the initial position value to position counter. @@ -305,9 +328,9 @@ void ENC_GetDefaultConfig(enc_config_t *config); * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and * LPOS), so that to provide the consistent operation the position counter registers. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. */ -void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); +void QDC_DoSoftwareLoadInitialPositionValue(QDC_Type *base); /*! * @brief Enable and configure the self test function. @@ -316,28 +339,28 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. * It is a factory test feature; however, it may be useful to customers' software development and testing. * - * @param base ENC peripheral base address. - * @param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + * @param base QDC peripheral base address. + * @param config Pointer to configuration structure. See to "qdc_self_test_config_t". Pass "NULL" to disable. */ -void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); +void QDC_SetSelfTestConfig(QDC_Type *base, const qdc_self_test_config_t *config); /*! - * @brief Enable watchdog for ENC module. + * @brief Enable watchdog for QDC module. * - * @param base ENC peripheral base address + * @param base QDC peripheral base address * @param enable Enables or disables the watchdog */ -void ENC_EnableWatchdog(ENC_Type *base, bool enable); +void QDC_EnableWatchdog(QDC_Type *base, bool enable); /*! - * @brief Set initial position value for ENC module. + * @brief Set initial position value for QDC module. * - * @param base ENC peripheral base address + * @param base QDC peripheral base address * @param value Positive initial value */ -void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); +void QDC_SetInitialPositionValue(QDC_Type *base, uint32_t value); -/* @} */ +/*! @} */ /*! * @name Status @@ -346,32 +369,32 @@ void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); /*! * @brief Get the status flags. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * - * @return Mask value of status flags. For available mask, see to "_enc_status_flags". + * @return Mask value of status flags. For available mask, see to "_qdc_status_flags". */ -uint32_t ENC_GetStatusFlags(ENC_Type *base); +uint32_t QDC_GetStatusFlags(QDC_Type *base); /*! * @brief Clear the status flags. * - * @param base ENC peripheral base address. - * @param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + * @param base QDC peripheral base address. + * @param mask Mask value of status flags to be cleared. For available mask, see to "_qdc_status_flags". */ -void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask); +void QDC_ClearStatusFlags(QDC_Type *base, uint32_t mask); /*! * @brief Get the signals' real-time status. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * - * @return Mask value of signals' real-time status. For available mask, see to "_enc_signal_status_flags" + * @return Mask value of signals' real-time status. For available mask, see to "_qdc_signal_status_flags" */ -static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) +static inline uint16_t QDC_GetSignalStatusFlags(QDC_Type *base) { return base->IMR; } -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -381,29 +404,29 @@ static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) /*! * @brief Enable the interrupts. * - * @param base ENC peripheral base address. - * @param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + * @param base QDC peripheral base address. + * @param mask Mask value of interrupts to be enabled. For available mask, see to "_qdc_interrupt_enable". */ -void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask); +void QDC_EnableInterrupts(QDC_Type *base, uint32_t mask); /*! * @brief Disable the interrupts. * - * @param base ENC peripheral base address. - * @param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + * @param base QDC peripheral base address. + * @param mask Mask value of interrupts to be disabled. For available mask, see to "_qdc_interrupt_enable". */ -void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask); +void QDC_DisableInterrupts(QDC_Type *base, uint32_t mask); /*! * @brief Get the enabled interrupts' flags. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return Mask value of enabled interrupts. */ -uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); +uint32_t QDC_GetEnabledInterrupts(QDC_Type *base); -/* @} */ +/*! @} */ /*! * @name Value Operation @@ -413,11 +436,11 @@ uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); /*! * @brief Get the current position counter's value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return Current position counter's value. */ -uint32_t ENC_GetPositionValue(ENC_Type *base); +uint32_t QDC_GetPositionValue(QDC_Type *base); /*! * @brief Get the hold position counter's value. @@ -426,20 +449,20 @@ uint32_t ENC_GetPositionValue(ENC_Type *base); * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to * be attained. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return Hold position counter's value. */ -uint32_t ENC_GetHoldPositionValue(ENC_Type *base); +uint32_t QDC_GetHoldPositionValue(QDC_Type *base); /*! * @brief Get the position difference counter's value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The position difference counter's value. */ -static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) +static inline uint16_t QDC_GetPositionDifferenceValue(QDC_Type *base) { return base->POSD; } @@ -451,11 +474,11 @@ static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to * be attained. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return Hold position difference counter's value. */ -static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) +static inline uint16_t QDC_GetHoldPositionDifferenceValue(QDC_Type *base) { return base->POSDH; } @@ -463,11 +486,11 @@ static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) /*! * @brief Get the position revolution counter's value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The position revolution counter's value. */ -static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) +static inline uint16_t QDC_GetRevolutionValue(QDC_Type *base) { return base->REV; } @@ -479,24 +502,24 @@ static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to * be attained. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return Hold position revolution counter's value. */ -static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base) +static inline uint16_t QDC_GetHoldRevolutionValue(QDC_Type *base) { return base->REVH; } -#if (defined(FSL_FEATURE_ENC_HAS_LASTEDGE) && FSL_FEATURE_ENC_HAS_LASTEDGE) +#if (defined(FSL_FEATURE_QDC_HAS_LASTEDGE) && FSL_FEATURE_QDC_HAS_LASTEDGE) /*! * @brief Get the last edge time value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The last edge time hold value. */ -static inline uint16_t ENC_GetLastEdgeTimeValue(ENC_Type *base) +static inline uint16_t QDC_GetLastEdgeTimeValue(QDC_Type *base) { return base->LASTEDGE; } @@ -504,25 +527,25 @@ static inline uint16_t ENC_GetLastEdgeTimeValue(ENC_Type *base) /*! * @brief Get the last edge time hold value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The last edge time hold value. */ -static inline uint16_t ENC_GetHoldLastEdgeTimeValue(ENC_Type *base) +static inline uint16_t QDC_GetHoldLastEdgeTimeValue(QDC_Type *base) { return base->LASTEDGEH; } #endif -#if (defined(FSL_FEATURE_ENC_HAS_POSDPER) && FSL_FEATURE_ENC_HAS_POSDPER) +#if (defined(FSL_FEATURE_QDC_HAS_POSDPER) && FSL_FEATURE_QDC_HAS_POSDPER) /*! * @brief Get the position difference period value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The position difference period hold value. */ -static inline uint16_t ENC_GetPositionDifferencePeriodValue(ENC_Type *base) +static inline uint16_t QDC_GetPositionDifferencePeriodValue(QDC_Type *base) { return base->POSDPER; } @@ -530,11 +553,11 @@ static inline uint16_t ENC_GetPositionDifferencePeriodValue(ENC_Type *base) /*! * @brief Get the position difference period buffer value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The position difference period hold value. */ -static inline uint16_t ENC_GetPositionDifferencePeriodBufferValue(ENC_Type *base) +static inline uint16_t QDC_GetPositionDifferencePeriodBufferValue(QDC_Type *base) { return base->POSDPERBFR; } @@ -542,21 +565,21 @@ static inline uint16_t ENC_GetPositionDifferencePeriodBufferValue(ENC_Type *base /*! * @brief Get the position difference period hold value. * - * @param base ENC peripheral base address. + * @param base QDC peripheral base address. * * @return The position difference period hold value. */ -static inline uint16_t ENC_GetHoldPositionDifferencePeriodValue(ENC_Type *base) +static inline uint16_t QDC_GetHoldPositionDifferencePeriodValue(QDC_Type *base) { return base->POSDPERH; } #endif -/* @} */ +/*! @} */ #if defined(__cplusplus) } #endif -/* @} */ +/*! @} */ -#endif /* _FSL_ENC_H_ */ +#endif /* FSL_QDC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_reset.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_reset.h index b517a45936..b2b42754dc 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_reset.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_reset.h @@ -25,8 +25,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief reset driver version 1.0.0. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) /*@}*/ /*! @@ -80,7 +80,7 @@ typedef enum _SYSCON_RSTn kUSB0_FS_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0-FS reset control */ kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kSMARTDMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */ + kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */ kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ kENET_RST_SHIFT_RSTn = 131072 | 2U, /**< Ethernet reset control */ @@ -107,8 +107,8 @@ typedef enum _SYSCON_RSTn kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */ kSINC_RST_SHIFT_RSTn = 196608 | 2U, /**< SINC reset control */ kCOOLFLUX_RST_SHIFT_RSTn = 196608 | 3U, /**< CoolFlux reset control */ - kENC0_RST_SHIFT_RSTn = 196608 | 4U, /**< ENC0 reset control */ - kENC1_RST_SHIFT_RSTn = 196608 | 5U, /**< ENC1 reset control */ + kQDC0_RST_SHIFT_RSTn = 196608 | 4U, /**< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = 196608 | 5U, /**< QDC1 reset control */ kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */ kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */ kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */ @@ -239,6 +239,19 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); */ void RESET_PeripheralReset(reset_ip_name_t peripheral); +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); +} + #if defined(__cplusplus) } #endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.c index 32d36a047f..6d69f5efb2 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.c @@ -32,6 +32,10 @@ typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); /*! @brief check flag avalibility */ #define IS_SAI_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) + +#if defined(SAI_RSTS) +#define SAI_RESETS_ARRAY SAI_RSTS +#endif /******************************************************************************* * Prototypes ******************************************************************************/ @@ -145,6 +149,10 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config, ******************************************************************************/ /* Base pointer array */ static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +#if defined(SAI_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_saiReset[] = SAI_RESETS_ARRAY; +#endif /*!@brief SAI handle pointer */ static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; /* IRQ number array */ @@ -385,254 +393,6 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config, #endif } -/*! - * brief Initializes the SAI Tx peripheral. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_TxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault - * because the clock is not enabled. - * - * param base SAI base pointer - * param config SAI configuration structure. - */ -void SAI_TxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); -#endif - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - SAI_TxReset(base); - - /* Configure audio protocol */ - if (config->protocol == kSAI_BusLeftJustified) - { - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusRightJustified) - { - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusI2S) - { - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusPCMA) - { - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - else - { - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->TCR2 |= I2S_TCR2_BCD_MASK; - base->TCR4 |= I2S_TCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); - base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); - } - else - { - base->TCR2 &= ~I2S_TCR2_BCD_MASK; - base->TCR4 &= ~I2S_TCR4_FSD_MASK; - } - - /* Set Sync mode */ - if (config->syncMode == kSAI_ModeAsync) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - } - if (config->syncMode == kSAI_ModeSync) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(1U)); - /* If sync with Rx, should set Rx to async mode */ - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - } -#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) - if (config->syncMode == kSAI_ModeSyncWithOtherTx) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(2U)); - } - if (config->syncMode == kSAI_ModeSyncWithOtherRx) - { - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(3U)); - } -#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR - SAI_TxSetFIFOErrorContinue(base, true); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ -} - -/*! - * brief Initializes the SAI Rx peripheral. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_RxGetDefaultConfig(). - * - * note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault - * because the clock is not enabled. - * - * param base SAI base pointer - * param config SAI configuration structure. - */ -void SAI_RxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SAI clock first. */ - (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); -#endif - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - SAI_RxReset(base); - - /* Configure audio protocol */ - if (config->protocol == kSAI_BusLeftJustified) - { - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusRightJustified) - { - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusI2S) - { - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); - } - else if (config->protocol == kSAI_BusPCMA) - { - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - else - { - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->RCR2 |= I2S_RCR2_BCD_MASK; - base->RCR4 |= I2S_RCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); - base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); - } - else - { - base->RCR2 &= ~I2S_RCR2_BCD_MASK; - base->RCR4 &= ~I2S_RCR4_FSD_MASK; - } - - /* Set Sync mode */ - if (config->syncMode == kSAI_ModeAsync) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - } - if (config->syncMode == kSAI_ModeSync) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(1U)); - /* If sync with Tx, should set Tx to async mode */ - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - } -#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) - if (config->syncMode == kSAI_ModeSyncWithOtherTx) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(2U)); - } - if (config->syncMode == kSAI_ModeSyncWithOtherRx) - { - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(3U)); - } -#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR - SAI_RxSetFIFOErrorContinue(base, true); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ -} - /*! * brief Initializes the SAI peripheral. * @@ -647,6 +407,10 @@ void SAI_Init(I2S_Type *base) (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(SAI_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_saiReset[SAI_GetInstance(base)]); +#endif + #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) /* disable interrupt and DMA request*/ base->TCSR &= @@ -677,74 +441,6 @@ void SAI_Deinit(I2S_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } -/*! - * brief Sets the SAI Tx configuration structure to default values. - * - * deprecated Do not use this function. It has been superceded by @ref - * SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig,SAI_GetRightJustifiedConfig, SAI_GetDSPConfig,SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_TxConfig(). - * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified - * before calling SAI_TxConfig(). - * This is an example. - code - sai_config_t config; - SAI_TxGetDefaultConfig(&config); - endcode - * - * param config pointer to master configuration structure - */ -void SAI_TxGetDefaultConfig(sai_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - config->mclkSource = kSAI_MclkSourceSysclk; -#endif -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeAsync; -} - -/*! - * brief Sets the SAI Rx configuration structure to default values. - * - * deprecated Do not use this function. It has been superceded by @ref - * SAI_GetClassicI2SConfig,SAI_GetLeftJustifiedConfig,SAI_GetRightJustifiedConfig,SAI_GetDSPConfig,SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_RxConfig(). - * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified - * before calling SAI_RxConfig(). - * This is an example. - code - sai_config_t config; - SAI_RxGetDefaultConfig(&config); - endcode - * - * param config pointer to master configuration structure - */ -void SAI_RxGetDefaultConfig(sai_config_t *config) -{ - /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); - - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) - config->mclkSource = kSAI_MclkSourceSysclk; -#endif -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeSync; -} - /*! * brief Resets the SAI Tx. * @@ -1533,7 +1229,7 @@ void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv assert(config != NULL); assert(config->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); - handle->bitWidth = config->frameSync.frameSyncWidth; + handle->bitWidth = config->serialData.dataWordNLength; #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) if ((config->fifo.fifoWatermark == 0U) || (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) @@ -1667,7 +1363,7 @@ void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv assert(handle != NULL); assert(config != NULL); - handle->bitWidth = config->frameSync.frameSyncWidth; + handle->bitWidth = config->serialData.dataWordNLength; #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) if ((config->fifo.fifoWatermark == 0U) || (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) @@ -1832,293 +1528,6 @@ void SAI_GetTDMConfig(sai_transceiver_t *config, config->serialData.dataWordNum = (uint8_t)dataWordNum; } -/*! - * brief Configures the SAI Tx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); - - uint32_t bclk = 0; - uint32_t val = 0; - uint8_t i = 0U, channelNums = 0U; - uint32_t divider = 0U; - - if (format->isFrameSyncCompact) - { - bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); - val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); - val |= I2S_TCR4_SYWD(format->bitWidth - 1U); - base->TCR4 = val; - } - else - { - bclk = format->sampleRate_Hz * 32U * 2U; - } - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled, then set master clock divider */ - if (IS_SAI_FLAG_SET(base->MCR, I2S_MCR_MOE_MASK)) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (IS_SAI_FLAG_SET(base->TCR2, I2S_TCR2_BCD_MASK)) - { - base->TCR2 &= ~I2S_TCR2_DIV_MASK; - /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ - divider = bclkSourceClockHz / bclk; - /* for the condition where the source clock is smaller than target bclk */ - if (divider == 0U) - { - divider++; - } - /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ - if ((bclkSourceClockHz / divider) > bclk) - { - divider++; - } - -#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) - /* if bclk same with MCLK, bypass the divider */ - if (divider == 1U) - { - base->TCR2 |= I2S_TCR2_BYP_MASK; - } - else -#endif - { - base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U); - } - } - - /* Set bitWidth */ - val = (format->isFrameSyncCompact) ? (format->bitWidth - 1U) : 31U; - if (format->protocol == kSAI_BusRightJustified) - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val); - } - else - { - if (IS_SAI_FLAG_SET(base->TCR4, I2S_TCR4_MF_MASK)) - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1UL); - } - else - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); - } - } - - /* Set mono or stereo */ - base->TMR = (uint32_t)format->stereo; - - /* if channel mask is not set, then format->channel must be set, - use it to get channel mask value */ - if (format->channelMask == 0U) - { - format->channelMask = 1U << format->channel; - } - - /* if channel nums is not set, calculate it here according to channelMask*/ - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - channelNums++; - format->endChannel = i; - } - } - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - format->channel = i; - break; - } - } - - format->channelNums = channelNums; -#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) - /* make sure combine mode disabled while multipe channel is used */ - if (format->channelNums > 1U) - { - base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; - } -#endif - - /* Set data channel */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(format->channelMask); - -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - /* Set watermark */ - base->TCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ -} - -/*! - * brief Configures the SAI Rx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); - - uint32_t bclk = 0; - uint32_t val = 0; - uint8_t i = 0U, channelNums = 0U; - uint32_t divider = 0U; - - if (format->isFrameSyncCompact) - { - bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); - val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); - val |= I2S_RCR4_SYWD(format->bitWidth - 1U); - base->RCR4 = val; - } - else - { - bclk = format->sampleRate_Hz * 32U * 2U; - } - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled */ - if (IS_SAI_FLAG_SET(base->MCR, I2S_MCR_MOE_MASK)) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (IS_SAI_FLAG_SET(base->RCR2, I2S_RCR2_BCD_MASK)) - { - base->RCR2 &= ~I2S_RCR2_DIV_MASK; - /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ - divider = bclkSourceClockHz / bclk; - /* for the condition where the source clock is smaller than target bclk */ - if (divider == 0U) - { - divider++; - } - /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ - if ((bclkSourceClockHz / divider) > bclk) - { - divider++; - } -#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) - /* if bclk same with MCLK, bypass the divider */ - if (divider == 1U) - { - base->RCR2 |= I2S_RCR2_BYP_MASK; - } - else -#endif - { - base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U); - } - } - - /* Set bitWidth */ - val = (format->isFrameSyncCompact) ? (format->bitWidth - 1U) : 31U; - if (format->protocol == kSAI_BusRightJustified) - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val); - } - else - { - if (IS_SAI_FLAG_SET(base->RCR4, I2S_RCR4_MF_MASK)) - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1UL); - } - else - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0UL); - } - } - - /* Set mono or stereo */ - base->RMR = (uint32_t)format->stereo; - - /* if channel mask is not set, then format->channel must be set, - use it to get channel mask value */ - if (format->channelMask == 0U) - { - format->channelMask = 1U << format->channel; - } - - /* if channel nums is not set, calculate it here according to channelMask*/ - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - channelNums++; - format->endChannel = i; - } - } - - for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) - { - if (IS_SAI_FLAG_SET((1UL << i), format->channelMask)) - { - format->channel = i; - break; - } - } - - format->channelNums = channelNums; - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) - /* make sure combine mode disabled while multipe channel is used */ - if (format->channelNums > 1U) - { - base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; - } -#endif - - /* Set data channel */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - /* enable all the channel */ - base->RCR3 |= I2S_RCR3_RCE(format->channelMask); - -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - /* Set watermark */ - base->RCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ -} - /*! * brief Sends data using a blocking method. * @@ -2353,106 +1762,6 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf (void)EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } -/*! - * brief Configures the SAI Tx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param handle SAI handle pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * return Status of this function. Return value is the status_t. - */ -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle != NULL); - - if ((bclkSourceClockHz < format->sampleRate_Hz) -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - || (mclkSourceClockHz < format->sampleRate_Hz) -#endif - ) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = (uint8_t)format->bitWidth; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->watermark = format->watermark; -#endif - - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - handle->channel = format->channel; - /* used for multi channel */ - handle->channelMask = format->channelMask; - handle->channelNums = format->channelNums; - handle->endChannel = format->endChannel; - - return kStatus_Success; -} - -/*! - * brief Configures the SAI Rx audio format. - * - * deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * param base SAI base pointer. - * param handle SAI handle pointer. - * param format Pointer to the SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * return Status of this function. Return value is one of status_t. - */ -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle != NULL); - - if ((bclkSourceClockHz < format->sampleRate_Hz) -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - || (mclkSourceClockHz < format->sampleRate_Hz) -#endif - ) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = (uint8_t)format->bitWidth; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->watermark = format->watermark; -#endif - - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - handle->channel = format->channel; - /* used for multi channel */ - handle->channelMask = format->channelMask; - handle->channelNums = format->channelNums; - handle->endChannel = format->endChannel; - - return kStatus_Success; -} - /*! * brief Performs an interrupt non-blocking send transfer on SAI. * diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.h index a303edf29f..16da4fd98e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SAI_H_ -#define _FSL_SAI_H_ +#ifndef FSL_SAI_H_ +#define FSL_SAI_H_ #include "fsl_common.h" @@ -21,9 +21,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 8)) /*!< Version 2.3.8 */ -/*@}*/ +/*! @{ */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*!< Version 2.4.2 */ +/*! @} */ /*! @brief _sai_status_t, SAI return status.*/ enum @@ -466,78 +466,6 @@ extern "C" { * @{ */ -/*! - * @brief Initializes the SAI Tx peripheral. - * @deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. - */ -void SAI_TxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Initializes the SAI Rx peripheral. - * @deprecated Do not use this function. It has been superceded by @ref SAI_Init - * - * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. - */ -void SAI_RxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Sets the SAI Tx configuration structure to default values. - * @deprecated Do not use this function. It has been superceded by - * @ref SAI_GetClassicI2SConfig, @ref SAI_GetLeftJustifiedConfig , @ref SAI_GetRightJustifiedConfig, @ref - SAI_GetDSPConfig, @ref SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_TxConfig(). - * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified - * before calling SAI_TxConfig(). - * This is an example. - @code - sai_config_t config; - SAI_TxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_TxGetDefaultConfig(sai_config_t *config); - -/*! - * @brief Sets the SAI Rx configuration structure to default values. - * @deprecated Do not use this function. It has been superceded by - * @ref SAI_GetClassicI2SConfig, @ref SAI_GetLeftJustifiedConfig , @ref SAI_GetRightJustifiedConfig, @ref - SAI_GetDSPConfig, @ref SAI_GetTDMConfig - * - * This API initializes the configuration structure for use in SAI_RxConfig(). - * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified - * before calling SAI_RxConfig(). - * This is an example. - @code - sai_config_t config; - SAI_RxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_RxGetDefaultConfig(sai_config_t *config); - /*! * @brief Initializes the SAI peripheral. * @@ -940,7 +868,7 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) * This function will also clear all the error flags such as FIFO error, sync error etc. * * @param base SAI base pointer - * @param tresetType Reset type, FIFO reset or software reset + * @param resetType Reset type, FIFO reset or software reset */ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType); @@ -1244,42 +1172,6 @@ static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t ch * @{ */ -/*! - * @brief Configures the SAI Tx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. - */ -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - /*! * @brief Sends data using a blocking method. * @@ -1417,47 +1309,6 @@ void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiv */ void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); -/*! - * @brief Configures the SAI Tx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * @return Status of this function. Return value is the status_t. - */ -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfig - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * @return Status of this function. Return value is one of status_t. - */ -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); /*! * @brief Performs an interrupt non-blocking send transfer on SAI. @@ -1583,4 +1434,4 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); /*! @} */ -#endif /* _FSL_SAI_H_ */ +#endif /* FSL_SAI_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.c index 47aa11def9..b3ffa7a7ec 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.c @@ -16,12 +16,12 @@ /******************************************************************************* * Definitions ******************************************************************************/ -/* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32UL) & ~0x1FU) +/* Used for edma_tcd_t size aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + sizeof(edma_tcd_t)) & ~(sizeof(edma_tcd_t) - 1U)) static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; /* Only support 2 and 4 channel */ -#define SAI_CHANNEL_MAP_MODULO(channel) (channel == 2U ? kEDMA_Modulo8bytes : kEDMA_Modulo16bytes) +#define SAI_CHANNEL_MAP_MODULO(channel) ((channel) == 2U ? kEDMA_Modulo8bytes : kEDMA_Modulo16bytes) /*dmaHandle = txDmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->dmaHandle = txDmaHandle; + handle->callback = callback; + handle->userData = userData; + handle->interleaveType = kSAI_EDMAInterleavePerChannelSample; /* Set SAI state to idle */ handle->state = (uint32_t)kSAI_Idle; @@ -233,9 +234,10 @@ void SAI_TransferRxCreateHandleEDMA( (void)memset(handle, 0, sizeof(*handle)); /* Set sai base to handle */ - handle->dmaHandle = rxDmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->dmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + handle->interleaveType = kSAI_EDMAInterleavePerChannelSample; /* Set SAI state to idle */ handle->state = (uint32_t)kSAI_Idle; @@ -251,53 +253,18 @@ void SAI_TransferRxCreateHandleEDMA( } /*! - * brief Configures the SAI Tx audio format. + * brief Initializes the SAI interleave type. * - * deprecated Do not use this function. It has been superceded by ref SAI_TransferTxSetConfigEDMA + * This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would + * like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is + * kSAI_EDMAInterleavePerChannelSample always * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * param base SAI base pointer. * param handle SAI eDMA handle pointer. - * param format Pointer to SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * retval kStatus_Success Audio format set successfully. - * retval kStatus_InvalidArgument The input argument is invalid. + * param interleaveType SAI interleave type. */ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) +void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType) { - assert((handle != NULL) && (format != NULL)); - - /* Configure the audio format to SAI registers */ - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the transfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = (uint8_t)(format->bitWidth / 8U); - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits until do a send/receive */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->count = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - format->watermark); -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + handle->interleaveType = interleaveType; } /*! @@ -357,56 +324,6 @@ void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ #endif /* FSL_FEATURE_SAI_HAS_FIFO */ } -/*! - * brief Configures the SAI Rx audio format. - * - * deprecated Do not use this function. It has been superceded by ref SAI_TransferRxSetConfigEDMA - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * param base SAI base pointer. - * param handle SAI eDMA handle pointer. - * param format Pointer to SAI audio data format structure. - * param mclkSourceClockHz SAI master clock source frequency in Hz. - * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * retval kStatus_Success Audio format set successfully. - * retval kStatus_InvalidArgument The input argument is invalid. - */ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert((handle != NULL) && (format != NULL)); - - /* Configure the audio format to SAI registers */ - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the transfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = (uint8_t)(format->bitWidth / 8U); - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits until do a send/receive */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; -#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) - handle->count = format->watermark; -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_HAS_FIFO */ -} - /*! * brief Configures the SAI Rx. * @@ -470,6 +387,18 @@ void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ * note This interface returns immediately after the transfer initiates. Call * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. * + * In classic I2S mode configuration. + * 1. The data source sent should be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelSample : + * -------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------- + * 2. The data source sent should be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelBlock : + * ------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ...| RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * ------------------------------------------------------------------------------------------------------- + * * This function support multi channel transfer, * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation * on channel numbers @@ -487,9 +416,14 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra { assert((handle != NULL) && (xfer != NULL)); - edma_transfer_config_t config = {0}; - uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); - uint32_t destOffset = 0U; + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + uint32_t destOffset = 0U; + uint32_t srcOffset = xfer->dataSize / 2U; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + edma_minor_offset_config_t minorOffset = {.enableSrcMinorOffset = true, + .enableDestMinorOffset = false, + .minorOffset = 0xFFFFFU - 2U * srcOffset + 1U + handle->bytesPerFrame}; /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -518,11 +452,31 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra } #endif - /* Prepare edma configure */ - EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, - (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, - (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); - + if (handle->interleaveType == kSAI_EDMAInterleavePerChannelSample) + { + /* Prepare edma configure */ + EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, + (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)2U * handle->bytesPerFrame, xfer->dataSize); +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfigExt(handle->dmaHandle->base, currentTCD, &minorOffset); + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequestExt(handle->dmaHandle->base, currentTCD, true); +#else + EDMA_TcdSetTransferConfig(currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfig(currentTCD, &minorOffset); + EDMA_TcdEnableInterrupts(currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequest(currentTCD, true); +#endif + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, currentTCD); + } /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ handle->nbytes = handle->count * handle->bytesPerFrame; @@ -564,6 +518,18 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra * note This interface returns immediately after the transfer initiates. Call * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. * + * In classic I2S mode configuration. + * 1. The output data will be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelSample : + * -------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------- + * 2. The output data will be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelBlock : + * ------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ...| RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * ------------------------------------------------------------------------------------------------------- + * * This function support multi channel transfer, * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation * on channel numbers @@ -581,9 +547,15 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ { assert((handle != NULL) && (xfer != NULL)); - edma_transfer_config_t config = {0}; - uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); - uint32_t srcOffset = 0U; + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + uint32_t srcOffset = 0U; + uint32_t destOffset = xfer->dataSize / 2U; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + edma_minor_offset_config_t minorOffset = { + .enableSrcMinorOffset = false, + .enableDestMinorOffset = true, + .minorOffset = 0xFFFFFU - 2U * destOffset + 1U + (uint32_t)handle->bytesPerFrame}; /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -612,10 +584,32 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ } #endif - /* Prepare edma configure */ - EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, - xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, - (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + if (handle->interleaveType == kSAI_EDMAInterleavePerChannelSample) + { + /* Prepare edma configure */ + EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, + (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)2U * handle->bytesPerFrame, xfer->dataSize); +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfigExt(handle->dmaHandle->base, currentTCD, &minorOffset); + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequestExt(handle->dmaHandle->base, currentTCD, true); +#else + EDMA_TcdSetTransferConfig(currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfig(currentTCD, &minorOffset); + EDMA_TcdEnableInterrupts(currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequest(currentTCD, true); +#endif + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, currentTCD); + } + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ handle->nbytes = handle->count * handle->bytesPerFrame; @@ -703,6 +697,23 @@ status_t SAI_TransferSendLoopEDMA(I2S_Type *base, handle->bytesPerFrame, (uint32_t)handle->count * handle->bytesPerFrame, transfer->dataSize, kEDMA_MemoryToPeripheral); +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + if (i == (loopTransferCount - 1U)) + { + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], &config, ¤tTCD[0U]); + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], + (uint32_t)kEDMA_MajorInterruptEnable); + handle->state = (uint32_t)kSAI_BusyLoopTransfer; + break; + } + else + { + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], &config, + ¤tTCD[tcdIndex + 1U]); + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], + (uint32_t)kEDMA_MajorInterruptEnable); + } +#else if (i == (loopTransferCount - 1U)) { EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[0U]); @@ -715,6 +726,7 @@ status_t SAI_TransferSendLoopEDMA(I2S_Type *base, EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[tcdIndex + 1U]); EDMA_TcdEnableInterrupts(¤tTCD[tcdIndex], (uint32_t)kEDMA_MajorInterruptEnable); } +#endif tcdIndex = tcdIndex + 1U; } @@ -787,6 +799,23 @@ status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, (uint32_t)handle->count * handle->bytesPerFrame, transfer->dataSize, kEDMA_PeripheralToMemory); +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + if (i == (loopTransferCount - 1U)) + { + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], &config, ¤tTCD[0U]); + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], + (uint32_t)kEDMA_MajorInterruptEnable); + handle->state = (uint32_t)kSAI_BusyLoopTransfer; + break; + } + else + { + EDMA_TcdSetTransferConfigExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], &config, + ¤tTCD[tcdIndex + 1U]); + EDMA_TcdEnableInterruptsExt(handle->dmaHandle->base, ¤tTCD[tcdIndex], + (uint32_t)kEDMA_MajorInterruptEnable); + } +#else if (i == (loopTransferCount - 1U)) { EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[0U]); @@ -799,6 +828,7 @@ status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[tcdIndex + 1U]); EDMA_TcdEnableInterrupts(¤tTCD[tcdIndex], (uint32_t)kEDMA_MajorInterruptEnable); } +#endif tcdIndex = tcdIndex + 1U; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.h index c5cb4d6ece..42507ff437 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sai_edma.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SAI_EDMA_H_ -#define _FSL_SAI_EDMA_H_ +#ifndef FSL_SAI_EDMA_H_ +#define FSL_SAI_EDMA_H_ #include "fsl_edma.h" #include "fsl_sai.h" @@ -22,15 +22,32 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) /*!< Version 2.5.0 */ -/*@}*/ +/*! @{ */ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 7, 1)) /*!< Version 2.7.1 */ +/*! @} */ typedef struct sai_edma_handle sai_edma_handle_t; /*! @brief SAI eDMA transfer callback function for finish and error */ typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); +/*!@brief sai interleave type */ +typedef enum _sai_edma_interleave +{ + kSAI_EDMAInterleavePerChannelSample = + 0U, /*!< SAI data interleave per channel sample + * --------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ....| + * --------------------------------------------------------------------------------------------------- + */ + kSAI_EDMAInterleavePerChannelBlock = + 1U, /*!< SAI data interleave per channel block + * -------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ... | RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------------- + */ +} sai_edma_interleave_t; + /*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ struct sai_edma_handle { @@ -47,6 +64,7 @@ struct sai_edma_handle uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + sai_edma_interleave_t interleaveType; /*!< Transfer interleave type */ volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ }; @@ -71,7 +89,6 @@ extern "C" { * * @param base SAI base pointer. * @param handle SAI eDMA handle pointer. - * @param base SAI peripheral base address. * @param callback Pointer to user callback function. * @param userData User parameter passed to the callback function. * @param txDmaHandle eDMA handle pointer, this handle shall be static allocated by users. @@ -90,7 +107,6 @@ void SAI_TransferTxCreateHandleEDMA(I2S_Type *base, * * @param base SAI base pointer. * @param handle SAI eDMA handle pointer. - * @param base SAI peripheral base address. * @param callback Pointer to user callback function. * @param userData User parameter passed to the callback function. * @param rxDmaHandle eDMA handle pointer, this handle shall be static allocated by users. @@ -102,50 +118,16 @@ void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, edma_handle_t *rxDmaHandle); /*! - * @brief Configures the SAI Tx audio format. + * @brief Initializes the SAI interleave type. * - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferTxSetConfigEDMA + * This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would + * like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is + * kSAI_EDMAInterleavePerChannelSample always * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. + * @param interleaveType Multi channel interleave type. */ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * @deprecated Do not use this function. It has been superceded by @ref SAI_TransferRxSetConfigEDMA - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - */ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); +void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType); /*! * @brief Configures the SAI Tx. diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.c index 4208097a8b..54a032e100 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -16,6 +16,10 @@ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.sctimer" #endif +#if defined(SCT_RSTS_N) || defined(SCT_RSTS) +#define FSL_FEATURE_SCT_HAS_RESET +#endif + /*! @brief Typedef for interrupt handler. */ typedef void (*sctimer_isr_t)(SCT_Type *base); @@ -43,6 +47,7 @@ static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FSL_FEATURE_SCT_HAS_RESET) #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) #if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET /*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ @@ -52,6 +57,7 @@ static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; static const reset_ip_name_t s_sctResets[] = SCT_RSTS; #endif #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SCT_HAS_RESET */ /*!< @brief SCTimer event Callback function. */ static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; @@ -113,10 +119,12 @@ status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(FSL_FEATURE_SCT_HAS_RESET) #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SCT_HAS_RESET */ /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ @@ -336,7 +344,7 @@ status_t SCTIMER_SetupPwm(SCT_Type *base, } else { - /* Set the initial output level to high which is the inactive state */ + /* Set the initial output level to high which is the active state */ base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); /* Clear the output when we reach the PWM pulse event */ SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); @@ -361,7 +369,7 @@ status_t SCTIMER_SetupPwm(SCT_Type *base, } else { - /* Set the initial output level to low which is the inactive state */ + /* Set the initial output level to low which is the active state */ base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); /* Set the output when we reach the PWM pulse event */ SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); @@ -402,6 +410,7 @@ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t du uint32_t periodMatchReg, pulseMatchReg; uint32_t pulsePeriod = 0, period; + bool isHighTrue = (0U != (base->OUT[output].CLR & (1UL << (event + 1U)))); /* Retrieve the match register number for the PWM period */ periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; @@ -411,22 +420,32 @@ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t du period = base->MATCH[periodMatchReg]; + /* Stop the counter before updating match register */ + SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ if (dutyCyclePercent >= 100U) { pulsePeriod = period + 2U; + + /* Set the initial output level base on output mode */ + if (isHighTrue) + { + base->OUTPUT |= (1UL << (uint32_t)output); + } + else + { + base->OUTPUT &= ~(1UL << (uint32_t)output); + } } else { pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); } - /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); - /* Update dutycycle */ - base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); - base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); + base->MATCH[pulseMatchReg] = pulsePeriod; + base->MATCHREL[pulseMatchReg] = pulsePeriod; /* Restart the counter */ SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); @@ -443,7 +462,7 @@ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t du * done when this event is triggered. * * param base SCTimer peripheral base address - * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * param howToMonitor Event type; options are available in the enumeration ::sctimer_event_t * param matchValue The match value that will be programmed to a match register * param whichIO The input or output that will be involved in event triggering. This field * is ignored if the event type is "match only" @@ -708,10 +727,10 @@ status_t SCTIMER_SetupCaptureAction(SCT_Type *base, { /* Set bit to enable event */ temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; - base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); + base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF0000U); /* Set this resource to be a capture rather than match */ temp = base->REGMODE_ACCESS16BIT.REGMODEL; - base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); + base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF0000U); /* Return the match register number */ *captureRegister = s_currentMatchhigh; @@ -754,9 +773,9 @@ void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint */ void SCTIMER_EventHandleIRQ(SCT_Type *base) { - uint32_t eventFlag = SCT0->EVFLAG; + uint32_t eventFlag = base->EVFLAG; /* Only clear the flags whose interrupt field is enabled */ - uint32_t clearFlag = (eventFlag & SCT0->EVEN); + uint32_t clearFlag = (eventFlag & base->EVEN); uint32_t mask = eventFlag; uint32_t i; @@ -780,12 +799,23 @@ void SCTIMER_EventHandleIRQ(SCT_Type *base) } /* Clear event interrupt flag */ - SCT0->EVFLAG = clearFlag; + base->EVFLAG = clearFlag; } +#if defined(SCT0) void SCT0_DriverIRQHandler(void); void SCT0_DriverIRQHandler(void) { s_sctimerIsr(SCT0); SDK_ISR_EXIT_BARRIER; } +#endif + +#if defined(SCT) +void SCT_DriverIRQHandler(void); +void SCT_DriverIRQHandler(void) +{ + s_sctimerIsr(SCT); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.h index 7cd481fd30..4df44e84b3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sctimer.h @@ -1,12 +1,12 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2022 NXP + * Copyright 2016-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SCTIMER_H_ -#define _FSL_SCTIMER_H_ +#ifndef FSL_SCTIMER_H_ +#define FSL_SCTIMER_H_ #include "fsl_common.h" @@ -22,9 +22,9 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 6)) /*!< Version */ -/*@}*/ +/*! @{ */ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) /*!< Version */ +/*! @} */ #ifndef SCT_EV_STATE_STATEMSKn #define SCT_EV_STATE_STATEMSKn(x) ((uint32_t)(x) & (((uint32_t)1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) @@ -1239,6 +1239,51 @@ static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint3 return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); } +/*! + * @brief Get the value of capture register. + * + * This function returns the captured value upon occurrence of the events selected by the corresponding + * Capture Control registers occurred. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param capChannel SCTimer capture register of capture channel. + * + * @return The SCTimer counter value at which this register was last captured. + */ +static inline uint32_t SCTIMER_GetCaptureValue(SCT_Type *base, sctimer_counter_t whichCounter, uint8_t capChannel) +{ + uint32_t value = 0; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(capChannel < SCT_CAPL_COUNT); + /* Use Counter_L bits when user wants to setup the Low counter */ + value = base->CAP_ACCESS16BIT[capChannel].CAPL; + break; + + case kSCTIMER_Counter_H: + assert(capChannel < SCT_CAPH_COUNT); + /* Use Counter_H bits when user wants to start the High counter */ + value = base->CAP_ACCESS16BIT[capChannel].CAPH; + break; + + case kSCTIMER_Counter_U: + assert(capChannel < SCT_CAP_COUNT); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + value = base->CAP[capChannel]; + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return value; +} + /*! * @brief SCTimer interrupt handler. * @@ -1254,4 +1299,4 @@ void SCTIMER_EventHandleIRQ(SCT_Type *base); /*! @}*/ -#endif /* _FSL_SCTIMER_H_ */ +#endif /* FSL_SCTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sema42.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sema42.c new file mode 100644 index 0000000000..fe0b750222 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sema42.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sema42.h" + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sema42" +#endif + +/* The first number write to RSTGDP when reset SEMA42 gate. */ +#define SEMA42_GATE_RESET_PATTERN_1 (0xE2U) +/* The second number write to RSTGDP when reset SEMA42 gate. */ +#define SEMA42_GATE_RESET_PATTERN_2 (0x1DU) + +#if defined(SEMA42_RSTS) +#define SEMA42_RESETS_ARRAY SEMA42_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for SEMA42 module. + * + * @param base SEMA42 peripheral base address. + */ +uint32_t SEMA42_GetInstance(SEMA42_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to sema42 bases for each instance. */ +static SEMA42_Type *const s_sema42Bases[] = SEMA42_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to sema42 clocks for each instance. */ +static const clock_ip_name_t s_sema42Clocks[] = SEMA42_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(SEMA42_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_sema42Resets[] = SEMA42_RESETS_ARRAY; +#endif + +/****************************************************************************** + * CODE + *****************************************************************************/ + +uint32_t SEMA42_GetInstance(SEMA42_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_sema42Bases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_sema42Bases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_sema42Bases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_sema42Bases)); + + return instance; +} + +/*! + * brief Initializes the SEMA42 module. + * + * This function initializes the SEMA42 module. It only enables the clock but does + * not reset the gates because the module might be used by other processors + * at the same time. To reset the gates, call either SEMA42_ResetGate or + * SEMA42_ResetAllGates function. + * + * param base SEMA42 peripheral base address. + */ +void SEMA42_Init(SEMA42_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_EnableClock(s_sema42Clocks[SEMA42_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(SEMA42_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_sema42Resets[SEMA42_GetInstance(base)]); +#endif +} + +/*! + * brief De-initializes the SEMA42 module. + * + * This function de-initializes the SEMA42 module. It only disables the clock. + * + * param base SEMA42 peripheral base address. + */ +void SEMA42_Deinit(SEMA42_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_DisableClock(s_sema42Clocks[SEMA42_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Tries to lock the SEMA42 gate. + * + * This function tries to lock the specific SEMA42 gate. If the gate has been + * locked by another processor, this function returns an error code. + * + * param base SEMA42 peripheral base address. + * param gateNum Gate number to lock. + * param procNum Current processor number. + * + * retval kStatus_Success Lock the sema42 gate successfully. + * retval kStatus_SEMA42_Busy Sema42 gate has been locked by another processor. + */ +status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum) +{ + status_t status; + + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA42_GATE_COUNT); + + ++procNum; + + /* Try to lock. */ + SEMA42_GATEn(base, gateNum) = procNum; + + /* Check locked or not. */ + if (procNum != SEMA42_GATEn(base, gateNum)) + { + status = kStatus_SEMA42_Busy; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Locks the SEMA42 gate. + * + * This function locks the specific SEMA42 gate. If the gate has been + * locked by other processors, this function waits until it is unlocked and then + * lock it. + * + * param base SEMA42 peripheral base address. + * param gateNum Gate number to lock. + * param procNum Current processor number. + */ +void SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum) +{ + while (kStatus_Success != SEMA42_TryLock(base, gateNum, procNum)) + { + } +} + +/*! + * brief Resets the SEMA42 gate to an unlocked status. + * + * This function resets a SEMA42 gate to an unlocked status. + * + * param base SEMA42 peripheral base address. + * param gateNum Gate number. + * + * retval kStatus_Success SEMA42 gate is reset successfully. + * retval kStatus_SEMA42_Reseting Some other reset process is ongoing. + */ +status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum) +{ + status_t status; + + /* + * Reset all gates if gateNum >= SEMA42_GATE_NUM_RESET_ALL + * Reset specific gate if gateNum < FSL_FEATURE_SEMA42_GATE_COUNT + */ + assert(!((gateNum < SEMA42_GATE_NUM_RESET_ALL) && (gateNum >= (uint8_t)FSL_FEATURE_SEMA42_GATE_COUNT))); + + /* Check whether some reset is ongoing. */ + /* + * $Branch Coverage Justification$ + * (0U == (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK))) not covered. Test unfeasible, + * the reset state is too short to catch. + */ + if (0U != (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK)) + { + /* + * $Line Coverage Justification$ + * Block not covered. Test unfeasible, the reset state is too short to catch. + */ + status = kStatus_SEMA42_Reseting; + } + else + { + /* First step. */ + base->RSTGT_W = SEMA42_RSTGT_W_RSTGDP(SEMA42_GATE_RESET_PATTERN_1); + /* Second step. */ + base->RSTGT_W = SEMA42_RSTGT_W_RSTGDP(SEMA42_GATE_RESET_PATTERN_2) | SEMA42_RSTGT_W_RSTGTN(gateNum); + + status = kStatus_Success; + } + + return status; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sema42.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sema42.h new file mode 100644 index 0000000000..5c0193a7a3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sema42.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SEMA42_H_ +#define FSL_SEMA42_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sema42 + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief SEMA42 driver version */ +#define FSL_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*! @} */ + +/*! + * @brief SEMA42 status return codes. + */ +enum +{ + kStatus_SEMA42_Busy = MAKE_STATUS(kStatusGroup_SEMA42, 0), /*!< SEMA42 gate has been locked by other processor. */ + kStatus_SEMA42_Reseting = MAKE_STATUS(kStatusGroup_SEMA42, 1) /*!< SEMA42 gate reseting is ongoing. */ +}; + +/*! + * @brief SEMA42 gate lock status. + */ +typedef enum _sema42_gate_status +{ + kSEMA42_Unlocked = 0U, /*!< The gate is unlocked. */ + kSEMA42_LockedByProc0 = 1U, /*!< The gate is locked by processor 0. */ + kSEMA42_LockedByProc1 = 2U, /*!< The gate is locked by processor 1. */ + kSEMA42_LockedByProc2 = 3U, /*!< The gate is locked by processor 2. */ + kSEMA42_LockedByProc3 = 4U, /*!< The gate is locked by processor 3. */ + kSEMA42_LockedByProc4 = 5U, /*!< The gate is locked by processor 4. */ + kSEMA42_LockedByProc5 = 6U, /*!< The gate is locked by processor 5. */ + kSEMA42_LockedByProc6 = 7U, /*!< The gate is locked by processor 6. */ + kSEMA42_LockedByProc7 = 8U, /*!< The gate is locked by processor 7. */ + kSEMA42_LockedByProc8 = 9U, /*!< The gate is locked by processor 8. */ + kSEMA42_LockedByProc9 = 10U, /*!< The gate is locked by processor 9. */ + kSEMA42_LockedByProc10 = 11U, /*!< The gate is locked by processor 10. */ + kSEMA42_LockedByProc11 = 12U, /*!< The gate is locked by processor 11. */ + kSEMA42_LockedByProc12 = 13U, /*!< The gate is locked by processor 12. */ + kSEMA42_LockedByProc13 = 14U, /*!< The gate is locked by processor 13. */ + kSEMA42_LockedByProc14 = 15U /*!< The gate is locked by processor 14. */ +} sema42_gate_status_t; + +/*! @brief The number to reset all SEMA42 gates. */ +#define SEMA42_GATE_NUM_RESET_ALL (64U) + +/*! @brief SEMA42 gate n register address. + * + * The SEMA42 gates are sorted in the order 3, 2, 1, 0, 7, 6, 5, 4, ... not in the order + * 0, 1, 2, 3, 4, 5, 6, 7, ... The macro SEMA42_GATEn gets the SEMA42 gate based on the gate + * index. + * + * The input gate index is XOR'ed with 3U: + * 0 ^ 3 = 3 + * 1 ^ 3 = 2 + * 2 ^ 3 = 1 + * 3 ^ 3 = 0 + * 4 ^ 3 = 7 + * 5 ^ 3 = 6 + * 6 ^ 3 = 5 + * 7 ^ 3 = 4 + * ... + */ +#define SEMA42_GATEn(base, n) (((volatile uint8_t *)(&((base)->GATE3)))[(n) ^ 3U]) + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the SEMA42 module. + * + * This function initializes the SEMA42 module. It only enables the clock but does + * not reset the gates because the module might be used by other processors + * at the same time. To reset the gates, call either SEMA42_ResetGate or + * SEMA42_ResetAllGates function. + * + * @param base SEMA42 peripheral base address. + */ +void SEMA42_Init(SEMA42_Type *base); + +/*! + * @brief De-initializes the SEMA42 module. + * + * This function de-initializes the SEMA42 module. It only disables the clock. + * + * @param base SEMA42 peripheral base address. + */ +void SEMA42_Deinit(SEMA42_Type *base); + +/*! + * @brief Tries to lock the SEMA42 gate. + * + * This function tries to lock the specific SEMA42 gate. If the gate has been + * locked by another processor, this function returns an error code. + * + * @param base SEMA42 peripheral base address. + * @param gateNum Gate number to lock. + * @param procNum Current processor number. + * + * @retval kStatus_Success Lock the sema42 gate successfully. + * @retval kStatus_SEMA42_Busy Sema42 gate has been locked by another processor. + */ +status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum); + +/*! + * @brief Locks the SEMA42 gate. + * + * This function locks the specific SEMA42 gate. If the gate has been + * locked by other processors, this function waits until it is unlocked and then + * lock it. + * + * @param base SEMA42 peripheral base address. + * @param gateNum Gate number to lock. + * @param procNum Current processor number. + */ +void SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum); + +/*! + * @brief Unlocks the SEMA42 gate. + * + * This function unlocks the specific SEMA42 gate. It only writes unlock value + * to the SEMA42 gate register. However, it does not check whether the SEMA42 gate is locked + * by the current processor or not. As a result, if the SEMA42 gate is not locked by the current + * processor, this function has no effect. + * + * @param base SEMA42 peripheral base address. + * @param gateNum Gate number to unlock. + */ +static inline void SEMA42_Unlock(SEMA42_Type *base, uint8_t gateNum) +{ + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA42_GATE_COUNT); + + /* ^= 0x03U because SEMA42 gates are in the order 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 7, ...*/ + SEMA42_GATEn(base, gateNum) = (uint8_t)kSEMA42_Unlocked; +} + +/*! + * @brief Gets the status of the SEMA42 gate. + * + * This function checks the lock status of a specific SEMA42 gate. + * + * @param base SEMA42 peripheral base address. + * @param gateNum Gate number. + * + * @return status Current status. + */ +static inline sema42_gate_status_t SEMA42_GetGateStatus(SEMA42_Type *base, uint8_t gateNum) +{ + assert(gateNum < (uint8_t)FSL_FEATURE_SEMA42_GATE_COUNT); + + return (sema42_gate_status_t)(SEMA42_GATEn(base, gateNum)); +} + +/*! + * @brief Resets the SEMA42 gate to an unlocked status. + * + * This function resets a SEMA42 gate to an unlocked status. + * + * @param base SEMA42 peripheral base address. + * @param gateNum Gate number. + * + * @retval kStatus_Success SEMA42 gate is reset successfully. + * @retval kStatus_SEMA42_Reseting Some other reset process is ongoing. + */ +status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum); + +/*! + * @brief Resets all SEMA42 gates to an unlocked status. + * + * This function resets all SEMA42 gate to an unlocked status. + * + * @param base SEMA42 peripheral base address. + * + * @retval kStatus_Success SEMA42 is reset successfully. + * @retval kStatus_SEMA42_Reseting Some other reset process is ongoing. + */ +static inline status_t SEMA42_ResetAllGates(SEMA42_Type *base) +{ + return SEMA42_ResetGate(base, SEMA42_GATE_NUM_RESET_ALL); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_SEMA42_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sinc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sinc.c new file mode 100644 index 0000000000..64c1692116 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sinc.c @@ -0,0 +1,353 @@ +/* + * Copyright 2022-2023 NXP + * + * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sinc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sinc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +static uint8_t SINC_GetInstance(SINC_Type *base); +#endif /*FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL*/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! brief Pointer to SINC clocks for each instance. */ +static clock_ip_name_t const s_sincClocks[] = SINC_CLOCKS; + +/*! brief Pointers to SINC bases for each instance. */ +static SINC_Type *const s_sincBases[] = SINC_BASE_PTRS; + +#endif /*FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL*/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +static uint8_t SINC_GetInstance(SINC_Type *base) +{ + uint8_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_sincBases); instance++) + { + if (s_sincBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_sincBases)); + + return instance; +} +#endif /*FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL*/ + +/*! + * brief Initialize selected SINC instance, including clock options and channel options. + * + * param base SINC peripheral base address. + * param config The pointer to sinc_config_t structure. + */ +void SINC_Init(SINC_Type *base, const sinc_config_t *config) +{ + assert(config != NULL); + uint8_t i = 0U; + + /* Enable SINC clock root. */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_sincClocks[SINC_GetInstance(base)]); +#endif /*FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL*/ + + SINC_EnableMaster(base, false); + /* Reset all function blocks except for the clock. */ + SINC_DoSoftwareReset(base); + + /* Set clock configuration. */ + SINC_SetClkPrescale(base, config->clockPreDivider); + SINC_SetModulatorClockDivider(base, config->modClkDivider); + SINC_DisableModulatorClockOutput(base, (uint32_t)kSINC_ModClk0, config->disableModClk0Output); + SINC_DisableModulatorClockOutput(base, (uint32_t)kSINC_ModClk1, config->disableModClk1Output); + SINC_DisableModulatorClockOutput(base, (uint32_t)kSINC_ModClk2, config->disableModClk2Output); + + SINC_DisableDozeMode(base, config->disableDozeMode); + + for (i = 0U; i < (uint8_t)SINC_CHANNEL_COUNT; i++) + { + if (config->channelsConfigArray[i] != NULL) + { + SINC_SetChannelConfig(base, (sinc_channel_id_t)i, config->channelsConfigArray[i]); + } + } + + SINC_EnableMaster(base, config->enableMaster); + if ((config->disableModClk0Output == false) && (config->enableMaster == true)) + { + while (!SINC_CheckModulatorClockReady(base, (uint32_t)kSINC_ModClk0)) + { + /* Loop until Modulator clock 0 is ready. */ + ; + } + } + else if ((config->disableModClk1Output == false) && (config->enableMaster == true)) + { + while (!SINC_CheckModulatorClockReady(base, (uint32_t)kSINC_ModClk1)) + { + /* Loop until Modulator clock 0 is ready. */ + ; + } + } + else if ((config->disableModClk2Output == false) && (config->enableMaster == true)) + { + while (!SINC_CheckModulatorClockReady(base, (uint32_t)kSINC_ModClk2)) + { + /* Loop until Modulator clock 0 is ready. */ + ; + } + } + else + { + /* Added comments to avoid violations of MISRA C-2012 rules. */ + } +} + +/*! + * brief De-initialize selected SINC instance. + * + * param base SINC peripheral base address. + */ +void SINC_Deinit(SINC_Type *base) +{ + SINC_DoSoftwareReset(base); + /* Disable master */ + SINC_EnableMaster(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_sincClocks[SINC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get default configuration. + * + * code {.c} + * config->clockPreDivider = kSINC_ClkPrescale1; + * config->modClkDivider = 2UL; + * config->disableModClk0Output = false; + * config->disableModClk1Output = false; + * config->disableModClk2Output = false; + * + * config->channelsConfigArray[SINC_CHANNEL_COUNT] = {NULL, NULL, NULL, NULL}; + * + * config->disableDozeMode = false; + * config->enableMaster = false; + * endcode + * + * + * param config The pointer to sinc_config_t structure, must not be NULL. + */ +void SINC_GetDefaultConfig(sinc_config_t *config) +{ + assert(config != NULL); + + config->clockPreDivider = kSINC_ClkPrescale1; + config->modClkDivider = 2UL; + config->disableModClk0Output = false; + config->disableModClk1Output = false; + config->disableModClk2Output = false; + + for (uint8_t i = 0U; i < (uint8_t)SINC_CHANNEL_COUNT; i++) + { + config->channelsConfigArray[i] = NULL; + } + + config->disableDozeMode = false; + config->enableMaster = false; +} + +/*! + * brief Set channel configurations, including input options, conversion options and protection options. + * + * param base SINC peripheral base address. + * param chId Selected channel id, please refer to sinc_channel_id_t. + * param chConfig Pointer to sinc_channel_config_t structure, must not be NULL. + */ +void SINC_SetChannelConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_config_t *chConfig) +{ + assert(chConfig != NULL); + + SINC_EnableChannel(base, chId, false); + + /* Set channel input options, including input clock and input source. */ + SINC_SetChannelInputOption(base, chId, chConfig->chInputOption); + + /* Set channel conversion options, including trigger source and primary filter. */ + SINC_SetChannelConversionOption(base, chId, chConfig->chConvOption); + + /* Set channel protection options, including SCD, limit check, CAD, zero crossing. */ + SINC_SetChannelProtectionOption(base, chId, chConfig->chProtectionOption); + + SINC_EnableChannelFIFO(base, chId, chConfig->bEnableFifo); + SINC_SetChannelFifoWatermark(base, chId, chConfig->u8FifoWaterMark); + + SINC_EnableChannelPrimaryDma(base, chId, chConfig->bEnablePrimaryDma); + +#if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) + SINC_SetChannelAltDmaSource(base, chId, chConfig->altDmaSource); +#endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */ + + SINC_SetChannelResultDataFormat(base, chId, chConfig->dataFormat); + + SINC_EnableChannel(base, chId, chConfig->bEnableChannel); +} +/*! + * brief Set channel input options, including input bit format, input bit source, input bit delay, input clock source, + * input clock edge. + * + * param base SINC peripheral base address. + * param chId Selected channel id, please refer to sinc_channel_id_t. + * param chInputOption Pointer to sinc_channel_input_option_t structure, must not be NULL. + */ +void SINC_SetChannelInputOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_input_option_t *chInputOption) +{ + assert(chInputOption != NULL); + + uint32_t u32Tmp; + + u32Tmp = ((base->CHANNEL[(uint8_t)chId].CCFR) & + ~(SINC_CCFR_IBFMT_MASK | SINC_CCFR_ICSEL_MASK | SINC_CCFR_ICESEL_MASK | SINC_CCFR_IBSEL_MASK)); + u32Tmp |= SINC_CCFR_ICSEL(chInputOption->inputClkSource) | SINC_CCFR_IBFMT(chInputOption->inputBitFormat) | + SINC_CCFR_ICESEL(chInputOption->inputClkEdge) | SINC_CCFR_IBSEL(chInputOption->inputBitSource); + base->CHANNEL[(uint8_t)chId].CCFR = u32Tmp; + + u32Tmp = ((base->CHANNEL[(uint8_t)chId].CACFR) & ~SINC_CACFR_IBDLY_MASK); + u32Tmp |= SINC_CACFR_IBDLY(chInputOption->inputBitDelay); + base->CHANNEL[(uint8_t)chId].CACFR = u32Tmp; +} + +/*! + * brief Set channel conversion options, including conversion mode, trigger source, and primary filter settings. + * + * param base SINC peripheral base address. + * param chId Selected channel id, please refer to sinc_channel_id_t. + * param chConvOption Pointer to sinc_channel_conv_option_t structure, must not be NULL. + */ +void SINC_SetChannelConversionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_conv_option_t *chConvOption) +{ + assert(chConvOption != NULL); + + /* Set trigger source. */ + SINC_SetChannelTriggerSource(base, chId, chConvOption->convTriggerSource); + + /* Set PF CIC options. */ + SINC_SetChannelConversionMode(base, chId, chConvOption->convMode); + SINC_SetChannelPfOrder(base, chId, chConvOption->pfOrder); + SINC_SetChannelPfOsr(base, chId, chConvOption->u16pfOverSampleRatio); + + /* Set HPF alpha coefficient. */ + SINC_SetChannelPfHpfAlphaCoeff(base, chId, chConvOption->pfHpfAlphaCoeff); + + /* Set shift options */ + SINC_SetChannelPfShiftConfig(base, chId, chConvOption->pfShiftDirection, chConvOption->u8pfShiftBitsNum); + + /* Set bias options. */ + SINC_SetChannelPfBiasConfig(base, chId, chConvOption->pfBiasSign, chConvOption->u32pfBiasValue); + + /* Enable channel's primary filter. */ + SINC_EnableChannelPrimaryFilter(base, chId, chConvOption->enableChPrimaryFilter); +} + +/*! + * brief Set channel protection options, including limit check, short-circuit detector, clock-absence detector, and + * zero-crossing detector. + * + * param base SINC peripheral base address. + * param chId Selected channel id, please refer to sinc_channel_id_t. + * param chProtection Pointer to sinc_channel_protection_option_t, must not be NULL. + */ +void SINC_SetChannelProtectionOption(SINC_Type *base, + sinc_channel_id_t chId, + sinc_channel_protection_option_t *chProtection) +{ + assert(chProtection != NULL); + + /* limit check */ + if (chProtection->limitDetectorMode == kSINC_Lmt_Disabled) + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_LMTEN_MASK; + } + else + { + SINC_SetChannelLowLimitThreshold(base, chId, chProtection->u32LowLimitThreshold); + SINC_SetChannelHighLimitThreshold(base, chId, chProtection->u32HighLimitThreshold); + base->CHANNEL[(uint8_t)chId].CPROT = (base->CHANNEL[(uint8_t)chId].CPROT & ~SINC_CPROT_LMTOP_MASK) | + SINC_CPROT_LMTOP((uint32_t)chProtection->limitDetectorMode & 0x3UL); + if (chProtection->bEnableLmtBreakSignal) + { + base->CHANNEL[(uint8_t)chId].CPROT |= + (((((uint32_t)(chProtection->limitDetectorMode)) & 0x1CUL) >> 2UL) << SINC_CPROT_LLMTBK_SHIFT); + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT &= + ~(((((uint32_t)(chProtection->limitDetectorMode)) & 0x1CUL) >> 2UL) << SINC_CPROT_LLMTBK_SHIFT); + } + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_LMTEN_MASK; + } + + /* Short-circuit detector. */ + if (chProtection->scdOperateMode == kSINC_Scd_OperateDisabled) + { + SINC_SetChannelScdOperateMode(base, chId, kSINC_Scd_OperateDisabled); + } + else + { + SINC_SetChannelScdLimitThreshold(base, chId, chProtection->u8ScdLimitThreshold); + SINC_SetChannelScdOption(base, chId, chProtection->scdOption); + SINC_EnableChannelScdBreakSignal(base, chId, chProtection->bEnableScdBreakSignal); + SINC_SetChannelScdOperateMode(base, chId, chProtection->scdOperateMode); + } + + /* Clock-absence detector. */ + SINC_EnableChannelCadBreakSignal(base, chId, chProtection->bEnableCadBreakSignal); + SINC_SetChannelCadLimitThreshold(base, chId, chProtection->cadLimitThreshold); + + /* zero-crossing detector. */ + SINC_SetChannelZcdOperateMode(base, chId, chProtection->zcdOperateMode); +} + +/*! + * brief Get selected channel's number of conversions. + * + * param base SINC peripheral base address. + * param chId Selected channel id, refer to sinc_channel_id_t for details. + * return uint8_t Selected channel's number of conversions. + */ +uint8_t SINC_GetChannelConversionCount(SINC_Type *base, sinc_channel_id_t chId) +{ + uint8_t u8Count; + + u8Count = (uint8_t)((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_CNUM_MASK) >> SINC_CSR_CNUM_SHIFT); + if ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_CNUM_OV_MASK) != 0UL) + { + u8Count += 128U; + } + + return u8Count; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sinc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sinc.h new file mode 100644 index 0000000000..b8bf925f37 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_sinc.h @@ -0,0 +1,2057 @@ +/* + * Copyright 2022-2024 NXP + * + * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SINC_H_ +#define FSL_SINC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sinc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief lower_component_name driver version 2.1.4. */ +#define FSL_SINC_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @} */ +#if defined(FSL_FEATURE_SINC_CHANNEL_COUNT) +#define SINC_CHANNEL_COUNT (FSL_FEATURE_SINC_CHANNEL_COUNT) +#else +#error "The definition of FSL_FEATURE_SINC_CHANNEL_COUNT is missing!" +#endif +#define SINC_NORMAL_INT_REG_ID (0ULL) +#define SINC_NORMAL_INT_NAME_COCIE (0ULL) +#define SINC_NORMAL_INT_NAME_CHFIE (1ULL) +#define SINC_NORMAL_INT_NAME_ZCDIE (2ULL) + +#define SINC_ERROR_INT_REG_ID (1ULL) +#define SINC_ERROR_INT_NAME_SCDIE (0ULL) +#define SINC_ERROR_INT_NAME_WLMTIE (1ULL) +#define SINC_ERROR_INT_NAME_LLMTIE (2ULL) +#define SINC_ERROR_INT_NAME_HLMTIE (3ULL) + +#define SINC_FIFO_CAD_INT_REG_ID (2ULL) +#define SINC_FIFO_CAD_INT_FUNFIE (0ULL) +#define SINC_FIFO_CAD_INT_FOVFIE (1ULL) +#define SINC_FIFO_CAD_INT_CADIE (2ULL) +#define SINC_FIFO_CAD_INT_SATIE (3ULL) + +#define SINC_ENCODE_INTERRUPT(regId, name, channelId) \ + ((((1ULL << (uint64_t)(channelId))) << ((uint64_t)(name) * (uint64_t)(SINC_CHANNEL_COUNT))) \ + << (uint64_t)(regId)*20ULL) + +#define SINC_DECODE_INTERRUPT(interruptMask) \ + normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \ + errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \ + fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL)) + +#define SINC_FIND_INT_FIELD_VALUE(mask, name) \ + ((((uint32_t)(mask) >> ((uint32_t)(name) * ((uint32_t)SINC_CHANNEL_COUNT))) & \ + ((1UL << ((uint32_t)SINC_CHANNEL_COUNT)) - 1UL)) \ + << (8UL * (uint32_t)(name))) + +#define SINC_FIND_STATUS_FIELD_VALUE(statusValue, name) \ + (((uint64_t)(statusValue) & (0xFFUL << ((uint64_t)(name)*8UL))) >> \ + ((uint64_t)(name) * (8UL - ((uint64_t)SINC_CHANNEL_COUNT)))) +/*! + * @brief The enumeration of SINC module's interrupts. + * @anchor sinc_interrupt_enable_t + */ +enum _sinc_interrupt_enable +{ + /* Normal interrupts enable. */ + /* Enable the conversion complete interrupt for channel 0. */ + kSINC_CH0ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 0ULL), + /* Enable the conversion complete interrupt for channel 1. */ + kSINC_CH1ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 1ULL), + /* Enable the conversion complete interrupt for channel 2. */ + kSINC_CH2ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 2ULL), + /* Enable the conversion complete interrupt for channel 3. */ + kSINC_CH3ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the conversion complete interrupt for channel 4. */ + kSINC_CH4ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 4ULL), +#endif + + /* Enable the data output ready interrupt for channel 0. */ + kSINC_CH0DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 0ULL), + /* Enable the data output ready interrupt for channel 1. */ + kSINC_CH1DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 1ULL), + /* Enable the data output ready interrupt for channel 2. */ + kSINC_CH2DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 2ULL), + /* Enable the data output ready interrupt for channel 3. */ + kSINC_CH3DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the data output ready interrupt for channel 4. */ + kSINC_CH4DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 4ULL), +#endif + + /* Enable the zero cross detected interrupt for channel 0. */ + kSINC_CH0ZeroCrossDetectedIntEnable = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 0ULL), + /* Enable the zero cross detected interrupt for channel 1. */ + kSINC_CH1ZeroCrossDetectedIntEnable = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 1ULL), + /* Enable the zero cross detected interrupt for channel 2. */ + kSINC_CH2ZeroCrossDetectedIntEnable = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 2ULL), + /* Enable the zero cross detected interrupt for channel 3. */ + kSINC_CH3ZeroCrossDetectedIntEnable = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the zero cross detected interrupt for channel 4. */ + kSINC_CH4ZeroCrossDetectedIntEnable = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 4ULL), +#endif + + /* Error interrupts enable. */ + /* Enable the short circuit detected interrupt for channel 0. */ + kSINC_CH0SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 0ULL), + /* Enable the short circuit detected interrupt for channel 1. */ + kSINC_CH1SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 1ULL), + /* Enable the short circuit detected interrupt for channel 2. */ + kSINC_CH2SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 2ULL), + /* Enable the short circuit detected interrupt for channel 3. */ + kSINC_CH3SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the short circuit detected interrupt for channel 4. */ + kSINC_CH4SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 4ULL), +#endif + + /* Enable the window limit interrupt for channel 0. */ + kSINC_CH0WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 0ULL), + /* Enable the window limit interrupt for channel 1. */ + kSINC_CH1WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 1ULL), + /* Enable the window limit interrupt for channel 2. */ + kSINC_CH2WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 2ULL), + /* Enable the window limit interrupt for channel 3. */ + kSINC_CH3WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the window limit interrupt for channel 4. */ + kSINC_CH4WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 4ULL), +#endif + + /* Enable the low limit interrupt for channel 0. */ + kSINC_CH0LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 0ULL), + /* Enable the low limit interrupt for channel 1. */ + kSINC_CH1LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 1ULL), + /* Enable the low limit interrupt for channel 2. */ + kSINC_CH2LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 2ULL), + /* Enable the low limit interrupt for channel 3. */ + kSINC_CH3LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the low limit interrupt for channel 4. */ + kSINC_CH4LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 4ULL), +#endif + + /* Enable the high limit interrupt for channel 0. */ + kSINC_CH0HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 0ULL), + /* Enable the high limit interrupt for channel 1. */ + kSINC_CH1HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 1ULL), + /* Enable the high limit interrupt for channel 2. */ + kSINC_CH2HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 2ULL), + /* Enable the high limit interrupt for channel 3. */ + kSINC_CH3HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the high limit interrupt for channel 4. */ + kSINC_CH4HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 4ULL), +#endif + + /* FIFO and CAD(clock-absence detector) Error interrupts enable. */ + /* Enable the FIFO underflow interrupt for channel 0. */ + kSINC_CH0FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 0ULL), + /* Enable the FIFO underflow interrupt for channel 1. */ + kSINC_CH1FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 1ULL), + /* Enable the FIFO underflow interrupt for channel 2. */ + kSINC_CH2FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 2ULL), + /* Enable the FIFO underflow interrupt for channel 3. */ + kSINC_CH3FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the FIFO underflow interrupt for channel 4. */ + kSINC_CH4FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 4ULL), +#endif + + /* Enable the FIFO overflow interrupt for channel 0. */ + kSINC_CH0FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 0ULL), + /* Enable the FIFO overflow interrupt for channel 1. */ + kSINC_CH1FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 1ULL), + /* Enable the FIFO overflow interrupt for channel 2. */ + kSINC_CH2FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 2ULL), + /* Enable the FIFO overflow interrupt for channel 3. */ + kSINC_CH3FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the FIFO overflow interrupt for channel 4. */ + kSINC_CH4FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 4ULL), +#endif + + /* Enable the clock absence interrupt for channel 0. */ + kSINC_CH0CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 0ULL), + /* Enable the clock absence interrupt for channel 1. */ + kSINC_CH1CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 1ULL), + /* Enable the clock absence interrupt for channel 2. */ + kSINC_CH2CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 2ULL), + /* Enable the clock absence interrupt for channel 3. */ + kSINC_CH3CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the clock absence interrupt for channel 4. */ + kSINC_CH4CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 4ULL), +#endif + + /* Enable the saturation interrupt for channel 0. */ + kSINC_CH0SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 0ULL), + /* Enable the saturation interrupt for channel 1. */ + kSINC_CH1SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 1ULL), + /* Enable the saturation interrupt for channel 2. */ + kSINC_CH2SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 2ULL), + /* Enable the saturation interrupt for channel 3. */ + kSINC_CH3SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Enable the saturation interrupt for channel 4. */ + kSINC_CH4SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 4ULL), +#endif +}; + +/*! + * @brief The enumeration of SINC interrupt status flags. + * @anchor sinc_interrupt_status_t + */ +enum _sinc_interrupt_status +{ + /* Normal interrupts status. */ + /* One conversion has finished and data is available in channel 0. */ + kSINC_CH0ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 0ULL), + /* One conversion has finished and data is available in channel 1. */ + kSINC_CH1ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 1ULL), + /* One conversion has finished and data is available in channel 2. */ + kSINC_CH2ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 2ULL), + /* One conversion has finished and data is available in channel 3. */ + kSINC_CH3ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* One conversion has finished and data is available in channel 4. */ + kSINC_CH4ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* The FIFO of channel 0 has exceeded its watermark level and the data is available in channel 0 result register. */ + kSINC_CH0DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 0ULL), + /* The FIFO of channel 1 has exceeded its watermark level and the data is available in channel 1 result register. */ + kSINC_CH1DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 1ULL), + /* The FIFO of channel 2 has exceeded its watermark level and the data is available in channel 2 result register. */ + kSINC_CH2DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 2ULL), + /* The FIFO of channel 3 has exceeded its watermark level and the data is available in channel 3 result register. */ + kSINC_CH3DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* The FIFO of channel 4 has exceeded its watermark level and the data is available in channel 4 result register. */ + kSINC_CH4DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* The resulting data on channel 0 crossed zero and changed sign. */ + kSINC_CH0ZeroCrossDetectedIntStatus = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 0ULL), + /* The resulting data on channel 1 crossed zero and changed sign. */ + kSINC_CH1ZeroCrossDetectedIntStatus = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 1ULL), + /* The resulting data on channel 2 crossed zero and changed sign. */ + kSINC_CH2ZeroCrossDetectedIntStatus = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 2ULL), + /* The resulting data on channel 3 crossed zero and changed sign. */ + kSINC_CH3ZeroCrossDetectedIntStatus = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* The resulting data on channel 4 crossed zero and changed sign. */ + kSINC_CH4ZeroCrossDetectedIntStatus = + SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* Error interrupts Status. */ + /* SINC detected a short circuit on channel 0. */ + kSINC_CH0SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 0ULL), + /* SINC detected a short circuit on channel 1. */ + kSINC_CH1SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 1ULL), + /* SINC detected a short circuit on channel 2. */ + kSINC_CH2SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 2ULL), + /* SINC detected a short circuit on channel 3. */ + kSINC_CH3SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* SINC detected a short circuit on channel 4. */ + kSINC_CH4SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* Indicates channel 0 exceeded its window limit. */ + kSINC_CH0WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 0ULL), + /* Indicates channel 1 exceeded its window limit. */ + kSINC_CH1WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 1ULL), + /* Indicates channel 2 exceeded its window limit. */ + kSINC_CH2WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 2ULL), + /* Indicates channel 3 exceeded its window limit. */ + kSINC_CH3WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Indicates channel 4 exceeded its window limit. */ + kSINC_CH4WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* Indicates channel 0 exceeded its low limit. */ + kSINC_CH0LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 0ULL), + /* Indicates channel 1 exceeded its window limit. */ + kSINC_CH1LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 1ULL), + /* Indicates channel 2 exceeded its window limit. */ + kSINC_CH2LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 2ULL), + /* Indicates channel 3 exceeded its window limit. */ + kSINC_CH3LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Indicates channel 4 exceeded its window limit. */ + kSINC_CH4LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* Indicates channel 0 exceeded its high limit. */ + kSINC_CH0HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 0ULL), + /* Indicates channel 1 exceeded its high limit. */ + kSINC_CH1HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 1ULL), + /* Indicates channel 2 exceeded its high limit. */ + kSINC_CH2HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 2ULL), + /* Indicates channel 3 exceeded its high limit. */ + kSINC_CH3HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Indicates channel 4 exceeded its high limit. */ + kSINC_CH4HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* FIFO and CAD(clock-absence detector) Error interrupts Status. */ + /* A FIFO underflow occurred on channel 0. */ + kSINC_CH0FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 0ULL), + /* A FIFO underflow occurred on channel 1. */ + kSINC_CH1FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 1ULL), + /* A FIFO underflow occurred on channel 2. */ + kSINC_CH2FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 2ULL), + /* A FIFO underflow occurred on channel 3. */ + kSINC_CH3FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* A FIFO underflow occurred on channel 4. */ + kSINC_CH4FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* A FIFO overflow occurred on channel 0. */ + kSINC_CH0FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 0ULL), + /* A FIFO overflow occurred on channel 1. */ + kSINC_CH1FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 1ULL), + /* A FIFO overflow occurred on channel 2. */ + kSINC_CH2FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 2ULL), + /* A FIFO overflow occurred on channel 3. */ + kSINC_CH3FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* A FIFO overflow occurred on channel 4. */ + kSINC_CH4FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* SINC detected the absence of a clock on channel 0. */ + kSINC_CH0CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 0ULL), + /* SINC detected the absence of a clock on channel 1. */ + kSINC_CH1CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 1ULL), + /* SINC detected the absence of a clock on channel 2. */ + kSINC_CH2CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 2ULL), + /* SINC detected the absence of a clock on channel 3. */ + kSINC_CH3CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* SINC detected the absence of a clock on channel 4. */ + kSINC_CH4CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ + + /* Channel 0 is saturated. */ + kSINC_CH0SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 0ULL), + /* Channel 1 is saturated. */ + kSINC_CH1SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 1ULL), + /* Channel 2 is saturated. */ + kSINC_CH2SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 2ULL), + /* Channel 3 is saturated. */ + kSINC_CH3SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 3ULL), +#if (SINC_CHANNEL_COUNT >= 5UL) + /* Channel 4 is saturated. */ + kSINC_CH4SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 4ULL), +#endif /* (SINC_CHANNEL_COUNT >= 5UL) */ +}; + +/*! + * @brief The enumeration of channel id, the sinc module contains 4 channels. + */ +typedef enum _sinc_channel_id +{ + kSINC_Channel0 = 0U, /*!< Channel 0. */ + kSINC_Channel1, /*!< Channel 1. */ + kSINC_Channel2, /*!< Channel 2. */ + kSINC_Channel3, /*!< Channel 3. */ +} sinc_channel_id_t; + +/*! + * @brief The enumeration of modulator clock name. + * @anchor _sinc_modulator_clock + */ +enum _sinc_modulator_clock +{ + kSINC_ModClk0 = 1UL, /*!< Modulator Clock 0 output. */ + kSINC_ModClk1 = 2UL, /*!< Modulator Clock 1 output. */ + kSINC_ModClk2 = 4UL, /*!< Modulator Clock 2 output. */ +}; + +/*! + * @brief The enumeration of input clock. + */ +typedef enum _sinc_inputClk_source +{ + kSINC_InputClk_SourceMclkOut0 = 0U, /*!< MCLK_OUT0 with internal routeback. */ + kSINC_InputClk_SourceMclkOut1 = 1U, /*!< MCLK_OUT1 with internal routeback. */ + kSINC_InputClk_SourceMclkOut2 = 2U, /*!< MCLK_OUT2 with internal routeback. */ + kSINC_InputClk_SourceExternalModulatorClk = 3U, /*!< External modulator clock dedicated to the selected channel. */ + kSINC_InputClk_SourceAdjacentChannelClk = 7U, /*!< Grouped clock shared with an adjacent channel. */ +} sinc_inputClk_source_t; + +/*! + * @brief The enumeration of clock edge. + */ +typedef enum _sinc_inputClk_edge +{ + kSINC_InputClk_EdgePositive = 1U, /*!< Positive edge. */ + kSINC_InputClk_EdgeNegative, /*!< Negative edge. */ + kSINC_InputClk_EdgeBoth, /*!< Both edges. */ + kSINC_InputClk_EdgeOddPositive, /*!< Every other odd positive edge. */ + kSINC_InputClk_EdgeEvenPositive, /*!< Every other even positive edge. */ + kSINC_InputClk_EdgeOddNegative, /*!< Every other odd negative edge. */ + kSINC_InputClk_EdgeEvenNegative, /*!< Every other even negative edge. */ +} sinc_inputClk_edge_t; + +/*! + * @brief The enumeration of input bit format. + */ +typedef enum _sinc_inputBit_format +{ + kSINC_InputBit_FormatExternalBitstream = 0U, /*!< External bitstream from the MBIT[n] signal. */ + kSINC_InputBit_FormatExternalManchesterCode, /*!< External Manchester code. */ + kSINC_InputBit_FormatInternal16bitParallelData, /*!< Internal 16-bit parallel data from MPDATA register. */ + kSINC_InputBit_FormatInternal32bitSerialData, /*!< Internal 32-bit serial data from MPDATA. */ +} sinc_inputBit_format_t; + +/*! + * @brief The enumeration of input bit source. + */ +typedef enum _sinc_inputBit_source +{ + kSINC_InputBit_SourceExternalBitstream = 0U, /*!< External bitstream from the MBIT[n] signal. */ + kSINC_InputBit_SourceInternalBitstream = 1U, /*!< Alternate internal bitstream from the INP[n] signal. */ + kSINC_InputBit_SourceAdjacentChannel = 3U, /*!< Grouped bitstream shared with an adjacent chanel. */ +} sinc_inputBit_source_t; + +/*! + * @brief The enumeration of trigger source. + */ +typedef enum _sinc_conv_trigger_source +{ + kSINC_ConvTrig_SoftPosEdge = 0x0U, /*!< Positive edge software trigger. */ + kSINC_ConvTrig_SoftHighLevel = 0x4U, /*!< High level software trigger. */ + kSINC_ConvTrig_HardPosEdge = 0x1U, /*!< Positive edge hardware trigger. */ + kSINC_ConvTrig_HardHighLevel = 0x5U, /*!< High level hardware trigger. */ + kSINC_ConvTrig_AdjacentChannel = 0x3U, /*!< Grouped hardware trigger shared with an adjacent channel. */ +} sinc_conv_trigger_source_t; + +/*! + * @brief The enumeration of conversion mode. + */ +typedef enum _sinc_conv_mode +{ + kSINC_ConvMode_Single = 0U, /*!< One conversion that follows an edge or level trigger event. */ + kSINC_ConvMode_Continuous, /*!< Multiple conversions that follow a triggering event, a new triggering event + cancels and restarts conversion. */ + kSINC_ConvMode_Always, /*!< Multiple conversions that follow the first triggering event, SINC ignores the + next triggering event. */ + kSINC_ConvMode_FixedNumber, /*!< Fixed number conversions that follow the first triggering event, a new + triggering event cancels and restarts conversion. */ +} sinc_conv_mode_t; + +/*! + * @brief The enumeration of pulse trigger mux. + */ +typedef enum _sinc_pulse_trigger_mux +{ + kSINC_PulseTrigger_Disabled = 0U, /*!< Disable pulse trigger output. */ + kSINC_PulseTrigger_MuxHighLimitLevelSignal, /*!< Select high limit level signal for pulse trigger output. */ + kSINC_PulseTrigger_MuxLowLimitLevelSignal, /*!< Select low limit level signal for pulse trigger output. */ + kSINC_PulseTrigger_MuxHighLowLimitLevelSignal, /*!< Select low or high limit level signal for pulse trigger output. + */ + kSINC_PulseTrigger_MuxWindowLimitLevelSignal, /*!< Select window limit level signal for pulse trigger output. */ + kSINC_PulseTrigger_MuxZeroCrossRisingLevelSignal, /*!< Select zero cross rising level signal for pulse trigger + output. */ + kSINC_PulseTrigger_MuxZeroCrossFallingLevelSignal, /*!< Select zero cross falling level signal for pulse trigger + output. */ + kSINC_PulseTrigger_MuxRsLimHighLevelSignal, /*!< Select level signal that indicates a high level from an RS + flip-flop or a schmitt trigger for pulse trigger output. */ + kSINC_PulseTrigger_MuxRsLimLowLevelSignal, /*!< Select level signal that indicates a low level from an RS flip-flop + or a schmitt trigger for pulse trigger output. */ + kSINC_PulseTrigger_MuxChannelRawInputModBitStream, /*!< Select channel raw input modulator bitstream for pulse + trigger output. */ + kSINC_PulseTrigger_MuxChannelRawInputModClock, /*!< Select channel raw input modulator clock for pulse trigger + output. */ + kSINC_PulseTrigger_MuxChannelRecoveredModBitStream, /*!< Select channel output recovered modulator bitstream for + pulse trigger output. */ + kSINC_PulseTrigger_MuxChannelRecoveredModClock, /*!< Select channel output recovered modulator clock for pulse + trigger output. */ + kSINC_PulseTrigger_MuxHighLimitPulseSignal, /*!< Select high limit pulse signal for pulse trigger output. */ + kSINC_PulseTrigger_MuxLowLimitPulseSignal, /*!< Select low limit pulse signal for pulse trigger output. */ + kSINC_PulseTrigger_MuxLimitPulseSignal, /*!< Select the pulse signal that indicates a high/low/window limit for + pulse trigger output. */ + kSINC_PulseTrigger_MuxWindowLimitPulseSignal, /*!< Select window limit pulse signal for pulse trigger output. */ + kSINC_PulseTrigger_MuxHighLowLimitPulseSignal, /*!< Select the pulse signal that indicates a high or low limit for + pulse trigger output. */ + kSINC_PulseTrigger_MuxZeroCrossRisePulseSignal, /*!< Select zero cross rise pulse signal for trigger output. */ + kSINC_PulseTrigger_MuxZeroCrossFallPulseSignal, /*!< Select zero cross fall pulse signal for trigger output. */ + kSINC_PulseTrigger_MuxZeroCrossRiseFallPulseSignal, /*!< Select zero cross rise/fall pulse signal for trigger + output. */ + kSINC_PulseTrigger_MuxFifoWatermarkOkPulseSignal, /*!< Select FIFO watermark OK pulse signal for trigger output. */ + kSINC_PulseTrigger_MuxFifoOverflowPulseSignal, /*!< Select FIFO overflow pulse signal. */ + kSINC_PulseTrigger_MuxFifoUnderflowPulseSignal, /*!< Select FIFO underflow pulse signal. */ + kSINC_PulseTrigger_MuxFifoEmptyPulseSignal, /*!< Select FIFO empty pulse signal. */ + kSINC_PulseTrigger_MuxClockMonitorAssertPulseSignal, /*!< Select clock monitor assert pulse signal. */ + kSINC_PulseTrigger_MuxShortCircuitAssertPulseSignal, /*!< Select short circuit assert pulse signal. */ + kSINC_PulseTrigger_MuxSaturationPulseSignal, /*!< Select saturation pulse signal. */ + kSINC_PulseTrigger_MuxConversionCompletePulseSignal, /*!< Select conversion complete pulse signal. */ +} sinc_pulse_trigger_mux_t; + +/*! + * @brief The enumeration of zero cross detector operate mode. + */ +typedef enum _sinc_zero_cross_operate_mode +{ + kSINC_ZCD_BothRiseAndFall = 0U, /*!< Zero cross detector operate on both rise and fall. */ + kSINC_ZCD_OnlyFall, /*!< Zero cross detector operate on fall edge. */ + kSINC_ZCD_OnlyRise, /*!< Zero cross detector operate on rise edge. */ + kSINC_ZCD_Disabled = 0xFU, /*!< Zero cross detector disabled. */ +} sinc_zero_cross_operate_mode_t; + +/*! + * @brief The enumeration of primary filter order. + */ +typedef enum _sinc_primary_filter_order +{ + kSINC_PF_FastSinc = 0U, /*!< Fast sinc filter, ORD is 4. */ + kSINC_PF_FirstOrder, /*!< First order filter, ORD is 1. */ + kSINC_PF_SecondOrder, /*!< Second order filter, ORD is 2. */ + kSINC_PF_ThirdOrder, /*!< Third order filter, ORD is 3. */ +} sinc_primary_filter_order_t; + +/*! + * @brief The enumeration of clock prescale that specify the clock divider ratio for the modulator clock. + */ +typedef enum _sinc_clock_prescale +{ + kSINC_ClkPrescale1 = 0UL, /*!< No prescale. */ + kSINC_ClkPrescale2, /*!< Modulator clock divider ratio is 2. */ + kSINC_ClkPrescale4, /*!< Modulator clock divider ratio is 4. */ + kSINC_ClkPrescale8, /*!< Modulator clock divider ratio is 8. */ +} sinc_clock_prescale_t; + +/*! + * @brief The enumeration of primary filter shift direction. + */ +typedef enum _sinc_primary_filter_shift_direction +{ + kSINC_PF_ShiftRight = 0U, /*!< Right shift the raw data. */ + kSINC_PF_ShiftLeft = 1U << 4U, /*!< Left shift the raw data. */ +} sinc_primary_filter_shift_direction_t; + +/*! + * @brief The enumeration of primary filer bias sign. + */ +typedef enum _sinc_primary_filter_bias_sign +{ + kSINC_PF_BiasPositive = 0UL, /*!< The bias sign is positive. */ + kSINC_PF_BiasNegative, /*!< The bias sign is negative. */ +} sinc_primary_filter_bias_sign_t; + +/*! + * @brief The enumeration of HPF DC remover Alpha coefficient. + */ +typedef enum _sinc_primary_filter_hpf_alpha_coeff +{ + kSINC_PF_HPFAlphaCoeff0 = 0UL, /*!< Disabled HPF. */ + kSINC_PF_HPFAlphaCoeff1, /*!< Alpha coefficient = 1 - (2^-5) */ + kSINC_PF_HPFAlphaCoeff2, /*!< Alpha coefficient = 1 - (2^-6) */ + kSINC_PF_HPFAlphaCoeff3, /*!< Alpha coefficient = 1 - (2^-7) */ + kSINC_PF_HPFAlphaCoeff4, /*!< Alpha coefficient = 1 - (2^-8) */ + kSINC_PF_HPFAlphaCoeff5, /*!< Alpha coefficient = 1 - (2^-9) */ + kSINC_PF_HPFAlphaCoeff6, /*!< Alpha coefficient = 1 - (2^-10) */ + kSINC_PF_HPFAlphaCoeff7, /*!< Alpha coefficient = 1 - (2^-11) */ + kSINC_PF_HPFAlphaCoeff8, /*!< Alpha coefficient = 1 - (2^-12) */ + kSINC_PF_HPFAlphaCoeff9, /*!< Alpha coefficient = 1 - (2^-13) */ + kSINC_PF_HPFAlphaCoeff10, /*!< Alpha coefficient = 1 - (2^-14) */ + kSINC_PF_HPFAlphaCoeff11, /*!< Alpha coefficient = 1 - (2^-15) */ + kSINC_PF_HPFAlphaCoeff12, /*!< Alpha coefficient = 1 - (2^-16) */ + kSINC_PF_HPFAlphaCoeff13, /*!< Alpha coefficient = 1 - (2^-17) */ + kSINC_PF_HPFAlphaCoeff14, /*!< Alpha coefficient = 1 - (2^-18) */ + kSINC_PF_HPFAlphaCoeff15, /*!< Alpha coefficient = 1 - (2^-19) */ +} sin_primary_filter_hpf_alpha_coeff_t; + +/*! + * @brief The enumeration of input bit delay. + */ +typedef enum _sinc_inputBit_delay +{ + kSINC_InputBit_DelayDisabled = 0U, /*!< Input modulator bitstream delay disabled. */ + kSINC_InputBit_Delay1ClkCycle, /*!< Input modulator bitstream delay 1 PRE_CLK cycle. */ + kSINC_InputBit_Delay2ClkCycle, /*!< Input modulator bitstream delay 2 PRE_CLK cycle. */ + kSINC_InputBit_Delay3ClkCycle, /*!< Input modulator bitstream delay 3 PRE_CLK cycle. */ + kSINC_InputBit_Delay4ClkCycle, /*!< Input modulator bitstream delay 4 PRE_CLK cycle. */ + kSINC_InputBit_Delay5ClkCycle, /*!< Input modulator bitstream delay 5 PRE_CLK cycle. */ + kSINC_InputBit_Delay6ClkCycle, /*!< Input modulator bitstream delay 6 PRE_CLK cycle. */ + kSINC_InputBit_Delay7ClkCycle, /*!< Input modulator bitstream delay 7 PRE_CLK cycle. */ + kSINC_InputBit_Delay8ClkCycle, /*!< Input modulator bitstream delay 8 PRE_CLK cycle. */ + kSINC_InputBit_Delay9ClkCycle, /*!< Input modulator bitstream delay 9 PRE_CLK cycle. */ + kSINC_InputBit_Delay10ClkCycle, /*!< Input modulator bitstream delay 10 PRE_CLK cycle. */ + kSINC_InputBit_Delay11ClkCycle, /*!< Input modulator bitstream delay 11 PRE_CLK cycle. */ + kSINC_InputBit_Delay12ClkCycle, /*!< Input modulator bitstream delay 12 PRE_CLK cycle. */ + kSINC_InputBit_Delay13ClkCycle, /*!< Input modulator bitstream delay 13 PRE_CLK cycle. */ + kSINC_InputBit_Delay14ClkCycle, /*!< Input modulator bitstream delay 14 PRE_CLK cycle. */ + kSINC_InputBit_Delay15ClkCycle, /*!< Input modulator bitstream delay 15 PRE_CLK cycle. */ +} sinc_inputBit_delay_t; + +/*! + * @brief The enumeration of short-circuit detector operate mode. + */ +typedef enum _sinc_scd_operate_mode +{ + kSINC_Scd_OperateAtChannelEnabled = 0U, /*!< SCD operates when the channel is enabled. */ + kSINC_Scd_OperateAtConversion, /*!< SCD operates when the PF is performing a conversion. */ + kSINC_Scd_OperateDisabled = 0xFU, /*!< Short circuit detect is disabled. */ +} sinc_scd_operate_mode_t; + +/*! + * @brief The enumeration of short-circuit detector option. + */ +typedef enum _sinc_scd_option +{ + kSINC_Scd_DetectRepeating0And1 = 0U, /*!< Both repeating 0 and 1 increment the SCD counter. */ + kSINC_Scd_DetectRepeatingOnly1, /*!< Only repeating 1 increment the SCD counter. */ + kSINC_Scd_DetectRepeatingOnly0, /*!< Only repeating 1 increment the SCD counter. */ +} sinc_scd_option_t; + +/*! + * @brief The mode of limit detector. + * + * @note The value of each limit detector contains lot of information: + * bit[1:0]: limit detection options, + * bit[2]: low limit break signal. + * bit[3]: window limit break signal. + * bit[4]: High limit break signal. + * bit[7]: Enable/disable limit detector. + */ +typedef enum _sinc_limit_detector_mode +{ + kSINC_Lmt_BothHighAndLowLimit = 0x94U, /*!< Limit detector is enabled, and compare the filter sample value to high + and low limit, if the value larger than high limit will trigger + interrupt or break, and if the value lower than low limit will trigger + interrupt or break. */ + kSINC_Lmt_OnlyHighLimit = 0x91U, /*!< Limit detector is enabled, and compare the filter sample value to high limit, + if the value larger than high limit will trigger interrupt or break. */ + kSINC_Lmt_OnlyLowLimit = 0x86U, /*!< Limit detector is enabled, and compare the filter sample value to low limit, if + the value lower than low limit will trigger interrupt or break. */ + kSINC_Lmt_WindowedValue = 0x8BU, /*!< Limit detector is enabled, and compare the filter sample value to high and low + limit, if the value higher than low limit and lower than high limit will trigger + interrupt or break. */ + kSINC_Lmt_Disabled = 0x0U, /*!< Limit detector is disabled. */ + +} sinc_limit_detector_mode_t; + +/*! + * @brief The enumeration of clock-absence threshold. + */ +typedef enum _sinc_cad_threshold +{ + kSINC_Cad_Disabled = 0U, /*!< Clock absence detector is disabled. */ + kSINC_Cad_Count1ClkCycle, /*!< Clock absence detector threshold is 1 clock cycle. */ + kSINC_Cad_Count2ClkCycle, /*!< Clock absence detector threshold is 2 clock cycle. */ + kSINC_Cad_Count3ClkCycle, /*!< Clock absence detector threshold is 3 clock cycle. */ + kSINC_Cad_Count4ClkCycle, /*!< Clock absence detector threshold is 4 clock cycle. */ + kSINC_Cad_Count5ClkCycle, /*!< Clock absence detector threshold is 5 clock cycle. */ + kSINC_Cad_Count6ClkCycle, /*!< Clock absence detector threshold is 6 clock cycle. */ + kSINC_Cad_Count7ClkCycle, /*!< Clock absence detector threshold is 7 clock cycle. */ + kSINC_Cad_Count8ClkCycle, /*!< Clock absence detector threshold is 8 clock cycle. */ + kSINC_Cad_Count9ClkCycle, /*!< Clock absence detector threshold is 9 clock cycle. */ + kSINC_Cad_Count10ClkCycle, /*!< Clock absence detector threshold is 10 clock cycle. */ + kSINC_Cad_Count11ClkCycle, /*!< Clock absence detector threshold is 11 clock cycle. */ + kSINC_Cad_Count12ClkCycle, /*!< Clock absence detector threshold is 12 clock cycle. */ + kSINC_Cad_Count13ClkCycle, /*!< Clock absence detector threshold is 13 clock cycle. */ + kSINC_Cad_Count14ClkCycle, /*!< Clock absence detector threshold is 14 clock cycle. */ + kSINC_Cad_Count15ClkCycle, /*!< Clock absence detector threshold is 15 clock cycle. */ +} sinc_cad_threshold_t; + +#if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) +/*! + * @brief The enumeration of alternate DMA source. + */ +typedef enum _sinc_alternate_dma_source +{ + kSINC_AltDma_Disabled = 0U, /*!< Alternate DMA disabled. */ + kSINC_AltDma_PfConvComplete, /*!< Select PF conversion complete for alternate DMA. */ + kSINC_AltDma_PfDataOutputReady, /*!< Select PF data output ready for alternate DMA. */ + kSINC_AltDma_ZeroCrossDetected, /*!< Select zero crossing detected for alternate DMA. */ + kSINC_AltDma_ShortCircuitDetected, /*!< Select short circuit detected for alternate DMA. */ + kSINC_AltDma_WindowLimitDetected, /*!< Select window limit detected for alternate DMA. */ + kSINC_AltDma_LowLimitDetected, /*!< Select low limit detected for alternate DMA. */ + kSINC_AltDma_HighLimitDetected, /*!< Select high limit detected for alternate DMA. */ + kSINC_AltDma_FifoUnderflow, /*!< Select FIFO underflow detected for alternate DMA. */ + kSINC_AltDma_FifoOverflow, /*!< Select FIFO overflow detected for alternate DMA. */ + kSINC_AltDma_ClockAbsence, /*!< Select clock absence detected for alternate DMA. */ + kSINC_AltDma_Saturation, /*!< Select channel saturation for alternate DMA. */ +} sinc_alternate_dma_source_t; +#endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */ + +/*! + * @brief The enumeration of result data format. + */ +typedef enum _sinc_result_data_format +{ + kSINC_LeftJustifiedSigned = 0U, /*!< Left justified, signed. */ + kSINC_LeftJustifiedUnsigned, /*!< Left justified, unsigned. */ +} sinc_result_data_format_t; + +/*! + * @brief The enumeration of debug output. + */ +typedef enum _sinc_debug_output +{ + kSINC_Debug_PfFinalData = 0U, /*!< Final data from PF(24 bits). */ + kSINC_Debug_OffsetData, /*!< Offset data(24 bits). */ + kSINC_Debug_PfShiftedData, /*!< Shifted data from the PF(24 bits). */ + kSINC_Debug_HpfData, /*!< DC remover(HPF) data(32 bits). */ + kSINC_Debug_CicRawData, /*!< Raw data from the PF's CIC filter. */ + kSINC_Debug_ScdHistoricalData, /*!< Historical data from SCD. */ + kSINC_Debug_ManchesterDecoderData, /*!< Data from the Manchester decoder. */ + kSINC_Debug_CadData, /*!< Data from CAD. */ + kSINC_Debug_FifoEntriesNum, /*!< Number of available entries in the FIFO. */ + kSINC_Debug_ParallelSerialConverterStatus, /*!< Status of the parallel or serial data converter. */ +} sinc_debug_output_t; + +/*! + * @brief The structure of channel input options, including input bit settings and input clock settings. + */ +typedef struct _sinc_channel_input_option +{ + sinc_inputBit_format_t inputBitFormat; /*!< Specify input bit format, please refer + to @ref sinc_inputBit_format_t. */ + sinc_inputBit_source_t inputBitSource; /*!< Specify input bit source, please refer + to @ref sinc_inputBit_source_t. */ + sinc_inputBit_delay_t inputBitDelay; /*!< Specify input bit delay, please refer to @ref sinc_inputBit_delay_t. */ + + sinc_inputClk_source_t inputClkSource; /*!< Specify input clock source, please refer + to @ref sinc_inputClk_source_t. */ + sinc_inputClk_edge_t inputClkEdge; /*!< Specify input clock edge, please refer to @ref sinc_inputClk_edge_t. */ +} sinc_channel_input_option_t; + +/*! + * @brief The structure of channel conversion options, including CIC filter settings, HPF settings, shift settings, + * bias settings and so on. + */ +typedef struct _sinc_channel_conv_option +{ + sinc_conv_mode_t convMode; /*!< Specify conversion mode, please refer to @ref sinc_conv_mode_t. */ + sinc_conv_trigger_source_t convTriggerSource; /*!< Specify conversion trigger source, please + refer to @ref sinc_conv_trigger_source_t. */ + + bool enableChPrimaryFilter; /*!< Enable/disable channel's primary filter. */ + sinc_primary_filter_order_t pfOrder; /*!< Specify the order of primary filter, please + refer to @ref sinc_primary_filter_order_t. */ + uint16_t u16pfOverSampleRatio; /*!< Control primary filter's OSR, the minimum permissible value is 3, + low value produce unpredictable result, the maximum permissible value depend on + PF order and the desired data format, if PF order is third order and data format + is signed, the maximum OSR value is 1289, if PF order is third order and data + format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR + value is 2047. Please note that the OSR for equation is + u16pfOverSampleRatio + 1*/ + + sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff; /*!< Specify HPF's alpha coeff, please + refer to @ref sin_primary_filter_hpf_alpha_coeff_t. */ + + sinc_primary_filter_shift_direction_t pfShiftDirection; /*!< Select shift direction, right or left. */ + uint8_t u8pfShiftBitsNum; /*!< Specify the number of bits to shift the data, ranges from 0 to 15. */ + + sinc_primary_filter_bias_sign_t pfBiasSign; /*!< Select bias sign, please refer + to @ref sinc_primary_filter_bias_sign_t. */ + uint32_t u32pfBiasValue; /*!< Range from 0 to 0x7FFFFFUL. */ +} sinc_channel_conv_option_t; + +/*! + * @brief The structure of channel protection options, including limit check settings, short-circuit settings, + * clock-absence settings, and zero-crossing settings. + */ +typedef struct _sinc_channel_protection_option +{ + sinc_limit_detector_mode_t limitDetectorMode; /*!< Specify limit detector mode, please + refer to @ref sinc_limit_detector_mode_t. */ + bool bEnableLmtBreakSignal; /*!< Enable/disable limit break signal, + the details of break signal is depended on detector mode. */ + uint32_t u32LowLimitThreshold; /*!< Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL. */ + uint32_t u32HighLimitThreshold; /*!< Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL. */ + + sinc_scd_operate_mode_t scdOperateMode; /*!< Enable/disable scd, and set SCD operate timming. */ + uint8_t u8ScdLimitThreshold; /*!< Range from 2 to 255, 0 and 1 are prohibited. */ + sinc_scd_option_t scdOption; /*!< Specify SCD options, please refer to @ref sinc_scd_option_t. */ + bool bEnableScdBreakSignal; /*!< Enable/disable SCD break signal. */ + + sinc_cad_threshold_t cadLimitThreshold; /*!< Specify the threshold value for the CAD counter. */ + bool bEnableCadBreakSignal; /*!< Enable/disable CAD break signal. */ + + sinc_zero_cross_operate_mode_t zcdOperateMode; /*!< Specify zero cross detector operate mode. */ +} sinc_channel_protection_option_t; + +/*! + * @brief The structure of channel configurations, including channel input option, channel conversion options, channel + * protection options, and so on. + */ +typedef struct _sinc_channel_config +{ + bool bEnableChannel; /*!< Enable/disable channel. */ + bool bEnableFifo; /*!< Enable/disable channel's FIFO. */ + uint8_t u8FifoWaterMark; /*!< Specify the fifo watermark, range from 0 to 15. */ + bool bEnablePrimaryDma; /*!< Used to enable/disable primary DMA. */ +#if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) + sinc_alternate_dma_source_t altDmaSource; /*!< Set channel's alternate DMA source, please refer + to @ref sinc_alternate_dma_source_t. */ +#endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */ + sinc_result_data_format_t dataFormat; /*!< Set channel's result data format, please refer + to @ref sinc_result_data_format_t. */ + + sinc_channel_input_option_t *chInputOption; /*!< The pointer to @ref sinc_channel_input_option_t that contains + channel input options. */ + sinc_channel_conv_option_t *chConvOption; /*!< The pointer to @ref sinc_channel_conv_option_t that contains + channel conversion options. */ + sinc_channel_protection_option_t *chProtectionOption; /*!< The pointer to @ref sinc_channel_protection_option_t + that contains channel protection options. */ +} sinc_channel_config_t; + +/*! + * @brief The structure of sinc configurations, including clock settings anc channels' settings. + */ +typedef struct _sinc_config +{ + sinc_clock_prescale_t clockPreDivider; /*!< Specify modulator clock pre divider, please + refer to @ref sinc_clock_prescale_t. */ + uint32_t modClkDivider; /*!< Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in + the MCLK output, write an even value to*/ + bool disableModClk0Output; /*!< Disable/enable modulator clock0 output. */ + bool disableModClk1Output; /*!< Disable/enable modulator clock1 output. */ + bool disableModClk2Output; /*!< Disable/enable modulator clock2 output. */ + + sinc_channel_config_t *channelsConfigArray[SINC_CHANNEL_COUNT]; /*!< The array that contains 4 elements, and the + type of each element is \b sinc_channel_config_t *, + channelsConfigArray[0] corresponding to channel0, + channelsConfigArray[1] corresponding to channel1, + channelsConfigArray[2] corresponding to channel2, + channelsConfigArray[3] corresponding to channel3, if some channels + are not used, the corresponding elements should be set as NULL. */ + + bool disableDozeMode; /*!< Disable/enable SINC module when the chip enters Doze or stop mode. */ + bool enableMaster; /*!< Enable/disable all function blocks of SINC module. */ +} sinc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name SINC Generic Functional Control APIs + * @{ + */ + +/*! + * @brief Initialize selected SINC instance, including clock options and channel options. + * + * @param base SINC peripheral base address. + * @param config The pointer to @ref sinc_config_t structure. + */ +void SINC_Init(SINC_Type *base, const sinc_config_t *config); + +/*! + * @brief De-initialize selected SINC instance. + * + * @param base SINC peripheral base address. + */ +void SINC_Deinit(SINC_Type *base); + +/*! + * @brief Get default configuration. + * + * @code {.c} + * config->clockPreDivider = kSINC_ClkPrescale1; + * config->modClkDivider = 2UL; + * config->disableModClk0Output = false; + * config->disableModClk1Output = false; + * config->disableModClk2Output = false; + * + * config->channelsConfigArray[4] = {NULL, NULL, NULL, NULL}; + * + * config->disableDozeMode = false; + * config->enableMaster = false; + * @endcode + * + * + * @param config The pointer to @ref sinc_config_t structure, must not be NULL. + */ +void SINC_GetDefaultConfig(sinc_config_t *config); + +/*! @} */ + +/*! + * @name SINC Generic Low Level Control APIs + * @{ + */ + +/*! + * @brief Enable/disable all function blocks enabled in their respective registers. + * + * @param base SINC peripheral base address. + * @param enable Used to enable/disable all function blocks: + * - \b true Enable all function blocks, please note that clock must be configured previously; + * - \b false Disable all function blocks. + */ +static inline void SINC_EnableMaster(SINC_Type *base, bool enable) +{ + if (enable) + { + base->MCR |= SINC_MCR_MEN_MASK; + } + else + { + base->MCR &= ~SINC_MCR_MEN_MASK; + } +} + +/*! + * @brief Reset all function blocks(except for the clock blocks), interrupt statuses. + * + * @param base SINC peripheral base address. + */ +static inline void SINC_DoSoftwareReset(SINC_Type *base) +{ + base->MCR |= SINC_MCR_RST_MASK; + base->MCR &= ~SINC_MCR_RST_MASK; +} + +/*! + * @brief Disable/enable SINC module when the chip enters Doze or Stop mode. + * + * @param base SINC peripheral base address. + * @param disable Used to control if module functional when the chip enters Doze and Stop mode: + * - \b true Disable SINC when the chip enters Doze or Stop mode; + * - \b false Enable SINC when the chip enters Doze or stop mode. + */ +static inline void SINC_DisableDozeMode(SINC_Type *base, bool disable) +{ + if (disable) + { + base->MCR |= SINC_MCR_DOZEN_MASK; + } + else + { + base->MCR &= ~SINC_MCR_DOZEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Clock Control APIs + * @{ + */ + +/*! + * @brief Check whether selected modulator clocks are ready. + * + * @note The result of this APIs means all selected modulator clocks are (not) ready. + * + * @param base SINC peripheral base address. + * @param modClkMasks The mask of modulator clocks, please refer to @ref _sinc_modulator_clock. + * + * @retval true The input mask of modulator clocks are ready. + * @retval false The input mask of modulator clocks are not ready. + */ +static inline bool SINC_CheckModulatorClockReady(SINC_Type *base, uint32_t modClkMasks) +{ + return ((base->SR & (modClkMasks << SINC_SR_MCLKRDY0_SHIFT)) != 0UL); +} + +/*! + * @brief Disable/enable modulator clocks' output. + * + * @note By default, modulator clock's output is enabled. + * + * @param base SINC peripheral base address. + * @param modClkMasks The mask of modulator clocks, please refer to @ref _sinc_modulator_clock. + * @param disable Used to enable/disable clock output: + * - \b true Disable modulator clocks' output; + * - \b false Enable modulator clocks' output. + */ +static inline void SINC_DisableModulatorClockOutput(SINC_Type *base, uint32_t modClkMasks, bool disable) +{ + if (disable) + { + base->MCR |= (modClkMasks << SINC_MCR_MCLK0DIS_SHIFT); + } + else + { + base->MCR &= ~(modClkMasks << SINC_MCR_MCLK0DIS_SHIFT); + } +} + +/*! + * @brief Set the clock divider ratio for the modulator clock. + * + * @param base SINC peripheral base address. + * @param clkPrescale Clock prescale value, please refer to @ref sinc_clock_prescale_t. + */ +static inline void SINC_SetClkPrescale(SINC_Type *base, sinc_clock_prescale_t clkPrescale) +{ + base->MCR = (((base->MCR) & (~SINC_MCR_PRESCALE_MASK)) | SINC_MCR_PRESCALE(clkPrescale)); +} + +/*! + * @brief Set modulator clock divider value. + * + * @note IMCLK0 = PRE_CLK / modClkDivider, the minimum clock divider ration is 2. + * + * @param base SINC peripheral base address. + * @param modClkDivider Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in the MCLK output, + * write an even value to \b modClkDivider . + */ +static inline void SINC_SetModulatorClockDivider(SINC_Type *base, uint32_t modClkDivider) +{ + assert(modClkDivider != 0UL); + assert(modClkDivider != 1UL); + + base->MCR = (((base->MCR) & (~SINC_MCR_MCLKDIV_MASK)) | SINC_MCR_MCLKDIV((modClkDivider - 1UL))); +} + +/* !} */ + +/*! + * @name Channel Functional Control APIs + * @{ + */ + +/*! + * @brief Set channel configurations, including input options, conversion options and protection options. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param chConfig Pointer to @ref sinc_channel_config_t structure, must not be NULL. + */ +void SINC_SetChannelConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_config_t *chConfig); + +/*! + * @brief Set channel input options, including input bit format, input bit source, input bit delay, input clock source, + * input clock edge. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param chInputOption Pointer to @ref sinc_channel_input_option_t structure, must not be NULL. + */ +void SINC_SetChannelInputOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_input_option_t *chInputOption); + +/*! + * @brief Set channel conversion options, including conversion mode, trigger source, and primary filter settings. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param chConvOption Pointer to @ref sinc_channel_conv_option_t structure, must not be NULL. + */ +void SINC_SetChannelConversionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_conv_option_t *chConvOption); + +/*! + * @brief Set channel protection options, including limit check, short-circuit detector, clock-absence detector, and + * zero-crossing detector. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param chProtection Pointer to @ref sinc_channel_protection_option_t, must not be NULL. + */ +void SINC_SetChannelProtectionOption(SINC_Type *base, + sinc_channel_id_t chId, + sinc_channel_protection_option_t *chProtection); + +/*! @} */ + +/*! + * @name Channel Result/FIFO Low Level Control APIs + * @{ + */ + +/*! + * @brief Read selected channel's result data. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * + * @return Result data of the selected channel, 24 bits width. + */ +static inline uint32_t SINC_ReadChannelResultData(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CRDATA & SINC_CRDATA_RDATA_MASK) >> SINC_CRDATA_RDATA_SHIFT); +} + +/*! + * @brief Enable/disable FIFO transfers for the primary filter. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable channl FIFO: + * - \b true Enable channel FIFO. + * - \b false Disable channle FIFO. + */ +static inline void SINC_EnableChannelFIFO(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_FIFOEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_FIFOEN_MASK; + } +} + +/*! + * @brief Set the FIFO watermark. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param fifoWaterMark Specify the fifo watermark, range from 0 to 15. + */ +static inline void SINC_SetChannelFifoWatermark(SINC_Type *base, sinc_channel_id_t chId, uint8_t fifoWaterMark) +{ + base->CHANNEL[(uint8_t)chId].CCFR = + ((base->CHANNEL[(uint8_t)chId].CCFR) & (~SINC_CCFR_FIFOWMK_MASK)) | (SINC_CCFR_FIFOWMK(fifoWaterMark)); +} + +/*! + * @brief Enable/disable selected channel. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable selected channel: + * - \b true Enable selected channel; + * - \b false Disable selected channel. + */ +static inline void SINC_EnableChannel(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_CHEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_CHEN_MASK; + } +} + +/*! + * @brief Enable/disable selected channel's primary DMA transfers when the channel's FIFO exceeds its watermark. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable primary DMA : + * - \b true Enable primary DMA; + * - \b false Disable primary DMA. + */ +static inline void SINC_EnableChannelPrimaryDma(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_DMAEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_DMAEN_MASK; + } +} + +#if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) +/*! + * @brief Set selected channel's alternate DMA source selection. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param altDmaSource Specify the trigger source for alternate DMA, please refer to @ref sinc_alternate_dma_source_t. + */ +static inline void SINC_SetChannelAltDmaSource(SINC_Type *base, + sinc_channel_id_t chId, + sinc_alternate_dma_source_t altDmaSource) +{ + base->CHANNEL[(uint8_t)chId].CACFR = + ((base->CHANNEL[(uint8_t)chId].CACFR & ~SINC_CACFR_ADMASEL_MASK) | SINC_CACFR_ADMASEL(altDmaSource)); +} +#endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */ + +/*! + * @brief Set selected channel's result data format. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param dataFormat Specify the result data format, please refer to @ref sinc_result_data_format_t. + */ +static inline void SINC_SetChannelResultDataFormat(SINC_Type *base, + sinc_channel_id_t chId, + sinc_result_data_format_t dataFormat) +{ + if (dataFormat == kSINC_LeftJustifiedSigned) + { + base->CHANNEL[(uint8_t)chId].CCFR &= ~SINC_CCFR_RDFMT_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCFR |= SINC_CCFR_RDFMT_MASK; + } +} + +/*! + * @brief Get the number of remaining data entries in the FIFO. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * + * @return The number of remaining data entries in the FIFO. + */ +static inline uint8_t SINC_GetChannelFifoCount(SINC_Type *base, sinc_channel_id_t chId) +{ + return (uint8_t)(base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_FIFOAVIL_MASK); +} + +/*! + * @brief Check whether the data in selected channel's result data register is stable when FIFO is disabled. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * + * @retval true Data in selected channel's result data regiter is stable. + * @retval false Data in selected channel's result data register is not stable. + */ +static inline bool SINC_CheckChannelResultDataReady(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_RDRS_MASK) != SINC_CSR_RDRS_MASK); +} + +/*! + * @brief Check whether selected channel's FIFO is empty. + * + * @param base SINC peripheral base address. + * @param chId The id of sinc channel to check. + * + * @retval true Selected channel's FIFO is empty. + * @retval false Selected channel's FIFO is not empty. + */ +static inline bool SINC_CheckChannelFifoEmpty(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->SR & (SINC_SR_FIFOEMPTY0_MASK << (uint32_t)chId)) != 0UL); +} + +/*! @} */ + +/*! + * @name Channel Conversion Low Level Control APIs + * @{ + */ + +/*! + * @brief Trigger selected channel's conversion. + * + * @param base SINC peripheral base address. + * @param chMask The mask of channels to trigger. + */ +static inline void SINC_AffirmChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask) +{ + base->MCR |= chMask; +} + +/*! + * @brief Negate the trigger of selected channel. + * + * @param base SINC peripheral base address. + * @param chMask The mask of channels. + */ +static inline void SINC_NegateChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask) +{ + base->MCR &= ~chMask; +} + +/*! + * @brief Set selected channel's conversion mode. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param mode The conversion mode to set, please refer to @ref sinc_conv_mode_t. + */ +static inline void SINC_SetChannelConversionMode(SINC_Type *base, sinc_channel_id_t chId, sinc_conv_mode_t mode) +{ + base->CHANNEL[(uint8_t)chId].CDR = ((base->CHANNEL[(uint8_t)chId].CDR & ~SINC_CDR_PFCM_MASK) | SINC_CDR_PFCM(mode)); +} + +/*! + * @brief Set selected channel's trigger source. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param triggerSource Trigger source to set, please refer to @ref sinc_conv_trigger_source_t. + */ +static inline void SINC_SetChannelTriggerSource(SINC_Type *base, + sinc_channel_id_t chId, + sinc_conv_trigger_source_t triggerSource) +{ + base->CHANNEL[(uint8_t)chId].CCFR = + (((base->CHANNEL[(uint8_t)chId].CCFR) & ~(SINC_CCFR_ITLVL_MASK | SINC_CCFR_ITSEL_MASK)) | + SINC_CCFR_ITLVL((((uint32_t)triggerSource) & 0x4UL) >> 2UL) | + SINC_CCFR_ITSEL((uint32_t)triggerSource & 0x3UL)); +} + +/*! + * @brief Set multipurpose data to selected channel. + * + * @note If input bit format is set as ManchesterCode, multipurpose data indicates the Manchester decoder threshold + * value and is 11 bits width; if input bit format is set as parallel, multipurpose data indicates the parallel 16-bit + * data and is 16 bits width; if input bit format is set as serial, multipurpose data indicates the serial data and is + * 32 bits width. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param data Multipurpose data to set. + */ +static inline void SINC_SetChannelMultipurposeData(SINC_Type *base, sinc_channel_id_t chId, uint32_t data) +{ + base->CHANNEL[(uint8_t)chId].CMPDATA = SINC_CMPDATA_MPDATA(data); +} + +/*! + * @brief Set selected channel's PF order. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param pfOrder Primary filter order to set, please refer to @ref sinc_primary_filter_order_t + */ +static inline void SINC_SetChannelPfOrder(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_order_t pfOrder) +{ + base->CHANNEL[(uint8_t)chId].CDR = + ((base->CHANNEL[(uint8_t)chId].CDR) & (~SINC_CDR_PFORD_MASK)) | (SINC_CDR_PFORD(pfOrder)); +} + +/*! + * @brief Set selected channel's PF over sample rate. + * + * @note If PF order is third order and data format is signed, the maximum OSR value is 1289, if PF order is third + * order and data format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR value is 2047. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param pfOsr Control the channel's PF OSR, the minimum permissible value is 3, low value produce unpredictable + * result, the maximum permissible value depend on PF order and the desired data format. + */ +static inline void SINC_SetChannelPfOsr(SINC_Type *base, sinc_channel_id_t chId, uint16_t pfOsr) +{ + base->CHANNEL[(uint8_t)chId].CDR = + ((base->CHANNEL[(uint8_t)chId].CDR) & (~SINC_CDR_PFOSR_MASK)) | (SINC_CDR_PFOSR(pfOsr)); +} + +/*! + * @brief set selected channel's HPF DC remover Alpha coefficient. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param pfHpfAlphaCoeff Specify the HPF alpha coefficient or disable HPF as described in @ref + * sin_primary_filter_hpf_alpha_coeff_t. + */ +static inline void SINC_SetChannelPfHpfAlphaCoeff(SINC_Type *base, + sinc_channel_id_t chId, + sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff) +{ + base->CHANNEL[(uint8_t)chId].CACFR = + ((base->CHANNEL[(uint8_t)chId].CACFR) & (~SINC_CACFR_HPFA_MASK)) | (SINC_CACFR_HPFA(pfHpfAlphaCoeff)); +} + +/*! + * @brief Set the value that shifts the PF data for the correct 24-bit precision. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param pfShiftDirection Specify the PF shift direction, including right and left. + * @param pfShiftBitsNum Specify the PF shift value, range from 0 to 15. + */ +static inline void SINC_SetChannelPfShiftConfig(SINC_Type *base, + sinc_channel_id_t chId, + sinc_primary_filter_shift_direction_t pfShiftDirection, + uint8_t pfShiftBitsNum) +{ + base->CHANNEL[(uint8_t)chId].CCFR = ((base->CHANNEL[(uint8_t)chId].CCFR) & (~SINC_CCFR_PFSFT_MASK)) | + (SINC_CCFR_PFSFT((uint32_t)pfShiftDirection | (uint32_t)pfShiftBitsNum)); +} + +/*! + * @brief Set the bias offset for the selected channel's PF. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param pfBiasSign Specify the bias sign, please refer to @ref sinc_primary_filter_bias_sign_t for details. + * @param pfBiasValue The bias value to subtracted from the output of PF shift block, range from 0 to 0x7FFFFFUL. + */ +static inline void SINC_SetChannelPfBiasConfig(SINC_Type *base, + sinc_channel_id_t chId, + sinc_primary_filter_bias_sign_t pfBiasSign, + uint32_t pfBiasValue) +{ + base->CHANNEL[(uint8_t)chId].CBIAS = (uint32_t)pfBiasSign << 31UL | pfBiasValue << SINC_CBIAS_BIAS_SHIFT; +} + +/*! + * @brief Enable/disable selected channel's primary filter. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable primary filter: + * - \b true Enable channel's PF; + * - \b false Disable channel's PF. + */ +static inline void SINC_EnableChannelPrimaryFilter(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_PFEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_PFEN_MASK; + } +} + +/*! + * @brief Check whether selected channel's multipurpose data is ready to write parallel or serial data. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * + * @retval true Selected channel's multipurpose data is ready to write parallel or serial data. + * @retval false Selected channel's multipurpose data is not ready to write parallel or serial data. + */ +static inline bool SINC_CheckChannelParallelSerialDataReady(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_PSRDY_MASK) == SINC_CSR_PSRDY_MASK); +} + +/*! + * @brief Check whether primary CIC filter saturation occurred. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * + * @retval true Selected channel's primary CIC filter saturation occurred. + * @retval false Selected channel's primary CIC filter saturation did not occurred. + */ +static inline bool SINC_CheckChannelPrimaryCICSaturation(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_PFSAT_MASK) == SINC_CSR_PFSAT_MASK); +} + +/*! + * @brief Check whether HPF saturation occurred. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * + * @retval true Selected channel's HPF saturation occurred. + * @retval false Selected channel's HPF saturation did not occurred. + */ +static inline bool SINC_CheckChannelHPFSaturation(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_HPFSAT_MASK) == SINC_CSR_HPFSAT_MASK); +} + +/*! + * @brief Check whether Shift saturation occurred. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * + * @retval true Selected channel's shift saturation occurred. + * @retval false Selected channel's shift saturation did not occurred. + */ +static inline bool SINC_CheckChannelShiftSaturation(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_SFTSAT_MASK) == SINC_CSR_SFTSAT_MASK); +} + +/*! + * @brief Check whether bias saturation occurred. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * + * @retval true Selected channel's bias saturation occurred. + * @retval false Selected channel's bias saturation did not occurred. + */ +static inline bool SINC_CheckChannelBiasSaturation(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_BIASSAT_MASK) == SINC_CSR_BIASSAT_MASK); +} + +/*! + * @brief Get selected channel's number of conversions. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details. + * @return uint8_t Selected channel's number of conversions. + */ +uint8_t SINC_GetChannelConversionCount(SINC_Type *base, sinc_channel_id_t chId); + +/*! + * @brief Check whether the selected channel is in conversion. + * + * @param base SINC peripheral base address. + * @param chId The id of sinc channel to check. + * + * @retval false Selected channel conversion not in progress. + * @retval true Selected channel conversion in progress. + */ +static inline bool SINC_CheckChannelConvProgress(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->SR & (((uint32_t)SINC_SR_CIP0_MASK) << (uint32_t)chId)) != 0UL); +} + +/*! + * @brief Check whether the selected channel is ready for conversion. + * + * @param base SINC peripheral base address. + * @param chId The id of sinc channel to check. + * + * @retval true Selected channel is ready for conversion. + * @retval false Selected channel is not ready for conversion. + */ +static inline bool SINC_CheckChannelReadyForConv(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->SR & (((uint32_t)SINC_SR_CHRDY0_MASK) << (uint32_t)chId)) != 0UL); +} + +/*! @} */ + +/*! + * @name Channel Protection Low Level Control APIs + * @{ + */ + +/*! + * @brief Set selected channel's low-limit threshold value. + * + * @note When the data exceeds the low-limit threshold value, a low-limit event occurs, and the limit threshold format + * is determines by channel's result data format @ref sinc_result_data_format_t. + * + * @note Low limit value must lower than high limit value, otherwise the low-limit threshold does not work. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param lowLimitThreshold Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL. + */ +static inline void SINC_SetChannelLowLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint32_t lowLimitThreshold) +{ + base->CHANNEL[(uint8_t)chId].CLOLMT = SINC_CLOLMT_LOLMT(lowLimitThreshold); +} + +/*! + * @brief Set selected channel's high-limit threshold value. + * + * @note When the data exceeds the high-limit threshold value, a high-limit event occurs, and the limit threshold format + * is determines by channel's result data format @ref sinc_result_data_format_t. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param highLimitThreshold Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL. + */ +static inline void SINC_SetChannelHighLimitThreshold(SINC_Type *base, + sinc_channel_id_t chId, + uint32_t highLimitThreshold) +{ + base->CHANNEL[(uint8_t)chId].CHILMT = SINC_CHILMT_HILMT(highLimitThreshold); +} + +/*! + * @brief Set selected channel's limit detector mode. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param mode Specify the mode of limit detector, please refer to @ref sinc_limit_detector_mode_t. + */ +static inline void SINC_SetChannelLimitDetectorMode(SINC_Type *base, + sinc_channel_id_t chId, + sinc_limit_detector_mode_t mode) +{ + if (mode == kSINC_Lmt_Disabled) + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_LMTEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT = + (base->CHANNEL[(uint8_t)chId].CPROT & ~SINC_CPROT_LMTOP_MASK) | SINC_CPROT_LMTOP((uint32_t)mode & 0x3UL); + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_LMTEN_MASK; + } +} + +/*! + * @brief Enable/disable selected channel's high limit break signal. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable high limit break signal: + * - \b true Enable the automatic assertion of the BREAK_HIGH signal when SINC detects a high-limit event on + * the selected channel. + * - \b false Disable high limit break signal. + */ +static inline void SINC_EnableChannelHighLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_HLMTBK_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_HLMTBK_MASK; + } +} + +/*! + * @brief Enable/disable selected channel's window limit break signal. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable window limit break signal: + * - \b true Enable the automatic assertion of the BREAK_WIN signal when SINC detects a window-limit event on + * the selected channel. + * - \b false Disable window limit break signal. + */ +static inline void SINC_EnableChannelWindowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_WLMTBK_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_WLMTBK_MASK; + } +} + +/*! + * @brief Enable/disable selected channel's low limit break signal. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable low limit break signal: + * - \b true Enable the automatic assertion of the BREAK_LOW signal when SINC detects a low-limit event on + * the selected channel. + * - \b false Disable low limit break signal. + */ +static inline void SINC_EnableChannelLowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_HLMTBK_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_HLMTBK_MASK; + } +} + +/*! + * @brief Set selected channel's short-circuit detector operate mode. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param opMode Specify the operate mode to set, please refer to @ref sinc_scd_operate_mode_t. + */ +static inline void SINC_SetChannelScdOperateMode(SINC_Type *base, + sinc_channel_id_t chId, + sinc_scd_operate_mode_t opMode) +{ + if (opMode == kSINC_Scd_OperateDisabled) + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_SCDEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT = + ((base->CHANNEL[(uint8_t)chId].CPROT & ~SINC_CPROT_SCDCM_MASK) | SINC_CPROT_SCDCM(opMode)); + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_SCDEN_MASK; + } +} + +/*! + * @brief Set selected channel's Scd limit threshold. + * + * @note The SCD counter tracks the number of received bits with the same repeating value(always 0 or always 1, set by + * SINC_SetChannelScdOption()), if that + * number exceeds the scdLimitThreshold, an SCD event occurs on the associated channel. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param u8ScdLimitThreshold Specify the threshold value for the SCD counter, range from 2 to 255. + */ +static inline void SINC_SetChannelScdLimitThreshold(SINC_Type *base, + sinc_channel_id_t chId, + uint8_t u8ScdLimitThreshold) +{ + assert(u8ScdLimitThreshold != 0U); + assert(u8ScdLimitThreshold != 1U); + + base->CHANNEL[(uint8_t)chId].CPROT = + ((base->CHANNEL[(uint8_t)chId].CPROT) & (~SINC_CPROT_SCDLMT_MASK)) | (SINC_CPROT_SCDLMT(u8ScdLimitThreshold)); +} + +/*! + * @brief Set selected channel's SDC option. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param option Specify which repeating bit value increments the SCD counter. + */ +static inline void SINC_SetChannelScdOption(SINC_Type *base, sinc_channel_id_t chId, sinc_scd_option_t option) +{ + base->CHANNEL[(uint8_t)chId].CPROT = + ((base->CHANNEL[(uint8_t)chId].CPROT) & (~SINC_CPROT_SCDOP_MASK)) | (SINC_CPROT_SCDOP(option)); +} + +/*! + * @brief Enable/disable the automatic assertion of the BREAK_SCD signal when SINC detects an SCD event on the selected + * channel. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disable SCD break signal: + * - \b true Enable SCD break signal. + * - \b false Disable SCD break signal. + */ +static inline void SINC_EnableChannelScdBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_SCDBK_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_SCDBK_MASK; + } +} + +/*! + * @brief Set the threshold value for the CAD counter. + * + * @note The CAD counter tracks the number of clock cycles during which SINC does not detect a clock, if that number + * exceeds the threshold value, a CAD event occurs on the selected channel. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param cadLimitThreshold Specify the threshold value for the CAD counter, please refer to @ref sinc_cad_threshold_t. + */ +static inline void SINC_SetChannelCadLimitThreshold(SINC_Type *base, + sinc_channel_id_t chId, + sinc_cad_threshold_t cadLimitThreshold) +{ + base->CHANNEL[(uint8_t)chId].CPROT = + ((base->CHANNEL[(uint8_t)chId].CPROT) & (~SINC_CPROT_CADLMT_MASK)) | (SINC_CPROT_CADLMT(cadLimitThreshold)); + if (cadLimitThreshold == kSINC_Cad_Disabled) + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_CADEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_CADEN_MASK; + } +} + +/*! + * @brief Enable/disable the automatic assertion of the BREAK_CAD signal when SINC detects a CAD event on the assoicated + * channel. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param enable Used to enable/disble CAD break signal: + * - \b true Enable selected channel's CAD break signal; + * - \b false Disable selected channel's CAD break signal. + */ +static inline void SINC_EnableChannelCadBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable) +{ + if (enable) + { + base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_CADBK_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_CADBK_MASK; + } +} + +/*! + * @brief Set selected channel's zero-crossing detector operate mode. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param opMode Specify the operate mode, please refer to @ref sinc_zero_cross_operate_mode_t. + */ +static inline void SINC_SetChannelZcdOperateMode(SINC_Type *base, + sinc_channel_id_t chId, + sinc_zero_cross_operate_mode_t opMode) +{ + if (opMode == kSINC_ZCD_Disabled) + { + base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_ZCDEN_MASK; + } + else + { + base->CHANNEL[(uint8_t)chId].CCFR = + ((base->CHANNEL[(uint8_t)chId].CCFR) & (~SINC_CCFR_ZCOP_MASK)) | (SINC_CCFR_ZCOP(opMode)); + base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_ZCDEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Channel Debug Low Level Control APIs + * @{ + */ + +#if !((defined(FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX) && FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX)) +/*! + * @brief Set selected channel's pulse trigger mux. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param pulseTrigMux Used to selected the signal for pulse-trigger output. + */ +static inline void SINC_SetChannelPulseTriggerMux(SINC_Type *base, + sinc_channel_id_t chId, + sinc_pulse_trigger_mux_t pulseTrigMux) +{ + base->CHANNEL[(uint8_t)chId].CACFR = + ((base->CHANNEL[(uint8_t)chId].CACFR & ~SINC_CACFR_PTMUX_MASK) | SINC_CACFR_PTMUX(pulseTrigMux)); +} +#endif /* !(defined(FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX) && FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX) */ + +/*! + * @brief Set selected channel's debug output. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * @param debugOutput Used to select debug output, please refer to @ref sinc_debug_output_t. + */ +static inline void SINC_SetChannelDebugOutput(SINC_Type *base, sinc_channel_id_t chId, sinc_debug_output_t debugOutput) +{ + base->CHANNEL[(uint8_t)chId].CCR = + ((base->CHANNEL[(uint8_t)chId].CCR & ~SINC_CCR_DBGSEL_MASK) | SINC_CCR_DBGSEL(debugOutput)); +} + +/*! + * @brief Start selected channel's debug data latch proceduce. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + */ +static inline void SINC_LatchChannelDebugProceduce(SINC_Type *base, sinc_channel_id_t chId) +{ + base->CHANNEL[(uint8_t)chId].CSR |= SINC_CSR_SRDS_MASK; +} + +/*! + * @brief Check if the selected channel's debug data is valid. + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * + * @retval true Data is valid. + * @retval false Data is invalid. + */ +static inline bool SINC_CheckChannelDebugDataValid(SINC_Type *base, sinc_channel_id_t chId) +{ + return ((base->CHANNEL[(uint8_t)chId].CSR & (SINC_CSR_SRDS_MASK | SINC_CSR_DBGRS_MASK)) == 0UL); +} + +/*! + * @brief Return selected channel's the debug data that requested by SINC_SetChannelDebugOutput(). + * + * @param base SINC peripheral base address. + * @param chId Selected channel id, please refer to @ref sinc_channel_id_t. + * + * @return Selected channel's debug data. + */ +static inline uint32_t SINC_GetChannelDebugData(SINC_Type *base, sinc_channel_id_t chId) +{ + return base->CHANNEL[(uint8_t)chId].CDBGR; +} + +/*! @} */ + +/*! + * @name Interrupt Control APIs + * @{ + */ + +/*! + * @brief Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on. + * + * @param base SINC peripheral base address. + * @param interruptMasks Mask of interrupts to enable, should be the OR'ed value of @ref sinc_interrupt_enable_t. + */ +static inline void SINC_EnableInterrupts(SINC_Type *base, uint64_t interruptMasks) +{ + uint32_t normalIntMask; + uint32_t errorIntMask; + uint32_t fifoCadIntMask; + + /* + * #define SINC_DECODE_INTERRUPT(interruptMask) \ + * normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \ + * errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \ + * fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL)) + */ + SINC_DECODE_INTERRUPT(interruptMasks); + + base->NIE |= SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_COCIE) | + SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_CHFIE) | + SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_ZCDIE); + + base->EIE |= SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_SCDIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_WLMTIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_LLMTIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_HLMTIE); + + base->FIFOIE |= SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FUNFIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FOVFIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_CADIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_SATIE); +} + +/*! + * @brief Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on. + * + * @param base SINC peripheral base address. + * @param interruptMasks Mask of interrupts to disable, should be the OR'ed value of @ref sinc_interrupt_enable_t. + */ +static inline void SINC_DisableInterrupts(SINC_Type *base, uint64_t interruptMasks) +{ + uint32_t normalIntMask; + uint32_t errorIntMask; + uint32_t fifoCadIntMask; + + /* + * #define SINC_DECODE_INTERRUPT(interruptMask) \ + * normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \ + * errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \ + * fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL)) + */ + SINC_DECODE_INTERRUPT(interruptMasks); + + base->NIE &= ~(SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_COCIE) | + SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_CHFIE) | + SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_ZCDIE)); + + base->EIE &= ~(SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_SCDIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_WLMTIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_LLMTIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_HLMTIE)); + + base->FIFOIE &= ~(SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FUNFIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FOVFIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_CADIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_SATIE)); +} + +/*! + * @brief Get interrupt status flags. + * + * @param base SINC peripheral base address. + * + * @return SINC module's interrupt status flags, the OR'ed value of @ref sinc_interrupt_status_t. + */ +static inline uint64_t SINC_GetInterruptStatus(SINC_Type *base) +{ + uint64_t allIntStatusValue = 0ULL; + uint32_t normalIntStatusValue = base->NIS; + uint32_t errorIntStatusValue = base->EIS; + uint32_t fifoCadIntStatusValue = base->FIFOIS; + + allIntStatusValue |= ((uint64_t)SINC_FIND_STATUS_FIELD_VALUE(normalIntStatusValue, SINC_NORMAL_INT_NAME_COCIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(normalIntStatusValue, SINC_NORMAL_INT_NAME_CHFIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(normalIntStatusValue, SINC_NORMAL_INT_NAME_ZCDIE)); + + allIntStatusValue |= (((uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_SCDIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_WLMTIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_LLMTIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_HLMTIE)) + << 20ULL); + + allIntStatusValue |= (((uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_FUNFIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_FOVFIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_CADIE) | + (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_SATIE)) + << 40ULL); + + return (uint64_t)allIntStatusValue; +} + +/*! + * @brief Clear selected mask of interrupt status flags. + * + * @param base SINC peripheral base address. + * @param statusMasks The mask of interrupt status flags to clear, should be the OR'ed + * value of @ref sinc_interrupt_status_t. + */ +static inline void SINC_ClearInterruptStatus(SINC_Type *base, uint64_t statusMasks) +{ + uint32_t normalIntMask; + uint32_t errorIntMask; + uint32_t fifoCadIntMask; + + /* + * #define SINC_DECODE_INTERRUPT(interruptMask) \ + * normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \ + * errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \ + * fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL)) + */ + SINC_DECODE_INTERRUPT(statusMasks); + + base->EIS = (SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_SCDIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_WLMTIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_LLMTIE) | + SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_HLMTIE)); + + base->FIFOIS = (SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FUNFIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FOVFIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_CADIE) | + SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_SATIE)); + + base->NIS = (SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_COCIE) | + SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_CHFIE) | + SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_ZCDIE)); +} + +/*! @} */ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_SINC_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard.h index 2c7f81609b..cacf963ff6 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SMARTCARD_H_ -#define _FSL_SMARTCARD_H_ +#ifndef FSL_SMARTCARD_H_ +#define FSL_SMARTCARD_H_ #include "fsl_common.h" @@ -21,11 +21,11 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief Smart card driver version 2.2.2. +/*! @{ */ +/*! @brief Smart card driver version 2.3.0. */ -#define FSL_SMARTCARD_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) -/*@}*/ +#define FSL_SMARTCARD_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*! @} */ /*! @brief Smart card global define which specify number of clock cycles until initial 'TS' character has to be received */ @@ -271,4 +271,4 @@ typedef struct _smartcard_context } smartcard_context_t; /*! @}*/ -#endif /* _FSL_SMARTCARD_H_*/ +#endif /* FSL_SMARTCARD_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_emvsim.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_emvsim.h index 397966bc02..503f411aaa 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_emvsim.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_emvsim.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SMARTCARD_EMVSIM_H_ -#define _FSL_SMARTCARD_EMVSIM_H_ +#ifndef FSL_SMARTCARD_EMVSIM_H_ +#define FSL_SMARTCARD_EMVSIM_H_ #include "fsl_smartcard.h" @@ -171,7 +171,7 @@ status_t SMARTCARD_EMVSIM_Control(EMVSIM_Type *base, * @param context A pointer to a smart card driver context structure. */ void SMARTCARD_EMVSIM_IRQHandler(EMVSIM_Type *base, smartcard_context_t *context); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -179,4 +179,4 @@ void SMARTCARD_EMVSIM_IRQHandler(EMVSIM_Type *base, smartcard_context_t *context /*! @}*/ -#endif /* _FSL_SMARTCARD_EMVSIM_H_*/ +#endif /* FSL_SMARTCARD_EMVSIM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_phy.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_phy.h index 21408bef76..007eee6763 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_phy.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartcard_phy.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SMARTCARD_PHY_H_ -#define _FSL_SMARTCARD_PHY_H_ +#ifndef FSL_SMARTCARD_PHY_H_ +#define FSL_SMARTCARD_PHY_H_ #include "fsl_smartcard.h" @@ -116,7 +116,7 @@ status_t SMARTCARD_PHY_Control(void *base, #if defined(USING_PHY_TDA8035) void SMARTCARD_PHY_IRQHandler(void *base, smartcard_context_t *context); #endif -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -124,4 +124,4 @@ void SMARTCARD_PHY_IRQHandler(void *base, smartcard_context_t *context); /*! @}*/ -#endif /* _FSL_SMARTCARD_PHY_H_*/ +#endif /* FSL_SMARTCARD_PHY_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma.c new file mode 100644 index 0000000000..d1560d46b6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma.c @@ -0,0 +1,159 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_smartdma" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef void (*smartdma_func_t)(void); + +#define SMARTDMA_HANDSHAKE_EVENT 0U +#define SMARTDMA_HANDSHAKE_ENABLE 1U +#define SMARTDMA_MASK_RESP 2U +#define SMARTDMA_ENABLE_AHBBUF 3U +#define SMARTDMA_ENABLE_GPISYNCH 4U + +#if defined(SMARTDMA0) && !(defined(SMARTDMA)) +#define SMARTDMA SMARTDMA0 +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static smartdma_func_t *s_smartdmaApiTable; +static smartdma_callback_t s_smartdmaCallback; +static void *s_smartdmaCallbackParam; +static smartdma_param_t s_smartdmaParam; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ +/*! + * brief Initialize the SMARTDMA. + * + * param apiMemAddr The address firmware will be copied to. + * param firmware The firmware to use. + * param firmwareSizeByte Size of firmware. + */ +void SMARTDMA_Init(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte) +{ + SMARTDMA_InitWithoutFirmware(); + SMARTDMA_InstallFirmware(apiMemAddr, firmware, firmwareSizeByte); +} + +/*! + * brief Initialize the SMARTDMA. + * + * This function is similar with SMARTDMA_Init, the difference is this function + * does not install the firmware, the firmware could be installed using + * SMARTDMA_InstallFirmware. + */ +void SMARTDMA_InitWithoutFirmware(void) +{ + /* Clear Smart DMA RAM */ + RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Smartdma); +} + +/*! + * @brief Install the firmware. + * + * param apiMemAddr The address firmware will be copied to. + * param firmware The firmware to use. + * param firmwareSizeByte Size of firmware. + */ +void SMARTDMA_InstallFirmware(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte) +{ + (void)memcpy((void *)(uint8_t *)apiMemAddr, firmware, firmwareSizeByte); + SMARTDMA->CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); + s_smartdmaApiTable = (smartdma_func_t *)apiMemAddr; +} + +/*! + * brief Install the complete callback function.. + * + * param callback The callback called when smartdma program finished. + */ +void SMARTDMA_InstallCallback(smartdma_callback_t callback, void *param) +{ + s_smartdmaCallback = callback; + s_smartdmaCallbackParam = param; +} + +/*! + * brief Boot the SMARTDMA to run program. + * + * param apiIndex Index of the API to call. + * param pParam Pointer to the parameter allocated by caller. + * param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + */ +void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask) +{ + SMARTDMA->ARM2EZH = (uint32_t)(uint8_t *)pParam | (uint32_t)mask; + SMARTDMA->BOOTADR = (uint32_t)(s_smartdmaApiTable[apiIndex]); + SMARTDMA->CTRL = 0xC0DE0011U | (0U << SMARTDMA_MASK_RESP) | (0U << SMARTDMA_ENABLE_AHBBUF); /* BOOT */ +}; + +/* + * brief Copy SMARTDMA params and Boot to run program. + * + * This function is similar with SMARTDMA_Boot, the only difference + * is, this function copies the *pParam to a local variable, upper layer + * can free the pParam's memory before the SMARTDMA execution finished, + * for example, upper layer can define the param as a local variable. + * + * param apiIndex Index of the API to call. + * param pParam Pointer to the parameter. + * param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + * note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_Boot1(uint32_t apiIndex, const smartdma_param_t *pParam, uint8_t mask) +{ + (void)memcpy(&s_smartdmaParam, pParam, sizeof(smartdma_param_t)); + SMARTDMA_Boot(apiIndex, &s_smartdmaParam, mask); +} + +/*! + * brief Deinitialize the SMARTDMA. + */ +void SMARTDMA_Deinit(void) +{ + SMARTDMA->CTRL = 0xC0DE0000U; + CLOCK_DisableClock(kCLOCK_Smartdma); +} + +/*! + * brief Reset the SMARTDMA. + */ +void SMARTDMA_Reset(void) +{ + RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); + SMARTDMA->CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); +} + +/*! + * brief SMARTDMA IRQ. + */ +void SMARTDMA_HandleIRQ(void) +{ + if (NULL != s_smartdmaCallback) + { + s_smartdmaCallback(s_smartdmaCallbackParam); + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma.h new file mode 100644 index 0000000000..8741711c9c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma.h @@ -0,0 +1,136 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_H_ +#define FSL_SMARTDMA_H_ + +#include "fsl_common.h" + +#if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) +#include "fsl_smartdma_rt500.h" +#elif defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || \ + defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ + defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#include "fsl_smartdma_mcxn.h" +#else +#error "Device not supported" +#endif + +/*! + * @addtogroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMARTDMA driver version */ +#define FSL_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) +/*@}*/ + +/*! @brief Callback function prototype for the smartdma driver. */ +typedef void (*smartdma_callback_t)(void *param); + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Initialize the SMARTDMA. + * + * @param apiMemAddr The address firmware will be copied to. + * @param firmware The firmware to use. + * @param firmwareSizeByte Size of firmware. + * @deprecated Do not use this function. It has been superceded by + * @ref SMARTDMA_InitWithoutFirmware and @ref SMARTDMA_InstallFirmware. + */ +void SMARTDMA_Init(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte); + +/*! + * @brief Initialize the SMARTDMA. + * + * This function is similar with @ref SMARTDMA_Init, the difference is this function + * does not install the firmware, the firmware could be installed using + * @ref SMARTDMA_InstallFirmware. + */ +void SMARTDMA_InitWithoutFirmware(void); + +/*! + * @brief Install the firmware. + * + * @param apiMemAddr The address firmware will be copied to. + * @param firmware The firmware to use. + * @param firmwareSizeByte Size of firmware. + * @note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_InstallFirmware(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte); + +/*! + * @brief Install the complete callback function. + * + * @param callback The callback called when smartdma program finished. + * @param param Parameter for the callback. + * @note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_InstallCallback(smartdma_callback_t callback, void *param); + +/*! + * @brief Boot the SMARTDMA to run program. + * + * @param apiIndex Index of the API to call. + * @param pParam Pointer to the parameter allocated by caller. + * @param mask Value set to register SMARTDMA->ARM2EZH[0:1]. + * @note Only call this function when SMARTDMA is not busy. + * @note The memory *pParam shall not be freed before the SMARTDMA function finished. + */ +void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask); + +/*! + * @brief Copy SMARTDMA params and Boot to run program. + * + * This function is similar with @ref SMARTDMA_Boot, the only difference + * is, this function copies the *pParam to a local variable, upper layer + * can free the pParam's memory before the SMARTDMA execution finished, + * for example, upper layer can define the param as a local variable. + * + * @param apiIndex Index of the API to call. + * @param pParam Pointer to the parameter. + * @param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + * @note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_Boot1(uint32_t apiIndex, const smartdma_param_t *pParam, uint8_t mask); + +/*! + * @brief Deinitialize the SMARTDMA. + */ +void SMARTDMA_Deinit(void); + +/*! + * @brief Reset the SMARTDMA. + */ +void SMARTDMA_Reset(void); + +/*! + * @brief SMARTDMA IRQ. + */ +void SMARTDMA_HandleIRQ(void); + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* FSL_SMARTDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_mcxn.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_mcxn.c new file mode 100644 index 0000000000..456b0e95ee --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_mcxn.c @@ -0,0 +1,545 @@ +/* + * Copyright 2019-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +#if defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \ + defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ + defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN236_SERIES) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x24U, 0x00U, 0x00U, 0x04U, 0x18U, 0x01U, 0x00U, 0x04U, 0xC8U, 0x02U, 0x00U, 0x04U, 0xF0U, 0x01U, 0x00U, 0x04U, + 0x7CU, 0x03U, 0x00U, 0x04U, 0xACU, 0x08U, 0x00U, 0x04U, 0x10U, 0x0EU, 0x00U, 0x04U, 0x38U, 0x10U, 0x00U, 0x04U, + 0xC0U, 0x12U, 0x00U, 0x04U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x08U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x00U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x01U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x02U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x03U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x04U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x05U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x06U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x07U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xF2U, 0x01U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 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0x02U, 0xC0U, 0x45U, 0x06U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x02U, 0xC0U, 0x35U, 0x00U, + 0x02U, 0xC0U, 0x45U, 0x01U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x02U, 0x02U, 0xC0U, 0x35U, 0x03U, + 0x02U, 0xC0U, 0x45U, 0x04U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x05U, 0x02U, 0xC0U, 0x35U, 0x06U, + 0x02U, 0xC0U, 0x45U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x5AU, 0x2AU, 0x00U}; + +const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); + +const uint8_t s_smartdmaCameraFirmware[] = { + 0x21U, 0x00U, 0x00U, 0x04U, 0x01U, 0x01U, 0x00U, 0x04U, 0x01U, 0x03U, 0x00U, 0x04U, 0xE1U, 0x03U, 0x00U, 0x04, + 0x21U, 0x05U, 0x00U, 0x04U, 0x21U, 0x07U, 0x00U, 0x04U, 0x21U, 0x09U, 0x00U, 0x04U, 0x00U, 0x00U, 0x00U, 0x00, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x04U, 0xF4U, 0x0F, + 0x1CU, 0x36U, 0xD0U, 0x04U, 0x18U, 0x20U, 0x02U, 0xF2U, 0x18U, 0xECU, 0x02U, 0xC2U, 0xB3U, 0x00U, 0x00U, 0x04, + 0xCFU, 0x00U, 0x00U, 0x04U, 0x18U, 0x20U, 0x02U, 0xF2U, 0x10U, 0x40U, 0xE8U, 0x20U, 0x02U, 0xC4U, 0x08U, 0x01, + 0x08U, 0x76U, 0x87U, 0x02U, 0x18U, 0x20U, 0x02U, 0xF2U, 0x12U, 0x00U, 0x00U, 0x00U, 0x83U, 0x00U, 0x00U, 0x04, + 0x18U, 0xECU, 0x02U, 0xC0U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x01U, 0x8CU, 0x05U, 0x01, + 0x18U, 0x20U, 0x02U, 0xF2U, 0x14U, 0x11U, 0x00U, 0x00U, 0x83U, 0x00U, 0x00U, 0x04U, 0x18U, 0xCCU, 0x00U, 0x20, + 0x18U, 0xCCU, 0x00U, 0x21U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x18U, 0x20U, 0x02U, 0xF2, + 0x83U, 0x00U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBF, + 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBF, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00, + 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x08U, 0x14U, 0x00, + 0x00U, 0x14U, 0x04U, 0x00U, 0x1CU, 0x36U, 0xD0U, 0x04U, 0x0DU, 0x80U, 0xF7U, 0x0FU, 0x18U, 0xECU, 0x02U, 0xC2, + 0x87U, 0x01U, 0x00U, 0x04U, 0xA7U, 0x01U, 0x00U, 0x04U, 0x08U, 0x76U, 0xC7U, 0x01U, 0x02U, 0xC4U, 0x08U, 0x01, + 0x18U, 0x20U, 0x02U, 0xF2U, 0x18U, 0xECU, 0x02U, 0xC0U, 0x00U, 0x08U, 0x14U, 0x00U, 0x00U, 0x14U, 0x04U, 0x00, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x18U, 0x20U, 0x02U, 0xF2, + 0x67U, 0x01U, 0x00U, 0x04U, 0x18U, 0xCCU, 0x00U, 0x20U, 0x18U, 0xCCU, 0x00U, 0x21U, 0x00U, 0x14U, 0x04U, 0x00, + 0x0DU, 0x88U, 0xF4U, 0x1FU, 0x01U, 0x90U, 0x05U, 0x02U, 0x0EU, 0x82U, 0xF4U, 0x00U, 0x20U, 0x04U, 0x04U, 0x00, + 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xE4U, 0x01U, 0x20U, 0x04U, 0x14U, 0x00, + 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xD4U, 0x02, + 0x20U, 0x04U, 0x24U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xC4U, 0x03, + 0x20U, 0x04U, 0x34U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33, + 0x0EU, 0x82U, 0xB4U, 0x04U, 0x20U, 0x04U, 0x44U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33, + 0x0EU, 0x82U, 0xA4U, 0x05U, 0x20U, 0x04U, 0x54U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x94U, 0x06U, 0x20U, 0x04U, 0x64U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x84U, 0x07U, 0x20U, 0x04U, 0x74U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00, + 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x74U, 0x08U, 0x20U, 0x04U, 0x84U, 0x00, + 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x64U, 0x09U, 0x20U, 0x04U, 0x94U, 0x00, + 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x54U, 0x0A, + 0x20U, 0x04U, 0xA4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x44U, 0x0B, + 0x20U, 0x04U, 0xB4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33, + 0x0EU, 0x82U, 0x34U, 0x0CU, 0x20U, 0x04U, 0xC4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33, + 0x0EU, 0x82U, 0x24U, 0x0DU, 0x20U, 0x04U, 0xD4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x14U, 0x0EU, 0x20U, 0x04U, 0xE4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00, + 0x25U, 0x44U, 0x00U, 0x33U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x0EU, 0x82U, 0x04U, 0x0F, + 0x20U, 0x04U, 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0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2, + 0x0EU, 0x82U, 0x04U, 0x18U, 0x20U, 0x04U, 0xF4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03, + 0x25U, 0x44U, 0x00U, 0x33U, 0x38U, 0xECU, 0x02U, 0x21U, 0x38U, 0xECU, 0x02U, 0x22U, 0x06U, 0x88U, 0x14U, 0x00, + 0x18U, 0x20U, 0x02U, 0xF2U, 0x83U, 0x07U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBF, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x04U, 0xF4U, 0x0F, + 0x1CU, 0x36U, 0xD0U, 0x04U, 0x10U, 0x40U, 0xE8U, 0x20U, 0x18U, 0xECU, 0x02U, 0xC2U, 0xABU, 0x09U, 0x00U, 0x04, + 0xCBU, 0x09U, 0x00U, 0x04U, 0x08U, 0xBEU, 0x04U, 0x28U, 0x82U, 0xC4U, 0x08U, 0x01U, 0x08U, 0x76U, 0x47U, 0x02, + 0x98U, 0x20U, 0x02U, 0xF2U, 0x06U, 0x88U, 0x14U, 0x00U, 0x18U, 0xECU, 0x02U, 0xC0U, 0x18U, 0xECU, 0x02U, 0xC1, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x00U, 0x08U, 0x04U, 0x00U, 0x00U, 0x10U, 0x04U, 0x00U, 0x18U, 0x20U, 0x02U, 0xF2, + 0x05U, 0x44U, 0x00U, 0x33U, 0x83U, 0x09U, 0x00U, 0x04U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x06U, 0x10U, 0x15U, 0x00, + 0x08U, 0x3EU, 0x05U, 0x05U, 0xB8U, 0xECU, 0x02U, 0xC2U, 0x08U, 0x3EU, 0x05U, 0x23U, 0xB8U, 0xECU, 0x02U, 0x22, + 0x00U, 0x08U, 0x04U, 0x00U, 0x83U, 0x09U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0x00U, +}; + +const uint32_t s_smartdmaCameraFirmwareSize = sizeof(s_smartdmaCameraFirmware); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SMARTDMA_IRQHandler(void); +void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_HandleIRQ(); +} + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_mcxn.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_mcxn.h new file mode 100644 index 0000000000..50acc39831 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_mcxn.h @@ -0,0 +1,155 @@ +/* + * Copyright 2019-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_MCXN_H_ +#define FSL_SMARTDMA_MCXN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup smartdma_mcxn MCXN SMARTDMA Firmware + * @ingroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#define SMARTDMA_USE_FLEXIO_SHIFTER_DMA 1 +#endif + +/*! @brief The firmware used for display. */ +extern const uint8_t s_smartdmaDisplayFirmware[]; + +/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ +#define SMARTDMA_DISPLAY_MEM_ADDR 0x04000000U + +/*! @brief Size of s_smartdmaDisplayFirmware */ +#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) + +/*! @brief Size of s_smartdmaDisplayFirmware */ +extern const uint32_t s_smartdmaDisplayFirmwareSize; + +/*! @brief The firmware used for camera. */ +extern const uint8_t s_smartdmaCameraFirmware[]; + +/*! @brief The s_smartdmaCameraFirmware firmware memory address. */ +#define SMARTDMA_CAMERA_MEM_ADDR 0x04000000U + +/*! @brief Size of s_smartdmacameraFirmware */ +#define SMARTDMA_CAMERA_FIRMWARE_SIZE (s_smartdmaCameraFirmwareSize) + +/*! @brief Size of s_smartdmacameraFirmware */ +extern const uint32_t s_smartdmaCameraFirmwareSize; + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter + smartdma_rgb565_rgb888_param_t. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use + parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ +}; + +/*! + * @brief Parameter for FlexIO MCULCD + */ +typedef struct _smartdma_flexio_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_flexio_mculcd_param_t; + +/*! + * @brief Parameter for RGB565To888 + */ +typedef struct _smartdma_rgb565_rgb888_param +{ + uint32_t *inBuf; + uint32_t *outBuf; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_rgb565_rgb888_param_t; + +/*! + * @brief The API index when using s_smartdmaCameraFirmware + */ +enum _smartdma_camera_api +{ + kSMARTDMA_FlexIO_CameraWholeFrame = 0U, /*! Deprecated. Use kSMARTDMA_CameraWholeFrameQVGA instead. */ + kSMARTDMA_FlexIO_CameraDiv16Frame = 1U, /*! Deprecated. Use kSMARTDMA_CameraDiv16FrameQVGA instead. */ + /*! Save whole frame of QVGA(320x240) to buffer in each interrupt in RGB565 format. */ + kSMARTDMA_CameraWholeFrameQVGA = 0U, + /*! Save 1/16 frame of QVGA(320x240) to buffer in each interrupt in RGB565 format, + takes 16 interrupts to get the whole frame. */ + kSMARTDMA_CameraDiv16FrameQVGA = 1U, + /*! Save whole frame of 480x320 to buffer in each interrupt in RGB565 format. */ + kSMARTDMA_CameraWholeFrame480_320 = 2U, + /*! Save 1/4 frame of QVGA(320x240) to buffer in each interrupt in grayscale format, + takes 4 interrupts to get the whole frame. */ + kSMARTDMA_CameraDiv4FrameQVGAGrayScale = 3U, + /*! Save 1/16 frame of QVGA(320x240) to buffer in each interrupt in grayscale format, + takes 16 interrupts to get the whole frame. */ + kSMARTDMA_CameraDiv16FrameQVGAGrayScale = 4U, + /*! Save 1/16 frame of 384x384 to buffer in each interrupt in grayscale format, + takes 16 interrupts to get the whole frame. */ + kSMARTDMA_CameraDiv16Frame384_384 = 5U, + /*! Save whole frame of 320x480 to buffer in each interrupt in RGB565 format. */ + kSMARTDMA_CameraWholeFrame320_480 = 6U, +}; + +/*! + * @brief Parameter for camera + */ +typedef struct _smartdma_camera_param +{ + uint32_t *smartdma_stack; /*!< Stack used by SMARTDMA, shall be at least 64 bytes. */ + uint32_t *p_buffer; /*!< Buffer to store the received camera data. */ + uint32_t *p_stripe_index; /*!< Pointer to stripe index. Used when only partial frame is received per interrupt. */ + uint32_t *p_buffer_ping_pong; /*!< Buffer to store the 2nd stripe of camera data. Used when only partial frame is + received per interrupt. */ +} smartdma_camera_param_t; + +/*! + * @brief Parameter for all supported APIs. + */ +typedef union +{ + smartdma_flexio_mculcd_param_t flexioMcuLcdParam; /*!< Parameter for flexio MCULCD. */ + smartdma_rgb565_rgb888_param_t rgb565_rgb888Param; /*!< Parameter for RGB565_RGB888 convertion. */ + smartdma_camera_param_t cameraParam; /*!< Parameter for camera. */ +} smartdma_param_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_SMARTDMA_MCXN_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_prv.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_prv.h new file mode 100644 index 0000000000..f297aa0687 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_prv.h @@ -0,0 +1,6058 @@ +/* + * @brief IOH Architecture B mnemonics + * + * @note + * Copyright 2014, 2019, NXP + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef FSL_SMARTDMA_PRV_H_ +#define FSL_SMARTDMA_PRV_H_ + +#include "fsl_common.h" + +#define SMARTDMA_INPUT_SOURCE_0 0 +#define SMARTDMA_INPUT_SOURCE_1 1 +#define SMARTDMA_INPUT_SOURCE_2 2 +#define SMARTDMA_INPUT_SOURCE_3 3 +#define SMARTDMA_INPUT_SOURCE_4 4 +#define SMARTDMA_INPUT_SOURCE_5 5 +#define SMARTDMA_INPUT_SOURCE_6 6 +#define SMARTDMA_INPUT_SOURCE_7 7 + +#define BS0(c) (c << 8) +#define BS1(c) (c << 11) +#define BS2(c) (c << 14) +#define BS3(c) (c << 17) +#define BS4(c) (c << 20) +#define BS5(c) (c << 23) +#define BS6(c) (c << 26) +#define BS7(c) (c << 29) + +#define SMARTDMA_DISABLE_EMERGENCY_BIT 8 + +#define SMARTDMA_HANDSHAKE_EVENT 0 +#define SMARTDMA_HANDSHAKE_ENABLE 1 + +#define SMARTDMA_MASK_RESP 2 +#define SMARTDMA_ENABLE_AHBBUF 3 +#define SMARTDMA_ENABLE_GPISYNCH 4 + +typedef enum +{ + ezh_trap_low = 1, + ezh_trap_high = 0 +} trap_pol; + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* SMARTDMA ARCH B */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R4 0x04 +#define R5 0x05 +#define R6 0x06 +#define R7 0x07 +#define GPO 0x08 +#define GPD 0x09 +#define CFS 0x0a +#define CFM 0x0b +#define SP 0x0c +#define PC 0x0d +#define GPI 0x0e +#define RA 0x0f + +/* Conditional Flags */ +#define EU 0x0 +#define ZE 0x1 +#define NZ 0x2 +#define PO 0x3 +#define NE 0x4 +#define AZ 0x5 +#define ZB 0x6 +#define CA 0x7 +#define NC 0x8 +#define CZ 0x9 +#define SPO 0xa +#define SNE 0xb +#define NBS 0xc +#define NEX 0xd +#define BS 0xe +#define EX 0xf + +#define UNS 0xa +#define NZS 0xb + +#define VECT0 0x1 +#define VECT1 0x2 +#define VECT2 0x4 +#define VECT3 0x8 +#define VECT4 0x10 +#define VECT5 0x20 +#define VECT6 0x40 +#define VECT7 0x80 + +/* Bit Slice Mux cfg */ + +#define BS_1 0 +#define BS_RISE 1 +#define BS_FALL 2 +#define BS_CHANGE 3 +#define BS_SIG 4 +#define BS_SIGN 5 +#define BS_0 6 +#define BS_EVENT 7 + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Unconditional OpCodes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_GOSUB(a30) DCD 0x03 + a30 +#define E_NOP DCD 0x12 +#define E_INT_TRIGGER(x24) DCD 0x14 + (x24 << 8) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_GOTO */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* the pre-processor/linker will calculate it this way (<< relative not allowed) */ +#define E_GOTO(a21) \ + DCD 0x15 + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_GOTO_REG(raddr) DCD 0x15 + (raddr << 14) + +/* the pre-processor/linker will calculate it this way (<< relative not allowed) */ +#define E_GOTOL(a21) \ + DCD 0x15 + (1 << 10) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_GOTO_REGL(raddr) DCD 0x15 + (raddr << 14) + (1 << 10) + +#define E_COND_GOTO(cond, a21) \ + DCD 0x15 + (cond << 5) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_COND_GOTO_REG(cond, raddr) DCD 0x15 + (raddr << 14) + (cond << 5) + +/* the pre-processor/linker will calculate it this way (<< relative not allowed) */ +#define E_COND_GOTOL(cond, a21) \ + DCD 0x15 + (1 << 10) + (cond << 5) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_COND_GOTO_REGL(cond, raddr) DCD 0x15 + (raddr << 14) + (1 << 10) + (cond << 5) +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_MOV */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_MOV(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) +#define E_MOVS(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU << 5) +#define E_COND_MOV(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) +#define E_COND_MOVS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond << 5) + +/* Invert */ +#define E_MVN(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) + (1 << 31) +#define E_MVNS(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU << 5) + (1 << 31) +#define E_COND_MVN(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) + (1 << 31) +#define E_COND_MVNS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond << 5) + (1 << 31) + +/* Load Immediate */ +#define E_LOAD_IMM(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) +#define E_LOAD_IMMS(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) +#define E_COND_LOAD_IMM(cond, dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) +#define E_COND_LOAD_IMMS(cond, dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + +/* Load Shifted Immediate */ +#define E_LOAD_SIMM(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) +#define E_LOAD_SIMMS(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) +#define E_COND_LOAD_SIMM(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) +#define E_COND_LOAD_SIMMS(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + +/* Load Inverted Immediate */ +#define E_LOAD_IMMN(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + (1 << 31) +#define E_LOAD_IMMNS(dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + (1 << 31) +#define E_COND_LOAD_IMMN(cond, dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + (1 << 31) +#define E_COND_LOAD_IMMNS(cond, dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + (1 << 31) + +/* Load Shifted then inverted Immediate */ +#define E_LOAD_SIMMN(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) +#define E_LOAD_SIMMNS(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) +#define E_COND_LOAD_SIMMN(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) +#define E_COND_LOAD_SIMMNS(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_AHB_READ Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Ptr PostIncrement (0 means pre-inc) Rdata Dest */ +/* Pointer WData Source Offset UpdatePointer */ +/* SizeWord Signed Access Cond */ + +/* LDR (Load, Load Byte, LoadByteSigned) */ +#define E_LDR(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRB(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRBS(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (1 << 21) + \ + (EU << 5) + +/* Conditional LDR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_LDR(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRB(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRBS(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (1 << 21) + \ + (cond << 5) + +/* With Update Pointer */ +#define E_LDR_PRE(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRB_PRE(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRBS_PRE(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (EU << 5) +#define E_COND_LDR_PRE(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRB_PRE(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRBS_PRE(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (cond << 5) + +/* With Update Pointer (Post Increment pointer) */ +#define E_LDR_POST(dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRB_POST(dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRBS_POST(dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (EU << 5) +#define E_COND_LDR_POST(cond, dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRB_POST(cond, dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRBS_POST(cond, dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_AHB_WRITE Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Ptr PostIncrement (0 means pre-inc) Rdata Dest */ +/* Pointer WData Source offset8s UpdatePointer */ +/* SizeWord Signed Access Cond */ + +/* STR (Load, Load Byte, LoadByteSigned) */ +#define E_STR(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (1 << 18) + (0 << 11) + \ + (EU << 5) +#define E_STRB(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (0 << 18) + (0 << 11) + \ + (EU << 5) + +/* Conditional STR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_STR(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (1 << 18) + (0 << 11) + \ + (cond << 5) +#define E_COND_STRB(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (0 << 18) + (0 << 11) + \ + (cond << 5) + +/* With Update Pointer */ +#define E_STR_PRE(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (EU << 5) +#define E_STRB_PRE(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (EU << 5) +#define E_COND_STR_PRE(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (cond << 5) +#define E_COND_STRB_PRE(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (cond << 5) + +/* With Update Pointer (Post Increment pointer) */ +#define E_STR_POST(raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (EU << 5) +#define E_STRB_POST(raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (EU << 5) +#define E_COND_STR_POST(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (cond << 5) +#define E_COND_STRB_POST(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Stack Operations (built up from E_LDR and E_STR codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Ptr PostIncrement (0 means pre-inc) Rdata Dest */ +/* Pointer WData Source Offset UpdatePointer + */ +/* SizeWord Signed Access Cond */ + +#define E_PUSH(source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (1 << 18) + (0 << 11) + (EU << 5) +#define E_POP(dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (1 << 18) + (0 << 21) + (EU << 5) +#define E_PUSHB(source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (0 << 18) + (0 << 11) + (EU << 5) +#define E_POPB(dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (0 << 21) + (EU << 5) + +#define E_POPBS(dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (1 << 21) + (EU << 5) + +#define E_COND_PUSH(cond, source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (1 << 18) + (0 << 11) + (cond << 5) +#define E_COND_POP(cond, dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (1 << 18) + (0 << 21) + (cond << 5) +#define E_COND_PUSHB(cond, source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (0 << 18) + (0 << 11) + (cond << 5) +#define E_COND_POPB(cond, dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (0 << 21) + (cond << 5) + +#define E_COND_POPBS(cond, dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (1 << 21) + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_PER_READ Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Address Cond */ + +#define E_PER_READ(dest, addr20) DCD 0x4 + (dest << 10) + ((addr20 & 0x000ffffc) << 12) + (EU << 5) +#define E_COND_PER_READ(cond, dest, addr20) DCD 0x4 + (dest << 10) + ((addr20 & 0x000ffffc) << 12) + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_PER_WRITE Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Address Cond */ + +#define E_PER_WRITE(source, addr20) \ + DCD 0x5 + (source << 20) + ((addr20 & 0x000ff000) << 12) + ((addr20 & 0x00000ffc) << 8) + (EU << 5) +#define E_COND_PER_WRITE(cond, source, addr20) \ + DCD 0x5 + (source << 20) + ((addr20 & 0x000ff000) << 12) + ((addr20 & 0x00000ffc) << 8) + (cond << 5) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ADD Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Amount + */ +/* Shift/Rotate Left/Right Flip */ + +/* Add reg to reg */ +#define E_ADD(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ADDS(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_ADD(cond, dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ADDS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* Add reg to reg and invert result */ +#define E_ADDN(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ADDNS(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ADDN(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ADDNS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* Add imm12s to reg */ +#define E_ADD_IMM(dest, src1, imm12s) DCD 0x6 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_ADD_IMMS(dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADD_IMM(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADD_IMMS(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* Add imm12s to reg and invert result */ +#define E_ADDN_IMM(dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ADDN_IMMS(dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADDN_IMM(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADDN_IMMS(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* Add reg to reg with Post Shift Left */ +#define E_ADD_LSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADD_LSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADD_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADD_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg and invert result with Post Shift Left */ +#define E_ADDN_LSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ADDN_LSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg with Post Shift Right */ +#define E_ADD_LSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADD_LSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADD_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADD_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg and invert result with Post Shift Right */ +#define E_ADDN_LSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ADDN_LSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg with Post Arith Shift Right */ +#define E_ADD_ASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADD_ASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADD_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADD_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg and invert result with Post Arith Shift Right */ +#define E_ADDN_ASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ADDN_ASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg with Post ROR */ +#define E_ADD_ROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADD_RORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADD_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADD_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg and invert result with ROR */ +#define E_ADDN_ROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ADDN_RORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg with Flip */ +#define E_ADD_F(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_ADD_FS(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADD_F(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_ADD_FS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Flip */ +#define E_ADDN_F(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADDN_FS(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_F(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg with Post Shift Left */ +#define E_ADD_FLSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADD_FLSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADD_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADD_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Post Shift Left */ +#define E_ADDN_FLSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ADDN_FLSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg with Post Shift Right */ +#define E_ADD_FLSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADD_FLSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADD_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADD_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Post Shift Right */ +#define E_ADDN_FLSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ADDN_FLSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* Add reg to reg with Post Arith Shift Right */ +#define E_ADD_FASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADD_FASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADD_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADD_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Post Arith Shift Right */ +#define E_ADDN_FASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ADDN_FASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg with Post ROR */ +#define E_ADD_FROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADD_FRORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADD_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADD_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* Add reg to reg and invert result with ROR */ +#define E_ADDN_FROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ADDN_FRORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_SUB Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* sub reg from reg */ +#define E_SUB(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_SUBS(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_SUB(cond, dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_SUBS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* sub reg from reg and invert result */ +#define E_SUBN(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_SUBNS(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_SUBN(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_SUBNS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* sub imm12s from reg */ +#define E_SUB_IMM(dest, src1, imm12s) DCD 0x8 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_SUB_IMMS(dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SUB_IMM(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SUB_IMMS(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* sub imm12s from reg and invert result */ +#define E_SUBN_IMM(dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_SUBN_IMMS(dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SUBN_IMM(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SUBN_IMMS(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* SUB reg to reg with Post Shift Left */ +#define E_SUB_LSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SUB_LSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUB_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SUB_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with Post Shift Left */ +#define E_SUBN_LSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_SUBN_LSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg with Post Shift Right */ +#define E_SUB_LSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SUB_LSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUB_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SUB_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with Post Shift Right */ +#define E_SUBN_LSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_SUBN_LSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* SUB reg to reg with Post Arith Shift Right */ +#define E_SUB_ASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SUB_ASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUB_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SUB_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with Post Arith Shift Right */ +#define E_SUBN_ASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_SUBN_ASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg with Post ROR */ +#define E_SUB_ROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SUB_RORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUB_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SUB_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with ROR */ +#define E_SUBN_ROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_SUBN_RORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* Sub reg to reg with Flip */ +#define E_SUB_F(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_SUB_FS(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUB_F(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_SUB_FS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* Sub reg to reg and invert result with Flip */ +#define E_SUBN_F(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SUBN_FS(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_F(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg with Post Shift Left */ +#define E_SUB_FLSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SUB_FLSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUB_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUB_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with Post Shift Left */ +#define E_SUBN_FLSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_SUBN_FLSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg with Post Shift Right */ +#define E_SUB_FLSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SUB_FLSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUB_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SUB_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with Post Shift Right */ +#define E_SUBN_FLSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_SUBN_FLSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* SUB reg to reg with Post Arith Shift Right */ +#define E_SUB_FASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SUB_FASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUB_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUB_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with Post Arith Shift Right */ +#define E_SUBN_FASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_SUBN_FASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg with Post ROR */ +#define E_SUB_FROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SUB_FRORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUB_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SUB_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with ROR */ +#define E_SUBN_FROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_SUBN_FRORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ADC Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* carry add reg from reg */ +#define E_ADC(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ADCS(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_ADC(cond, dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ADCS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* carry add reg from reg and invert result */ +#define E_ADCN(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ADCNS(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ADCN(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ADCNS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* carry add imm12s from reg */ +#define E_ADC_IMM(dest, src1, imm12s) DCD 0x9 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_ADC_IMMS(dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADC_IMM(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADC_IMMS(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* carry add imm12s from reg and invert result */ +#define E_ADCN_IMM(dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ADCN_IMMS(dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADCN_IMM(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADCN_IMMS(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* ADC reg to reg with Post Shift Left */ +#define E_ADC_LSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADC_LSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADC_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADC_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with Post Shift Left */ +#define E_ADCN_LSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ADCN_LSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg with Post Shift Right */ +#define E_ADC_LSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADC_LSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADC_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADC_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with Post Shift Right */ +#define E_ADCN_LSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ADCN_LSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* ADC reg to reg with Post Arith Shift Right */ +#define E_ADC_ASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADC_ASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADC_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADC_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with Post Arith Shift Right */ +#define E_ADCN_ASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ADCN_ASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg with Post ROR */ +#define E_ADC_ROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADC_RORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADC_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADC_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with ROR */ +#define E_ADCN_ROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ADCN_RORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* adc reg to reg with Flip */ +#define E_ADC_F(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_ADC_FS(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADC_F(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_ADC_FS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Flip */ +#define E_ADCN_F(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADCN_FS(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_F(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg with Post Shift Left */ +#define E_ADC_FLSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADC_FLSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADC_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADC_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Post Shift Left */ +#define E_ADCN_FLSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ADCN_FLSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg with Post Shift Right */ +#define E_ADC_FLSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADC_FLSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADC_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADC_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Post Shift Right */ +#define E_ADCN_FLSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ADCN_FLSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* ADC reg to reg with Post Arith Shift Right */ +#define E_ADC_FASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADC_FASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADC_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADC_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Post Arith Shift Right */ +#define E_ADCN_FASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ADCN_FASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg with Post ROR */ +#define E_ADC_FROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADC_FRORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADC_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADC_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with ROR */ +#define E_ADCN_FROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ADCN_FRORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_SBC Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* carry sub reg from reg */ +#define E_SBC(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_SBCS(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_SBC(cond, dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_SBCS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* carry sub reg from reg and invert result */ +#define E_SBCN(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_SBCNS(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_SBCN(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_SBCNS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* carry sub imm12s from reg */ +#define E_SBC_IMM(dest, src1, imm12s) DCD 0xA + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_SBC_IMMS(dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SBC_IMM(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SBC_IMMS(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* carry sub imm12s from reg and invert result */ +#define E_SBCN_IMM(dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_SBCN_IMMS(dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SBCN_IMM(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SBCN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* SBC reg to reg with Post Shift Left */ +#define E_SBC_LSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SBC_LSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBC_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SBC_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with Post Shift Left */ +#define E_SBCN_LSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_SBCN_LSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg with Post Shift Right */ +#define E_SBC_LSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SBC_LSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBC_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SBC_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with Post Shift Right */ +#define E_SBCN_LSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_SBCN_LSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* SBC reg to reg with Post Arith Shift Right */ +#define E_SBC_ASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SBC_ASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBC_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SBC_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with Post Arith Shift Right */ +#define E_SBCN_ASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_SBCN_ASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg with Post ROR */ +#define E_SBC_ROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SBC_RORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBC_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SBC_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with ROR */ +#define E_SBCN_ROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_SBCN_RORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* SBC reg to reg with Flip */ +#define E_SBC_F(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_SBC_FS(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBC_F(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_SBC_FS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Flip */ +#define E_SBCN_F(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SBCN_FS(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_F(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg with Post Shift Left */ +#define E_SBC_FLSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SBC_FLSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBC_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBC_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Post Shift Left */ +#define E_SBCN_FLSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_SBCN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg with Post Shift Right */ +#define E_SBC_FLSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SBC_FLSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBC_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SBC_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Post Shift Right */ +#define E_SBCN_FLSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_SBCN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* SBC reg to reg with Post Arith Shift Right */ +#define E_SBC_FASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SBC_FASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBC_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBC_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Post Arith Shift Right */ +#define E_SBCN_FASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_SBCN_FASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg with Post ROR */ +#define E_SBC_FROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SBC_FRORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBC_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SBC_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with ROR */ +#define E_SBCN_FROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_SBCN_FRORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_OR Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* or reg with reg */ +#define E_OR(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ORS(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_OR(cond, dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ORS(cond, dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* or reg with reg and invert result */ +#define E_ORN(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ORNS(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ORN(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ORNS(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* or imm12s with reg */ +#define E_OR_IMM(dest, src1, imm12s) DCD 0xC + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_OR_IMMS(dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_OR_IMM(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_OR_IMMS(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* or imm12s with reg and invert result */ +#define E_ORN_IMM(dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ORN_IMMS(dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ORN_IMM(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ORN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* OR reg to reg with Post Shift Left */ +#define E_OR_LSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_OR_LSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_OR_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_OR_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg and invert result with Post Shift Left */ +#define E_ORN_LSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ORN_LSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg with Post Shift Right */ +#define E_OR_LSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_OR_LSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_OR_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_OR_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* OR reg to reg and invert result with Post Shift Right */ +#define E_ORN_LSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ORN_LSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* OR reg to reg with Post Arith Shift Right */ +#define E_OR_ASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_OR_ASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_OR_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_OR_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg and invert result with Post Arith Shift Right */ +#define E_ORN_ASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ORN_ASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg with Post ROR */ +#define E_OR_ROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_OR_RORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_OR_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_OR_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* OR reg to reg and invert result with ROR */ +#define E_ORN_ROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ORN_RORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +/* Flip Endianness and then shift5/Rotate */ + +/* OR reg to reg with Flip */ +#define E_OR_F(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_OR_FS(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_OR_F(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_OR_FS(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Flip */ +#define E_ORN_F(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ORN_FS(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_F(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ORN_FS(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg with Post Shift Left */ +#define E_OR_FLSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_OR_FLSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_OR_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_OR_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Post Shift Left */ +#define E_ORN_FLSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ORN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg with Post Shift Right */ +#define E_OR_FLSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_OR_FLSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_OR_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_OR_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Post Shift Right */ +#define E_ORN_FLSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ORN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* OR reg to reg with Post Arith Shift Right */ +#define E_OR_FASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_OR_FASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_OR_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_OR_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Post Arith Shift Right */ +#define E_ORN_FASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ORN_FASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg with Post ROR */ +#define E_OR_FROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_OR_FRORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_OR_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_OR_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* OR reg to reg and invert result with ROR */ +#define E_ORN_FROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ORN_FRORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_AND Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* AND reg with reg */ +#define E_AND(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ANDS(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_AND(cond, dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ANDS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* AND reg with reg and invert result */ +#define E_ANDN(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ANDNS(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ANDN(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ANDNS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* AND imm12s with reg */ +#define E_AND_IMM(dest, src1, imm12s) DCD 0xd + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_AND_IMMS(dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_AND_IMM(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_AND_IMMS(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* AND imm12s with reg and invert result */ +#define E_ANDN_IMM(dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ANDN_IMMS(dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ANDN_IMM(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ANDN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* AND reg to reg with Post Shift Left */ +#define E_AND_LSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_AND_LSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_AND_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_AND_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg and invert result with Post Shift Left */ +#define E_ANDN_LSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ANDN_LSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg with Post Shift Right */ +#define E_AND_LSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_AND_LSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_AND_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_AND_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* AND reg to reg and invert result with Post Shift Right */ +#define E_ANDN_LSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ANDN_LSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* AND reg to reg with Post Arith Shift Right */ +#define E_AND_ASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_AND_ASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_AND_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_AND_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg and invert result with Post Arith Shift Right */ +#define E_ANDN_ASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ANDN_ASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg with Post ROR */ +#define E_AND_ROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_AND_RORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_AND_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_AND_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* AND reg to reg and invert result with ROR */ +#define E_ANDN_ROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ANDN_RORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* AND reg to reg with Flip */ +#define E_AND_F(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_AND_FS(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_AND_F(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_AND_FS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Flip */ +#define E_ANDN_F(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ANDN_FS(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_F(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg with Post Shift Left */ +#define E_AND_FLSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_AND_FLSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_AND_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_AND_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Post Shift Left */ +#define E_ANDN_FLSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ANDN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg with Post Shift Right */ +#define E_AND_FLSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_AND_FLSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_AND_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_AND_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Post Shift Right */ +#define E_ANDN_FLSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ANDN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* AND reg to reg with Post Arith Shift Right */ +#define E_AND_FASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_AND_FASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_AND_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_AND_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Post Arith Shift Right */ +#define E_ANDN_FASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ANDN_FASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg with Post ROR */ +#define E_AND_FROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_AND_FRORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_AND_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_AND_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* AND reg to reg and invert result with ROR */ +#define E_ANDN_FROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ANDN_FRORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_XOR Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* XOR reg with reg */ +#define E_XOR(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_XORS(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_XOR(cond, dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_XORS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* XOR reg with reg XOR invert result */ +#define E_XORN(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_XORNS(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_XORN(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_XORNS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* XOR imm12s with reg */ +#define E_XOR_IMM(dest, src1, imm12s) DCD 0xe + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_XOR_IMMS(dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_XOR_IMM(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_XOR_IMMS(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* XOR imm12s with reg XOR invert result */ +#define E_XORN_IMM(dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_XORN_IMMS(dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_XORN_IMM(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_XORN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* XOR reg to reg with Post Shift Left */ +#define E_XOR_LSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_XOR_LSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XOR_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_XOR_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Left */ +#define E_XORN_LSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_XORN_LSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg with Post Shift Right */ +#define E_XOR_LSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_XOR_LSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XOR_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_XOR_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Right */ +#define E_XORN_LSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_XORN_LSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* XOR reg to reg with Post Arith Shift Right */ +#define E_XOR_ASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_XOR_ASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XOR_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_XOR_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with Post Arith Shift Right */ +#define E_XORN_ASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_XORN_ASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg with Post ROR */ +#define E_XOR_ROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_XOR_RORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XOR_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_XOR_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with ROR */ +#define E_XORN_ROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_XORN_RORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* XOR reg to reg with Flip */ +#define E_XOR_F(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_XOR_FS(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XOR_F(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_XOR_FS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* XOR reg to reg and invert result with Flip */ +#define E_XORN_F(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_XORN_FS(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_F(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XORN_FS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg with Post Shift Left */ +#define E_XOR_FLSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_XOR_FLSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XOR_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XOR_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Left */ +#define E_XORN_FLSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_XORN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg with Post Shift Right */ +#define E_XOR_FLSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_XOR_FLSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XOR_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_XOR_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Right */ +#define E_XORN_FLSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_XORN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* XOR reg to reg with Post Arith Shift Right */ +#define E_XOR_FASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_XOR_FASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XOR_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XOR_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with Post Arith Shift Right */ +#define E_XORN_FASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_XORN_FASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg with Post ROR */ +#define E_XOR_FROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_XOR_FRORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XOR_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_XOR_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with ROR */ +#define E_XORN_FROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_XORN_FRORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_Shift Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation */ +/* Left/Right Shift/Rotate */ + +/* Logical Shift */ +#define E_LSL(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_LSR(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_LSLS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_LSRS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_LSL_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_LSL_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_LSL_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_LSL_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_LSL_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_LSL_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_LSL_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_LSL_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_LSL_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_LSL_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_LSL_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_LSL_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_LSL_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_LSL_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/* Conditional */ +/* Logical Shift */ +#define E_COND_LSL(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_LSR(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_COND_LSLS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_LSRS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_COND_LSL_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_COND_LSL_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_COND_LSL_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_COND_LSL_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_COND_LSL_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_LSL_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_COND_LSL_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_LSL_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_COND_LSL_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_LSL_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_COND_LSL_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_LSL_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_COND_LSL_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_LSL_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ROTATE Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate */ + +/* Rotate */ +#define E_ROR(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_RORS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_ROR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_ROR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_ROR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_ROR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_ROR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_ROR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_ROR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_ROR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_ROR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_ROR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_ROR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_ROR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_ROR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_ROR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/* Conditional */ +/* Rotate */ +#define E_COND_ROR(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_COND_RORS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_COND_ROR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_COND_ROR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_COND_ROR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_COND_ROR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_COND_ROR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_COND_ROR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_COND_ROR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_COND_ROR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_COND_ROR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_COND_ROR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_COND_ROR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_COND_ROR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_COND_ROR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_COND_ROR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Arithmetical Shift Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate Arith/Shift */ + +/* Arith Shift Right */ +#define E_ASR(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag */ +#define E_ASRS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then AND */ +#define E_ASR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then AND */ +#define E_ASR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then OR */ +#define E_ASR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then OR */ +#define E_ASR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then XOR */ +#define E_ASR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then XOR */ +#define E_ASR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADD */ +#define E_ASR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADD */ +#define E_ASR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SUB */ +#define E_ASR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SUB */ +#define E_ASR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADC */ +#define E_ASR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADC */ +#define E_ASR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SBC */ +#define E_ASR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SBC */ +#define E_ASR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/* Conditional */ +/* Conditional Arith Shift */ +#define E_COND_ASR(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag */ +#define E_COND_ASRS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then AND */ +#define E_COND_ASR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_ASR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then OR */ +#define E_COND_ASR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_ASR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_ASR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_ASR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_ASR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_ASR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_ASR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_ASR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_ASR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_ASR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_ASR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_ASR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Flip Opcodes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Endian/bit + */ +/* ARITH Arith/Shift */ + +/* Flip Endian , ASR Right */ +#define E_FEND_ASR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag */ +#define E_FEND_ASRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , AND */ +#define E_FEND_ASR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then AND */ +#define E_FEND_ASR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , OR */ +#define E_FEND_ASR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then OR */ +#define E_FEND_ASR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , XOR */ +#define E_FEND_ASR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then XOR */ +#define E_FEND_ASR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , ADD */ +#define E_FEND_ASR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then ADD */ +#define E_FEND_ASR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , SUB */ +#define E_FEND_ASR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then SUB */ +#define E_FEND_ASR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , ADC */ +#define E_FEND_ASR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then ADC */ +#define E_FEND_ASR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , SBC */ +#define E_FEND_ASR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then SBC */ +#define E_FEND_ASR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) + +/* Conditional */ +/* Conditional Flip Endian , ASR */ +#define E_COND_FEND_ASR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag */ +#define E_COND_FEND_ASRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , AND */ +#define E_COND_FEND_ASR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then AND */ +#define E_COND_FEND_ASR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , OR */ +#define E_COND_FEND_ASR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then OR */ +#define E_COND_FEND_ASR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , XOR */ +#define E_COND_FEND_ASR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then XOR */ +#define E_COND_FEND_ASR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , ADD */ +#define E_COND_FEND_ASR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then ADD */ +#define E_COND_FEND_ASR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , SUB */ +#define E_COND_FEND_ASR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then SUB */ +#define E_COND_FEND_ASR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , ADC */ +#define E_COND_FEND_ASR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then ADC */ +#define E_COND_FEND_ASR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , SBC */ +#define E_COND_FEND_ASR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then SBC */ +#define E_COND_FEND_ASR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) + +/* Bitwise Flip ASR */ + +/* Flip Bitwise , ASR Right */ +#define E_FBIT_ASR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag */ +#define E_FBIT_ASRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , AND */ +#define E_FBIT_ASR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then AND */ +#define E_FBIT_ASR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , OR */ +#define E_FBIT_ASR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then OR */ +#define E_FBIT_ASR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , XOR */ +#define E_FBIT_ASR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then XOR */ +#define E_FBIT_ASR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , ADD */ +#define E_FBIT_ASR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then ADD */ +#define E_FBIT_ASR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , SUB */ +#define E_FBIT_ASR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then SUB */ +#define E_FBIT_ASR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , ADC */ +#define E_FBIT_ASR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then ADC */ +#define E_FBIT_ASR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , SBC */ +#define E_FBIT_ASR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then SBC */ +#define E_FBIT_ASR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) + +/* Conditional */ +/* Conditional Flip Bitwise , ASR */ +#define E_COND_FBIT_ASR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag */ +#define E_COND_FBIT_ASRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , AND */ +#define E_COND_FBIT_ASR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then AND */ +#define E_COND_FBIT_ASR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , OR */ +#define E_COND_FBIT_ASR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then OR */ +#define E_COND_FBIT_ASR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , XOR */ +#define E_COND_FBIT_ASR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then XOR */ +#define E_COND_FBIT_ASR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , ADD */ +#define E_COND_FBIT_ASR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then ADD */ +#define E_COND_FBIT_ASR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , SUB */ +#define E_COND_FBIT_ASR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then SUB */ +#define E_COND_FBIT_ASR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , ADC */ +#define E_COND_FBIT_ASR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then ADC */ +#define E_COND_FBIT_ASR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , SBC */ +#define E_COND_FBIT_ASR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then SBC */ +#define E_COND_FBIT_ASR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) + +/* Flip Endian , LSR Right */ +#define E_FEND_LSR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag */ +#define E_FEND_LSRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , AND */ +#define E_FEND_LSR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then AND */ +#define E_FEND_LSR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , OR */ +#define E_FEND_LSR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then OR */ +#define E_FEND_LSR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , XOR */ +#define E_FEND_LSR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then XOR */ +#define E_FEND_LSR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , ADD */ +#define E_FEND_LSR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then ADD */ +#define E_FEND_LSR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , SUB */ +#define E_FEND_LSR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then SUB */ +#define E_FEND_LSR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , ADC */ +#define E_FEND_LSR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then ADC */ +#define E_FEND_LSR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , SBC */ +#define E_FEND_LSR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then SBC */ +#define E_FEND_LSR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) + +/* Conditional */ +/* Conditional Flip Endian , LSR */ +#define E_COND_FEND_LSR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag */ +#define E_COND_FEND_LSRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , AND */ +#define E_COND_FEND_LSR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then AND */ +#define E_COND_FEND_LSR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , OR */ +#define E_COND_FEND_LSR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then OR */ +#define E_COND_FEND_LSR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , XOR */ +#define E_COND_FEND_LSR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then XOR */ +#define E_COND_FEND_LSR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , ADD */ +#define E_COND_FEND_LSR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then ADD */ +#define E_COND_FEND_LSR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , SUB */ +#define E_COND_FEND_LSR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then SUB */ +#define E_COND_FEND_LSR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , ADC */ +#define E_COND_FEND_LSR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then ADC */ +#define E_COND_FEND_LSR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , SBC */ +#define E_COND_FEND_LSR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then SBC */ +#define E_COND_FEND_LSR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) + +/* Bitwise Flip LSR */ + +/* Flip Bitwise , LSR Right */ +#define E_FBIT_LSR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag */ +#define E_FBIT_LSRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , AND */ +#define E_FBIT_LSR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then AND */ +#define E_FBIT_LSR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , OR */ +#define E_FBIT_LSR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then OR */ +#define E_FBIT_LSR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , XOR */ +#define E_FBIT_LSR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then XOR */ +#define E_FBIT_LSR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , ADD */ +#define E_FBIT_LSR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then ADD */ +#define E_FBIT_LSR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , SUB */ +#define E_FBIT_LSR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then SUB */ +#define E_FBIT_LSR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , ADC */ +#define E_FBIT_LSR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then ADC */ +#define E_FBIT_LSR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , SBC */ +#define E_FBIT_LSR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then SBC */ +#define E_FBIT_LSR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) + +/* Conditional */ +/* Conditional Flip Bitwise , LSR */ +#define E_COND_FBIT_LSR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag */ +#define E_COND_FBIT_LSRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , AND */ +#define E_COND_FBIT_LSR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then AND */ +#define E_COND_FBIT_LSR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , OR */ +#define E_COND_FBIT_LSR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then OR */ +#define E_COND_FBIT_LSR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , XOR */ +#define E_COND_FBIT_LSR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then XOR */ +#define E_COND_FBIT_LSR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , ADD */ +#define E_COND_FBIT_LSR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then ADD */ +#define E_COND_FBIT_LSR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , SUB */ +#define E_COND_FBIT_LSR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then SUB */ +#define E_COND_FBIT_LSR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , ADC */ +#define E_COND_FBIT_LSR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then ADC */ +#define E_COND_FBIT_LSR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , SBC */ +#define E_COND_FBIT_LSR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then SBC */ +#define E_COND_FBIT_LSR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ANDOR */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* opcode Dest Src1 src2 SFlag */ +/* Cond SRC3 */ + +/* ANDOR */ +#define E_ANDOR(dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (0 << 9) + (EU << 5) + (ror << 24) +#define E_ANDORS(dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (1 << 9) + (EU << 5) + (ror << 24) +#define E_COND_ANDOR(cond, dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (0 << 9) + (cond << 5) + (ror << 24) +#define E_COND_ANDORS(cond, dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (1 << 9) + (cond << 5) + (ror << 24) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_Shift byte reg Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Extra Operation Left/Right */ +/* Shift/Rotate Invert */ + +/* Logical Shift */ +#define E_RLSL(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_RLSR(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_RLSLS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_RLSRS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_RLSL_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_RLSL_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_RLSL_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_RLSL_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_RLSL_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_RLSL_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_RLSL_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_RLSL_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_RLSL_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_RLSL_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_RLSL_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_RLSL_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_RLSL_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_RLSL_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/* Conditional */ +/* Logical Shift */ +#define E_COND_RLSL(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_RLSR(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_COND_RLSLS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_RLSRS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_COND_RLSL_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_COND_RLSL_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_COND_RLSL_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_COND_RLSL_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_COND_RLSL_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_RLSL_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_COND_RLSL_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_RLSL_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_COND_RLSL_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_RLSL_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_COND_RLSL_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_RLSL_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_COND_RLSL_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_RLSL_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation */ +/* Left/Right Shift/Rotate POSTshift */ + +/* Logical Shift and then AND */ +#define E_AND_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_AND_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_AND_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_AND_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_OR_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_OR_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_OR_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_OR_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_XOR_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_XOR_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_XOR_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_XOR_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_ADD_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADD_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_ADD_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADD_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_SUB_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SUB_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_SUB_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SUB_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_ADC_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADC_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_ADC_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADC_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_SBC_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SBC_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_SBC_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SBC_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Conditional */ + +/* Logical Shift and then AND */ +#define E_COND_AND_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_AND_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_COND_AND_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_AND_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_COND_OR_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_OR_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_COND_OR_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_OR_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_COND_XOR_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_XOR_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_XOR_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_XOR_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_COND_ADD_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADD_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_ADD_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADD_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_COND_SUB_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SUB_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_SUB_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SUB_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_COND_ADC_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADC_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_ADC_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADC_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_COND_SBC_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SBC_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_SBC_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SBC_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_Shift byte reg with inversion */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* Logical Shift */ +#define E_RLSLN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSRN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag */ +#define E_RLSLNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSRNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then AND */ +#define E_RLSL_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then AND */ +#define E_RLSL_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then OR */ +#define E_RLSL_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then OR */ +#define E_RLSL_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then XOR */ +#define E_RLSL_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then XOR */ +#define E_RLSL_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADD */ +#define E_RLSL_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADD */ +#define E_RLSL_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SUB */ +#define E_RLSL_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SUB */ +#define E_RLSL_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADC */ +#define E_RLSL_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADC */ +#define E_RLSL_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SBC */ +#define E_RLSL_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SBC */ +#define E_RLSL_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Conditional */ +/* Logical Shift */ +#define E_COND_RLSLN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSRN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag */ +#define E_COND_RLSLNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSRNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then AND */ +#define E_COND_RLSL_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then AND */ +#define E_COND_RLSL_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then OR */ +#define E_COND_RLSL_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then OR */ +#define E_COND_RLSL_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then XOR */ +#define E_COND_RLSL_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_RLSL_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADD */ +#define E_COND_RLSL_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_RLSL_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SUB */ +#define E_COND_RLSL_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_RLSL_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADC */ +#define E_COND_RLSL_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_RLSL_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SBC */ +#define E_COND_RLSL_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_RLSL_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation */ +/* Left/Right Shift/Rotate Inv POSTshift */ + +/* Logical Shift and then AND */ +#define E_ANDN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ANDN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_ANDN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ANDN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_ORN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ORN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_ORN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ORN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_XORN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_XORN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_XORN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_XORN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_ADDN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADDN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_ADDN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADDN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_SUBN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SUBN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_SUBN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SUBN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_ADCN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADCN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_ADCN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADCN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_SBCN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SBCN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_SBCN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SBCN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Conditional */ + +/* Logical Shift and then AND */ +#define E_COND_ANDN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ANDN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_COND_ANDN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ANDN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_COND_ORN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ORN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_COND_ORN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ORN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_COND_XORN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_XORN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_XORN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_XORN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_COND_ADDN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADDN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_ADDN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADDN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_COND_SUBN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SUBN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_SUBN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SUBN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_COND_ADCN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADCN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_ADCN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADCN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_COND_SBCN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SBCN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_SBCN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SBCN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ROTATE by Reg Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate */ + +/* Rotate */ +#define E_RROR(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_RRORS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_RROR_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_RROR_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_RROR_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_RROR_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_RROR_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_RROR_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_RROR_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_RROR_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_RROR_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_RROR_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_RROR_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_RROR_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_RROR_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_RROR_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/* Conditional */ +/* Rotate */ +#define E_COND_RROR(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_COND_RRORS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_COND_RROR_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_COND_RROR_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_COND_RROR_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_COND_RROR_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_COND_RROR_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_COND_RROR_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_COND_RROR_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_COND_RROR_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_COND_RROR_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_COND_RROR_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_COND_RROR_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_COND_RROR_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_COND_RROR_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_COND_RROR_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_AND_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_AND_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then OR */ +#define E_OR_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_OR_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then XOR */ +#define E_XOR_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_XOR_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADD */ +#define E_ADD_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_ADD_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SUB */ +#define E_SUB_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_SUB_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADC */ +#define E_ADC_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_ADC_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SBC */ +#define E_SBC_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_SBC_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Conditional */ + +/* Rotate and then AND */ +#define E_COND_AND_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_COND_AND_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then OR */ +#define E_COND_OR_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_COND_OR_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then XOR */ +#define E_COND_XOR_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_COND_XOR_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADD */ +#define E_COND_ADD_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_COND_ADD_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SUB */ +#define E_COND_SUB_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_COND_SUB_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADC */ +#define E_COND_ADC_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_COND_ADC_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SBC */ +#define E_COND_SBC_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_COND_SBC_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ROTATE by Reg Codes and invert ALU result */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate */ + +/* Rotate */ +#define E_RRORN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag */ +#define E_RRORNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then AND */ +#define E_RROR_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then AND */ +#define E_RROR_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then OR */ +#define E_RROR_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then OR */ +#define E_RROR_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then XOR */ +#define E_RROR_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then XOR */ +#define E_RROR_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADD */ +#define E_RROR_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADD */ +#define E_RROR_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SUB */ +#define E_RROR_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SUB */ +#define E_RROR_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADC */ +#define E_RROR_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADC */ +#define E_RROR_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SBC */ +#define E_RROR_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SBC */ +#define E_RROR_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Conditional */ +/* Rotate */ +#define E_COND_RRORN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag */ +#define E_COND_RRORNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then AND */ +#define E_COND_RROR_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then AND */ +#define E_COND_RROR_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then OR */ +#define E_COND_RROR_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then OR */ +#define E_COND_RROR_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then XOR */ +#define E_COND_RROR_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then XOR */ +#define E_COND_RROR_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADD */ +#define E_COND_RROR_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADD */ +#define E_COND_RROR_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SUB */ +#define E_COND_RROR_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SUB */ +#define E_COND_RROR_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADC */ +#define E_COND_RROR_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADC */ +#define E_COND_RROR_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SBC */ +#define E_COND_RROR_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SBC */ +#define E_COND_RROR_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then AND */ +#define E_ANDN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_ANDN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then OR */ +#define E_ORN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_ORN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then XOR */ +#define E_XORN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_XORN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADD */ +#define E_ADDN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_ADDN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SUB */ +#define E_SUBN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_SUBN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADC */ +#define E_ADCN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_ADCN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SBC */ +#define E_SBCN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_SBCN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional */ + +/* Rotate and then AND */ +#define E_COND_ANDN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_COND_ANDN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then OR */ +#define E_COND_ORN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_COND_ORN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then XOR */ +#define E_COND_XORN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_COND_XORN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADD */ +#define E_COND_ADDN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_COND_ADDN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SUB */ +#define E_COND_SUBN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_COND_SUBN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADC */ +#define E_COND_ADCN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_COND_ADCN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SBC */ +#define E_COND_SBCN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_COND_SBCN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Arithmetical Shift Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate Arith/Shift */ + +/* Arith Shift Right */ +#define E_RASR(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag */ +#define E_RASRS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then AND */ +#define E_RASR_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then AND */ +#define E_RASR_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then OR */ +#define E_RASR_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then OR */ +#define E_RASR_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then XOR */ +#define E_RASR_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then XOR */ +#define E_RASR_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADD */ +#define E_RASR_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADD */ +#define E_RASR_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SUB */ +#define E_RASR_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SUB */ +#define E_RASR_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADC */ +#define E_RASR_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADC */ +#define E_RASR_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SBC */ +#define E_RASR_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SBC */ +#define E_RASR_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/* Conditional */ +/* Conditional Arith Shift */ +#define E_COND_RASR(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag */ +#define E_COND_RASRS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then AND */ +#define E_COND_RASR_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_RASR_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then OR */ +#define E_COND_RASR_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_RASR_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_RASR_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_RASR_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_RASR_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_RASR_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_RASR_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_RASR_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_RASR_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_RASR_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_RASR_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_RASR_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then AND */ +#define E_AND_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then AND */ +#define E_AND_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then OR */ +#define E_OR_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then OR */ +#define E_OR_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then XOR */ +#define E_XOR_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then XOR */ +#define E_XOR_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then ADD */ +#define E_ADD_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then ADD */ +#define E_ADD_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then SUB */ +#define E_SUB_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then SUB */ +#define E_SUB_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then ADC */ +#define E_ADC_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then ADC */ +#define E_ADC_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then SBC */ +#define E_SBC_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then SBC */ +#define E_SBC_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional */ + +/* Conditional Arith Shift and then AND */ +#define E_COND_AND_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_AND_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then OR */ +#define E_COND_OR_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_OR_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_XOR_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_XOR_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_ADD_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_ADD_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_SUB_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_SUB_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_ADC_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_ADC_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_SBC_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_SBC_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Arithmetical Shift Codes with invert ALU */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate pOSTShift */ + +/* Arith Shift Right */ +#define E_RASRN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag */ +#define E_RASRNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then AND */ +#define E_RASR_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then AND */ +#define E_RASR_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then OR */ +#define E_RASR_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then OR */ +#define E_RASR_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then XOR */ +#define E_RASR_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then XOR */ +#define E_RASR_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then ADD */ +#define E_RASR_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then ADD */ +#define E_RASR_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then SUB */ +#define E_RASR_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then SUB */ +#define E_RASR_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then ADC */ +#define E_RASR_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then ADC */ +#define E_RASR_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then SBC */ +#define E_RASR_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then SBC */ +#define E_RASR_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional */ +/* Conditional Arith Shift */ +#define E_COND_RASRN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag */ +#define E_COND_RASRNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then AND */ +#define E_COND_RASR_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_RASR_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then OR */ +#define E_COND_RASR_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_RASR_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_RASR_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_RASR_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_RASR_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_RASR_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_RASR_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_RASR_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_RASR_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_RASR_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_RASR_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_RASR_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then AND */ +#define E_ANDN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then AND */ +#define E_ANDN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then OR */ +#define E_ORN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then OR */ +#define E_ORN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then XOR */ +#define E_XORN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then XOR */ +#define E_XORN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then ADD */ +#define E_ADDN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then ADD */ +#define E_ADDN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then SUB */ +#define E_SUBN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then SUB */ +#define E_SUBN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then ADC */ +#define E_ADCN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then ADC */ +#define E_ADCN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then SBC */ +#define E_SBCN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then SBC */ +#define E_SBCN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional */ + +/* Conditional Arith Shift and then AND */ +#define E_COND_ANDN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_ANDN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then OR */ +#define E_COND_ORN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_ORN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_XORN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_XORN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_ADDN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_ADDN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_SUBN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_SUBN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_ADCN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_ADCN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_SBCN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_SBCN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Bit Manipulate */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* opcode Dest Src1 src2 SFlag */ +/* Cond Imm Extra Operation ShiftByByte + */ +/* Neg/Pos Mask */ + +/* Bit test by byte */ +#define E_BTST(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BCLR(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_BSET(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BTOG(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Bit test by byte with set flags */ +#define E_BTSTS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BCLRS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_BSETS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BTOGS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Conditional Bit test by byte */ +#define E_COND_BTST(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BCLR(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_COND_BSET(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BTOG(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Conditional Bit test by byte with set flags */ +#define E_COND_BTSTS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BCLRS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_COND_BSETS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BTOGS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Bit test by imm */ +#define E_BTST_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BCLR_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_BSET_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BTOG_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/* Bit test by imm with set flags */ +#define E_BTST_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BCLR_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_BSET_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BTOG_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/* Conditional Bit test by imm */ +#define E_COND_BTST_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BCLR_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_COND_BSET_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BTOG_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/* Conditional Bit test by imm with set flags */ +#define E_COND_BTST_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BCLR_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_COND_BSET_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BTOG_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Tight Loop */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_TIGHT_LOOP(rend, rcount) DCD 0x1A + (rend << 14) + (rcount << 20) +#define E_COND_TIGHT_LOOP(cond, rend, rcount) DCD 0x1A + (rend << 14) + (rcount << 20) + (cond << 5) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Boolean Detect */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Opcode Dest Vector/Single NoUpdateRA */ +/* LargeVectors Cond Table */ + +#define E_HOLD DCD 0x1C + (PC << 10) + (1 << 15) + (0 << 18) + (0 << 19) + (EU << 5) +#define E_COND_HOLD(cond) DCD 0x1C + (PC << 10) + (1 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + +/* Small Vector Versions */ +#define E_VECTORED_HOLD(table) DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD(cond, table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + (table << 20) +#define E_VECTORED_HOLD_NRA(table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD_NRA \ + (cond, table) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (cond << 5) + (table << 20) + +/* Large Vector Versions */ +#define E_VECTORED_HOLD_LV(table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD_LV(cond, table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (cond << 5) + (table << 20) +#define E_VECTORED_HOLD_LV_NRA(table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD_LV_NRA \ + (cond, table) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (cond << 5) + (table << 20) + +/*/ Accelarated Vectored_hold */ +/* Small Vector Versions */ +#define E_ACC_VECTORED_HOLD(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD(cond, table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_ACC_VECTORED_HOLD_NRA(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD_NRA \ + (cond, table, vectors) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (cond << 5) + \ + (table << 20) + (1 << 9) + (vectors << 24) + +/* Large Vector Versions */ +#define E_ACC_VECTORED_HOLD_LV(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD_LV(cond, table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (cond << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_ACC_VECTORED_HOLD_LV_NRA(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD_LV_NRA \ + (cond, table, vectors) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (cond << 5) + \ + (table << 20) + (1 << 9) + (vectors << 24) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Reg offset Read */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Rdata Dest Pointer WData Source */ +/* Offset SizeWord Signed Access Cond Write */ + +/* LDR (Load, Load Byte, LoadByteSigned) */ +#define E_LDR_REG(dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (1 << 18) + (0 << 21) + (EU << 5) +#define E_LDR_REGB(dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (0 << 21) + (EU << 5) +#define E_LDR_REGBS(dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (1 << 21) + (EU << 5) + +/* Conditional LDR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_LDR_REG(cond, dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (1 << 18) + (0 << 21) + (cond << 5) +#define E_COND_LDR_REGB(cond, dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (0 << 21) + (cond << 5) +#define E_COND_LDR_REGBS(cond, dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (1 << 21) + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Reg offset Write */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Rdata Dest Pointer WData Source */ +/* Offset SizeWord Signed Access Cond Write */ + +/* STR (Load, Load Byte, LoadByteSigned) */ +#define E_STR_REG(raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (1 << 18) + (0 << 11) + (EU << 5) + (1 << 30) +#define E_STR_REGB(raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (0 << 18) + (0 << 11) + (EU << 5) + (1 << 30) + +/* Conditional STR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_STR_REG(cond, raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (1 << 18) + (0 << 11) + (cond << 5) + (1 << 30) +#define E_COND_STR_REGB(cond, raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (0 << 18) + (0 << 11) + (cond << 5) + (1 << 30) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* GPO modify Byte */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_MODIFY_GPO_BYTE(andmask, ormask, xormask) DCD 0x1E + (andmask << 8) + (ormask << 16) + (xormask << 24) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* HeartBeat opcodes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_HEART_RYTHM_IMM(val16imm) DCD 0x32 + (val16imm << 16) +#define E_HEART_RYTHM(r16bit) DCD 0x32 + (r16bit << 14) + (1 << 9) +#define E_SYNCH_ALL_TO_BEAT(on1imm) DCD 0x52 + (on1imm << 31) +#define E_WAIT_FOR_BEAT DCD 0x72 + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_rt500.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_rt500.c new file mode 100644 index 0000000000..f8952e16e1 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_rt500.c @@ -0,0 +1,2518 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +#if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_AND_FLEXIO) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x60U, 0x00U, 0x10U, 0x24U, 0x40U, 0x01U, 0x10U, 0x24U, 0xC8U, 0x02U, 0x10U, 0x24U, + 0x04U, 0x02U, 0x10U, 0x24U, 0x68U, 0x03U, 0x10U, 0x24U, 0x98U, 0x08U, 0x10U, 0x24U, + 0xE8U, 0x0DU, 0x10U, 0x24U, 0xFCU, 0x0FU, 0x10U, 0x24U, 0x70U, 0x12U, 0x10U, 0x24U, + 0xE8U, 0x14U, 0x10U, 0x24U, 0xACU, 0x25U, 0x10U, 0x24U, 0x54U, 0x16U, 0x10U, 0x24U, + 0xCCU, 0x27U, 0x10U, 0x24U, 0x18U, 0x19U, 0x10U, 0x24U, 0x7CU, 0x2BU, 0x10U, 0x24U, + 0xE4U, 0x1BU, 0x10U, 0x24U, 0x54U, 0x1DU, 0x10U, 0x24U, 0x24U, 0x20U, 0x10U, 0x24U, + 0xDCU, 0x2EU, 0x10U, 0x24U, 0x68U, 0x33U, 0x10U, 0x24U, 0x70U, 0x38U, 0x10U, 0x24U, + 0x8CU, 0x3BU, 0x10U, 0x24U, 0xF8U, 0x22U, 0x10U, 0x24U, 0x44U, 0x3EU, 0x10U, 0x24U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x08U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x04U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x08U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 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0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x2AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x8AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xEAU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x4AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xAAU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x0AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x7BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x7BU, 0x20U, + 0x00U, 0x00U, 0xF4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x02U, 0x80U, 0x45U, 0x00U, 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, + 0x00U, 0x08U, 0x06U, 0x06U, 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x02U, 0x40U, 0x05U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x24U, 0x0FU, 0x02U, + 0x02U, 0xC0U, 0x45U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x4AU, 0x7CU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x1CU, 0xF4U, 0x0FU, 0x05U, 0x10U, 0x70U, 0x32U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x18U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x20U, 0x32U, 0x04U, 0x4CU, 0x20U, 0x32U, + 0x04U, 0x90U, 0x20U, 0x32U, 0x04U, 0xD4U, 0x20U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, + 0x04U, 0x1CU, 0x21U, 0x32U, 0x04U, 0x4CU, 0x21U, 0x32U, 0x04U, 0x90U, 0x21U, 0x32U, + 0x04U, 0xD4U, 0x21U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, 0x02U, 0x04U, 0x3CU, 0x01U, + 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x7DU, 0x20U +}; +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_FLEXIO_ONLY) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x28U, 0x00U, 0x10U, 0x24U, 0x08U, 0x01U, 0x10U, 0x24U, 0x90U, 0x02U, 0x10U, 0x24U, 0xCCU, 0x01U, 0x10U, 0x24U, + 0x30U, 0x03U, 0x10U, 0x24U, 0x80U, 0x08U, 0x10U, 0x24U, 0x94U, 0x0AU, 0x10U, 0x24U, 0x08U, 0x0DU, 0x10U, 0x24U, + 0x80U, 0x0FU, 0x10U, 0x24U, 0x34U, 0x12U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x08U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x04U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x08U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x10U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x14U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xD2U, 0x01U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0x07U, 0x07U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, + 0x01U, 0x14U, 0x1CU, 0xFFU, 0x11U, 0x08U, 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0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x10U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x14U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x14U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x18U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x1CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x1CU, 0xF4U, 0x0FU, 0x05U, 0x10U, 0x70U, 0x32U, + 0x10U, 0x04U, 0x18U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x20U, 0x32U, + 0x04U, 0x4CU, 0x20U, 0x32U, 0x04U, 0x90U, 0x20U, 0x32U, 0x04U, 0xD4U, 0x20U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x04U, 0x1CU, 0x21U, 0x32U, + 0x04U, 0x4CU, 0x21U, 0x32U, 0x04U, 0x90U, 0x21U, 0x32U, 0x04U, 0xD4U, 0x21U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x82U, 0x25U, 0x20U}; +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_ONLY) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x34U, 0x00U, 0x10U, 0x24U, 0x44U, 0x0EU, 0x10U, 0x24U, 0xA0U, 0x01U, 0x10U, 0x24U, + 0x64U, 0x10U, 0x10U, 0x24U, 0x64U, 0x04U, 0x10U, 0x24U, 0x14U, 0x14U, 0x10U, 0x24U, + 0x30U, 0x07U, 0x10U, 0x24U, 0xA0U, 0x08U, 0x10U, 0x24U, 0x70U, 0x0BU, 0x10U, 0x24U, + 0x74U, 0x17U, 0x10U, 0x24U, 0x00U, 0x1CU, 0x10U, 0x24U, 0x08U, 0x21U, 0x10U, 0x24U, + 0x24U, 0x24U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xCAU, 0x00U, 0x20U, + 0x15U, 0xF2U, 0x01U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xF2U, 0x00U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x10U, 0x4CU, 0x10U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, + 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0xF2U, 0x00U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x4AU, 0x01U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, + 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0xCAU, 0x00U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x03U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, + 0x10U, 0x18U, 0x68U, 0x02U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x1AU, 0x02U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x10U, 0xDCU, 0x40U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, 0x08U, 0x9AU, 0x15U, 0x00U, + 0x55U, 0x1AU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, + 0x35U, 0x62U, 0x02U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, 0x25U, 0x80U, 0x32U, 0x31U, + 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x06U, 0xDCU, 0x15U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x84U, 0x72U, 0x31U, + 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, 0x00U, 0x1CU, 0x14U, 0x00U, + 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, 0x08U, 0x46U, 0x20U, 0x00U, + 0xB5U, 0xF2U, 0x01U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x02U, 0x03U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x01U, 0x9CU, 0x05U, 0x03U, 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, + 0x35U, 0xA2U, 0x03U, 0x20U, 0x15U, 0x5AU, 0x06U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 0x60U, 0x08U, 0xC4U, 0x0FU, 0x80U, 0x48U, 0x00U, 0x00U, 0x95U, 0xC2U, 0x04U, 0x20U, + 0x00U, 0x24U, 0x54U, 0x01U, 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0xE5U, 0x03U, + 0x75U, 0xCAU, 0x03U, 0x20U, 0x01U, 0x10U, 0x1CU, 0x01U, 0x01U, 0x14U, 0x1CU, 0x01U, + 0x01U, 0x18U, 0x1CU, 0x01U, 0x11U, 0x1CU, 0x40U, 0x08U, 0x10U, 0xDCU, 0x70U, 0x48U, + 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x10U, 0x48U, 0x18U, 0x0DU, 0x8CU, 0xF5U, 0x0FU, + 0x10U, 0x0CU, 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0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x4AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xDAU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x3AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x5AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x9AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xFAU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x4CU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x5AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x4CU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xBAU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x4CU, 0x20U, 0x00U, 0x00U, 0xF4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x02U, 0x80U, 0x45U, 0x00U, + 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, 0x00U, 0x08U, 0x06U, 0x06U, + 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x02U, 0x40U, 0x05U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x24U, 0x0FU, 0x02U, 0x02U, 0xC0U, 0x45U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x4DU, 0x20U +}; +#endif +const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SDMA_IRQHandler(void); +void SDMA_IRQHandler(void) +{ + SMARTDMA_HandleIRQ(); +} + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_rt500.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_rt500.h new file mode 100644 index 0000000000..8e680bf51d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_smartdma_rt500.h @@ -0,0 +1,321 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_RT500_H_ +#define FSL_SMARTDMA_RT500_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup smartdma_rt500 RT500 SMARTDMA Firmware + * @ingroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SMARTDMA_DISPLAY_MIPI_AND_FLEXIO 0 +#define SMARTDMA_DISPLAY_MIPI_ONLY 1 +#define SMARTDMA_DISPLAY_FLEXIO_ONLY 2 + +/* Select firmware for MIPI and FLEXIO by default. */ +#ifndef SMARTDMA_DISPLAY_FIRMWARE_SELECT +#define SMARTDMA_DISPLAY_FIRMWARE_SELECT SMARTDMA_DISPLAY_MIPI_AND_FLEXIO +#endif + +/*! @brief The firmware used for display. */ +extern const uint8_t s_smartdmaDisplayFirmware[]; + +/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ +#define SMARTDMA_DISPLAY_MEM_ADDR 0x24100000U + +/*! @brief Size of s_smartdmaDisplayFirmware */ +#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) + +/*! @brief Size of s_smartdmaDisplayFirmware */ +extern const uint32_t s_smartdmaDisplayFirmwareSize; + +#if (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_AND_FLEXIO) +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter + smartdma_rgb565_rgb888_param_t. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to + FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ + kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter + smartdma_dsi_2d_param_t. */ + kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter + smartdma_dsi_param_t */ + kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, + use parameter smartdma_dsi_checkerboard_param_t. */ + kSMARTDMA_MIPI_Enter_ULPS, /*!< Set MIPI-DSI to enter ultra low power state. */ + kSMARTDMA_MIPI_Exit_ULPS, /*!< Set MIPI-DSI to exit ultra low power state. */ + kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ + kSMARTDMA_FlexIO_FIFO2RAM, /*!< Read data from FlexIO FIFO to ram space. */ +}; + +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_ONLY) + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ + kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter + smartdma_dsi_2d_param_t. */ + kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter + smartdma_dsi_param_t */ + kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, + use parameter smartdma_dsi_checkerboard_param_t. */ + kSMARTDMA_MIPI_Enter_ULPS, /*!< Set MIPI-DSI to enter ultra low power state. */ + kSMARTDMA_MIPI_Exit_ULPS, /*!< Set MIPI-DSI to exit ultra low power state. */ +}; + +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_FLEXIO_ONLY) + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use + parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ + kSMARTDMA_FlexIO_FIFO2RAM, /*!< Read data from FlexIO FIFO to ram space. */ +}; +#endif + +/*! + * @brief Parameter for FlexIO MCULCD except kSMARTDMA_FlexIO_DMA_ONELANE + */ +typedef struct _smartdma_flexio_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_flexio_mculcd_param_t; + +/*! + * @brief Parameter for kSMARTDMA_FlexIO_DMA_ONELANE + */ +typedef struct _smartdma_flexio_onelane_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t offset; + uint32_t *smartdma_stack; +} smartdma_flexio_onelane_mculcd_param_t; + +/*! + * @brief Parameter for MIPI DSI + */ +typedef struct _smartdma_dsi_param +{ + /*! Pointer to the buffer to send. */ + const uint8_t *p_buffer; + /*! Buffer size in byte. */ + uint32_t buffersize; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * format is RGB565: + * LSB MSB + * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_param_t; + +/*! + * @brief Parameter for kSMARTDMA_MIPI_RGB565_DMA2D, kSMARTDMA_MIPI_RGB888_DMA2D + * and kSMARTDMA_MIPI_XRGB2RGB_DMA2D. + */ +typedef struct _smartdma_dsi_2d_param +{ + /*! Pointer to the buffer to send. */ + const uint8_t *p_buffer; + /*! SRC data transfer in a minor loop */ + uint32_t minorLoop; + /*! SRC data offset added after a minor loop */ + uint32_t minorLoopOffset; + /*! SRC data transfer in a major loop */ + uint32_t majorLoop; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * format is RGB565: + * LSB MSB + * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_2d_param_t; + +/*! + * @brief Parameter for kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA + */ +typedef struct _smartdma_dsi_checkerboard_param +{ + /*! Pointer to the buffer to send, pixel format is ARGB8888. */ + const uint8_t *p_buffer; + uint32_t height; /*! Height resolution in pixel. */ + uint32_t width; /*! Width resolution in pixel. */ + /*! Cube block type. + * cbType=1 : 1/2 pixel mask cases + * cbType=2 : 1/4 pixel mask cases + */ + uint32_t cbType; + /*! which pixel is turned off in each type + * cbType=2: indexOff= 1,2,3,4 + * cbType=1: indexOff= 0,1 + */ + uint32_t indexOff; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * for example + * format is RGB888: + * LSB MSB + * B0 B1 B2 B3 B4 B5 B6 B7 | G0 G1 G2 G3 G4 G5 G6 G7 | R0 R1 R2 R3 R4 R5 R6 R7 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * R0 R1 R2 R3 R4 R5 R6 R7 | G0 G1 G2 G3 G4 G5 G6 G7 | B0 B1 B2 B3 B4 B5 B6 B7 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_checkerboard_param_t; + +/*! + * @brief Parameter for RGB565To888 + */ +typedef struct _smartdma_rgb565_rgb888_param +{ + uint32_t *inBuf; + uint32_t *outBuf; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_rgb565_rgb888_param_t; + +/*! + * @brief Parameter for all supported APIs. + */ +typedef union +{ + /*! Parameter for flexio MCULCD. */ + smartdma_flexio_mculcd_param_t flexioMcuLcdParam; + /*! Parameter for flexio MCULCD with one shift buffer. */ + smartdma_flexio_onelane_mculcd_param_t flexioOneLineMcuLcdParam; + /*! Parameter for MIPI DSI functions. */ + smartdma_dsi_param_t dsiParam; + /*! Parameter for MIPI DSI 2D functions. */ + smartdma_dsi_2d_param_t dsi2DParam; + /*! Parameter for MIPI DSI checker board functions. */ + smartdma_dsi_checkerboard_param_t dsiCheckerBoardParam; + /*! Parameter for RGB565_RGB888 convertion. */ + smartdma_rgb565_rgb888_param_t rgb565_rgb888Param; +} smartdma_param_t; + +typedef struct +{ + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /* 0x20 */ + __IO uint32_t CTRL; /* 0x24 */ + __I uint32_t PC; /* 0x28 */ + __I uint32_t SP; /* 0x2C */ + __IO uint32_t BREAK_ADDR; /* 0x30 */ + __IO uint32_t BREAK_VECT; /* 0x34 */ + __IO uint32_t EMER_VECT; /* 0x38 */ + __IO uint32_t EMER_SEL; /* 0x3C */ + __IO uint32_t ARM2EZH; /* 0x40 */ + __IO uint32_t EZH2ARM; /* 0x44 */ + __IO uint32_t PENDTRAP; /* 0x48 */ +} SMARTDMA_Type; + +#define SMARTDMA_BASE 0x40027000 +#define SMARTDMA ((volatile SMARTDMA_Type *)SMARTDMA_BASE) + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_SMARTDMA_RT500_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.c index db853aedb7..c6a9b29326 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.c @@ -1,5 +1,5 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -45,6 +45,8 @@ */ spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId) { + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + uint32_t val; val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT); @@ -99,6 +101,7 @@ void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_con base->LPREQ_CFG = reg; } +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /*! * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. * @@ -122,6 +125,7 @@ void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_d base->VDD_CORE_GLITCH_DETECT_SC = reg; } +#endif /*! * brief Set SRAM operate voltage. @@ -154,8 +158,15 @@ void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t * /*! * brief Configs Bandgap mode in Active mode. * - * note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to - * disable Bandgap in active mode + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configrue LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. * * param base SPC peripheral base address. * param mode The Bandgap mode be selected. @@ -181,18 +192,28 @@ status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t m } /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == - SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength) || - (base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) { return kStatus_SPC_BandgapModeWrong; } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) { return kStatus_SPC_BandgapModeWrong; } +#endif #if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) == SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) @@ -213,13 +234,19 @@ status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t m /*! * brief Configs Bandgap mode in Low Power mode. * - * This function configs Bandgap mode in Low Power mode. - * IF user wants to disable Bandgap while keeping any of the Regulator in Normal Driver Strength - * or if any of the High voltage detectors/Low voltage detectors are kept enabled, the Bandgap mode - * will be set as Bandgap Enabled with Buffer Disabled. + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. * * param base SPC peripheral base address. * param mode The Bandgap mode be selected. + * * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. * retval kStatus_Success Config Bandgap mode in Low Power power mode successful. */ @@ -240,21 +267,33 @@ status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t return kStatus_SPC_BandgapModeWrong; } - /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ - if (((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) || - ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == - SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) || - ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == - SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength))) +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == + SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) { return kStatus_SPC_BandgapModeWrong; } +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) { return kStatus_SPC_BandgapModeWrong; } +#endif } reg &= ~SPC_LP_CFG_BGMODE_MASK; @@ -281,14 +320,17 @@ void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detec uint32_t reg = 0UL; +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U); - reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U); base->VD_CORE_CFG = reg; } +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) /*! * brief Enables the Core High Voltage Detector in Active mode. * @@ -318,35 +360,6 @@ status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable) return status; } -/*! - * brief Enables the Core Low Voltage Detector in Active mode. - * - * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled - * and the drive strength of each regulator must not set to low. - * - * param base SPC peripheral base address. - * param enable Enable/Disable Core LVD. - * true - Enable Core Low voltage detector in active mode. - * false - Disable Core Low voltage detector in active mode. - * - * retval kStatus_Success Enable Core Low Voltage Detect successfully. - */ -status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) -{ - status_t status = kStatus_Success; - - if (enable) - { - base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; - } - else - { - base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; - } - - return status; -} - /*! * brief Enables the Core High Voltage Detector in Low Power mode. * @@ -376,11 +389,41 @@ status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable return status; } +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! + * brief Enables the Core VDD Low Voltage Detector in Active mode. + * + * note If the Core VDD high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + + return status; +} /*! * brief Enables the Core Low Voltage Detector in Low Power mode. * - * note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * note If the Core VDD low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled * and the drive strength of each regulator must not set to low in Low Power mode. * * param base SPC peripheral base address. @@ -407,28 +450,34 @@ status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) } /*! - * @brief Set system VDD Low-voltage level selection. + * brief Set system VDD Low-voltage level selection. * * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level * must be done after disabling the System VDD low voltage reset and interrupt. - * - * @param base SPC peripheral base address. - * @param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * param base SPC peripheral base address. + * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. */ void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) { + (void)level; + (void)base; + + /* uint32_t reg; reg = base->VD_SYS_CFG; - /* Before changing voltage level, must disable low voltage detect interrupt and reset. */ + base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK); reg |= SPC_VD_SYS_CFG_LVSEL(level); - base->VD_SYS_CFG = reg; + base->VD_SYS_CFG = reg; */ } /*! - * brief Configs SYS voltage detect options. + * brief Configs SYS VDD voltage detect options. * * This function config SYS voltage detect options. * Note: Setting both the voltage detect interrupt and reset @@ -451,12 +500,12 @@ void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_d base->VD_SYS_CFG = reg; - /* Set trip voltage level. */ - SPC_SetSystemVDDLowVoltageLevel(base, config->level); + (void)(config->level); + /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */ } /*! - * brief Enables the System High Voltage Detector in Active mode. + * brief Enables the System VDD High Voltage Detector in Active mode. * * note If the System_LDO high voltage detect is enabled in Active mode, * please note that the bandgap must be enabled and the drive strength of @@ -486,7 +535,7 @@ status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable } /*! - * brief Enables the System Low Voltage Detector in Active mode. + * brief Enables the System VDD Low Voltage Detector in Active mode. * * note If the System_LDO low voltage detect is enabled in Active mode, * please note that the bandgap must be enabled and the drive strength of each @@ -516,7 +565,7 @@ status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable) } /*! - * brief Enables the System High Voltage Detector in Low Power mode. + * brief Enables the System VDD High Voltage Detector in Low Power mode. * * note If the System_LDO high voltage detect is enabled in low power mode, * please note that the bandgap must be enabled and the drive strength of each @@ -546,7 +595,7 @@ status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enab } /*! - * brief Enables the System Low Voltage Detector in Low Power mode. + * brief Enables the System VDD Low Voltage Detector in Low Power mode. * * note If the System_LDO low voltage detect is enabled in Low Power mode, * please note that the bandgap must be enabled and the drive strength of each @@ -575,6 +624,7 @@ status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enabl return status; } +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) /*! * brief Set IO VDD Low-Voltage level selection. * @@ -597,7 +647,7 @@ void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t } /*! - * brief Configs IO voltage detect options. + * brief Configs IO VDD voltage detect options. * * This function config IO voltage detect options. * Note: Setting both the voltage detect interrupt and reset @@ -628,7 +678,7 @@ void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_co } /*! - * brief Enables the IO High Voltage Detector in Active mode. + * brief Enables the IO VDD High Voltage Detector in Active mode. * * note If the IO high voltage detect is enabled in Active mode, * please note that the bandgap must be enabled and the drive strength @@ -658,7 +708,7 @@ status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable) } /*! - * brief Enables the IO Low Voltage Detector in Active mode. + * brief Enables the IO VDD Low Voltage Detector in Active mode. * * note If the IO low voltage detect is enabled in Active mode, * please note that the bandgap must be enabled and the drive strength @@ -688,7 +738,7 @@ status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable) } /*! - * brief Enables the IO High Voltage Detector in Low Power mode. + * brief Enables the IO VDD High Voltage Detector in Low Power mode. * * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled * and the drive strength of each regulator must not set to low in Low Power mode. @@ -717,7 +767,7 @@ status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable) } /*! - * brief Enables the IO Low Voltage Detector in Low Power mode. + * brief Enables the IO VDD Low Voltage Detector in Low Power mode. * * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled * and the drive strength of each regulator must not set to low in Low Power mode. @@ -744,6 +794,7 @@ status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable) return status; } +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ /*! * brief Configs external voltage domains @@ -763,70 +814,141 @@ void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask } /*! - * brief Configs Core LDO VDD Regulator in Active mode. + * brief Configs Core LDO Regulator in Active mode. * - * note If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. - * note Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. * * param base SPC peripheral base address. * param option Pointer to the spc_active_mode_Core_LDO_option_t structure. * * retval kStatus_Success Config Core LDO regulator in Active power mode successful. * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, core_ldo's drive strength can not - * set to low. - * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. */ status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option) { assert(option != NULL); -#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS - spc_core_ldo_voltage_level_t preVoltage; - uint32_t state; -#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ - if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { return kStatus_SPC_Busy; } + /* Check input parameters. */ + /* 1. Bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 2. To set to low drive strength, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + + if ((uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) != (uint8_t)(option->CoreLDOVoltage)) + { #if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS - if (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) - { - /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. - */ - state = SPC_GetActiveModeVoltageDetectStatus(base); - if (state != 0UL) - { - return kStatus_SPC_CORELDOLowDriveStrengthIgnore; - } - - /* Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal. */ - preVoltage = SPC_GetActiveModeCoreLDOVDDVoltageLevel(base); - if ((option->CoreLDOVoltage != kSPC_CoreLDO_MidDriveVoltage) && (preVoltage != option->CoreLDOVoltage)) - { - return kStatus_SPC_CORELDOVoltageSetFail; - } - - base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK; - } -#else - base->ACTIVE_CFG = ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | - SPC_ACTIVE_CFG_CORELDO_VDD_LVL(option->CoreLDOVoltage)); + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, kSPC_CoreLDO_NormalDriveStrength); #endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ - - /* - * $Branch Coverage Justification$ - * $ref spc_c_ref_1$. - */ - while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) - { + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); } +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + return kStatus_Success; } +/*! + * brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval kStatus_SPC_CORELDOVoltageSetFail Core LDO voltage level should only be + * changed when the CORE_LDO is in normal drive strength. + * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base)) + { +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + if (SPC_GetActiveModeCoreLDODriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength) + { + return kStatus_SPC_CORELDOVoltageSetFail; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + } + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + /*! * brief Configs CORE LDO Regulator in low power mode * @@ -841,15 +963,12 @@ status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_activ * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure. * retval kStatus_Success Config Core LDO regulator in power mode successfully. * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in low powermode is wrong. - * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. - * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. - * retval kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore HVDs/LVDs are not disabled before invoking this function. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. */ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option) { - spc_core_ldo_voltage_level_t preVoltage; - uint32_t state; + status_t status = kStatus_Success; if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { @@ -860,35 +979,48 @@ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_low return kStatus_SPC_Busy; } - if (option->CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) + status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + if (status == kStatus_Success) { - base->LP_CFG |= SPC_LP_CFG_CORELDO_VDD_DS_MASK; - base->LP_CFG = - ((base->LP_CFG & (~SPC_LP_CFG_CORELDO_VDD_LVL_MASK)) | SPC_LP_CFG_CORELDO_VDD_LVL(option->CoreLDOVoltage)); + (void)SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); } - else + + return status; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If Core LDO's drive strengths are same in active and low power mode, the Core LDO's voltage must be set to the + * same value in active and low power mode. Application should take care of this limitation. + * + * @note Some devices require Core LDO and DCDC have the same voltage level even if Core LDO is off. Application should + * take care of this limitation. + * + * param base SPC peripheral base address. + * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval #kStatus_SPC_Busy The SPC instance is busy to execute other operation. + * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { - state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); - /* If any HVD/LVDs are kept enabled write to set drive strength to low will be ignored. */ - if (state != 0UL) - { - return kStatus_SPC_CORELDOLowDriveStrengthIgnore; - } - - preVoltage = SPC_GetLowPowerCoreLDOVDDVoltageLevel(base); - /* Core LDO voltage level can only be changed when the Core LDO Drive Strength set to Normal */ - if ((option->CoreLDOVoltage >= kSPC_CoreLDO_MidDriveVoltage) && (preVoltage != option->CoreLDOVoltage)) - { - return kStatus_SPC_CORELDOVoltageSetFail; - } - - base->LP_CFG &= ~SPC_LP_CFG_CORELDO_VDD_DS_MASK; + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; } + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel)); + /* - * $Branch Coverage Justification$ - * $ref spc_c_ref_1$. - */ + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { } @@ -896,6 +1028,44 @@ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_low return kStatus_Success; } +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to + * low. + */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + else + { + /* To specify normal drive strength, the bandgap must be enabled in low power mode. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | SPC_LP_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) /*! * brief Configs System LDO VDD Regulator in Active mode. * @@ -913,8 +1083,8 @@ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_low * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure. * retval kStatus_Success Config System LDO regulator in Active power mode successful. * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. - * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive voltage. * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be * ignored. */ @@ -922,9 +1092,6 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act { assert(option != NULL); - uint32_t reg; - uint32_t state; - if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { /* @@ -934,47 +1101,98 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act return kStatus_SPC_Busy; } - if (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) + /* Check input parameters before setting registers. */ + /* 1. To set to low DS, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) { - /* When select System LDO voltage level to Over Drive voltage, The HVD of System LDO must be disabled. */ - if (((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) && - (option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage)) + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + /* 2. If specify normal drive strength, bandgap must not be disabled. */ + if ((SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) && + (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 3. Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) && + ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + + (void)SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + (void)SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel) +{ + if (voltageLevel == kSPC_SysLDO_OverDriveVoltage) + { + /* Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) { return kStatus_SPC_SYSLDOOverDriveVoltageFail; } } - else + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) { - state = (uint32_t)SPC_GetActiveModeVoltageDetectStatus(base); - - /* If any HVD/LVDs are kept enabled write to set drive strength to low will be ignored. */ - if (state != 0UL) - { - return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; - } - - /* If select voltage level as Over Drive Voltage, Drive Strength can not be set to low. */ - if (option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) { return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; } } - reg = base->ACTIVE_CFG; - reg &= ~(SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK); - reg |= SPC_ACTIVE_CFG_SYSLDO_VDD_DS(option->SysLDODriveStrength) | - SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(option->SysLDOVoltage); - - base->ACTIVE_CFG = reg; - - /* - * $Branch Coverage Justification$ - * $ref spc_c_ref_1$. - */ - while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + if (driveStrength == kSPC_SysLDO_NormalDriveStrength) { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } } + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength); + return kStatus_Success; } @@ -989,6 +1207,7 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act * * param base SPC peripheral base address. * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure. + * * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully. * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong. @@ -996,8 +1215,7 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act */ status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option) { - uint32_t reg; - uint32_t state; + status_t status; if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { @@ -1008,57 +1226,65 @@ status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_l return kStatus_SPC_Busy; } - if (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength) + status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + + return status; +} + +/*! + * brief Set System LDO Regulator drive strength in Low Power Mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) { - state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); - /* If any HVD/LVDs are kept enabled write to set drive strength to low will be ignored. */ - if (state != 0UL) + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) { return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; } } - - reg = base->LP_CFG; - reg &= ~(SPC_LP_CFG_SYSLDO_VDD_DS_MASK); - reg |= SPC_LP_CFG_SYSLDO_VDD_DS(option->SysLDODriveStrength); - - base->LP_CFG = reg; - - /* - * $Branch Coverage Justification$ - * $ref spc_c_ref_1$. - */ - while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + else { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } } + base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength); + return kStatus_Success; } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) /*! * brief Configs DCDC VDD Regulator in Active mode. * - * This function configs DCDC VDD Regulator in Active mode. - * If DCDDC VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed - * to a value that enable the bandgap. - * If any voltage detects are kept enabled, configuration to set DCDC VDD drive strength to low will - * be ignored. - * When switching DCDC from low drive strength to Normal driver strength, make sure the DCDC high VDD LVL - * setting to the same level that is set prior to switching the DCDC to low drive strength. + * note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. * * param base SPC peripheral base address. * param option Pointer to the spc_active_mode_DCDC_option_t structure. + * * retval kStatus_Success Config DCDC regulator in Active power mode successful. * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. - * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. */ status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option) { assert(option != NULL); - - uint32_t reg; - uint32_t state; + status_t status = kStatus_Success; if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { @@ -1069,22 +1295,13 @@ status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_m return kStatus_SPC_Busy; } - if (option->DCDCDriveStrength == kSPC_DCDC_LowDriveStrength) + status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + + if (status == kStatus_Success) { - state = (uint32_t)SPC_GetActiveModeVoltageDetectStatus(base); - /* If any HVD/LVDs are kept enabled write to set drive strength to low will be ignored. */ - if (state != 0UL) - { - return kStatus_SPC_DCDCLowDriveStrengthIgnore; - } + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); } - reg = base->ACTIVE_CFG; - reg &= ~(SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK); - reg |= SPC_ACTIVE_CFG_DCDC_VDD_DS(option->DCDCDriveStrength) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(option->DCDCVoltage); - - base->ACTIVE_CFG = reg; - /* * $Branch Coverage Justification$ * $ref spc_c_ref_1$. @@ -1093,32 +1310,53 @@ status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_m { } + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Active mode. + * + * note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength); + return kStatus_Success; } /*! * brief Configs DCDC VDD Regulator in Low power modes. * - * This function configs DCDC VDD Regulator in Low Power modes. * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed * to a value that enables the Bandgap. - * If any of voltage detectors are kept enabled, configuration to set DCDC VDD Drive Strength to Low or Pulse mode - * will be ignored. * In Deep Power Down mode, DCDC regulator is always turned off. * * param base SPC peripheral base address. * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure. + * * retval kStatus_Success Config DCDC regulator in low power mode successfully. * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. - * retval kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. - * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + * retval kStatus_SPC_BandgapModeWrong The bandgap should be enabled before invoking this function. */ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option) { - uint32_t reg; - uint32_t state; - if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) { /* @@ -1128,31 +1366,25 @@ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpow return kStatus_SPC_Busy; } - state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); - - if (state != 0UL) + /* Check input parameter before setting registers. */ + if ((option->DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) && + (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)) { - /* If any HVD/LVDs are kept enabled write to set DCDC regulator's drive strength to low/pluse refresh will be - * ignored. */ - if (option->DCDCDriveStrength == kSPC_DCDC_PulseRefreshMode) - { - return kStatus_SPC_DCDCPulseRefreshModeIgnore; - } - else if (option->DCDCDriveStrength == kSPC_DCDC_LowDriveStrength) - { - return kStatus_SPC_DCDCLowDriveStrengthIgnore; - } - else - { - /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ - } + return kStatus_SPC_BandgapModeWrong; } - reg = base->LP_CFG; - reg &= ~(SPC_LP_CFG_DCDC_VDD_LVL_MASK | SPC_LP_CFG_DCDC_VDD_DS_MASK); - reg |= SPC_LP_CFG_DCDC_VDD_LVL(option->DCDCVoltage) | SPC_LP_CFG_DCDC_VDD_DS(option->DCDCDriveStrength); + /* + 1. Configure to desired voltage level. + 2. Change to low drive strength. + 3. Configure same voltage level in active mode. + */ + SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); - base->LP_CFG = reg; + /* Change to desired drive strength. */ + if (option->DCDCDriveStrength != kSPC_DCDC_LowDriveStrength) + { + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + } /* * $Branch Coverage Justification$ @@ -1165,6 +1397,31 @@ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpow return kStatus_Success; } +/*! + * brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + /*! * brief Config DCDC Burst options * @@ -1174,44 +1431,28 @@ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpow void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) { assert(config != NULL); - uint32_t reg; - reg = base->DCDC_CFG; - reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK); - reg |= config->freq; + reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq); reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U); - base->DCDC_CFG = reg; - if (config->externalBurstRequest) + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + if ((config->sofwareBurstRequest) || (config->externalBurstRequest)) { - /* - * $Line Coverage Justification$ - * The following lines and branchs are not covered, because external request signal is required. - */ /* Clear DCDC burst acknowledge flag. */ base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; - base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK; - - while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0U) - { - } - - base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; } + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); if (config->sofwareBurstRequest) { - base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; - - while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0U) - { - } - - base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; } } @@ -1234,11 +1475,29 @@ void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count) base->DCDC_BURST_CFG = reg; } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ /*! - * brief Configs regulators in Active mode. + * brief Configs all settings of regulators in Active mode at a time. * - * This function provides the method to config all on-chip regulators in active mode. + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other low-level functions. * * param base SPC peripheral base address. * param config Pointer to spc_active_mode_regulators_config_t structure. @@ -1254,26 +1513,85 @@ status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode { assert(config != NULL); - status_t status; + uint32_t activeModeVDValue = SPC_GetActiveModeVoltageDetectStatus(base); - status = SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); - if (status == kStatus_Success) + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((activeModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckActiveModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) { - status = SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); - if (status == kStatus_Success) - { - status = SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); - if (status == kStatus_Success) - { - status = SPC_SetActiveModeBandgapModeConfig(base, config->bandgapMode); - if (status == kStatus_Success) - { - SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); - } - } - } + return kStatus_SPC_BandgapModeWrong; } - return status; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. Must disable system LDO high voltage detector before specifing SysLDO to overdrive voltage */ + if (((activeModeVDValue & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) && + (config->SysLDOOption.SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 3. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 4. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & ~(SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; } /*! @@ -1283,41 +1601,80 @@ status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode * * param base SPC peripheral base address. * param config Pointer to spc_lowpower_mode_regulators_config_t structure. - * retval kStatus_Success Config regulators in Low power mode successful. - * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. - * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. - * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. - * retval kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. - * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. - * retval kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. - * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + * retval #kStatus_Success Config regulators in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. */ status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config) { assert(config != NULL); + uint32_t lpModeVDValue = SPC_GetLowPowerModeVoltageDetectStatus(base); - status_t status = kStatus_Success; - - status = SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); - if (status == kStatus_Success) + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((lpModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) { - status = SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); - if (status == kStatus_Success) - { - status = SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); - if (status == kStatus_Success) - { - status = SPC_SetLowPowerModeBandgapmodeConfig(base, config->bandgapMode); - if (status == kStatus_Success) - { - SPC_EnableLowPowerModeCMPBandgapBufferMode(base, config->lpBuff); - SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); - SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); - } - } - } + return kStatus_SPC_BandgapModeWrong; } - return status; +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 3. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + base->LP_CFG = ((base->LP_CFG) & ~(SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableLowPowerModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.h index 8ce0719c66..52cb71c24d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_spc.h @@ -1,12 +1,12 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SPC_H_ -#define _FSL_SPC_H_ +#ifndef FSL_SPC_H_ +#define FSL_SPC_H_ #include "fsl_common.h" /*! @@ -18,6 +18,12 @@ * Definitions ******************************************************************************/ +/*! @name Driver version */ +/*! @{ */ +/*! @brief SPC driver version 2.4.2. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) +/*! @} */ + #define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL #define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL #define SPC_EVD_CFG_REG_EVDSTAT_SHIFT 16UL @@ -26,27 +32,43 @@ #define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT) #define SPC_EVD_CFG_REG_EVDSTAT(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT) -/*! @name Driver version */ -/*@{*/ -/*! @brief SPC driver version 2.0.0. */ -#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif /*! * @brief SPC status enumeration. + * + * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual + * to check. */ enum { kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any type of power mode transition. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be ignored for LVD/HVD enabled. */ kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive strength setting be ignored for LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive voltage failed for SYS LDO HVD must be disabled. */ kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U), /*!< SYS LDO Low driver strength - setting be ignored for LDO LVD/HVD enabled. */ + setting be ignored for LDO LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength setting be ignored for LDO LVD/HVD enabled. */ kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wrong. */ @@ -59,16 +81,22 @@ enum */ enum _spc_voltage_detect_flags { - kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ - kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ - kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ - kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ - kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ - kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ + kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ + kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ }; /*! * @brief SPC power domain isolation status. + * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to + * check. */ enum _spc_power_domains { @@ -85,10 +113,10 @@ enum _spc_analog_module_control kSPC_controlVref = 1UL << 0UL, /*!< Enable/disable VREF in active or low-power modes. */ kSPC_controlUsb3vDet = 1UL << 1UL, /*!< Enable/disable USB3V_Det in active or low-power modes. */ kSPC_controlDac0 = 1UL << 4UL, /*!< Enable/disable DAC0 in active or low-power modes. */ - kSPC_controlDac1 = 1UL << 5UL, /*!< Enablle/disable DAC1 in active or low-power modes. */ + kSPC_controlDac1 = 1UL << 5UL, /*!< Enable/disable DAC1 in active or low-power modes. */ kSPC_controlDac2 = 1UL << 6UL, /*!< Enable/disable DAC2 in active or low-power modes. */ kSPC_controlOpamp0 = 1UL << 8UL, /*!< Enable/disable OPAMP0 in active or low-power modes. */ - kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in actove or low-power modes. */ + kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in active or low-power modes. */ kSPC_controlOpamp2 = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */ kSPC_controlCmp0 = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */ kSPC_controlCmp1 = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */ @@ -148,32 +176,44 @@ typedef enum _spc_bandgap_mode kSPC_BandgapDisabled = 0x0U, /*!< Bandgap disabled. */ kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */ kSPC_BandgapEnabledBufferEnabled = 0x2U, /*!< Bandgap enabled with Buffer enabled. */ - kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ + kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ } spc_bandgap_mode_t; +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) /*! * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode. + * + * @note #kSPC_DCDC_RetentionVoltage not supported for all power modes. */ typedef enum _spc_dcdc_voltage_level { - kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC VDD Regulator regulate to Mid Voltage(1.0V). */ - kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC VDD Regulator regulate to Normal Voltage(1.1V). */ - kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC VDD Regulator regulate to Safe-Mode Voltage(1.2V). */ + kSPC_DCDC_RetentionVoltage = 0x0U, /*!< DCDC_CORE Regulator regulate to retention + Voltage(Only supportedin low power modes) */ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC_CORE Regulator regulate to Mid Voltage(1.0V). */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC_CORE Regulator regulate to Normal Voltage(1.1V). */ + kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V). */ } spc_dcdc_voltage_level_t; /*! * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode. + * + * @note Different drive strength differ in these DCDC characterstics: + * Maximum load current + * Quiescent current + * Transient response. */ typedef enum _spc_dcdc_drive_strength { - kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC VDD Regulator Drive Strength set to Pulse Refresh Mode, + kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode, * This enum member is only useful for Low Power Mode config, please * note that pluse refresh mode is invalid in SLEEP mode. */ - kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC VDD regulator Drive Strength set to low. */ - kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC VDD regulator Drive Strength set to Normal. */ + kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC_CORE regulator Drive Strength set to low. */ + kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC_CORE regulator Drive Strength set to Normal. */ } spc_dcdc_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) /*! * @brief SYS LDO regulator voltage level enumeration in Active mode. */ @@ -191,17 +231,21 @@ typedef enum _spc_sys_ldo_drive_strength kSPC_SysLDO_LowDriveStrength = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */ kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */ } spc_sys_ldo_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ /*! * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode. */ typedef enum _spc_core_ldo_voltage_level { - kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to Under Drive Voltage, please note that - underDrive voltage only useful in low power modes. */ - kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ - kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ - kSPC_CoreLDO_SafeModeVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to Safe-Mode Voltages. */ + kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< @deprecated, to align with description of latest RM, please use + #kSPC_Core_LDO_RetentionVoltage as instead. */ + kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, please note that + only useful in low power modes and not all devices support this options + please refer to devices' RM for details. */ + kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ + kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ + kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. */ } spc_core_ldo_voltage_level_t; /*! @@ -214,14 +258,18 @@ typedef enum _spc_core_ldo_drive_strength } spc_core_ldo_drive_strength_t; /*! - * @brief System/IO VDD Low-Voltage Level Select. + * @brief IO VDD Low-Voltage Level Select. */ typedef enum _spc_low_voltage_level_select { - kSPC_LowVoltageNormalLevel = 0x0U, /*!< Trip point set to Normal level. */ - kSPC_LowVoltageSafeLevel = 0x1U, /*!< Trip point set to Safe level. */ + kSPC_LowVoltageNormalLevel = 0x0U, /*!< @deprecated, please use kSPC_LowVoltageHighRange as instead. */ + kSPC_LowVoltageSafeLevel = 0x1U, /*!< @deprecated, please use kSPC_LowVoltageLowRange as instead. */ + + kSPC_LowVoltageHighRange = 0x0U, /*!< High range LVD threshold. */ + kSPC_LowVoltageLowRange = 0x1U, /*!< Low range LVD threshold. */ } spc_low_voltage_level_select_t; +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /*! * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. */ @@ -236,6 +284,7 @@ typedef enum _spc_vdd_core_glitch_ripple_counter_select kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter to detect glitch on VDD Core. */ } spc_vdd_core_glitch_ripple_counter_select_t; +#endif /*! * @brief The list of the operating voltage for the SRAM's read/write timing margin. @@ -247,6 +296,7 @@ typedef enum _spc_sram_operate_voltage kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */ } spc_sram_operate_voltage_t; +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /*! * @brief The configuration of VDD Core glitch detector. */ @@ -258,6 +308,7 @@ typedef struct _spc_vdd_core_glitch_detector_config bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ } spc_vdd_core_glitch_detector_config_t; +#endif typedef struct _spc_sram_voltage_config { @@ -282,10 +333,13 @@ typedef struct _spc_lowpower_request_config typedef struct _spc_active_mode_core_ldo_option { spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength selection in Active mode */ +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ } spc_active_mode_core_ldo_option_t; +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) /*! * @brief System LDO regulator options in Active mode. */ @@ -295,15 +349,18 @@ typedef struct _spc_active_mode_sys_ldo_option spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength selection in Active mode. */ } spc_active_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) /*! * @brief DCDC regulator options in Active mode. */ typedef struct _spc_active_mode_dcdc_option { spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Active mode. */ - spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC VDD Regulator Drive Strength selection in Active mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Active mode. */ } spc_active_mode_dcdc_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ /*! * @brief Core LDO regulator options in Low Power mode. @@ -315,6 +372,7 @@ typedef struct _spc_lowpower_mode_core_ldo_option selection in Low Power mode */ } spc_lowpower_mode_core_ldo_option_t; +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) /*! * @brief System LDO regulator options in Low Power mode. */ @@ -323,16 +381,31 @@ typedef struct _spc_lowpower_mode_sys_ldo_option spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength selection in Low Power mode. */ } spc_lowpower_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) /*! * @brief DCDC regulator options in Low Power mode. */ typedef struct _spc_lowpower_mode_dcdc_option { spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Low Power mode. */ - spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC VDD Regulator Drive Strength selection in Low Power mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Low Power mode. */ } spc_lowpower_mode_dcdc_option_t; +/*! + * @brief DCDC Burst configuration. + * @deprecated Do not recommend to use this structure. + */ +typedef struct _spc_dcdc_burst_config +{ + bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ + bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ + bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ + uint8_t freq; /*!< The frequency of the current burst. */ +} spc_dcdc_burst_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + /*! * @brief CORE/SYS/IO VDD Voltage Detect options. */ @@ -344,17 +417,6 @@ typedef struct _spc_voltage_detect_option bool LVDResetEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */ } spc_voltage_detect_option_t; -/*! - * @brief DCDC Burst configuration. - */ -typedef struct _spc_dcdc_burst_config -{ - bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ - bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ - bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ - uint8_t freq; /*!< The frequency of the current burst. */ -} spc_dcdc_burst_config_t; - /*! * @brief Core Voltage Detect configuration. */ @@ -369,9 +431,10 @@ typedef struct _spc_core_voltage_detect_config typedef struct _spc_system_voltage_detect_config { spc_voltage_detect_option_t option; /*!< System VDD Voltage Detect option. */ - spc_low_voltage_level_select_t level; /*!< System VDD low-voltage selection. */ + spc_low_voltage_level_select_t level; /*!< @deprecated, reserved for all devices, will removed in next release. */ } spc_system_voltage_detect_config_t; +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) /*! * @brief IO Voltage Detect Configuration. */ @@ -380,16 +443,27 @@ typedef struct _spc_io_voltage_detect_config spc_voltage_detect_option_t option; /*!< IO VDD Voltage Detect option. */ spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */ } spc_io_voltage_detect_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ /*! * @brief Active mode configuration. */ typedef struct _spc_active_mode_regulators_config { - spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ - bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ - spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) spc_active_mode_sys_ldo_option_t SysLDOOption; /*!< Specify System LDO configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */ } spc_active_mode_regulators_config_t; @@ -398,12 +472,25 @@ typedef struct _spc_active_mode_regulators_config */ typedef struct _spc_lowpower_mode_regulators_config { - bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ - spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ - bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ - bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ - spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ + bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) spc_lowpower_mode_sys_ldo_option_t SysLDOOption; /*!< Specify system LDO configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */ } spc_lowpower_mode_regulators_config_t; @@ -491,6 +578,21 @@ static inline void SPC_ClearLowPowerRequest(SPC_Type *base) base->SC |= SPC_SC_SPC_LP_REQ_MASK; } +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) +/*! + * @brief Checks whether the power switch is on. + * + * @param base SPC peripheral base address. + * + * @retval true The power switch is on. + * @retval false The power switch is off. + */ +static inline bool SPC_CheckSwitchState(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL); +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */ + /*! * @brief Gets selected power domain's requested low power mode. * @@ -512,6 +614,7 @@ spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, */ static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId) { + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) == SPC_PD_STATUS_PWR_REQ_STATUS_MASK); } @@ -524,10 +627,65 @@ static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power */ static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId) { + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK; } -/* @} */ +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) +/*! + * @name SRAM Retention LDO Control APIs + * @{ + */ + +/*! + * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V. + * + * @param base SPC peripheral base address. + * @param trimValue Reference voltage trim value. + */ +static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue) +{ + base->SRAMRETLDO_REFTRIM = + ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue)); +} + +/*! + * @brief Enables/disables SRAM retention LDO. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable SRAM LDO : + * - \b true Enable SRAM LDO; + * - \b false Disable SRAM LDO. + */ +static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable) +{ + if (enable) + { + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } + else + { + base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } +} + +/*! + * @brief + * + * @todo Need to check. + * + * @param base SPC peripheral base address. + * @param mask The OR'ed value of SRAM Array. + */ +static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask) +{ + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */ /*! * @name Low Power Request configuration @@ -543,8 +701,64 @@ static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_p */ void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config); -/* @} */ +/*! @} */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG) +/*! + * @name Integrated Power Switch Control APIs + * @{ + */ + +/*! + * @brief Enables/disables the integrated power switch manually. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable the integrated power switch: + * - \b true Enable the integrated power switch; + * - \b false Disable the integrated power switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } + else + { + base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } +} + +/*! + * @brief Enables/disables the integrated power switch automatically. + * + * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low + * power modes: + * @code + * SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true); + * @endcode + * + * @param base SPC peripheral base address. + * @param sleepGate Enable the integrated power switch when chip enter low power modes: + * - \b true SPC asserts an output pin at low-power entry to power-gate the switch; + * - \b false SPC does not assert an output pin at low-power entry to power-gate the switch. + * @param wakeupUngate Enables the switch after wake-up from low power modes: + * - \b true SPC asserts an output pin at low-power exit to power-ungate the switch; + * - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate) +{ + uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)); + + tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate); + + base->CFG = tmp32; +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /*! * @name VDD Core Glitch Detector Control APIs * @{ @@ -621,7 +835,8 @@ static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); } -/* @} */ +/*! @} */ +#endif /*! * @name SRAM Control APIs @@ -636,27 +851,13 @@ static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base */ void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config); -/* @} */ +/*! @} */ /*! - * @name Active Mode configuration. + * @name Active Mode configuration * @{ */ -/*! - * @brief Gets CORE LDO VDD Regulator Voltage level. - * - * This function returns the voltage level of CORE LDO Regulator in Active mode. - * - * @param base SPC peripheral base address. - * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. - */ -static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) -{ - return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> - SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); -} - /*! * @brief Gets the Bandgap mode in Active mode. * @@ -679,16 +880,33 @@ static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) { uint32_t state; state = base->ACTIVE_CFG & - (SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | SPC_ACTIVE_CFG_SYS_HVDE_MASK | - SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_HVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK); + ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_ACTIVE_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); return state; } /*! * @brief Configs Bandgap mode in Active mode. * - * @note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to - * disable Bandgap in active mode + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configrue LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. * * @param base SPC peripheral base address. * @param mode The Bandgap mode be selected. @@ -698,6 +916,7 @@ static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) */ status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) /*! * @brief Enables/Disable the CMP Bandgap Buffer in Active mode. * @@ -717,6 +936,7 @@ static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool ena base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK; } } +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ /*! * @brief Sets the delay when the regulators change voltage level in Active mode. @@ -730,22 +950,42 @@ static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t de } /*! - * @brief Configs regulators in Active mode. + * @brief Configs all settings of regulators in Active mode at a time. * - * This function provides the method to config all on-chip regulators in active mode. + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. * * @param base SPC peripheral base address. * @param config Pointer to spc_active_mode_regulators_config_t structure. + * * @retval #kStatus_Success Config regulators in Active power mode successful. - * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * @retval #kStatus_SPC_BandgapModeWrong Based on input setting, bandgap can not be disabled. * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. - * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. - * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. - * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage due to + * System VDD HVD is not disabled. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. */ status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config); +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /*! * @brief Disables/Enables VDD Core Glitch Detect in Active mode. * @@ -769,6 +1009,26 @@ static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool } } +/*! + * @brief Check if Glitch detect hardware is enabled in active mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckActiveModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} + +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ + /*! * @brief Enables analog modules in active mode. * @@ -805,37 +1065,13 @@ static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base) return base->ACTIVE_CFG1; } -/* @} */ +/*! @} */ /*! - * @name Low Power mode configuration. + * @name Low Power mode configuration * @{ */ -/*! - * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. - * - * @param base SPC peripheral base address. - * @return The CORE LDO's VDD Drive Strength. - */ -static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) -{ - return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> - SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); -} - -/*! - * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. - * - * @param base SPC peripheral base address. - * @return The CORE LDO VDD Regulator's voltage level. - */ -static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) -{ - return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> - SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); -} - /*! * @brief Gets the Bandgap mode in Low Power mode. * @@ -856,8 +1092,18 @@ static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base) static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base) { uint32_t state; - state = base->LP_CFG & (SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | SPC_LP_CFG_SYS_HVDE_MASK | - SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_HVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK); + state = base->LP_CFG & ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_LP_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); return state; } @@ -888,26 +1134,55 @@ static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enabl /*! * @brief Configs Bandgap mode in Low Power mode. * - * This function configs Bandgap mode in Low Power mode. - * IF user want to disable Bandgap while keeping any of the Regulator in Normal Driver Strength - * or if any of the High voltage detectors/Low voltage detectors are kept enabled, the Bandgap mode - * will be set as Bandgap Enabled with Buffer Disabled. + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. * - * @note This API shall be invoked following set HVDs/LVDs and regulators' driver strength. + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. * * @param base SPC peripheral base address. * @param mode The Bandgap mode be selected. + * * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful. */ status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) +/*! + * @brief Enables/disables SRAM_LDO deep power low power IREF. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable low power IREF : + * - \b true: Low Power IREF is enabled ; + * - \b false: Low Power IREF is disabled for power saving. + */ +static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) /*! * @brief Enables/Disables CMP Bandgap Buffer. * * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off * in Deep Power Down mode. * + * @deprecated No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead. + * * @param base SPC peripheral base address. * @param enable Enable/Disable CMP Bandgap buffer. * true - Enable Buffer Stored Reference Voltage to CMP. @@ -925,6 +1200,33 @@ static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bo } } +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) /*! * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes. * @@ -948,6 +1250,7 @@ static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK; } } +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ /*! * @brief Sets the delay when exit the low power modes. @@ -961,24 +1264,37 @@ static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay) } /*! - * @brief Configs regulators in Low Power mode. + * @brief Configs all settings of regulators in Low power mode at a time. * - * This function provides the method to config all on-chip regulators in Low Power mode. + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in low power mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. * * @param base SPC peripheral base address. * @param config Pointer to spc_lowpower_mode_regulators_config_t structure. * @retval #kStatus_Success Config regulators in Low power mode successful. - * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. - * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. - * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. - * @retval #kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. - * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. */ status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config); +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) /*! * @brief Disable/Enable VDD Core Glitch Detect in low power mode. * @@ -1002,6 +1318,25 @@ static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bo } } +/*! + * @brief Check if Glitch detect hardware is enabled in low power mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} +#endif + /*! * @brief Enables analog modules in low power modes. * @@ -1038,10 +1373,10 @@ static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) return base->LP_CFG1; } -/* @} */ +/*! @} */ /*! - * @name Voltage Detect Status. + * @name Voltage Detect Status * @{ */ /*! @@ -1066,7 +1401,7 @@ static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask base->VD_STAT |= mask; } -/* @} */ +/*! @} */ /*! * @name Voltage Detect configuration for Core voltage domain. @@ -1111,21 +1446,6 @@ static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base) base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK; } -/*! - * @brief Enables/Disables the Core High Voltage Detector in Active mode. - * - * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled - * and the drive strength of each regulator must not set to low. - * - * @param base SPC peripheral base address. - * @param enable Enable/Disable Core HVD. - * true - Enable Core High voltage detector in active mode. - * false - Disable Core High voltage detector in active mode. - * - * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. - */ -status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); - /*! * @brief Enables/Disables the Core Low Voltage Detector in Active mode. * @@ -1141,25 +1461,6 @@ status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); */ status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable); -/*! - * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. - * - * This function enables/disables the Core High Voltage Detector. - * If enabled the Core High Voltage detector. The Bandgap mode in - * low power mode must be programmed so that Bandgap is enabled. - * - * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled - * and the drive strength of each regulator must not set to low in low power mode. - * - * @param base SPC peripheral base address. - * @param enable Enable/Disable Core HVD. - * true - Enable Core High voltage detector in low power mode. - * false - Disable Core High voltage detector in low power mode. - * - * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. - */ -status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); - /*! * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode. * @@ -1179,10 +1480,46 @@ status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable */ status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable); -/* @} */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * @brief Enables/Disables the Core High Voltage Detector in Active mode. + * + * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); /*! - * @name Voltage detect configuration for System Voltage domain. + * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. + * + * This function enables/disables the Core High Voltage Detector. + * If enabled the Core High Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in low power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! @} */ + +/*! + * @name Voltage detect configuration for System Voltage domain * @{ */ /*! @@ -1191,6 +1528,8 @@ status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level * must be done after disabling the System VDD low voltage reset and interrupt. * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * * @param base SPC peripheral base address. * @param level System VDD Low-Voltage level selection. */ @@ -1298,10 +1637,11 @@ status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enab */ status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable); -/* @} */ +/*! @} */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) /*! - * @name Voltage detect configuration for IO voltage domain. + * @name Voltage detect configuration for IO voltage domain * @{ */ /*! @@ -1414,10 +1754,12 @@ status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable); */ status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable); -/* @} */ +/*! @} */ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ /*! - * @name External Voltage domains configuration. + * @name External Voltage domains configuration * @{ */ /*! @@ -1435,8 +1777,6 @@ void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask /*! * @brief Gets External Domains status. * - * This function configs external voltage domains status. - * * @param base SPC peripheral base address. * @return The status of each external domain. */ @@ -1445,12 +1785,14 @@ static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); } -/* @} */ +/*! @} */ /*! - * @name Set CORE LDO Regulator. + * @name Low Level APIs To Set CORE LDO Regulator * @{ */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) /*! * @brief Enable/Disable Core LDO regulator. * @@ -1476,7 +1818,10 @@ static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable) base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK; } } +#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && \ + FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) /*! * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down. * @@ -1498,25 +1843,85 @@ static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown) base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; } } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */ /*! - * @brief Configs Core LDO VDD Regulator in Active mode. + * @brief Configs Core LDO Regulator in Active mode. * - * @note If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. - * - * @note Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. * * @param base SPC peripheral base address. * @param option Pointer to the spc_active_mode_core_ldo_option_t structure. * - * @retval #kStatus_Success Config Core LDO regulator in Active power mode successful. - * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, core_ldo's drive strength can not - * set to low. - * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * @retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * @retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * @retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. */ status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option); +/*! + * @brief Set Core LDO Regulator Voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * @retval kStatus_SPC_CORELDOVoltageSetFail The drive strength of Core LDO is not normal. + * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets CORE LDO Regulator Voltage level. + * + * This function returns the voltage level of CORE LDO Regulator in Active mode. + * + * @param base SPC peripheral base address. + * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); +} + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT); +} +#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + /*! * @brief Configs CORE LDO Regulator in low power mode * @@ -1538,9 +1943,66 @@ status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_activ status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option); /*! - * @name Set System LDO Regulator. + * @brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * @param base SPC peripheral base address. + * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO VDD Regulator's voltage level. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO's VDD Drive Strength. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> + SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @name Low Level APIs To Set System LDO Regulator * @{ */ + /*! * @brief Enable/Disable System LDO regulator. * @@ -1590,26 +2052,81 @@ static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink) /*! * @brief Configs System LDO VDD Regulator in Active mode. * - * This function configs System LDO VDD Regulator in Active mode. - * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * @note If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed * to a value that enables the bandgap. - * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * @note If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will * be ignored. - * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. - * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. - * Otherwise it will be fail to regulator to Over Drive Voltage. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be + * disabled. Otherwise it will be fail to regulator to Over Drive Voltage. * * @param base SPC peripheral base address. * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure. * * @retval #kStatus_Success Config System LDO regulator in Active power mode successful. * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. - * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive + * voltage. + * @retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. */ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option); +/*! + * @brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Get System LDO Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t. + */ +static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT); +} + +/*! + * @brief Set System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT); +} + /*! * @brief Configs System LDO regulator in low power modes. * @@ -1628,17 +2145,44 @@ status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_act */ status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option); -/* @} */ +/*! + * @brief Set System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); /*! - * @name Set DCDC Regulator. + * @brief Get System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT); +} +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @name Low Level APIs To Set DCDC Regulator * @{ */ /*! * @brief Enable/Disable DCDC Regulator. * - * @note The DCDC enable bit is write-once. + * @note The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event. * * @param base SPC peripheral base address. * @param enable Enable/Disable DCDC Regulator. @@ -1670,61 +2214,220 @@ static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable) void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config); /*! - * @brief Set the count value of the reference clock. + * @brief Trigger a software burst request to DCDC. * - * This function set the count value of the reference clock to control the frequency - * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * @param base SPC peripheral base address. + */ +static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base) +{ + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; +} + +/*! + * @brief Check if burst acknowlege flag is asserted. + * + * @param base SPC peripheral base address. + * + * @retval false DCDC burst not complete. + * @retval true DCDC burst complete. + */ +static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base) +{ + return ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0UL); +} + +/*! + * @brief Clear DCDC busrt acknowledge flag. + * + * @param base SPC periphral base address. + */ +static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base) +{ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; +} + +/*! + * @brief Set the count value of the reference clock to configure the period of DCDC not active. + * + * @note This function is only useful when DCDC's drive strength is set as pulse refresh. + * @note The pulse duration(time between on and off) is: reference clock period * (count + 2). * * @param base SPC peripheral base address. * @param count The count value, 16 bit width. */ void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) && FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) /*! - * @brief Configs DCDC VDD Regulator in Active mode. + * @brief Enable a bleed resistor to discharge DCDC output when DCDC is disabled. * - * This function configs DCDC VDD Regulator in Active mode. - * If DCDDC VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed - * to a value that enable the bandgap. - * If any voltage detects are kept enabled, configuration to set DCDC VDD drive strength to low will - * be ignored. - * When switching DCDC from low drive strength to Normal driver strength, make sure the DCDC high VDD LVL - * setting to the same level that was set prior to switching the DCDC to low drive strength. + * @param base SPC peripheral base address. + * @param enable Used to enable/disable bleed resistor. + */ +static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable) +{ + if (enable) + { + base->DCDC_CFG |= SPC_DCDC_CFG_BLEED_EN_MASK; + } + else + { + base->DCDC_CFG &= ~SPC_DCDC_CFG_BLEED_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN */ + +/*! + * @brief Configs DCDC_CORE Regulator in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. * * @param base SPC peripheral base address. * @param option Pointer to the spc_active_mode_dcdc_option_t structure. * * @retval #kStatus_Success Config DCDC regulator in Active power mode successful. * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. */ status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option); /*! - * @brief Configs DCDC VDD Regulator in Low power modes. + * @brief Set DCDC_CORE Regulator voltage level in Active mode. * - * This function configs DCDC VDD Regulator in Low Power modes. - * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = + (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Active mode. + * + * @note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Configs DCDC_CORE Regulator in Low power modes. + * + * @note If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed * to a value that enables the Bandgap. - * If any of voltage detectors are kept enabled, configuration to set DCDC VDD Drive Strength to Low or Pulse mode - * will be ignored. - * In Deep Power Down mode, DCDC regulator is always turned off. + * @note In Deep Power Down mode, DCDC regulator is always turned off. * * @param base SPC peripheral base address. * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure. * * @retval #kStatus_Success Config DCDC regulator in low power mode successfully. * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. - * @retval #kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. - * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. */ status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option); -/* @} */ +/*! + * @brief Set DCDC_CORE Regulator drive strength in Low power mode. + * + * @note To set drive strength as normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Low power mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >> + SPC_LP_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Low power mode. + * + * @note To change DCDC level in Low-Power mode: + * 1. Configure LP_CFG[DCDC_VDD_LVL] to desired level; + * 2. Configure LP_CFG[DCDC_VDD_DS] to low driver strength; + * 3. Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1. + * + * @note After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed, + * if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel); + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, kSPC_DCDC_LowDriveStrength); + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >> + SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + #if defined(__cplusplus) } #endif /* __cplusplus */ /*! @} */ -#endif /* _FSL_SPC_H_ */ +#endif /* FSL_SPC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_syspm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_syspm.h index ed5df6c9d9..bfa5bf28aa 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_syspm.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_syspm.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SYSPM_H_ -#define _FSL_SYSPM_H_ +#ifndef FSL_SYSPM_H_ +#define FSL_SYSPM_H_ #include "fsl_common.h" @@ -19,11 +19,11 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief SYSPM driver version */ #define FSL_SYSPM_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ +/*! @} */ /*! @brief syspm select control monitor */ typedef enum _syspm_monitor { @@ -162,4 +162,4 @@ uint64_t SYSPM_GetEventCounter(SYSPM_Type *base, syspm_monitor_t monitor, syspm_ /*! @}*/ -#endif /* _FSL_SYSPM_H_*/ +#endif /* FSL_SYSPM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.c index 3404d711e9..4caa262a50 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.c @@ -193,6 +193,7 @@ void TDET_Deinit(DIGTMP_Type *base) * defaultConfig->updateMode = kTDET_StatusLockWithTamper * defaultConfig->clockSourceActiveTamper0 = kTDET_ClockType1Hz * defaultConfig->clockSourceActiveTamper1 = kTDET_ClockType1Hz + * defaultConfig->disablePrescalerAfterTamper = false * defaultConfig->prescaler = 0 * endcode * param base TDET peripheral base address @@ -209,6 +210,7 @@ void TDET_GetDefaultConfig(DIGTMP_Type *base, tdet_config_t *defaultConfig) kTDET_StatusLockWithTamper, /* updateMode */ kTDET_ClockType1Hz, /* clockSourceActiveTamper0 */ kTDET_ClockType1Hz, /* clockSourceActiveTamper1 */ + false, /* disable prescaler on tamper event */ 0, /* prescaler */ }; @@ -239,6 +241,7 @@ status_t TDET_SetConfig(DIGTMP_Type *base, const tdet_config_t *config) tmpCR |= DIGTMP_CR_UM(config->updateMode); tmpCR |= DIGTMP_CR_ATCS0(config->clockSourceActiveTamper0); tmpCR |= DIGTMP_CR_ATCS1(config->clockSourceActiveTamper1); + tmpCR |= DIGTMP_CR_DISTAM(config->disablePrescalerAfterTamper); tmpCR |= DIGTMP_CR_DPR(config->prescaler); /* write the computed value to the CR register */ base->CR = tmpCR; @@ -377,7 +380,7 @@ void TDET_PinGetDefaultConfig(DIGTMP_Type *base, tdet_pin_config_t *pinConfig) * param base TDET peripheral base address * param pinConfig Pointer to structure with tamper pin and glitch filter configuration parameters * param pinSelect Bit mask for tamper pins to be configured. The passed value is combination of - * enum _tdet_tamper_pin (tdet_tamper_pin_t) values (OR'ed). + * enum _tdet_external_tamper_pin (tdet_external_tamper_pin_t) values (OR'ed). * return kStatus_Fail when writing to TDET Pin Direction, Pin Polarity or Glitch Filter Register(s) is not allowed * return kStatus_Success when operation completes successfully */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.h index 84f3678d83..78ecda6d87 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tdet.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_TDET_H_ -#define _FSL_TDET_H_ +#ifndef FSL_TDET_H_ +#define FSL_TDET_H_ #include "fsl_common.h" @@ -21,15 +21,17 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief Defines TDET driver version 2.0.0. +/*! @{ */ +/*! @brief Defines TDET driver version 2.1.0. * * Change log: + * - Version 2.1.0 + * - Added setting of disabling prescaler on tamper event into TDET_SetConfig() and TDET_GetDefaultConfig functions. * - Version 2.0.0 - * - initial version + * - Initial version */ -#define FSL_TDET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ +#define FSL_TDET_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @} */ /*! * @brief TDET Update Mode. @@ -71,8 +73,13 @@ typedef struct _tdet_config enum _tdet_active_tamper_clock clockSourceActiveTamper0; /*!< Selects clock source for Active Tamper Shift Register 0 */ enum _tdet_active_tamper_clock - clockSourceActiveTamper1; /*!< Selects clock source for Active Tamper Shift Register 1 */ - uint32_t prescaler; /*!< Initial value for the TDET prescaler 15-bit value. */ + clockSourceActiveTamper1; /*!< Selects clock source for Active Tamper Shift Register 1 */ + bool disablePrescalerAfterTamper; /*!< Allows the 32-KHz clock and prescaler to be automatically disabled after + tamper detection and until the system acknowledges the tamper. Disabling the + prescaler after detecting a tamper event conserves power and freezes the state + of the active tamper outputs and glitch filters. To ensure a clean transition, + the prescaler is disabled at the end of a 1 Hz period. */ + uint32_t prescaler; /*!< Initial value for the TDET prescaler 15-bit value. */ } tdet_config_t; /*! @@ -591,4 +598,4 @@ void TDET_LockRegisters(DIGTMP_Type *base, uint32_t mask); /*! @}*/ /* end of group tdet */ -#endif /* _FSL_TDET_H_ */ +#endif /* FSL_TDET_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc.c new file mode 100644 index 0000000000..b94abe1afb --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc.c @@ -0,0 +1,854 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_trdc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trdc1" +#endif + +/* The memory increment definition in byte of MBC and MRC configuration registers */ +#define TRDC_MRC_DOMAIN_INCREMENT 0x100UL +#define TRDC_MBC_DOMAIN_INCREMENT 0x200UL +/* In latest TRDC register definition this macro has been removed from device header file. Add this for backward + * compatability. */ +#ifndef TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL +#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) ((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) +#endif +/* Get the memory increment in for each slave inside MBC */ +#define TRDC_MBC_SLAVE_INCREMENT(x) \ + (((x) == 0U) ? (0U) : (((x) == 1U) ? (0x140UL) : (((x) == 2U) ? (0x168UL) : (0x190UL)))) + +typedef union +{ +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT + trdc_processor_domain_assignment_t _processor_domain_assignment; + trdc_non_processor_domain_assignment_t _non_processor_domain_assignment; + trdc_pid_config_t _pid_config; +#endif +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG + trdc_idau_config_t _idau_config; +#endif +#if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \ + (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC) + trdc_memory_access_control_config_t _memory_access_control; +#endif +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC + trdc_mbc_memory_block_config_t _mbc_memory_blk; + trdc_mbc_nse_update_config_t _mbc_nse_update; +#endif + uint32_t _u32; +} trdc_reg32_convert_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * brief Gets the TRDC hardware configuration. + * + * This function gets the TRDC hardware configurations, including number of bus + * masters, number of domains, number of MRCs and number of PACs. + * + * param base TRDC peripheral base address. + * param config Pointer to the structure to get the configuration. + */ +void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config) +{ + assert(NULL != config); + + config->masterNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT); + config->domainNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT); + config->mbcNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> TRDC_TRDC_HWCFG0_NMBC_SHIFT); + config->mrcNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMRC_MASK) >> TRDC_TRDC_HWCFG0_NMRC_SHIFT); +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker). + * + * param base TRDC peripheral base address. + * param config Pointer to the structure to get the configuration. + * param mbcIdx MBC number. + * param slvIdx Slave number. + */ +void TRDC_GetMbcHardwareConfig(TRDC_Type *base, + trdc_slave_memory_hardware_config_t *config, + uint8_t mbcIdx, + uint8_t slvIdx) +{ + assert(NULL != config); +#if defined(TRDC_MBC_COUNT) && TRDC_MBC_COUNT + assert(mbcIdx < (uint8_t)TRDC_MBC_COUNT); +#else + assert(mbcIdx < (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> + TRDC_TRDC_HWCFG0_NMBC_SHIFT)); +#endif + assert(slvIdx < 4U); + + config->blockNum = TRDC_MBC_BASE(base, mbcIdx)->MBC_MEM_GLBCFG[slvIdx] & TRDC_MBC_MEM_GLBCFG_NBLKS_MASK; + config->blockSize = (TRDC_MBC_BASE(base, mbcIdx)->MBC_MEM_GLBCFG[slvIdx] & TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) >> + TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT +/*! + * brief Gets the default master domain assignment for the processor bus master. + * + * This function gets the default master domain assignment for the processor bus master. + * It should only be used for the processor bus masters, such as CORE0. This function + * sets the assignment as follows: + * + * code + * assignment->domainId = 0U; + * assignment->domainIdSelect = kTRDC_DidMda; + * assignment->lock = 0U; + * endcode + * + * param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment) +{ + assert(NULL != domainAssignment); + + /* Initializes the configure structure to zero. */ + (void)memset(domainAssignment, 0, sizeof(*domainAssignment)); +} + +/*! + * brief Gets the default master domain assignment for non-processor bus master. + * + * This function gets the default master domain assignment for non-processor bus master. + * It should only be used for the non-processor bus masters, such as DMA. This function + * sets the assignment as follows: + * + * code + * assignment->domainId = 0U; + * assignment->privilegeAttr = kTRDC_ForceUser; + * assignment->secureAttr = kTRDC_ForceSecure; + * assignment->bypassDomainId = 0U; + * assignment->lock = 0U; + * endcode + * + * param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment) +{ + assert(NULL != domainAssignment); + + /* Initializes the configure structure to zero. */ + (void)memset(domainAssignment, 0, sizeof(*domainAssignment)); +} + +/*! + * brief Sets the processor bus master domain assignment. + * + * This function sets the processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for core 0. + * + * code + * trdc_processor_domain_assignment_t processorAssignment; + * + * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); + * + * processorAssignment.domainId = 0; + * processorAssignment.xxx = xxx; + * TRDC_SetMasterDomainAssignment(TRDC, 1, &processorAssignment); + * endcode + * + * param base TRDC peripheral base address. + * param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance. + * param regNum Which register to configure, processor master can have more than one register for the MDAC + * configuration. param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + uint8_t regNum, + const trdc_processor_domain_assignment_t *domainAssignment) +{ + /* Make sure the master number does not exceed the max master count. */ + assert(master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + /* Make sure the master is a processor master. */ + assert(0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)); + assert(NULL != domainAssignment); + assert(domainAssignment->domainId < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT)); + + trdc_reg32_convert_t pid; + pid._processor_domain_assignment = *domainAssignment; + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] = pid._u32 | TRDC_MDA_W_DFMT0_VLD_MASK; +} + +/*! + * brief Sets the non-processor bus master domain assignment. + * + * This function sets the non-processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for DMA0. + * code + * trdc_non_processor_domain_assignment_t nonProcessorAssignment; + * + * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); + * nonProcessorAssignment.domainId = 1; + * nonProcessorAssignment.xxx = xxx; + * + * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment); + * endcode + * + * param base TRDC peripheral base address. + * param master Which master to configure, refer to trdc_master_t in processor header file. + * param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + const trdc_non_processor_domain_assignment_t *domainAssignment) +{ + /* The master number should be less than the master count. */ + assert(master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + /* Make sure the master is a non-CPU/non-processor master */ + assert(0U != (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)); + assert(NULL != domainAssignment); + assert(domainAssignment->domainId < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT)); + + trdc_reg32_convert_t pid; + pid._non_processor_domain_assignment = *domainAssignment; + + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] = pid._u32 | TRDC_MDA_W_DFMT1_VLD_MASK; +} + +/*! + * brief Sets the current Process identifier(PID) for processor core. + * + * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. + * Secure privileged software saves and restores the PID as part of any context switch. + * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register + * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] + * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding + * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information + * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality. + * + * param base TRDC peripheral base address. + * param master Which processor master to configure, refer to trdc_master_t in processor header file. + * param pidConfig Pointer to the configuration structure. + */ +void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig) +{ + assert(pidConfig != NULL); + /* The master number should be less than the master count. */ + assert(master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + /* This master has to be a processor master. */ + assert((TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK) == 0U); + + trdc_reg32_convert_t pid; + pid._pid_config = *pidConfig; + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->PID[master] = pid._u32; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration. + * + * code + * config->lockSecureVTOR = false; + * config->lockNonsecureVTOR = false; + * config->lockSecureMPU = false; + * config->lockNonsecureMPU = false; + * config->lockSAU = false; + * endcode + * + * param domainAssignment Pointer to the configuration structure. + */ +void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration) +{ + assert(NULL != idauConfiguration); + + /* Initializes the configure structure to zero. */ + (void)memset(idauConfiguration, 0, sizeof(*idauConfiguration)); +} + +/*! + * brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration. + * + * Example: Lock the secure and non-secure MPU registers. + * + * code + * trdc_idau_config_t idauConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&idauConfiguration); + * + * idauConfiguration.lockSecureMPU = true; + * idauConfiguration.lockNonsecureMPU = true; + * TRDC_SetIDAU(TRDC, &idauConfiguration); + * endcode + * + * param base TRDC peripheral base address. + * param domainAssignment Pointer to the configuration structure. + */ +void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration) +{ + assert(NULL != idauConfiguration); + + trdc_reg32_convert_t pid; + pid._idau_config = *idauConfiguration; + + TRDC_GENERAL_BASE(base)->TRDC_IDAU_CR = pid._u32 | TRDC_TRDC_IDAU_CR_VLD_MASK; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW +/*! + * brief Gets the default FLW(Flsh Logical Window) configuration. + * + * code + * config->blockCount = false; + * config->arrayBaseAddr = false; + * config->lock = false; + * config->enable = false; + * endcode + * + * param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration) +{ + assert(NULL != flwConfiguration); + + /* Initializes the configure structure to zero. */ + (void)memset(flwConfiguration, 0, sizeof(*flwConfiguration)); + + flwConfiguration->enable = 0x1UL; +} + +/*! + * brief Sets the FLW function's configuration. + * + * code + * trdc_flw_config_t flwConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&flwConfiguration); + * + * flwConfiguration.blockCount = 32U; + * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX; + * TRDC_SetIDAU(TRDC, &flwConfiguration); + * endcode + * + * param base TRDC peripheral base address. + * param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration) +{ + assert(NULL != flwConfiguration); + + TRDC_FLW_BASE(base)->TRDC_FLW_ABASE = flwConfiguration->arrayBaseAddr; + TRDC_FLW_BASE(base)->TRDC_FLW_BCNT = flwConfiguration->blockCount; + TRDC_FLW_BASE(base)->TRDC_FLW_CTL = + TRDC_TRDC_FLW_CTL_V(flwConfiguration->enable) | TRDC_TRDC_FLW_CTL_LK(flwConfiguration->lock); +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__))) +/*! + * @brief Count the leading zeros. + * + * Count the leading zeros of an 32-bit data. This function is only defined + * for CM0 and CM0+ for IAR, because other cortex series have the clz instruction, + * KEIL and ARMGCC have toolchain build in function for this purpose. + * + * @param data The data to process. + * @return Count of the leading zeros. + */ +static uint8_t TRDC_CountLeadingZeros(uint32_t data) +{ + uint8_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count++; + mask >>= 1U; + } + + return count; +} +#endif +#endif + +/*! + * brief Initializes the TRDC module. + * + * This function enables the TRDC clock. + * + * param base TRDC peripheral base address. + */ +void TRDC_Init(TRDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the TRDC module. + * + * This function disables the TRDC clock. + * + * param base TRDC peripheral base address. + */ +void TRDC_Deinit(TRDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +/*! + * brief Gets and clears the first domain error of the current domain. + * + * This function gets the first access violation information for the current domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * param base TRDC peripheral base address. + * param error Pointer to the error information. + * return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error) +{ + return TRDC_GetAndClearFirstSpecificDomainError(base, error, TRDC_GetCurrentMasterDomainId(base)); +} + +/*! + * brief Gets and clears the first domain error of the specific domain. + * + * This function gets the first access violation information for the specific domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * param base TRDC peripheral base address. + * param error Pointer to the error information. + * param domainId The error of which domain to get and clear. + * return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId) +{ + assert(NULL != error); + + status_t status; + uint8_t errorIndex; /* The index of first domain error. */ + uint32_t errorBitMap; /* Domain error location bit map. */ + uint32_t regW1; /* To save TRDC_DERR_W1. */ + + /* Get the error bitmap. */ + errorBitMap = TRDC_DOMAIN_ERROR_BASE(base)->TRDC_DERRLOC[domainId]; + + if (0U == errorBitMap) /* No error captured. */ + { + status = kStatus_NoData; + } + else + { + /* Get the first error controller index. */ +#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__))) + errorIndex = 31U - TRDC_CountLeadingZeros(errorBitMap); +#else + errorIndex = 31U - __CLZ(errorBitMap); +#endif + + /* Must write TRDC_FDID[TRDC_FDID] with the domain ID before reading the Domain Error registers. */ + TRDC_DOMAIN_ERROR_BASE(base)->TRDC_FDID = TRDC_TRDC_FDID_FDID(domainId); + + /* Initializes the error structure to zero. */ + (void)memset(error, 0, sizeof(*error)); + + if (errorIndex > 15U) + { + /* Error in Memory Region Checker (MRC) */ + errorIndex -= 12U; + error->controller = (trdc_controller_t)errorIndex; + errorIndex -= 4U; + + /* Get the error information. */ + regW1 = TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W1; + error->address = TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W0; + /* Clear error pending. */ + TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W3 = TRDC_W3_RECR(0x01U); + } + else + { + /* Error in Memory Block Controller (MBC) */ + error->slaveMemoryIdx = errorIndex % 4U; + errorIndex /= 4U; + error->controller = (trdc_controller_t)errorIndex; + + /* Check if the MBC error index exceeds the module's max MBC index to avoid overrun access. */ + if (errorIndex >= + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> TRDC_TRDC_HWCFG0_NMBC_SHIFT)) + { + return kStatus_Fail; + } + + error->controller = (trdc_controller_t)errorIndex; + + /* Get the error information. */ + regW1 = TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W1; + error->address = TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W0; + /* Clear error pending. */ + TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W3 = TRDC_W3_RECR(0x01U); + } + + uint8_t tempVal = 0U; + error->domainId = (uint8_t)((regW1 & TRDC_W1_EDID_MASK) >> TRDC_W1_EDID_MASK); + tempVal = (uint8_t)((regW1 & TRDC_W1_EATR_MASK) >> TRDC_W1_EATR_SHIFT); + error->errorAttr = (trdc_error_attr_t)tempVal; + tempVal = (uint8_t)((regW1 & TRDC_W1_ERW_MASK) >> TRDC_W1_ERW_SHIFT); + error->errorType = (trdc_error_type_t)tempVal; + error->errorPort = (uint8_t)((regW1 & TRDC_W1_EPORT_MASK) >> TRDC_W1_EPORT_SHIFT); + tempVal = (uint8_t)((regW1 & TRDC_W1_EST_MASK) >> TRDC_W1_EST_SHIFT); + error->errorState = (trdc_error_state_t)tempVal; + + status = kStatus_Success; + } + + return status; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC +/*! + * brief Sets the memory access configuration for one of the access control register of one MRC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1); + * endcode + * + * param base TRDC peripheral base address. + * param config Pointer to the configuration structure. + * param mrcIdx MRC index. + * param regIdx Register number. + */ +void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mrcIdx, + uint8_t regIdx) +{ + assert(NULL != base); + assert(NULL != config); + + trdc_reg32_convert_t pid; + + pid._memory_access_control = *config; + TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBAC[regIdx] = pid._u32; +} + +/*! + * brief Enables the update of the selected domians. + * + * After the domians' update are enabled, their regions' NSE bits can be set or clear. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param domianMask Bit mask of the domains to be enabled. + * param enable True to enable, false to disable. + */ +void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable) +{ + assert(NULL != base); + + if (enable) + { + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_INDIRECT |= ((uint32_t)domianMask << 16U); + } + else + { + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_INDIRECT &= ~((uint32_t)domianMask << 16U); + } +} + +/*! + * brief Sets the NSE bits of the selected regions for domains. + * + * This function sets the NSE bits for the selected regions for the domains whose update are enabled. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param regionMask Bit mask of the regions whose NSE bits to set. + */ +void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask) +{ + assert(NULL != base); + + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_SET = ((uint32_t)regionMask); +} + +/*! + * brief Clears the NSE bits of the selected regions for domains. + * + * This function clears the NSE bits for the selected regions for the domains whose update are enabled. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param regionMask Bit mask of the regions whose NSE bits to clear. + */ +void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask) +{ + assert(NULL != base); + + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_CLR = ((uint32_t)regionMask); +} + +/*! + * brief Clears the NSE bits for all the regions of the selected domains. + * + * This function clears the NSE bits for all regions of selected domains whose update are enabled. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param domainMask Bit mask of the domians whose NSE bits to clear. + */ +void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask) +{ + assert(NULL != base); + + uint8_t domainCount = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT); + uint8_t maxDomainId = 0U; + uint16_t tmpDomainMask = domainMask; + + while (tmpDomainMask != 0U) + { + tmpDomainMask >>= 1U; + maxDomainId++; + } + + /* Check whether the domain mask contains invalid domain. */ + if (maxDomainId > domainCount) + { + assert(false); + } + + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_CLR_ALL = ((uint32_t)domainMask << 16U); +} + +/*! + * brief Sets the configuration for one of the region descriptor per domain per MRC instnce. + * + * This function sets the configuration for one of the region descriptor, including the start + * and end address of the region, memory access control policy and valid. + * + * param base TRDC peripheral base address. + * param config Pointer to region descriptor configuration structure. + */ +void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config) +{ + assert(NULL != base); + + uint32_t regAddr = (uint32_t) & (TRDC_MRC_BASE(base, config->mrcIdx)->MRC_DOM0_RGD_W[config->regionIdx][0]); + + regAddr += TRDC_MRC_DOMAIN_INCREMENT * config->domainIdx; + + /* Set configuration for word 0 */ + uint32_t data = TRDC_MRC_DOM0_RGD_W_MRACSEL(config->memoryAccessControlSelect) | + ((config->startAddr) & ~(TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK)); + *(uint32_t *)regAddr = data; + + /* Set configuration for word 1 */ + regAddr += 4U; + data = TRDC_MRC_DOM0_RGD_W_VLD(config->valid) | TRDC_MRC_DOM0_RGD_W_NSE(config->nseEnable) | + ((config->endAddr) & ~(TRDC_MRC_DOM0_RGD_W_VLD_MASK | TRDC_MRC_DOM0_RGD_W_NSE_MASK)); + *(uint32_t *)regAddr = data; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * brief Sets the NSR update configuration for one of the MBC instance. + * + * After set the NSE configuration, the configured memory area can be updateby NSE set/clear. + * + * param base TRDC peripheral base address. + * param config Pointer to NSE update configuration structure. + * param mbcIdx MBC index. + */ +void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx) +{ + assert(base != NULL); + + trdc_reg32_convert_t pid; + + pid._mbc_nse_update = *config; + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_INDEX = pid._u32; +} + +/*! + * brief Sets the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * param base TRDC peripheral base address. + * param mbcIdx MBC index. + * param bitMask Mask of the bits whose NSE bits to set. + */ +void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask) +{ + assert(NULL != base); + + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_SET = ((uint32_t)bitMask); +} + +/*! + * brief Clears the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * param base TRDC peripheral base address. + * param mbcIdx MBC index. + * param bitMask Mask of the bits whose NSE bits to clear. + */ +void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask) +{ + assert(NULL != base); + + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_CLR = ((uint32_t)bitMask); +} + +/*! + * brief Clears all configuration words' NSE bits of the selected domain and memory. + * + * param base TRDC peripheral base address. + * param mbcIdx MBC index. + * param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2. + * param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits. + */ +void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave) +{ + assert(NULL != base); + +#if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && FSL_FEATURE_TRDC_DOMAIN_COUNT + uint8_t dmainCount = FSL_FEATURE_TRDC_DOMAIN_COUNT; +#else + uint8_t dmainCount = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT); +#endif + uint8_t maxDomainId = 0U; + uint16_t tmpDomainMask = domainMask; + + while (tmpDomainMask != 0U) + { + tmpDomainMask >>= 1U; + maxDomainId++; + } + + if (maxDomainId > dmainCount) + { + assert(false); + } + + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_CLR_ALL = + TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(domainMask) | TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(slave); +} + +/*! + * brief Sets the memory access configuration for one of the region descriptor of one MBC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1); + * endcode + * + * param base TRDC peripheral base address. + * param config Pointer to the configuration structure. + * param mbcIdx MBC index. + * param rgdIdx Region descriptor number. + */ +void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mbcIdx, + uint8_t rgdIdx) +{ + assert(NULL != base); + assert(NULL != config); + + trdc_reg32_convert_t pid; + + pid._memory_access_control = *config; + TRDC_MBC_BASE(base, mbcIdx)->MBC_MEMN_GLBAC[rgdIdx] = pid._u32; +} + +/*! + * brief Sets the configuration for one of the memory block per domain per MBC instnce. + * + * This function sets the configuration for one of the memory block, including the memory access + * control policy and nse enable. + * + * param base TRDC peripheral base address. + * param config Pointer to memory block configuration structure. + */ +void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config) +{ + assert(NULL != base); + + uint32_t shift = 4UL * (config->memoryBlockIdx % 8UL); + uint32_t regAddr = (uint32_t) & (TRDC_MBC_BASE(base, config->mbcIdx)->MBC_DOM0_MEM0_BLK_CFG_W[0]); + uint32_t configWord = 0U; + trdc_reg32_convert_t pid; + + pid._mbc_memory_blk = *config; + configWord = (pid._u32 & 0xFU) << shift; + + regAddr += (TRDC_MBC_DOMAIN_INCREMENT * config->domainIdx + TRDC_MBC_SLAVE_INCREMENT(config->slaveMemoryIdx)) + + ((uint32_t)config->memoryBlockIdx / 8U) * sizeof(uint32_t); + configWord = configWord | (*(uint32_t *)regAddr & ~(0xFUL << shift)); + *(uint32_t *)regAddr = configWord; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc.h new file mode 100644 index 0000000000..68d2953088 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc.h @@ -0,0 +1,1131 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_TRDC_H_ +#define FSL_TRDC_H_ + +#include "fsl_common.h" +#include "fsl_trdc_core.h" + +/*! + * @addtogroup trdc + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ +#define FSL_TRDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/* Hardware configuration definitions */ +/*! + * @brief TRDC hardware configuration. + */ +typedef struct _trdc_hardware_config +{ + uint8_t masterNumber; /*!< Number of bus masters. */ + uint8_t domainNumber; /*!< Number of domains. */ + uint8_t mbcNumber; /*!< Number of MBCs. */ + uint8_t mrcNumber; /*!< Number of MRCs. */ +} trdc_hardware_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * @brief Hardware configuration of the two slave memories within each MBC(memory block checker). + */ +typedef struct _trdc_slave_memory_hardware_config +{ + uint32_t blockNum; /*!< Number of blocks. */ + uint32_t blockSize; /*!< Block size. */ +} trdc_slave_memory_hardware_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT +/* Master domain assignment definitions */ +/*! + * @brief TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for + * domain hit evaluation. + */ +typedef enum _trdc_did_sel +{ + kTRDC_DidMda, /*!< Use MDAn[2:0] as DID. */ + kTRDC_DidInput, /*!< Use the input DID (DID_in) as DID. */ + kTRDC_DidMdaAndInput, /*!< Use MDAn[2] concatenated with DID_in[1:0] as DID. */ + kTRDC_DidReserved /*!< Reserved. */ +} trdc_did_sel_t; + +/*! + * @brief TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for + * bus master domain assignment. + */ +typedef enum _trdc_secure_attr +{ + kTRDC_ForceSecure, /*!< Force the bus attribute for this master to secure. */ + kTRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure. */ + kTRDC_MasterSecure, /*!< Use the bus master's secure/nonsecure attribute directly. */ + kTRDC_MasterSecure1, /*!< Use the bus master's secure/nonsecure attribute directly. */ +} trdc_secure_attr_t; + +/*! + * @brief The configuration of domain hit evaluation of PID. + */ +typedef enum _trdc_pid_domain_hit_config +{ + kTRDC_pidDomainHitNone0, /*!< No PID is included in the domain hit evaluation. */ + kTRDC_pidDomainHitNone1, /*!< No PID is included in the domain hit evaluation. */ + kTRDC_pidDomainHitInclusive, /*!< The PID is included in the domain hit evaluation when (PID & ~PIDM). */ + kTRDC_pidDomainHitExclusive, /*!< The PID is included in the domain hit evaluation when ~(PID & ~PIDM). */ +} trdc_pid_domain_hit_config_t; + +/*! + * @brief Domain assignment for the processor bus master. + */ +typedef struct _trdc_processor_domain_assignment +{ + uint32_t domainId : 4U; /*!< Domain ID. */ + uint32_t domainIdSelect : 2U; /*!< Domain ID select method, see @ref trdc_did_sel_t. */ + uint32_t pidDomainHitConfig : 2U; /*!< The configuration of the domain hit evaluation for PID, see @ref + trdc_pid_domain_hit_config_t. */ + uint32_t pidMask : 6U; /*!< The mask combined with PID, so multiple PID can be included as part of the domain hit + determination. Set to 0 to disable. */ + uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */ + uint32_t pid : 6U; /*!< The process identifier, combined with pidMask to form the domain hit determination. */ + uint32_t : 8U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the register. */ + uint32_t : 1U; /*!< Reserved. */ +} trdc_processor_domain_assignment_t; + +/*! + * @brief TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor + * bus master domain assignment. + */ +typedef enum _trdc_privilege_attr +{ + kTRDC_ForceUser, /*!< Force the bus attribute for this master to user. */ + kTRDC_ForcePrivilege, /*!< Force the bus attribute for this master to privileged. */ + kTRDC_MasterPrivilege, /*!< Use the bus master's attribute directly. */ + kTRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */ +} trdc_privilege_attr_t; + +/*! + * @brief Domain assignment for the non-processor bus master. + */ +typedef struct _trdc_non_processor_domain_assignment +{ + uint32_t domainId : 4U; /*!< Domain ID. */ + uint32_t privilegeAttr : 2U; /*!< Privileged attribute, see @ref trdc_privilege_attr_t. */ + uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */ + uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */ + uint32_t : 21U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the register. */ + uint32_t : 1U; /*!< Reserved. */ +} trdc_non_processor_domain_assignment_t; + +/*! + * @brief PID lock configuration. + */ +typedef enum _trdc_pid_lock +{ + kTRDC_PidUnlocked0, /*!< The PID value can be updated by any secure priviledged write. */ + kTRDC_PidUnlocked1, /*!< The PID value can be updated by any secure priviledged write. */ + kTRDC_PidUnlocked2, /*!< The PID value can be updated by any secure priviledged write from the bus master that first + configured this register. */ + kTRDC_PidLocked, /*!< The PID value is locked until next reset. */ +} trdc_pid_lock_t; + +/*! + * @brief Process identifier(PID) configuration for processor cores. + */ +typedef struct _trdc_pid_config +{ + uint32_t pid : 6U; /*!< The process identifier of the executing task. The highest bit can be used to define + secure/nonsecure attribute of the task. */ + uint32_t : 23U; /*!< Reserved. */ + uint32_t lock : 2U; /*!< How to lock the register, see @ref trdc_pid_lock_t. */ + uint32_t : 1U; /*!< Reserved. */ +} trdc_pid_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/* TZ-M congiguration definitions */ +/*! + * @brief IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control. + */ +typedef struct _trdc_idau_config +{ + uint32_t : 8U; /*!< Reserved. */ + uint32_t lockSecureVTOR : 1U; /*!< Disable writes to secure VTOR(Vector Table Offset Register). */ + uint32_t lockNonsecureVTOR : 1U; /*!< Disable writes to non-secure VTOR, Application interrupt and Reset Control + Registers. */ + uint32_t lockSecureMPU : 1U; /*!< Disable writes to secure MPU(Memory Protection Unit) from software or from a debug + agent connected to the processor in Secure state. */ + uint32_t lockNonsecureMPU : 1U; /*!< Disable writes to non-secure MPU(Memory Protection Unit) from software or from + a debug agent connected to the processor. */ + uint32_t lockSAU : 1U; /*!< Disable writes to SAU(Security Attribution Unit) registers. */ + uint32_t : 19U; /*!< Reserved. */ +} trdc_idau_config_t; + +/* FLW(Flash Logical Window) configuration definitions */ +/*! + * @brief FLW(Flash Logical Window) configuration. + */ +typedef struct _trdc_flw_config +{ + uint16_t blockCount; /*!< Block count of the Flash Logic Window in 32KByte blocks. */ + uint32_t arrayBaseAddr; /*!< Flash array base address of the Flash Logical Window. */ + bool lock; /*!< Disable writes to FLW registers. */ + bool enable; /*!< Enable FLW function. */ +} trdc_flw_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +/* Domain error check and clear definitions */ +/*! + * @brief TRDC controller definition for domain error check. Each TRDC instance may have different + * MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count. + */ +typedef enum _trdc_controller +{ + kTRDC_MemBlockController0 = 0U, /*!< Memory block checker 0. */ + kTRDC_MemBlockController1 = 1U, /*!< Memory block checker 1. */ + kTRDC_MemBlockController2 = 2U, /*!< Memory block checker 2. */ + kTRDC_MemBlockController3 = 3U, /*!< Memory block checker 3. */ + kTRDC_MemRegionChecker0 = 4U, /*!< Memory region checker 0. */ + kTRDC_MemRegionChecker1 = 5U, /*!< Memory region checker 1. */ + kTRDC_MemRegionChecker2 = 6U, /*!< Memory region checker 2. */ + kTRDC_MemRegionChecker3 = 7U, /*!< Memory region checker 3. */ + kTRDC_MemRegionChecker4 = 8U, /*!< Memory region checker 4. */ + kTRDC_MemRegionChecker5 = 9U, /*!< Memory region checker 5. */ + kTRDC_MemRegionChecker6 = 10U, /*!< Memory region checker 6. */ +} trdc_controller_t; + +/*! + * @brief TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST]. + */ +typedef enum _trdc_error_state +{ + kTRDC_ErrorStateNone = 0x00U, /*!< No access violation detected. */ + kTRDC_ErrorStateNone1 = 0x01U, /*!< No access violation detected. */ + kTRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected. */ + kTRDC_ErrorStateMulti = 0x03U /*!< Multiple access violation detected. */ +} trdc_error_state_t; + +/*! + * @brief TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR]. + */ +typedef enum _trdc_error_attr +{ + kTRDC_ErrorSecureUserInst = 0x00U, /*!< Secure user mode, instruction fetch access. */ + kTRDC_ErrorSecureUserData = 0x01U, /*!< Secure user mode, data access. */ + kTRDC_ErrorSecurePrivilegeInst = 0x02U, /*!< Secure privileged mode, instruction fetch access. */ + kTRDC_ErrorSecurePrivilegeData = 0x03U, /*!< Secure privileged mode, data access. */ + kTRDC_ErrorNonSecureUserInst = 0x04U, /*!< NonSecure user mode, instruction fetch access. */ + kTRDC_ErrorNonSecureUserData = 0x05U, /*!< NonSecure user mode, data access. */ + kTRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access. */ + kTRDC_ErrorNonSecurePrivilegeData = 0x07U /*!< NonSecure privileged mode, data access. */ +} trdc_error_attr_t; + +/*! + * @brief TRDC domain error access type definition TRDC_DERR_W1_n[ERW]. + */ +typedef enum _trdc_error_type +{ + kTRDC_ErrorTypeRead = 0x00U, /*!< Error occurs on read reference. */ + kTRDC_ErrorTypeWrite = 0x01U /*!< Error occurs on write reference. */ +} trdc_error_type_t; + +/*! + * @brief TRDC domain error definition. + */ +typedef struct _trdc_domain_error +{ + trdc_controller_t controller; /*!< Which controller captured access violation. */ + uint32_t address; /*!< Access address that generated access violation. */ + trdc_error_state_t errorState; /*!< Error state. */ + trdc_error_attr_t errorAttr; /*!< Error attribute. */ + trdc_error_type_t errorType; /*!< Error type. */ + uint8_t errorPort; /*!< Error port. */ + uint8_t domainId; /*!< Domain ID. */ + uint8_t slaveMemoryIdx; /*!< The slave memory index. Only apply when violation in MBC. */ +} trdc_domain_error_t; +#endif + +#if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \ + (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC) +/* Common definitions for MBC/MRC configuration */ +/*! + * @brief Memory access control configuration for MBC/MRC. + */ +typedef struct _trdc_memory_access_control_config +{ + uint32_t nonsecureUsrX : 1U; /*!< Allow nonsecure user execute access. */ + uint32_t nonsecureUsrW : 1U; /*!< Allow nonsecure user write access. */ + uint32_t nonsecureUsrR : 1U; /*!< Allow nonsecure user read access. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t nonsecurePrivX : 1U; /*!< Allow nonsecure privilege execute access. */ + uint32_t nonsecurePrivW : 1U; /*!< Allow nonsecure privilege write access. */ + uint32_t nonsecurePrivR : 1U; /*!< Allow nonsecure privilege read access. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t secureUsrX : 1U; /*!< Allow secure user execute access. */ + uint32_t secureUsrW : 1U; /*!< Allow secure user write access. */ + uint32_t secureUsrR : 1U; /*!< Allow secure user read access. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t securePrivX : 1U; /*!< Allownsecure privilege execute access. */ + uint32_t securePrivW : 1U; /*!< Allownsecure privilege write access. */ + uint32_t securePrivR : 1U; /*!< Allownsecure privilege read access. */ + uint32_t : 16U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the configuration until next reset, only apply to access control register 0. */ +} trdc_memory_access_control_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC +/*! @brief The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions. + */ +enum _trdc_region_descriptor +{ + kTRDC_RegionDescriptor0 = (1U << 0U), /*!< Region descriptor 0. */ + kTRDC_RegionDescriptor1 = (1U << 1U), /*!< Region descriptor 1. */ + kTRDC_RegionDescriptor2 = (1U << 2U), /*!< Region descriptor 2. */ + kTRDC_RegionDescriptor3 = (1U << 3U), /*!< Region descriptor 3. */ + kTRDC_RegionDescriptor4 = (1U << 4U), /*!< Region descriptor 4. */ + kTRDC_RegionDescriptor5 = (1U << 5U), /*!< Region descriptor 5. */ + kTRDC_RegionDescriptor6 = (1U << 6U), /*!< Region descriptor 6. */ + kTRDC_RegionDescriptor7 = (1U << 7U), /*!< Region descriptor 7. */ + kTRDC_RegionDescriptor8 = (1U << 8U), /*!< Region descriptor 8. */ + kTRDC_RegionDescriptor9 = (1U << 9U), /*!< Region descriptor 9. */ + kTRDC_RegionDescriptor10 = (1U << 10U), /*!< Region descriptor 10. */ + kTRDC_RegionDescriptor11 = (1U << 11U), /*!< Region descriptor 11. */ + kTRDC_RegionDescriptor12 = (1U << 12U), /*!< Region descriptor 12. */ + kTRDC_RegionDescriptor13 = (1U << 13U), /*!< Region descriptor 13. */ + kTRDC_RegionDescriptor14 = (1U << 14U), /*!< Region descriptor 14. */ + kTRDC_RegionDescriptor15 = (1U << 15U), /*!< Region descriptor 15. */ +}; + +/* MRC configuration definitions */ +/*! @brief The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or + * several domains. */ +enum _trdc_MRC_domain +{ + kTRDC_MrcDomain0 = (1U << 0U), /*!< Domain 0. */ + kTRDC_MrcDomain1 = (1U << 1U), /*!< Domain 1. */ + kTRDC_MrcDomain2 = (1U << 2U), /*!< Domain 2. */ + kTRDC_MrcDomain3 = (1U << 3U), /*!< Domain 3. */ + kTRDC_MrcDomain4 = (1U << 4U), /*!< Domain 4. */ + kTRDC_MrcDomain5 = (1U << 5U), /*!< Domain 5. */ + kTRDC_MrcDomain6 = (1U << 6U), /*!< Domain 6. */ + kTRDC_MrcDomain7 = (1U << 7U), /*!< Domain 7. */ + kTRDC_MrcDomain8 = (1U << 8U), /*!< Domain 8. */ + kTRDC_MrcDomain9 = (1U << 9U), /*!< Domain 9. */ + kTRDC_MrcDomain10 = (1U << 10U), /*!< Domain 10. */ + kTRDC_MrcDomain11 = (1U << 11U), /*!< Domain 11. */ + kTRDC_MrcDomain12 = (1U << 12U), /*!< Domain 12. */ + kTRDC_MrcDomain13 = (1U << 13U), /*!< Domain 13. */ + kTRDC_MrcDomain14 = (1U << 14U), /*!< Domain 14. */ + kTRDC_MrcDomain15 = (1U << 15U), /*!< Domain 15. */ +}; + +/*! + * @brief The configuration of each region descriptor per domain per MRC instance. + */ +typedef struct _trdc_mrc_region_descriptor_config +{ + uint8_t memoryAccessControlSelect; /*!< Select one of the 8 access control policies for this region, for + access cotrol policies see @ref trdc_memory_access_control_config_t. */ + uint32_t startAddr; /*!< Physical start address. */ + bool valid; /*!< Lock the register. */ + bool nseEnable; /*!< Enable non-secure accesses and disable secure accesses. */ + uint32_t endAddr; /*!< Physical start address. */ + uint8_t mrcIdx; /*!< The index of the MRC for this configuration to take effect. */ + uint8_t domainIdx; /*!< The index of the domain for this configuration to take effect. */ + uint8_t regionIdx; /*!< The index of the region for this configuration to take effect. */ +} trdc_mrc_region_descriptor_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/* MBC configuration definitions */ +/*! + * @brief The configuration of MBC NSE update. + */ +#if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && (FSL_FEATURE_TRDC_DOMAIN_COUNT > 0x8U) +typedef struct _trdc_mbc_nse_update_config +{ + uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this + configuration. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */ + uint32_t : 2U; /*!< Reserved. */ + uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */ + uint32_t : 4U; /*!< Reserved. */ + uint32_t domianSelect : 16U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */ +} trdc_mbc_nse_update_config_t; +#else +typedef struct _trdc_mbc_nse_update_config +{ + uint32_t : 2U; /*!< Reserved. */ + uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */ + uint32_t : 2U; /*!< Reserved. */ + uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */ + uint32_t : 4U; /*!< Reserved. */ + uint32_t domianSelect : 8U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */ + uint32_t : 7U; /*!< Reserved. */ + uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this + configuration. */ +} trdc_mbc_nse_update_config_t; +#endif + +/*! @brief The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or + * several domains. */ +enum _trdc_MBC_domain +{ + kTRDC_MbcDomain0 = (1U << 0U), /*!< Domain 0. */ + kTRDC_MbcDomain1 = (1U << 1U), /*!< Domain 1. */ + kTRDC_MbcDomain2 = (1U << 2U), /*!< Domain 2. */ + kTRDC_MbcDomain3 = (1U << 3U), /*!< Domain 3. */ + kTRDC_MbcDomain4 = (1U << 4U), /*!< Domain 4. */ + kTRDC_MbcDomain5 = (1U << 5U), /*!< Domain 5. */ + kTRDC_MbcDomain6 = (1U << 6U), /*!< Domain 6. */ + kTRDC_MbcDomain7 = (1U << 7U), /*!< Domain 7. */ +}; + +/*! @brief The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one + * or several memory block. */ +enum _trdc_MBC_memory +{ + kTRDC_MbcSlaveMemory0 = (1U << 0U), /*!< Memory 0. */ + kTRDC_MbcSlaveMemory1 = (1U << 1U), /*!< Memory 1. */ + kTRDC_MbcSlaveMemory2 = (1U << 2U), /*!< Memory 2. */ + kTRDC_MbcSlaveMemory3 = (1U << 3U), /*!< Memory 3. */ +}; + +/*! @brief The MBC bit enumeration, used to form a mask to set/clear configured words' NSE. */ +enum _trdc_MBC_bit +{ + kTRDC_MbcBit0 = (1U << 0U), /*!< Bit 0. */ + kTRDC_MbcBit1 = (1U << 1U), /*!< Bit 1. */ + kTRDC_MbcBit2 = (1U << 2U), /*!< Bit 2. */ + kTRDC_MbcBit3 = (1U << 3U), /*!< Bit 3. */ + kTRDC_MbcBit4 = (1U << 4U), /*!< Bit 4. */ + kTRDC_MbcBit5 = (1U << 5U), /*!< Bit 5. */ + kTRDC_MbcBit6 = (1U << 6U), /*!< Bit 6. */ + kTRDC_MbcBit7 = (1U << 7U), /*!< Bit 7. */ + kTRDC_MbcBit8 = (1U << 8U), /*!< Bit 8. */ + kTRDC_MbcBit9 = (1U << 9U), /*!< Bit 9. */ + kTRDC_MbcBit10 = (1U << 10U), /*!< Bit 10. */ + kTRDC_MbcBit11 = (1U << 11U), /*!< Bit 11. */ + kTRDC_MbcBit12 = (1U << 12U), /*!< Bit 12. */ + kTRDC_MbcBit13 = (1U << 13U), /*!< Bit 13. */ + kTRDC_MbcBit14 = (1U << 14U), /*!< Bit 14. */ + kTRDC_MbcBit15 = (1U << 15U), /*!< Bit 15. */ + kTRDC_MbcBit16 = (1U << 16U), /*!< Bit 16. */ + kTRDC_MbcBit17 = (1U << 17U), /*!< Bit 17. */ + kTRDC_MbcBit18 = (1U << 18U), /*!< Bit 18. */ + kTRDC_MbcBit19 = (1U << 19U), /*!< Bit 19. */ + kTRDC_MbcBit20 = (1U << 20U), /*!< Bit 20. */ + kTRDC_MbcBit21 = (1U << 21U), /*!< Bit 21. */ + kTRDC_MbcBit22 = (1U << 22U), /*!< Bit 22. */ + kTRDC_MbcBit23 = (1U << 23U), /*!< Bit 23. */ + kTRDC_MbcBit24 = (1U << 24U), /*!< Bit 24. */ + kTRDC_MbcBit25 = (1U << 25U), /*!< Bit 25. */ + kTRDC_MbcBit26 = (1U << 26U), /*!< Bit 26. */ + kTRDC_MbcBit27 = (1U << 27U), /*!< Bit 27. */ + kTRDC_MbcBit28 = (1U << 28U), /*!< Bit 28. */ + kTRDC_MbcBit29 = (1U << 29U), /*!< Bit 29. */ + kTRDC_MbcBit30 = (1U << 30U), /*!< Bit 30. */ + kTRDC_MbcBit31 = (1U << 31U), /*!< Bit 31. */ +}; + +/*! + * @brief The configuration of each memory block per domain per MBC instance. + */ +typedef struct _trdc_mbc_memory_block_config +{ + uint32_t memoryAccessControlSelect : 3U; /*!< Select one of the 8 access control policies for this memory block, for + access cotrol policies see @ref trdc_memory_access_control_config_t. */ + uint32_t nseEnable : 1U; /*!< Enable non-secure accesses and disable secure accesses. */ + uint32_t mbcIdx : 4U; /*!< The index of the MBC for this configuration to take effect. */ + uint32_t domainIdx : 8U; /*!< The index of the domain for this configuration to take effect. */ + uint32_t slaveMemoryIdx : 8U; /*!< The index of the slave memory for this configuration to take effect. */ + uint32_t memoryBlockIdx : 8U; /*!< The index of the memory block for this configuration to take effect. */ +} trdc_mbc_memory_block_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ +/*! + * @brief Initializes the TRDC module. + * + * This function enables the TRDC clock. + * + * @param base TRDC peripheral base address. + */ +void TRDC_Init(TRDC_Type *base); + +/*! + * @brief De-initializes the TRDC module. + * + * This function disables the TRDC clock. + * + * @param base TRDC peripheral base address. + */ +void TRDC_Deinit(TRDC_Type *base); +/*! @} */ + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @name Hardware configuration + * @{ + */ +/*! + * @brief Gets the domain ID of the current bus master. + * + * @param base TRDC peripheral base address. + * @return Domain ID of current bus master. + */ +static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base) +{ + return (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG1 & TRDC_TRDC_HWCFG1_DID_MASK) >> TRDC_TRDC_HWCFG1_DID_SHIFT); +} + +/*! + * @brief Gets the TRDC hardware configuration. + * + * This function gets the TRDC hardware configurations, including number of bus + * masters, number of domains, number of MRCs and number of PACs. + * + * @param base TRDC peripheral base address. + * @param config Pointer to the structure to get the configuration. + */ +void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT +/*! + * @name Master domain assignment + * @{ + */ +/*! + * @brief Sets the TRDC DAC(Domain Assignment Controllers) global valid. + * + * Once enabled, it will remain enabled until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_SetDacGlobalValid(TRDC_Type *base) +{ + TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDM_MASK; +} + +/*! + * @brief Locks the bus master domain assignment register. + * + * This function locks the master domain assignment. After it is locked, the register can't be changed + * until next reset. + * + * @param base TRDC peripheral base address. + * @param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance. + * @param regNum Which register to configure, processor master can have more than one register for the MDAC + configuration. + * @param assignIndex Which assignment register to lock. + */ +static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum) +{ + /* Make sure in the master range. */ + assert((uint32_t)master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)) + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_LK1_MASK; + } + else + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_LK1_MASK; + } +} + +/*! + * @brief Sets the master domain assignment as valid or invalid. + * + * This function sets the master domain assignment as valid or invalid. + * + * @param base TRDC peripheral base address. + * @param master Which master to configure. + * @param regNum Which register to configure, processor master can have more than one register for the MDAC + * configuration. + * @param assignIndex Index for the domain assignment register. + * @param valid True to set valid, false to set invalid. + */ +static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid) +{ + /* Make sure in the master range. */ + assert((uint32_t)master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + if (valid) + { + if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)) + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_VLD_MASK; + } + else + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_VLD_MASK; + } + } + else + { + if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)) + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] &= ~TRDC_MDA_W_DFMT0_VLD_MASK; + } + else + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] &= ~TRDC_MDA_W_DFMT1_VLD_MASK; + } + } +} + +/*! + * @brief Gets the default master domain assignment for the processor bus master. + * + * This function gets the default master domain assignment for the processor bus master. + * It should only be used for the processor bus masters, such as CORE0. This function + * sets the assignment as follows: + * + * @code + * assignment->domainId = 0U; + * assignment->domainIdSelect = kTRDC_DidMda; + * assignment->lock = 0U; + * @endcode + * + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Gets the default master domain assignment for non-processor bus master. + * + * This function gets the default master domain assignment for non-processor bus master. + * It should only be used for the non-processor bus masters, such as DMA. This function + * sets the assignment as follows: + * + * @code + * assignment->domainId = 0U; + * assignment->privilegeAttr = kTRDC_ForceUser; + * assignment->secureAttr = kTRDC_ForceSecure; + * assignment->bypassDomainId = 0U; + * assignment->lock = 0U; + * @endcode + * + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Sets the processor bus master domain assignment. + * + * This function sets the processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for core 0. + * + * @code + * trdc_processor_domain_assignment_t processorAssignment; + * + * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); + * + * processorAssignment.domainId = 0; + * processorAssignment.xxx = xxx; + * TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment); + * @endcode + * + * @param base TRDC peripheral base address. + * @param master Which master to configure, refer to trdc_master_t in processor header file. + * @param regNum Which register to configure, processor master can have more than one register for the MDAC + * configuration. + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + uint8_t regNum, + const trdc_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Sets the non-processor bus master domain assignment. + * + * This function sets the non-processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for DMA0. + * @code + * trdc_non_processor_domain_assignment_t nonProcessorAssignment; + * + * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); + * nonProcessorAssignment.domainId = 1; + * nonProcessorAssignment.xxx = xxx; + * + * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment); + * @endcode + * + * @param base TRDC peripheral base address. + * @param master Which master to configure, refer to trdc_master_t in processor header file. + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + const trdc_non_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Gets the bit map of the bus master(s) that is(are) sourcing a PID register. + * + * This function sets the non-processor master domain assignment as valid. + * + * @param base TRDC peripheral base address. + * @return the bit map of the master(s). Bit 1 sets indicates bus master 1. + */ +static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base) +{ + return ((uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG3 << 32U) | (uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG2; +} + +/*! + * @brief Sets the current Process identifier(PID) for processor core. + * + * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. + * Secure privileged software saves and restores the PID as part of any context switch. + * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register + * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] + * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding + * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information + * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality. + * + * @param base TRDC peripheral base address. + * @param master Which processor master to configure, refer to trdc_master_t in processor header file. + * @param pidConfig Pointer to the configuration structure. + */ +void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @name TZ-M congiguration + * @{ + */ +/*! + * @brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration. + * + * @code + * config->lockSecureVTOR = false; + * config->lockNonsecureVTOR = false; + * config->lockSecureMPU = false; + * config->lockNonsecureMPU = false; + * config->lockSAU = false; + * @endcode + * + * @param domainAssignment Pointer to the configuration structure. + */ +void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration); + +/*! + * @brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration. + * + * Example: Lock the secure and non-secure MPU registers. + * + * @code + * trdc_idau_config_t idauConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&idauConfiguration); + * + * idauConfiguration.lockSecureMPU = true; + * idauConfiguration.lockNonsecureMPU = true; + * TRDC_SetIDAU(TRDC, &idauConfiguration); + * @endcode + * + * @param base TRDC peripheral base address. + * @param domainAssignment Pointer to the configuration structure. + */ +void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW +/*! + * @name FLW(Flash Logical Window) configuration + * @{ + */ +/*! + * @brief Enables/disables the FLW(flash logical window) function. + * + * @param base TRDC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable) +{ + if (enable) + { + TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_V_MASK; + } + else + { + TRDC_FLW_BASE(base)->TRDC_FLW_CTL &= ~TRDC_TRDC_FLW_CTL_V_MASK; + } +} + +/*! + * @brief Locks FLW registers. Once locked the registers can noy be updated until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base) +{ + TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_LK_MASK; +} + +/*! + * @brief Gets the FLW physical base address. + * + * @param base TRDC peripheral base address. + * @return Physical address of the FLW function. + */ +static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base) +{ + return TRDC_FLW_BASE(base)->TRDC_FLW_PBASE; +} + +/*! + * @brief Sets the FLW size. + * + * @param base TRDC peripheral base address. + * @param size Size of the FLW in unit of 32k bytes. + */ +static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size) +{ + TRDC_FLW_BASE(base)->TRDC_FLW_BCNT = size; +} + +/*! + * @brief Gets the default FLW(Flsh Logical Window) configuration. + * + * @code + * config->blockCount = false; + * config->arrayBaseAddr = false; + * config->lock = false; + * config->enable = false; + * @endcode + * + * @param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration); + +/*! + * @brief Sets the FLW function's configuration. + * + * @code + * trdc_flw_config_t flwConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&flwConfiguration); + * + * flwConfiguration.blockCount = 32U; + * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX; + * TRDC_SetIDAU(TRDC, &flwConfiguration); + * @endcode + * + * @param base TRDC peripheral base address. + * @param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +/*! + * @name Domain error check and clear + * @{ + */ +/*! + * @brief Gets and clears the first domain error of the current domain. + * + * This function gets the first access violation information for the current domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * @param base TRDC peripheral base address. + * @param error Pointer to the error information. + * @return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error); + +/*! + * @brief Gets and clears the first domain error of the specific domain. + * + * This function gets the first access violation information for the specific domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * @param base TRDC peripheral base address. + * @param error Pointer to the error information. + * @param domainId The error of which domain to get and clear. + * @return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC +/*! + * @name MRC configuration + * @{ + */ +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @brief Sets the TRDC MRC(Memory Region Checkers) global valid. + * + * Once enabled, it will remain enabled until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base) +{ + TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDR_MASK; +} +#endif + +/*! + * @brief Gets the TRDC MRC(Memory Region Checkers) region number valid. + * + * @param base TRDC peripheral base address. + * @return the region number of the given MRC instance + */ +static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx) +{ + return (uint8_t)((TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBCFG & TRDC_MRC_GLBCFG_NRGNS_MASK) >> + TRDC_MRC_GLBCFG_NRGNS_SHIFT); +} + +/*! + * @brief Sets the memory access configuration for one of the access control register of one MRC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * @code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1); + * @endcode + * + * @param base TRDC peripheral base address. + * @param config Pointer to the configuration structure. + * @param mrcIdx MRC index. + * @param regIdx Register number. + */ +void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mrcIdx, + uint8_t regIdx); + +/*! + * @brief Enables the update of the selected domians. + * + * After the domians' update are enabled, their regions' NSE bits can be set or clear. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param domianMask Bit mask of the domains to be enabled. + * @param enable True to enable, false to disable. + */ +void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable); + +/*! + * @brief Sets the NSE bits of the selected regions for domains. + * + * This function sets the NSE bits for the selected regions for the domains whose update are enabled. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param regionMask Bit mask of the regions whose NSE bits to set. + */ +void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask); + +/*! + * @brief Clears the NSE bits of the selected regions for domains. + * + * This function clears the NSE bits for the selected regions for the domains whose update are enabled. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param regionMask Bit mask of the regions whose NSE bits to clear. + */ +void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask); + +/*! + * @brief Clears the NSE bits for all the regions of the selected domains. + * + * This function clears the NSE bits for all regions of selected domains whose update are enabled. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param domainMask Bit mask of the domians whose NSE bits to clear. + */ +void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask); + +/*! + * @brief Sets the configuration for one of the region descriptor per domain per MRC instnce. + * + * This function sets the configuration for one of the region descriptor, including the start + * and end address of the region, memory access control policy and valid. + * + * @param base TRDC peripheral base address. + * @param config Pointer to region descriptor configuration structure. + */ +void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * @name MBC configuration + * @{ + */ +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @brief Sets the TRDC MBC(Memory Block Checkers) global valid. + * + * Once enabled, it will remain enabled until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base) +{ + TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDB_MASK; +} +#endif + +/*! + * @brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker). + * + * @param base TRDC peripheral base address. + * @param config Pointer to the structure to get the configuration. + * @param mbcIdx MBC number. + * @param slvIdx Slave number. + */ +void TRDC_GetMbcHardwareConfig(TRDC_Type *base, + trdc_slave_memory_hardware_config_t *config, + uint8_t mbcIdx, + uint8_t slvIdx); + +/*! + * @brief Sets the NSR update configuration for one of the MBC instance. + * + * After set the NSE configuration, the configured memory area can be updateby NSE set/clear. + * + * @param base TRDC peripheral base address. + * @param config Pointer to NSE update configuration structure. + * @param mbcIdx MBC index. + */ +void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx); + +/*! + * @brief Sets the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * @param base TRDC peripheral base address. + * @param mbcIdx MBC index. + * @param bitMask Mask of the bits whose NSE bits to set. + */ +void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask); + +/*! + * @brief Clears the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * @param base TRDC peripheral base address. + * @param mbcIdx MBC index. + * @param bitMask Mask of the bits whose NSE bits to clear. + */ +void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask); + +/*! + * @brief Clears all configuration words' NSE bits of the selected domain and memory. + * + * @param base TRDC peripheral base address. + * @param mbcIdx MBC index. + * @param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2. + * @param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits. + */ +void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave); + +/*! + * @brief Sets the memory access configuration for one of the region descriptor of one MBC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * @code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1); + * @endcode + * + * @param base TRDC peripheral base address. + * @param config Pointer to the configuration structure. + * @param mbcIdx MBC index. + * @param rgdIdx Region descriptor number. + */ +void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mbcIdx, + uint8_t rgdIdx); + +/*! + * @brief Sets the configuration for one of the memory block per domain per MBC instnce. + * + * This function sets the configuration for one of the memory block, including the memory access + * control policy and nse enable. + * + * @param base TRDC peripheral base address. + * @param config Pointer to memory block configuration structure. + */ +void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config); +/*! @} */ +#endif + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_TRDC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc_core.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc_core.h new file mode 100644 index 0000000000..8c3e2a9b50 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc_core.h @@ -0,0 +1,489 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_TRDC_CORE_H_ +#define FSL_TRDC_CORE_H_ + +#include "fsl_trdc_soc.h" + +/*! + * @addtogroup trdc_core + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*!@brief TRDC general configuration register definition. */ +typedef struct _TRDC_General_Type +{ + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + __I uint32_t TRDC_HWCFG2; /**< TRDC Hardware Configuration Register 2, offset: 0xF8 */ + __I uint32_t TRDC_HWCFG3; /**< TRDC Hardware Configuration Register 3, offset: 0xFC */ + __I uint8_t DACFG[8]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */ + uint8_t RESERVED_1[184]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ +} TRDC_General_Type; + +/*!@brief TRDC flash logical control register definition. */ +typedef struct _TRDC_FLW_Type +{ + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ +} TRDC_FLW_Type; + +/*!@brief TRDC domain error register definition. */ +typedef struct _TRDC_DomainError_Type +{ + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_4[448]; + struct + { /* offset: 0x400, array step: 0x10 */ + __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */ + __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __O uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ + } MBC_DERR[8]; + struct + { /* offset: 0x480, array step: 0x10 */ + __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */ + __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __O uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ + } MRC_DERR[8]; +} TRDC_DomainError_Type; + +/*!@brief TRDC master domain assignment register definition. */ +typedef struct _TRDC_DomainAssignment_Type +{ + __IO uint32_t PID[8]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_7[224]; + union + { + struct + { /* offset: 0x800, array step: 0x20 */ + __IO uint32_t MDA_W_DFMT0[8]; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: + index*0x20, index2*0x4 */ + } MDA_DFMT0[8]; + struct + { /* offset: 0x800, array step: 0x20 */ + __IO uint32_t MDA_W_DFMT1[1]; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: + index*0x20, index2*0x4 */ + uint8_t RESERVED_0[28]; + } MDA_DFMT1[8]; + }; +} TRDC_DomainAssignment_Type; + +/*!@brief TRDC MBC control register definition. */ +typedef struct _TRDC_MBC_Type +{ + __I uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: + index*0x2000, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ + __O uint32_t + MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, + index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10180, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_0[72]; + __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10380, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_1[72]; + __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10580, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_2[72]; + __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10780, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_3[72]; + __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10980, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_4[72]; + __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_5[72]; + __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_7[72]; + __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_8[72]; + __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11180, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array + step: index*0x2000, index2*0x4 */ + + __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11380, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_9[72]; + __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11580, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_10[72]; + __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11780, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_11[72]; + __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11980, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_12[72]; + __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_13[72]; + __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_14[72]; + __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_15[8]; +} TRDC_MBC_Type; + +/*!@brief TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word] */ +typedef struct _TRDC_MRC_Type +{ + __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000 */ + uint8_t RESERVED_0[12]; + __IO uint32_t + MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000 */ + __O uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000 */ + __O uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000 */ + __O uint32_t + MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000 */ + __IO uint32_t + MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4 */ + __IO uint32_t MRC_DOM0_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14040, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000 */ + uint8_t RESERVED_1[124]; + __IO uint32_t MRC_DOM1_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14140, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000 */ + uint8_t RESERVED_2[124]; + __IO uint32_t MRC_DOM2_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14240, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000 */ + uint8_t RESERVED_3[124]; + __IO uint32_t MRC_DOM3_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14340, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000 */ + uint8_t RESERVED_4[124]; + __IO uint32_t MRC_DOM4_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14440, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000 */ + uint8_t RESERVED_5[124]; + __IO uint32_t MRC_DOM5_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14540, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000 */ + uint8_t RESERVED_6[124]; + __IO uint32_t MRC_DOM6_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14640, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000 */ + uint8_t RESERVED_7[124]; + __IO uint32_t MRC_DOM7_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14740, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000 */ + uint8_t RESERVED_8[124]; + __IO uint32_t MRC_DOM8_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14840, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000 */ + uint8_t RESERVED_9[124]; + __IO uint32_t MRC_DOM9_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14940, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000 */ + uint8_t RESERVED_10[124]; + __IO uint32_t MRC_DOM10_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000 */ + uint8_t RESERVED_11[124]; + __IO uint32_t MRC_DOM11_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000 */ + uint8_t RESERVED_12[124]; + __IO uint32_t MRC_DOM12_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000 */ + uint8_t RESERVED_13[124]; + __IO uint32_t MRC_DOM13_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000 */ + uint8_t RESERVED_14[124]; + __IO uint32_t MRC_DOM14_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000 */ + uint8_t RESERVED_15[124]; + __IO uint32_t MRC_DOM15_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000 */ +} TRDC_MRC_Type; + +/*!@brief TRDC base address convert macro */ +#define TRDC_GENERAL_BASE(base) ((TRDC_General_Type *)((base))) +#define TRDC_FLW_BASE(base) ((TRDC_FLW_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_FLW_OFFSET))) +#define TRDC_DOMAIN_ERROR_BASE(base) ((TRDC_DomainError_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_DOMAIN_ERROR_OFFSET))) +#define TRDC_DOMAIN_ASSIGNMENT_BASE(base) \ + ((TRDC_DomainAssignment_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_DOMAIN_ASSIGNMENT_OFFSET))) +#define TRDC_MBC_BASE(base, instance) \ + ((TRDC_MBC_Type *)((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_MBC_OFFSET(base) + (instance) * (uint32_t)TRDC_MBC_ARRAY_STEP)) +#define TRDC_MRC_BASE(base, instance) \ + ((TRDC_MRC_Type *)((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_MRC_OFFSET(base) + (instance) * (uint32_t)TRDC_MRC_ARRAY_STEP)) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* FSL_TRDC_CORE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc_soc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc_soc.h new file mode 100644 index 0000000000..8c06108353 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trdc_soc.h @@ -0,0 +1,67 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_TRDC_SOC_H_ +#define _FSL_TRDC_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup trdc_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + /* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trdc_soc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*!@brief TRDC base table */ +#define TRDC_BASE_PTRS \ + { \ + TRDC \ + } +/* @} */ + +#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT +#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL +#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0 + +/*!@brief TRDC feature */ +#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1 + +/*!@brief TRDC base address convert macro */ +#define TRDC_MBC_COUNT 1 +#define TRDC_MBC_OFFSET(x) 0x0 +#define TRDC_MBC_ARRAY_STEP 0U + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_TRDC_SOC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trng.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trng.c deleted file mode 100644 index ffef789d94..0000000000 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trng.c +++ /dev/null @@ -1,2026 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017, 2020-2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_trng.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.trng" -#endif - -/* Default values for user configuration structure.*/ -#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ - defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES) || defined(KW37A4_SERIES) || defined(KW37Z4_SERIES) || \ - defined(KW38A4_SERIES) || defined(KW38Z4_SERIES) || defined(KW39A4_SERIES) || defined(KW35Z4_SERIES) || \ - defined(KW36A4_SERIES) || defined(KW35A4_SERIES) || defined(KW34A4_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 -#elif (defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ - defined(KL82Z7_SERIES) || defined(K32L2A41A_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 -#elif ( \ - defined(K81F25615_SERIES) || defined(K32L3A60_cm4_SERIES) || defined(K32L3A60_cm0plus_SERIES) || \ - defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN548_cm33_core0_SERIES) || \ - defined(MCXN548_cm33_core1_SERIES) || defined(MCXN945_cm33_core0_SERIES) || defined(MCXN945_cm33_core1_SERIES) || \ - defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \ - defined(MCXN947_cm33_core1_SERIES) || defined(MCXN948_cm33_core0_SERIES) || defined(MCXN948_cm33_core1_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 -#else -/* Default value for the TRNG user configuration structure can be optionally - defined by device specific preprocessor macros. */ -#if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_OSC_DIV) && \ - (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_OSC_DIV > 0) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_OSC_DIV_VALUE) -#else -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0 -#endif -#endif - -#if (defined(RW610_SERIES) || defined(RW612_SERIES)) - -/* RW610 specific settings for the TRNG */ -#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 -#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 -#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 256 -#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 -#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 -#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34 - -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 171 -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 86) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 63 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 56) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 38 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 38) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 26 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 26) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912 -#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467) - -#else - -#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 -#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 -#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 512 -#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 -#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 -#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 32 - -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 317 -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 122) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 107 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 80) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 62 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 55) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 39 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 39) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 26 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 26) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 18 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 18) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 17 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 17) -#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 1600 -#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 570) - -#endif - -#if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM) && \ - (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM > 0) -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM_VALUE) -#else -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 30000 -#endif - -#if defined(FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM) && \ - (FSL_FEATURE_TRNG_FORCE_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM > 0) -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM (FSL_FEATURE_TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM_VALUE) -#else -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600 -#endif - -/*! @brief TRNG work mode */ -typedef enum _trng_work_mode -{ - kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ - kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ -} trng_work_mode_t; - -/*! @brief TRNG statistical check type*/ -typedef enum _trng_statistical_check -{ - kTRNG_StatisticalCheckMonobit = - 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */ - kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during - entropy generation. */ - kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */ - kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */ -} trng_statistical_check_t; - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ -/*! - * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW) - * - * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation, - * the RTY_CT value indicates the number of times a retry should occur before - * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This - * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing - * the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */ -#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT) - -/*! @brief Set the RTY_CT field to a new value. */ -#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCML - RNG Statistical Check Monobit Limit Register - ******************************************************************************/ -/*! - * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW) - * - * Reset value: 0x010C0568U - * - * The RNG Statistical Check Monobit Limit Register defines the allowable - * maximum and minimum number of ones/zero detected during entropy generation. To pass - * the test, the number of ones/zeroes generated must be less than the programmed - * maximum value, and the number of ones/zeroes generated must be greater than - * (maximum - range). If this test fails, the Retry Counter in SCMISC will be - * decremented, and a retry will occur if the Retry Count has not reached zero. If - * the Retry Count has reached zero, an error will be generated. Note that this - * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, - * this offset is used as SCMC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCML register - */ -/*@{*/ -#define TRNG_SCML_REG(base) ((base)->SCML) -#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) -#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) -#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW) - * - * Monobit Maximum Limit. Defines the maximum allowable count taken during - * entropy generation. The number of ones/zeroes detected during entropy generation - * must be less than MONO_MAX, else a retry or error will occur. This register is - * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */ -#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT) - -/*! @brief Set the MONO_MAX field to a new value. */ -#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW) - * - * Monobit Range. The number of ones/zeroes detected during entropy generation - * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur. - * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */ -#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT) - -/*! @brief Set the MONO_RNG field to a new value. */ -#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW) - * - * Reset value: 0x00B20195U - * - * The RNG Statistical Check Run Length 1 Limit Register defines the allowable - * maximum and minimum number of runs of length 1 detected during entropy - * generation. To pass the test, the number of runs of length 1 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 1 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR1L register - */ -/*@{*/ -#define TRNG_SCR1L_REG(base) ((base)->SCR1L) -#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base)) -#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) -#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW) - * - * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 1 detected during entropy generation must be less than RUN1_MAX, else a - * retry or error will occur. This register is cleared to 01E5h (decimal 485) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */ -#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT) - -/*! @brief Set the RUN1_MAX field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW) - * - * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1) - * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a - * retry or error will occur. This register is cleared to 0102h (decimal 258) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */ -#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT) - -/*! @brief Set the RUN1_RNG field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW) - * - * Reset value: 0x007A00DCU - * - * The RNG Statistical Check Run Length 2 Limit Register defines the allowable - * maximum and minimum number of runs of length 2 detected during entropy - * generation. To pass the test, the number of runs of length 2 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 2 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR2L register - */ -/*@{*/ -#define TRNG_SCR2L_REG(base) ((base)->SCR2L) -#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base)) -#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) -#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR2L bitfields - */ - -/*! - * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW) - * - * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 2 detected during entropy generation must be less than RUN2_MAX, else a - * retry or error will occur. This register is cleared to 00DCh (decimal 220) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */ -#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT) - -/*! @brief Set the RUN2_MAX field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW) - * - * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1) - * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a - * retry or error will occur. This register is cleared to 007Ah (decimal 122) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */ -#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT) - -/*! @brief Set the RUN2_RNG field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW) - * - * Reset value: 0x0058007DU - * - * The RNG Statistical Check Run Length 3 Limit Register defines the allowable - * maximum and minimum number of runs of length 3 detected during entropy - * generation. To pass the test, the number of runs of length 3 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 3 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR3L register - */ -/*@{*/ -#define TRNG_SCR3L_REG(base) ((base)->SCR3L) -#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base)) -#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) -#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR3L bitfields - */ - -/*! - * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW) - * - * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 3 detected during entropy generation must be less than RUN3_MAX, else a - * retry or error will occur. This register is cleared to 007Dh (decimal 125) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */ -#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT) - -/*! @brief Set the RUN3_MAX field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW) - * - * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1) - * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a - * retry or error will occur. This register is cleared to 0058h (decimal 88) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */ -#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT) - -/*! @brief Set the RUN3_RNG field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register - ******************************************************************************/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) -/*! - * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW) - * - * Reset value: 0x0040004BU - * - * The RNG Statistical Check Run Length 4 Limit Register defines the allowable - * maximum and minimum number of runs of length 4 detected during entropy - * generation. To pass the test, the number of runs of length 4 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 4 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR4L register - */ -/*@{*/ -#define TRNG_SCR4L_REG(base) ((base)->SCR4L) -#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base)) -#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) -#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR4L bitfields - */ - -/*! - * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW) - * - * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 4 detected during entropy generation must be less than RUN4_MAX, else a - * retry or error will occur. This register is cleared to 004Bh (decimal 75) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */ -#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT) - -/*! @brief Set the RUN4_MAX field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW) - * - * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1) - * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a - * retry or error will occur. This register is cleared to 0040h (decimal 64) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */ -#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT) - -/*! @brief Set the RUN4_RNG field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L */ - -/******************************************************************************* - * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register - ******************************************************************************/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) -/*! - * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 5 Limit Register defines the allowable - * maximum and minimum number of runs of length 5 detected during entropy - * generation. To pass the test, the number of runs of length 5 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 5 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR5L register - */ -/*@{*/ -#define TRNG_SCR5L_REG(base) ((base)->SCR5L) -#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base)) -#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) -#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR5L bitfields - */ - -/*! - * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW) - * - * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 5 detected during entropy generation must be less than RUN5_MAX, else a - * retry or error will occur. This register is cleared to 002Fh (decimal 47) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */ -#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT) - -/*! @brief Set the RUN5_MAX field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW) - * - * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1) - * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a - * retry or error will occur. This register is cleared to 002Eh (decimal 46) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */ -#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT) - -/*! @brief Set the RUN5_RNG field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L */ - -/******************************************************************************* - * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register - ******************************************************************************/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) -/*! - * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable - * maximum and minimum number of runs of length 6 or more detected during entropy - * generation. To pass the test, the number of runs of length 6 or more (for - * samples of both 0 and 1) must be less than the programmed maximum value, and the - * number of runs of length 6 or more must be greater than (maximum - range). If - * this test fails, the Retry Counter in SCMISC will be decremented, and a retry - * will occur if the Retry Count has not reached zero. If the Retry Count has - * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is - * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is - * used as SCR6PC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR6PL register - */ -/*@{*/ -#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) -#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base)) -#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) -#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR6PL bitfields - */ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW) - * - * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6 - * or more (for both 0 and 1) detected during entropy generation. The number of - * runs of length 6 or more detected during entropy generation must be less than - * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh - * (decimal 47) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */ -#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT) - -/*! @brief Set the RUN6P_MAX field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW) - * - * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and - * 1) detected during entropy generation must be greater than RUN6P_MAX - - * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh - * (decimal 46) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */ -#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT) - -/*! @brief Set the RUN6P_RNG field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L */ - -/******************************************************************************* - * TRNG_PKRMAX - RNG Poker Maximum Limit Register - ******************************************************************************/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) && FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) -/*! - * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW) - * - * Reset value: 0x00006920U - * - * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during - * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is - * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used - * as the PKRSQ readback register. - */ -/*! - * @name Constants and macros for entire TRNG_PKRMAX register - */ -/*@{*/ -#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX) -#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base)) -#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) -#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRMAX bitfields - */ - -/*! - * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW) - * - * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is - * run which requires a maximum and minimum limit. The maximum allowable result is - * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if - * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by - * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers - * combined are used to define the minimum allowable Poker result, which is PKR_MAX - - * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used - * to read the Poker Test Square Calculation result in register PKRSQ, as defined - * in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */ -#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT) - -/*! @brief Set the PKR_MAX field to a new value. */ -#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \ - (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX */ - -/******************************************************************************* - * TRNG_PKRRNG - RNG Poker Range Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRRNG - RNG Poker Range Register (RW) - * - * Reset value: 0x000009A3U - * - * The RNG Poker Range Register defines the difference between the TRNG Poker - * Maximum Limit and the minimum limit. These limits are used during the TRNG - * Statistical Check Poker Test. - */ -/*! - * @name Constants and macros for entire TRNG_PKRRNG register - */ -/*@{*/ -#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG) -#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base)) -#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value)) -#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRRNG bitfields - */ - -/*! - * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW) - * - * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which - * requires a maximum and minimum limit. The maximum is programmed in the - * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG - * value from the programmed maximum value. This field is writable only if - * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is - * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that - * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */ -#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT) - -/*! @brief Set the PKR_RNG field to a new value. */ -#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \ - (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW) - * - * Reset value: 0x00006400U - * - * The RNG Frequency Count Maximum Limit Register defines the maximum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is greater than this programmed maximum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note - * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as FRQCNT readback register. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMAX register - */ -/*@{*/ -#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX) -#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base)) -#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value)) -#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMAX bitfields - */ - -/*! - * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW) - * - * Frequency Counter Maximum Limit. Defines the maximum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1. - * Note that if MCTL[PRGM] bit is 0, this register address is used to read the - * Frequency Count result in register FRQCNT, as defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */ -#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT) - -/*! @brief Set the FRQ_MAX field to a new value. */ -#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \ - (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW) - * - * Reset value: 0x00000640U - * - * The RNG Frequency Count Minimum Limit Register defines the minimum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is less than this programmed minimum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMIN register - */ -/*@{*/ -#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN) -#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base)) -#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value)) -#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMIN bitfields - */ - -/*! - * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW) - * - * Frequency Count Minimum Limit. Defines the minimum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64 - * by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */ -#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT) - -/*! @brief Set the FRQ_MIN field to a new value. */ -#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \ - (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_MCTL - RNG Miscellaneous Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW) - * - * Reset value: 0x00012001U - * - * This register is intended to be used for programming, configuring and testing - * the RNG. It is the main register to read/write, in order to enable Entropy - * generation, to stop entropy generation and to block access to entropy registers. - * This is done via the special TRNG_ACC and PRGM bits below. The RNG - * Miscellaneous Control Register is a read/write register used to control the RNG's True - * Random Number Generator (TRNG) access, operation and test. Note that in many - * cases two RNG registers share the same address, and a particular register at the - * shared address is selected based upon the value in the PRGM field of the MCTL - * register. - */ -/*! - * @name Constants and macros for entire TRNG_MCTL register - */ -/*@{*/ -#define TRNG_MCTL_REG(base) ((base)->MCTL) -#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base)) -#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) -#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW) - * - * Force System Clock. If set, the system clock is used to operate the TRNG, - * instead of the ring oscillator. This is for test use only, and indeterminate - * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is - * being written to 1 simultaneously to writing this bit. This bit is cleared by - * writing the RST_DEF bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */ -#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT) - -/*! @brief Set the FOR_SCLK field to a new value. */ -#define TRNG_WR_MCTL_FOR_SCLK(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW) - * - * Oscillator Divide. Determines the amount of dividing done to the ring - * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is - * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This - * field is cleared to 00 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use ring oscillator with no divide - * - 0b01 - use ring oscillator divided-by-2 - * - 0b10 - use ring oscillator divided-by-4 - * - 0b11 - use ring oscillator divided-by-8 - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */ -#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT) - -/*! @brief Set the OSC_DIV field to a new value. */ -#define TRNG_WR_MCTL_OSC_DIV(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value))) -/*@}*/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) -/*! - * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW) - * - * Sample Mode. Determines the method of sampling the ring oscillator while - * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM - * bit is being written to 1 simultaneously with writing this field. This field - * is cleared to 01 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical - * Checker - * - 0b01 - use raw data into both Entropy shifter and Statistical Checker - * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into - * Statistical Checker - * - 0b11 - reserved. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */ -#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT) - -/*! @brief Set the SAMP_MODE field to a new value. */ -#define TRNG_WR_MCTL_SAMP_MODE(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE */ - -/*! - * @name Register TRNG_MCTL, field PRGM[16] (RW) - * - * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode, - * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is - * in Program Mode. Note that different RNG registers are accessible at the same - * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG - * register descriptions. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_PRGM field. */ -#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT) - -/*! @brief Set the PRGM field to a new value. */ -#define TRNG_WR_MCTL_PRGM(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field RST_DEF[6] (WO) - * - * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and - * bits within registers, to their default state. This bit is writable only if PRGM - * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this - * bit. Reading this bit always produces a 0. - */ -/*@{*/ -/*! @brief Set the RST_DEF field to a new value. */ -#define TRNG_WR_MCTL_RST_DEF(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value))) -/*@}*/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) -/*! - * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW) - * - * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy - * value that can be read via the ENT0-ENT15 registers. The Entropy value may be - * read once the ENT VAL bit is asserted. Also see ENTa register descriptions - * (For a = 0 to 15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */ -#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT) - -/*! @brief Set the TRNG_ACC field to a new value. */ -#define TRNG_WR_MCTL_TRNG_ACC(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ - -/*! - * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO) - * - * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before - * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG - * free-running ring oscillator whenever new entropy is being generated and turns off the - * ring oscillator when entropy generation is complete. If the RNG clock is - * stopped while the TRNG ring oscillator is running, the oscillator will continue - * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG - * ring oscillator is not running. and therefore it is ok to stop the RNG clock. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */ -#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ENT_VAL[10] (RO) - * - * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then - * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0 - * through ENT14 should be read before reading ENT15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */ -#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ERR[12] (W1C) - * - * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear - * errors. Writing 0 has no effect. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ERR field. */ -#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT) - -/*! @brief Set the ERR field to a new value. */ -#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SDCTL - RNG Seed Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_SDCTL - RNG Seed Control Register (RW) - * - * Reset value: 0x0C8009C4U - * - * The RNG Seed Control Register contains two fields. One field defines the - * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field - * indicates the number of samples that will taken during each TRNG Entropy - * generation (SAMP_SIZE). - */ -/*! - * @name Constants and macros for entire TRNG_SDCTL register - */ -/*@{*/ -#define TRNG_SDCTL_REG(base) ((base)->SDCTL) -#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base)) -#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) -#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SDCTL bitfields - */ - -/*! - * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW) - * - * Sample Size. Defines the total number of Entropy samples that will be taken - * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h - * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */ -#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT) - -/*! @brief Set the SAMP_SIZE field to a new value. */ -#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \ - (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value))) -/*@}*/ - -/*! - * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW) - * - * Entropy Delay. Defines the length (in system clocks) of each Entropy sample - * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read - * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */ -#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT) - -/*! @brief Set the ENT_DLY field to a new value. */ -#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SBLIM - RNG Sparse Bit Limit Register - ******************************************************************************/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM > 0)) -/*! - * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW) - * - * Reset value: 0x0000003FU - * - * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is - * selected during Entropy Generation. It defines the maximum number of consecutive Von - * Neumann samples which may be discarded before an error is generated. Note - * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as TOTSAM readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SBLIM register - */ -/*@{*/ -#define TRNG_SBLIM_REG(base) ((base)->SBLIM) -#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base)) -#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value)) -#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SBLIM bitfields - */ - -/*! - * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW) - * - * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE], - * samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. The Sparse Bit Limit defines the maximum number of - * consecutive samples that may be discarded before an error is generated. This field - * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by - * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this - * register address is used to read the Total Samples count in register TOTSAM, as - * defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */ -#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT) - -/*! @brief Set the SB_LIM field to a new value. */ -#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value))) -/*@}*/ -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM */ - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW) - * - * Reset value: 0x0001001FU - * - * The RNG Statistical Check Miscellaneous Register contains the Long Run - * Maximum Limit value and the Retry Count value. This register is accessible only when - * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot - * be written. - */ -/*! - * @name Constants and macros for entire TRNG_SCMISC register - */ -/*@{*/ -#define TRNG_SCMISC_REG(base) ((base)->SCMISC) -#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base)) -#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value)) -#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCMISC bitfields - */ - -/*! - * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW) - * - * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive - * samples of all 1, or all 0, that is allowed during the Entropy generation. - * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes - * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */ -#define TRNG_RD_SCMISC_LRUN_MAX(base) \ - ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT) - -/*! @brief Set the LRUN_MAX field to a new value. */ -#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \ - (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_ENT - RNG TRNG Entropy Read Register - ******************************************************************************/ - -/*! - * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO) - * - * Reset value: 0x00000000U - * - * The RNG TRNG can be programmed to generate an entropy value that is readable - * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the - * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this - * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value. - * Note that once ENT15 is read, the entropy value will be cleared and a new - * value will begin generation, so it is important that ENT15 be read last. These - * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1 - * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read. - */ -/*! - * @name Constants and macros for entire TRNG_ENT register - */ -/*@{*/ -#define TRNG_ENT_REG(base, index) ((base)->ENT[index]) -#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index)) -/*@}*/ - -/******************************************************************************* - * TRNG_SEC_CFG - RNG Security Configuration Register - ******************************************************************************/ - -/*! - * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW) - * - * Reset value: 0x00000000U - * - * The RNG Security Configuration Register is a read/write register used to - * control the test mode, programmability and state modes of the RNG. Many bits are - * place holders for this version. More configurability will be added here. Clears - * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0 - * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use - * these registers, if hard coded. - */ -/*! - * @name Constants and macros for entire TRNG_SEC_CFG register - */ -/*@{*/ -#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG) -#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base)) -#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value)) -#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW) - * - * If set the TRNG registers cannot be programmed. That is, regardless of the - * TRNG access mode in the SA-TRNG Miscellaneous Control Register. - * - * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous - * Control Register's access mode bit. - * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents - * TRNG register programming. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */ -#define TRNG_RD_SEC_CFG_NO_PRGM(base) \ - ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT) - -/*! @brief Set the NO_PRGM field to a new value. */ -#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \ - (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value))) -/*@}*/ - -/*! @brief Array to map TRNG instance number to base pointer. */ -static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clock array name */ -static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_TRNG_HAS_RSTCTL) && (FSL_FEATURE_TRNG_HAS_RSTCTL > 0) -static const reset_ip_name_t trng_reset = TRNG_RSTS; -#endif /* FSL_FEATURE_TRNG_HAS_RSTCTL */ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig); -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count); -static status_t trng_SetMonobitLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetRunBit1Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetRunBit2Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetRunBit3Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetRunBit4Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetRunBit5Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetRunBit6Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetPokerMaxLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum); -static status_t trng_SetFrequencyCountMaxLimit(TRNG_Type *base, uint32_t limit_minimum, uint32_t limit_maximum); -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit); -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index); -static uint32_t trng_GetInstance(TRNG_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t trng_GetInstance(TRNG_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++) - { - if (s_trngBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_trngBases)); - - return instance; -} - -/*FUNCTION********************************************************************* - * - * Function Name : TRNG_InitUserConfigDefault - * Description : Initializes user configuration structure to default settings. - * - *END*************************************************************************/ -/*! - * brief Initializes the user configuration structure to default values. - * - * This function initializes the configuration structure to default values. The default - * values are as follows. - * code - * userConfig->lock = 0; - * userConfig->clockMode = kTRNG_ClockModeRingOscillator; - * userConfig->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. - * userConfig->sampleMode = kTRNG_SampleModeRaw; - * userConfig->entropyDelay = 3200; - * userConfig->sampleSize = 2500; - * userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - * userConfig->retryCount = 63; - * userConfig->longRunMaxLimit = 34; - * userConfig->monobitLimit.maximum = 1384; - * userConfig->monobitLimit.minimum = 1116; - * userConfig->runBit1Limit.maximum = 405; - * userConfig->runBit1Limit.minimum = 227; - * userConfig->runBit2Limit.maximum = 220; - * userConfig->runBit2Limit.minimum = 98; - * userConfig->runBit3Limit.maximum = 125; - * userConfig->runBit3Limit.minimum = 37; - * userConfig->runBit4Limit.maximum = 75; - * userConfig->runBit4Limit.minimum = 11; - * userConfig->runBit5Limit.maximum = 47; - * userConfig->runBit5Limit.minimum = 1; - * userConfig->runBit6PlusLimit.maximum = 47; - * userConfig->runBit6PlusLimit.minimum = 1; - * userConfig->pokerLimit.maximum = 26912; - * userConfig->pokerLimit.minimum = 24445; - * userConfig->frequencyCountLimit.maximum = 25600; - * userConfig->frequencyCountLimit.minimum = 1600; - * endcode - * - * param userConfig User configuration structure. - * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) -{ - status_t result; - - if (userConfig != NULL) - { - /* Initializes the configuration structure to default values. */ - - /* Lock programmability of TRNG registers. */ - userConfig->lock = (bool)TRNG_USER_CONFIG_DEFAULT_LOCK; - /* Clock settings */ - userConfig->clockMode = kTRNG_ClockModeRingOscillator; - userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; - userConfig->sampleMode = kTRNG_SampleModeRaw; -#if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0) - userConfig->oscillatorMode = kTRNG_SingleOscillatorModeOsc1; - userConfig->ringOsc2Div = kTRNG_RingOscDiv4; -#endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */ - /* Seed control*/ - userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; - userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; - userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - - /* Statistical Check Parameters.*/ - userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; - userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; - - userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; - userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; - userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; - userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; - userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; - userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; - userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; - userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; - userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; - userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; - userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; - userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; - userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; - userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; - /* Limits for statistical check of "Poker Test". */ - userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; - userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; - /* Limits for statistical check of entropy sample frequency count. */ - userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; - userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; - - result = kStatus_Success; - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -/*! - * @brief Sets the TRNG retry count. - * - * This function sets the retry counter which defines the number of times a - * statistical check may fails during the TRNG Entropy Generation before - * generating an error. - */ -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) -{ - status_t status; - - if ((retry_count >= 1u) && (retry_count <= 15u)) - { - /* Set retry count.*/ - TRNG_WR_SCMISC_RTY_CT(base, retry_count); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Check Monobit Limit Register . - * - * This function set register TRNG_SCML - Statistical Check Monobit Limit Register - */ -static status_t trng_SetMonobitLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0xffffu) && (limit_maximum <= 0xffffu)) - - { - /* Set TRNG_SCML register */ - TRNG_WR_SCML_MONO_MAX(base, limit_maximum); - TRNG_WR_SCML_MONO_RNG(base, range); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Statistical Check Run Length 1 Limit Register . - * - * This function set register TRNG_SCR1L - Statistical Check Run Length 1 Limit Register - */ -static status_t trng_SetRunBit1Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0x7fffu) && (limit_maximum <= 0x7fffu)) - { - /* Set TRNG_SCR1L register */ - TRNG_WR_SCR1L_RUN1_MAX(base, limit_maximum); - TRNG_WR_SCR1L_RUN1_RNG(base, range); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Statistical Check Run Length 2 Limit Register . - * - * This function set register TRNG_SCR2L - Statistical Check Run Length 2 Limit Register - */ -static status_t trng_SetRunBit2Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0x3fffu) && (limit_maximum <= 0x3fffu)) - { - /* Set TRNG_SCR2L register */ - TRNG_WR_SCR2L_RUN2_MAX(base, limit_maximum); - TRNG_WR_SCR2L_RUN2_RNG(base, range); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Statistical Check Run Length 3 Limit Register . - * - * This function set register TRNG_SCR3L - Statistical Check Run Length 3 Limit Register - */ -static status_t trng_SetRunBit3Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0x1fffu) && (limit_maximum <= 0x1fffu)) - { - /* Set TRNG_SCR3L register */ - TRNG_WR_SCR3L_RUN3_MAX(base, limit_maximum); - TRNG_WR_SCR3L_RUN3_RNG(base, range); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Statistical Check Run Length 4 Limit Register . - * This function set register TRNG_SCR4L - Statistical Check Run Length 4 Limit Register - */ -static status_t trng_SetRunBit4Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0xfffu) && (limit_maximum <= 0xfffu)) - { -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L) - /* Set TRNG_SCR4L register */ - TRNG_WR_SCR4L_RUN4_MAX(base, limit_maximum); - TRNG_WR_SCR4L_RUN4_RNG(base, range); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L */ - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Statistical Check Run Length 5 Limit Register . - * This function set register TRNG_SCR5L - Statistical Check Run Length 5 Limit Register - */ -static status_t trng_SetRunBit5Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0x7ffu) && (limit_maximum <= 0x7ffu)) - { -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L) - /* Set TRNG_SCR5L register */ - TRNG_WR_SCR5L_RUN5_MAX(base, limit_maximum); - TRNG_WR_SCR5L_RUN5_RNG(base, range); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L */ - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Statistical Check Run Length 6 Limit Register . - * This function set register TRNG_SCR6L - Statistical Check Run Length 6 Limit Register - */ -static status_t trng_SetRunBit6Limit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0x7ffu) && (limit_maximum <= 0x7ffu)) - { -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) && FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L) - /* Set TRNG_SCR6L register */ - TRNG_WR_SCR6PL_RUN6P_MAX(base, limit_maximum); - TRNG_WR_SCR6PL_RUN6P_RNG(base, range); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L */ - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Poker Maximum Limit Register. - * This function set register TRNG_PKRMAX - Poker Maximum Limit Register - */ -static status_t trng_SetPokerMaxLimit(TRNG_Type *base, uint32_t range, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((range <= 0xffffu) && (limit_maximum <= 0xffffffu)) - { -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) && FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX) - /* Set TRNG_PKRMAX register */ - TRNG_WR_PKRMAX_PKR_MAX(base, limit_maximum); - TRNG_WR_PKRRNG_PKR_RNG(base, range); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX */ - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical Frequency Count Maximum Limit Register. - * This function set register TRNG_FRQMAX - Frequency Count Maximum Limit Register - */ -static status_t trng_SetFrequencyCountMaxLimit(TRNG_Type *base, uint32_t limit_minimum, uint32_t limit_maximum) -{ - status_t status; - - /* Check input parameters*/ - if ((limit_minimum <= 0x3fffffu) && (limit_maximum <= 0x3fffffu)) - { - /* Set FRQMAX register */ - TRNG_WR_FRQMAX_FRQ_MAX(base, limit_maximum); - TRNG_WR_FRQMIN_FRQ_MIN(base, limit_minimum); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical check limits. - * - * This function is used to set minimum and maximum limits of statistical checks. - * - */ -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit) -{ - uint32_t range; - status_t status = kStatus_Success; - - if ((NULL != limit) && (limit->maximum > limit->minimum)) - { - range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ - - if (statistical_check == kTRNG_StatisticalCheckMonobit) /* Allowable maximum and minimum number of ones/zero - detected during entropy generation. */ - { - status = trng_SetMonobitLimit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckRunBit1) /* Allowable maximum and minimum number of runs of - length 1 detected during entropy generation. */ - { - status = trng_SetRunBit1Limit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckRunBit2) /* Allowable maximum and minimum number of runs of - length 2 detected during entropy generation. */ - { - status = trng_SetRunBit2Limit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckRunBit3) /* Allowable maximum and minimum number of runs of - length 3 detected during entropy generation. */ - { - status = trng_SetRunBit3Limit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckRunBit4) /* Allowable maximum and minimum number of runs of - length 4 detected during entropy generation. */ - { - status = trng_SetRunBit4Limit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckRunBit5) /* Allowable maximum and minimum number of runs of - length 5 detected during entropy generation. */ - { - status = trng_SetRunBit5Limit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckRunBit6Plus) /* Allowable maximum and minimum number of - length 6 or more detected during entropy - generation */ - { - status = trng_SetRunBit6Limit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckPoker) /* Allowable maximum and minimum limit of "Poker - Test" detected during entropy generation . */ - { - status = trng_SetPokerMaxLimit(base, range, limit->maximum); - } - else if (statistical_check == kTRNG_StatisticalCheckFrequencyCount) /* Allowable maximum and minimum limit of - entropy sample frquency count during - entropy generation . */ - { - status = trng_SetFrequencyCountMaxLimit(base, limit->minimum, limit->maximum); - } - else - { - status = kStatus_InvalidArgument; - } - } - - return status; -} - -/*FUNCTION********************************************************************* - * - * Function Name : trng_ApplyUserConfig - * Description : Apply user configuration settings to TRNG module. - * - *END*************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t status; - - /* Set retry count */ - status = trng_SetRetryCount(base, userConfig->retryCount); - - /* Set statistical check limit */ - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, &userConfig->runBit6PlusLimit); - } - - if (kStatus_Success == status) - { - status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit); - } - - if (kStatus_Success == status) - { - status = - trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, &userConfig->frequencyCountLimit); - } - - if (kStatus_Success == status) - { -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE) - /* Set clock mode used to operate TRNG */ - TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE */ - /* Set ring oscillator divider used by TRNG */ - TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); -#if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0) - base->OSC2_CTL |= TRNG_OSC2_CTL_TRNG_ENT_CTL(userConfig->oscillatorMode); - base->OSC2_CTL |= TRNG_OSC2_CTL_OSC2_DIV(userConfig->ringOsc2Div); -#endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */ -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) && FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE) - /* Set sample mode of the TRNG ring oscillator. */ - TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE */ - /* Set length of each Entropy sample taken */ - TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); - /* Set number of entropy samples that will be taken during Entropy generation */ - TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM > 0)) - /* Set Sparse Bit Limit */ - TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); -#endif /* FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM */ - TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); - } - - return status; -} - -/*! - * @brief Gets a entry data from the TRNG. - * - * This function gets an entropy data from TRNG. - * Entropy data is spread over TRNG_ENT_COUNT registers. - * Read register number is defined by index parameter. - */ -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) -{ - uint32_t data; - - index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/ - - data = TRNG_RD_ENT(base, index); - - if (index == (TRNG_ENT_COUNT - 1u)) - { - /* Dummy read. Defect workaround. - * TRNG could not clear ENT_VAL flag automatically, application - * had to do a dummy reading operation for anyone TRNG register - * to clear it firstly, then to read the RTENT0 to RTENT15 again */ - index = TRNG_RD_ENT(base, 0); - } - - return data; -} - -/*! - * brief Initializes the TRNG. - * - * This function initializes the TRNG. - * When called, the TRNG entropy generation starts immediately. - * - * param base TRNG base address - * param userConfig Pointer to the initialization configuration structure. - * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t result; - - /* Check input parameters.*/ - if ((base != NULL) && (userConfig != NULL)) - { -#if defined(FSL_FEATURE_TRNG_HAS_RSTCTL) && (FSL_FEATURE_TRNG_HAS_RSTCTL > 0) - /* Reset TRNG peripheral */ -#if (defined(RW610_SERIES) || defined(RW612_SERIES)) - SYSCTL2->TRNG_PIN_CTRL |= SYSCTL2_TRNG_PIN_CTRL_ENABLE_MASK; -#endif /* RW610_SERIES RW612_SERIES */ - RESET_PeripheralReset(trng_reset); -#endif /* FSL_FEATURE_TRNG_HAS_RSTCTL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock gate. */ - CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Clear pending errors, set program mode and reset the registers to default values.*/ - /* MCTL[PRGM] = 1 (kTRNG_WorkModeProgram); MCTL[ERR] = 1; MCTL[RST_DEF] = 1 */ - TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK), - TRNG_MCTL_PRGM(kTRNG_WorkModeProgram) | TRNG_MCTL_ERR(1) | TRNG_MCTL_RST_DEF(1)); - - /* Set configuration.*/ - if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success) - { - /* Start entropy generation.*/ - /* Set to Run mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) - /* Enable TRNG Access Mode. To generate an Entropy - * value that can be read via the true0-true15 registers.*/ - TRNG_WR_MCTL_TRNG_ACC(base, 1); -#endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ - - (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); - - if (true == userConfig->lock) /* Disable programmability of TRNG registers. */ - { - TRNG_WR_SEC_CFG_NO_PRGM(base, 1); - } - - result = kStatus_Success; - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -/*! - * brief Shuts down the TRNG. - * - * This function shuts down the TRNG. - * - * param base TRNG base address. - */ -void TRNG_Deinit(TRNG_Type *base) -{ - /* Check input parameters.*/ - if (NULL != base) - { - /* Move to program mode. Stop entropy generation.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - - /* Check before clock stop. - TRNG turns on the TRNG free-running ring oscillator whenever new entropy - is being generated and turns off the ring oscillator when entropy generation - is complete. If the TRNG clock is stopped while the TRNG ring oscillator - is running, the oscillator continues running though the RNG clock. - is stopped. */ - while (TRNG_RD_MCTL_TSTOP_OK(base) == 0u) - { - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable Clock*/ - CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -} - -/*! - * brief Gets random data. - * - * This function gets random data from the TRNG. - * - * param base TRNG base address. - * param data Pointer address used to store random data. - * param dataSize Size of the buffer pointed by the data parameter. - * return random data - */ -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Success; - uint32_t random_32; - uint8_t *random_p; - uint32_t random_size; - uint8_t *data_p = (uint8_t *)data; - uint32_t i; - uint32_t tmpValidFlag; - uint32_t tmpErrorFlag; - - int index = 0; - - /* Check input parameters.*/ - if ((NULL != base) && (NULL != data) && (0U != dataSize)) - { - /* After a deepsleep exit some errors bits are set in MCTL and must be cleared before processing further. - Also, trigger new 512 bits entropy generation to be sure we will have fresh bits.*/ - if (0U != TRNG_RD_MCTL_ERR(base)) - { - /* clear errors bits */ - TRNG_WR_MCTL_ERR(base, 1); - /* restart new entropy generation */ - (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); - } - - do - { - /* Wait for Valid or Error flag*/ - tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base); - tmpErrorFlag = TRNG_RD_MCTL_ERR(base); - while ((tmpValidFlag == 0u) && (tmpErrorFlag == 0u)) - { - tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base); - tmpErrorFlag = TRNG_RD_MCTL_ERR(base); - } - - /* Check HW error.*/ - if (0U != TRNG_RD_MCTL_ERR(base)) - { - result = kStatus_Fail; /* TRNG module error occurred */ - /* Clear error.*/ - TRNG_WR_MCTL_ERR(base, 1); - break; /* No sense stay here.*/ - } - - /* Read Entropy.*/ - random_32 = trng_ReadEntropy(base, (uint32_t)index++); - - random_p = (uint8_t *)&random_32; - - if (dataSize < sizeof(random_32)) - { - random_size = dataSize; - } - else - { - random_size = sizeof(random_32); - } - - for (i = 0U; i < random_size; i++) - { - *data_p++ = *random_p++; - } - - dataSize -= random_size; - } while (dataSize > 0u); - - /* Start a new entropy generation. - It is done by reading of the last entropy register.*/ - if (((unsigned)index % TRNG_ENT_COUNT) != 0U) - { - (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trng.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trng.h deleted file mode 100644 index db4909e7bb..0000000000 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_trng.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018, 2020-2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_TRNG_DRIVER_H_ -#define _FSL_TRNG_DRIVER_H_ - -#include "fsl_common.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/*! - * @addtogroup trng - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief TRNG driver version 2.0.16. - * - * Current version: 2.0.16 - * - - * Change log: - * - version 2.0.16 - * - Added support for Dual oscillator mode. - * - version 2.0.15 - * - Changed TRNG_USER_CONFIG_DEFAULT_XXX values according to latest reccomended by design team. - * - version 2.0.14 - * - add support for RW610 and RW612 - * - version 2.0.13 - * - After deepsleep it might return error, added clearing bits in TRNG_GetRandomData() and generating new entropy. - * - Modified reloading entropy in TRNG_GetRandomData(), for some data length it doesn't reloading entropy correctly. - * - version 2.0.12 - * - For KW34A4_SERIES, KW35A4_SERIES, KW36A4_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv8. - * - version 2.0.11 - * - Add clearing pending errors in TRNG_Init(). - * - version 2.0.10 - * - Fixed doxygen issues. - * - version 2.0.9 - * - Fix HIS_CCM metrics issues. - * - version 2.0.8 - * - For K32L2A41A_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv4. - * - version 2.0.7 - * - Fix MISRA 2004 issue rule 12.5. - * - version 2.0.6 - * - For KW35Z4_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv8. - * - version 2.0.5 - * - Add possibility to define default TRNG configuration by device specific preprocessor macros - * for FRQMIN, FRQMAX and OSCDIV. - * - version 2.0.4 - * - Fix MISRA-2012 issues. - * - Version 2.0.3 - * - update TRNG_Init to restart entropy generation - * - Version 2.0.2 - * - fix MISRA issues - * - Version 2.0.1 - * - add support for KL8x and KL28Z - * - update default OSCDIV for K81 to divide by 2 - */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 16)) -/*@}*/ - -/*! @brief TRNG sample mode. Used by trng_config_t. */ -typedef enum _trng_sample_mode -{ - kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeVonNeumannRaw = - 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ -} trng_sample_mode_t; - -/*! @brief TRNG clock mode. Used by trng_config_t. */ -typedef enum _trng_clock_mode -{ - kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ - kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and - indeterminate results may occur. */ -} trng_clock_mode_t; - -/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */ -typedef enum _trng_ring_osc_div -{ - kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */ - kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */ - kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */ - kTRNG_RingOscDiv8 = 3U /*!< Ring oscillator divided-by-8. */ -} trng_ring_osc_div_t; - -#if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0) -/*! @brief TRNG oscillator mode . Used by trng_config_t. */ -typedef enum trng_oscillator_mode_t -{ - kTRNG_SingleOscillatorModeOsc1 = 0U, /*!< Single oscillator mode, using OSC1 (default)*/ - kTRNG_DualOscillatorMode = 1U, /*!< Dual oscillator mode*/ - kTRNG_SingleOscillatorModeOsc2 = 2U, /*!< Single oscillator mode, using OSC2 */ -} trng_oscillator_mode_t; -#endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */ - -/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */ -typedef struct _trng_statistical_check_limit -{ - uint32_t maximum; /*!< Maximum limit.*/ - uint32_t minimum; /*!< Minimum limit.*/ -} trng_statistical_check_limit_t; - -/*! - * @brief Data structure for the TRNG initialization - * - * This structure initializes the TRNG by calling the TRNG_Init() function. - * It contains all TRNG configurations. - */ -typedef struct _trng_user_config -{ - bool lock; /*!< @brief Disable programmability of TRNG registers. */ - trng_clock_mode_t clockMode; /*!< @brief Clock mode used to operate TRNG.*/ - trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */ - trng_sample_mode_t sampleMode; /*!< @brief Sample mode of the TRNG ring oscillator. */ -#if defined(FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS) && (FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS > 0) - trng_oscillator_mode_t oscillatorMode; /*!< @brief TRNG oscillator mode . */ - trng_ring_osc_div_t ringOsc2Div; /*!< @brief Divider used for Ring oscillator 2. */ -#endif /* FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS */ - /* Seed Control*/ - uint16_t - entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ - uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during - Entropy generation. */ - uint16_t sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of - * consecutive samples that may be discarded before an error is generated. - * This limit is used only for during von Neumann sampling (enabled by - * TRNG_HAL_SetSampleMode()). Samples are discarded if two consecutive raw samples are both - * 0 or both 1. If this discarding occurs for a long period of time, it indicates that - * there is insufficient Entropy. */ - /* Statistical Check Parameters.*/ - uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails - * during the TRNG Entropy Generation before generating an error. */ - uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, - * that is allowed during the Entropy generation. */ - trng_statistical_check_limit_t monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number - of ones/zero detected during entropy generation. */ - trng_statistical_check_limit_t runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number - of runs of length 1 detected during entropy generation. */ - trng_statistical_check_limit_t runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number - of runs of length 2 detected during entropy generation. */ - trng_statistical_check_limit_t runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number - of runs of length 3 detected during entropy generation. */ - trng_statistical_check_limit_t runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number - of runs of length 4 detected during entropy generation. */ - trng_statistical_check_limit_t runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number - of runs of length 5 detected during entropy generation. */ - trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of - number of runs of length 6 or more detected during entropy - generation. */ - trng_statistical_check_limit_t - pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ - trng_statistical_check_limit_t frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of - entropy sample frequency count. */ -} trng_config_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the user configuration structure to default values. - * - * This function initializes the configuration structure to default values. The default - * values are as follows. - * @code - * userConfig->lock = 0; - * userConfig->clockMode = kTRNG_ClockModeRingOscillator; - * userConfig->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. - * userConfig->sampleMode = kTRNG_SampleModeRaw; - * userConfig->entropyDelay = 3200; - * userConfig->sampleSize = 2500; - * userConfig->sparseBitLimit = 63; - * userConfig->retryCount = 1; - * userConfig->longRunMaxLimit = 32; - * userConfig->monobitLimit.maximum = 317; - * userConfig->monobitLimit.minimum = 195; - * userConfig->runBit1Limit.maximum = 107; - * userConfig->runBit1Limit.minimum = 27; - * userConfig->runBit2Limit.maximum = 62; - * userConfig->runBit2Limit.minimum = 7; - * userConfig->runBit3Limit.maximum = 39; - * userConfig->runBit3Limit.minimum = 0; - * userConfig->runBit4Limit.maximum = 26; - * userConfig->runBit4Limit.minimum = 0; - * userConfig->runBit5Limit.maximum = 18; - * userConfig->runBit5Limit.minimum = 0; - * userConfig->runBit6PlusLimit.maximum = 17; - * userConfig->runBit6PlusLimit.minimum = 0; - * userConfig->pokerLimit.maximum = 1600; - * userConfig->pokerLimit.minimum = 1030; - * userConfig->frequencyCountLimit.maximum = 30000; - * userConfig->frequencyCountLimit.minimum = 1600; - * @endcode - * - * @param userConfig User configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig); - -/*! - * @brief Initializes the TRNG. - * - * This function initializes the TRNG. - * When called, the TRNG entropy generation starts immediately. - * - * @param base TRNG base address - * @param userConfig Pointer to the initialization configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig); - -/*! - * @brief Shuts down the TRNG. - * - * This function shuts down the TRNG. - * - * @param base TRNG base address. - */ -void TRNG_Deinit(TRNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the TRNG. - * - * @param base TRNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ -#endif /*_FSL_TRNG_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tsi_v6.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tsi_v6.h index f6e05a56df..c6fc98772f 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tsi_v6.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_tsi_v6.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_TSI_V6_H_ -#define _FSL_TSI_V6_H_ +#ifndef FSL_TSI_V6_H_ +#define FSL_TSI_V6_H_ #include "fsl_common.h" @@ -1112,4 +1112,4 @@ static inline void TSI_ClearUsedTxChannel(TSI_Type *base, tsi_mutual_tx_channel_ /*! @}*/ -#endif /* _FSL_TSI_V6_H_ */ +#endif /* FSL_TSI_V6_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.c index f2c82d8cde..7738f53144 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.c @@ -957,7 +957,9 @@ void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) (htCapability & (USDHC_HOST_CTRL_CAP_ADMAS_MASK | USDHC_HOST_CTRL_CAP_HSS_MASK | USDHC_HOST_CTRL_CAP_DMAS_MASK | USDHC_HOST_CTRL_CAP_SRS_MASK | USDHC_HOST_CTRL_CAP_VS33_MASK)); capability->flags |= htCapability & USDHC_HOST_CTRL_CAP_VS30_MASK; +#if !(defined(FSL_FEATURE_USDHC_HAS_NO_VS18) && FSL_FEATURE_USDHC_HAS_NO_VS18) capability->flags |= htCapability & USDHC_HOST_CTRL_CAP_VS18_MASK; +#endif capability->flags |= htCapability & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK; #if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && FSL_FEATURE_USDHC_HAS_SDR104_MODE capability->flags |= USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK; @@ -2148,6 +2150,24 @@ void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; +#if defined(USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) && USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK; + /* 1bit data width */ + if (busWidth == 0UL) + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_BIT_EN(2U); + } + /* 4bit data width */ + else if (busWidth == 1UL) + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_BIT_EN(0U); + } + /* 8bit data width */ + else + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_BIT_EN(1U); + } +#else /* 1bit data width */ if (busWidth == 0UL) { @@ -2166,6 +2186,7 @@ void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; } +#endif } #endif /* FSL_FEATURE_USDHC_HAS_SDR50_MODE */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.h index 9cf1fc07c3..5fd51c2195 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_usdhc.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_USDHC_H_ -#define _FSL_USDHC_H_ +#ifndef FSL_USDHC_H_ +#define FSL_USDHC_H_ #include "fsl_common.h" @@ -20,10 +20,10 @@ *****************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.8.2. */ -#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 8U, 2U)) -/*@}*/ +/*! @{ */ +/*! @brief Driver version 2.8.4. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 8U, 4U)) +/*! @} */ /*! @brief Maximum block count can be set one time */ #define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) @@ -60,7 +60,9 @@ enum kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume. */ kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V. */ kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V. */ +#if !(defined(FSL_FEATURE_USDHC_HAS_NO_VS18) && FSL_FEATURE_USDHC_HAS_NO_VS18) kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V. */ +#endif kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Flag in HTCAPBLT_MBL's position, supporting 4-bit mode. */ kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), @@ -824,7 +826,7 @@ void USDHC_Deinit(USDHC_Type *base); */ bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); -/* @} */ +/*! @} */ /*! * @name DMA Control @@ -912,7 +914,7 @@ static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable) } } -/* @} */ +/*! @} */ /*! * @name Interrupts @@ -963,7 +965,7 @@ static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) base->INT_SIGNAL_EN &= ~mask; } -/* @} */ +/*! @} */ /*! * @name Status @@ -1040,7 +1042,7 @@ static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) return base->PRES_STATE; } -/* @} */ +/*! @} */ /*! * @name Bus Operations @@ -1591,7 +1593,7 @@ void USDHC_SetDataConfig(USDHC_Type *base, usdhc_transfer_direction_t dataDirection, uint32_t blockCount, uint32_t blockSize); -/* @} */ +/*! @} */ /*! * @name Transactional functions @@ -1693,11 +1695,11 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig */ void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); -/* @} */ +/*! @} */ #if defined(__cplusplus) } #endif /*! @} */ -#endif /* _FSL_USDHC_H_*/ +#endif /* FSL_USDHC_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_utick.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_utick.h index 48c7d6b86d..a3b734eae4 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_utick.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_utick.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_UTICK_H_ -#define _FSL_UTICK_H_ +#ifndef FSL_UTICK_H_ +#define FSL_UTICK_H_ #include "fsl_common.h" /*! @@ -21,10 +21,10 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief UTICK driver version 2.0.5. */ #define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) -/*@}*/ +/*! @} */ /*! @brief UTICK timer operational mode. */ typedef enum _utick_mode @@ -107,7 +107,7 @@ void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_ca */ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -115,4 +115,4 @@ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); /*! @}*/ -#endif /* _FSL_UTICK_H_ */ +#endif /* FSL_UTICK_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.c index 79ec6ff0e8..60f9757157 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -42,6 +42,7 @@ void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config) VBAT_UngateFRO16k(base, config->enabledConnectionsMask); } +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) /*! * brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. * @@ -77,7 +78,7 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, if (operateMode == kVBAT_Osc32kEnabledToLowPowerBackupMode) { - if ((extalCap & 0x1U) != 0U) + if (((uint8_t)extalCap & 0x1U) != 0U) { return kStatus_VBAT_WrongCapacitanceValue; } @@ -90,15 +91,17 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | (VBAT_OSCCTLA_XTAL_CAP_SEL(xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(extalCap))); base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | - VBAT_OSCCTLA_XTAL_CAP_SEL(~xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~extalCap)); + VBAT_OSCCTLA_XTAL_CAP_SEL(~(uint32_t)xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~(uint32_t)extalCap)); } base->OSCCTLA = (((base->OSCCTLA & ~VBAT_OSCCTLA_MODE_EN_MASK)) | VBAT_OSCCTLA_MODE_EN(operateMode)); - base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN((uint8_t)~operateMode)); + base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN(~(uint32_t)operateMode)); return kStatus_Success; } +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) /*! * brief Enable/disable Bandgap. * @@ -219,7 +222,9 @@ status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base) return status; } +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) /*! * brief Enable/disable Bandgap timer. * @@ -333,3 +338,161 @@ void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod) base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; } } +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * brief Initializes the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_clock_monitor_config_t structure. + * + * retval kStatus_Success Clock monitor is initialized successfully. + * retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if ((VBAT_GetStatusFlags(base) & kVBAT_StatusFlagOsc32kReady) != 0UL) + { + if (VBAT_CheckClockMonitorControlLocked(base)) + { + status = kStatus_VBAT_ClockMonitorLocked; + } + else + { + /* Disable clock monitor before configuring clock monitor. */ + VBAT_EnableClockMonitor(base, false); + /* Set clock monitor divide trim value. */ + VBAT_SetClockMonitorDivideTrim(base, config->divideTrim); + /* Set clock monitor frequency trim value. */ + VBAT_SetClockMonitorFrequencyTrim(base, config->freqTrim); + /* Enable clock monitor. */ + VBAT_EnableClockMonitor(base, true); + + if (config->lock) + { + VBAT_LockClockMonitorControl(base); + } + } + } + else + { + status = kStatus_VBAT_OSC32KNotReady; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief Deinitialize the VBAT clock monitor. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Clock monitor is de-initialized successfully. + * retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base) +{ + if (VBAT_CheckClockMonitorControlLocked(base)) + { + return kStatus_VBAT_ClockMonitorLocked; + } + + VBAT_EnableClockMonitor(base, false); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * brief Initialize tamper control. + * + * note Both FRO16K and bandgap should be enabled before calling this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_tamper_config_t structure. + * + * retval kStatus_Success Tamper is initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + * retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + else + { + base->TAMCTLA = ((base->TAMCTLA & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN(config->enableVoltageDetect) | + VBAT_TAMCTLA_TEMP_EN(config->enableTemperatureDetect)); + base->TAMCTLB = ((base->TAMCTLB & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN((config->enableVoltageDetect) ? 0U : 1U) | + VBAT_TAMCTLA_TEMP_EN((config->enableTemperatureDetect) ? 0U : 1U)); + + if (config->lock) + { + VBAT_LockTamperControl(base); + } + } + } + else + { + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief De-initialize tamper control. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Tamper is de-initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base) +{ + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + + base->TAMCTLA &= ~(VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + base->TAMCTLB |= (VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.h index e34f3b87a3..5858b005eb 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vbat.h @@ -1,12 +1,12 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2024 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_VBAT_H_ -#define _FSL_VBAT_H_ +#ifndef FSL_VBAT_H_ +#define FSL_VBAT_H_ #include "fsl_common.h" @@ -21,10 +21,16 @@ /*! @name Driver version */ /*@{*/ -/*! @brief VBAT driver version 2.0.0. */ -#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief VBAT driver version 2.3.1. */ +#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ +#if !defined(VBAT_LDORAMC_RET_MASK) +#define VBAT_LDORAMC_RET_MASK (0xF00U) +#define VBAT_LDORAMC_RET_SHIFT (8U) +#define VBAT_LDORAMC_RET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK) +#endif + /*! * @brief The enumeration of VBAT module status. */ @@ -35,8 +41,13 @@ enum kStatus_VBAT_BandgapNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 1), /*!< Bandgap not enabled. */ kStatus_VBAT_WrongCapacitanceValue = MAKE_STATUS(kStatusGroup_VBAT, 2), /*!< Wrong capacitance for selected oscillator mode. */ + kStatus_VBAT_ClockMonitorLocked = MAKE_STATUS(kStatusGroup_VBAT, 3), /*!< Clock monitor locked. */ + kStatus_VBAT_OSC32KNotReady = MAKE_STATUS(kStatusGroup_VBAT, 4), /*!< OSC32K not ready. */ + kStatus_VBAT_LDONotReady = MAKE_STATUS(kStatusGroup_VBAT, 5), /*!< LDO not ready. */ + kStatus_VBAT_TamperLocked = MAKE_STATUS(kStatusGroup_VBAT, 6), /*!< Tamper locked. */ }; +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) /*! * @brief The enumeration of VBAT status flags. * @@ -50,7 +61,20 @@ enum _vbat_status_flag kVBAT_StatusFlagBandgapTimer1 = VBAT_STATUSA_TIMER1_FLAG_MASK, /*!< Bandgap Timer1 period reached. */ kVBAT_StatusFlagLdoReady = VBAT_STATUSA_LDO_RDY_MASK, /*!< LDO is enabled and ready. */ kVBAT_StatusFlagOsc32kReady = VBAT_STATUSA_OSC_RDY_MASK, /*!< OSC32k is enabled and clock is ready. */ - kVBAT_StatusFlagConfigDetect = VBAT_STATUSA_CONFIG_DET_MASK, /*!< Configuration error detected. */ +#if defined(VBAT_STATUSA_CLOCK_DET_MASK) + kVBAT_StatusFlagClockDetect = VBAT_STATUSA_CLOCK_DET_MASK, /*!< The clock monitor has detected an error. */ +#endif /* VBAT_STATUSA_CLOCK_DET_MASK */ + kVBAT_StatusFlagConfigDetect = VBAT_STATUSA_CONFIG_DET_MASK, /*!< Configuration error detected. */ +#if defined(VBAT_STATUSA_VOLT_DET_MASK) + kVBAT_StatusFlagVoltageDetect = VBAT_STATUSA_VOLT_DET_MASK, /*!< Voltage monitor has detected + an error with VBAT supply. */ +#endif /* VBAT_STATUSA_VOLT_DET_MASK */ +#if defined(VBAT_STATUSA_TEMP_DET_MASK) + kVBAT_StatusFlagTemperatureDetect = VBAT_STATUSA_TEMP_DET_MASK, /*!< Temperature monitor has detected an error. */ +#endif /* VBAT_STATUSA_TEMP_DET_MASK */ +#if defined(VBAT_STATUSA_SEC0_DET_MASK) + kVBAT_StatusFlagSec0Detect = VBAT_STATUSA_SEC0_DET_MASK, /*!< Security input 0 has detected an error. */ +#endif /* VBAT_STATUSA_SEC0_DET_MASK */ kVBAT_StatusFlagInterrupt0Detect = VBAT_STATUSA_IRQ0_DET_MASK, /*!< Interrupt 0 asserted. */ kVBAT_StatusFlagInterrupt1Detect = VBAT_STATUSA_IRQ1_DET_MASK, /*!< Interrupt 1 asserted. */ kVBAT_StatusFlagInterrupt2Detect = VBAT_STATUSA_IRQ2_DET_MASK, /*!< Interrupt 2 asserted. */ @@ -73,8 +97,21 @@ enum _vbat_interrupt_enable Timer1 period reached. */ kVBAT_InterruptEnableLdoReady = VBAT_IRQENA_LDO_RDY_MASK, /*!< Enable LDO ready interrupt. */ kVBAT_InterruptEnableOsc32kReady = VBAT_IRQENA_OSC_RDY_MASK, /*!< Enable OSC32K ready interrupt. */ +#if defined(VBAT_IRQENA_CLOCK_DET_MASK) + kVBAT_InterruptEnableClockDetect = VBAT_IRQENA_CLOCK_DET_MASK, /*!< Enable clock monitor detect interrupt. */ +#endif /* VBAT_IRQENA_CLOCK_DET_MASK */ kVBAT_InterruptEnableConfigDetect = - VBAT_IRQENA_CONFIG_DET_MASK, /*!< Enable configuration error detected interrupt. */ + VBAT_IRQENA_CONFIG_DET_MASK, /*!< Enable configuration error detected interrupt. */ +#if defined(VBAT_IRQENA_VOLT_DET_MASK) + kVBAT_InterruptEnableVoltageDetect = VBAT_IRQENA_VOLT_DET_MASK, /*!< Enable voltage monitor detect interrupt. */ +#endif /* VBAT_IRQENA_VOLT_DET_MASK */ +#if defined(VBAT_IRQENA_TEMP_DET_MASK) + kVBAT_InterruptEnableTemperatureDetect = VBAT_IRQENA_TEMP_DET_MASK, /*!< Enable temperature monitor detect + interrupt. */ +#endif /* VBAT_IRQENA_TEMP_DET_MASK */ +#if defined(VBAT_IRQENA_SEC0_DET_MASK) + kVBAT_InterruptEnableSec0Detect = VBAT_IRQENA_SEC0_DET_MASK, /*!< Enable security input 0 detect interrupt. */ +#endif /* VBAT_IRQENA_SEC0_DET_MASK */ kVBAT_InterruptEnableInterrupt0 = VBAT_IRQENA_IRQ0_DET_MASK, /*!< Enable the interrupt0. */ kVBAT_InterruptEnableInterrupt1 = VBAT_IRQENA_IRQ1_DET_MASK, /*!< Enable the interrupt1. */ kVBAT_InterruptEnableInterrupt2 = VBAT_IRQENA_IRQ2_DET_MASK, /*!< Enable the interrupt2. */ @@ -103,8 +140,24 @@ enum _vbat_wakeup_enable timer1 period reached. */ kVBAT_WakeupEnableLdoReady = VBAT_WAKENA_LDO_RDY_MASK, /*!< Enable wakeup when LDO ready. */ kVBAT_WakeupEnableOsc32kReady = VBAT_WAKENA_OSC_RDY_MASK, /*!< Enable wakeup when OSC32k ready. */ - kVBAT_WakeupEnableConfigDetect = VBAT_WAKENA_CONFIG_DET_MASK, /*!< Enable wakeup when - configuration error detected. */ +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + kVBAT_WakeupEnableClockDetect = + VBAT_WAKENA_CLOCK_DET_MASK, /*!< Enable wakeup when clock monitor detect an error. */ +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ + kVBAT_WakeupEnableConfigDetect = VBAT_WAKENA_CONFIG_DET_MASK, /*!< Enable wakeup when + configuration error detected. */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + kVBAT_WakeupEnableVoltageDetect = VBAT_WAKENA_VOLT_DET_MASK, /*!< Enable wakeup when voltage monitor detect an + error. */ +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + kVBAT_WakeupEnableTemperatureDetect = VBAT_WAKENA_TEMP_DET_MASK, /*!< Enable wakeup when temperature monitor + detect an error. */ +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + kVBAT_WakeupEnableSec0Detect = VBAT_WAKENA_SEC0_DET_MASK, /*!< Enable wakeup when security input 0 detect an + error. */ +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ kVBAT_WakeupEnableInterrupt0 = VBAT_WAKENA_IRQ0_DET_MASK, /*!< Enable wakeup when interrupt0 asserted. */ kVBAT_WakeupEnableInterrupt1 = VBAT_WAKENA_IRQ1_DET_MASK, /*!< Enable wakeup when interrupt1 asserted. */ kVBAT_WakeupEnableInterrupt2 = VBAT_WAKENA_IRQ2_DET_MASK, /*!< Enable wakeup when interrupt2 asserted. */ @@ -113,9 +166,48 @@ enum _vbat_wakeup_enable kVBAT_AllWakeupsEnable = (VBAT_WAKENA_POR_DET_MASK | VBAT_WAKENA_WAKEUP_FLAG_MASK | VBAT_WAKENA_TIMER0_FLAG_MASK | VBAT_WAKENA_TIMER1_FLAG_MASK | VBAT_WAKENA_LDO_RDY_MASK | VBAT_WAKENA_OSC_RDY_MASK | VBAT_WAKENA_CONFIG_DET_MASK | VBAT_WAKENA_IRQ0_DET_MASK | VBAT_WAKENA_IRQ1_DET_MASK | - VBAT_WAKENA_IRQ2_DET_MASK | VBAT_WAKENA_IRQ3_DET_MASK), /*!< Enable all wakeup. */ -}; + VBAT_WAKENA_IRQ2_DET_MASK | VBAT_WAKENA_IRQ3_DET_MASK +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + | VBAT_WAKENA_CLOCK_DET_MASK + +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + | VBAT_WAKENA_VOLT_DET_MASK + +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + | VBAT_WAKENA_TEMP_DET_MASK + +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + | VBAT_WAKENA_SEC0_DET_MASK + +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + ), /*!< Enable all wakeup. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The enumeration of VBAT tamper enable. + */ +enum _vbat_tamper_enable +{ + kVBAT_TamperEnablePOR = VBAT_TAMPERA_POR_DET_MASK, /*!< Enable tamper if POR asserted in STATUS register. */ + kVBAT_TamperEnableClockDetect = VBAT_TAMPERA_CLOCK_DET_MASK, /*!< Enable tamper if clock monitor detect an error. */ + kVBAT_TamperEnableConfigDetect = + VBAT_TAMPERA_CONFIG_DET_MASK, /*!< Enable tamper if configuration error detected. */ + kVBAT_TamperEnableVoltageDetect = VBAT_TAMPERA_VOLT_DET_MASK, /*!< Enable tamper if voltage monitor detect an + error. */ + kVBAT_TamperEnableTemperatureDetect = VBAT_TAMPERA_TEMP_DET_MASK, /*!< Enable tamper if temperature monitor + detect an error. */ + kVBAT_TamperEnableSec0Detect = VBAT_TAMPERA_SEC0_DET_MASK, /*!< Enable tamper if security input 0 detect an + error. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) /*! * @brief The enumeration of bandgap timer id, VBAT support two bandgap timers. * @@ -126,6 +218,7 @@ enum _vbat_bandgap_timer_id kVBAT_BandgapTimer0 = 1U << 0U, /*!< Bandgap Timer0. */ kVBAT_BandgapTimer1 = 1U << 1U, /*!< Bandgap Timer1. */ }; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ /*! * @brief The enumeration of connections for OSC32K/FRO32K output clock to other modules. @@ -134,12 +227,17 @@ enum _vbat_bandgap_timer_id */ enum _vbat_clock_enable { - kVBAT_EnableClockToVddBat = 1U << 0U, /*!< Enable OSC32K/FRO32K to VDD_BAT power domain. */ - kVBAT_EnableClockToVddSys = 1U << 1U, /*!< Enable OSC32K/FRO32K to VDD_SYS power domain. */ - kVBAT_EnableClockToVddWake = 1U << 2U, /*!< Enable OSC32K/FRO32K to VDD_WAKE power domain. */ - kVBAT_EnableClockToVddMain = 1U << 3U, /*!< Enable OSC32K/FRO32K to VDD_MAIN power domain. */ + kVBAT_EnableClockToDomain0 = 1U << 0U, /*!< Enable clock to power domain0. */ + kVBAT_EnableClockToDomain1 = 1U << 1U, /*!< Enable clock to power domain1. */ + kVBAT_EnableClockToDomain2 = 1U << 2U, /*!< Enable clock to power domain2. */ + kVBAT_EnableClockToDomain3 = 1U << 3U, /*!< Enable clock to power domain3. */ }; +#define kVBAT_EnableClockToVddBat kVBAT_EnableClockToDomain0 +#define kVBAT_EnableClockToVddSys kVBAT_EnableClockToDomain1 +#define kVBAT_EnableClockToVddWake kVBAT_EnableClockToDomain2 +#define kVBAT_EnableClockToVddMain kVBAT_EnableClockToDomain3 +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) /*! * @brief The enumeration of SRAM arrays that controlled by VBAT. * @anchor vbat_ram_array_t @@ -151,6 +249,7 @@ enum _vbat_ram_array kVBAT_SramArray2 = 1U << 2U, /*!< Specify SRAM array2 that controlled by VBAT. */ kVBAT_SramArray3 = 1U << 3U, /*!< Specify SRAM array3 that controlled by VBAT. */ }; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ /*! * @brief The enumeration of bandgap refresh period. @@ -163,6 +262,7 @@ typedef enum _vbat_bandgap_refresh_period kVBAT_BandgapRefresh62P5ms = 3U, /*!< Bandgap refresh every 62.5ms. */ } vbat_bandgap_refresh_period_t; +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) /*! * @brief The enumeration of bandgap timer0 timeout period. */ @@ -175,7 +275,9 @@ typedef enum _vbat_bandgap_timer0_timeout_period kVBAT_BangapTimer0Timeout62P5ms = 4U, /*!< Bandgap timer0 timerout every 62.5ms. */ kVBAT_BangapTimer0Timeout31P25ms = 5U, /*!< Bandgap timer0 timerout every 31.25ms. */ } vbat_bandgap_timer0_timeout_period_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) /*! * @brief The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on. */ @@ -225,7 +327,9 @@ typedef enum _vbat_osc32k_start_up_time kVBAT_Osc32kStartUpTime0P125Sec, /*!< Configure the start-up time as 0.125 seconds. */ kVBAT_Osc32kStartUpTime0P5MSec, /*!< Configure the start-up time as 0.5 milliseconds. */ } vbat_osc32k_start_up_time_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) /*! * @brief The enumeration of VBAT module supplies. */ @@ -234,6 +338,29 @@ typedef enum _vbat_internal_module_supply kVBAT_ModuleSuppliedByVddBat = 0U, /*!< VDD_BAT supplies VBAT modules. */ kVBAT_ModuleSuppliedByVddSys = 1U, /*!< VDD_SYS supplies VBAT modules. */ } vbat_internal_module_supply_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The enumeration of VBAT clock monitor divide trim value + */ +typedef enum _vbat_clock_monitor_divide_trim +{ + kVBAT_ClockMonitorOperateAt1kHz = 0U, /*!< Clock monitor operates at 1 kHz. */ + kVBAT_ClockMonitorOperateAt64Hz = 1U, /*!< Clock monitor operates at 64 Hz. */ +} vbat_clock_monitor_divide_trim_t; + +/*! + * @brief The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert. + */ +typedef enum _vbat_clock_monitor_freq_trim +{ + kVBAT_ClockMonitorAssert2Cycle = 0U, /*!< Clock monitor assert 2 cycles after expected edge. */ + kVBAT_ClockMonitorAssert4Cycle = 1U, /*!< Clock monitor assert 4 cycles after expected edge. */ + kVBAT_ClockMonitorAssert6Cycle = 2U, /*!< Clock monitor assert 8 cycles after expected edge. */ + kVBAT_ClockMonitorAssert8Cycle = 3U, /*!< Clock monitor assert 8 cycles after expected edge. */ +} vbat_clock_monitor_freq_trim_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ /*! * @brief The structure of internal 16kHz free running oscillator attributes. @@ -243,6 +370,33 @@ typedef struct _vbat_fro16k_config bool enableFRO16k; /*!< Enable/disable internal 16kHz free running oscillator. */ uint8_t enabledConnectionsMask; /*!< The mask of connected modules to enable FRO16k clock output. */ } vbat_fro16k_config_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The structure of internal clock monitor, including divide trim and frequency trim. + */ +typedef struct _vbat_clock_monitor_config +{ + vbat_clock_monitor_divide_trim_t divideTrim : 1U; /* !< Divide trim value, please + refer to @ref vbat_clock_monitor_divide_trim_t */ + vbat_clock_monitor_freq_trim_t freqTrim : 2U; /*!< Frequency trim value used to adjust the clock monitor + assert, please refer to @ref vbat_clock_monitor_freq_trim_t. */ + bool lock : 1U; /*!< Lock the clock monitor control after enabled. */ +} vbat_clock_monitor_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The structure of Tamper configuration. + */ +typedef struct _vbat_tamper_config +{ + bool enableVoltageDetect : 1U; /*!< Enable/disable voltage detection. */ + bool enableTemperatureDetect : 1U; /*!< Enable/disable temperature detection. */ + bool lock : 1U; /*!< Lock the tamper control after enabled. */ +} vbat_tamper_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + /******************************************************************************* * API ******************************************************************************/ @@ -277,12 +431,16 @@ static inline void VBAT_EnableFRO16k(VBAT_Type *base, bool enable) if (enable) { base->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) base->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ } else { base->FROCTLA &= ~VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) base->FROCTLB |= VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ } } @@ -333,7 +491,9 @@ static inline void VBAT_GateFRO16k(VBAT_Type *base, uint8_t connectionsMask) static inline void VBAT_LockFRO16kSettings(VBAT_Type *base) { base->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; +#if (defined(VBAT_FROLCKB_LOCK_MASK)) base->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; +#endif /* VBAT_FROLCKB_LOCK_MASK */ } /*! @@ -350,6 +510,7 @@ static inline bool VBAT_CheckFRO16kSettingsLocked(VBAT_Type *base) /*! @} */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) /*! * @name OSC32K Control Interfaces * @{ @@ -372,7 +533,7 @@ static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable) /* Polling status register to check clock is ready. */ while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL) - ; + {} } else { @@ -406,6 +567,7 @@ static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass) } } +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) /*! * @brief Adjust 32k crystal oscillator amplifier gain. * @@ -420,6 +582,20 @@ static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_ base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine))); } +#else +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse) +{ + base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse)); + base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~(uint32_t)coarse)); +} + +#endif /* */ /*! * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. @@ -447,7 +623,7 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime) { base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime)); - base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~startupTime)); + base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime))); } /*! @@ -459,7 +635,7 @@ static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32 static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue) { base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue)); - base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~comparatorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue))); } /*! @@ -471,7 +647,7 @@ static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue) { base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue)); - base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~delayTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue))); } /*! @@ -483,7 +659,7 @@ static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8 static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue) { base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue)); - base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~capacitorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue))); } /*! @@ -542,7 +718,9 @@ static inline void VBAT_GateOsc32k(VBAT_Type *base, uint8_t connectionsMask) } /*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) /*! * @name RAM_LDO Control Interfaces * @{ @@ -678,7 +856,7 @@ static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base) */ static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) { - base->LDORAMC |= VBAT_LDORAMC_RET(sramMask); + base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask); } /*! @@ -689,7 +867,7 @@ static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sr */ static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) { - base->LDORAMC &= ~VBAT_LDORAMC_RET(sramMask); + base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask); } /*! @@ -713,7 +891,9 @@ static inline void VBAT_EnableSRAMIsolation(VBAT_Type *base, bool enable) } /*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_RAM_LDO */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) /*! @name Bandgap Timer Control Interfaces * @{ */ @@ -756,7 +936,9 @@ void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_time void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod); /*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) /*! @name Switch Control Interfaces * @{ */ @@ -790,7 +972,7 @@ static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_i */ static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base) { - return (base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK); + return (vbat_internal_module_supply_t)(uint8_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK); } /*! @@ -854,7 +1036,234 @@ static inline bool VBAT_CheckSwitchControlLocked(VBAT_Type *base) } /*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @name Clock Monitor Interfaces + * @{ + */ + +/*! + * @brief Initialize the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * @note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_clock_monitor_config_t structure. + * + * @retval kStatus_Success Clock monitor is initialized successfully. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * @retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * @retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config); + +/*! + * @brief Deinitialize the VBAT clock monitor. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Clock monitor is de-initialized successfully. + * @retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base); + +/*! + * @brief Enable/disable clock monitor. + * + * @param base VBAT peripheral base address. + * @param enable Switcher to enable/disable clock monitor: + * - true: enable clock monitor; + * - false: disable clock monitor. + */ +static inline void VBAT_EnableClockMonitor(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->MONCTLA |= VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB &= ~VBAT_MONCTLA_MON_EN_MASK; + } + else + { + base->MONCTLA &= ~VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB |= VBAT_MONCTLA_MON_EN_MASK; + } +} + +/*! + * @brief Set clock monitor's divide trim, avaiable value is #kVBAT_ClockMonitorOperateAt1kHz and + * #kVBAT_ClockMonitorOperateAt64Hz + * + * @param base VBAT peripheral base address. + * @param divideTrim Specify divide trim value, please refer to @ref vbat_clock_monitor_divide_trim_t. + */ +static inline void VBAT_SetClockMonitorDivideTrim(VBAT_Type *base, vbat_clock_monitor_divide_trim_t divideTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(divideTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(~divideTrim); +} + +/*! + * @brief Set clock monitor's frequency trim, avaiable value is #kVBAT_ClockMonitorAssert2Cycle, + * #kVBAT_ClockMonitorAssert4Cycle, #kVBAT_ClockMonitorAssert6Cycle and #kVBAT_ClockMonitorAssert8Cycle. + * + * @param base VBAT peripheral base address. + * @param freqTrim Specify frequency trim value, please refer to @ref vbat_clock_monitor_freq_trim_t. + */ +static inline void VBAT_SetClockMonitorFrequencyTrim(VBAT_Type *base, vbat_clock_monitor_freq_trim_t freqTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(freqTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(~freqTrim); +} + +/*! + * @brief Lock clock monitor enable/disable control. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA |= VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB &= ~VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock clock monitor enable/disable control. + * + * @param base VBTA peripheral base address. + */ +static inline void VBAT_UnlockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA &= ~VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB |= VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Check if clock monitor enable/disable control is locked. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + * + * @retval false clock monitor enable/disable control is not locked. + * @retval true clock monitor enable/disable control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckClockMonitorControlLocked(VBAT_Type *base) +{ + return ((base->MONLCKA & VBAT_MONLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_CLOCK_MONITOR */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! @name Tamper Control Interfaces + * + */ + +/*! + * @brief Initialize tamper control. + * + * @note Both FRO16K and bandgap should be enabled before calling this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_tamper_config_t structure. + * + * @retval kStatus_Success Tamper is initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + * @retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config); + +/*! + * @brief De-initialize tamper control. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Tamper is de-initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base); + +/*! + * @brief Enable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be enabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_EnableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA |= tamperEnableMask; + base->TAMPERB &= ~tamperEnableMask; +} + +/*! + * @brief Disable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be disabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_DisableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA &= ~tamperEnableMask; + base->TAMPERB |= tamperEnableMask; +} + +/*! + * @brief Get tamper enable information. + * + * @param base VBAT peripheral base address. + * + * @return Mask of tamper enable information, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline uint32_t VBAT_GetTamperEnableInfo(VBAT_Type *base) +{ + return base->TAMPERA; +} + +/*! + * @brief Lock tamper control, if locked, it is not allowed to change tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA |= VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB &= ~VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA &= ~VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB |= VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Check if tamper control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false Tamper control is not locked. + * @retval true Tamper control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckTamperControlLocked(VBAT_Type *base) +{ + return ((base->TAMLCKA & VBAT_TAMLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_TAMPER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) /*! @name Status, Interrupt, Wakeup Control Interfaces * @{ */ @@ -965,6 +1374,7 @@ static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert) } /*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ #if defined(__cplusplus) } @@ -973,4 +1383,4 @@ static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert) /*! * @} */ -#endif /* __FSL_VBAT_H__ */ +#endif /* FSL_VBAT_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.c index 5620d630ec..fd8ee68ae2 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.c @@ -46,8 +46,18 @@ static uint32_t VREF_GetInstance(VREF_Type *base) uint32_t instance; /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_vrefBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++) { + /* + * $Branch Coverage Justification$ + * (s_vrefBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ if (s_vrefBases[instance] == base) { break; @@ -122,13 +132,9 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config) { tmp32 |= VREF_CSR_BUF21EN_MASK; } - else if (config->bufferMode == kVREF_ModeHighPowerBuffer) - { - tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); - } else { - /* Add comments to prevent the case of MISRA C-2012 ruel 15.7. */ + tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); } base->CSR |= tmp32; @@ -215,6 +221,12 @@ void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue) } else { + /*Wait internal HC voltage reference stable*/ + /* + * $Branch Coverage Justification$ + * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible, + * the internal HC voltage stable state is too short not to catch. + */ while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) { } @@ -249,6 +261,12 @@ void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) } else { + /*Wait internal HC voltage reference stable*/ + /* + * $Branch Coverage Justification$ + * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible, + * the internal HC voltage stable state is too short not to catch. + */ while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) { } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.h index fc8f28e9e3..4c248df98c 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_vref.h @@ -1,12 +1,12 @@ /* - * Copyright 2019-2022 NXP + * Copyright 2019-2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_VREF_H_ -#define _FSL_VREF_H_ +#ifndef FSL_VREF_H_ +#define FSL_VREF_H_ #include "fsl_common.h" @@ -20,16 +20,16 @@ ******************************************************************************/ /*! @name Driver version */ -/*@{*/ -#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ -/*@}*/ +/*! @{ */ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2. */ +/*! @} */ /*! @brief VREF buffer modes. */ typedef enum _vref_buffer_mode { kVREF_ModeBandgapOnly = 0U, /*!< Bandgap enabled/standby. */ - kVREF_ModeLowPowerBuffer = 1U, /*!< High-power buffer mode enabled */ - kVREF_ModeHighPowerBuffer = 2U, /*!< Low-power buffer mode enabled */ + kVREF_ModeLowPowerBuffer = 1U, /*!< Low-power buffer mode enabled */ + kVREF_ModeHighPowerBuffer = 2U, /*!< High-power buffer mode enabled */ } vref_buffer_mode_t; /*! @brief The description structure for the VREF module. */ @@ -110,7 +110,7 @@ void VREF_Deinit(VREF_Type *base); */ void VREF_GetDefaultConfig(vref_config_t *config); -/* @} */ +/*! @} */ /*! * @name Trim functions @@ -161,7 +161,7 @@ uint8_t VREF_GetVrefTrimVal(VREF_Type *base); */ uint8_t VREF_GetTrim21Val(VREF_Type *base); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -169,4 +169,4 @@ uint8_t VREF_GetTrim21Val(VREF_Type *base); /*! @}*/ -#endif /* _FSL_VREF_H_ */ +#endif /* FSL_VREF_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.c index 9b15981368..214e7c07f0 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2023 NXP. + * Copyright 2019-2024 NXP. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -118,6 +118,26 @@ void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu } } +/*! + * brief Disable and clear external wakeup pin settings. + * + * param base MUU peripheral base address. + * param pinIndex The index of the external input pin. + */ +void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex) +{ + if (pinIndex <= 15U) + { + base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex)); + base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex)); + } + else + { + base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL))); + base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL))); + } +} + /*! * brief Config Internal modules' event as the wake up soures. * @@ -143,6 +163,29 @@ void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu } } +/*! + * brief Disable an on-chip internal modules' event as the wakeup sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch(event) + { + case kWUU_InternalModuleInterrupt: + base->ME &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + /*! * brief Configs and Enables Pin filters. * diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.h index 8233c08e5d..bedfde5685 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wuu.h @@ -1,11 +1,11 @@ /* - * Copyright 2019-2022 NXP. + * Copyright 2019-2024 NXP. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_WUU_H_ -#define _FSL_WUU_H_ +#ifndef FSL_WUU_H_ +#define FSL_WUU_H_ #include "fsl_common.h" @@ -17,10 +17,10 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ -/*! @brief Defines WUU driver version 2.2.0. */ -#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) -/*@}*/ +/*! @{ */ +/*! @brief Defines WUU driver version 2.4.0. */ +#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*! @} */ /*! * @brief External WakeUp pin edge detection enumeration. @@ -135,6 +135,14 @@ extern "C" { */ void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config); +/*! + * @brief Disable and clear external wakeup pin settings. + * + * @param base MUU peripheral base address. + * @param pinIndex The index of the external input pin. + */ +void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex); + /*! * @brief Gets External Wakeup pin flags. * @@ -160,7 +168,7 @@ static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask { base->PF = mask; } -/* @} */ +/*! @} */ /*! * @name Internal Wakeup Module control APIs. @@ -178,6 +186,15 @@ static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask */ void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); +/*! + * @brief Disable an on-chip internal modules' event as the wakeup sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + #if (defined(FSL_FEATURE_WUU_HAS_MF) && FSL_FEATURE_WUU_HAS_MF) /*! * @brief Get wakeup flags for internal wakeup modules. @@ -206,7 +223,7 @@ static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t modu } #endif /* FSL_FEATURE_WUU_HAS_MF */ -/* @} */ +/*! @} */ /*! * @name Pin Filter Control APIs @@ -266,7 +283,7 @@ bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); * param pinIndex A pin index, which starts from 0. */ void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); -/* @} */ +/*! @} */ #if defined(__cplusplus) } @@ -274,4 +291,4 @@ void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); /*! @} */ -#endif /*_FSL_WUU_H_*/ +#endif /*FSL_WUU_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wwdt.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wwdt.h index 2546253496..40c90e48b3 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wwdt.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_wwdt.h @@ -5,8 +5,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_WWDT_H_ -#define _FSL_WWDT_H_ +#ifndef FSL_WWDT_H_ +#define FSL_WWDT_H_ #include "fsl_common.h" @@ -22,16 +22,16 @@ *******************************************************************************/ /*! @name Driver version */ -/*@{*/ +/*! @{ */ /*! @brief Defines WWDT driver version. */ #define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) -/*@}*/ +/*! @} */ /*! @name Refresh sequence */ -/*@{*/ +/*! @{ */ #define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ #define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ -/*@}*/ +/*! @} */ /*! @brief Describes WWDT configuration structure. */ typedef struct _wwdt_config @@ -126,7 +126,7 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); */ void WWDT_Deinit(WWDT_Type *base); -/* @} */ +/*! @} */ /*! * @name WWDT Functional Operation @@ -265,7 +265,7 @@ static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) */ void WWDT_Refresh(WWDT_Type *base); -/*@}*/ +/*! @} */ #if defined(__cplusplus) } @@ -273,4 +273,4 @@ void WWDT_Refresh(WWDT_Type *base); /*! @}*/ -#endif /* _FSL_WWDT_H_ */ +#endif /* FSL_WWDT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_efuse.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_efuse.h index 7f6c1ba934..53f4004775 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_efuse.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_efuse.h @@ -6,8 +6,8 @@ * */ -#ifndef _FSL_EFUSE_H_ -#define _FSL_EFUSE_H_ +#ifndef FSL_EFUSE_H_ +#define FSL_EFUSE_H_ #include "fsl_flash.h" @@ -101,12 +101,12 @@ status_t EFUSE_Read(uint32_t addr, uint32_t *data); */ status_t EFUSE_Program(uint32_t addr, uint32_t data); -/*@}*/ +/*! @} */ #ifdef __cplusplus } #endif -/*@}*/ +/*! @} */ -#endif /*! _FSL_EFUSE_H_ */ +#endif /*! FSL_EFUSE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash.h index 06942493c2..012f22e7be 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash.h @@ -6,8 +6,8 @@ * */ -#ifndef _FSL_FLASH_H_ -#define _FSL_FLASH_H_ +#ifndef FSL_FLASH_H_ +#define FSL_FLASH_H_ #include "fsl_common.h" /*! @@ -40,7 +40,7 @@ enum _flash_driver_version_constants kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ }; -/*@}*/ +/*! @} */ /*! * @name Flash driver support feature @@ -48,7 +48,7 @@ enum _flash_driver_version_constants */ #define FSL_FEATURE_SYSCON_HAS_FLASH_HIDING 1U -/*@}*/ +/*! @} */ /*! * @name Flash status @@ -137,7 +137,7 @@ enum kStatus_FLASH_CommandOperationInProgress = MAKE_STATUS( kStatusGroupFlashDriver, 0x34), /*!< The flash state is busy, indicate that a flash command in progress. */ }; -/*@}*/ +/*! @} */ /*! * @name Flash API key @@ -159,7 +159,7 @@ enum _flash_driver_api_keys { kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ }; -/*@}*/ +/*! @} */ /*! * @brief Enumeration for various flash properties. @@ -349,7 +349,7 @@ status_t FLASH_Init(flash_config_t *config); */ status_t FLASH_Deinit(flash_config_t *config); -/*@}*/ +/*! @} */ /*! * @name Erasing @@ -383,7 +383,7 @@ status_t FLASH_Deinit(flash_config_t *config); */ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -/*@}*/ +/*! @} */ /*! * @name Programming @@ -447,7 +447,7 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin */ status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); -/*@}*/ +/*! @} */ /*! * @name Verification @@ -517,7 +517,7 @@ status_t FLASH_VerifyProgram(flash_config_t *config, uint32_t *failedAddress, uint32_t *failedData); -/*@}*/ +/*! @} */ /*! * @name Properties @@ -538,7 +538,7 @@ status_t FLASH_VerifyProgram(flash_config_t *config, */ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); -/*@}*/ +/*! @} */ /*! * @name CustKeyStore @@ -558,7 +558,7 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro */ status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -/*@}*/ +/*! @} */ /*! * @name flash status @@ -580,12 +580,12 @@ status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); #endif -/*@}*/ +/*! @} */ #ifdef __cplusplus } #endif -/*@}*/ +/*! @} */ #endif /* _FLASH_FLASH_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash_ffr.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash_ffr.h index fe3b127676..a8e2caf1c2 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash_ffr.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flash_ffr.h @@ -6,8 +6,8 @@ * */ -#ifndef _FSL_FLASH_FFR_H_ -#define _FSL_FLASH_FFR_H_ +#ifndef FSL_FLASH_FFR_H_ +#define FSL_FLASH_FFR_H_ #include "fsl_flash.h" @@ -522,7 +522,7 @@ status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bo status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); /*! - * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. * * @param config A pointer to the storage for the driver runtime state. @@ -580,12 +580,12 @@ status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStor */ status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); -/*@}*/ +/*! @} */ #ifdef __cplusplus } #endif -/*@}*/ +/*! @} */ -#endif /*! _FSL_FLASH_FFR_H_ */ +#endif /*! FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flexspi_nor_flash.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flexspi_nor_flash.h index 858609fe59..6965988e95 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flexspi_nor_flash.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/fsl_flexspi_nor_flash.h @@ -6,8 +6,8 @@ * */ -#ifndef _FSL_FLEXSPI_NOR_FLASH_H__ -#define _FSL_FLEXSPI_NOR_FLASH_H__ +#ifndef FSL_FLEXSPI_NOR_FLASH_H__ +#define FSL_FLEXSPI_NOR_FLASH_H__ #include "fsl_common.h" /*! @@ -298,7 +298,7 @@ enum kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ }; -/*@}*/ +/*! @} */ /*! @brief Manufacturer ID */ enum @@ -718,4 +718,4 @@ void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32 } #endif -#endif /*! _FSL_FLEXSPI_NOR_FLASH_H__ */ +#endif /*! FSL_FLEXSPI_NOR_FLASH_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/src/fsl_flash.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/src/fsl_flash.c index 5e7bca736f..c6450b5a0b 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/src/fsl_flash.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/flash/src/fsl_flash.c @@ -43,7 +43,7 @@ typedef union StandardVersion uint8_t major; /*!< major version [23:16] */ char name; /*!< name [31:24] */ }; - uint32_t version; /*!< combined version numbers */ + uint32_t version; /*!< combined version numbers */ } standard_version_t; /*! @brief Interface for the flash driver.*/ @@ -368,7 +368,7 @@ status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint } /*! - * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. */ status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) @@ -477,10 +477,10 @@ status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) /*! * @brief Configure FlexSPI Lookup table */ -status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq) +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber) { assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->update_lut(instance, seqIndex, lutBase, numberOfSeq); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber); } /*! @@ -538,5 +538,31 @@ status_t EFUSE_Read(uint32_t addr, uint32_t *data) status_t EFUSE_Program(uint32_t addr, uint32_t data) { assert(BOOTLOADER_API_TREE_POINTER); - return BOOTLOADER_API_TREE_POINTER->efuseDriver->program(addr, data); + status_t status; + bool is_hvd_enabled = false; + + /* Workaround for ROM Errata ERR052108 */ + /* Disable SYS_HVD */ + if (0U != (SPC0->ACTIVE_CFG & SPC_ACTIVE_CFG_SYS_HVDE_MASK)) + { + is_hvd_enabled = true; + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + /* Call ROM API to program efuse */ + status = BOOTLOADER_API_TREE_POINTER->efuseDriver->program(addr, data); + + /* Bring VDD_SYS back to 1.8v */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK; + + /* Wait for voltage to settle */ + SDK_DelayAtLeastUs(5000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enable SYS_HVD back */ + if (is_hvd_enabled) + { + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_mem_interface.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_mem_interface.h index 6d99e708fc..98147b6baf 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_mem_interface.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_mem_interface.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_MEM_INTERFACE_H_ -#define _FSL_MEM_INTERFACE_H_ +#ifndef FSL_MEM_INTERFACE_H_ +#define FSL_MEM_INTERFACE_H_ #include "fsl_sbloader.h" #include "fsl_common.h" @@ -376,4 +376,4 @@ status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId); * @} */ -#endif /* _FSL_MEM_INTERFACE_H_ */ +#endif /* FSL_MEM_INTERFACE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader.h index 1c4c8d5b87..1f2f14bee7 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SBLOADER_H_ -#define _FSL_SBLOADER_H_ +#ifndef FSL_SBLOADER_H_ +#define FSL_SBLOADER_H_ #include "fsl_flash.h" #include "fsl_flexspi_nor_flash.h" @@ -286,7 +286,7 @@ typedef struct memory_context_struct typedef struct api_memory_region_interface { status_t (*init)(mem_attribute_t *attr); -#if ROM_API_HAS_FEATURE_MEM_READ +#if (defined(ROM_API_HAS_FEATURE_MEM_READ) && ROM_API_HAS_FEATURE_MEM_READ) status_t (*read)(mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf); #endif status_t (*write)(mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf); @@ -370,4 +370,4 @@ status_t Sbloader_Finalize(api_core_context_t *ctx); /*! @}*/ -#endif /* _FSL_SBLOADER_H_ */ +#endif /* FSL_SBLOADER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader_v3.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader_v3.h index b16ef82338..795d8f19e7 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader_v3.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/mem_interface/fsl_sbloader_v3.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_SBLOADER_V3_H_ -#define _FSL_SBLOADER_V3_H_ +#ifndef FSL_SBLOADER_V3_H_ +#define FSL_SBLOADER_V3_H_ #include @@ -268,4 +268,4 @@ struct _ldr_Context_v3 /*! @} */ -#endif /* _FSL_SBLOADER_V3_H_ */ +#endif /* FSL_SBLOADER_V3_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot.h index 88520059dc..f1cca4da17 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_NBOOT_H_ -#define _FSL_NBOOT_H_ +#ifndef FSL_NBOOT_H_ +#define FSL_NBOOT_H_ #include "fsl_common.h" @@ -343,4 +343,4 @@ nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, * @} */ -#endif /* _FSL_NBOOT_H_ */ +#endif /* FSL_NBOOT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot_hal.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot_hal.h index acd4701046..79e0dd490e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot_hal.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/fsl_nboot_hal.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_NBOOT_HAL_H_ -#define _FSL_NBOOT_HAL_H_ +#ifndef FSL_NBOOT_HAL_H_ +#define FSL_NBOOT_HAL_H_ #include "fsl_nboot.h" @@ -228,4 +228,4 @@ typedef enum _nboot_hash_algo_t /*! @} */ -#endif /*_FSL_NBOOT_HAL_H_ */ +#endif /*FSL_NBOOT_HAL_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/src/fsl_nboot.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/src/fsl_nboot.c index 5e3b8a420c..909be4ae3e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/src/fsl_nboot.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/nboot/src/fsl_nboot.c @@ -10,6 +10,11 @@ /******************************************************************************* * Definitions ******************************************************************************/ +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.nboot" +#endif + #define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) /** diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/runbootloader/fsl_runbootloader.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/runbootloader/fsl_runbootloader.h index e4e5baa7b4..de0ed4a9c5 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/runbootloader/fsl_runbootloader.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/romapi/runbootloader/fsl_runbootloader.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _FSL_RUN_BOOTLOADER_H_ -#define _FSL_RUN_BOOTLOADER_H_ +#ifndef FSL_RUN_BOOTLOADER_H_ +#define FSL_RUN_BOOTLOADER_H_ #include "fsl_common.h" @@ -18,15 +18,15 @@ ******************************************************************************/ /* API prototype fields definition. -| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | - | Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | -| | | | Used For Boot mode 0| | | -| | 0: Passive mode | 0 - Auto detection | | | | -| | 1: ISP mode | 1 - USB-HID | | | | -| | | 2 - UART | | | | -| | | 3 - SPI | | | | -| | | 4 - I2C | | | | -| | | 5 - CAN | | | | +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | + | Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | */ typedef struct @@ -69,4 +69,4 @@ void bootloader_user_entry(void *arg); * @} */ -#endif /* _FSL_RUN_BOOTLOADER_H_ */ +#endif /* FSL_RUN_BOOTLOADER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/fsl_device_registers.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/fsl_device_registers.h index dd63783f59..3678503d1e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/fsl_device_registers.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/fsl_device_registers.h @@ -1,8 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2016-2023 NXP - * All rights reserved. - * * SPDX-License-Identifier: BSD-3-Clause * */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core0.S b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core0.S index 23ccf875ea..2cac371b57 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core0.S +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core0.S @@ -2,15 +2,13 @@ /* @file: startup_MCXN947_cm33_core0.s */ /* @purpose: CMSIS Cortex-M33 Core Device Startup File */ /* MCXN947_cm33_core0 */ -/* @version: 1.0 */ -/* @date: 2022-10-1 */ -/* @build: b230131 */ +/* @version: 2.0 */ +/* @date: 2023-2-1 */ +/* @build: b240410 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2023 NXP */ -/* All rights reserved. */ -/* */ +/* Copyright 2016-2024 NXP */ /* SPDX-License-Identifier: BSD-3-Clause */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ @@ -164,14 +162,14 @@ __Vectors: .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ - .long ENC0_COMPARE_IRQHandler /* ENC0_Compare interrupt*/ - .long ENC0_HOME_IRQHandler /* ENC0_Home interrupt*/ - .long ENC0_WDG_SAB_IRQHandler /* ENC0_WDG_IRQ/SAB interrupt*/ - .long ENC0_IDX_IRQHandler /* ENC0_IDX interrupt*/ - .long ENC1_COMPARE_IRQHandler /* ENC1_Compare interrupt*/ - .long ENC1_HOME_IRQHandler /* ENC1_Home interrupt*/ - .long ENC1_WDG_SAB_IRQHandler /* ENC1_WDG_IRQ/SAB interrupt*/ - .long ENC1_IDX_IRQHandler /* ENC1_IDX interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ .long BSP32_IRQHandler /* CoolFlux BSP32 interrupt*/ .long ELS_ERR_IRQHandler /* ELS error interrupt*/ @@ -190,8 +188,8 @@ __Vectors: .long WUU_IRQHandler /* Wake Up Unit interrupt*/ .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ .long ETB0_IRQHandler /* ETB counter expires interrupt*/ - .long SM3_IRQHandler /* Secure Generic Interface (SGI) SAFO interrupt */ - .long TRNG0_IRQHandler /* True Random Number Generator interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ @@ -202,6 +200,11 @@ __Vectors: .text .thumb +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#endif +#endif /* Reset Handler */ .thumb_func @@ -296,8 +299,12 @@ Reset_Handler: /*End of stack / heap initializaiton */ cpsie i /* Unmask interrupts */ #ifndef __START +#ifdef __REDLIB__ +#define __START __main +#else #define __START _start #endif +#endif #ifndef __ATOLLIC__ ldr r0,=__START blx r0 @@ -1481,75 +1488,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler: .align 1 .thumb_func - .weak ENC0_COMPARE_IRQHandler - .type ENC0_COMPARE_IRQHandler, %function -ENC0_COMPARE_IRQHandler: - ldr r0,=ENC0_COMPARE_DriverIRQHandler + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler bx r0 - .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC0_HOME_IRQHandler - .type ENC0_HOME_IRQHandler, %function -ENC0_HOME_IRQHandler: - ldr r0,=ENC0_HOME_DriverIRQHandler + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler bx r0 - .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler .align 1 .thumb_func - .weak ENC0_WDG_SAB_IRQHandler - .type ENC0_WDG_SAB_IRQHandler, %function -ENC0_WDG_SAB_IRQHandler: - ldr r0,=ENC0_WDG_SAB_DriverIRQHandler + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler bx r0 - .size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC0_IDX_IRQHandler - .type ENC0_IDX_IRQHandler, %function -ENC0_IDX_IRQHandler: - ldr r0,=ENC0_IDX_DriverIRQHandler + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler bx r0 - .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler .align 1 .thumb_func - .weak ENC1_COMPARE_IRQHandler - .type ENC1_COMPARE_IRQHandler, %function -ENC1_COMPARE_IRQHandler: - ldr r0,=ENC1_COMPARE_DriverIRQHandler + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler bx r0 - .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC1_HOME_IRQHandler - .type ENC1_HOME_IRQHandler, %function -ENC1_HOME_IRQHandler: - ldr r0,=ENC1_HOME_DriverIRQHandler + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler bx r0 - .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler .align 1 .thumb_func - .weak ENC1_WDG_SAB_IRQHandler - .type ENC1_WDG_SAB_IRQHandler, %function -ENC1_WDG_SAB_IRQHandler: - ldr r0,=ENC1_WDG_SAB_DriverIRQHandler + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler bx r0 - .size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC1_IDX_IRQHandler - .type ENC1_IDX_IRQHandler, %function -ENC1_IDX_IRQHandler: - ldr r0,=ENC1_IDX_DriverIRQHandler + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler bx r0 - .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler .align 1 .thumb_func @@ -1715,21 +1722,21 @@ ETB0_IRQHandler: .align 1 .thumb_func - .weak SM3_IRQHandler - .type SM3_IRQHandler, %function -SM3_IRQHandler: - ldr r0,=SM3_DriverIRQHandler + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler bx r0 - .size SM3_IRQHandler, . - SM3_IRQHandler + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler .align 1 .thumb_func - .weak TRNG0_IRQHandler - .type TRNG0_IRQHandler, %function -TRNG0_IRQHandler: - ldr r0,=TRNG0_DriverIRQHandler + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler bx r0 - .size TRNG0_IRQHandler, . - TRNG0_IRQHandler + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler .align 1 .thumb_func @@ -1905,14 +1912,14 @@ CTI0_IRQHandler: def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler - def_irq_handler ENC0_COMPARE_DriverIRQHandler - def_irq_handler ENC0_HOME_DriverIRQHandler - def_irq_handler ENC0_WDG_SAB_DriverIRQHandler - def_irq_handler ENC0_IDX_DriverIRQHandler - def_irq_handler ENC1_COMPARE_DriverIRQHandler - def_irq_handler ENC1_HOME_DriverIRQHandler - def_irq_handler ENC1_WDG_SAB_DriverIRQHandler - def_irq_handler ENC1_IDX_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler def_irq_handler ITRC0_DriverIRQHandler def_irq_handler BSP32_DriverIRQHandler def_irq_handler ELS_ERR_DriverIRQHandler @@ -1931,8 +1938,8 @@ CTI0_IRQHandler: def_irq_handler WUU_DriverIRQHandler def_irq_handler PORT_EFT_DriverIRQHandler def_irq_handler ETB0_DriverIRQHandler - def_irq_handler SM3_DriverIRQHandler - def_irq_handler TRNG0_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler def_irq_handler WWDT0_DriverIRQHandler def_irq_handler WWDT1_DriverIRQHandler def_irq_handler CMC0_DriverIRQHandler diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core1.S b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core1.S index c0c24d4868..1e528bcd12 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core1.S +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/gcc/startup_MCXN947_cm33_core1.S @@ -2,15 +2,13 @@ /* @file: startup_MCXN947_cm33_core1.s */ /* @purpose: CMSIS Cortex-M33 Core Device Startup File */ /* MCXN947_cm33_core1 */ -/* @version: 1.0 */ -/* @date: 2022-10-1 */ -/* @build: b230131 */ +/* @version: 2.0 */ +/* @date: 2023-2-1 */ +/* @build: b240410 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2023 NXP */ -/* All rights reserved. */ -/* */ +/* Copyright 2016-2024 NXP */ /* SPDX-License-Identifier: BSD-3-Clause */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ @@ -164,14 +162,14 @@ __Vectors: .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ - .long ENC0_COMPARE_IRQHandler /* ENC0_Compare interrupt*/ - .long ENC0_HOME_IRQHandler /* ENC0_Home interrupt*/ - .long ENC0_WDG_SAB_IRQHandler /* ENC0_WDG_IRQ/SAB interrupt*/ - .long ENC0_IDX_IRQHandler /* ENC0_IDX interrupt*/ - .long ENC1_COMPARE_IRQHandler /* ENC1_Compare interrupt*/ - .long ENC1_HOME_IRQHandler /* ENC1_Home interrupt*/ - .long ENC1_WDG_SAB_IRQHandler /* ENC1_WDG_IRQ/SAB interrupt*/ - .long ENC1_IDX_IRQHandler /* ENC1_IDX interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ .long BSP32_IRQHandler /* CoolFlux BSP32 interrupt*/ .long ELS_ERR_IRQHandler /* ELS error interrupt*/ @@ -190,8 +188,8 @@ __Vectors: .long WUU_IRQHandler /* Wake Up Unit interrupt*/ .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ .long ETB0_IRQHandler /* ETB counter expires interrupt*/ - .long SM3_IRQHandler /* Secure Generic Interface (SGI) SAFO interrupt */ - .long TRNG0_IRQHandler /* True Random Number Generator interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ @@ -202,6 +200,11 @@ __Vectors: .text .thumb +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#endif +#endif /* Reset Handler */ .thumb_func @@ -287,8 +290,12 @@ Reset_Handler: /*End of stack / heap initializaiton */ cpsie i /* Unmask interrupts */ #ifndef __START +#ifdef __REDLIB__ +#define __START __main +#else #define __START _start #endif +#endif #ifndef __ATOLLIC__ ldr r0,=__START blx r0 @@ -1472,75 +1479,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler: .align 1 .thumb_func - .weak ENC0_COMPARE_IRQHandler - .type ENC0_COMPARE_IRQHandler, %function -ENC0_COMPARE_IRQHandler: - ldr r0,=ENC0_COMPARE_DriverIRQHandler + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler bx r0 - .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC0_HOME_IRQHandler - .type ENC0_HOME_IRQHandler, %function -ENC0_HOME_IRQHandler: - ldr r0,=ENC0_HOME_DriverIRQHandler + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler bx r0 - .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler .align 1 .thumb_func - .weak ENC0_WDG_SAB_IRQHandler - .type ENC0_WDG_SAB_IRQHandler, %function -ENC0_WDG_SAB_IRQHandler: - ldr r0,=ENC0_WDG_SAB_DriverIRQHandler + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler bx r0 - .size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC0_IDX_IRQHandler - .type ENC0_IDX_IRQHandler, %function -ENC0_IDX_IRQHandler: - ldr r0,=ENC0_IDX_DriverIRQHandler + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler bx r0 - .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler .align 1 .thumb_func - .weak ENC1_COMPARE_IRQHandler - .type ENC1_COMPARE_IRQHandler, %function -ENC1_COMPARE_IRQHandler: - ldr r0,=ENC1_COMPARE_DriverIRQHandler + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler bx r0 - .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler .align 1 .thumb_func - .weak ENC1_HOME_IRQHandler - .type ENC1_HOME_IRQHandler, %function -ENC1_HOME_IRQHandler: - ldr r0,=ENC1_HOME_DriverIRQHandler + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler bx r0 - .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler .align 1 .thumb_func - .weak ENC1_WDG_SAB_IRQHandler - .type ENC1_WDG_SAB_IRQHandler, %function -ENC1_WDG_SAB_IRQHandler: - ldr r0,=ENC1_WDG_SAB_DriverIRQHandler + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler bx r0 - .size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler .align 1 .thumb_func - .weak ENC1_IDX_IRQHandler - .type ENC1_IDX_IRQHandler, %function -ENC1_IDX_IRQHandler: - ldr r0,=ENC1_IDX_DriverIRQHandler + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler bx r0 - .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler .align 1 .thumb_func @@ -1706,21 +1713,21 @@ ETB0_IRQHandler: .align 1 .thumb_func - .weak SM3_IRQHandler - .type SM3_IRQHandler, %function -SM3_IRQHandler: - ldr r0,=SM3_DriverIRQHandler + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler bx r0 - .size SM3_IRQHandler, . - SM3_IRQHandler + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler .align 1 .thumb_func - .weak TRNG0_IRQHandler - .type TRNG0_IRQHandler, %function -TRNG0_IRQHandler: - ldr r0,=TRNG0_DriverIRQHandler + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler bx r0 - .size TRNG0_IRQHandler, . - TRNG0_IRQHandler + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler .align 1 .thumb_func @@ -1896,14 +1903,14 @@ CTI0_IRQHandler: def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler - def_irq_handler ENC0_COMPARE_DriverIRQHandler - def_irq_handler ENC0_HOME_DriverIRQHandler - def_irq_handler ENC0_WDG_SAB_DriverIRQHandler - def_irq_handler ENC0_IDX_DriverIRQHandler - def_irq_handler ENC1_COMPARE_DriverIRQHandler - def_irq_handler ENC1_HOME_DriverIRQHandler - def_irq_handler ENC1_WDG_SAB_DriverIRQHandler - def_irq_handler ENC1_IDX_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler def_irq_handler ITRC0_DriverIRQHandler def_irq_handler BSP32_DriverIRQHandler def_irq_handler ELS_ERR_DriverIRQHandler @@ -1922,8 +1929,8 @@ CTI0_IRQHandler: def_irq_handler WUU_DriverIRQHandler def_irq_handler PORT_EFT_DriverIRQHandler def_irq_handler ETB0_DriverIRQHandler - def_irq_handler SM3_DriverIRQHandler - def_irq_handler TRNG0_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler def_irq_handler WWDT0_DriverIRQHandler def_irq_handler WWDT1_DriverIRQHandler def_irq_handler CMC0_DriverIRQHandler diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core0.s b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core0.s index 567defbd66..35a27f3241 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core0.s +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core0.s @@ -2,15 +2,13 @@ ; @file: startup_MCXN947_cm33_core0.s ; @purpose: CMSIS Cortex-M33 Core Device Startup File ; MCXN947_cm33_core0 -; @version: 1.0 -; @date: 2022-10-1 -; @build: b230131 +; @version: 2.0 +; @date: 2023-2-1 +; @build: b240410 ; ------------------------------------------------------------------------- ; ; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2023 NXP -; All rights reserved. -; +; Copyright 2016-2024 NXP ; SPDX-License-Identifier: BSD-3-Clause ; ; The modules in this file are included in the libraries, and may be replaced @@ -193,14 +191,14 @@ __vector_table_0x1c DCD FLEXPWM1_SUBMODULE1_IRQHandler ;FlexPWM1 Submodule 1 capture/compare/reload interrupt DCD FLEXPWM1_SUBMODULE2_IRQHandler ;FlexPWM1 Submodule 2 capture/compare/reload interrupt DCD FLEXPWM1_SUBMODULE3_IRQHandler ;FlexPWM1 Submodule 3 capture/compare/reload interrupt - DCD ENC0_COMPARE_IRQHandler ;ENC0_Compare interrupt - DCD ENC0_HOME_IRQHandler ;ENC0_Home interrupt - DCD ENC0_WDG_SAB_IRQHandler ;ENC0_WDG_IRQ/SAB interrupt - DCD ENC0_IDX_IRQHandler ;ENC0_IDX interrupt - DCD ENC1_COMPARE_IRQHandler ;ENC1_Compare interrupt - DCD ENC1_HOME_IRQHandler ;ENC1_Home interrupt - DCD ENC1_WDG_SAB_IRQHandler ;ENC1_WDG_IRQ/SAB interrupt - DCD ENC1_IDX_IRQHandler ;ENC1_IDX interrupt + DCD QDC0_COMPARE_IRQHandler ;QDC0_Compare interrupt + DCD QDC0_HOME_IRQHandler ;QDC0_Home interrupt + DCD QDC0_WDG_SAB_IRQHandler ;QDC0_WDG_IRQ/SAB interrupt + DCD QDC0_IDX_IRQHandler ;QDC0_IDX interrupt + DCD QDC1_COMPARE_IRQHandler ;QDC1_Compare interrupt + DCD QDC1_HOME_IRQHandler ;QDC1_Home interrupt + DCD QDC1_WDG_SAB_IRQHandler ;QDC1_WDG_IRQ/SAB interrupt + DCD QDC1_IDX_IRQHandler ;QDC1_IDX interrupt DCD ITRC0_IRQHandler ;Intrusion and Tamper Response Controller interrupt DCD BSP32_IRQHandler ;CoolFlux BSP32 interrupt DCD ELS_ERR_IRQHandler ;ELS error interrupt @@ -219,8 +217,8 @@ __vector_table_0x1c DCD WUU_IRQHandler ;Wake Up Unit interrupt DCD PORT_EFT_IRQHandler ;PORT0~5 EFT interrupt DCD ETB0_IRQHandler ;ETB counter expires interrupt - DCD SM3_IRQHandler ;Secure Generic Interface (SGI) SAFO interrupt - DCD TRNG0_IRQHandler ;True Random Number Generator interrupt + DCD Reserved166_IRQHandler ;Reserved interrupt + DCD Reserved167_IRQHandler ;Reserved interrupt DCD WWDT0_IRQHandler ;Windowed Watchdog Timer 0 interrupt DCD WWDT1_IRQHandler ;Windowed Watchdog Timer 1 interrupt DCD CMC0_IRQHandler ;Core Mode Controller interrupt @@ -1172,60 +1170,60 @@ FLEXPWM1_SUBMODULE3_IRQHandler LDR R0, =FLEXPWM1_SUBMODULE3_DriverIRQHandler BX R0 - PUBWEAK ENC0_COMPARE_IRQHandler - PUBWEAK ENC0_COMPARE_DriverIRQHandler + PUBWEAK QDC0_COMPARE_IRQHandler + PUBWEAK QDC0_COMPARE_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_COMPARE_IRQHandler - LDR R0, =ENC0_COMPARE_DriverIRQHandler +QDC0_COMPARE_IRQHandler + LDR R0, =QDC0_COMPARE_DriverIRQHandler BX R0 - PUBWEAK ENC0_HOME_IRQHandler - PUBWEAK ENC0_HOME_DriverIRQHandler + PUBWEAK QDC0_HOME_IRQHandler + PUBWEAK QDC0_HOME_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_HOME_IRQHandler - LDR R0, =ENC0_HOME_DriverIRQHandler +QDC0_HOME_IRQHandler + LDR R0, =QDC0_HOME_DriverIRQHandler BX R0 - PUBWEAK ENC0_WDG_SAB_IRQHandler - PUBWEAK ENC0_WDG_SAB_DriverIRQHandler + PUBWEAK QDC0_WDG_SAB_IRQHandler + PUBWEAK QDC0_WDG_SAB_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_WDG_SAB_IRQHandler - LDR R0, =ENC0_WDG_SAB_DriverIRQHandler +QDC0_WDG_SAB_IRQHandler + LDR R0, =QDC0_WDG_SAB_DriverIRQHandler BX R0 - PUBWEAK ENC0_IDX_IRQHandler - PUBWEAK ENC0_IDX_DriverIRQHandler + PUBWEAK QDC0_IDX_IRQHandler + PUBWEAK QDC0_IDX_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_IDX_IRQHandler - LDR R0, =ENC0_IDX_DriverIRQHandler +QDC0_IDX_IRQHandler + LDR R0, =QDC0_IDX_DriverIRQHandler BX R0 - PUBWEAK ENC1_COMPARE_IRQHandler - PUBWEAK ENC1_COMPARE_DriverIRQHandler + PUBWEAK QDC1_COMPARE_IRQHandler + PUBWEAK QDC1_COMPARE_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_COMPARE_IRQHandler - LDR R0, =ENC1_COMPARE_DriverIRQHandler +QDC1_COMPARE_IRQHandler + LDR R0, =QDC1_COMPARE_DriverIRQHandler BX R0 - PUBWEAK ENC1_HOME_IRQHandler - PUBWEAK ENC1_HOME_DriverIRQHandler + PUBWEAK QDC1_HOME_IRQHandler + PUBWEAK QDC1_HOME_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_HOME_IRQHandler - LDR R0, =ENC1_HOME_DriverIRQHandler +QDC1_HOME_IRQHandler + LDR R0, =QDC1_HOME_DriverIRQHandler BX R0 - PUBWEAK ENC1_WDG_SAB_IRQHandler - PUBWEAK ENC1_WDG_SAB_DriverIRQHandler + PUBWEAK QDC1_WDG_SAB_IRQHandler + PUBWEAK QDC1_WDG_SAB_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_WDG_SAB_IRQHandler - LDR R0, =ENC1_WDG_SAB_DriverIRQHandler +QDC1_WDG_SAB_IRQHandler + LDR R0, =QDC1_WDG_SAB_DriverIRQHandler BX R0 - PUBWEAK ENC1_IDX_IRQHandler - PUBWEAK ENC1_IDX_DriverIRQHandler + PUBWEAK QDC1_IDX_IRQHandler + PUBWEAK QDC1_IDX_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_IDX_IRQHandler - LDR R0, =ENC1_IDX_DriverIRQHandler +QDC1_IDX_IRQHandler + LDR R0, =QDC1_IDX_DriverIRQHandler BX R0 PUBWEAK ITRC0_IRQHandler @@ -1354,18 +1352,18 @@ ETB0_IRQHandler LDR R0, =ETB0_DriverIRQHandler BX R0 - PUBWEAK SM3_IRQHandler - PUBWEAK SM3_DriverIRQHandler + PUBWEAK Reserved166_IRQHandler + PUBWEAK Reserved166_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -SM3_IRQHandler - LDR R0, =SM3_DriverIRQHandler +Reserved166_IRQHandler + LDR R0, =Reserved166_DriverIRQHandler BX R0 - PUBWEAK TRNG0_IRQHandler - PUBWEAK TRNG0_DriverIRQHandler + PUBWEAK Reserved167_IRQHandler + PUBWEAK Reserved167_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -TRNG0_IRQHandler - LDR R0, =TRNG0_DriverIRQHandler +Reserved167_IRQHandler + LDR R0, =Reserved167_DriverIRQHandler BX R0 PUBWEAK WWDT0_IRQHandler @@ -1520,14 +1518,14 @@ FLEXPWM1_SUBMODULE0_DriverIRQHandler FLEXPWM1_SUBMODULE1_DriverIRQHandler FLEXPWM1_SUBMODULE2_DriverIRQHandler FLEXPWM1_SUBMODULE3_DriverIRQHandler -ENC0_COMPARE_DriverIRQHandler -ENC0_HOME_DriverIRQHandler -ENC0_WDG_SAB_DriverIRQHandler -ENC0_IDX_DriverIRQHandler -ENC1_COMPARE_DriverIRQHandler -ENC1_HOME_DriverIRQHandler -ENC1_WDG_SAB_DriverIRQHandler -ENC1_IDX_DriverIRQHandler +QDC0_COMPARE_DriverIRQHandler +QDC0_HOME_DriverIRQHandler +QDC0_WDG_SAB_DriverIRQHandler +QDC0_IDX_DriverIRQHandler +QDC1_COMPARE_DriverIRQHandler +QDC1_HOME_DriverIRQHandler +QDC1_WDG_SAB_DriverIRQHandler +QDC1_IDX_DriverIRQHandler ITRC0_DriverIRQHandler BSP32_DriverIRQHandler ELS_ERR_DriverIRQHandler @@ -1546,8 +1544,8 @@ SPC_DriverIRQHandler WUU_DriverIRQHandler PORT_EFT_DriverIRQHandler ETB0_DriverIRQHandler -SM3_DriverIRQHandler -TRNG0_DriverIRQHandler +Reserved166_DriverIRQHandler +Reserved167_DriverIRQHandler WWDT0_DriverIRQHandler WWDT1_DriverIRQHandler CMC0_DriverIRQHandler diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core1.s b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core1.s index 63c748540c..6418f2b2ae 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core1.s +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/iar/startup_MCXN947_cm33_core1.s @@ -2,15 +2,13 @@ ; @file: startup_MCXN947_cm33_core1.s ; @purpose: CMSIS Cortex-M33 Core Device Startup File ; MCXN947_cm33_core1 -; @version: 1.0 -; @date: 2022-10-1 -; @build: b230131 +; @version: 2.0 +; @date: 2023-2-1 +; @build: b240410 ; ------------------------------------------------------------------------- ; ; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2023 NXP -; All rights reserved. -; +; Copyright 2016-2024 NXP ; SPDX-License-Identifier: BSD-3-Clause ; ; The modules in this file are included in the libraries, and may be replaced @@ -193,14 +191,14 @@ __vector_table_0x1c DCD FLEXPWM1_SUBMODULE1_IRQHandler ;FlexPWM1 Submodule 1 capture/compare/reload interrupt DCD FLEXPWM1_SUBMODULE2_IRQHandler ;FlexPWM1 Submodule 2 capture/compare/reload interrupt DCD FLEXPWM1_SUBMODULE3_IRQHandler ;FlexPWM1 Submodule 3 capture/compare/reload interrupt - DCD ENC0_COMPARE_IRQHandler ;ENC0_Compare interrupt - DCD ENC0_HOME_IRQHandler ;ENC0_Home interrupt - DCD ENC0_WDG_SAB_IRQHandler ;ENC0_WDG_IRQ/SAB interrupt - DCD ENC0_IDX_IRQHandler ;ENC0_IDX interrupt - DCD ENC1_COMPARE_IRQHandler ;ENC1_Compare interrupt - DCD ENC1_HOME_IRQHandler ;ENC1_Home interrupt - DCD ENC1_WDG_SAB_IRQHandler ;ENC1_WDG_IRQ/SAB interrupt - DCD ENC1_IDX_IRQHandler ;ENC1_IDX interrupt + DCD QDC0_COMPARE_IRQHandler ;QDC0_Compare interrupt + DCD QDC0_HOME_IRQHandler ;QDC0_Home interrupt + DCD QDC0_WDG_SAB_IRQHandler ;QDC0_WDG_IRQ/SAB interrupt + DCD QDC0_IDX_IRQHandler ;QDC0_IDX interrupt + DCD QDC1_COMPARE_IRQHandler ;QDC1_Compare interrupt + DCD QDC1_HOME_IRQHandler ;QDC1_Home interrupt + DCD QDC1_WDG_SAB_IRQHandler ;QDC1_WDG_IRQ/SAB interrupt + DCD QDC1_IDX_IRQHandler ;QDC1_IDX interrupt DCD ITRC0_IRQHandler ;Intrusion and Tamper Response Controller interrupt DCD BSP32_IRQHandler ;CoolFlux BSP32 interrupt DCD ELS_ERR_IRQHandler ;ELS error interrupt @@ -219,8 +217,8 @@ __vector_table_0x1c DCD WUU_IRQHandler ;Wake Up Unit interrupt DCD PORT_EFT_IRQHandler ;PORT0~5 EFT interrupt DCD ETB0_IRQHandler ;ETB counter expires interrupt - DCD SM3_IRQHandler ;Secure Generic Interface (SGI) SAFO interrupt - DCD TRNG0_IRQHandler ;True Random Number Generator interrupt + DCD Reserved166_IRQHandler ;Reserved interrupt + DCD Reserved167_IRQHandler ;Reserved interrupt DCD WWDT0_IRQHandler ;Windowed Watchdog Timer 0 interrupt DCD WWDT1_IRQHandler ;Windowed Watchdog Timer 1 interrupt DCD CMC0_IRQHandler ;Core Mode Controller interrupt @@ -1165,60 +1163,60 @@ FLEXPWM1_SUBMODULE3_IRQHandler LDR R0, =FLEXPWM1_SUBMODULE3_DriverIRQHandler BX R0 - PUBWEAK ENC0_COMPARE_IRQHandler - PUBWEAK ENC0_COMPARE_DriverIRQHandler + PUBWEAK QDC0_COMPARE_IRQHandler + PUBWEAK QDC0_COMPARE_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_COMPARE_IRQHandler - LDR R0, =ENC0_COMPARE_DriverIRQHandler +QDC0_COMPARE_IRQHandler + LDR R0, =QDC0_COMPARE_DriverIRQHandler BX R0 - PUBWEAK ENC0_HOME_IRQHandler - PUBWEAK ENC0_HOME_DriverIRQHandler + PUBWEAK QDC0_HOME_IRQHandler + PUBWEAK QDC0_HOME_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_HOME_IRQHandler - LDR R0, =ENC0_HOME_DriverIRQHandler +QDC0_HOME_IRQHandler + LDR R0, =QDC0_HOME_DriverIRQHandler BX R0 - PUBWEAK ENC0_WDG_SAB_IRQHandler - PUBWEAK ENC0_WDG_SAB_DriverIRQHandler + PUBWEAK QDC0_WDG_SAB_IRQHandler + PUBWEAK QDC0_WDG_SAB_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_WDG_SAB_IRQHandler - LDR R0, =ENC0_WDG_SAB_DriverIRQHandler +QDC0_WDG_SAB_IRQHandler + LDR R0, =QDC0_WDG_SAB_DriverIRQHandler BX R0 - PUBWEAK ENC0_IDX_IRQHandler - PUBWEAK ENC0_IDX_DriverIRQHandler + PUBWEAK QDC0_IDX_IRQHandler + PUBWEAK QDC0_IDX_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC0_IDX_IRQHandler - LDR R0, =ENC0_IDX_DriverIRQHandler +QDC0_IDX_IRQHandler + LDR R0, =QDC0_IDX_DriverIRQHandler BX R0 - PUBWEAK ENC1_COMPARE_IRQHandler - PUBWEAK ENC1_COMPARE_DriverIRQHandler + PUBWEAK QDC1_COMPARE_IRQHandler + PUBWEAK QDC1_COMPARE_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_COMPARE_IRQHandler - LDR R0, =ENC1_COMPARE_DriverIRQHandler +QDC1_COMPARE_IRQHandler + LDR R0, =QDC1_COMPARE_DriverIRQHandler BX R0 - PUBWEAK ENC1_HOME_IRQHandler - PUBWEAK ENC1_HOME_DriverIRQHandler + PUBWEAK QDC1_HOME_IRQHandler + PUBWEAK QDC1_HOME_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_HOME_IRQHandler - LDR R0, =ENC1_HOME_DriverIRQHandler +QDC1_HOME_IRQHandler + LDR R0, =QDC1_HOME_DriverIRQHandler BX R0 - PUBWEAK ENC1_WDG_SAB_IRQHandler - PUBWEAK ENC1_WDG_SAB_DriverIRQHandler + PUBWEAK QDC1_WDG_SAB_IRQHandler + PUBWEAK QDC1_WDG_SAB_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_WDG_SAB_IRQHandler - LDR R0, =ENC1_WDG_SAB_DriverIRQHandler +QDC1_WDG_SAB_IRQHandler + LDR R0, =QDC1_WDG_SAB_DriverIRQHandler BX R0 - PUBWEAK ENC1_IDX_IRQHandler - PUBWEAK ENC1_IDX_DriverIRQHandler + PUBWEAK QDC1_IDX_IRQHandler + PUBWEAK QDC1_IDX_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -ENC1_IDX_IRQHandler - LDR R0, =ENC1_IDX_DriverIRQHandler +QDC1_IDX_IRQHandler + LDR R0, =QDC1_IDX_DriverIRQHandler BX R0 PUBWEAK ITRC0_IRQHandler @@ -1347,18 +1345,18 @@ ETB0_IRQHandler LDR R0, =ETB0_DriverIRQHandler BX R0 - PUBWEAK SM3_IRQHandler - PUBWEAK SM3_DriverIRQHandler + PUBWEAK Reserved166_IRQHandler + PUBWEAK Reserved166_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -SM3_IRQHandler - LDR R0, =SM3_DriverIRQHandler +Reserved166_IRQHandler + LDR R0, =Reserved166_DriverIRQHandler BX R0 - PUBWEAK TRNG0_IRQHandler - PUBWEAK TRNG0_DriverIRQHandler + PUBWEAK Reserved167_IRQHandler + PUBWEAK Reserved167_DriverIRQHandler SECTION .text:CODE:REORDER:NOROOT(2) -TRNG0_IRQHandler - LDR R0, =TRNG0_DriverIRQHandler +Reserved167_IRQHandler + LDR R0, =Reserved167_DriverIRQHandler BX R0 PUBWEAK WWDT0_IRQHandler @@ -1513,14 +1511,14 @@ FLEXPWM1_SUBMODULE0_DriverIRQHandler FLEXPWM1_SUBMODULE1_DriverIRQHandler FLEXPWM1_SUBMODULE2_DriverIRQHandler FLEXPWM1_SUBMODULE3_DriverIRQHandler -ENC0_COMPARE_DriverIRQHandler -ENC0_HOME_DriverIRQHandler -ENC0_WDG_SAB_DriverIRQHandler -ENC0_IDX_DriverIRQHandler -ENC1_COMPARE_DriverIRQHandler -ENC1_HOME_DriverIRQHandler -ENC1_WDG_SAB_DriverIRQHandler -ENC1_IDX_DriverIRQHandler +QDC0_COMPARE_DriverIRQHandler +QDC0_HOME_DriverIRQHandler +QDC0_WDG_SAB_DriverIRQHandler +QDC0_IDX_DriverIRQHandler +QDC1_COMPARE_DriverIRQHandler +QDC1_HOME_DriverIRQHandler +QDC1_WDG_SAB_DriverIRQHandler +QDC1_IDX_DriverIRQHandler ITRC0_DriverIRQHandler BSP32_DriverIRQHandler ELS_ERR_DriverIRQHandler @@ -1539,8 +1537,8 @@ SPC_DriverIRQHandler WUU_DriverIRQHandler PORT_EFT_DriverIRQHandler ETB0_DriverIRQHandler -SM3_DriverIRQHandler -TRNG0_DriverIRQHandler +Reserved166_DriverIRQHandler +Reserved167_DriverIRQHandler WWDT0_DriverIRQHandler WWDT1_DriverIRQHandler CMC0_DriverIRQHandler diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.c index 7a2295167b..9a52dd2771 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCX N1xNxxx Reference Manual -** Version: rev. 1.0, 2022-10-01 -** Build: b230131 +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 2.0, 2023-02-01 +** Build: b231219 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,8 +19,6 @@ ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2023 NXP -** All rights reserved. -** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,15 +26,17 @@ ** ** Revisions: ** - rev. 1.0 (2022-10-01) -** Initial version based on SPEC1.14 +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN947_cm33_core0 - * @version 1.0 - * @date 2022-10-01 + * @version 2.0 + * @date 2023-02-01 * @brief Device specific configuration file for MCXN947_cm33_core0 * (implementation file) * @@ -48,6 +48,11 @@ #include #include "fsl_device_registers.h" + + + + + /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ @@ -58,51 +63,68 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; -- SystemInit() ---------------------------------------------------------------------------- */ -__attribute__((weak)) void SystemInit(void) -{ - SYSCON->ECC_ENABLE_CTRL = 0x00; - //SYSCON->AHBCLKCTRL0 = 0xFFFFFFFF; - +__attribute__ ((weak)) void SystemInit (void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ #if defined(__MCUXPRESSO) - extern void (*const g_pfnVectors[])(void); - SCB->VTOR = (uint32_t)&g_pfnVectors; + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; #else extern void *__Vectors; - SCB->VTOR = (uint32_t)&__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; #endif + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; - SystemInitHook(); + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + SystemInitHook(); } /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ -void SystemCoreClockUpdate(void) -{ +void SystemCoreClockUpdate (void) { + + + } /* ---------------------------------------------------------------------------- -- SystemInitHook() ---------------------------------------------------------------------------- */ -__attribute__((weak)) void SystemInitHook(void) -{ - /* Void implementation of the weak function. */ +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.h index 981193e128..6d0550f3da 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core0.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCX N1xNxxx Reference Manual -** Version: rev. 1.0, 2022-10-01 -** Build: b230131 +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 2.0, 2023-02-01 +** Build: b231219 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,8 +19,6 @@ ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2023 NXP -** All rights reserved. -** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,15 +26,17 @@ ** ** Revisions: ** - rev. 1.0 (2022-10-01) -** Initial version based on SPEC1.14 +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN947_cm33_core0 - * @version 1.0 - * @date 2022-10-01 + * @version 2.0 + * @date 2023-02-01 * @brief Device specific configuration file for MCXN947_cm33_core0 (header file) * * Provides a system configuration function and a global variable that contains @@ -45,7 +45,7 @@ */ #ifndef _SYSTEM_MCXN947_cm33_core0_H_ -#define _SYSTEM_MCXN947_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MCXN947_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -53,9 +53,12 @@ extern "C" { #include -#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + /** * @brief System clock frequency (core clock) @@ -75,7 +78,7 @@ extern uint32_t SystemCoreClock; * microcontroller device. For systems with variable clock speed it also updates * the variable SystemCoreClock. SystemInit is called from startup_device file. */ -void SystemInit(void); +void SystemInit (void); /** * @brief Updates the SystemCoreClock variable. @@ -84,7 +87,7 @@ void SystemInit(void); * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates * the current core clock. */ -void SystemCoreClockUpdate(void); +void SystemCoreClockUpdate (void); /** * @brief SystemInit function hook. @@ -96,10 +99,10 @@ void SystemCoreClockUpdate(void); * NOTE: No global r/w variables can be used in this hook function because the * initialization of these variables happens after this function. */ -void SystemInitHook(void); +void SystemInitHook (void); #ifdef __cplusplus } #endif -#endif /* _SYSTEM_MCXN947_cm33_core0_H_ */ +#endif /* _SYSTEM_MCXN947_cm33_core0_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.c index b4d6dad48e..ff9f3ae73d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.c +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.c @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCX N1xNxxx Reference Manual -** Version: rev. 1.0, 2022-10-01 -** Build: b230131 +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 2.0, 2023-02-01 +** Build: b231219 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,8 +19,6 @@ ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2023 NXP -** All rights reserved. -** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,15 +26,17 @@ ** ** Revisions: ** - rev. 1.0 (2022-10-01) -** Initial version based on SPEC1.14 +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN947_cm33_core1 - * @version 1.0 - * @date 2022-10-01 + * @version 2.0 + * @date 2023-02-01 * @brief Device specific configuration file for MCXN947_cm33_core1 * (implementation file) * @@ -48,6 +48,11 @@ #include #include "fsl_device_registers.h" + + + + + /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ @@ -58,41 +63,62 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; -- SystemInit() ---------------------------------------------------------------------------- */ -__attribute__((weak)) void SystemInit(void) -{ - SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +__attribute__ ((weak)) void SystemInit (void) { - SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ - SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ #if defined(__MCUXPRESSO) - extern void (*const g_pfnVectors[])(void); - SCB->VTOR = (uint32_t)&g_pfnVectors; + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; #else extern void *__Vectors; - SCB->VTOR = (uint32_t)&__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; #endif + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; - SystemInitHook(); + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + SystemInitHook(); } /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ -void SystemCoreClockUpdate(void) -{ +void SystemCoreClockUpdate (void) { + + + } /* ---------------------------------------------------------------------------- -- SystemInitHook() ---------------------------------------------------------------------------- */ -__attribute__((weak)) void SystemInitHook(void) -{ - /* Void implementation of the weak function. */ +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ } diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.h index 44d8af4d72..08f8fe9a2f 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.h +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/system_MCXN947_cm33_core1.h @@ -8,9 +8,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: MCX N1xNxxx Reference Manual -** Version: rev. 1.0, 2022-10-01 -** Build: b230131 +** Reference manual: MCXNx4x Reference Manual +** Version: rev. 2.0, 2023-02-01 +** Build: b231219 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -19,8 +19,6 @@ ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2023 NXP -** All rights reserved. -** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com @@ -28,15 +26,17 @@ ** ** Revisions: ** - rev. 1.0 (2022-10-01) -** Initial version based on SPEC1.14 +** Initial version +** - rev. 2.0 (2023-02-01) +** Initial version based on Rev. 2 Draft B ** ** ################################################################### */ /*! * @file MCXN947_cm33_core1 - * @version 1.0 - * @date 2022-10-01 + * @version 2.0 + * @date 2023-02-01 * @brief Device specific configuration file for MCXN947_cm33_core1 (header file) * * Provides a system configuration function and a global variable that contains @@ -45,7 +45,7 @@ */ #ifndef _SYSTEM_MCXN947_cm33_core1_H_ -#define _SYSTEM_MCXN947_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ +#define _SYSTEM_MCXN947_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -53,9 +53,12 @@ extern "C" { #include -#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + /** * @brief System clock frequency (core clock) @@ -75,7 +78,7 @@ extern uint32_t SystemCoreClock; * microcontroller device. For systems with variable clock speed it also updates * the variable SystemCoreClock. SystemInit is called from startup_device file. */ -void SystemInit(void); +void SystemInit (void); /** * @brief Updates the SystemCoreClock variable. @@ -84,7 +87,7 @@ void SystemInit(void); * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates * the current core clock. */ -void SystemCoreClockUpdate(void); +void SystemCoreClockUpdate (void); /** * @brief SystemInit function hook. @@ -96,10 +99,10 @@ void SystemCoreClockUpdate(void); * NOTE: No global r/w variables can be used in this hook function because the * initialization of these variables happens after this function. */ -void SystemInitHook(void); +void SystemInitHook (void); #ifdef __cplusplus } #endif -#endif /* _SYSTEM_MCXN947_cm33_core1_H_ */ +#endif /* _SYSTEM_MCXN947_cm33_core1_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript index 1fef0cf290..7be4cc8aca 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript @@ -28,27 +28,34 @@ src += ['MCXN947/drivers/fsl_dac14.c'] src += ['MCXN947/drivers/fsl_edma.c'] src += ['MCXN947/drivers/fsl_edma_soc.c'] src += ['MCXN947/drivers/fsl_eim.c'] -src += ['MCXN947/drivers/fsl_enc.c'] src += ['MCXN947/drivers/fsl_enet.c'] src += ['MCXN947/drivers/fsl_erm.c'] src += ['MCXN947/drivers/fsl_evtg.c'] src += ['MCXN947/drivers/fsl_ewm.c'] src += ['MCXN947/drivers/fsl_flexcan.c'] +src += ['MCXN947/drivers/fsl_flexcan_edma.c'] src += ['MCXN947/drivers/fsl_flexio.c'] src += ['MCXN947/drivers/fsl_flexio_i2c_master.c'] src += ['MCXN947/drivers/fsl_flexio_mculcd.c'] src += ['MCXN947/drivers/fsl_flexio_mculcd_edma.c'] +src += ['MCXN947/drivers/fsl_flexio_mculcd_smartdma.c'] src += ['MCXN947/drivers/fsl_flexio_spi.c'] src += ['MCXN947/drivers/fsl_flexio_spi_edma.c'] src += ['MCXN947/drivers/fsl_flexio_uart.c'] src += ['MCXN947/drivers/fsl_flexio_uart_edma.c'] src += ['MCXN947/drivers/fsl_flexspi.c'] src += ['MCXN947/drivers/fsl_flexspi_edma.c'] +src += ['MCXN947/drivers/fsl_freqme.c'] +src += ['MCXN947/drivers/fsl_gdet.c'] src += ['MCXN947/drivers/fsl_gpio.c'] src += ['MCXN947/drivers/fsl_i3c.c'] +src += ['MCXN947/drivers/fsl_i3c_edma.c'] +src += ['MCXN947/drivers/fsl_inputmux.c'] +src += ['MCXN947/drivers/fsl_intm.c'] src += ['MCXN947/drivers/fsl_irtc.c'] src += ['MCXN947/drivers/fsl_itrc.c'] src += ['MCXN947/drivers/fsl_lpadc.c'] +src += ['MCXN947/drivers/fsl_lpcmp.c'] src += ['MCXN947/drivers/fsl_lpflexcomm.c'] src += ['MCXN947/drivers/fsl_lpi2c.c'] src += ['MCXN947/drivers/fsl_lpi2c_edma.c'] @@ -56,12 +63,55 @@ src += ['MCXN947/drivers/fsl_lpspi.c'] src += ['MCXN947/drivers/fsl_lpspi_edma.c'] src += ['MCXN947/drivers/fsl_lptmr.c'] src += ['MCXN947/drivers/fsl_lpuart.c'] +src += ['MCXN947/drivers/fsl_lpuart_edma.c'] src += ['MCXN947/drivers/fsl_mrt.c'] +src += ['MCXN947/drivers/fsl_opamp.c'] +src += ['MCXN947/drivers/fsl_ostimer.c'] +src += ['MCXN947/drivers/fsl_pdm.c'] +src += ['MCXN947/drivers/fsl_pdm_edma.c'] +src += ['MCXN947/drivers/fsl_pint.c'] +src += ['MCXN947/drivers/fsl_plu.c'] +src += ['MCXN947/drivers/fsl_power.c'] +src += ['MCXN947/drivers/fsl_powerquad_basic.c'] +src += ['MCXN947/drivers/fsl_powerquad_data.c'] +src += ['MCXN947/drivers/fsl_powerquad_filter.c'] +src += ['MCXN947/drivers/fsl_powerquad_math.c'] +src += ['MCXN947/drivers/fsl_powerquad_matrix.c'] +src += ['MCXN947/drivers/fsl_powerquad_transform.c'] +src += ['MCXN947/drivers/fsl_puf_v3.c'] +src += ['MCXN947/drivers/fsl_pwm.c'] +src += ['MCXN947/drivers/fsl_qdc.c'] src += ['MCXN947/drivers/fsl_reset.c'] +src += ['MCXN947/drivers/fsl_sai.c'] +src += ['MCXN947/drivers/fsl_sai_edma.c'] +src += ['MCXN947/drivers/fsl_sctimer.c'] +src += ['MCXN947/drivers/fsl_sema42.c'] +src += ['MCXN947/drivers/fsl_sinc.c'] +src += ['MCXN947/drivers/fsl_smartcard_emvsim.c'] +src += ['MCXN947/drivers/fsl_smartcard_phy_emvsim.c'] +src += ['MCXN947/drivers/fsl_smartdma.c'] +src += ['MCXN947/drivers/fsl_smartdma_mcxn.c'] +src += ['MCXN947/drivers/fsl_smartdma_rt500.c'] src += ['MCXN947/drivers/fsl_spc.c'] -src += ['MCXN947/drivers/fsl_vref.c'] +src += ['MCXN947/drivers/fsl_syspm.c'] +src += ['MCXN947/drivers/fsl_tdet.c'] +src += ['MCXN947/drivers/fsl_trdc.c'] +src += ['MCXN947/drivers/fsl_tsi_v6.c'] src += ['MCXN947/drivers/fsl_usdhc.c'] +src += ['MCXN947/drivers/fsl_utick.c'] +src += ['MCXN947/drivers/fsl_vbat.c'] +src += ['MCXN947/drivers/fsl_vref.c'] +src += ['MCXN947/drivers/fsl_wuu.c'] +src += ['MCXN947/drivers/fsl_wwdt.c'] +src += ['MCXN947/drivers/romapi/flash/src/fsl_flash.c'] +src += ['MCXN947/drivers/romapi/mem_interface/src/fsl_mem_interface.c'] +src += ['MCXN947/drivers/romapi/nboot/src/fsl_nboot.c'] +src += ['MCXN947/drivers/romapi/runbootloader/src/fsl_runbootloader.c'] +path += [cwd + '/MCXN947/drivers/romapi/flash'] +path += [cwd + '/MCXN947/drivers/romapi/mem_interface'] +path += [cwd + '/MCXN947/drivers/romapi/nboot'] +path += [cwd + '/MCXN947/drivers/romapi/runbootloader'] group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)