mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-02-07 18:02:15 +08:00
Jamie
GitHub
File diff suppressed because it is too large
Load Diff
42
bsp/hc32f4a0/.gitignore
vendored
42
bsp/hc32f4a0/.gitignore
vendored
@@ -1,42 +0,0 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
@@ -1,23 +0,0 @@
|
||||
mainmenu "RT-Thread Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "board/Kconfig"
|
||||
|
||||
|
||||
|
||||
@@ -1,214 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file adc/adc_01_base/source/ddl_config.h
|
||||
* @brief This file contains HC32 Series Device Driver Library usage management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Yangjp First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __DDL_CONFIG_H__
|
||||
#define __DDL_CONFIG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Chip module on-off define */
|
||||
#define DDL_ON (1U)
|
||||
#define DDL_OFF (0U)
|
||||
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the Device Driver Library.
|
||||
* Select the modules you need to use to DDL_ON.
|
||||
* @note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
* properly.
|
||||
* @note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
* Library.
|
||||
* @note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
*/
|
||||
#define DDL_ICG_ENABLE (DDL_ON)
|
||||
#define DDL_UTILITY_ENABLE (DDL_ON)
|
||||
#define DDL_PRINT_ENABLE (DDL_ON)
|
||||
|
||||
#define DDL_ADC_ENABLE (DDL_ON)
|
||||
#define DDL_AES_ENABLE (DDL_ON)
|
||||
#define DDL_CAN_ENABLE (DDL_ON)
|
||||
#define DDL_CLK_ENABLE (DDL_ON)
|
||||
#define DDL_CMP_ENABLE (DDL_ON)
|
||||
#define DDL_CRC_ENABLE (DDL_ON)
|
||||
#define DDL_CTC_ENABLE (DDL_ON)
|
||||
#define DDL_DAC_ENABLE (DDL_ON)
|
||||
#define DDL_DCU_ENABLE (DDL_ON)
|
||||
#define DDL_DMA_ENABLE (DDL_ON)
|
||||
#define DDL_DMC_ENABLE (DDL_ON)
|
||||
#define DDL_DVP_ENABLE (DDL_ON)
|
||||
#define DDL_EFM_ENABLE (DDL_ON)
|
||||
#define DDL_EMB_ENABLE (DDL_ON)
|
||||
#define DDL_ETH_ENABLE (DDL_ON)
|
||||
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define DDL_FCM_ENABLE (DDL_ON)
|
||||
#define DDL_FMAC_ENABLE (DDL_ON)
|
||||
#define DDL_GPIO_ENABLE (DDL_ON)
|
||||
#define DDL_HASH_ENABLE (DDL_ON)
|
||||
#define DDL_HRPWM_ENABLE (DDL_ON)
|
||||
#define DDL_I2C_ENABLE (DDL_ON)
|
||||
#define DDL_I2S_ENABLE (DDL_ON)
|
||||
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define DDL_KEYSCAN_ENABLE (DDL_ON)
|
||||
#define DDL_MAU_ENABLE (DDL_ON)
|
||||
#define DDL_MPU_ENABLE (DDL_ON)
|
||||
#define DDL_NFC_ENABLE (DDL_ON)
|
||||
#define DDL_OTS_ENABLE (DDL_ON)
|
||||
#define DDL_PWC_ENABLE (DDL_ON)
|
||||
#define DDL_QSPI_ENABLE (DDL_ON)
|
||||
#define DDL_RMU_ENABLE (DDL_ON)
|
||||
#define DDL_RTC_ENABLE (DDL_ON)
|
||||
#define DDL_SDIOC_ENABLE (DDL_ON)
|
||||
#define DDL_SMC_ENABLE (DDL_ON)
|
||||
#define DDL_SPI_ENABLE (DDL_ON)
|
||||
#define DDL_SRAM_ENABLE (DDL_ON)
|
||||
#define DDL_SWDT_ENABLE (DDL_ON)
|
||||
#define DDL_TMR0_ENABLE (DDL_ON)
|
||||
#define DDL_TMR2_ENABLE (DDL_ON)
|
||||
#define DDL_TMR4_ENABLE (DDL_ON)
|
||||
#define DDL_TMR6_ENABLE (DDL_ON)
|
||||
#define DDL_TMRA_ENABLE (DDL_ON)
|
||||
#define DDL_TRNG_ENABLE (DDL_ON)
|
||||
#define DDL_USART_ENABLE (DDL_ON)
|
||||
#define DDL_USBFS_ENABLE (DDL_OFF)
|
||||
#define DDL_USBHS_ENABLE (DDL_OFF)
|
||||
#define DDL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/* BSP on-off define */
|
||||
#define BSP_ON (1U)
|
||||
#define BSP_OFF (0U)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F4A0_LQFP176 (1U)
|
||||
#define BSP_MS_HC32F4A0_LQFP176_050_MEM (2U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F4A0 is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to BSP_EV_HC32F4A0.
|
||||
*/
|
||||
#define BSP_EV_HC32F4A0 (BSP_EV_HC32F4A0)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
* Select the components you need to use to BSP_ON.
|
||||
*/
|
||||
#define BSP_CY62167EV30LL_ENABLE (BSP_OFF)
|
||||
#define BSP_IS42S16400J7TLI_ENABLE (BSP_OFF)
|
||||
#define BSP_IS62WV51216_ENABLE (BSP_OFF)
|
||||
#define BSP_MT29F2G08AB_ENABLE (BSP_OFF)
|
||||
#define BSP_NT35510_ENABLE (BSP_OFF)
|
||||
#define BSP_OV5640_ENABLE (BSP_OFF)
|
||||
#define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF)
|
||||
#define BSP_TCA9539_ENABLE (BSP_OFF)
|
||||
#define BSP_W25QXX_ENABLE (BSP_OFF)
|
||||
#define BSP_WM8731_ENABLE (BSP_OFF)
|
||||
|
||||
/**
|
||||
* @brief Ethernet and PHY Configuration.
|
||||
* @note PHY delay these values are based on a 1 ms Systick interrupt.
|
||||
*/
|
||||
/* MAC ADDRESS */
|
||||
#define ETH_MAC_ADDR0 (2U)
|
||||
#define ETH_MAC_ADDR1 (0U)
|
||||
#define ETH_MAC_ADDR2 (0U)
|
||||
#define ETH_MAC_ADDR3 (0U)
|
||||
#define ETH_MAC_ADDR4 (0U)
|
||||
#define ETH_MAC_ADDR5 (0U)
|
||||
|
||||
/* Ethernet driver buffers size and count */
|
||||
#define ETH_TXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for receive */
|
||||
#define ETH_RXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for transmit */
|
||||
#define ETH_TXBUF_NUMBER (4UL) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_RXBUF_NUMBER (4UL) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* PHY Address*/
|
||||
#define PHY_ADDRESS (0x00U) /* RTL8201F */
|
||||
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_HW_RESET_DELAY (0x0000003FUL)
|
||||
#define PHY_RESET_DELAY (0x0000007FUL)
|
||||
#define PHY_CONFIG_DELAY (0x0000003FUL)
|
||||
#define PHY_READ_TIMEOUT (0x00000005UL)
|
||||
#define PHY_WRITE_TIMEOUT (0x00000005UL)
|
||||
|
||||
/* Common PHY Registers */
|
||||
#define PHY_BCR (0x00U) /*!< Basic Control Register */
|
||||
#define PHY_BSR (0x01U) /*!< Basic Status Register */
|
||||
|
||||
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
|
||||
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
|
||||
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
|
||||
|
||||
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
|
||||
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
|
||||
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
|
||||
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
|
||||
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
*/
|
||||
#ifndef I2S_EXT_CLK_FREQ
|
||||
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
|
||||
#endif /* I2S_EXT_CLK_FREQ */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DDL_CONFIG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,319 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_common.h
|
||||
* @brief This file contains the common part of the HC32 series.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Yangjp First version
|
||||
2020-09-07 Yangjp Add the precompiled configuration of ARM compiler V6
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_COMMON_H__
|
||||
#define __HC32_COMMON_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32_Common_Part
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HC32 Common Device Include
|
||||
*/
|
||||
#if defined(HC32F120)
|
||||
#include "hc32f120.h"
|
||||
#include "system_hc32f120.h"
|
||||
#elif defined(HC32F4A0)
|
||||
#include "hc32f4a0.h"
|
||||
#include "system_hc32f4a0.h"
|
||||
#elif defined(HC32M120)
|
||||
#include "hc32m120.h"
|
||||
#include "system_hc32m120.h"
|
||||
#elif defined(HC32M423)
|
||||
#include "hc32m423.h"
|
||||
#include "system_hc32m423.h"
|
||||
#else
|
||||
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32_Common_Global_Types HC32 Common Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Single precision floating point number (4 byte)
|
||||
*/
|
||||
typedef float float32_t;
|
||||
|
||||
/**
|
||||
* @brief Double precision floating point number (8 byte)
|
||||
*/
|
||||
typedef double float64_t;
|
||||
|
||||
/**
|
||||
* @brief Function pointer type to void/void function
|
||||
*/
|
||||
typedef void (*func_ptr_t)(void);
|
||||
|
||||
/**
|
||||
* @brief Function pointer type to void/uint8_t function
|
||||
*/
|
||||
typedef void (*func_ptr_arg1_t)(uint8_t);
|
||||
|
||||
/**
|
||||
* @brief Functional state
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Disable = 0U,
|
||||
Enable = 1U,
|
||||
} en_functional_state_t;
|
||||
|
||||
/* Check if it is a functional state */
|
||||
#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable))
|
||||
|
||||
/**
|
||||
* @brief Flag status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Reset = 0U,
|
||||
Set = 1U,
|
||||
} en_flag_status_t, en_int_status_t;
|
||||
|
||||
/**
|
||||
* @brief Generic error codes
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Ok = 0U, /*!< No error */
|
||||
Error = 1U, /*!< Non-specific error code */
|
||||
ErrorAddressAlignment = 2U, /*!< Address alignment does not match */
|
||||
ErrorAccessRights = 3U, /*!< Wrong mode (e.g. user/system) mode is set */
|
||||
ErrorInvalidParameter = 4U, /*!< Provided parameter is not valid */
|
||||
ErrorOperationInProgress = 5U, /*!< A conflicting or requested operation is still in progress */
|
||||
ErrorInvalidMode = 6U, /*!< Operation not allowed in current mode */
|
||||
ErrorUninitialized = 7U, /*!< Module (or part of it) was not initialized properly */
|
||||
ErrorBufferEmpty = 8U, /*!< Circular buffer can not be read because the buffer is empty */
|
||||
ErrorBufferFull = 9U, /*!< Circular buffer can not be written because the buffer is full */
|
||||
ErrorTimeout = 10U, /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
|
||||
ErrorNotReady = 11U, /*!< A requested final state is not reached */
|
||||
OperationInProgress = 12U, /*!< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) */
|
||||
} en_result_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32_Common_Global_Macros HC32 Common Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compiler Macro Definitions
|
||||
*/
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif /* __UNUSED */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned(4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
|
||||
/* Usage: void __RAM_FUNC foo(void) */
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned (4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
|
||||
/* Usage: void __RAM_FUNC foo(void) */
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __weak
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __ramfunc
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __no_init
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT
|
||||
#endif /* __NO_INIT */
|
||||
/* RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. */
|
||||
#define __RAM_FUNC
|
||||
#else
|
||||
#error "unsupported compiler!!"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup Extend_Macro_Definitions Extend Macro Definitions
|
||||
* @{
|
||||
*/
|
||||
/* Decimal to BCD */
|
||||
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
|
||||
|
||||
/* BCD to decimal */
|
||||
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
|
||||
|
||||
/* Returns the dimension of an array */
|
||||
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Address_Align Address Align
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADDRESS_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
|
||||
#define IS_ADDRESS_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
|
||||
#define IS_ADDRESS_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Register_Macro_Definitions Register Macro Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
|
||||
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
|
||||
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
|
||||
|
||||
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
|
||||
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
|
||||
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
|
||||
|
||||
#define CLEAR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
|
||||
#define CLEAR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
|
||||
#define CLEAR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
|
||||
|
||||
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
|
||||
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
|
||||
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
|
||||
|
||||
#define CLEAR_REG8(REG) ((REG) = ((uint8_t)(0U)))
|
||||
#define CLEAR_REG16(REG) ((REG) = ((uint16_t)(0U)))
|
||||
#define CLEAR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
|
||||
|
||||
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
|
||||
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
|
||||
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
|
||||
|
||||
#define READ_REG8(REG) (REG)
|
||||
#define READ_REG16(REG) (REG)
|
||||
#define READ_REG32(REG) (REG)
|
||||
|
||||
#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK)))))
|
||||
#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK)))))
|
||||
#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK)))))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_COMMON_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,346 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ddl.h
|
||||
* @brief This file contains HC32 Series Device Driver Library file call
|
||||
* management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Yangjp First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_DDL_H__
|
||||
#define __HC32_DDL_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Defined use Device Driver Library */
|
||||
#if !defined (USE_DDL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the Device Driver Library.
|
||||
* In this case, the application code will be based on direct access to
|
||||
* peripherals registers.
|
||||
*/
|
||||
/* #define USE_DDL_DRIVER */
|
||||
#endif /* USE_DDL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief HC32 Series Device Driver Library version number
|
||||
*/
|
||||
#define HC32_DDL_VERSION_MAIN 0x01U /*!< [31:24] main version */
|
||||
#define HC32_DDL_VERSION_SUB1 0x00U /*!< [23:16] sub1 version */
|
||||
#define HC32_DDL_VERSION_SUB2 0x04U /*!< [15:8] sub2 version */
|
||||
#define HC32_DDL_VERSION_RC 0x00U /*!< [7:0] release candidate */
|
||||
#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \
|
||||
(HC32_DDL_VERSION_SUB1 << 16) | \
|
||||
(HC32_DDL_VERSION_SUB2 << 8 ) | \
|
||||
(HC32_DDL_VERSION_RC))
|
||||
|
||||
/* Use Device Driver Library */
|
||||
#if defined (USE_DDL_DRIVER)
|
||||
|
||||
/**
|
||||
* @brief Include peripheral module's header file
|
||||
*/
|
||||
#if (DDL_ADC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_adc.h"
|
||||
#endif /* DDL_ADC_ENABLE */
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_aes.h"
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_can.h"
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
#if (DDL_CLK_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_clk.h"
|
||||
#endif /* DDL_CLK_ENABLE */
|
||||
|
||||
#if (DDL_CMP_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_cmp.h"
|
||||
#endif /* DDL_CMP_ENABLE */
|
||||
|
||||
#if (DDL_CRC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_crc.h"
|
||||
#endif /* DDL_CRC_ENABLE */
|
||||
|
||||
#if (DDL_CTC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_ctc.h"
|
||||
#endif /* DDL_CTC_ENABLE */
|
||||
|
||||
#if (DDL_DAC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dac.h"
|
||||
#endif /* DDL_DAC_ENABLE */
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dcu.h"
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
#if (DDL_DMA_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dma.h"
|
||||
#endif /* DDL_DMA_ENABLE */
|
||||
|
||||
#if (DDL_DMC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dmc.h"
|
||||
#endif /* DDL_DMC_ENABLE */
|
||||
|
||||
#if (DDL_DVP_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dvp.h"
|
||||
#endif /* DDL_DVP_ENABLE */
|
||||
|
||||
#if (DDL_EFM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_efm.h"
|
||||
#endif /* DDL_EFM_ENABLE */
|
||||
|
||||
#if (DDL_EMB_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_emb.h"
|
||||
#endif /* DDL_EMB_ENABLE */
|
||||
|
||||
#if (DDL_ETH_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_eth.h"
|
||||
#endif /* DDL_ETH_ENABLE */
|
||||
|
||||
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_event_port.h"
|
||||
#endif /* DDL_EVENT_PORT_ENABLE */
|
||||
|
||||
#if (DDL_FCM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_fcm.h"
|
||||
#endif /* DDL_FCM_ENABLE */
|
||||
|
||||
#if (DDL_FMAC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_fmac.h"
|
||||
#endif /* DDL_FMAC_ENABLE */
|
||||
|
||||
#if (DDL_GPIO_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_gpio.h"
|
||||
#endif /* DDL_GPIO_ENABLE */
|
||||
|
||||
#if (DDL_HASH_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_hash.h"
|
||||
#endif /* DDL_HASH_ENABLE */
|
||||
|
||||
#if (DDL_I2C_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_i2c.h"
|
||||
#endif /* DDL_I2C_ENABLE */
|
||||
|
||||
#if (DDL_I2S_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_i2s.h"
|
||||
#endif /* DDL_I2S_ENABLE */
|
||||
|
||||
#if (DDL_ICG_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_icg.h"
|
||||
#endif /* DDL_ICG_ENABLE */
|
||||
|
||||
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_interrupts.h"
|
||||
#endif /* DDL_INTERRUPTS_ENABLE */
|
||||
|
||||
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_keyscan.h"
|
||||
#endif /* DDL_KEYSCAN_ENABLE */
|
||||
|
||||
#if (DDL_MAU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_mau.h"
|
||||
#endif /* DDL_MAU_ENABLE */
|
||||
|
||||
#if (DDL_MPU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_mpu.h"
|
||||
#endif /* DDL_MPU_ENABLE */
|
||||
|
||||
#if (DDL_NFC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_nfc.h"
|
||||
#endif /* DDL_NFC_ENABLE */
|
||||
|
||||
#if (DDL_OTS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_ots.h"
|
||||
#endif /* DDL_OTS_ENABLE */
|
||||
|
||||
#if (DDL_PWC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_pwc.h"
|
||||
#endif /* DDL_PWC_ENABLE */
|
||||
|
||||
#if (DDL_QSPI_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_qspi.h"
|
||||
#endif /* DDL_QSPI_ENABLE */
|
||||
|
||||
#if (DDL_RMU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_rmu.h"
|
||||
#endif /* DDL_RMU_ENABLE */
|
||||
|
||||
#if (DDL_RTC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_rtc.h"
|
||||
#endif /* DDL_RTC_ENABLE */
|
||||
|
||||
#if (DDL_SDIOC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_sdioc.h"
|
||||
#endif /* DDL_SDIOC_ENABLE */
|
||||
|
||||
#if (DDL_SMC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_smc.h"
|
||||
#endif /* DDL_SMC_ENABLE */
|
||||
|
||||
#if (DDL_SPI_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_spi.h"
|
||||
#endif /* DDL_SPI_ENABLE */
|
||||
|
||||
#if (DDL_SRAM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_sram.h"
|
||||
#endif /* DDL_SRAM_ENABLE */
|
||||
|
||||
#if (DDL_SWDT_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_swdt.h"
|
||||
#endif /* DDL_SWDT_ENABLE */
|
||||
|
||||
#if (DDL_TMR0_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr0.h"
|
||||
#endif /* DDL_TMR0_ENABLE */
|
||||
|
||||
#if (DDL_TMR2_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr2.h"
|
||||
#endif /* DDL_TMR2_ENABLE */
|
||||
|
||||
#if (DDL_TMR4_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr4.h"
|
||||
#endif /* DDL_TMR4_ENABLE */
|
||||
|
||||
#if (DDL_TMR6_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr6.h"
|
||||
#endif /* DDL_TMR6_ENABLE */
|
||||
|
||||
#if (DDL_TMRA_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmra.h"
|
||||
#endif /* DDL_TMRA_ENABLE */
|
||||
|
||||
#if (DDL_TRNG_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_trng.h"
|
||||
#endif /* DDL_TRNG_ENABLE */
|
||||
|
||||
#if (DDL_USART_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_usart.h"
|
||||
#endif /* DDL_USART_ENABLE */
|
||||
|
||||
#if (DDL_USBFS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_usbfs.h"
|
||||
#endif /* DDL_USBFS_ENABLE */
|
||||
|
||||
#if (DDL_USBHS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_usbhs.h"
|
||||
#endif /* DDL_USBHS_ENABLE */
|
||||
|
||||
#if (DDL_UTILITY_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_utility.h"
|
||||
#endif /* DDL_UTILITY_ENABLE */
|
||||
|
||||
#if (DDL_WDT_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_wdt.h"
|
||||
#endif /* DDL_WDT_ENABLE */
|
||||
|
||||
#if (DDL_HRPWM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_hrpwm.h"
|
||||
#endif /* DDL_HRPWM_ENABLE */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Include BSP board's header file
|
||||
*/
|
||||
#if (BSP_EV_HC32F4A0_LQFP176 == BSP_EV_HC32F4A0)
|
||||
#include "ev_hc32f4a0_lqfp176.h"
|
||||
#endif /* BSP_EV_HC32F4A0_LQFP176 */
|
||||
|
||||
#if (BSP_MS_HC32F4A0_LQFP176_050_MEM == BSP_EV_HC32F4A0)
|
||||
#include "ms_hc32f4a0_lqfp176_050_mem.h"
|
||||
#endif /* BSP_MS_HC32F4A0_LQFP176_050_MEM */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Include BSP device component's header file
|
||||
*/
|
||||
#if (BSP_CY62167EV30LL_ENABLE == BSP_ON)
|
||||
#include "cy62167ev30ll.h"
|
||||
#endif /* BSP_CY62167EV30LL_ENABLE */
|
||||
|
||||
#if (BSP_IS42S16400J7TLI_ENABLE == BSP_ON)
|
||||
#include "is42s16400j7tli.h"
|
||||
#endif /* BSP_IS42S16400J7TLI_ENABLE */
|
||||
|
||||
#if (BSP_IS62WV51216_ENABLE == BSP_ON)
|
||||
#include "is62wv51216.h"
|
||||
#endif /* BSP_IS62WV51216_ENABLE */
|
||||
|
||||
#if (BSP_MT29F2G08AB_ENABLE == BSP_ON)
|
||||
#include "mt29f2g08ab.h"
|
||||
#endif /* BSP_MT29F2G08AB_ENABLE */
|
||||
|
||||
#if (BSP_NT35510_ENABLE == BSP_ON)
|
||||
#include "nt35510.h"
|
||||
#endif /* BSP_NT35510_ENABLE */
|
||||
|
||||
#if (BSP_OV5640_ENABLE == BSP_ON)
|
||||
#include "ov5640.h"
|
||||
#endif /* BSP_OV5640_ENABLE */
|
||||
|
||||
#if (BSP_S29GL064N90TFI03_ENABLE == BSP_ON)
|
||||
#include "s29gl064n90tfi03.h"
|
||||
#endif /* BSP_S29GL064N90TFI03_ENABLE */
|
||||
|
||||
#if (BSP_TCA9539_ENABLE == BSP_ON)
|
||||
#include "ev_hc32f4a0_lqfp176_tca9539.h"
|
||||
#include "tca9539.h"
|
||||
#endif /* BSP_TCA9539_ENABLE */
|
||||
|
||||
#if (BSP_W25QXX_ENABLE == BSP_ON)
|
||||
#include "w25qxx.h"
|
||||
#endif /* BSP_W25QXX_ENABLE */
|
||||
|
||||
#if (BSP_WM8731_ENABLE == BSP_ON)
|
||||
#include "wm8731.h"
|
||||
#endif /* BSP_WM8731_ENABLE */
|
||||
|
||||
#endif /* USE_DDL_DRIVER */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_DDL_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,154 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f4a0.h
|
||||
* @brief This file contains all the functions prototypes of the HC32 System.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Zhangxl First version
|
||||
2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __SYSTEM_HC32F4A0_H__
|
||||
#define __SYSTEM_HC32F4A0_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clock setup macro definition
|
||||
*/
|
||||
#define CLOCK_SETTING_NONE 0U /*!< User provides own clock setting in application */
|
||||
#define CLOCK_SETTING_CMSIS 1U
|
||||
|
||||
#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL)))
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#if !defined (HRC_16MHz_VALUE)
|
||||
#define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (HRC_20MHz_VALUE)
|
||||
#define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (MRC_VALUE)
|
||||
#define MRC_VALUE ((uint32_t)8000000UL) /*!< Internal middle speed RC freq.(8MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (LRC_VALUE)
|
||||
#define LRC_VALUE ((uint32_t)32768UL) /*!< Internal low speed RC freq.(32.768KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (RTCLRC_VALUE)
|
||||
#define RTCLRC_VALUE ((uint32_t)32768UL) /*!< Internal RTC low speed RC freq.(32.768KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (SWDTLRC_VALUE)
|
||||
#define SWDTLRC_VALUE ((uint32_t)10000UL) /*!< External low speed OSC freq.(10KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL_VALUE)
|
||||
#define XTAL_VALUE ((uint32_t)8000000UL) /*!< External high speed OSC freq.(8MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL32_VALUE)
|
||||
#define XTAL32_VALUE ((uint32_t)32768UL) /*!< External low speed OSC freq.(32.768KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (HCLK_VALUE)
|
||||
#define HCLK_VALUE (SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Exported_Variable
|
||||
* @{
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
|
||||
extern uint32_t HRC_VALUE; /*!< HRC frequency */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
extern void SystemInit(void); /*!< Initialize the system */
|
||||
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_HC32F4A0_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,168 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f4a0.c
|
||||
* @brief This file provides two functions and one global variable to be called
|
||||
* from user application
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Zhangxl First version
|
||||
2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC
|
||||
2020-09-10 Zhangxl Simplify the declare
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< System clock frequency (Core clock) */
|
||||
__NO_INIT uint32_t SystemCoreClock;
|
||||
/*!< High speed RC frequency (HCR clock) */
|
||||
__NO_INIT uint32_t HRC_VALUE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system. Initialize the System and update
|
||||
* the SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
(*((volatile unsigned short*)(0x400543FEUL)))=0xA50BU;
|
||||
(*((volatile unsigned int*)(0x4004CCE8UL)))=0x00040000UL;
|
||||
(*((volatile unsigned short*)(0x400543FEUL)))=0xA500U;
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
uint32_t plln;
|
||||
uint32_t pllp;
|
||||
uint32_t pllm;
|
||||
|
||||
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
|
||||
/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
|
||||
/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
|
||||
if (1UL == (HRC_FREQ_MON() & 1UL))
|
||||
{
|
||||
HRC_VALUE = HRC_16MHz_VALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
HRC_VALUE = HRC_20MHz_VALUE;
|
||||
}
|
||||
|
||||
tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
|
||||
switch(tmp)
|
||||
{
|
||||
case 0x00U: /* use internal high speed RC */
|
||||
SystemCoreClock = HRC_VALUE;
|
||||
break;
|
||||
case 0x01U: /* use internal middle speed RC */
|
||||
SystemCoreClock = MRC_VALUE;
|
||||
break;
|
||||
case 0x02U: /* use internal low speed RC */
|
||||
SystemCoreClock = LRC_VALUE;
|
||||
break;
|
||||
case 0x03U: /* use external high speed OSC */
|
||||
SystemCoreClock = XTAL_VALUE;
|
||||
break;
|
||||
case 0x04U: /* use external low speed OSC */
|
||||
SystemCoreClock = XTAL32_VALUE;
|
||||
break;
|
||||
case 0x05U: /* use PLLH */
|
||||
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
|
||||
pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
|
||||
plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
|
||||
pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);
|
||||
|
||||
/* use external high speed OSC as PLL source */
|
||||
if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC)
|
||||
{
|
||||
SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
}
|
||||
/* use internal high RC as PLL source */
|
||||
else
|
||||
{
|
||||
SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,283 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,39 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.3
|
||||
* @date 24. June 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,272 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,346 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,132 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_aes.h
|
||||
* @brief This file contains all the functions prototypes of the AES driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Heqb First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_AES_H__
|
||||
#define __HC32F4A0_AES_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_AES
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup AES_Global_Macros AES Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES key length in bytes is 16. */
|
||||
#define AES_BLOCK_LEN (16U)
|
||||
|
||||
/**
|
||||
* @defgroup AES_STATUS AES Start or Stop
|
||||
* @{
|
||||
*/
|
||||
#define AES_START (AES_CR_START)
|
||||
#define AES_STOP (0x0UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AES_KEY_SIZE AES Key Size
|
||||
* @{
|
||||
*/
|
||||
#define AES_KEY_SIZE_128BIT (0UL << AES_CR_KEYSIZE_POS)
|
||||
#define AES_KEY_SIZE_192BIT (1UL << AES_CR_KEYSIZE_POS)
|
||||
#define AES_KEY_SIZE_256BIT (2UL << AES_CR_KEYSIZE_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup AES_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
en_result_t AES_Encrypt(uint8_t au8Plaintext[],
|
||||
uint32_t u32PlaintextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t u8KeyLength,
|
||||
uint8_t au8Ciphertext[]);
|
||||
|
||||
en_result_t AES_Decrypt(uint8_t au8Ciphertext[],
|
||||
uint32_t u32CiphertextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t u8KeyLength,
|
||||
uint8_t au8Plaintext[]);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_AES_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,374 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_cmp.h
|
||||
* @brief Head file for CMP module.
|
||||
*
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Heqb First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_CMP_H__
|
||||
#define __HC32F4A0_CMP_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_CMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_CMP_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CMP_Global_Types CMP Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CMP configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t u8CmpCh; /*!< Select the compare voltage channel for normal mode
|
||||
@ref CMP_CVSL_Channal */
|
||||
uint16_t u16CmpVol; /*!< Select the compare voltage source for normal mode
|
||||
(Config the parameter when use CMP1 or CMP3)@ref CMP1_3_CVSL_Source */
|
||||
uint8_t u8RefVol; /*!< Reference voltage for normal mode, @ref CMP_RVSL_Source*/
|
||||
|
||||
uint8_t u8OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
|
||||
|
||||
uint8_t u8OutDetectEdges; /*!< Output detecte edge, @ref CMP_Out_Detect_Edge */
|
||||
|
||||
uint8_t u8OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
|
||||
}stc_cmp_init_t;
|
||||
|
||||
/**
|
||||
* @brief CMP reference voltage for window mode configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t u8CmpCh1; /*!< Select the compare voltage channel for window mode
|
||||
@ref CMP_CVSL_Channal */
|
||||
uint16_t u16CmpVol; /*!< Select the compare voltage source for window mode
|
||||
(Config the parameter when use CMP1 or CMP3)@ref CMP1_3_CVSL_Source */
|
||||
uint8_t u8CmpCh2; /*!< Select the compare voltage channel for window mode
|
||||
@ref CMP_CVSL_Channal */
|
||||
uint8_t u8WinVolLow; /*!< CMP reference low voltage for window mode
|
||||
@ref CMP_RVSL_Source */
|
||||
uint8_t u8WinVolHigh; /*!< CMP reference high voltage for window mode
|
||||
@ref CMP_RVSL_Source */
|
||||
}stc_cmp_win_ref_t;
|
||||
|
||||
/**
|
||||
* @brief CMP timer windows function configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t u16TWSelect; /*!< Timer window source select
|
||||
@ref CMP_TimerWin_Select */
|
||||
uint8_t u8TWOutLevel; /*!< Timer window mode output level
|
||||
@ref CMP_TimerWin_output_Level*/
|
||||
uint8_t u8TWInvalidLevel; /*!< Output level when timer window invalid
|
||||
@ref CMP_TimerWin_Invalid_Level */
|
||||
}stc_cmp_timerwindow_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @defgroup CMP_Global_Macros CMP Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_Mode CMP compare mode
|
||||
* @{
|
||||
*/
|
||||
#define CMP_MODE_NORMAL (0x00U) /*!< Normal mode */
|
||||
#define CMP_MODE_WINDOW (CMP_MDR_CWDE) /*!< Window mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_CVSL_Channal CMP compare voltage channel selection
|
||||
* @{
|
||||
*/
|
||||
#define CMP_CVSL_NONE (0x0U) /*!< No input compare voltage */
|
||||
#define CMP_CVSL_INP1 (CMP_PMSR_CVSL_0) /*!< Select INP1 as compare voltage */
|
||||
#define CMP_CVSL_INP2 (CMP_PMSR_CVSL_1) /*!< Select INP2 as compare voltage */
|
||||
#define CMP_CVSL_INP3 (CMP_PMSR_CVSL_2) /*!< Select INP3 as compare voltage */
|
||||
#define CMP_CVSL_INP4 (CMP_PMSR_CVSL_3) /*!< Select INP4 as compare voltage */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_RVSL_Source CMP reference voltage selection
|
||||
* @{
|
||||
*/
|
||||
#define CMP_RVSL_NONE (0x0U) /*!< No input reference voltage */
|
||||
#define CMP_RVSL_INM1 (CMP_PMSR_RVSL_0) /*!< Select INM1 as reference voltage */
|
||||
#define CMP_RVSL_INM2 (CMP_PMSR_RVSL_1) /*!< Select INM2 as reference voltage */
|
||||
#define CMP_RVSL_INM3 (CMP_PMSR_RVSL_2) /*!< Select INM3 as reference voltage */
|
||||
#define CMP_RVSL_INM4 (CMP_PMSR_RVSL_3) /*!< Select INM4 as reference voltage */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP1_3_CVSL_Source CMP1 CMP3 compare voltage selection
|
||||
* @{
|
||||
*/
|
||||
#define CMP1_INP3_NONE (0x0U) /*!< No input voltage to CMP1 INP3 */
|
||||
#define CMP1_INP3_CMP1_INP3 (CMP_VISR_P3SL_0) /*!< Select CMP1_INP3 as CMP1 INP3 input */
|
||||
#define CMP1_INP3_CMP2_INP3 (CMP_VISR_P3SL_1) /*!< Select CMP2_INP3 as CMP1 INP3 input */
|
||||
#define CMP1_INP2_NONE (0x0U) /*!< No input voltage to CMP1 INP2 */
|
||||
#define CMP1_INP2_PGA1 (CMP_VISR_P2SL_0) /*!< Select PGA1 as CMP1 INP2 input */
|
||||
#define CMP1_INP2_PGA2 (CMP_VISR_P2SL_1) /*!< Select PGA2 as CMP1 INP2 input */
|
||||
#define CMP1_INP2_CMP1_INP2 (CMP_VISR_P2SL_2) /*!< Select CMP1_INP2 as CMP1 INP2 input */
|
||||
#define CMP3_INP3_NONE (0x0U) /*!< No input voltage to CMP3 INP3 */
|
||||
#define CMP3_INP3_CMP3_INP3 (CMP_VISR_P3SL_0) /*!< Select CMP3_INP3 as CMP3 INP3 input */
|
||||
#define CMP3_INP3_CMP4_INP3 (CMP_VISR_P3SL_1) /*!< Select CMP4_INP3 as CMP3 INP3 input */
|
||||
#define CMP3_INP2_NONE (0x0U) /*!< No input voltage to CMP3 INP2 */
|
||||
#define CMP3_INP2_PGA3 (CMP_VISR_P2SL_0) /*!< Select PGA3 as CMP3 INP2 input */
|
||||
#define CMP3_INP2_PGA4 (CMP_VISR_P2SL_1) /*!< Select PGA4 as CMP3 INP2 input */
|
||||
#define CMP3_INP2_CMP3_INP2 (CMP_VISR_P2SL_2) /*!< Select CMP3_INP2 as CMp3 INP2 input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_Out_Polarity_Select CMP output polarity selection
|
||||
* @{
|
||||
*/
|
||||
#define CMP_OUT_REVERSE_OFF (0x0U) /*!< CMP output don't reverse */
|
||||
#define CMP_OUT_REVERSE_ON (CMP_OCR_COPS) /*!< CMP output level reverse */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_Out_Detect_Edge CMP output detect edge selection
|
||||
* @{
|
||||
*/
|
||||
#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */
|
||||
#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */
|
||||
#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */
|
||||
#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_Out_Filter CMP output filter configuration
|
||||
* @{
|
||||
*/
|
||||
#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */
|
||||
#define CMP_OUT_FILTER_PCLK3 (1U) /*!< Use pclk3 */
|
||||
#define CMP_OUT_FILTER_PCLK3_DIV8 (2U) /*!< Use pclk3/8 */
|
||||
#define CMP_OUT_FILTER_PCLK3_DIV32 (3U) /*!< Use pclk3/32 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_TimerWin_func CMP timer window function configuration
|
||||
* @{
|
||||
*/
|
||||
#define CMP_TIMERWIN_OFF (0x0U) /*!< Disable Timer Window function */
|
||||
#define CMP_TIMERWIN_ON (CMP_OCR_TWOE) /*!< Enable Timer Window function */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_TimerWin_Select CMP output timer window function control signal definition for CMP
|
||||
* @{
|
||||
*/
|
||||
#define CMP_1_TIMERWIN_TIMA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_1_PWM1 as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIMA_3_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_3_PWM1 as timer window signal for CMP2*/
|
||||
#define CMP_3_TIMERWIN_TIMA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_1_PWM1 as timer window signal for CMP3*/
|
||||
#define CMP_4_TIMERWIN_TIMA_2_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_2_PWM1 as timer window signal for CMP4*/
|
||||
|
||||
#define CMP_1_TIMERWIN_TIMA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_1_PWM2 as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIMA_3_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_3_PWM2 as timer window signal for CMP2*/
|
||||
#define CMP_3_TIMERWIN_TIMA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_1_PWM2 as timer window signal for CMP3*/
|
||||
#define CMP_4_TIMERWIN_TIMA_2_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_2_PWM2 as timer window signal for CMP4*/
|
||||
|
||||
#define CMP_1_TIMERWIN_TIMA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_1_PWM3 as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIMA_3_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_3_PWM3 as timer window signal for CMP2*/
|
||||
#define CMP_3_TIMERWIN_TIMA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_1_PWM3 as timer window signal for CMP3*/
|
||||
#define CMP_4_TIMERWIN_TIMA_2_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_2_PWM3 as timer window signal for CMP3*/
|
||||
|
||||
#define CMP_1_TIMERWIN_TIMA_2_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_2_PWM1 as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIMA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_4_PWM1 as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIMA_3_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_3_PWM1 as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIMA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_4_PWM1 as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIMA_2_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_2_PWM2 as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIMA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_4_PWM2 as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIMA_3_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_3_PWM2 as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIMA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_4_PWM2 as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIMA_2_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_2_PWM3 as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIMA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_4_PWM3 as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIMA_3_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_3_PWM3 as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIMA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_4_PWM3 as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM6_1_PWMA (CMP_TWSR_CTWS6) /*!< Selection TIM6_1_PWMA as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM6_5_PWMA (CMP_TWSR_CTWS6) /*!< Selection TIM6_5_PWMA as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM6_1_PWMB (CMP_TWSR_CTWS6) /*!< Selection TIM6_1_PWMB as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM6_5_PWMB (CMP_TWSR_CTWS6) /*!< Selection TIM6_5_PWMB as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM6_2_PWMA (CMP_TWSR_CTWS7) /*!< Selection TIM6_2_PWMA as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM6_6_PWMA (CMP_TWSR_CTWS7) /*!< Selection TIM6_6_PWMA as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM6_2_PWMB (CMP_TWSR_CTWS7) /*!< Selection TIM6_2_PWMB as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM6_6_PWMB (CMP_TWSR_CTWS7) /*!< Selection TIM6_6_PWMB as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM6_3_PWMA (CMP_TWSR_CTWS8) /*!< Selection TIM6_3_PWMA as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM6_7_PWMA (CMP_TWSR_CTWS8) /*!< Selection TIM6_7_PWMA as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM6_3_PWMB (CMP_TWSR_CTWS8) /*!< Selection TIM6_3_PWMB as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM6_7_PWMB (CMP_TWSR_CTWS8) /*!< Selection TIM6_7_PWMB as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM6_4_PWMA (CMP_TWSR_CTWS9) /*!< Selection TIM6_4_PWMA as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM6_8_PWMA (CMP_TWSR_CTWS9) /*!< Selection TIM6_8_PWMA as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM6_4_PWMB (CMP_TWSR_CTWS9) /*!< Selection TIM6_4_PWMB as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM6_8_PWMB (CMP_TWSR_CTWS9) /*!< Selection TIM6_8_PWMB as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM4_1_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_1_OUH as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM4_2_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_2_OUH as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM4_3_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_3_OUH as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM4_3_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_4_OUH as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM4_1_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_1_OUL as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM4_2_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_2_OUL as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM4_3_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_3_OUL as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM4_3_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_4_OUL as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM4_1_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_1_OVH as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM4_2_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_2_OVH as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM4_3_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_3_OVH as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM4_3_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_4_OVH as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM4_1_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_1_OVL as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM4_2_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_2_OVL as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM4_3_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_3_OVL as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM4_3_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_4_OVL as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM4_1_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_1_OWH as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM4_2_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_2_OWH as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM4_3_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_3_OWH as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM4_3_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_4_OWH as timer window signal for CMP4 */
|
||||
|
||||
#define CMP_1_TIMERWIN_TIM4_1_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_1_OWL as timer window signal for CMP1 */
|
||||
#define CMP_2_TIMERWIN_TIM4_2_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_2_OWL as timer window signal for CMP2 */
|
||||
#define CMP_3_TIMERWIN_TIM4_3_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_3_OWL as timer window signal for CMP3 */
|
||||
#define CMP_4_TIMERWIN_TIM4_3_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_4_OWL as timer window signal for CMP4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_TimerWin_Invalid_Level CMP output level when timer window invalid
|
||||
* @{
|
||||
*/
|
||||
#define CMP_TIMERWIN_INVALID_LEVEL_LOW (0x0U) /*!< Output Low when timer window invalid */
|
||||
#define CMP_TIMERWIN_INVALID_LEVEL_HIGH (CMP_OCR_TWOL) /*!< Output High when timer window invalid */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMP_TimerWin_output_Level CMP output level in timer windows mode
|
||||
* @{
|
||||
*/
|
||||
#define CMP_TIMERWIN_OUT_LEVEL_LOW (0U) /*!< Output Low in timer windows mode */
|
||||
#define CMP_TIMERWIN_OUT_LEVEL_HIGH (1U) /*!< Output High in timer windows mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CMP_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
en_result_t CMP_StructInit(stc_cmp_init_t *pstcCMP_InitStruct);
|
||||
en_result_t CMP_NormalModeInit(M4_CMP_TypeDef *CMPx,
|
||||
const stc_cmp_init_t *pstcCmpInit);
|
||||
en_result_t CMP_WindowModeInit(const M4_CMP_TypeDef *CMPx,
|
||||
const stc_cmp_init_t *pstcCmpInit,
|
||||
const stc_cmp_win_ref_t *pstcCmpWinRef);
|
||||
en_result_t CMP_TimerWindowConfig(M4_CMP_TypeDef *CMPx,
|
||||
const stc_cmp_timerwindow_t *pstcCMP_TimerWinStruct);
|
||||
|
||||
void CMP_FuncCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
|
||||
void CMP_IntCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
|
||||
void CMP_OutputCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
|
||||
void CMP_VCOUTCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
|
||||
void CMP_SetOutDetectEdges(M4_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
|
||||
void CMP_SetOutputFilter(M4_CMP_TypeDef *CMPx, uint8_t u8CmpFilter);
|
||||
void CMP_SetOutputPolarity(M4_CMP_TypeDef *CMPx, uint8_t u8CmpPolarity);
|
||||
void CMP_SetCompareVol(M4_CMP_TypeDef *CMPx, uint8_t u8CmpCh, uint8_t u8CmpVol);
|
||||
void CMP_SetRefVol(M4_CMP_TypeDef *CMPx, uint8_t u8RefVol);
|
||||
void CMP_DeInit(M4_CMP_TypeDef *CMPx);
|
||||
void CMP_SetTimerWinSignal(M4_CMP_TypeDef *CMPx, \
|
||||
uint16_t u16TWSignal, en_functional_state_t enNewStatus);
|
||||
en_flag_status_t CMP_GetResult(const M4_CMP_TypeDef *CMPx);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_CMP_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_CMP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,143 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_crc.h
|
||||
* @brief This file contains all the functions prototypes of the CRC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Heqb First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_CRC_H__
|
||||
#define __HC32F4A0_CRC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_CRC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Bits definitions of CRC control register(CRC_CR). */
|
||||
/**
|
||||
* @defgroup CRC_Global_Macros CRC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit
|
||||
* @note: - CRC16 polynomial is X16 + X12 + X5 + 1
|
||||
* - CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \
|
||||
* X8 + X7 + X5 + X4 + X2 + X + 1
|
||||
* @{
|
||||
*/
|
||||
#define CRC_CRC16 (0x0UL)
|
||||
#define CRC_CRC32 (CRC_CR_CR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Flag_Bit_Mask CRC Flag Bit Mask
|
||||
* @{
|
||||
*/
|
||||
#define CRC_FLAG_MASK (CRC_CR_FLAG)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CRC_Bit_Width CRC Bit Width
|
||||
* @{
|
||||
*/
|
||||
#define CRC_BW_8 (8U)
|
||||
#define CRC_BW_16 (16U)
|
||||
#define CRC_BW_32 (32U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CRC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t CRC_Calculate(uint32_t u32CrcProtocol,
|
||||
const void *pvData,
|
||||
uint32_t u32InitVal,
|
||||
uint32_t u32Length,
|
||||
uint8_t u8BitWidth);
|
||||
|
||||
en_flag_status_t CRC_Check(uint32_t u32CrcProtocol,
|
||||
uint32_t u32CheckSum,
|
||||
const void *pvData,
|
||||
uint32_t u32InitVal,
|
||||
uint32_t u32Length,
|
||||
uint8_t u8BitWidth);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_CRC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_CRC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,210 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_ctc.h
|
||||
* @brief This file contains all the functions prototypes of the Clock Trimming
|
||||
* Controller(CTC) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-09-01 Hongjh First version
|
||||
2020-10-30 Hongjh Refine CTC initialization structure
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_CTC_H__
|
||||
#define __HC32F4A0_CTC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_CTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_CTC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CTC_Global_Types CTC Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CTC initialization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32RefClockFreq; /*!< Reference clock frequency
|
||||
This parameter should refer user manual recommended values */
|
||||
uint32_t u32RefClockSrc; /*!< Reference clock source selection
|
||||
This parameter can be a value of @ref CTC_Reference_Clock_Source */
|
||||
uint32_t u32RefClockDiv; /*!< Reference clock division
|
||||
This parameter can be a value of @ref CTC_Reference_Clock_Division */
|
||||
float32_t f32ToleranceDeviation; /*!< CTC Tolerance bias.
|
||||
This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */
|
||||
uint32_t u32TrimValue; /*!< CTC TRMVAL value
|
||||
This parameter can be a value between Min_Data=0 and Max_Data=0x3F */
|
||||
} stc_ctc_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup CTC_Global_Macros CTC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CTC_Reference_Clock_Source CTC Reference Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define CTC_REF_CLK_CTCREF (0UL) /*!< Clock source: CTCREF */
|
||||
#define CTC_REF_CLK_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */
|
||||
#define CTC_REF_CLK_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CTC_Tolerance_Deviation_Max CTC Tolerance Deviation Max
|
||||
* @{
|
||||
*/
|
||||
#define CTC_TOLERANCE_DEVIATION_MAX (1.0F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CTC_Flag CTC Flag
|
||||
* @{
|
||||
*/
|
||||
#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */
|
||||
#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */
|
||||
#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */
|
||||
#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */
|
||||
#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OK | \
|
||||
CTC_FLAG_TRIM_OVF | \
|
||||
CTC_FLAG_TRIM_UDF | \
|
||||
CTC_FLAG_BUSY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define CTC_REF_CLK_DIV8 (0UL) /*!< REFCLK/8 */
|
||||
#define CTC_REF_CLK_DIV32 (1UL) /*!< REFCLK/32 */
|
||||
#define CTC_REF_CLK_DIV128 (2UL) /*!< REFCLK/128 */
|
||||
#define CTC_REF_CLK_DIV256 (3UL) /*!< REFCLK/256 */
|
||||
#define CTC_REF_CLK_DIV512 (4UL) /*!< REFCLK/512 */
|
||||
#define CTC_REF_CLK_DIV1024 (5UL) /*!< REFCLK/1024 */
|
||||
#define CTC_REF_CLK_DIV2048 (6UL) /*!< REFCLK/2048 */
|
||||
#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup CTC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start CTC trimming.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void CTC_Start(void)
|
||||
{
|
||||
WRITE_REG32(bM4_CTC->CR1_b.CTCEN, 1UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop CTC trimming.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void CTC_Stop(void)
|
||||
{
|
||||
WRITE_REG32(bM4_CTC->CR1_b.CTCEN, 0UL);
|
||||
}
|
||||
|
||||
en_result_t CTC_Init(const stc_ctc_init_t *pstcCtcInit);
|
||||
en_result_t CTC_StructInit(stc_ctc_init_t *pstcCtcInit);
|
||||
en_result_t CTC_DeInit(void);
|
||||
void CTC_SetRefClockDiv(uint32_t u32Div);
|
||||
void CTC_SetRefClockSrc(uint32_t u32ClockSrc);
|
||||
void CTC_IntCmd(en_functional_state_t enNewState);
|
||||
en_flag_status_t CTC_GetStatus(uint32_t u32Flag);
|
||||
void CTC_SetTrimValue(uint32_t u32TrimValue);
|
||||
uint32_t CTC_GetTrimValue(void);
|
||||
void CTC_SetReloadValue(uint32_t u32ReloadValue);
|
||||
uint16_t CTC_GetReloadValue(void);
|
||||
void CTC_SetOffsetValue(uint32_t u32OffsetValue);
|
||||
uint32_t CTC_GetOffsetValue(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_CTC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_CTC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,189 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_dac.h
|
||||
* @brief This file contains all the functions prototypes of the DAC driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Hexiao First version
|
||||
2020-07-15 Hexiao 1. Modify DAC_ChannelCmd to DAC_Start and DAC_Stop
|
||||
2. Modify DAC_DualChannelCmd to DAC_DualChannelStart
|
||||
and DAC_DualChannelStop
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_DAC_H__
|
||||
#define __HC32F4A0_DAC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
#include "hc32f4a0_utility.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_DAC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DAC_Global_Types DAC Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Structure definition of DAC initialization.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t u16Src; /*!< Data source to be converted
|
||||
This parameter can be a value of @ref DAC_DATA_SRC */
|
||||
|
||||
en_functional_state_t enOutput; /*!< Enable or disable analog output
|
||||
This parameter can be a value of @ref en_functional_state_t */
|
||||
|
||||
} stc_dac_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @defgroup DAC_Global_Macros DAC Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DAC_CH DAC channel
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CH_1 (0U)
|
||||
#define DAC_CH_2 (1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DAC_DATA_SRC DAC data source
|
||||
* @{
|
||||
*/
|
||||
#define DAC_DATA_SRC_DATAREG (0U)
|
||||
#define DAC_DATA_SRC_DCU (1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern
|
||||
* @{
|
||||
*/
|
||||
#define DAC_DATA_ALIGN_L (DAC_DACR_DPSEL)
|
||||
#define DAC_DATA_ALIGN_R (0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DAC_DATAREG_VALUE_MAX (4096UL)
|
||||
|
||||
/**
|
||||
* @defgroup DAC_ADP_SELECT DAC ADCx priority select
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ADP_SELECT_ADC1 (DAC_DAADPCR_ADPSL1)
|
||||
#define DAC_ADP_SELECT_ADC2 (DAC_DAADPCR_ADPSL2)
|
||||
#define DAC_ADP_SELECT_ADC3 (DAC_DAADPCR_ADPSL3)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup DAC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
en_result_t DAC_StructInit(stc_dac_init_t * pstcInit);
|
||||
en_result_t DAC_Init(M4_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcInit);
|
||||
void DAC_DeInit(M4_DAC_TypeDef *DACx);
|
||||
|
||||
void DAC_SetDataSource(M4_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src);
|
||||
void DAC_DataRegAlignConfig(M4_DAC_TypeDef *DACx, uint16_t u16Align);
|
||||
void DAC_OutputCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
|
||||
en_result_t DAC_AMPCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
|
||||
void DAC_ADCPrioCmd(M4_DAC_TypeDef *DACx, en_functional_state_t enNewState);
|
||||
void DAC_ADCPrioConfig(M4_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState);
|
||||
|
||||
en_result_t DAC_Start(M4_DAC_TypeDef *DACx, uint16_t u16Ch);
|
||||
en_result_t DAC_Stop(M4_DAC_TypeDef *DACx, uint16_t u16Ch);
|
||||
void DAC_DualChannelStart(M4_DAC_TypeDef *DACx);
|
||||
void DAC_DualChannelStop(M4_DAC_TypeDef *DACx);
|
||||
|
||||
void DAC_SetChannel1Data(M4_DAC_TypeDef *DACx, uint16_t data);
|
||||
void DAC_SetChannel2Data(M4_DAC_TypeDef *DACx, uint16_t data);
|
||||
void DAC_SetDualChannelData(M4_DAC_TypeDef *DACx, uint16_t data2, uint16_t data1);
|
||||
en_result_t DAC_GetChannel1ConvState(const M4_DAC_TypeDef *DACx);
|
||||
en_result_t DAC_GetChannel2ConvState(const M4_DAC_TypeDef *DACx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_DAC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_DAC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,347 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_dcu.h
|
||||
* @brief This file contains all the functions prototypes of the DCU(Data
|
||||
* Computing Unit) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Hongjh First version
|
||||
2020-07-23 Hongjh 1. Correct the macro define: DCU_CMP_TRIG_DATA01;
|
||||
2. Refine the macro define for interrupt, flag and mode;
|
||||
3. Modify API: from DCU_IntFuncCmd to DCU_GlobalIntCmd;
|
||||
4. Delete API: DCU_SetCmpIntMode;
|
||||
5. Modify DCU DATA read/write API.
|
||||
2020-09-07 Hongjh Refine API: DCU_SetTriggerSrc
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_DCU_H__
|
||||
#define __HC32F4A0_DCU_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_DCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DCU_Global_Types DCU Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCU initialization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32IntEn; /*!< Select DCU interrupt function.
|
||||
This parameter can be a value of @ref DCU_Interrupt_Configure */
|
||||
|
||||
uint32_t u32DataSize; /*!< Specifies DCU data size.
|
||||
This parameter can be a value of @ref DCU_Data_Size */
|
||||
|
||||
uint32_t u32Mode; /*!< Specifies DCU operation.
|
||||
This parameter can be a value of @ref DCU_Mode */
|
||||
|
||||
uint32_t u32CmpTriggerMode; /*!< Specifies DCU compare operation trigger mode size.
|
||||
This parameter can be a value of @ref DCU_Compare_Trigger_Mode */
|
||||
} stc_dcu_init_t;
|
||||
|
||||
/**
|
||||
* @brief DCU wave output configure structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32LowerLimit; /*!< Defines the wave lower limit of the wave amplitude.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
|
||||
|
||||
uint32_t u32UpperLimit; /*!< Defines the upper limit of the wave amplitude.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
|
||||
|
||||
uint32_t u32Step; /*!< Defines the increasing/decreasing step.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
|
||||
} stc_dcu_wave_cfg_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DCU_Global_Macros DCU Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Data_Size DCU Data Size
|
||||
* @{
|
||||
*/
|
||||
#define DCU_DATA_SIZE_8BIT (0UL) /*!< DCU data size: 8 bit */
|
||||
#define DCU_DATA_SIZE_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data size: 16 bit */
|
||||
#define DCU_DATA_SIZE_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data size: 32 bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Compare_Trigger_Mode DCU Compare Trigger Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */
|
||||
#define DCU_CMP_TRIG_DATA012 (DCU_CTL_COMP_TRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Mode DCU Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INVALID (0UL) /*!< DCU invalid */
|
||||
#define DCU_ADD (DCU_CTL_MODE_0) /*!< DCU add operation */
|
||||
#define DCU_SUB (DCU_CTL_MODE_1) /*!< DCU sub operation */
|
||||
#define DCU_HW_ADD (DCU_CTL_MODE_1 | \
|
||||
DCU_CTL_MODE_0) /*!< Hardware trigger DCU add */
|
||||
#define DCU_HW_SUB (DCU_CTL_MODE_2) /*!< Hardware trigger DCU sub */
|
||||
#define DCU_CMP (DCU_CTL_MODE_2 | \
|
||||
DCU_CTL_MODE_0) /*!< DCU compare */
|
||||
#define DCU_TRIANGLE_WAVE (DCU_CTL_MODE_3) /*!< DCU triangle wave output mode */
|
||||
#define DCU_SAWTOOTH_WAVE_INC (DCU_CTL_MODE_3 | \
|
||||
DCU_CTL_MODE_0) /*!< DCU increasing sawtooth wave output mode */
|
||||
#define DCU_SAWTOOTH_WAVE_DEC (DCU_CTL_MODE_3 | \
|
||||
DCU_CTL_MODE_1) /*!< DCU decreasing sawtooth wave output mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Interrupt_Configure DCU Interrupt Configure
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_DISABLE (0UL) /*!< Disable DCU interrupt */
|
||||
#define DCU_INT_ENABLE (DCU_CTL_INTEN) /*!< Enable DCU interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Flag DCU Flag
|
||||
* @{
|
||||
*/
|
||||
#define DCU_FLAG_OPERATION (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */
|
||||
#define DCU_FLAG_DATA0_LS_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */
|
||||
#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */
|
||||
#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */
|
||||
#define DCU_FLAG_DATA0_LS_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */
|
||||
#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */
|
||||
#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */
|
||||
#define DCU_FLAG_WAVE_SAWTOOTH_RELOAD (DCU_FLAG_FLAG_RLD) /*!< DCU sawtooth wave mode reload interrupt */
|
||||
#define DCU_FLAG_WAVE_TRIANGLE_BOTTOM (DCU_FLAG_FLAG_BTM) /*!< DCU triangle wave mode bottom interrupt */
|
||||
#define DCU_FLAG_WAVE_TRIANGLE_TOP (DCU_FLAG_FLAG_TOP) /*!< DCU triangle wave mode top interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Interrupt_Category DCU Interrupt Category
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_OP (0UL) /*!< DCU operation result(overflow/underflow) interrupt */
|
||||
#define DCU_INT_WAVE_MD (1UL) /*!< DCU wave mode(sawtooth/triangle wave mode) interrupt */
|
||||
#define DCU_INT_CMP_WIN (2UL) /*!< DCU comparison(window) interrupt */
|
||||
#define DCU_INT_CMP_NON_WIN (3UL) /*!< DCU comparison(non-window) interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Interrupt_Type DCU Interrupt Type
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt
|
||||
* @{
|
||||
* @note Compare interrupt selection is valid only when select DCU comparison(non-window) interrupt(DCU_INTSEL.INT_WIN=0) under DCU compare mode
|
||||
*/
|
||||
#define DCU_INT_CMP_DATA0_LS_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_LS_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */
|
||||
#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */
|
||||
#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LS_DATA2 | \
|
||||
DCU_INT_CMP_DATA0_EQ_DATA2 | \
|
||||
DCU_INT_CMP_DATA0_GT_DATA2 | \
|
||||
DCU_INT_CMP_DATA0_LS_DATA1 | \
|
||||
DCU_INT_CMP_DATA0_EQ_DATA1 | \
|
||||
DCU_INT_CMP_DATA0_GT_DATA1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */
|
||||
#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */
|
||||
#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | \
|
||||
DCU_INT_CMP_WIN_OUTSIDE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Wave_Mode_Interrupt DCU Wave Mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_WAVE_SAWTOOTH_RELOAD (DCU_INTEVTSEL_SEL_RLD) /*!< DCU sawtooth wave mode reload interrupt */
|
||||
#define DCU_INT_WAVE_TRIANGLE_BOTTOM (DCU_INTEVTSEL_SEL_BTM) /*!< DCU triangle wave mode bottom interrupt */
|
||||
#define DCU_INT_WAVE_TRIANGLE_TOP (DCU_INTEVTSEL_SEL_TOP) /*!< DCU triangle wave mode top interrupt */
|
||||
#define DCU_INT_WAVE_MD_ALL (DCU_INT_WAVE_TRIANGLE_TOP |\
|
||||
DCU_INT_WAVE_TRIANGLE_BOTTOM |\
|
||||
DCU_INT_WAVE_SAWTOOTH_RELOAD)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Operation_Interrupt DCU Operation Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define DCU_INT_OP_UDF_OVF (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Data_Register_Index DCU Data Register Index
|
||||
* @{
|
||||
*/
|
||||
#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */
|
||||
#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */
|
||||
#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DCU_Common_Trigger_Source_Configure DCU common Trigger Source Configure
|
||||
* @{
|
||||
*/
|
||||
#define DCU_COM_TRIG1 (AOS_DCU_1_TRGSEL_COMTRG_EN_0)
|
||||
#define DCU_COM_TRIG2 (AOS_DCU_1_TRGSEL_COMTRG_EN_1)
|
||||
#define DCU_COM_TRIG_MASK (AOS_DCU_1_TRGSEL_COMTRG_EN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup DCU_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and configuration DCU functions */
|
||||
en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInit);
|
||||
en_result_t DCU_StructInit(stc_dcu_init_t *pstcInit);
|
||||
void DCU_DeInit(M4_DCU_TypeDef *DCUx);
|
||||
|
||||
en_result_t DCU_WaveCfg(M4_DCU_TypeDef *DCUx, const stc_dcu_wave_cfg_t *pstcCfg);
|
||||
void DCU_SetMode(M4_DCU_TypeDef *DCUx, uint32_t u32Mode);
|
||||
uint32_t DCU_GetMode(const M4_DCU_TypeDef *DCUx);
|
||||
void DCU_SetDataSize(M4_DCU_TypeDef *DCUx, uint32_t u32DataSize);
|
||||
uint32_t DCU_GetDataSize(const M4_DCU_TypeDef *DCUx);
|
||||
en_flag_status_t DCU_GetStatus(const M4_DCU_TypeDef *DCUx, uint32_t u32Flag);
|
||||
void DCU_ClearStatus(M4_DCU_TypeDef *DCUx, uint32_t u32Flag);
|
||||
void DCU_IntCmd(M4_DCU_TypeDef *DCUx,
|
||||
uint32_t u32IntCategory,
|
||||
uint32_t u32IntType,
|
||||
en_functional_state_t enNewState);
|
||||
void DCU_GlobalIntCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enNewState);
|
||||
void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx,
|
||||
uint32_t u32ComTrig,
|
||||
en_functional_state_t enNewState);
|
||||
void DCU_SetTriggerSrc(const M4_DCU_TypeDef *DCUx, en_event_src_t enEventSrc);
|
||||
|
||||
uint8_t DCU_ReadData8(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
|
||||
void DCU_WriteData8(M4_DCU_TypeDef *DCUx,
|
||||
uint32_t u32DataIndex,
|
||||
uint8_t u8Data);
|
||||
uint16_t DCU_ReadData16(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
|
||||
void DCU_WriteData16(M4_DCU_TypeDef *DCUx,
|
||||
uint32_t u32DataIndex,
|
||||
uint16_t u16Data);
|
||||
uint32_t DCU_ReadData32(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
|
||||
void DCU_WriteData32(M4_DCU_TypeDef *DCUx,
|
||||
uint32_t u32DataIndex,
|
||||
uint32_t u32Data);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_DCU_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,439 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_dmc.h
|
||||
* @brief This file contains all the functions prototypes of the EXMC DMC
|
||||
* (External Memory Controller: Dynamic Memory Controller) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Hongjh First version
|
||||
2020-07-14 Hongjh Merge API from EXMC_DMC_Enable/Disable to EXMC_DMC_Cmd
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_DMC_H__
|
||||
#define __HC32F4A0_DMC_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_EXMC_DMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_DMC_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Global_Types Dynamic Memory Controller Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXMC DMC CS Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32AddrMask; /*!< Defines the address mask.
|
||||
This parameter can be a value of @ref EXMC_DMC_Mask_Address. */
|
||||
|
||||
uint32_t u32AddrMatch; /*!< Defines the address match.
|
||||
This parameter can be a value of @ref EXMC_DMC_Match_Address. */
|
||||
|
||||
uint32_t u32AddrDecodeMode; /*!< Defines the address decode mode.
|
||||
This parameter can be a value of @ref EXMC_DMC_CS_Decode_Mode. */
|
||||
} stc_exmc_dmc_cs_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief EXMC DMC Chip Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t u32ColumnBitsNumber; /*!< Defines the number of bits of column address.
|
||||
This parameter can be a value of @ref EXMC_DMC_Column_Bits_Number. */
|
||||
|
||||
uint32_t u32RowBitsNumber; /*!< Defines the number of bits of row address.
|
||||
This parameter can be a value of @ref EXMC_DMC_Row_Bits_Number. */
|
||||
|
||||
uint32_t u32AutoPrechargePin; /*!< Defines the auto-precharge pin.
|
||||
This parameter can be a value of @ref EXMC_DMC_Auto_Precharge_Pin. */
|
||||
|
||||
uint32_t u32MemClkSel; /*!< Defines the memory clock selection.
|
||||
This parameter can be a value of @ref EXMC_DMC_MemClock_Selection */
|
||||
|
||||
uint32_t u32CkeOutputSel; /*!< Defines the CKE output selection.
|
||||
This parameter can be a value of @ref EXMC_DMC_CKE_Output_Selection */
|
||||
|
||||
uint32_t u32CkeDisablePeriod; /*!< Defines the CKE disable period.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x3F */
|
||||
|
||||
uint32_t u32MemBurst; /*!< Defines the number of data accesses.
|
||||
This parameter can be a value of @ref EXMC_DMC_Memory_Burst. */
|
||||
|
||||
uint32_t u32AutoRefreshChips; /*!< Defines the refresh command generation for the number of memory chips.
|
||||
This parameter can be a value of @ref EXMC_DMC_Auto_Refresh_Chips. */
|
||||
}stc_exmc_dmc_chip_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief EXMC DMC Timing Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32CASL; /*!< Defines the CAS latency in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32DQSS; /*!< Defines the DQSS in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 3 */
|
||||
uint32_t u32MRD; /*!< Defines the the mode register command time in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x7F */
|
||||
uint32_t u32RAS; /*!< Defines the RAS in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
|
||||
uint32_t u32RC; /*!< Defines the RC in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
|
||||
uint32_t u32RCD; /*!< Defines the RCD in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32RFC; /*!< Defines the RFC in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */
|
||||
uint32_t u32RP; /*!< Defines the RP in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32RRD; /*!< Defines the RRD in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
|
||||
uint32_t u32WR; /*!< Defines the WR in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32WTR; /*!< Defines the WTR in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
|
||||
uint32_t u32XP; /*!< Defines the XP in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
|
||||
uint32_t u32XSR; /*!< Defines the XSR in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
|
||||
uint32_t u32ESR; /*!< Defines the ESR in memory clock cycles.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
|
||||
} stc_exmc_dmc_timing_cfg_t;
|
||||
|
||||
/**
|
||||
* @brief EXMC DMC Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32DmcMemWidth; /*!< DMC memory width.
|
||||
This parameter can be a value of @ref EXMC_DMC_Memory_Width. */
|
||||
|
||||
uint32_t u32RefreshPeriod; /*!< DMC memory refresh period.
|
||||
This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFF */
|
||||
|
||||
stc_exmc_dmc_chip_cfg_t stcChipCfg; /*!< DMC memory chip configure.
|
||||
This structure details refer @ref stc_exmc_dmc_chip_cfg_t. */
|
||||
|
||||
stc_exmc_dmc_timing_cfg_t stcTimingCfg; /*!< DMC memory timing configure.
|
||||
This structure details refer @ref stc_exmc_dmc_timing_cfg_t. */
|
||||
} stc_exmc_dmc_init_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Global_Macros Dynamic Memory Controller Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Memory_Width EXMC DMC Memory Width
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_MEMORY_WIDTH_16BIT (0UL)
|
||||
#define EXMC_DMC_MEMORY_WIDTH_32BIT (DMC_BACR_DMCMW_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Chip EXMC DMC Chip
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_CHIP_0 (0UL) /*!< Chip 0 */
|
||||
#define EXMC_DMC_CHIP_1 (1UL) /*!< Chip 1 */
|
||||
#define EXMC_DMC_CHIP_2 (2UL) /*!< Chip 2 */
|
||||
#define EXMC_DMC_CHIP_3 (3UL) /*!< Chip 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Bank EXMC DMC Bank
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_BANK_0 (0UL) /*!< Bank 0 */
|
||||
#define EXMC_DMC_BANK_1 (1UL) /*!< Bank 1 */
|
||||
#define EXMC_DMC_BANK_2 (2UL) /*!< Bank 2 */
|
||||
#define EXMC_DMC_BANK_3 (3UL) /*!< Bank 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Current_Status EXMC DMC Current Status
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_CURR_STATUS_CONFIGURE (0UL)
|
||||
#define EXMC_DMC_CURR_STATUS_READY (DMC_STSR_STATUS_0)
|
||||
#define EXMC_DMC_CURR_STATUS_PAUSED (DMC_STSR_STATUS_1)
|
||||
#define EXMC_DMC_CURR_STATUS_LOWPOWER (DMC_STSR_STATUS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Control_State EXMC DMC Control State
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_CTL_STATE_GO (0UL)
|
||||
#define EXMC_DMC_CTL_STATE_SLEEP (1UL)
|
||||
#define EXMC_DMC_CTL_STATE_WAKEUP (2UL)
|
||||
#define EXMC_DMC_CTL_STATE_PAUSE (3UL)
|
||||
#define EXMC_DMC_CTL_STATE_CONFIGURE (4UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Command EXMC DMC Command
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_CMD_PRECHARGEALL (0UL) /*!< Precharge all */
|
||||
#define EXMC_DMC_CMD_AUTOREFRESH (DMC_CMDR_CMD_0) /*!< Auto refresh */
|
||||
#define EXMC_DMC_CMD_MDREGCONFIG (DMC_CMDR_CMD_1) /*!< Set memory device mode register */
|
||||
#define EXMC_DMC_CMD_NOP (DMC_CMDR_CMD) /*!< NOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Refresh_Period_Max EXMC DMC Refresh Period Max
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_REFRESH_PERIOD_MAX (0x00007FFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_CS_Decode_Mode EXMC DMC CS Decode Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_CS_DECODE_ROWBANKCOL (0UL) /*!< Row -> Bank -> Column */
|
||||
#define EXMC_DMC_CS_DECODE_BANKROWCOL (DMC_CSCR_BRC) /*!< Bank -> Row -> Column */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Column_Bits_Number EXMC DMC Column Bits Number
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_COLUMN_BITS_NUM_8 (0UL)
|
||||
#define EXMC_DMC_COLUMN_BITS_NUM_9 (DMC_CPCR_COLBS_0)
|
||||
#define EXMC_DMC_COLUMN_BITS_NUM_10 (DMC_CPCR_COLBS_1)
|
||||
#define EXMC_DMC_COLUMN_BITS_NUM_11 (DMC_CPCR_COLBS_1 | \
|
||||
DMC_CPCR_COLBS_0)
|
||||
#define EXMC_DMC_COLUMN_BITS_NUM_12 (DMC_CPCR_COLBS_2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Row_Bits_Number EXMC DMC Row Bits Number
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_ROW_BITS_NUM_11 (0UL)
|
||||
#define EXMC_DMC_ROW_BITS_NUM_12 (DMC_CPCR_ROWBS_0)
|
||||
#define EXMC_DMC_ROW_BITS_NUM_13 (DMC_CPCR_ROWBS_1)
|
||||
#define EXMC_DMC_ROW_BITS_NUM_14 (DMC_CPCR_ROWBS_1 | \
|
||||
DMC_CPCR_ROWBS_0)
|
||||
#define EXMC_DMC_ROW_BITS_NUM_15 (DMC_CPCR_ROWBS_2)
|
||||
#define EXMC_DMC_ROW_BITS_NUM_16 (DMC_CPCR_ROWBS_2 | \
|
||||
DMC_CPCR_ROWBS_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Auto_Precharge_Pin EXMC DMC Auto Pre-charge Pin
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_AUTO_PRECHARGE_A8 (DMC_CPCR_APBS)
|
||||
#define EXMC_DMC_AUTO_PRECHARGE_A10 (0UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_CKE_Output_Selection EXMC DMC CKE Output Selection
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_CKE_OUTPUT_ENABLE (0UL)
|
||||
#define EXMC_DMC_CKE_OUTPUT_DISABLE (DMC_CPCR_CKEDIS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_MemClock_Selection EXMC DMC MemClock Selection
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_MEMCLK_NORMAL_OUTPUT (0UL)
|
||||
#define EXMC_DMC_MEMCLK_NOP_STOP_OUTPUT (DMC_CPCR_CKSTOP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Memory_Burst EXMC DMC Memory Burst
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_MEM_BURST_1 (0UL)
|
||||
#define EXMC_DMC_MEM_BURST_2 (DMC_CPCR_BURST_0)
|
||||
#define EXMC_DMC_MEM_BURST_4 (DMC_CPCR_BURST_1)
|
||||
#define EXMC_DMC_MEM_BURST_8 (DMC_CPCR_BURST_1 | \
|
||||
DMC_CPCR_BURST_0)
|
||||
#define EXMC_DMC_MEM_BURST_16 (DMC_CPCR_BURST_2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Auto_Refresh_Chips EXMC DMC Auto Refresh
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_AUTO_REFRESH_CHIP_0 (0UL)
|
||||
#define EXMC_DMC_AUTO_REFRESH_CHIPS_01 (DMC_CPCR_ACTCP_0)
|
||||
#define EXMC_DMC_AUTO_REFRESH_CHIPS_012 (DMC_CPCR_ACTCP_1)
|
||||
#define EXMC_DMC_AUTO_REFRESH_CHIPS_0123 (DMC_CPCR_ACTCP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Match_Address EXMC DMC Match Address
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_ADDR_MATCH_0X80000000 (0x80UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X81000000 (0x81UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X82000000 (0x82UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X83000000 (0x83UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X84000000 (0x84UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X85000000 (0x85UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X86000000 (0x86UL << DMC_CSCR_ADDMAT_POS)
|
||||
#define EXMC_DMC_ADDR_MATCH_0X87000000 (0x87UL << DMC_CSCR_ADDMAT_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup EXMC_DMC_Mask_Address EXMC DMC Mask Address
|
||||
* @{
|
||||
*/
|
||||
#define EXMC_DMC_ADDR_MASK_16MB (0xFFUL)
|
||||
#define EXMC_DMC_ADDR_MASK_32MB (0xFEUL)
|
||||
#define EXMC_DMC_ADDR_MASK_64MB (0xFCUL)
|
||||
#define EXMC_DMC_ADDR_MASK_128MB (0xF8UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup EXMC_DMC_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get DMC status.
|
||||
* @param None
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg EXMC_DMC_CURR_STATUS_CONFIGURE: Configure status
|
||||
* @arg EXMC_DMC_CURR_STATUS_READY: Ready status
|
||||
* @arg EXMC_DMC_CURR_STATUS_PAUSED: Pause status
|
||||
* @arg EXMC_DMC_CURR_STATUS_LOWPOWER: Sleep for low power status
|
||||
*/
|
||||
__STATIC_INLINE uint32_t EXMC_DMC_GetStatus(void)
|
||||
{
|
||||
return READ_REG32_BIT(M4_DMC->STSR, DMC_STSR_STATUS);
|
||||
}
|
||||
|
||||
/* Initialization and configuration EXMC DMC functions */
|
||||
en_result_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcInit);
|
||||
void EXMC_DMC_DeInit(void);
|
||||
en_result_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcInit);
|
||||
void EXMC_DMC_Cmd(en_functional_state_t enNewState);
|
||||
en_result_t EXMC_DMC_CsConfig(uint32_t u32Chip,
|
||||
const stc_exmc_dmc_cs_cfg_t *pstcCfg);
|
||||
uint32_t EXMC_DMC_ChipStartAddress(uint32_t u32Chip);
|
||||
uint32_t EXMC_DMC_ChipEndAddress(uint32_t u32Chip);
|
||||
en_result_t EXMC_DMC_SetCommand(uint32_t u32Chip,
|
||||
uint32_t u32Bank,
|
||||
uint32_t u32Cmd,
|
||||
uint32_t u32Address);
|
||||
void EXMC_DMC_SetState(uint32_t u32State);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_DMC_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_DMC_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -1,293 +0,0 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_dvp.h
|
||||
* @brief This file contains all the functions prototypes of the DVP(Digital
|
||||
* Video Processor) driver library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-08-20 Hongjh First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_DVP_H__
|
||||
#define __HC32F4A0_DVP_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_DVP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_DVP_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DVP_Global_Types DVP Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DVP Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32SyncMode; /*!< The DVP sync mode.
|
||||
This parameter can be a value of @ref DVP_Sync_Mode. */
|
||||
uint32_t u32DataWidth; /*!< The DVP data interface width.
|
||||
This parameter can be a value of @ref DVP_Data_Width. */
|
||||
uint32_t u32CaptureMode; /*!< The DVP capture mode.
|
||||
This parameter can be a value of @ref DVP_Capture_Mode. */
|
||||
uint32_t u32CaptureFreq; /*!< The DVP capture frequence.
|
||||
This parameter can be a value of @ref DVP_Capture_Frequence. */
|
||||
uint32_t u32PIXCLKPolarity; /*!< The DVP_PIXCLK Polarity.
|
||||
This parameter can be a value of @ref DVP_PIXCLK_Polarity. */
|
||||
uint32_t u32HSYNCPolarity; /*!< The DVP_HSYNC Polarity.
|
||||
This parameter can be a value of @ref DVP_HSYNC_Polarity. */
|
||||
uint32_t u32VSYNCPolarity; /*!< The DVP_VSYNC Polarity.
|
||||
This parameter can be a value of @ref DVP_VSYNC_Polarity. */
|
||||
} stc_dvp_init_t;
|
||||
|
||||
/**
|
||||
* @brief DVP Crop Window Configure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32X; /*!< The DVP window X offset
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
uint32_t u32Y; /*!< The DVP window Y offset
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
uint32_t u32XSize; /*!< The DVP window pixel per line
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
uint32_t u32YSize; /*!< The DVP window line number.
|
||||
This parameter can be a value between 0x00 and 0x3FFF */
|
||||
} stc_dvp_crop_window_config_t;
|
||||
|
||||
/**
|
||||
* @brief DVP Software Sync Code definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32FrameStartSyncCode; /*!< The sync code of the frame start delimiter.
|
||||
This parameter can be a value between 0x00 and 0xFF */
|
||||
uint32_t u32LineStartSyncCode; /*!< The sync code of the line start delimiter.
|
||||
This parameter can be a value between 0x00 and 0xFF */
|
||||
uint32_t u32LineEndSyncCode; /*!< The sync code of the line end delimiter.
|
||||
This parameter can be a value between 0x00 and 0xFF */
|
||||
uint32_t u32FrameEndSyncCode; /*!< The sync code of the frame end delimiter.
|
||||
This parameter can be a value between 0x00 and 0xFF */
|
||||
} stc_dvp_sw_sync_code_t;
|
||||
|
||||
/**
|
||||
* @brief DVP Software Mask Code definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32FrameStartMaskCode; /*!< The mask code of the frame start delimiter.
|
||||
This parameter can be a value between between 0x00 and 0xFF */
|
||||
uint32_t u32LineStartMaskCode; /*!< The mask code of the line start delimiter.
|
||||
This parameter can be a value between between 0x00 and 0xFF */
|
||||
uint32_t u32LineEndMaskCode; /*!< The mask code of the line end delimiter.
|
||||
This parameter can be a value between between 0x00 and 0xFF */
|
||||
uint32_t u32FrameEndMaskCode; /*!< The mask code of the frame end delimiter.
|
||||
This parameter can be a value between between 0x00 and 0xFF */
|
||||
} stc_dvp_sw_mask_code_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup DVP_Global_Macros DVP Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_Capture_Mode DVP Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DVP_CAPT_MD_CONTINUOS_FRAME (0UL)
|
||||
#define DVP_CAPT_MD_SINGLE_FRAME (DVP_CTR_CAPMD)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_Sync_Mode DVP Sync Mode
|
||||
* @{
|
||||
*/
|
||||
#define DVP_SYNC_MD_HW (0UL) /*!< Hardware sync */
|
||||
#define DVP_SYNC_MD_SW (DVP_CTR_SWSYNC) /*!< Software sync */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_PIXCLK_Polarity DVP PIXCLK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DVP_PIXCLK_FALLING (0UL) /*!< DVP_PIXCLK active on Falling edge */
|
||||
#define DVP_PIXCLK_RISING (DVP_CTR_PIXCKSEL) /*!< DVP_PIXCLK active on Rising edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_HSYNC_Polarity DVP HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DVP_HSYNC_LOW (0UL) /*!< DVP_HSYNC active Low */
|
||||
#define DVP_HSYNC_HIGH (DVP_CTR_HSYNCSEL) /*!< DVP_HSYNC active High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_VSYNC_Polarity DVP VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DVP_VSYNC_LOW (0UL) /*!< DVP_VSYNC active Low */
|
||||
#define DVP_VSYNC_HIGH (DVP_CTR_VSYNCSEL) /*!< DVP_VSYNC active High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DVP_Capture_Frequence DVP Capture Frequence
|
||||
* @{
|
||||
*/
|
||||
#define DVP_CAPT_FREQ_ALL_FRAME (0UL) /*!< All frames are captured */
|
||||
#define DVP_CAPT_FREQ_ONT_TIME_2FRAME (DVP_CTR_CAPFRC_0) /*!< One frame per 2 frames captured */
|
||||
#define DVP_CAPT_FREQ_ONT_TIME_4FRAME (DVP_CTR_CAPFRC_1) /*!< One frame per 4 frames captured */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DVP_Data_Width DVP Data Width
|
||||
* @{
|
||||
*/
|
||||
#define DVP_DATA_WIDTH_8BIT (0UL) /*!< DVP captures 8-bit data on every DVP_PIXCLK clock */
|
||||
#define DVP_DATA_WIDTH_10BIT (DVP_CTR_BITSEL_0) /*!< DVP captures 10-bit data on every DVP_PIXCLK clock */
|
||||
#define DVP_DATA_WIDTH_12BIT (DVP_CTR_BITSEL_1) /*!< DVP captures 12-bit data on every DVP_PIXCLK clock */
|
||||
#define DVP_DATA_WIDTH_14BIT (DVP_CTR_BITSEL) /*!< DVP captures 14-bit data on every DVP_PIXCLK clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DVP_Flag DVP Flag
|
||||
* @{
|
||||
*/
|
||||
#define DVP_FLAG_FRAME_START (DVP_STR_FSF) /*!< Frame start flag */
|
||||
#define DVP_FLAG_LINE_START (DVP_STR_LSF) /*!< Line start flag */
|
||||
#define DVP_FLAG_LINE_END (DVP_STR_LEF) /*!< Line end flag */
|
||||
#define DVP_FLAG_FRAME_END (DVP_STR_FEF) /*!< Frame end flag */
|
||||
#define DVP_FLAG_FIFO_OVF (DVP_STR_FIFOERF) /*!< FIFO overflow error flag */
|
||||
#define DVP_FLAG_SYNC_ERR (DVP_STR_SQUERF) /*!< Sync error flag */
|
||||
#define DVP_FLAG_ALL (DVP_FLAG_SYNC_ERR | \
|
||||
DVP_FLAG_FIFO_OVF | \
|
||||
DVP_FLAG_LINE_END | \
|
||||
DVP_FLAG_LINE_START | \
|
||||
DVP_FLAG_FRAME_END | \
|
||||
DVP_FLAG_FRAME_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup DVP_Interrupt DVP Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define DVP_INT_FRAME_START (DVP_IER_FSIEN) /*!< Frame start interrupt */
|
||||
#define DVP_INT_LINE_START (DVP_IER_LSIEN) /*!< Line start interrupt */
|
||||
#define DVP_INT_LINE_END (DVP_IER_LEIEN) /*!< Line end interrupt */
|
||||
#define DVP_INT_FRAME_END (DVP_IER_FEIEN) /*!< Frame end interrupt */
|
||||
#define DVP_INT_FIFO_OVF (DVP_IER_FIFOERIEN) /*!< FIFO overflow error interrupt */
|
||||
#define DVP_INT_SYNC_ERR (DVP_IER_SQUERIEN) /*!< Sync error interrupt */
|
||||
#define DVP_INT_ALL (DVP_INT_SYNC_ERR | \
|
||||
DVP_INT_FIFO_OVF | \
|
||||
DVP_INT_LINE_END | \
|
||||
DVP_INT_LINE_START | \
|
||||
DVP_INT_FRAME_END | \
|
||||
DVP_INT_FRAME_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup DVP_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
en_result_t DVP_Init(const stc_dvp_init_t *pstcDvpInit);
|
||||
void DVP_DeInit(void);
|
||||
en_result_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit);
|
||||
void DVP_Cmd(en_functional_state_t enNewState);
|
||||
void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
|
||||
void DVP_CropCmd(en_functional_state_t enNewState);
|
||||
void DVP_JPEGCmd(en_functional_state_t enNewState);
|
||||
void DVP_CaptrueCmd(en_functional_state_t enNewState);
|
||||
en_functional_state_t DVP_GetCaptrueCmdState(void);
|
||||
en_flag_status_t DVP_GetStatus(uint32_t u32Flag);
|
||||
void DVP_ClearStatus(uint32_t u32Flag);
|
||||
en_result_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode);
|
||||
en_result_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode);
|
||||
en_result_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_DVP_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_DVP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
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Reference in New Issue
Block a user