Add the BSP of HC32 series. (#5905)

* Add the BSP of HC32 series.
2026-02-06 17:12:01 +08:00 · 2022-05-06 09:28:21 +08:00
parent 0e66f3f833
commit 28b551bfe3
345 changed files with 402773 additions and 0 deletions
--- a/bsp/hc32/README.md
+++ b/bsp/hc32/README.md
@@ -0,0 +1,22 @@
+
+# HC32 BSP 说明
+
+HC32 系列 BSP 目前支持情况如下表所示：
+
+| **BSP 文件夹名称**       | **开发板名称**                 |
+|:------------------------- |:------------------------- |
+| **F1 系列** |  |
+| **F4 系列** |  |
+| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
+| **M1 系列** |  |
+| **M4 系列** |  |
+
+可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
+
+| **BSP 使用教程** | **简介**                                          |
+|:-------------------- |:------------------------------------------------- |
+| [外设驱动使用教程](docs/HC32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
+| [外设驱动介绍与应用](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
+| **BSP 制作与提交** | **简介**                                     |
+| [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 |
+
--- a/bsp/hc32/docs/HC32系列BSP制作教程.md
+++ b/bsp/hc32/docs/HC32系列BSP制作教程.md
@@ -0,0 +1,2 @@
+# HC32 系列 BSP 制作教程
+
--- a/bsp/hc32/docs/HC32系列BSP外设驱动使用教程.md
+++ b/bsp/hc32/docs/HC32系列BSP外设驱动使用教程.md
@@ -0,0 +1 @@
+# HC32系列BSP外设驱动使用教程
--- a/bsp/hc32/docs/HC32系列驱动介绍.md
+++ b/bsp/hc32/docs/HC32系列驱动介绍.md
@@ -0,0 +1,2 @@
+# HC32系列驱动介绍
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/.config
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.config
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.gitignore
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md
@@ -0,0 +1,116 @@
+# XHSC EV_F4A0_LQ176 开发板 BSP 说明
+
+## 简介
+
+本文档为小华半导体为 EV_F4A0_LQ176 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+EV_F4A0_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A0SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A0SITB 的芯片性能。
+
+开发板外观如下图所示：
+
+ ![board](figures/board.jpg)
+
+EV_F4A0_LQ176 开发板常用 **板载资源** 如下：
+
+- MCU：HC32F4A0SITB，主频240MHz，2048KB FLASH，512KB RAM
+- 外部RAM：IS62WV51216(SRAM, 1MB) IS42S16400J(SDRAM, 8MB)
+- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 64MB)
+- 常用外设
+  - LED：3 个， user LED(LED0,LED1,LED2)。
+  - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。
+- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口
+- 调试接口：板载DAP调试器、标准JTAG/SWD。
+
+开发板更多详细信息请参考小华半导体半导体[EV_F4A0_LQ176](http://www.xhsc.com.cn)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| USB 转串口    |      支持     |          使用 UART1                  |
+| SPI Flash     |     支持     |           使用 SPI1                   |
+| LED           |     支持     |           LED                   |
+| **片上外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| GPIO          |     支持     | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
+| UART          |     支持     |              UART1~10                 |
+| SPI           |     支持     |              SPI1~6                   |
+| I2C           |     支持     |              软件 I2C                 |
+| RTC           |     支持     |      支持外部晶振和内部低速时钟         |
+| PWM           |     支持     |                                       |
+| HWTIMER       |     支持     |                                       |
+| LED           |     支持     |              LED11                    |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用Type-A to MircoUSB线连接开发板和PC供电。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。
+
+USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.0 build Apr 24 2022 13:32:39
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+
+## 联系人信息
+
+维护人:
+
+-  [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/SConscript
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hc32_library = 'hc32f4a0_ddl'
+rtconfig.BSP_LIBRARY_TYPE = hc32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/SConscript
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+
+/* defined the LED_GREEN pin: PC9 */
+#define LED_GREEN_PIN GET_PIN(C, 9)
+
+
+int main(void)
+{
+    /* set LED_GREEN_PIN pin mode to output */
+    rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_GREEN_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig
@@ -0,0 +1,372 @@
+menu "Hardware Drivers Config"
+
+config SOC_HC32F4A0SI
+    bool 
+    select SOC_SERIES_HC32F4
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config PHY_USING_RTL8201F
+        bool
+
+    menuconfig BSP_USING_ETH
+        bool "Enable Ethernet"
+        default n
+        select BSP_USING_I2C1
+        select RT_USING_LWIP
+        select PHY_USING_RTL8201F
+        select RT_LWIP_USING_HW_CHECKSUM
+        select BSP_USING_TCA9539
+        if BSP_USING_ETH
+            config ETH_USING_INTERFACE_RMII
+                bool "select RMII interface"
+                default n
+
+            config PHY_USING_INTERRUPT_MODE
+                bool "enable phy interrupt mode"
+                select ETH_PHY_INT_PIN
+                default n
+ 
+            config ETH_PHY_INT_PIN
+                int 
+                default 16
+        endif
+
+    config BSP_USING_TCA9539
+        bool "Enable TCA9539"
+        select BSP_USING_I2C1
+        default n
+
+    config BSP_USING_SPI_FLASH
+        bool "Enable SPI FLASH (spi1)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI1
+        default n
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+
+            config BSP_UART1_RX_USING_DMA
+                bool "Enable UART1 RX DMA"
+                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART1_TX_USING_DMA
+                bool "Enable UART1 TX DMA"
+                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART2_TX_USING_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                default n
+            
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+
+            config BSP_USING_UART5
+                bool "Enable UART5"
+                default n
+
+            config BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+            
+            config BSP_UART6_RX_USING_DMA
+                bool "Enable UART6 RX DMA"
+                depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART6_TX_USING_DMA
+                bool "Enable UART6 TX DMA"
+                depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_USING_UART7
+                bool "Enable UART7"
+                default n
+
+            config BSP_UART7_RX_USING_DMA
+                bool "Enable UART7 RX DMA"
+                depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART7_TX_USING_DMA
+                bool "Enable UART7 TX DMA"
+                depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_USING_UART8
+                bool "Enable UART8"
+                default n
+
+            config BSP_USING_UART9
+                bool "Enable UART9"
+                default n
+
+            config BSP_USING_UART10
+                bool "Enable UART10"
+                default n
+        endif
+
+    menuconfig BSP_USING_I2C1
+        bool "Enable I2C1 BUS (software simulation)"
+        default y
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN 
+        if BSP_USING_I2C1
+            config BSP_I2C1_SCL_PIN
+                int "i2c1 scl pin number"
+                range 1 176
+                default 51
+            config BSP_I2C1_SDA_PIN
+                int "I2C1 sda pin number"
+                range 1 176
+                default 90
+        endif 
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1 BUS"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                depends on BSP_USING_SPI1
+                default n
+                
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                depends on BSP_USING_SPI1
+                select BSP_SPI1_TX_USING_DMA
+                default n
+                
+            config BSP_USING_SPI2
+                bool "Enable SPI2 BUS"
+                default n  
+                
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                depends on BSP_USING_SPI2
+                default n
+                
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                depends on BSP_USING_SPI2
+                select BSP_SPI2_TX_USING_DMA
+                default n
+                
+            config BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n        
+
+            config BSP_SPI3_TX_USING_DMA
+                bool "Enable SPI3 TX DMA"
+                depends on BSP_USING_SPI3
+                default n
+                
+            config BSP_SPI3_RX_USING_DMA
+                bool "Enable SPI3 RX DMA"
+                depends on BSP_USING_SPI3
+                select BSP_SPI3_TX_USING_DMA
+                default n  
+
+            config BSP_USING_SPI4
+                bool "Enable SPI4 BUS"
+                default n
+
+            config BSP_SPI4_TX_USING_DMA
+                bool "Enable SPI4 TX DMA"
+                depends on BSP_USING_SPI4
+                default n
+                
+            config BSP_SPI4_RX_USING_DMA
+                bool "Enable SPI4 RX DMA"
+                depends on BSP_USING_SPI4
+                select BSP_SPI4_TX_USING_DMA
+                default n
+        endif
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+        if BSP_USING_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_LRC
+
+                config BSP_RTC_USING_XTAL32
+                    bool "RTC USING XTAL32"
+
+                config BSP_RTC_USING_LRC
+                    bool "RTC USING LRC"
+            endchoice
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        menuconfig BSP_USING_PWM1
+            bool "Enable timer1 output PWM"
+            default n
+            if BSP_USING_PWM1
+                config BSP_USING_PWM1_CH1
+                    bool "Enable PWM1 channel1"
+                    default n
+
+                config BSP_USING_PWM1_CH2
+                    bool "Enable PWM1 channel2"
+                    default n
+
+                config BSP_USING_PWM1_CH3
+                    bool "Enable PWM1 channel3"
+                    default n
+
+                config BSP_USING_PWM1_CH4
+                    bool "Enable PWM1 channel4"
+                    default n
+            endif
+
+        menuconfig BSP_USING_PWM2
+            bool "Enable timer2 output PWM"
+            default n
+            if BSP_USING_PWM2
+                config BSP_USING_PWM2_CH1
+                    bool "Enable PWM2 channel1"
+                    default n
+
+                config BSP_USING_PWM2_CH2
+                    bool "Enable PWM2 channel2"
+                    default n
+
+                config BSP_USING_PWM2_CH3
+                    bool "Enable PWM2 channel3"
+                    default n
+
+                config BSP_USING_PWM2_CH4
+                    bool "Enable PWM2 channel4"
+                    default n
+            endif
+        endif
+
+    menuconfig BSP_USING_TIMER
+        bool "Enable TIMER"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIMER
+            config BSP_USING_TIMER5
+                bool "Enable TIMER5"
+                default n
+
+            config BSP_USING_TIMER6
+                bool "Enable TIMER6"
+                default n
+
+            config BSP_USING_TIMER7
+                bool "Enable TIMER7"
+                default n
+
+            config BSP_USING_TIMER8
+                bool "Enable TIMER8"
+                default n
+        endif
+
+    menuconfig BSP_USING_PULSE_ENCODER
+        bool "Enable Pulse Encoder"
+        default n
+        select RT_USING_PULSE_ENCODER
+        if BSP_USING_PULSE_ENCODER
+            config BSP_USING_PULSE_ENCODER9
+                bool "Enable Pulse Encoder9"
+                default n
+
+            config BSP_USING_PULSE_ENCODER10
+                bool "Enable Pulse Encoder10"
+                default n
+
+            config BSP_USING_PULSE_ENCODER11
+                bool "Enable Pulse Encoder11"
+                default n
+
+            config BSP_USING_PULSE_ENCODER12
+                bool "Enable Pulse Encoder12"
+                default n
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "using adc1"
+                default n
+            config BSP_USING_ADC2
+                bool "using adc2"
+                default n
+            config BSP_USING_ADC3
+                bool "using adc3"
+                default n
+        endif
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        select BSP_USING_TCA9539
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using can1"
+                default n
+            config BSP_USING_CAN2
+                bool "using can2"
+                default n
+        endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+ 
+endmenu
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript
@@ -0,0 +1,36 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+board_config.c
+''')
+
+if GetDepend(['BSP_USING_TCA9539']):
+    src += Glob('ports/tca9539.c')
+
+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('ports/spi_flash.c')
+
+path =  [cwd]
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
+
+CPPDEFINES = ['HC32F4A0']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include "board.h"
+
+/* unlock/lock peripheral */
+#define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
+                                         LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
+#define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void Error_Handler(void)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    stc_clock_xtal_init_t stcXtalInit;
+    stc_clock_pll_init_t stcPLLHInit;
+
+    /* PCLK0, HCLK  Max 240MHz */
+    /* PCLK1, PCLK4 Max 120MHz */
+    /* PCLK2, PCLK3 Max 60MHz  */
+    /* EX BUS Max 120MHz */
+    CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
+                    (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
+                     CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
+                     CLK_HCLK_DIV1));
+
+    (void)CLK_XtalStructInit(&stcXtalInit);
+    /* Config Xtal and enable Xtal */
+    stcXtalInit.u8Mode   = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8Drv    = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8State  = CLK_XTAL_ON;
+    stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
+    (void)CLK_XtalInit(&stcXtalInit);
+
+    (void)CLK_PLLStructInit(&stcPLLHInit);
+    /* VCO = (8/1)*120 = 960MHz*/
+    stcPLLHInit.u8PLLState = CLK_PLL_ON;
+    stcPLLHInit.PLLCFGR = 0UL;
+    stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+    (void)CLK_PLLInit(&stcPLLHInit);
+
+    /* Highspeed SRAM set to 0 Read/Write wait cycle */
+    SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
+
+    /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
+    SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
+
+    /* 0-wait @ 40MHz */
+    (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
+
+    /* 4 cycles for 200 ~ 250MHz */
+    GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
+
+    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    stc_clock_freq_t stcClkFreq;
+    rt_uint32_t cnts;
+
+    CLK_GetClockFreq(&stcClkFreq);
+
+    cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
+
+    SysTick_Config(cnts);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+    /* Peripheral registers write unprotected */
+    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
+
+    SystemClock_Config();
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    uint32_t start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = SystemCoreClock / 1000000UL;
+
+    do
+    {
+        now = SysTick->VAL;
+        delta = start > now ?  start - now : reload + start - now;
+    }
+    while (delta < us_tick * us);
+}
+
+/*@}*/
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "hc32_ll.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HC32_SRAM_SIZE                  (512)
+#define HC32_SRAM_END                   (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN                      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN                      (&__bss_end)
+#endif
+
+#define HEAP_END                        HC32_SRAM_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <rtdevice.h>
+#include "board_config.h"
+#include "tca9539.h"
+
+/**
+ * The below functions will initialize HC32 board.
+ */
+
+#if defined RT_USING_SERIAL
+rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)USARTx)
+    {
+#if defined(BSP_USING_UART1)
+    case (rt_uint32_t)CM_USART1:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, GPIO_FUNC_33);
+        GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, GPIO_FUNC_32);
+        break;
+#endif
+#if defined(BSP_USING_UART6)
+    case (rt_uint32_t)CM_USART6:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, GPIO_FUNC_37);
+        GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, GPIO_FUNC_36);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_PWM)
+rt_err_t rt_hw_board_pwm_init(CM_TMRA_TypeDef *TMRAx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)TMRAx)
+    {
+#if defined(BSP_USING_PWM1)
+    case (rt_uint32_t)CM_TMRA_1:
+#if defined(BSP_USING_PWM1_CH1)
+        GPIO_SetFunc(PWM1_CH1_PORT, PWM1_CH1_PIN, PWM1_CH1_FUNC);
+#endif
+#if defined(BSP_USING_PWM1_CH2)
+        GPIO_SetFunc(PWM1_CH2_PORT, PWM1_CH2_PIN, PWM1_CH2_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)TMRAx)
+    {
+#if defined(BSP_USING_PULSE_ENCODER9)
+    case (rt_uint32_t)CM_TMRA_9:
+        GPIO_SetFunc(PULSE_ENCODER9_CLKA_PORT, PULSE_ENCODER9_CLKA_PIN, PULSE_ENCODER9_CLKA_FUNC);
+        GPIO_SetFunc(PULSE_ENCODER9_CLKB_PORT, PULSE_ENCODER9_CLKB_PIN, PULSE_ENCODER9_CLKB_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_ADC)
+void rt_hw_board_adc_clock_init(void)
+{
+    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
+
+    /* 1. Enable ADC peripheral clock. */
+#if defined(BSP_USING_ADC1)
+    FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE);
+#endif
+#if defined(BSP_USING_ADC2)
+    FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE);
+#endif
+#if defined(BSP_USING_ADC3)
+    FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE);
+#endif
+}
+
+rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    switch ((rt_uint32_t)ADCx)
+    {
+#if defined(BSP_USING_ADC1)
+    case (rt_uint32_t)CM_ADC1:
+
+        (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_ADC2)
+    case (rt_uint32_t)CM_ADC2:
+
+        (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_ADC3)
+    case (rt_uint32_t)CM_ADC3:
+
+        (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_CAN)
+void CanPhyEnable(void)
+{
+    TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET);
+    TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT);
+}
+rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)CANx)
+    {
+#if defined(BSP_USING_CAN1)
+    case (rt_uint32_t)CM_CAN1:
+        GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_CAN2)
+    case (rt_uint32_t)CM_CAN2:
+        GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+
+#if defined (RT_USING_SPI)
+rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)CM_SPIx)
+    {
+#if defined(BSP_USING_SPI1)
+    case (rt_uint32_t)CM_SPI1:
+        GPIO_SetFunc(GPIO_PORT_C, GPIO_PIN_06, GPIO_FUNC_40);   /* SCK  */
+        GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_13, GPIO_FUNC_41);   /* MOSI */
+        GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_12, GPIO_FUNC_42);   /* MISO */
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_ETH)
+/* PHY hardware reset time */
+#define PHY_HW_RST_DELAY                (0x40U)
+
+rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx)
+{
+    TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT);
+    TCA9539_WritePin(TCA9539_IO_PORT1,  EIO_ETH_RST, TCA9539_PIN_RESET);
+    rt_thread_mdelay(PHY_HW_RST_DELAY);
+    TCA9539_WritePin(TCA9539_IO_PORT1,  EIO_ETH_RST, TCA9539_PIN_SET);
+    rt_thread_mdelay(PHY_HW_RST_DELAY);
+    return RT_EOK;
+}
+
+rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx)
+{
+#if defined(ETH_USING_INTERFACE_RMII)
+    /*
+        ETH_SMI_MDIO ----------------> PA2
+        ETH_SMI_MDC -----------------> PC1
+        ETH_RMII_TX_EN --------------> PG11
+        ETH_RMII_TXD0 ---------------> PG13
+        ETH_RMII_TXD1 ---------------> PG14
+        ETH_RMII_REF_CLK ------------> PA1
+        ETH_RMII_CRS_DV -------------> PA7
+        ETH_RMII_RXD0 ---------------> PC4
+        ETH_RMII_RXD1 ---------------> PC5
+        ETH_RMII_RX_ER --------------> PI10
+    */
+    /* Configure PA1, PA2 and PA7 */
+    GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11);
+    /* Configure PC1, PC4 and PC5 */
+    GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11);
+    /* Configure PG11, PG13 and PG14 */
+    GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11);
+    /* Configure PI10 */
+    GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11);
+#else
+    /*
+        ETH_SMI_MDIO ----------------> PA2
+        ETH_SMI_MDC -----------------> PC1
+        ETH_MII_TX_CLK --------------> PB6
+        ETH_MII_TX_EN ---------------> PG11
+        ETH_MII_TXD0 ----------------> PG13
+        ETH_MII_TXD1 ----------------> PG14
+        ETH_MII_TXD2 ----------------> PB9
+        ETH_MII_TXD3 ----------------> PB8
+        ETH_MII_RX_CLK --------------> PA1
+        ETH_MII_RX_DV ---------------> PA7
+        ETH_MII_RXD0 ----------------> PC4
+        ETH_MII_RXD1 ----------------> PC5
+        ETH_MII_RXD2 ----------------> PB0
+        ETH_MII_RXD3 ----------------> PB1
+        ETH_MII_RX_ER ---------------> PI10
+        ETH_MII_CRS -----------------> PH2
+        ETH_MII_COL -----------------> PH3
+    */
+    /* Configure PA1, PA2 and PA7 */
+    GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11);
+    /* Configure PB0, PB1, PB6, PB8 and PB9 */
+    GPIO_SetFunc(GPIO_PORT_B, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_06 | GPIO_PIN_08 | GPIO_PIN_09), GPIO_FUNC_11);
+    /* Configure PC1, PC4 and PC5 */
+    GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11);
+    /* Configure PG11, PG13 and PG14 */
+    GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11);
+    /* Configure PH2, PH3 */
+    GPIO_SetFunc(GPIO_PORT_H, (GPIO_PIN_02 | GPIO_PIN_03), GPIO_FUNC_11);
+    /* Configure PI10 */
+    GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11);
+#endif
+    return RT_EOK;
+}
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+
+#ifndef __BOARD_CONFIG_H__
+#define __BOARD_CONFIG_H__
+
+#include <rtconfig.h>
+#include "hc32_ll.h"
+#include "drv_config.h"
+
+
+/************************ USART port **********************/
+#if defined(BSP_USING_UART1)
+    #define USART1_RX_PORT                  (GPIO_PORT_H)
+    #define USART1_RX_PIN                   (GPIO_PIN_13)
+
+    #define USART1_TX_PORT                  (GPIO_PORT_H)
+    #define USART1_TX_PIN                   (GPIO_PIN_15)
+#endif
+
+#if defined(BSP_USING_UART6)
+    #define USART6_RX_PORT                  (GPIO_PORT_H)
+    #define USART6_RX_PIN                   (GPIO_PIN_06)
+
+    #define USART6_TX_PORT                  (GPIO_PORT_E)
+    #define USART6_TX_PIN                   (GPIO_PIN_06)
+#endif
+
+/*********************** PWM port *************************/
+#if defined(BSP_USING_PWM1)
+
+    #if defined(BSP_USING_PWM1_CH1)
+        #define PWM1_CH1_PORT                   (GPIO_PORT_A)
+        #define PWM1_CH1_PIN                    (GPIO_PIN_08)
+        #define PWM1_CH1_FUNC                   (GPIO_FUNC_4)
+    #endif
+
+    #if defined(BSP_USING_PWM1_CH2)
+        #define PWM1_CH2_PORT                   (GPIO_PORT_A)
+        #define PWM1_CH2_PIN                    (GPIO_PIN_09)
+        #define PWM1_CH2_FUNC                   (GPIO_FUNC_4)
+    #endif
+
+#endif
+
+/****************** Pulse encoder port ********************/
+#if defined(BSP_USING_PULSE_ENCODER9)
+    #define PULSE_ENCODER9_CLKA_PORT        (GPIO_PORT_G)
+    #define PULSE_ENCODER9_CLKA_PIN         (GPIO_PIN_04)
+    #define PULSE_ENCODER9_CLKA_FUNC        (GPIO_FUNC_4)
+
+    #define PULSE_ENCODER9_CLKB_PORT        (GPIO_PORT_G)
+    #define PULSE_ENCODER9_CLKB_PIN         (GPIO_PIN_05)
+    #define PULSE_ENCODER9_CLKB_FUNC        (GPIO_FUNC_4)
+#endif
+
+/***********  ADC configure *********/
+#if defined(BSP_USING_ADC1)
+    #define ADC1_CH_PORT                     (GPIO_PORT_C)
+    #define ADC1_CH_PIN                      (GPIO_PIN_00)
+#endif
+
+#if defined(BSP_USING_ADC2)
+    #define ADC2_CH_PORT                     (GPIO_PORT_C)
+    #define ADC2_CH_PIN                      (GPIO_PIN_01)
+#endif
+
+#if defined(BSP_USING_ADC3)
+    #define ADC3_CH_PORT                     (GPIO_PORT_C)
+    #define ADC3_CH_PIN                      (GPIO_PIN_02)
+#endif
+
+/***********  CAN configure *********/
+#if defined(BSP_USING_CAN1)
+    #define CAN1_TX_PORT                     (GPIO_PORT_D)
+    #define CAN1_TX_PIN                      (GPIO_PIN_05)
+    #define CAN1_TX_PIN_FUNC                 (GPIO_FUNC_60)
+
+    #define CAN1_RX_PORT                     (GPIO_PORT_D)
+    #define CAN1_RX_PIN                      (GPIO_PIN_04)
+    #define CAN1_RX_PIN_FUNC                 (GPIO_FUNC_61)
+
+    #define CAN1_INT_PRIO                    (DDL_IRQ_PRIO_03)
+    #define CAN1_INT_SRC                     (INT_SRC_CAN1_HOST)
+    #define CAN1_INT_IRQn                    (INT004_IRQn)
+#endif
+
+#if defined(BSP_USING_CAN2)
+    #define CAN2_TX_PORT                     (GPIO_PORT_D)
+    #define CAN2_TX_PIN                      (GPIO_PIN_07)
+    #define CAN2_TX_PIN_FUNC                 (GPIO_FUNC_62)
+
+    #define CAN2_RX_PORT                     (GPIO_PORT_D)
+    #define CAN2_RX_PIN                      (GPIO_PIN_06)
+    #define CAN2_RX_PIN_FUNC                 (GPIO_FUNC_63)
+
+    #define CAN2_INT_PRIO                    (DDL_IRQ_PRIO_03)
+    #define CAN2_INT_SRC                     (INT_SRC_CAN2_HOST)
+    #define CAN2_INT_IRQn                    (INT005_IRQn)
+#endif
+
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                             \
+    {                                                                           \
+       .name                            = "adc1",                               \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                             \
+    {                                                                           \
+       .name                            = "adc2",                               \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                             \
+    {                                                                           \
+       .name                            = "adc3",                               \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_CAN1
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                                         \
+    {                                                       \
+       .name = "can1",                                      \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+#ifndef CAN2_CONFIG
+#define CAN2_CONFIG                                         \
+    {                                                       \
+       .name = "can2",                                      \
+    }
+#endif /* CAN2_CONFIG */
+#endif /* BSP_USING_CAN2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 ch0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_RX_DMA_INSTANCE            CM_DMA1
+#define SPI1_RX_DMA_CHANNEL             DMA_CH0
+#define SPI1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI1_RX_DMA_IRQn                INT038_IRQn
+#define SPI1_RX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#endif
+
+/* DMA1 ch1 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_TX_DMA_INSTANCE            CM_DMA1
+#define SPI1_TX_DMA_CHANNEL             DMA_CH1
+#define SPI1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI1_TX_DMA_IRQn                INT039_IRQn
+#define SPI1_TX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#endif
+
+/* DMA1 ch2 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_RX_DMA_INSTANCE            CM_DMA1
+#define SPI2_RX_DMA_CHANNEL             DMA_CH2
+#define SPI2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_RX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define SPI2_RX_DMA_IRQn                INT040_IRQn
+#define SPI2_RX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#endif
+
+/* DMA1 ch3 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_TX_DMA_INSTANCE            CM_DMA1
+#define SPI2_TX_DMA_CHANNEL             DMA_CH3
+#define SPI2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_TX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define SPI2_TX_DMA_IRQn                INT041_IRQn
+#define SPI2_TX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+#endif
+
+/* DMA1 ch4 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE            CM_DMA1
+#define SPI3_RX_DMA_CHANNEL             DMA_CH4
+#define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA1_4
+#define SPI3_RX_DMA_IRQn                INT042_IRQn
+#define SPI3_RX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC4
+#endif
+
+/* DMA1 ch5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE            CM_DMA1
+#define SPI3_TX_DMA_CHANNEL             DMA_CH5
+#define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA1_5
+#define SPI3_TX_DMA_IRQn                INT043_IRQn
+#define SPI3_TX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC5
+#endif
+
+/* DMA1 ch6 */
+#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_RX_DMA_INSTANCE            CM_DMA1
+#define SPI4_RX_DMA_CHANNEL             DMA_CH6
+#define SPI4_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI4_RX_DMA_TRIG_SELECT         AOS_DMA1_6
+#define SPI4_RX_DMA_IRQn                INT018_IRQn
+#define SPI4_RX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC6
+#endif
+
+/* DMA1 ch7 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_TX_DMA_INSTANCE            CM_DMA1
+#define SPI4_TX_DMA_CHANNEL             DMA_CH7
+#define SPI4_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI4_TX_DMA_TRIG_SELECT         AOS_DMA1_7
+#define SPI4_TX_DMA_IRQn                INT019_IRQn
+#define SPI4_TX_DMA_INT_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define SPI4_TX_DMA_INT_SRC             INT_SRC_DMA1_TC7
+#endif
+
+/* DMA2 ch0 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE           CM_DMA2
+#define UART1_RX_DMA_CHANNEL            DMA_CH0
+#define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_RX_DMA_TRIG_SELECT        AOS_DMA2_0
+#define UART1_RX_DMA_IRQn               INT044_IRQn
+#define UART1_RX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART1_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
+#endif
+
+/* DMA2 ch1 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE           CM_DMA2
+#define UART1_TX_DMA_CHANNEL            DMA_CH1
+#define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_1
+#define UART1_TX_DMA_IRQn               INT045_IRQn
+#define UART1_TX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
+#endif
+
+/* DMA2 ch2 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_RX_DMA_INSTANCE           CM_DMA2
+#define UART2_RX_DMA_CHANNEL            DMA_CH2
+#define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_RX_DMA_TRIG_SELECT        AOS_DMA2_2
+#define UART2_RX_DMA_IRQn               INT046_IRQn
+#define UART2_RX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART2_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#endif
+
+/* DMA2 ch3 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE           CM_DMA2
+#define UART2_TX_DMA_CHANNEL            DMA_CH3
+#define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_3
+#define UART2_TX_DMA_IRQn               INT047_IRQn
+#define UART2_TX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
+#endif
+
+/* DMA2 ch4 */
+#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_RX_DMA_INSTANCE           CM_DMA2
+#define UART6_RX_DMA_CHANNEL            DMA_CH4
+#define UART6_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART6_RX_DMA_TRIG_SELECT        AOS_DMA2_4
+#define UART6_RX_DMA_IRQn               INT048_IRQn
+#define UART6_RX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART6_RX_DMA_INT_SRC            INT_SRC_DMA2_TC4
+#endif
+
+/* DMA2 ch5 */
+#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_TX_DMA_INSTANCE           CM_DMA2
+#define UART6_TX_DMA_CHANNEL            DMA_CH5
+#define UART6_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART6_TX_DMA_TRIG_SELECT        AOS_DMA2_5
+#define UART6_TX_DMA_IRQn               INT049_IRQn
+#define UART6_TX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART6_TX_DMA_INT_SRC            INT_SRC_DMA2_TC5
+#endif
+
+/* DMA2 ch6 */
+#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_RX_DMA_INSTANCE           CM_DMA2
+#define UART7_RX_DMA_CHANNEL            DMA_CH6
+#define UART7_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART7_RX_DMA_TRIG_SELECT        AOS_DMA2_6
+#define UART7_RX_DMA_IRQn               INT020_IRQn
+#define UART7_RX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART7_RX_DMA_INT_SRC            INT_SRC_DMA2_TC6
+#endif
+
+/* DMA2 ch7 */
+#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_TX_DMA_INSTANCE           CM_DMA2
+#define UART7_TX_DMA_CHANNEL            DMA_CH7
+#define UART7_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART7_TX_DMA_TRIG_SELECT        AOS_DMA2_7
+#define UART7_TX_DMA_IRQn               INT021_IRQn
+#define UART7_TX_DMA_INT_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define UART7_TX_DMA_INT_SRC            INT_SRC_DMA2_TC7
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __ETH_CONFIG_H__
+#define __ETH_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_ETH)
+
+#ifndef ETH_IRQ_CONFIG
+#define ETH_IRQ_CONFIG                                      \
+    {                                                       \
+        .irq_num    = INT104_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_ETH_GLB_INT,                  \
+    }
+#endif /* ETH_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ETH_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __GPIO_CONFIG_H__
+#define __GPIO_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(RT_USING_PIN)
+
+#ifndef EXTINT0_IRQ_CONFIG
+#define EXTINT0_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT022_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ0,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT1_IRQ_CONFIG
+#define EXTINT1_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT023_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ1,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT2_IRQ_CONFIG
+#define EXTINT2_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT024_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ2,                   \
+    }
+#endif /* EXTINT2_IRQ_CONFIG */
+
+#ifndef EXTINT3_IRQ_CONFIG
+#define EXTINT3_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT025_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ3,                   \
+    }
+#endif /* EXTINT3_IRQ_CONFIG */
+
+#ifndef EXTINT4_IRQ_CONFIG
+#define EXTINT4_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT026_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ4,                   \
+    }
+#endif /* EXTINT4_IRQ_CONFIG */
+
+#ifndef EXTINT5_IRQ_CONFIG
+#define EXTINT5_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT027_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ5,                   \
+    }
+#endif /* EXTINT5_IRQ_CONFIG */
+
+#ifndef EXTINT6_IRQ_CONFIG
+#define EXTINT6_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT028_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ6,                   \
+    }
+#endif /* EXTINT6_IRQ_CONFIG */
+
+#ifndef EXTINT7_IRQ_CONFIG
+#define EXTINT7_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT029_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ7,                   \
+    }
+#endif /* EXTINT7_IRQ_CONFIG */
+
+#ifndef EXTINT8_IRQ_CONFIG
+#define EXTINT8_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT030_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ8,                   \
+    }
+#endif /* EXTINT8_IRQ_CONFIG */
+
+#ifndef EXTINT9_IRQ_CONFIG
+#define EXTINT9_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = INT031_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ9,                   \
+    }
+#endif /* EXTINT9_IRQ_CONFIG */
+
+#ifndef EXTINT10_IRQ_CONFIG
+#define EXTINT10_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = INT032_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ10,                  \
+    }
+#endif /* EXTINT10_IRQ_CONFIG */
+
+#ifndef EXTINT11_IRQ_CONFIG
+#define EXTINT11_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = INT033_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ11,                  \
+    }
+#endif /* EXTINT11_IRQ_CONFIG */
+
+#ifndef EXTINT12_IRQ_CONFIG
+#define EXTINT12_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = INT034_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ12,                  \
+    }
+#endif /* EXTINT12_IRQ_CONFIG */
+
+#ifndef EXTINT13_IRQ_CONFIG
+#define EXTINT13_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = INT035_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ13,                  \
+    }
+#endif /* EXTINT13_IRQ_CONFIG */
+
+#ifndef EXTINT14_IRQ_CONFIG
+#define EXTINT14_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = INT036_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ14,                  \
+    }
+#endif /* EXTINT14_IRQ_CONFIG */
+
+#ifndef EXTINT15_IRQ_CONFIG
+#define EXTINT15_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = INT037_IRQn,                          \
+        .irq_prio   = DDL_IRQ_PRIO_DEFAULT,                 \
+        .int_src    = INT_SRC_PORT_EIRQ15,                  \
+    }
+#endif /* EXTINT15_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI1,                                \
+        .bus_name = "spi1",                                 \
+        .clock    = FCG1_PERIPH_SPI1,                       \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_TX_DMA_INSTANCE,             \
+        .channel        = SPI1_TX_DMA_CHANNEL,              \
+        .clock          = SPI1_TX_DMA_CLOCK,                \
+        .trigger_select = SPI1_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPTI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_RX_DMA_INSTANCE,             \
+        .channel        = SPI1_RX_DMA_CHANNEL,              \
+        .clock          = SPI1_RX_DMA_CLOCK,                \
+        .trigger_select = SPI1_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPRI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI2,                                \
+        .bus_name = "spi2",                                 \
+        .clock    = FCG1_PERIPH_SPI2,                       \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_TX_DMA_INSTANCE,             \
+        .channel        = SPI2_TX_DMA_CHANNEL,              \
+        .clock          = SPI2_TX_DMA_CLOCK,                \
+        .trigger_select = SPI2_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPTI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_RX_DMA_INSTANCE,             \
+        .channel        = SPI2_RX_DMA_CHANNEL,              \
+        .clock          = SPI2_RX_DMA_CLOCK,                \
+        .trigger_select = SPI2_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPRI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI3,                                \
+        .bus_name = "spi3",                                 \
+        .clock    = FCG1_PERIPH_SPI3,                       \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_TX_DMA_INSTANCE,             \
+        .channel        = SPI3_TX_DMA_CHANNEL,              \
+        .clock          = SPI3_TX_DMA_CLOCK,                \
+        .trigger_select = SPI3_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPTI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_RX_DMA_INSTANCE,             \
+        .channel        = SPI3_RX_DMA_CHANNEL,              \
+        .clock          = SPI3_RX_DMA_CLOCK,                \
+        .trigger_select = SPI3_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPRI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI4,                                \
+        .bus_name = "spi4",                                 \
+        .clock    = FCG1_PERIPH_SPI4,                       \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_TX_DMA_INSTANCE,             \
+        .channel        = SPI4_TX_DMA_CHANNEL,              \
+        .clock          = SPI4_TX_DMA_CLOCK,                \
+        .trigger_select = SPI4_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPTI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_RX_DMA_INSTANCE,             \
+        .channel        = SPI4_RX_DMA_CHANNEL,              \
+        .clock          = SPI4_RX_DMA_CLOCK,                \
+        .trigger_select = SPI4_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPRI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI5,                                \
+        .bus_name = "spi5",                                 \
+        .clock    = FCG1_PERIPH_SPI5,                       \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_TX_DMA_INSTANCE,             \
+        .channel        = SPI5_TX_DMA_CHANNEL,              \
+        .clock          = SPI5_TX_DMA_CLOCK,                \
+        .trigger_select = SPI5_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPTI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_RX_DMA_INSTANCE,             \
+        .channel        = SPI5_RX_DMA_CHANNEL,              \
+        .clock          = SPI5_RX_DMA_CLOCK,                \
+        .trigger_select = SPI5_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPRI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI6
+#ifndef SPI6_BUS_CONFIG
+#define SPI6_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI6,                                \
+        .bus_name = "spi6",                                 \
+        .clock    = FCG1_PERIPH_SPI6,                       \
+    }
+#endif /* SPI6_BUS_CONFIG */
+#endif /* BSP_USING_SPI6 */
+
+#ifdef BSP_SPI6_TX_USING_DMA
+#ifndef SPI6_TX_DMA_CONFIG
+#define SPI6_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_TX_DMA_INSTANCE,             \
+        .channel        = SPI6_TX_DMA_CHANNEL,              \
+        .clock          = SPI6_TX_DMA_CLOCK,                \
+        .trigger_select = SPI6_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPTI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_TX_DMA_CONFIG */
+#endif /* BSP_SPI6_TX_USING_DMA */
+
+#ifdef BSP_SPI6_RX_USING_DMA
+#ifndef SPI6_RX_DMA_CONFIG
+#define SPI6_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_RX_DMA_INSTANCE,             \
+        .channel        = SPI6_RX_DMA_CHANNEL,              \
+        .clock          = SPI6_RX_DMA_CLOCK,                \
+        .trigger_select = SPI6_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPRI,                \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_RX_DMA_CONFIG */
+#endif /* BSP_SPI6_RX_USING_DMA */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                                         \
+    {                                                       \
+       .tim_handle.Instance     = TIM3,                     \
+       .tim_irqn                = TIM3_IRQn,                \
+       .name                    = "timer3",                 \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "config/dma_config.h"
+#include "config/uart_config.h"
+#include "config/spi_config.h"
+#include "config/adc_config.h"
+#include "config/tim_config.h"
+#include "config/gpio_config.h"
+#include "config/eth_config.h"
+#include "config/can_config.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h
@@ -0,0 +1,210 @@
+/**
+ *******************************************************************************
+ * @file  template/source/hc32f4xx_conf.h
+ * @brief This file contains HC32 Series Device Driver Library usage management.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-04-28       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32F4XX_CONF_H__
+#define __HC32F4XX_CONF_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @brief This is the list of modules to be used in the Device Driver Library.
+ * Select the modules you need to use to DDL_ON.
+ * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
+ * properly.
+ * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
+ * Library.
+ * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
+ */
+#define LL_ICG_ENABLE                               (DDL_ON)
+#define LL_UTILITY_ENABLE                           (DDL_ON)
+#define LL_PRINT_ENABLE                             (DDL_OFF)
+
+#define LL_ADC_ENABLE                               (DDL_ON)
+#define LL_AES_ENABLE                               (DDL_ON)
+#define LL_AOS_ENABLE                               (DDL_ON)
+#define LL_CAN_ENABLE                               (DDL_ON)
+#define LL_CLK_ENABLE                               (DDL_ON)
+#define LL_CMP_ENABLE                               (DDL_ON)
+#define LL_CRC_ENABLE                               (DDL_ON)
+#define LL_CTC_ENABLE                               (DDL_ON)
+#define LL_DAC_ENABLE                               (DDL_ON)
+#define LL_DCU_ENABLE                               (DDL_ON)
+#define LL_DMA_ENABLE                               (DDL_ON)
+#define LL_DMC_ENABLE                               (DDL_ON)
+#define LL_DVP_ENABLE                               (DDL_ON)
+#define LL_EFM_ENABLE                               (DDL_ON)
+#define LL_EMB_ENABLE                               (DDL_ON)
+#define LL_ETH_ENABLE                               (DDL_ON)
+#define LL_EVENT_PORT_ENABLE                        (DDL_OFF)
+#define LL_FCG_ENABLE                               (DDL_ON)
+#define LL_FCM_ENABLE                               (DDL_ON)
+#define LL_FMAC_ENABLE                              (DDL_ON)
+#define LL_GPIO_ENABLE                              (DDL_ON)
+#define LL_HASH_ENABLE                              (DDL_ON)
+#define LL_HRPWM_ENABLE                             (DDL_ON)
+#define LL_I2C_ENABLE                               (DDL_ON)
+#define LL_I2S_ENABLE                               (DDL_ON)
+#define LL_INTERRUPTS_ENABLE                        (DDL_ON)
+#define LL_INTERRUPTS_SHARE_ENABLE                  (DDL_ON)
+#define LL_KEYSCAN_ENABLE                           (DDL_ON)
+#define LL_MAU_ENABLE                               (DDL_ON)
+#define LL_MDIO_ENABLE                              (DDL_OFF)
+#define LL_MPU_ENABLE                               (DDL_ON)
+#define LL_NFC_ENABLE                               (DDL_ON)
+#define LL_OTS_ENABLE                               (DDL_ON)
+#define LL_PLA_ENABLE                               (DDL_OFF)
+#define LL_PWC_ENABLE                               (DDL_ON)
+#define LL_QSPI_ENABLE                              (DDL_ON)
+#define LL_RMU_ENABLE                               (DDL_ON)
+#define LL_RTC_ENABLE                               (DDL_ON)
+#define LL_SDIOC_ENABLE                             (DDL_ON)
+#define LL_SMC_ENABLE                               (DDL_ON)
+#define LL_SPI_ENABLE                               (DDL_ON)
+#define LL_SRAM_ENABLE                              (DDL_ON)
+#define LL_SWDT_ENABLE                              (DDL_ON)
+#define LL_TMR0_ENABLE                              (DDL_ON)
+#define LL_TMR2_ENABLE                              (DDL_ON)
+#define LL_TMR4_ENABLE                              (DDL_ON)
+#define LL_TMR6_ENABLE                              (DDL_ON)
+#define LL_TMRA_ENABLE                              (DDL_ON)
+#define LL_TRNG_ENABLE                              (DDL_ON)
+#define LL_USART_ENABLE                             (DDL_ON)
+#define LL_USB_ENABLE                               (DDL_OFF)
+#define LL_VREF_ENABLE                              (DDL_OFF)
+#define LL_WDT_ENABLE                               (DDL_ON)
+
+/**
+ * @brief The following is a list of currently supported BSP boards.
+ */
+#define BSP_EV_HC32F4A0_LQFP176                     (1U)
+#define BSP_EV_HC32F4A0_LQFP176_MEM                 (2U)
+#define BSP_EV_HC32F460_LQFP100_V1                  (3U)
+#define BSP_EV_HC32F460_LQFP100_V2                  (4U)
+#define BSP_EV_HC32F451_LQFP100                     (5U)
+#define BSP_EV_HC32F452_LQFP100                     (6U)
+#define BSP_EV_HC32F472_LQFP100                     (7U)
+#define BSP_SK_HC32F4A0_LQFP100                     (8U)
+
+/**
+ * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
+ * in use.
+ * The value should be set to one of the list of currently supported BSP boards.
+ * @note  If there is no supported BSP board or the BSP function is not used,
+ * the value needs to be set to 0U.
+ */
+#define BSP_EV_HC32F4XX                             (BSP_EV_HC32F4A0_LQFP176)
+
+/**
+ * @brief This is the list of BSP components to be used.
+ * Select the components you need to use to DDL_ON.
+ */
+#define BSP_24CXX_ENABLE                            (DDL_OFF)
+#define BSP_CY62167EV30LL_ENABLE                    (DDL_OFF)
+#define BSP_IS42S16400J7TLI_ENABLE                  (DDL_OFF)
+#define BSP_IS62WV51216_ENABLE                      (DDL_OFF)
+#define BSP_MT29F2G08AB_ENABLE                      (DDL_OFF)
+#define BSP_NT35510_ENABLE                          (DDL_OFF)
+#define BSP_OV5640_ENABLE                           (DDL_OFF)
+#define BSP_S29GL064N90TFI03_ENABLE                 (DDL_OFF)
+#define BSP_TCA9539_ENABLE                          (DDL_OFF)
+#define BSP_W25QXX_ENABLE                           (DDL_OFF)
+#define BSP_WM8731_ENABLE                           (DDL_OFF)
+
+/**
+ * @brief Ethernet and PHY Configuration.
+ */
+/* MAC ADDRESS */
+#define ETH_MAC_ADDR0                               (0x02U)
+#define ETH_MAC_ADDR1                               (0x00U)
+#define ETH_MAC_ADDR2                               (0x00U)
+#define ETH_MAC_ADDR3                               (0x00U)
+#define ETH_MAC_ADDR4                               (0x00U)
+#define ETH_MAC_ADDR5                               (0x00U)
+
+/* PHY(RTL8201F) Address*/
+#define ETH_PHY_ADDR                                (0x00U)
+
+/* PHY Configuration delay(ms) */
+#define ETH_PHY_RST_DELAY                           (0x0080UL)
+#define ETH_PHY_CONFIG_DELAY                        (0x0040UL)
+#define ETH_PHY_RD_TIMEOUT                          (0x0005UL)
+#define ETH_PHY_WR_TIMEOUT                          (0x0005UL)
+
+/* Common PHY Registers */
+#define PHY_BCR                                     (0x00U)     /*!< Basic Control Register               */
+#define PHY_BSR                                     (0x01U)     /*!< Basic Status Register                */
+
+#define PHY_SOFT_RESET                              (0x8000U)   /*!< PHY Soft Reset                       */
+#define PHY_LOOPBACK                                (0x4000U)   /*!< Select loop-back mode                */
+#define PHY_FULLDUPLEX_100M                         (0x2100U)   /*!< SET the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M                         (0x2000U)   /*!< SET the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M                          (0x0100U)   /*!< SET the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M                          (0x0000U)   /*!< SET the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION                         (0x1000U)   /*!< Enable auto-negotiation function     */
+#define PHY_POWERDOWN                               (0x0800U)   /*!< Select the power down mode           */
+#define PHY_ISOLATE                                 (0x0400U)   /*!< Isolate PHY from MII                 */
+#define PHY_RESTART_AUTONEGOTIATION                 (0x0200U)   /*!< Restart auto-negotiation function    */
+
+#define PHY_100BASE_TX_FD                           (0x4000U)   /*!< 100Base-TX full duplex support       */
+#define PHY_100BASE_TX_HD                           (0x2000U)   /*!< 100Base-TX half duplex support       */
+#define PHY_10BASE_T_FD                             (0x1000U)   /*!< 10Base-T full duplex support         */
+#define PHY_10BASE_T_HD                             (0x0800U)   /*!< 10Base-T half duplex support         */
+#define PHY_AUTONEGO_COMPLETE                       (0x0020U)   /*!< Auto-Negotiation process completed   */
+#define PHY_LINK_STATUS                             (0x0004U)   /*!< Valid link established               */
+#define PHY_JABBER_DETECTION                        (0x0002U)   /*!< Jabber condition detected            */
+
+/**
+ * @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0).
+ * @note  Set value to non-zero if re-define main function.
+ */
+#define RE_DEFINE_MAIN                              (0)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32F4XX_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf
@@ -0,0 +1,51 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x001FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x030017FF;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x2005FFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__   = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
+                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
+define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
+                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld
@@ -0,0 +1,267 @@
+/******************************************************************************
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ */
+/*****************************************************************************/
+/*  File        HC32F4A0xI.ld                                                */
+/*  Abstract    Linker script for HC32F4A0 Device with                       */
+/*              2MByte FLASH, 516KByte RAM                                   */
+/*  Version     V1.0                                                         */
+/*  Date        2022-04-28                                                   */
+/*****************************************************************************/
+
+/* Custom defines, according to section 7.7 of the user manual.
+   Take OTP sector 16 for example. */
+__OTP_DATA_START = 0x03000000;
+__OTP_DATA_SIZE  = 2048;
+__OTP_LOCK_START = 0x03001840;
+__OTP_LOCK_SIZE  = 4;
+
+/* Use contiguous memory regions for simple. */
+MEMORY
+{
+    FLASH       (rx): ORIGIN = 0x00000000, LENGTH = 2M
+    OTP_DATA    (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
+    OTP_LOCK    (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
+    RAM        (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
+    RAMB       (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        . = ALIGN(4);
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+    } >FLASH
+
+    .icg_sec 0x00000400 :
+    {
+        KEEP(*(.icg_sec))
+    } >FLASH
+
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } >FLASH
+
+    .rodata :
+    {
+        . = ALIGN(4);
+        *(.rodata)
+        *(.rodata*)
+        . = ALIGN(4);
+    } >FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } >FLASH
+    __exidx_end = .;
+
+    .preinit_array :
+    {
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .init_array :
+    {
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .fini_array :
+    {
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    __etext = ALIGN(4);
+
+    .otp_data_sec :
+    {
+        KEEP(*(.otp_data_sec))
+    } >OTP_DATA
+
+    .otp_lock_sec :
+    {
+        KEEP(*(.otp_lock_sec))
+    } >OTP_LOCK
+
+    .data : AT (__etext)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(vtable)
+        *(.data)
+        *(.data*)
+        *(.gnu.linkonce.d*)
+        . = ALIGN(4);
+        *(.ramfunc)
+        *(.ramfunc*)
+        . = ALIGN(4);
+        __data_end__ = .;
+    } >RAM
+
+    __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
+    .ramb_data : AT (__etext_ramb)
+    {
+        . = ALIGN(4);
+        __data_start_ramb__ = .;
+        *(.ramb_data)
+        *(.ramb_data*)
+        . = ALIGN(4);
+        __data_end_ramb__ = .;
+    } >RAMB
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = _sbss;
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        __bss_end__ = _ebss;
+    } >RAM
+    __bss_end = .;
+
+    .ramb_bss :
+    {
+        . = ALIGN(4);
+        __bss_start_ramb__ = .;
+        *(.ramb_bss)
+        *(.ramb_bss*)
+        . = ALIGN(4);
+        __bss_end_ramb__ = .;
+    } >RAMB
+
+    .heap_stack (COPY) :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        *(.heap*)
+        . = ALIGN(8);
+        __HeapLimit = .;
+
+        __StackLimit = .;
+        *(.stack*)
+        . = ALIGN(8);
+        __StackTop = .;
+    } >RAM
+
+    /DISCARD/ :
+    {
+        libc.a (*)
+        libm.a (*)
+        libgcc.a (*)
+    }
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+
+    PROVIDE(_stack = __StackTop);
+    PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
+    PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
+
+    __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
+    ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.sct
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00000000 0x00200000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x00200000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+        .ANY (+XO)
+    }
+    RW_IRAM1 0x1FFE0000 0x00080000  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+}
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <rtthread.h>
+#include "drv_spi.h"
+
+#if defined(BSP_USING_SPI_FLASH)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+static int rt_hw_spi_flash_init(void)
+{
+    rt_hw_spi_device_attach("spi1", "spi10", GPIO_PORT_C, GPIO_PIN_07);
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
+
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+#ifdef BSP_USING_TCA9539
+
+#include "tca9539.h"
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* Define for TCA9539 */
+#define BSP_TCA9539_I2C_BUS_NAME        "i2c1"
+#define BSP_TCA9539_DEV_ADDR            (0x74U)
+
+#define TCA9539_RST_PIN                 (45)    /* PC13 */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @brief  BSP TCA9539 write data.
+ * @param  [in] bus:                    Pointer to the i2c bus device.
+ * @param  [in] reg:                    Register to be written.
+ * @param  [in] data:                   The pointer to the buffer contains the data to be written.
+ * @param  [in] len:                    Buffer size in byte.
+ * @retval rt_err_t:
+ *           - RT_EOK
+ *           - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+    struct rt_i2c_msg msgs;
+    rt_uint8_t buf[6];
+
+    buf[0] = reg;
+    if (len > 0)
+    {
+        if (len < 6)
+        {
+            rt_memcpy(buf + 1, data, len);
+        }
+        else
+        {
+            return -RT_ERROR;
+        }
+    }
+    msgs.addr   = BSP_TCA9539_DEV_ADDR;
+    msgs.flags  = RT_I2C_WR;
+    msgs.buf    = buf;
+    msgs.len    = len + 1;
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+}
+
+/**
+ * @brief  BSP TCA9539 Read data.
+ * @param  [in] bus:                    Pointer to the i2c bus device.
+ * @param  [in] reg:                    Register to be read.
+ * @param  [out] data:                  The pointer to the buffer contains the data to be read.
+ * @param  [in] len:                    Buffer size in byte.
+ * @retval rt_err_t:
+ *           - RT_EOK
+ *           - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+    struct rt_i2c_msg msgs;
+
+    if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
+    {
+        return -RT_ERROR;
+    }
+    msgs.addr   = BSP_TCA9539_DEV_ADDR;
+    msgs.flags  = RT_I2C_RD;
+    msgs.buf    = data;
+    msgs.len    = len;
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+}
+
+
+/**
+ * @brief  Reset TCA9539.
+ * @param  [in] None
+ * @retval None
+ */
+static void TCA9539_Reset(void)
+{
+    rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
+    /* Reset the device */
+    rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
+    rt_thread_mdelay(3U);
+    rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
+}
+
+/**
+ * @brief  Write TCA9539 pin output value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+    if (0U == u8PinState)
+    {
+        u8TempData[1] &= (uint8_t)(~u8Pin);
+    }
+    else
+    {
+        u8TempData[1] |= u8Pin;
+    }
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Read TCA9539 pin input value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+    if (0U != (u8TempData[1] & u8Pin))
+    {
+        *pu8PinState = TCA9539_PIN_SET;
+    }
+    else
+    {
+        *pu8PinState = TCA9539_PIN_RESET;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Toggle TCA9539 pin output value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+    u8TempData[1] ^= u8Pin;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Configuration TCA9539 pin.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8Dir                   Pin output direction.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Direction_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+    if (TCA9539_DIR_OUT == u8Dir)
+    {
+        u8TempData[1] &= (uint8_t)(~u8Pin);
+    }
+    else
+    {
+        u8TempData[1] |= u8Pin;
+    }
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Initialize TCA9539.
+ * @param  [in] None
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+int TCA9539_Init(void)
+{
+    char name[RT_NAME_MAX];
+    uint8_t u8TempData[2];
+
+    TCA9539_Reset();
+    rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
+    if (i2c_bus == RT_NULL)
+    {
+        rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
+        return RT_ERROR;
+    }
+    /* All Pins are input as default */
+    u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
+    u8TempData[1] = 0xFFU;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+    u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_PREV_EXPORT(TCA9539_Init);
+
+#endif /* BSP_USING_TCA9539 */
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __TCA9539_H__
+#define __TCA9539_H__
+
+#include <rtdevice.h>
+
+/**
+ * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
+ * @{
+ */
+#define TCA9539_REG_INPUT_PORT0         (0x00U)
+#define TCA9539_REG_INPUT_PORT1         (0x01U)
+#define TCA9539_REG_OUTPUT_PORT0        (0x02U)
+#define TCA9539_REG_OUTPUT_PORT1        (0x03U)
+#define TCA9539_REG_INVERT_PORT0        (0x04U)
+#define TCA9539_REG_INVERT_PORT1        (0x05U)
+#define TCA9539_REG_CONFIG_PORT0        (0x06U)
+#define TCA9539_REG_CONFIG_PORT1        (0x07U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Port_Definition TCA9539 Port Definition
+ * @{
+ */
+#define TCA9539_IO_PORT0                (0x00U)
+#define TCA9539_IO_PORT1                (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
+ * @{
+ */
+#define TCA9539_IO_PIN0                 (0x01U)
+#define TCA9539_IO_PIN1                 (0x02U)
+#define TCA9539_IO_PIN2                 (0x04U)
+#define TCA9539_IO_PIN3                 (0x08U)
+#define TCA9539_IO_PIN4                 (0x10U)
+#define TCA9539_IO_PIN5                 (0x20U)
+#define TCA9539_IO_PIN6                 (0x40U)
+#define TCA9539_IO_PIN7                 (0x80U)
+#define TCA9539_IO_PIN_ALL              (0xFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
+ * @{
+ */
+#define TCA9539_DIR_OUT                 (0x00U)
+#define TCA9539_DIR_IN                  (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
+ * @{
+ */
+#define TCA9539_PIN_RESET               (0x00U)
+#define TCA9539_PIN_SET                 (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition
+ * @{
+ */
+#define EIO_USBFS_OC                    (TCA9539_IO_PIN0)   /* USBFS over-current, input */
+#define EIO_USBHS_OC                    (TCA9539_IO_PIN1)   /* USBHS over-current, input */
+#define EIO_SDIC1_CD                    (TCA9539_IO_PIN2)   /* SDIC1 card detect, input */
+#define EIO_SCI_CD                      (TCA9539_IO_PIN3)   /* Smart card detect, input */
+#define EIO_TOUCH_INT                   (TCA9539_IO_PIN4)   /* Touch screen interrupt, input */
+#define EIO_LIN_SLEEP                   (TCA9539_IO_PIN5)   /* LIN PHY sleep, output */
+#define EIO_RTCS_CTRST                  (TCA9539_IO_PIN6)   /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
+#define EIO_LCD_RST                     (TCA9539_IO_PIN7)   /* LCD panel reset, output */
+
+#define EIO_CAM_RST                     (TCA9539_IO_PIN0)   /* Camera module reset, output */
+#define EIO_CAM_STB                     (TCA9539_IO_PIN1)   /* Camera module standby, output */
+#define EIO_USB3300_RST                 (TCA9539_IO_PIN2)   /* USBHS PHY USB3300 reset, output */
+#define EIO_ETH_RST                     (TCA9539_IO_PIN3)   /* ETH PHY reset, output */
+#define EIO_CAN_STB                     (TCA9539_IO_PIN4)   /* CAN PHY standby, output */
+#define EIO_LED_RED                     (TCA9539_IO_PIN5)   /* Red LED, output */
+#define EIO_LED_YELLOW                  (TCA9539_IO_PIN6)   /* Yellow LED, output */
+#define EIO_LED_BLUE                    (TCA9539_IO_PIN7)   /* Blue LED, output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
+ * @{
+ */
+#define LED_PORT                        (TCA9539_IO_PORT1)
+#define LED_RED_PORT                    (TCA9539_IO_PORT1)
+#define LED_RED_PIN                     (EIO_LED_RED)
+#define LED_YELLOW_PORT                 (TCA9539_IO_PORT1)
+#define LED_YELLOW_PIN                  (EIO_LED_YELLOW)
+#define LED_BLUE_PORT                   (TCA9539_IO_PORT1)
+#define LED_BLUE_PIN                    (EIO_LED_BLUE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup  BSP CAN PHY STB port/pin definition
+ * @{
+ */
+#define CAN_STB_PORT                    (TCA9539_IO_PORT1)
+#define CAN_STB_PIN                     (EIO_CAN_STB)
+/**
+ * @}
+ */
+
+int TCA9539_Init(void);
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
+
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/figures/board.jpg
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/figures/board.jpg
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewd
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewd
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.eww
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvoptx
@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h
@@ -0,0 +1,202 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40100
+#define ARCH_ARM
+#define RT_USING_CPU_FFS
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M4
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* POSIX extension functions */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+#define SOC_FAMILY_HC32
+#define SOC_SERIES_HC32F4
+
+/* Hardware Drivers Config */
+
+#define SOC_HC32F4A0SI
+
+/* Onboard Peripheral Drivers */
+
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Board extended module Drivers */
+
+
+#endif
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:/Users/XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iar'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/template.ewp
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.ewp
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/template.eww
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvoptx
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvoptx
@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
--- a/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx
+++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx
@@ -0,0 +1,390 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>HC32F4A0SITB</Device>
+          <Vendor>HDSC</Vendor>
+          <PackID>HDSC.HC32F4A0.1.0.6</PackID>
+          <PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
+          <Cpu>IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000)  IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:HC32F4A0SITB$Device\Include\HC32F4A0SITB.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>../libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR</SFDFile>
+          <bCustSvd>1</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>1</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1ffe0000</StartAddress>
+                <Size>0x80000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x3000000</StartAddress>
+                <Size>0x1800</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1ffe0000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x200f0000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF8000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>
--- a/bsp/hc32/libraries/.ignore_format.yml
+++ b/bsp/hc32/libraries/.ignore_format.yml
@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- hc32f4a0_ddl
--- a/bsp/hc32/libraries/Kconfig
+++ b/bsp/hc32/libraries/Kconfig
@@ -0,0 +1,22 @@
+config SOC_FAMILY_HC32
+    bool
+
+config SOC_SERIES_HC32F1
+    bool
+    select ARCH_ARM_CORTEX_M0
+    select SOC_FAMILY_HC32
+
+config SOC_SERIES_HC32F4
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_HC32
+
+config SOC_SERIES_HC32M1
+    bool
+    select ARCH_ARM_CORTEX_M0
+    select SOC_FAMILY_HC32
+
+config SOC_SERIES_HC32M4
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_HC32
--- a/bsp/hc32/libraries/hc32_drivers/Kconfig
+++ b/bsp/hc32/libraries/hc32_drivers/Kconfig
@@ -0,0 +1,26 @@
+if BSP_USING_USBD
+    config BSP_USBD_TYPE_FS
+        bool
+        # "USB Full Speed (FS) Core"
+    config BSP_USBD_TYPE_HS
+        bool
+        # "USB High Speed (HS) Core"
+
+    config BSP_USBD_SPEED_HS
+        bool 
+        # "USB High Speed (HS) Mode"
+    config BSP_USBD_SPEED_HSINFS
+        bool 
+        # "USB High Speed (HS) Core in FS mode"
+
+    config BSP_USBD_PHY_EMBEDDED
+        bool 
+        # "Using Embedded phy interface"
+    config BSP_USBD_PHY_UTMI
+        bool 
+        # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+    config BSP_USBD_PHY_ULPI
+        bool 
+        # "ULPI: UTMI+ Low Pin Interface"
+endif
+
--- a/bsp/hc32/libraries/hc32_drivers/SConscript
+++ b/bsp/hc32/libraries/hc32_drivers/SConscript
@@ -0,0 +1,74 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+drv_irq.c
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_PULSE_ENCODER']):
+    src += ['drv_pulse_encoder.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drv_qspi.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
+    src += ['drv_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+    src += ['drv_dac.c']
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['RT_USING_PM']):
+    src += ['drv_pm.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['RT_USING_ON_CHIP_FLASH']):
+    src += ['drv_flash.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['RT_USING_SDIO']):
+    src += ['drv_sdio.c']
+
+if GetDepend(['RT_USING_USBD']):
+    src += ['drv_usbd.c']
+
+if GetDepend(['RT_USING_USBH']):
+    src += ['drv_usbh.c']
+
+
+path = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
--- a/Show More
+++ b/Show More