mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-02 14:23:19 +08:00
Jamie
@@ -0,0 +1,22 @@
|
||||
|
||||
# HC32 BSP 说明
|
||||
|
||||
HC32 系列 BSP 目前支持情况如下表所示：
|
||||
|
||||
| **BSP 文件夹名称** | **开发板名称** |
|
||||
|:------------------------- |:------------------------- |
|
||||
| **F1 系列** | |
|
||||
| **F4 系列** | |
|
||||
| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
|
||||
| **M1 系列** | |
|
||||
| **M4 系列** | |
|
||||
|
||||
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
|
||||
|
||||
| **BSP 使用教程** | **简介** |
|
||||
|:-------------------- |:------------------------------------------------- |
|
||||
| [外设驱动使用教程](docs/HC32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
|
||||
| [外设驱动介绍与应用](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
|
||||
| **BSP 制作与提交** | **简介** |
|
||||
| [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 |
|
||||
|
||||
@@ -0,0 +1,2 @@
|
||||
# HC32 系列 BSP 制作教程
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
# HC32系列BSP外设驱动使用教程
|
||||
@@ -0,0 +1,2 @@
|
||||
# HC32系列驱动介绍
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,42 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
@@ -0,0 +1,21 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
@@ -0,0 +1,116 @@
|
||||
# XHSC EV_F4A0_LQ176 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为小华半导体为 EV_F4A0_LQ176 开发板提供的 BSP (板级支持包) 说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
|
||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
EV_F4A0_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A0SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A0SITB 的芯片性能。
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
EV_F4A0_LQ176 开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：HC32F4A0SITB，主频240MHz，2048KB FLASH，512KB RAM
|
||||
- 外部RAM：IS62WV51216(SRAM, 1MB) IS42S16400J(SDRAM, 8MB)
|
||||
- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 64MB)
|
||||
- 常用外设
|
||||
- LED：3 个， user LED(LED0,LED1,LED2)。
|
||||
- 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。
|
||||
- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口
|
||||
- 调试接口：板载DAP调试器、标准JTAG/SWD。
|
||||
|
||||
开发板更多详细信息请参考小华半导体半导体[EV_F4A0_LQ176](http://www.xhsc.com.cn)
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| USB 转串口 | 支持 | 使用 UART1 |
|
||||
| SPI Flash | 支持 | 使用 SPI1 |
|
||||
| LED | 支持 | LED |
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
|
||||
| UART | 支持 | UART1~10 |
|
||||
| SPI | 支持 | SPI1~6 |
|
||||
| I2C | 支持 | 软件 I2C |
|
||||
| RTC | 支持 | 支持外部晶振和内部低速时钟 |
|
||||
| PWM | 支持 | |
|
||||
| HWTIMER | 支持 | |
|
||||
| LED | 支持 | LED11 |
|
||||
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用Type-A to MircoUSB线连接开发板和PC供电。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。
|
||||
|
||||
USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.1.0 build Apr 24 2022 13:32:39
|
||||
2006 - 2022 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>
|
||||
@@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,60 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
hc32_library = 'hc32f4a0_ddl'
|
||||
rtconfig.BSP_LIBRARY_TYPE = hc32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,11 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
|
||||
/* defined the LED_GREEN pin: PC9 */
|
||||
#define LED_GREEN_PIN GET_PIN(C, 9)
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED_GREEN_PIN pin mode to output */
|
||||
rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_TCA9539']):
|
||||
src += Glob('ports/tca9539.c')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/spi_flash.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
|
||||
|
||||
CPPDEFINES = ['HC32F4A0']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,160 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/* unlock/lock peripheral */
|
||||
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
stc_clock_xtal_init_t stcXtalInit;
|
||||
stc_clock_pll_init_t stcPLLHInit;
|
||||
|
||||
/* PCLK0, HCLK Max 240MHz */
|
||||
/* PCLK1, PCLK4 Max 120MHz */
|
||||
/* PCLK2, PCLK3 Max 60MHz */
|
||||
/* EX BUS Max 120MHz */
|
||||
CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
|
||||
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
|
||||
CLK_HCLK_DIV1));
|
||||
|
||||
(void)CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||||
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||||
stcXtalInit.u8State = CLK_XTAL_ON;
|
||||
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||||
(void)CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*120 = 960MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||||
(void)CLK_PLLInit(&stcPLLHInit);
|
||||
|
||||
/* Highspeed SRAM set to 0 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
|
||||
|
||||
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
|
||||
|
||||
/* 0-wait @ 40MHz */
|
||||
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
|
||||
|
||||
/* 4 cycles for 200 ~ 250MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
|
||||
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SysTick_Configuration
|
||||
* Description : Configures the SysTick for OS tick.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SysTick_Configuration(void)
|
||||
{
|
||||
stc_clock_freq_t stcClkFreq;
|
||||
rt_uint32_t cnts;
|
||||
|
||||
CLK_GetClockFreq(&stcClkFreq);
|
||||
|
||||
cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial GD32 board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* Peripheral registers write unprotected */
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
|
||||
SystemClock_Config();
|
||||
/* Configure the SysTick */
|
||||
SysTick_Configuration();
|
||||
|
||||
/* Heap initialization */
|
||||
#if defined(RT_USING_HEAP)
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
/* Board underlying hardware initialization */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
uint32_t start, now, delta, reload, us_tick;
|
||||
start = SysTick->VAL;
|
||||
reload = SysTick->LOAD;
|
||||
us_tick = SystemCoreClock / 1000000UL;
|
||||
|
||||
do
|
||||
{
|
||||
now = SysTick->VAL;
|
||||
delta = start > now ? start - now : reload + start - now;
|
||||
}
|
||||
while (delta < us_tick * us);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define HC32_SRAM_SIZE (512)
|
||||
#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __BOARD_CONFIG_H__
|
||||
#define __BOARD_CONFIG_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
|
||||
/************************ USART port **********************/
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define USART1_RX_PORT (GPIO_PORT_H)
|
||||
#define USART1_RX_PIN (GPIO_PIN_13)
|
||||
|
||||
#define USART1_TX_PORT (GPIO_PORT_H)
|
||||
#define USART1_TX_PIN (GPIO_PIN_15)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#define USART6_RX_PORT (GPIO_PORT_H)
|
||||
#define USART6_RX_PIN (GPIO_PIN_06)
|
||||
|
||||
#define USART6_TX_PORT (GPIO_PORT_E)
|
||||
#define USART6_TX_PIN (GPIO_PIN_06)
|
||||
#endif
|
||||
|
||||
/*********************** PWM port *************************/
|
||||
#if defined(BSP_USING_PWM1)
|
||||
|
||||
#if defined(BSP_USING_PWM1_CH1)
|
||||
#define PWM1_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM1_CH1_PIN (GPIO_PIN_08)
|
||||
#define PWM1_CH1_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM1_CH2)
|
||||
#define PWM1_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM1_CH2_PIN (GPIO_PIN_09)
|
||||
#define PWM1_CH2_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/****************** Pulse encoder port ********************/
|
||||
#if defined(BSP_USING_PULSE_ENCODER9)
|
||||
#define PULSE_ENCODER9_CLKA_PORT (GPIO_PORT_G)
|
||||
#define PULSE_ENCODER9_CLKA_PIN (GPIO_PIN_04)
|
||||
#define PULSE_ENCODER9_CLKA_FUNC (GPIO_FUNC_4)
|
||||
|
||||
#define PULSE_ENCODER9_CLKB_PORT (GPIO_PORT_G)
|
||||
#define PULSE_ENCODER9_CLKB_PIN (GPIO_PIN_05)
|
||||
#define PULSE_ENCODER9_CLKB_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
|
||||
/*********** ADC configure *********/
|
||||
#if defined(BSP_USING_ADC1)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC1_CH_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC2)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC2_CH_PIN (GPIO_PIN_01)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC3)
|
||||
#define ADC3_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC3_CH_PIN (GPIO_PIN_02)
|
||||
#endif
|
||||
|
||||
/*********** CAN configure *********/
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define CAN1_TX_PORT (GPIO_PORT_D)
|
||||
#define CAN1_TX_PIN (GPIO_PIN_05)
|
||||
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60)
|
||||
|
||||
#define CAN1_RX_PORT (GPIO_PORT_D)
|
||||
#define CAN1_RX_PIN (GPIO_PIN_04)
|
||||
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61)
|
||||
|
||||
#define CAN1_INT_PRIO (DDL_IRQ_PRIO_03)
|
||||
#define CAN1_INT_SRC (INT_SRC_CAN1_HOST)
|
||||
#define CAN1_INT_IRQn (INT004_IRQn)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_CAN2)
|
||||
#define CAN2_TX_PORT (GPIO_PORT_D)
|
||||
#define CAN2_TX_PIN (GPIO_PIN_07)
|
||||
#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62)
|
||||
|
||||
#define CAN2_RX_PORT (GPIO_PORT_D)
|
||||
#define CAN2_RX_PIN (GPIO_PIN_06)
|
||||
#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63)
|
||||
|
||||
#define CAN2_INT_PRIO (DDL_IRQ_PRIO_03)
|
||||
#define CAN2_INT_SRC (INT_SRC_CAN2_HOST)
|
||||
#define CAN2_INT_IRQn (INT005_IRQn)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_CONFIG
|
||||
#define ADC1_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_CONFIG */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_CONFIG
|
||||
#define ADC2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_CONFIG */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_CONFIG
|
||||
#define ADC3_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC3_CONFIG */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
#define __CAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#ifndef CAN1_CONFIG
|
||||
#define CAN1_CONFIG \
|
||||
{ \
|
||||
.name = "can1", \
|
||||
}
|
||||
#endif /* CAN1_CONFIG */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#ifndef CAN2_CONFIG
|
||||
#define CAN2_CONFIG \
|
||||
{ \
|
||||
.name = "can2", \
|
||||
}
|
||||
#endif /* CAN2_CONFIG */
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ETH_CONFIG_H__
|
||||
#define __ETH_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_ETH)
|
||||
|
||||
#ifndef ETH_IRQ_CONFIG
|
||||
#define ETH_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT104_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_ETH_GLB_INT, \
|
||||
}
|
||||
#endif /* ETH_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ETH_CONFIG_H__ */
|
||||
@@ -0,0 +1,174 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_CONFIG_H__
|
||||
#define __GPIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#ifndef EXTINT0_IRQ_CONFIG
|
||||
#define EXTINT0_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT022_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ0, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT1_IRQ_CONFIG
|
||||
#define EXTINT1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT023_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ1, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT2_IRQ_CONFIG
|
||||
#define EXTINT2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT024_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ2, \
|
||||
}
|
||||
#endif /* EXTINT2_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT3_IRQ_CONFIG
|
||||
#define EXTINT3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT025_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ3, \
|
||||
}
|
||||
#endif /* EXTINT3_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT4_IRQ_CONFIG
|
||||
#define EXTINT4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT026_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ4, \
|
||||
}
|
||||
#endif /* EXTINT4_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT5_IRQ_CONFIG
|
||||
#define EXTINT5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT027_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ5, \
|
||||
}
|
||||
#endif /* EXTINT5_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT6_IRQ_CONFIG
|
||||
#define EXTINT6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT028_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ6, \
|
||||
}
|
||||
#endif /* EXTINT6_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT7_IRQ_CONFIG
|
||||
#define EXTINT7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT029_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ7, \
|
||||
}
|
||||
#endif /* EXTINT7_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT8_IRQ_CONFIG
|
||||
#define EXTINT8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT030_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ8, \
|
||||
}
|
||||
#endif /* EXTINT8_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT9_IRQ_CONFIG
|
||||
#define EXTINT9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT031_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ9, \
|
||||
}
|
||||
#endif /* EXTINT9_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT10_IRQ_CONFIG
|
||||
#define EXTINT10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT032_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ10, \
|
||||
}
|
||||
#endif /* EXTINT10_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT11_IRQ_CONFIG
|
||||
#define EXTINT11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT033_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ11, \
|
||||
}
|
||||
#endif /* EXTINT11_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT12_IRQ_CONFIG
|
||||
#define EXTINT12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT034_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ12, \
|
||||
}
|
||||
#endif /* EXTINT12_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT13_IRQ_CONFIG
|
||||
#define EXTINT13_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT035_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ13, \
|
||||
}
|
||||
#endif /* EXTINT13_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT14_IRQ_CONFIG
|
||||
#define EXTINT14_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT036_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ14, \
|
||||
}
|
||||
#endif /* EXTINT14_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT15_IRQ_CONFIG
|
||||
#define EXTINT15_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = INT037_IRQn, \
|
||||
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
|
||||
.int_src = INT_SRC_PORT_EIRQ15, \
|
||||
}
|
||||
#endif /* EXTINT15_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 3000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = HWTIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM3
|
||||
#ifndef TIM3_CONFIG
|
||||
#define TIM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.tim_irqn = TIM3_IRQn, \
|
||||
.name = "timer3", \
|
||||
}
|
||||
#endif /* TIM3_CONFIG */
|
||||
#endif /* BSP_USING_TIM3 */
|
||||
|
||||
#ifdef BSP_USING_TIM11
|
||||
#ifndef TIM11_CONFIG
|
||||
#define TIM11_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM11, \
|
||||
.tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \
|
||||
.name = "timer11", \
|
||||
}
|
||||
#endif /* TIM11_CONFIG */
|
||||
#endif /* BSP_USING_TIM11 */
|
||||
|
||||
#ifdef BSP_USING_TIM13
|
||||
#ifndef TIM13_CONFIG
|
||||
#define TIM13_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM13, \
|
||||
.tim_irqn = TIM8_UP_TIM13_IRQn, \
|
||||
.name = "timer13", \
|
||||
}
|
||||
#endif /* TIM13_CONFIG */
|
||||
#endif /* BSP_USING_TIM13 */
|
||||
|
||||
#ifdef BSP_USING_TIM14
|
||||
#ifndef TIM14_CONFIG
|
||||
#define TIM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \
|
||||
.name = "timer14", \
|
||||
}
|
||||
#endif /* TIM14_CONFIG */
|
||||
#endif /* BSP_USING_TIM14 */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/gpio_config.h"
|
||||
#include "config/eth_config.h"
|
||||
#include "config/can_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,51 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,15 @@
|
||||
; ****************************************************************
|
||||
; Scatter-Loading Description File
|
||||
; ****************************************************************
|
||||
LR_IROM1 0x00000000 0x00200000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFE0000 0x00080000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "drv_spi.h"
|
||||
|
||||
#if defined(BSP_USING_SPI_FLASH)
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
static int rt_hw_spi_flash_init(void)
|
||||
{
|
||||
rt_hw_spi_device_attach("spi1", "spi10", GPIO_PORT_C, GPIO_PIN_07);
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TCA9539_H__
|
||||
#define __TCA9539_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_REG_INPUT_PORT0 (0x00U)
|
||||
#define TCA9539_REG_INPUT_PORT1 (0x01U)
|
||||
#define TCA9539_REG_OUTPUT_PORT0 (0x02U)
|
||||
#define TCA9539_REG_OUTPUT_PORT1 (0x03U)
|
||||
#define TCA9539_REG_INVERT_PORT0 (0x04U)
|
||||
#define TCA9539_REG_INVERT_PORT1 (0x05U)
|
||||
#define TCA9539_REG_CONFIG_PORT0 (0x06U)
|
||||
#define TCA9539_REG_CONFIG_PORT1 (0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Port_Definition TCA9539 Port Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PORT0 (0x00U)
|
||||
#define TCA9539_IO_PORT1 (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PIN0 (0x01U)
|
||||
#define TCA9539_IO_PIN1 (0x02U)
|
||||
#define TCA9539_IO_PIN2 (0x04U)
|
||||
#define TCA9539_IO_PIN3 (0x08U)
|
||||
#define TCA9539_IO_PIN4 (0x10U)
|
||||
#define TCA9539_IO_PIN5 (0x20U)
|
||||
#define TCA9539_IO_PIN6 (0x40U)
|
||||
#define TCA9539_IO_PIN7 (0x80U)
|
||||
#define TCA9539_IO_PIN_ALL (0xFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_DIR_OUT (0x00U)
|
||||
#define TCA9539_DIR_IN (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_PIN_RESET (0x00U)
|
||||
#define TCA9539_PIN_SET (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition
|
||||
* @{
|
||||
*/
|
||||
#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */
|
||||
#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */
|
||||
#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */
|
||||
#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */
|
||||
#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */
|
||||
#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */
|
||||
#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
|
||||
#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */
|
||||
|
||||
#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */
|
||||
#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */
|
||||
#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */
|
||||
#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */
|
||||
#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */
|
||||
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
|
||||
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
|
||||
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define LED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PIN (EIO_LED_RED)
|
||||
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
|
||||
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_BLUE_PIN (EIO_LED_BLUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP CAN PHY STB port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN_STB_PIN (EIO_CAN_STB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
int TCA9539_Init(void);
|
||||
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
|
||||
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
|
||||
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
|
||||
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
|
||||
|
||||
#endif
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 481 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,189 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,189 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,6 @@
|
||||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
dir_path:
|
||||
- hc32f4a0_ddl
|
||||
@@ -0,0 +1,22 @@
|
||||
config SOC_FAMILY_HC32
|
||||
bool
|
||||
|
||||
config SOC_SERIES_HC32F1
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M0
|
||||
select SOC_FAMILY_HC32
|
||||
|
||||
config SOC_SERIES_HC32F4
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M4
|
||||
select SOC_FAMILY_HC32
|
||||
|
||||
config SOC_SERIES_HC32M1
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M0
|
||||
select SOC_FAMILY_HC32
|
||||
|
||||
config SOC_SERIES_HC32M4
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M4
|
||||
select SOC_FAMILY_HC32
|
||||
@@ -0,0 +1,26 @@
|
||||
if BSP_USING_USBD
|
||||
config BSP_USBD_TYPE_FS
|
||||
bool
|
||||
# "USB Full Speed (FS) Core"
|
||||
config BSP_USBD_TYPE_HS
|
||||
bool
|
||||
# "USB High Speed (HS) Core"
|
||||
|
||||
config BSP_USBD_SPEED_HS
|
||||
bool
|
||||
# "USB High Speed (HS) Mode"
|
||||
config BSP_USBD_SPEED_HSINFS
|
||||
bool
|
||||
# "USB High Speed (HS) Core in FS mode"
|
||||
|
||||
config BSP_USBD_PHY_EMBEDDED
|
||||
bool
|
||||
# "Using Embedded phy interface"
|
||||
config BSP_USBD_PHY_UTMI
|
||||
bool
|
||||
# "UTMI: USB 2.0 Transceiver Macrocell Interace"
|
||||
config BSP_USBD_PHY_ULPI
|
||||
bool
|
||||
# "ULPI: UTMI+ Low Pin Interface"
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
drv_irq.c
|
||||
""")
|
||||
|
||||
if GetDepend(['RT_USING_PIN']):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
if GetDepend(['RT_USING_SERIAL']):
|
||||
src += ['drv_usart.c']
|
||||
|
||||
if GetDepend(['RT_USING_HWTIMER']):
|
||||
src += ['drv_hwtimer.c']
|
||||
|
||||
if GetDepend(['RT_USING_PWM']):
|
||||
src += ['drv_pwm.c']
|
||||
|
||||
if GetDepend(['RT_USING_PULSE_ENCODER']):
|
||||
src += ['drv_pulse_encoder.c']
|
||||
|
||||
if GetDepend(['RT_USING_SPI']):
|
||||
src += ['drv_spi.c']
|
||||
|
||||
if GetDepend(['RT_USING_QSPI']):
|
||||
src += ['drv_qspi.c']
|
||||
|
||||
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
|
||||
src += ['drv_soft_i2c.c']
|
||||
|
||||
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
|
||||
src += ['drv_eth.c']
|
||||
|
||||
if GetDepend(['RT_USING_ADC']):
|
||||
src += ['drv_adc.c']
|
||||
|
||||
if GetDepend(['RT_USING_DAC']):
|
||||
src += ['drv_dac.c']
|
||||
|
||||
if GetDepend(['RT_USING_CAN']):
|
||||
src += ['drv_can.c']
|
||||
|
||||
if GetDepend(['RT_USING_PM']):
|
||||
src += ['drv_pm.c']
|
||||
|
||||
if GetDepend(['RT_USING_RTC']):
|
||||
src += ['drv_rtc.c']
|
||||
|
||||
if GetDepend(['RT_USING_ON_CHIP_FLASH']):
|
||||
src += ['drv_flash.c']
|
||||
|
||||
if GetDepend(['RT_USING_WDT']):
|
||||
src += ['drv_wdt.c']
|
||||
|
||||
if GetDepend(['RT_USING_SDIO']):
|
||||
src += ['drv_sdio.c']
|
||||
|
||||
if GetDepend(['RT_USING_USBD']):
|
||||
src += ['drv_usbd.c']
|
||||
|
||||
if GetDepend(['RT_USING_USBH']):
|
||||
src += ['drv_usbh.c']
|
||||
|
||||
|
||||
path = [cwd]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __DRV_ADC_H__
|
||||
#define __DRV_ADC_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
|
||||
#include "hc32_ll.h"
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
struct hc32_adc_init_type
|
||||
{
|
||||
char name[8];
|
||||
uint16_t resolution; /*!< Specifies the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
uint16_t data_align; /*!< Specifies ADC data alignment.
|
||||
This parameter can be a value of @ref ADC_Data_Align */
|
||||
rt_bool_t hard_trig_enable;
|
||||
|
||||
uint32_t hard_trig_src; /*a value of @ref ADC_Hard_Trigger_Sel */
|
||||
rt_bool_t internal_trig0_comtrg0_enable;
|
||||
rt_bool_t internal_trig0_comtrg1_enable;
|
||||
en_event_src_t internal_trig0_sel; /*@ref en_event_src_t in details */
|
||||
rt_bool_t internal_trig1_comtrg0_enable;
|
||||
rt_bool_t internal_trig1_comtrg1_enable;
|
||||
en_event_src_t internal_trig1_sel; /*@ref en_event_src_t in details */
|
||||
|
||||
rt_bool_t continue_conv_mode_enable;
|
||||
rt_bool_t data_reg_auto_clear;
|
||||
uint32_t eoc_poll_time_max;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_USART_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CAN_H__
|
||||
#define __DRV_CAN_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <board.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
|
||||
|
||||
/* stm32 can device */
|
||||
struct hc32_can_init_type
|
||||
{
|
||||
char *name;
|
||||
};
|
||||
|
||||
int rt_hw_can_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__DRV_CAN_H__ */
|
||||
|
||||
/************************** end of file ******************/
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_DMA_H__
|
||||
#define __DRV_DMA_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtthread.h>
|
||||
#include "drv_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct dma_config
|
||||
{
|
||||
CM_DMA_TypeDef *Instance;
|
||||
rt_uint32_t channel;
|
||||
rt_uint32_t clock;
|
||||
rt_uint32_t trigger_select;
|
||||
en_event_src_t trigger_event;
|
||||
struct hc32_irq_config irq_config;
|
||||
func_ptr_t irq_callback;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_DMA_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __DRV_ETH_H__
|
||||
#define __DRV_ETH_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* The PHY basic control register */
|
||||
#define PHY_BASIC_CONTROL_REG 0x00U
|
||||
#define PHY_RESET_MASK (1<<15)
|
||||
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
|
||||
|
||||
/* The PHY basic status register */
|
||||
#define PHY_BASIC_STATUS_REG 0x01U
|
||||
#define PHY_LINKED_STATUS_MASK (1<<2)
|
||||
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
|
||||
|
||||
/* The PHY ID one register */
|
||||
#define PHY_ID1_REG 0x02U
|
||||
|
||||
|
||||
#ifdef PHY_USING_RTL8201F
|
||||
/* Extended PHY Registers */
|
||||
#define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */
|
||||
#define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */
|
||||
#define PHY_PSR (0x1FU) /*!< Page Select Register */
|
||||
#define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */
|
||||
#define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */
|
||||
|
||||
/* The following parameters will return to default values after a software reset */
|
||||
#define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */
|
||||
|
||||
#define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */
|
||||
#define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */
|
||||
#define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */
|
||||
#define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */
|
||||
|
||||
#define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */
|
||||
#define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */
|
||||
|
||||
#define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */
|
||||
#define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */
|
||||
#define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */
|
||||
|
||||
#define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */
|
||||
#define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */
|
||||
#define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */
|
||||
#define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */
|
||||
#define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */
|
||||
#define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */
|
||||
#define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */
|
||||
#define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */
|
||||
#define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */
|
||||
#define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_ETH_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_GPIO_H__
|
||||
#define __DRV_GPIO_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include "drv_irq.h"
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#define __HC_PORT(port) GPIO_PORT_##port
|
||||
#define GET_PIN(PORT, PIN) (rt_base_t)(((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN)
|
||||
|
||||
struct hc32_pin_irq_map
|
||||
{
|
||||
rt_uint16_t pinbit;
|
||||
func_ptr_t irq_callback;
|
||||
struct hc32_irq_config irq_config;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_GPIO_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_HWTIMER_H__
|
||||
#define __DRV_HWTIMER_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "board_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIMER1
|
||||
#ifndef TIMER1_IRQ_CONFIG
|
||||
#define TIMER1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER1_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER1_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER1_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER1 */
|
||||
|
||||
#ifdef BSP_USING_TIMER2
|
||||
#ifndef TIMER2_IRQ_CONFIG
|
||||
#define TIMER2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER2_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER2_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER2_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER2 */
|
||||
|
||||
#ifdef BSP_USING_TIMER3
|
||||
#ifndef TIMER3_IRQ_CONFIG
|
||||
#define TIMER3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER3_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER3_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER3_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER3 */
|
||||
|
||||
#ifdef BSP_USING_TIMER4
|
||||
#ifndef TIMER4_IRQ_CONFIG
|
||||
#define TIMER4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER4_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER4_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER4_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER4 */
|
||||
|
||||
#ifdef BSP_USING_TIMER5
|
||||
#ifndef TIMER5_IRQ_CONFIG
|
||||
#define TIMER5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER5_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER5_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER5_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER5 */
|
||||
|
||||
#ifdef BSP_USING_TIMER6
|
||||
#ifndef TIMER6_IRQ_CONFIG
|
||||
#define TIMER6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER6_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER6_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER6_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER6 */
|
||||
|
||||
#ifdef BSP_USING_TIMER7
|
||||
#ifndef TIMER7_IRQ_CONFIG
|
||||
#define TIMER7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER7_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER7_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER7_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER7 */
|
||||
|
||||
#ifdef BSP_USING_TIMER8
|
||||
#ifndef TIMER8_IRQ_CONFIG
|
||||
#define TIMER8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER8_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER8_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER8_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER8 */
|
||||
|
||||
#ifdef BSP_USING_TIMER9
|
||||
#ifndef TIMER9_IRQ_CONFIG
|
||||
#define TIMER9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER9_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER9_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER9_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER9 */
|
||||
|
||||
#ifdef BSP_USING_TIMER10
|
||||
#ifndef TIMER10_IRQ_CONFIG
|
||||
#define TIMER10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER10_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER10_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER10_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER10 */
|
||||
|
||||
#ifdef BSP_USING_TIMER11
|
||||
#ifndef TIMER11_IRQ_CONFIG
|
||||
#define TIMER11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER11_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER11_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER11_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER11 */
|
||||
|
||||
#ifdef BSP_USING_TIMER12
|
||||
#ifndef TIMER12_IRQ_CONFIG
|
||||
#define TIMER12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = TIMER12_CNT_INT_IRQn, \
|
||||
.irq_prio = TIMER12_CNT_INT_PRIO, \
|
||||
}
|
||||
#endif /* TIMER12_IRQ_CONFIG */
|
||||
#endif /* BSP_USING_TIMER12 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_HWTIMER_H__ */
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtthread.h>
|
||||
#include "drv_irq.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
|
||||
void (*irq_hdr)(void),
|
||||
rt_bool_t irq_enable)
|
||||
{
|
||||
rt_err_t result = -RT_ERROR;
|
||||
stc_irq_signin_config_t stcIrqSignConfig;
|
||||
|
||||
RT_ASSERT(RT_NULL != irq_config);
|
||||
RT_ASSERT(RT_NULL != irq_hdr);
|
||||
|
||||
stcIrqSignConfig.enIRQn = irq_config->irq_num;
|
||||
stcIrqSignConfig.enIntSrc = irq_config->int_src;
|
||||
stcIrqSignConfig.pfnCallback = irq_hdr;
|
||||
if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig))
|
||||
{
|
||||
NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn);
|
||||
NVIC_SetPriority(stcIrqSignConfig.enIRQn, irq_config->irq_prio);
|
||||
if (RT_TRUE == irq_enable)
|
||||
{
|
||||
NVIC_EnableIRQ(stcIrqSignConfig.enIRQn);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC_DisableIRQ(stcIrqSignConfig.enIRQn);
|
||||
}
|
||||
result = RT_EOK;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_IRQ_H__
|
||||
#define __DRV_IRQ_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtdef.h>
|
||||
#include "hc32_ll.h"
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
struct hc32_irq_config
|
||||
{
|
||||
IRQn_Type irq_num;
|
||||
uint32_t irq_prio;
|
||||
en_int_src_t int_src;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
|
||||
void (*irq_hdr)(void),
|
||||
rt_bool_t irq_enable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_IRQ_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: DO NOT include this file on the header file.
|
||||
*/
|
||||
|
||||
#ifndef LOG_TAG
|
||||
#define DBG_TAG "drv"
|
||||
#else
|
||||
#define DBG_TAG LOG_TAG
|
||||
#endif /* LOG_TAG */
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#else
|
||||
#define DBG_LVL DBG_INFO
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
#include <rtdbg.h>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,195 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtdbg.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <sys/time.h>
|
||||
|
||||
#ifdef BSP_USING_RTC
|
||||
|
||||
static struct rt_device rtc;
|
||||
|
||||
static time_t hc32_rtc_get_time_stamp(void)
|
||||
{
|
||||
stc_rtc_time_t stcRtcTime = {0};
|
||||
stc_rtc_date_t stcRtcDate = {0};
|
||||
struct tm tm_new = {0};
|
||||
|
||||
RTC_GetTime(RTC_DATA_FMT_DEC, &stcRtcTime);
|
||||
RTC_GetDate(RTC_DATA_FMT_DEC, &stcRtcDate);
|
||||
|
||||
tm_new.tm_sec = stcRtcTime.u8Second;
|
||||
tm_new.tm_min = stcRtcTime.u8Minute;
|
||||
tm_new.tm_hour = stcRtcTime.u8Hour;
|
||||
tm_new.tm_mday = stcRtcDate.u8Day;
|
||||
tm_new.tm_mon = stcRtcDate.u8Month - 1;
|
||||
tm_new.tm_year = stcRtcDate.u8Year + 100;
|
||||
tm_new.tm_wday = stcRtcDate.u8Weekday;
|
||||
|
||||
LOG_D("get rtc time.");
|
||||
return timegm(&tm_new);
|
||||
}
|
||||
|
||||
static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp)
|
||||
{
|
||||
stc_rtc_time_t stcRtcTime = {0};
|
||||
stc_rtc_date_t stcRtcDate = {0};
|
||||
struct tm *p_tm;
|
||||
|
||||
p_tm = gmtime(&time_stamp);
|
||||
if (p_tm->tm_year < 100)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
stcRtcTime.u8Second = p_tm->tm_sec ;
|
||||
stcRtcTime.u8Minute = p_tm->tm_min ;
|
||||
stcRtcTime.u8Hour = p_tm->tm_hour;
|
||||
stcRtcDate.u8Day = p_tm->tm_mday;
|
||||
stcRtcDate.u8Month = p_tm->tm_mon + 1 ;
|
||||
stcRtcDate.u8Year = p_tm->tm_year - 100;
|
||||
stcRtcDate.u8Weekday = p_tm->tm_wday;
|
||||
|
||||
if (LL_OK != RTC_SetTime(RTC_DATA_FMT_DEC, &stcRtcTime))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (LL_OK != RTC_SetDate(RTC_DATA_FMT_DEC, &stcRtcDate))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
LOG_D("set rtc time.");
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t hc32_rtc_init(struct rt_device *dev)
|
||||
{
|
||||
stc_rtc_init_t stcRtcInit;
|
||||
|
||||
#ifdef BSP_RTC_USING_XTAL32
|
||||
stc_clk_xtal32_init_t stcXtal32Init;
|
||||
|
||||
/* Xtal32 config */
|
||||
stcXtal32Init.u8Xtal32State = CLK_XTAL32_ON;
|
||||
stcXtal32Init.u8Xtal32Drv = CLK_XTAL32DRV_HIGH;
|
||||
stcXtal32Init.u8Xtal32NF = CLK_XTAL32NF_PART;
|
||||
(void)CLK_Xtal32Init(&stcXtal32Init);
|
||||
/* Waiting for XTAL32 stabilization */
|
||||
rt_thread_delay(1000);
|
||||
#endif
|
||||
|
||||
/* Reset RTC counter */
|
||||
if (LL_ERR_TIMEOUT == RTC_DeInit())
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configure structure initialization */
|
||||
(void)RTC_StructInit(&stcRtcInit);
|
||||
/* Configuration RTC structure */
|
||||
#ifdef BSP_RTC_USING_XTAL32
|
||||
stcRtcInit.u8ClockSrc = RTC_CLK_SRC_XTAL32;
|
||||
#else
|
||||
stcRtcInit.u8ClockSrc = RTC_CLK_SRC_LRC;
|
||||
#endif
|
||||
stcRtcInit.u8HourFormat = RTC_HOUR_FMT_24H;
|
||||
(void)RTC_Init(&stcRtcInit);
|
||||
/* Startup RTC count */
|
||||
RTC_Cmd(ENABLE);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t hc32_rtc_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_RTC_GET_TIME:
|
||||
*(rt_uint32_t *)args = hc32_rtc_get_time_stamp();
|
||||
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_RTC_SET_TIME:
|
||||
if (hc32_rtc_set_time_stamp(*(rt_uint32_t *)args))
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
|
||||
break;
|
||||
default:
|
||||
return RT_EINVAL;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
const static struct rt_device_ops rtc_ops =
|
||||
{
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
hc32_rtc_control
|
||||
};
|
||||
#endif
|
||||
|
||||
//static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
|
||||
//{
|
||||
// RT_ASSERT(device != RT_NULL);
|
||||
|
||||
// if (hc32_rtc_init(device) != RT_EOK)
|
||||
// {
|
||||
// return -RT_ERROR;
|
||||
// }
|
||||
//#ifdef RT_USING_DEVICE_OPS
|
||||
// device->ops = &rtc_ops;
|
||||
//#else
|
||||
// device->init = RT_NULL;
|
||||
// device->open = RT_NULL;
|
||||
// device->close = RT_NULL;
|
||||
// device->read = RT_NULL;
|
||||
// device->write = RT_NULL;
|
||||
// device->control = hc32_rtc_control;
|
||||
//#endif
|
||||
// device->type = RT_Device_Class_RTC;
|
||||
// device->rx_indicate = RT_NULL;
|
||||
// device->tx_complete = RT_NULL;
|
||||
// device->user_data = RT_NULL;
|
||||
|
||||
// /* register a character device */
|
||||
// return rt_device_register(device, name, flag);
|
||||
//}
|
||||
|
||||
int rt_hw_rtc_init(void)
|
||||
{
|
||||
// rt_err_t result;
|
||||
|
||||
// result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
|
||||
// if (result != RT_EOK)
|
||||
// {
|
||||
// LOG_E("rtc register err code: %d", result);
|
||||
// return result;
|
||||
// }
|
||||
// LOG_D("rtc init success");
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
|
||||
|
||||
#endif /* BSP_USING_RTC */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __DRV_I2C_H__
|
||||
#define __DRV_I2C_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtdevice.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
struct hc32_soft_i2c_config
|
||||
{
|
||||
rt_uint16_t scl_pin;
|
||||
rt_uint16_t sda_pin;
|
||||
const char *bus_name;
|
||||
};
|
||||
|
||||
struct hc32_i2c
|
||||
{
|
||||
struct rt_i2c_bit_ops ops;
|
||||
struct rt_i2c_bus_device i2c_bus;
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_I2C1
|
||||
#define I2C1_BUS_CONFIG \
|
||||
{ \
|
||||
.scl_pin = BSP_I2C1_SCL_PIN, \
|
||||
.sda_pin = BSP_I2C1_SDA_PIN, \
|
||||
.bus_name = "i2c1", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C2
|
||||
#define I2C2_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C2_SCL_PIN, \
|
||||
.sda = BSP_I2C2_SDA_PIN, \
|
||||
.bus_name = "i2c2", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C3
|
||||
#define I2C3_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C3_SCL_PIN, \
|
||||
.sda = BSP_I2C3_SDA_PIN, \
|
||||
.bus_name = "i2c3", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C4
|
||||
#define I2C4_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C4_SCL_PIN, \
|
||||
.sda = BSP_I2C4_SDA_PIN, \
|
||||
.bus_name = "i2c4", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C5
|
||||
#define I2C5_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C5_SCL_PIN, \
|
||||
.sda = BSP_I2C5_SDA_PIN, \
|
||||
.bus_name = "i2c5", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C6
|
||||
#define I2C6_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C6_SCL_PIN, \
|
||||
.sda = BSP_I2C6_SDA_PIN, \
|
||||
.bus_name = "i2c6", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_I2C_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __DRV_SPI_H__
|
||||
#define __DRV_SPI_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include "drv_dma.h"
|
||||
#include "drv_irq.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
struct hc32_hw_spi_cs
|
||||
{
|
||||
rt_uint8_t port;
|
||||
rt_uint16_t pin;
|
||||
};
|
||||
|
||||
struct hc32_spi_config
|
||||
{
|
||||
CM_SPI_TypeDef *Instance;
|
||||
char *bus_name;
|
||||
rt_uint32_t clock;
|
||||
// struct hc32_irq_config irq_config;
|
||||
struct dma_config *dma_rx;
|
||||
struct dma_config *dma_tx;
|
||||
};
|
||||
|
||||
struct hc32_spi
|
||||
{
|
||||
struct hc32_spi_config *config;
|
||||
struct rt_spi_configuration *cfg;
|
||||
struct rt_spi_bus spi_bus;
|
||||
rt_uint8_t spi_dma_flag;
|
||||
};
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint8_t cs_gpio_port, uint16_t cs_gpio_pin);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_SPI_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_USART_H__
|
||||
#define __DRV_USART_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include "drv_irq.h"
|
||||
#include "drv_dma.h"
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
struct hc32_uart_irq_config
|
||||
{
|
||||
struct hc32_irq_config irq_config;
|
||||
func_ptr_t irq_callback;
|
||||
};
|
||||
|
||||
/* HC32 config Rx timeout */
|
||||
struct hc32_uart_rxto
|
||||
{
|
||||
CM_TMR0_TypeDef *TMR0_Instance;
|
||||
rt_uint32_t channel;
|
||||
rt_uint32_t clock;
|
||||
rt_size_t timeout_bits;
|
||||
struct hc32_irq_config irq_config;
|
||||
func_ptr_t irq_callback;
|
||||
};
|
||||
|
||||
/* HC32 config uart class */
|
||||
struct hc32_uart_config
|
||||
{
|
||||
const char *name;
|
||||
CM_USART_TypeDef *Instance;
|
||||
rt_uint32_t clock;
|
||||
struct hc32_uart_irq_config rxerr_irq;
|
||||
struct hc32_uart_irq_config rx_irq;
|
||||
struct hc32_uart_irq_config tx_irq;
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
struct hc32_uart_rxto *rx_timeout;
|
||||
struct dma_config *dma_rx;
|
||||
struct hc32_uart_irq_config *tc_irq;
|
||||
struct dma_config *dma_tx;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* HC32 uart dirver class */
|
||||
struct hc32_uart
|
||||
{
|
||||
struct hc32_uart_config *config;
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
rt_size_t dma_rx_last_index;
|
||||
#endif
|
||||
rt_uint16_t uart_dma_flag;
|
||||
struct rt_serial_device serial;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_USART_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,29 @@
|
||||
BSD 3-Clause License
|
||||
|
||||
Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. ("XHSC")
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of the copyright holder nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
@@ -0,0 +1,4 @@
|
||||
version date comment
|
||||
2.0.0
|
||||
Mar 31, 2022 Initial release.
|
||||
EOF
|
||||
@@ -0,0 +1,74 @@
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Split('''
|
||||
drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_aos.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_clk.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_dma.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_efm.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_fcg.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_gpio.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_icg.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_interrupts.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_pwc.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_rmu.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_sram.c
|
||||
drivers/hc32_ll_driver/src/hc32_ll_utility.c
|
||||
drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c
|
||||
''')
|
||||
|
||||
if GetDepend(['RT_USING_SERIAL']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_usart.c']
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr0.c']
|
||||
|
||||
if GetDepend(['RT_USING_I2C']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_i2c.c']
|
||||
|
||||
if GetDepend(['RT_USING_SPI']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_spi.c']
|
||||
|
||||
if GetDepend(['RT_USING_CAN']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_can.c']
|
||||
|
||||
if GetDepend(['BSP_USING_ETH']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_eth.c']
|
||||
|
||||
if GetDepend(['RT_USING_ADC']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_adc.c']
|
||||
|
||||
if GetDepend(['RT_USING_DAC']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_dac.c']
|
||||
|
||||
if GetDepend(['RT_USING_RTC']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_rtc.c']
|
||||
|
||||
if GetDepend(['RT_USING_WDT']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_swdt.c']
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_wdt.c']
|
||||
|
||||
if GetDepend(['RT_USING_SDIO']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_sdioc.c']
|
||||
|
||||
if GetDepend(['RT_USING_ON_CHIP_FLASH']):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_efm.c']
|
||||
|
||||
if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])):
|
||||
src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c']
|
||||
|
||||
path = [
|
||||
cwd + '/drivers/cmsis/Device/HDSC/hc32f4xx/Include',
|
||||
cwd + '/drivers/cmsis/Include',
|
||||
cwd + '/drivers/hc32_ll_driver/inc',]
|
||||
|
||||
CPPDEFINES = ['USE_DDL_DRIVER']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,16 @@
|
||||
setup()
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
__message "----- Prepare hardware for Flashloader -----\n";
|
||||
setup();
|
||||
}
|
||||
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
|
||||
{
|
||||
__message "----- Prepare hardware for Flashloader -----\n";
|
||||
setup();
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.out</exe>
|
||||
<page>4</page>
|
||||
<block>1 0x1800</block>
|
||||
<flash_base>0x03000000</flash_base>
|
||||
<macro>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
</flash_device>
|
||||
Binary file not shown.
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.out</exe>
|
||||
<page>256</page>
|
||||
<block>2048 0x1000</block>
|
||||
<flash_base>0x98000000</flash_base>
|
||||
<aggregate>0</aggregate>
|
||||
</flash_device>
|
||||
Binary file not shown.
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.out</exe>
|
||||
<page>4</page>
|
||||
<block>128 0x2000</block>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<macro>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
</flash_device>
|
||||
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.out</exe>
|
||||
<page>4</page>
|
||||
<block>256 0x2000</block>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<macro>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
</flash_device>
|
||||
@@ -0,0 +1,18 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0xG.flash</loader>
|
||||
<range>CODE 0x0 0xFFFFF</range>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.flash</loader>
|
||||
<range>CODE 0x03000000 0x030017FF</range>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.flash</loader>
|
||||
<range>CODE 0x98000000 0x987FFFFF</range>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0xI.flash</loader>
|
||||
<range>CODE 0x0 0x1FFFFF</range>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.flash</loader>
|
||||
<range>CODE 0x03000000 0x030017FF</range>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.flash</loader>
|
||||
<range>CODE 0x98000000 0x987FFFFF</range>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x1FFE0000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFE0000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,53 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in QSPI_region { readonly section .ex_rom };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,53 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in QSPI_region { readonly section .ex_rom };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
+23785
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,66 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4xx.h
|
||||
* @brief This file contains the common part of the HC32 series.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4XX_H__
|
||||
#define __HC32F4XX_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @brief HC32F4xx Device Include
|
||||
*/
|
||||
#if defined(HC32F4A0)
|
||||
#include "hc32f4a0.h"
|
||||
#include "system_hc32f4a0.h"
|
||||
#else
|
||||
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4XX_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
+142
@@ -0,0 +1,142 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f4a0.h
|
||||
* @brief This file contains all the functions prototypes of the HC32 System.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2022-03-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __SYSTEM_HC32F4A0_H__
|
||||
#define __SYSTEM_HC32F4A0_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#if !defined (MRC_VALUE)
|
||||
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (LRC_VALUE)
|
||||
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (RTCLRC_VALUE)
|
||||
#define RTCLRC_VALUE (32768UL) /*!< Internal RTC low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (SWDTLRC_VALUE)
|
||||
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL_VALUE)
|
||||
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL32_VALUE)
|
||||
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
|
||||
#endif
|
||||
|
||||
#if !defined (HCLK_VALUE)
|
||||
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Exported_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
|
||||
extern uint32_t HRC_VALUE; /*!< HRC frequency */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void); /*!< Initialize the system */
|
||||
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
|
||||
|
||||
#if defined (ROM_EXT_QSPI)
|
||||
void SystemInit_QspiMem(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_HC32F4A0_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+16
@@ -0,0 +1,16 @@
|
||||
FUNC void Setup (void) {
|
||||
|
||||
SP = _RDWORD(0x1FFE0000);
|
||||
|
||||
PC = _RDWORD(0x1FFE0004);
|
||||
|
||||
_WDWORD(0xE000ED08, 0x1FFE0000);
|
||||
|
||||
}
|
||||
|
||||
|
||||
LOAD .\output\release\efm_sequence_program.axf INCREMENTAL
|
||||
|
||||
Setup();
|
||||
|
||||
g, main
|
||||
BIN
Binary file not shown.
+594
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user