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Unified management interrupt vector table. (#5925)

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* Unified management interrupt vector table.
This commit is contained in:
Jamie
2022-05-15 20:57:35 +08:00
committed by GitHub
parent e848031c93
commit db27095da6
18 changed files with 774 additions and 434 deletions
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bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript
+1
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@@ -20,6 +20,7 @@ if GetDepend(['BSP_USING_SPI_FLASH']):
path = [cwd]
path += [cwd + '/ports']
path += [cwd + '/config']
startup_path_prefix = SDK_LIB
bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c
+19
View File
@@ -81,6 +81,24 @@ void SystemClock_Config(void)
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
}
/** Peripheral Clock Configuration
*/
static void PeripheralClock_Config(void)
{
#if defined(HC32F4A0)
#if defined(BSP_USING_CAN1)
CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
#endif
#if defined(BSP_USING_CAN2)
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
#endif
#if defined(RT_USING_ADC)
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
#endif
#endif
}
/*******************************************************************************
* Function Name : SysTick_Configuration
* Description : Configures the SysTick for OS tick.
@@ -124,6 +142,7 @@ void rt_hw_board_init()
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
SystemClock_Config();
PeripheralClock_Config();
/* Configure the SysTick */
SysTick_Configuration();
bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c
-19
View File
@@ -95,22 +95,6 @@ rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx)
#endif
#if defined(RT_USING_ADC)
void rt_hw_board_adc_clock_init(void)
{
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
/* 1. Enable ADC peripheral clock. */
#if defined(BSP_USING_ADC1)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE);
#endif
#if defined(BSP_USING_ADC2)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE);
#endif
#if defined(BSP_USING_ADC3)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE);
#endif
}
rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
{
rt_err_t result = RT_EOK;
@@ -122,19 +106,16 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
{
#if defined(BSP_USING_ADC1)
case (rt_uint32_t)CM_ADC1:
(void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
break;
#endif
#if defined(BSP_USING_ADC2)
case (rt_uint32_t)CM_ADC2:
(void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
break;
#endif
#if defined(BSP_USING_ADC3)
case (rt_uint32_t)CM_ADC3:
(void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
break;
#endif
bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h
-8
View File
@@ -87,10 +87,6 @@
#define CAN1_RX_PORT (GPIO_PORT_D)
#define CAN1_RX_PIN (GPIO_PIN_04)
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61)
#define CAN1_INT_PRIO (DDL_IRQ_PRIO_03)
#define CAN1_INT_SRC (INT_SRC_CAN1_HOST)
#define CAN1_INT_IRQn (INT004_IRQn)
#endif
#if defined(BSP_USING_CAN2)
@@ -101,10 +97,6 @@
#define CAN2_RX_PORT (GPIO_PORT_D)
#define CAN2_RX_PIN (GPIO_PIN_06)
#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63)
#define CAN2_INT_PRIO (DDL_IRQ_PRIO_03)
#define CAN2_INT_SRC (INT_SRC_CAN2_HOST)
#define CAN2_INT_IRQn (INT005_IRQn)
#endif
#endif
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h
+10 -9
View File
@@ -12,14 +12,15 @@
#define __ADC_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
#ifndef ADC1_INIT_PARAMS
#define ADC1_INIT_PARAMS \
{ \
.name = "adc1", \
.resolution = ADC_RESOLUTION_12BIT, \
@@ -36,12 +37,12 @@ extern "C" {
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC1_CONFIG */
#endif /* ADC1_INIT_PARAMS */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
#ifndef ADC2_INIT_PARAMS
#define ADC2_INIT_PARAMS \
{ \
.name = "adc2", \
.resolution = ADC_RESOLUTION_12BIT, \
@@ -58,12 +59,12 @@ extern "C" {
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC2_CONFIG */
#endif /* ADC2_INIT_PARAMS */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
#ifndef ADC3_INIT_PARAMS
#define ADC3_INIT_PARAMS \
{ \
.name = "adc3", \
.resolution = ADC_RESOLUTION_12BIT, \
@@ -80,7 +81,7 @@ extern "C" {
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC3_CONFIG */
#endif /* ADC3_INIT_PARAMS */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h
+88 -6
View File
@@ -12,29 +12,111 @@
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_CAN1
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
#ifndef CAN1_INIT_PARAMS
#define CAN1_INIT_PARAMS \
{ \
.name = "can1", \
}
#endif /* CAN1_CONFIG */
#endif /* CAN1_INIT_PARAMS */
#endif /* BSP_USING_CAN1 */
#ifdef BSP_USING_CAN2
#ifndef CAN2_CONFIG
#define CAN2_CONFIG \
#ifndef CAN2_INIT_PARAMS
#define CAN2_INIT_PARAMS \
{ \
.name = "can2", \
}
#endif /* CAN2_CONFIG */
#endif /* CAN2_INIT_PARAMS */
#endif /* BSP_USING_CAN2 */
/* Bit time config
Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
TQ = u32Prescaler / CANClock.
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
The following bit time configures are based on CAN Clock 40M
*/
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
{ \
.u32Prescaler = 2, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
{ \
.u32Prescaler = 2, \
.u32TimeSeg1 = 20, \
.u32TimeSeg2 = 5, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
{ \
.u32Prescaler = 4, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
{ \
.u32Prescaler = 8, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
{ \
.u32Prescaler = 16, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
{ \
.u32Prescaler = 20, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
{ \
.u32Prescaler = 40, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
{ \
.u32Prescaler = 100, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
{ \
.u32Prescaler = 200, \
.u32TimeSeg1 = 16, \
.u32TimeSeg2 = 4, \
.u32SJW = 4 \
}
#ifdef __cplusplus
}
#endif
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h
+33 -32
View File
@@ -12,6 +12,7 @@
#define __DMA_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
@@ -23,8 +24,8 @@ extern "C" {
#define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_IRQn INT038_IRQn
#define SPI1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#endif
@@ -34,8 +35,8 @@ extern "C" {
#define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_IRQn INT039_IRQn
#define SPI1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#endif
@@ -45,8 +46,8 @@ extern "C" {
#define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_IRQn INT040_IRQn
#define SPI2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#endif
@@ -56,8 +57,8 @@ extern "C" {
#define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_IRQn INT041_IRQn
#define SPI2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#endif
@@ -67,8 +68,8 @@ extern "C" {
#define SPI3_RX_DMA_CHANNEL DMA_CH4
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4
#define SPI3_RX_DMA_IRQn INT042_IRQn
#define SPI3_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
#endif
@@ -78,8 +79,8 @@ extern "C" {
#define SPI3_TX_DMA_CHANNEL DMA_CH5
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5
#define SPI3_TX_DMA_IRQn INT043_IRQn
#define SPI3_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
#endif
@@ -89,8 +90,8 @@ extern "C" {
#define SPI4_RX_DMA_CHANNEL DMA_CH6
#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6
#define SPI4_RX_DMA_IRQn INT018_IRQn
#define SPI4_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6
#endif
@@ -100,8 +101,8 @@ extern "C" {
#define SPI4_TX_DMA_CHANNEL DMA_CH7
#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7
#define SPI4_TX_DMA_IRQn INT019_IRQn
#define SPI4_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7
#endif
@@ -111,8 +112,8 @@ extern "C" {
#define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_RX_DMA_IRQn INT044_IRQn
#define UART1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#endif
@@ -122,8 +123,8 @@ extern "C" {
#define UART1_TX_DMA_CHANNEL DMA_CH1
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART1_TX_DMA_IRQn INT045_IRQn
#define UART1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#endif
@@ -133,8 +134,8 @@ extern "C" {
#define UART2_RX_DMA_CHANNEL DMA_CH2
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART2_RX_DMA_IRQn INT046_IRQn
#define UART2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#endif
@@ -144,8 +145,8 @@ extern "C" {
#define UART2_TX_DMA_CHANNEL DMA_CH3
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART2_TX_DMA_IRQn INT047_IRQn
#define UART2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#endif
@@ -155,8 +156,8 @@ extern "C" {
#define UART6_RX_DMA_CHANNEL DMA_CH4
#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4
#define UART6_RX_DMA_IRQn INT048_IRQn
#define UART6_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
#endif
@@ -166,8 +167,8 @@ extern "C" {
#define UART6_TX_DMA_CHANNEL DMA_CH5
#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5
#define UART6_TX_DMA_IRQn INT049_IRQn
#define UART6_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
#endif
@@ -177,8 +178,8 @@ extern "C" {
#define UART7_RX_DMA_CHANNEL DMA_CH6
#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6
#define UART7_RX_DMA_IRQn INT020_IRQn
#define UART7_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM
#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO
#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6
#endif
@@ -188,8 +189,8 @@ extern "C" {
#define UART7_TX_DMA_CHANNEL DMA_CH7
#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7
#define UART7_TX_DMA_IRQn INT021_IRQn
#define UART7_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM
#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO
#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7
#endif
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h
+3 -2
View File
@@ -12,6 +12,7 @@
#define __ETH_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
@@ -23,8 +24,8 @@ extern "C" {
#ifndef ETH_IRQ_CONFIG
#define ETH_IRQ_CONFIG \
{ \
.irq_num = INT104_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_ETH_IRQ_NUM, \
.irq_prio = BSP_ETH_IRQ_PRIO, \
.int_src = INT_SRC_ETH_GLB_INT, \
}
#endif /* ETH_IRQ_CONFIG */
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h
+33 -32
View File
@@ -12,6 +12,7 @@
#define __GPIO_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
@@ -23,8 +24,8 @@ extern "C" {
#ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = INT022_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \
}
#endif /* EXTINT1_IRQ_CONFIG */
@@ -32,8 +33,8 @@ extern "C" {
#ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = INT023_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \
}
#endif /* EXTINT1_IRQ_CONFIG */
@@ -41,8 +42,8 @@ extern "C" {
#ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = INT024_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \
}
#endif /* EXTINT2_IRQ_CONFIG */
@@ -50,8 +51,8 @@ extern "C" {
#ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = INT025_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \
}
#endif /* EXTINT3_IRQ_CONFIG */
@@ -59,8 +60,8 @@ extern "C" {
#ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = INT026_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \
}
#endif /* EXTINT4_IRQ_CONFIG */
@@ -68,8 +69,8 @@ extern "C" {
#ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = INT027_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \
}
#endif /* EXTINT5_IRQ_CONFIG */
@@ -77,8 +78,8 @@ extern "C" {
#ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = INT028_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \
}
#endif /* EXTINT6_IRQ_CONFIG */
@@ -86,8 +87,8 @@ extern "C" {
#ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = INT029_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \
}
#endif /* EXTINT7_IRQ_CONFIG */
@@ -95,8 +96,8 @@ extern "C" {
#ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = INT030_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \
}
#endif /* EXTINT8_IRQ_CONFIG */
@@ -104,8 +105,8 @@ extern "C" {
#ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = INT031_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \
}
#endif /* EXTINT9_IRQ_CONFIG */
@@ -113,8 +114,8 @@ extern "C" {
#ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = INT032_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \
}
#endif /* EXTINT10_IRQ_CONFIG */
@@ -122,8 +123,8 @@ extern "C" {
#ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = INT033_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \
}
#endif /* EXTINT11_IRQ_CONFIG */
@@ -131,8 +132,8 @@ extern "C" {
#ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = INT034_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \
}
#endif /* EXTINT12_IRQ_CONFIG */
@@ -140,8 +141,8 @@ extern "C" {
#ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = INT035_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \
}
#endif /* EXTINT13_IRQ_CONFIG */
@@ -149,8 +150,8 @@ extern "C" {
#ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = INT036_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \
}
#endif /* EXTINT14_IRQ_CONFIG */
@@ -158,8 +159,8 @@ extern "C" {
#ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = INT037_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \
}
#endif /* EXTINT15_IRQ_CONFIG */
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h
+248
View File
@@ -0,0 +1,248 @@
/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __IRQ_CONFIG_H__
#define __IRQ_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#define BSP_EXTINT0_IRQ_NUM INT022_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM INT023_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM INT024_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM INT025_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM INT026_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM INT027_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM INT028_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM INT029_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM INT030_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM INT031_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM INT032_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM INT033_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM INT034_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM INT035_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM INT036_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM INT037_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch0 */
#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch1 */
#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch2 */
#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch3 */
#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch4 */
#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch5 */
#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch6 */
#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn
#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch7 */
#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch0 */
#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch1 */
#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch2 */
#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch3 */
#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch4 */
#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn
#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch5 */
#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn
#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch6 */
#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn
#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch7 */
#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn
#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_ETH)
#define BSP_ETH_IRQ_NUM INT104_IRQn
#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_USING_UART1)
#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn
#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_RX_IRQ_NUM INT089_IRQn
#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART1_TX_IRQ_NUM INT088_IRQn
#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART1_RX_USING_DMA)
#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn
#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_UART1_TX_USING_DMA)
#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn
#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_RX_IRQ_NUM INT091_IRQn
#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART2_TX_IRQ_NUM INT090_IRQn
#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART2_RX_USING_DMA)
#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn
#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_UART2_TX_USING_DMA)
#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn
#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_RX_IRQ_NUM INT095_IRQn
#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART3_TX_IRQ_NUM INT094_IRQn
#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn
#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_RX_IRQ_NUM INT097_IRQn
#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART4_TX_IRQ_NUM INT096_IRQn
#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn
#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART5_RX_IRQ_NUM INT101_IRQn
#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART5_TX_IRQ_NUM INT100_IRQn
#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn
#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART6_RX_IRQ_NUM INT103_IRQn
#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART6_TX_IRQ_NUM INT102_IRQn
#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART6_RX_USING_DMA)
#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn
#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_UART6_TX_USING_DMA)
#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn
#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn
#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART7_RX_IRQ_NUM INT107_IRQn
#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART7_TX_IRQ_NUM INT106_IRQn
#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_UART7_RX_USING_DMA)
#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn
#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#if defined(BSP_UART7_TX_USING_DMA)
#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn
#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif
#endif /* BSP_USING_UART7 */
#if defined(BSP_USING_UART8)
#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn
#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART8_RX_IRQ_NUM INT109_IRQn
#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART8_TX_IRQ_NUM INT108_IRQn
#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART8 */
#if defined(BSP_USING_UART9)
#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn
#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART9_RX_IRQ_NUM INT110_IRQn
#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART9_TX_IRQ_NUM INT111_IRQn
#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART9 */
#if defined(BSP_USING_UART10)
#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn
#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART10_RX_IRQ_NUM INT114_IRQn
#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_UART10_TX_IRQ_NUM INT113_IRQn
#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART10 */
#if defined(BSP_USING_CAN1)
#define BSP_CAN1_IRQ_NUM INT004_IRQn
#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_CAN1 */
#if defined(BSP_USING_CAN2)
#define BSP_CAN2_IRQ_NUM INT005_IRQn
#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_CAN2 */
#ifdef __cplusplus
}
#endif
#endif /* __IRQ_CONFIG_H__ */
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h
+1
View File
@@ -12,6 +12,7 @@
#define __SPI_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h
+1
View File
@@ -12,6 +12,7 @@
#define __TIM_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h
+77 -76
View File
@@ -12,6 +12,7 @@
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "irq_config.h"
#ifdef __cplusplus
extern "C" {
@@ -27,20 +28,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART1, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT010_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART1_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART1_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT089_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART1_RX_IRQ_NUM, \
.irq_prio = BSP_UART1_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART1_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT088_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART1_TX_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TI, \
}, \
}
@@ -73,8 +74,8 @@ extern "C" {
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT006_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART1_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART1_RTO, \
}, \
}
@@ -87,8 +88,8 @@ extern "C" {
{ \
.irq_config = \
{ \
.irq_num = INT086_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
@@ -122,20 +123,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART2, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT011_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART2_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART2_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT091_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART2_RX_IRQ_NUM, \
.irq_prio = BSP_UART2_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART2_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT090_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART2_TX_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TI, \
}, \
}
@@ -168,8 +169,8 @@ extern "C" {
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT007_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART2_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART2_RTO, \
}, \
}
@@ -182,8 +183,8 @@ extern "C" {
{ \
.irq_config = \
{ \
.irq_num = INT087_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
@@ -217,20 +218,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART3, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT012_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART3_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART3_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT095_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART3_RX_IRQ_NUM, \
.irq_prio = BSP_UART3_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART3_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT094_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART3_TX_IRQ_NUM, \
.irq_prio = BSP_UART3_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART3_TI, \
}, \
}
@@ -246,20 +247,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART4, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT013_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART4_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART4_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT097_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART4_RX_IRQ_NUM, \
.irq_prio = BSP_UART4_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART4_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT096_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART4_TX_IRQ_NUM, \
.irq_prio = BSP_UART4_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART4_TI, \
}, \
}
@@ -275,20 +276,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART5, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT014_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART5_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART5_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT101_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART5_RX_IRQ_NUM, \
.irq_prio = BSP_UART5_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART5_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT100_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART5_TX_IRQ_NUM, \
.irq_prio = BSP_UART5_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART5_TI, \
}, \
}
@@ -304,20 +305,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART6, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT015_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART6_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART6_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT103_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART6_RX_IRQ_NUM, \
.irq_prio = BSP_UART6_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART6_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT102_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART6_TX_IRQ_NUM, \
.irq_prio = BSP_UART6_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART6_TI, \
}, \
}
@@ -350,8 +351,8 @@ extern "C" {
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT008_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART6_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART6_RTO, \
}, \
}
@@ -364,8 +365,8 @@ extern "C" {
{ \
.irq_config = \
{ \
.irq_num = INT099_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART6_TCI, \
}, \
}
@@ -399,20 +400,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART7, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT016_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART7_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART7_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT107_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART7_RX_IRQ_NUM, \
.irq_prio = BSP_UART7_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART7_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT106_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART7_TX_IRQ_NUM, \
.irq_prio = BSP_UART7_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART7_TI, \
}, \
}
@@ -445,8 +446,8 @@ extern "C" {
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT009_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART7_RXTO_IRQ_NUM, \
.irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \
.int_src = INT_SRC_USART7_RTO, \
}, \
}
@@ -459,8 +460,8 @@ extern "C" {
{ \
.irq_config = \
{ \
.irq_num = INT105_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \
.irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \
.int_src = INT_SRC_USART6_TCI, \
}, \
}
@@ -494,20 +495,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART8, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT017_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART8_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART8_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT109_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART8_RX_IRQ_NUM, \
.irq_prio = BSP_UART8_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART8_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT108_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART8_TX_IRQ_NUM, \
.irq_prio = BSP_UART8_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART8_TI, \
}, \
}
@@ -523,20 +524,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART9, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT112_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART9_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART9_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT110_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART9_RX_IRQ_NUM, \
.irq_prio = BSP_UART9_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART9_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT111_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART9_TX_IRQ_NUM, \
.irq_prio = BSP_UART9_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART9_TI, \
}, \
}
@@ -552,20 +553,20 @@ extern "C" {
.clock = FCG3_PERIPH_USART10, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT115_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART10_RXERR_IRQ_NUM, \
.irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \
.int_src = INT_SRC_USART7_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT114_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART10_RX_IRQ_NUM, \
.irq_prio = BSP_UART10_RX_IRQ_PRIO, \
.int_src = INT_SRC_USART7_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT113_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.irq_num = BSP_UART10_TX_IRQ_NUM, \
.irq_prio = BSP_UART10_TX_IRQ_PRIO, \
.int_src = INT_SRC_USART7_TI, \
}, \
}
bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h
+8 -8
View File
@@ -18,14 +18,14 @@
extern "C" {
#endif
#include "config/dma_config.h"
#include "config/uart_config.h"
#include "config/spi_config.h"
#include "config/adc_config.h"
#include "config/tim_config.h"
#include "config/gpio_config.h"
#include "config/eth_config.h"
#include "config/can_config.h"
#include "dma_config.h"
#include "uart_config.h"
#include "spi_config.h"
#include "adc_config.h"
#include "tim_config.h"
#include "gpio_config.h"
#include "eth_config.h"
#include "can_config.h"
#ifdef __cplusplus
}
bsp/hc32/libraries/hc32_drivers/drv_adc.c
+66 -56
View File
@@ -20,44 +20,44 @@
#ifdef RT_USING_ADC
typedef struct
{
struct rt_adc_device adc_dev;
CM_ADC_TypeDef *hc32_adc_instance;
struct hc32_adc_init_type init;
} hc32_adc_device;
struct rt_adc_device rt_adc;
CM_ADC_TypeDef *instance;
struct adc_dev_init_params init;
} adc_device;
#if !defined(BSP_USING_ADC1) && !defined(BSP_USING_ADC2) && !defined(BSP_USING_ADC3)
#error "Please define at least one BSP_USING_ADCx"
#endif
static hc32_adc_device g_hc32_devs[] =
static adc_device g_adc_dev_array[] =
{
#ifdef BSP_USING_ADC1
{
{0},
CM_ADC1,
ADC1_CONFIG,
ADC1_INIT_PARAMS,
},
#endif
#ifdef BSP_USING_ADC2
{
{0},
CM_ADC2,
ADC2_CONFIG,
ADC2_INIT_PARAMS,
},
#endif
#ifdef BSP_USING_ADC3
{
{0},
CM_ADC3,
ADC3_CONFIG,
ADC3_INIT_PARAMS,
},
#endif
};
static void internal_trigger0_set(hc32_adc_device *dev)
static void _adc_internal_trigger0_set(adc_device *p_adc_dev)
{
uint32_t u32TriggerSel;
rt_bool_t is_internal_trig0_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
rt_bool_t is_internal_trig0_enabled = (p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
if (is_internal_trig0_enabled == RT_FALSE)
{
@@ -65,7 +65,7 @@ static void internal_trigger0_set(hc32_adc_device *dev)
}
#if defined(HC32F4A0)
switch ((rt_uint32_t)dev->hc32_adc_instance)
switch ((rt_uint32_t)p_adc_dev->instance)
{
case (rt_uint32_t)CM_ADC1:
u32TriggerSel = AOS_ADC1_0;
@@ -79,16 +79,16 @@ static void internal_trigger0_set(hc32_adc_device *dev)
default:
break;
}
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
#endif
AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig0_sel);
AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig0_sel);
}
static void internal_trigger1_set(hc32_adc_device *dev)
static void _adc_internal_trigger1_set(adc_device *p_adc_dev)
{
uint32_t u32TriggerSel;
rt_bool_t is_internal_trig1_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
rt_bool_t is_internal_trig1_enabled = (p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
if (is_internal_trig1_enabled == RT_FALSE)
{
@@ -96,7 +96,7 @@ static void internal_trigger1_set(hc32_adc_device *dev)
}
#if defined(HC32F4A0)
switch ((rt_uint32_t)dev->hc32_adc_instance)
switch ((rt_uint32_t)p_adc_dev->instance)
{
case (rt_uint32_t)CM_ADC1:
u32TriggerSel = AOS_ADC1_1;
@@ -110,22 +110,20 @@ static void internal_trigger1_set(hc32_adc_device *dev)
default:
break;
}
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
#endif
AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig1_sel);
AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig1_sel);
}
static rt_err_t hc32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
static rt_err_t _adc_enable(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
hc32_adc_device *adc;
adc = rt_container_of(device, hc32_adc_device, adc_dev);
ADC_ChCmd(adc->hc32_adc_instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled);
adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
ADC_ChCmd(p_adc_dev->instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled);
return 0;
}
static rt_err_t hc32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
static rt_err_t _adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
rt_err_t rt_ret = RT_ERROR;
@@ -134,81 +132,93 @@ static rt_err_t hc32_adc_convert(struct rt_adc_device *device, rt_uint32_t chann
return -RT_EINVAL;
}
hc32_adc_device *adc;
adc = rt_container_of(device, hc32_adc_device, adc_dev);
if (adc->init.hard_trig_enable == RT_FALSE && adc->hc32_adc_instance->STR == 0)
adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
if (p_adc_dev->init.hard_trig_enable == RT_FALSE && p_adc_dev->instance->STR == 0)
{
ADC_Start(adc->hc32_adc_instance);
ADC_Start(p_adc_dev->instance);
}
uint32_t start_time = rt_tick_get();
do
{
if (ADC_GetStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA) == SET)
if (ADC_GetStatus(p_adc_dev->instance, ADC_FLAG_EOCA) == SET)
{
ADC_ClearStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA);
ADC_ClearStatus(p_adc_dev->instance, ADC_FLAG_EOCA);
rt_ret = LL_OK;
break;
}
}
while ((rt_tick_get() - start_time) < adc->init.eoc_poll_time_max);
while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max);
if (rt_ret == LL_OK)
{
/* Get any ADC value of sequence A channel that needed. */
*value = ADC_GetValue(adc->hc32_adc_instance, channel);
*value = ADC_GetValue(p_adc_dev->instance, channel);
}
return rt_ret;
}
static struct rt_adc_ops g_hc32_adc_ops =
static struct rt_adc_ops g_adc_ops =
{
hc32_adc_enabled,
hc32_adc_convert,
_adc_enable,
_adc_convert,
};
static void _adc_clock_enable(void)
{
#if defined(HC32F4A0)
#if defined(BSP_USING_ADC1)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE);
#endif
#if defined(BSP_USING_ADC2)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE);
#endif
#if defined(BSP_USING_ADC3)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE);
#endif
#endif
}
extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx);
extern void rt_hw_board_adc_clock_init(void);
static int rt_hw_adc_init(void)
{
int ret, i = 0;
stc_adc_init_t stcAdcInit = {0};
int32_t ll_ret = 0;
rt_hw_board_adc_clock_init();
uint32_t dev_cnt = sizeof(g_hc32_devs) / sizeof(g_hc32_devs[0]);
_adc_clock_enable();
uint32_t dev_cnt = sizeof(g_adc_dev_array) / sizeof(g_adc_dev_array[0]);
for (; i < dev_cnt; i++)
{
ADC_DeInit(g_hc32_devs[i].hc32_adc_instance);
ADC_DeInit(g_adc_dev_array[i].instance);
/* Initializes ADC. */
stcAdcInit.u16Resolution = g_hc32_devs[i].init.resolution;
stcAdcInit.u16DataAlign = g_hc32_devs[i].init.data_align;
stcAdcInit.u16ScanMode = (g_hc32_devs[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT;
ll_ret = ADC_Init((void *)g_hc32_devs[i].hc32_adc_instance, &stcAdcInit);
stcAdcInit.u16Resolution = g_adc_dev_array[i].init.resolution;
stcAdcInit.u16DataAlign = g_adc_dev_array[i].init.data_align;
stcAdcInit.u16ScanMode = (g_adc_dev_array[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT;
ll_ret = ADC_Init((void *)g_adc_dev_array[i].instance, &stcAdcInit);
if (ll_ret != LL_OK)
{
ret = -RT_ERROR;
break;
}
ADC_TriggerCmd(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, (en_functional_state_t)g_hc32_devs[i].init.hard_trig_enable);
ADC_TriggerConfig(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, g_hc32_devs[i].init.hard_trig_src);
if (g_hc32_devs[i].init.hard_trig_enable && g_hc32_devs[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN)
ADC_TriggerCmd(g_adc_dev_array[i].instance, ADC_SEQ_A, (en_functional_state_t)g_adc_dev_array[i].init.hard_trig_enable);
ADC_TriggerConfig(g_adc_dev_array[i].instance, ADC_SEQ_A, g_adc_dev_array[i].init.hard_trig_src);
if (g_adc_dev_array[i].init.hard_trig_enable && g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN)
{
internal_trigger0_set(&g_hc32_devs[i]);
internal_trigger1_set(&g_hc32_devs[i]);
_adc_internal_trigger0_set(&g_adc_dev_array[i]);
_adc_internal_trigger1_set(&g_adc_dev_array[i]);
}
rt_hw_board_adc_init((void *)g_hc32_devs[i].hc32_adc_instance);
ret = rt_hw_adc_register(&g_hc32_devs[i].adc_dev, \
(const char *)g_hc32_devs[i].init.name, \
&g_hc32_adc_ops, (void *)g_hc32_devs[i].hc32_adc_instance);
rt_hw_board_adc_init((void *)g_adc_dev_array[i].instance);
ret = rt_hw_adc_register(&g_adc_dev_array[i].rt_adc, \
(const char *)g_adc_dev_array[i].init.name, \
&g_adc_ops, (void *)g_adc_dev_array[i].instance);
if (ret != RT_EOK)
{
/* TODO err handler */
// LOG_E("failed register %s, err=%d", g_hc32_devs[i].name, ret);
// LOG_E("failed register %s, err=%d", g_adc_dev_array[i].name, ret);
}
}
return ret;
bsp/hc32/libraries/hc32_drivers/drv_adc.h
+1 -1
View File
@@ -30,7 +30,7 @@ extern "C"
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
struct hc32_adc_init_type
struct adc_dev_init_params
{
char name[8];
uint16_t resolution; /*!< Specifies the ADC resolution.
bsp/hc32/libraries/hc32_drivers/drv_can.c
+183 -183
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/libraries/hc32_drivers/drv_can.h
+2 -2
View File
@@ -21,8 +21,8 @@ extern "C" {
/* stm32 can device */
struct hc32_can_init_type
/* hc32 can device */
struct can_dev_init_params
{
char *name;
};