From db27095da66f5c9f750c70d7c4460ded0549b778 Mon Sep 17 00:00:00 2001 From: Jamie <48308473+JamieTx@users.noreply.github.com> Date: Sun, 15 May 2022 20:57:35 +0800 Subject: [PATCH] Unified management interrupt vector table. (#5925) * Unified management interrupt vector table. --- bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript | 1 + bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c | 19 + .../ev_hc32f4a0_lqfp176/board/board_config.c | 19 - .../ev_hc32f4a0_lqfp176/board/board_config.h | 8 - .../board/config/adc_config.h | 19 +- .../board/config/can_config.h | 94 ++++- .../board/config/dma_config.h | 65 ++-- .../board/config/eth_config.h | 5 +- .../board/config/gpio_config.h | 65 ++-- .../board/config/irq_config.h | 248 ++++++++++++ .../board/config/spi_config.h | 1 + .../board/config/tim_config.h | 1 + .../board/config/uart_config.h | 153 ++++---- .../ev_hc32f4a0_lqfp176/board/drv_config.h | 16 +- bsp/hc32/libraries/hc32_drivers/drv_adc.c | 122 +++--- bsp/hc32/libraries/hc32_drivers/drv_adc.h | 2 +- bsp/hc32/libraries/hc32_drivers/drv_can.c | 366 +++++++++--------- bsp/hc32/libraries/hc32_drivers/drv_can.h | 4 +- 18 files changed, 774 insertions(+), 434 deletions(-) create mode 100644 bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript index abc21f957a..03d0c9f875 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript @@ -20,6 +20,7 @@ if GetDepend(['BSP_USING_SPI_FLASH']): path = [cwd] path += [cwd + '/ports'] +path += [cwd + '/config'] startup_path_prefix = SDK_LIB diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c index b3c27756d9..152ae9b123 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c @@ -81,6 +81,24 @@ void SystemClock_Config(void) CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); } +/** Peripheral Clock Configuration +*/ +static void PeripheralClock_Config(void) +{ +#if defined(HC32F4A0) +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif +#endif +} + /******************************************************************************* * Function Name : SysTick_Configuration * Description : Configures the SysTick for OS tick. @@ -124,6 +142,7 @@ void rt_hw_board_init() LL_PERIPH_WE(EXAMPLE_PERIPH_WE); SystemClock_Config(); + PeripheralClock_Config(); /* Configure the SysTick */ SysTick_Configuration(); diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c index 6029bbb25c..fd9fbe8d48 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c @@ -95,22 +95,6 @@ rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx) #endif #if defined(RT_USING_ADC) -void rt_hw_board_adc_clock_init(void) -{ - CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); - - /* 1. Enable ADC peripheral clock. */ -#if defined(BSP_USING_ADC1) - FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE); -#endif -#if defined(BSP_USING_ADC2) - FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE); -#endif -#if defined(BSP_USING_ADC3) - FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE); -#endif -} - rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) { rt_err_t result = RT_EOK; @@ -122,19 +106,16 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) { #if defined(BSP_USING_ADC1) case (rt_uint32_t)CM_ADC1: - (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); break; #endif #if defined(BSP_USING_ADC2) case (rt_uint32_t)CM_ADC2: - (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); break; #endif #if defined(BSP_USING_ADC3) case (rt_uint32_t)CM_ADC3: - (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); break; #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h index c419c67054..4e86ac5eeb 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h @@ -87,10 +87,6 @@ #define CAN1_RX_PORT (GPIO_PORT_D) #define CAN1_RX_PIN (GPIO_PIN_04) #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) - - #define CAN1_INT_PRIO (DDL_IRQ_PRIO_03) - #define CAN1_INT_SRC (INT_SRC_CAN1_HOST) - #define CAN1_INT_IRQn (INT004_IRQn) #endif #if defined(BSP_USING_CAN2) @@ -101,10 +97,6 @@ #define CAN2_RX_PORT (GPIO_PORT_D) #define CAN2_RX_PIN (GPIO_PIN_06) #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) - - #define CAN2_INT_PRIO (DDL_IRQ_PRIO_03) - #define CAN2_INT_SRC (INT_SRC_CAN2_HOST) - #define CAN2_INT_IRQn (INT005_IRQn) #endif #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h index abca2da019..b2e90e2b0f 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h @@ -12,14 +12,15 @@ #define __ADC_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { #endif #ifdef BSP_USING_ADC1 -#ifndef ADC1_CONFIG -#define ADC1_CONFIG \ +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ { \ .name = "adc1", \ .resolution = ADC_RESOLUTION_12BIT, \ @@ -36,12 +37,12 @@ extern "C" { .continue_conv_mode_enable = RT_FALSE, \ .data_reg_auto_clear = RT_TRUE, \ } -#endif /* ADC1_CONFIG */ +#endif /* ADC1_INIT_PARAMS */ #endif /* BSP_USING_ADC1 */ #ifdef BSP_USING_ADC2 -#ifndef ADC2_CONFIG -#define ADC2_CONFIG \ +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ { \ .name = "adc2", \ .resolution = ADC_RESOLUTION_12BIT, \ @@ -58,12 +59,12 @@ extern "C" { .continue_conv_mode_enable = RT_FALSE, \ .data_reg_auto_clear = RT_TRUE, \ } -#endif /* ADC2_CONFIG */ +#endif /* ADC2_INIT_PARAMS */ #endif /* BSP_USING_ADC2 */ #ifdef BSP_USING_ADC3 -#ifndef ADC3_CONFIG -#define ADC3_CONFIG \ +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ { \ .name = "adc3", \ .resolution = ADC_RESOLUTION_12BIT, \ @@ -80,7 +81,7 @@ extern "C" { .continue_conv_mode_enable = RT_FALSE, \ .data_reg_auto_clear = RT_TRUE, \ } -#endif /* ADC3_CONFIG */ +#endif /* ADC3_INIT_PARAMS */ #endif /* BSP_USING_ADC3 */ #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h index 54bbe8129f..66adf1daa9 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h @@ -12,29 +12,111 @@ #define __CAN_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { #endif #ifdef BSP_USING_CAN1 -#ifndef CAN1_CONFIG -#define CAN1_CONFIG \ +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ { \ .name = "can1", \ } -#endif /* CAN1_CONFIG */ +#endif /* CAN1_INIT_PARAMS */ #endif /* BSP_USING_CAN1 */ #ifdef BSP_USING_CAN2 -#ifndef CAN2_CONFIG -#define CAN2_CONFIG \ +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ { \ .name = "can2", \ } -#endif /* CAN2_CONFIG */ +#endif /* CAN2_INIT_PARAMS */ #endif /* BSP_USING_CAN2 */ +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + #ifdef __cplusplus } #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h index 612db91b47..b129864bdb 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h @@ -12,6 +12,7 @@ #define __DMA_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { @@ -23,8 +24,8 @@ extern "C" { #define SPI1_RX_DMA_CHANNEL DMA_CH0 #define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_IRQn INT038_IRQn -#define SPI1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO #define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif @@ -34,8 +35,8 @@ extern "C" { #define SPI1_TX_DMA_CHANNEL DMA_CH1 #define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_IRQn INT039_IRQn -#define SPI1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO #define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif @@ -45,8 +46,8 @@ extern "C" { #define SPI2_RX_DMA_CHANNEL DMA_CH2 #define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_IRQn INT040_IRQn -#define SPI2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO #define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif @@ -56,8 +57,8 @@ extern "C" { #define SPI2_TX_DMA_CHANNEL DMA_CH3 #define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_IRQn INT041_IRQn -#define SPI2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO #define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif @@ -67,8 +68,8 @@ extern "C" { #define SPI3_RX_DMA_CHANNEL DMA_CH4 #define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define SPI3_RX_DMA_IRQn INT042_IRQn -#define SPI3_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO #define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #endif @@ -78,8 +79,8 @@ extern "C" { #define SPI3_TX_DMA_CHANNEL DMA_CH5 #define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define SPI3_TX_DMA_IRQn INT043_IRQn -#define SPI3_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO #define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #endif @@ -89,8 +90,8 @@ extern "C" { #define SPI4_RX_DMA_CHANNEL DMA_CH6 #define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 -#define SPI4_RX_DMA_IRQn INT018_IRQn -#define SPI4_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO #define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 #endif @@ -100,8 +101,8 @@ extern "C" { #define SPI4_TX_DMA_CHANNEL DMA_CH7 #define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 -#define SPI4_TX_DMA_IRQn INT019_IRQn -#define SPI4_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO #define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 #endif @@ -111,8 +112,8 @@ extern "C" { #define UART1_RX_DMA_CHANNEL DMA_CH0 #define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_RX_DMA_IRQn INT044_IRQn -#define UART1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO #define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif @@ -122,8 +123,8 @@ extern "C" { #define UART1_TX_DMA_CHANNEL DMA_CH1 #define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART1_TX_DMA_IRQn INT045_IRQn -#define UART1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO #define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif @@ -133,8 +134,8 @@ extern "C" { #define UART2_RX_DMA_CHANNEL DMA_CH2 #define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART2_RX_DMA_IRQn INT046_IRQn -#define UART2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO #define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif @@ -144,8 +145,8 @@ extern "C" { #define UART2_TX_DMA_CHANNEL DMA_CH3 #define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART2_TX_DMA_IRQn INT047_IRQn -#define UART2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO #define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif @@ -155,8 +156,8 @@ extern "C" { #define UART6_RX_DMA_CHANNEL DMA_CH4 #define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART6_RX_DMA_IRQn INT048_IRQn -#define UART6_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO #define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #endif @@ -166,8 +167,8 @@ extern "C" { #define UART6_TX_DMA_CHANNEL DMA_CH5 #define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART6_TX_DMA_IRQn INT049_IRQn -#define UART6_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO #define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #endif @@ -177,8 +178,8 @@ extern "C" { #define UART7_RX_DMA_CHANNEL DMA_CH6 #define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 -#define UART7_RX_DMA_IRQn INT020_IRQn -#define UART7_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO #define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 #endif @@ -188,8 +189,8 @@ extern "C" { #define UART7_TX_DMA_CHANNEL DMA_CH7 #define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 -#define UART7_TX_DMA_IRQn INT021_IRQn -#define UART7_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO #define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h index aad1868525..f5c400142e 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h @@ -12,6 +12,7 @@ #define __ETH_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { @@ -23,8 +24,8 @@ extern "C" { #ifndef ETH_IRQ_CONFIG #define ETH_IRQ_CONFIG \ { \ - .irq_num = INT104_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ .int_src = INT_SRC_ETH_GLB_INT, \ } #endif /* ETH_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h index 066d20bc5c..25906040e5 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h @@ -12,6 +12,7 @@ #define __GPIO_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { @@ -23,8 +24,8 @@ extern "C" { #ifndef EXTINT0_IRQ_CONFIG #define EXTINT0_IRQ_CONFIG \ { \ - .irq_num = INT022_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ @@ -32,8 +33,8 @@ extern "C" { #ifndef EXTINT1_IRQ_CONFIG #define EXTINT1_IRQ_CONFIG \ { \ - .irq_num = INT023_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ @@ -41,8 +42,8 @@ extern "C" { #ifndef EXTINT2_IRQ_CONFIG #define EXTINT2_IRQ_CONFIG \ { \ - .irq_num = INT024_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ @@ -50,8 +51,8 @@ extern "C" { #ifndef EXTINT3_IRQ_CONFIG #define EXTINT3_IRQ_CONFIG \ { \ - .irq_num = INT025_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ @@ -59,8 +60,8 @@ extern "C" { #ifndef EXTINT4_IRQ_CONFIG #define EXTINT4_IRQ_CONFIG \ { \ - .irq_num = INT026_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ @@ -68,8 +69,8 @@ extern "C" { #ifndef EXTINT5_IRQ_CONFIG #define EXTINT5_IRQ_CONFIG \ { \ - .irq_num = INT027_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ @@ -77,8 +78,8 @@ extern "C" { #ifndef EXTINT6_IRQ_CONFIG #define EXTINT6_IRQ_CONFIG \ { \ - .irq_num = INT028_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ @@ -86,8 +87,8 @@ extern "C" { #ifndef EXTINT7_IRQ_CONFIG #define EXTINT7_IRQ_CONFIG \ { \ - .irq_num = INT029_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ @@ -95,8 +96,8 @@ extern "C" { #ifndef EXTINT8_IRQ_CONFIG #define EXTINT8_IRQ_CONFIG \ { \ - .irq_num = INT030_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ @@ -104,8 +105,8 @@ extern "C" { #ifndef EXTINT9_IRQ_CONFIG #define EXTINT9_IRQ_CONFIG \ { \ - .irq_num = INT031_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ @@ -113,8 +114,8 @@ extern "C" { #ifndef EXTINT10_IRQ_CONFIG #define EXTINT10_IRQ_CONFIG \ { \ - .irq_num = INT032_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ @@ -122,8 +123,8 @@ extern "C" { #ifndef EXTINT11_IRQ_CONFIG #define EXTINT11_IRQ_CONFIG \ { \ - .irq_num = INT033_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ @@ -131,8 +132,8 @@ extern "C" { #ifndef EXTINT12_IRQ_CONFIG #define EXTINT12_IRQ_CONFIG \ { \ - .irq_num = INT034_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ @@ -140,8 +141,8 @@ extern "C" { #ifndef EXTINT13_IRQ_CONFIG #define EXTINT13_IRQ_CONFIG \ { \ - .irq_num = INT035_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ @@ -149,8 +150,8 @@ extern "C" { #ifndef EXTINT14_IRQ_CONFIG #define EXTINT14_IRQ_CONFIG \ { \ - .irq_num = INT036_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ @@ -158,8 +159,8 @@ extern "C" { #ifndef EXTINT15_IRQ_CONFIG #define EXTINT15_IRQ_CONFIG \ { \ - .irq_num = INT037_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h new file mode 100644 index 0000000000..5916f917f7 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch6 */ +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch7 */ +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_ETH) +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART6_RX_USING_DMA) +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART6_TX_USING_DMA) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART7_RX_USING_DMA) +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART7_TX_USING_DMA) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT004_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_CAN1 */ + +#if defined(BSP_USING_CAN2) +#define BSP_CAN2_IRQ_NUM INT005_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_CAN2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h index da93ebdff8..c1cb687e20 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h @@ -12,6 +12,7 @@ #define __SPI_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h index 3ed0a17f50..83924088b4 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h @@ -12,6 +12,7 @@ #define __TIM_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h index dba447e691..32b6936af5 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h @@ -12,6 +12,7 @@ #define __UART_CONFIG_H__ #include +#include "irq_config.h" #ifdef __cplusplus extern "C" { @@ -27,20 +28,20 @@ extern "C" { .clock = FCG3_PERIPH_USART1, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT010_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART1_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT089_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART1_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT088_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART1_TI, \ }, \ } @@ -73,8 +74,8 @@ extern "C" { .timeout_bits = 20UL, \ .irq_config = \ { \ - .irq_num = INT006_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ .int_src = INT_SRC_USART1_RTO, \ }, \ } @@ -87,8 +88,8 @@ extern "C" { { \ .irq_config = \ { \ - .irq_num = INT086_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ .int_src = INT_SRC_USART1_TCI, \ }, \ } @@ -122,20 +123,20 @@ extern "C" { .clock = FCG3_PERIPH_USART2, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT011_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART2_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT091_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART2_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT090_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART2_TI, \ }, \ } @@ -168,8 +169,8 @@ extern "C" { .timeout_bits = 20UL, \ .irq_config = \ { \ - .irq_num = INT007_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ .int_src = INT_SRC_USART2_RTO, \ }, \ } @@ -182,8 +183,8 @@ extern "C" { { \ .irq_config = \ { \ - .irq_num = INT087_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ .int_src = INT_SRC_USART2_TCI, \ }, \ } @@ -217,20 +218,20 @@ extern "C" { .clock = FCG3_PERIPH_USART3, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT012_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART3_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT095_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART3_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT094_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART3_TI, \ }, \ } @@ -246,20 +247,20 @@ extern "C" { .clock = FCG3_PERIPH_USART4, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT013_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART4_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT097_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART4_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT096_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART4_TI, \ }, \ } @@ -275,20 +276,20 @@ extern "C" { .clock = FCG3_PERIPH_USART5, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT014_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART5_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT101_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART5_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT100_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART5_TI, \ }, \ } @@ -304,20 +305,20 @@ extern "C" { .clock = FCG3_PERIPH_USART6, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT015_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART6_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT103_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART6_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT102_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART6_TI, \ }, \ } @@ -350,8 +351,8 @@ extern "C" { .timeout_bits = 20UL, \ .irq_config = \ { \ - .irq_num = INT008_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ .int_src = INT_SRC_USART6_RTO, \ }, \ } @@ -364,8 +365,8 @@ extern "C" { { \ .irq_config = \ { \ - .irq_num = INT099_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ .int_src = INT_SRC_USART6_TCI, \ }, \ } @@ -399,20 +400,20 @@ extern "C" { .clock = FCG3_PERIPH_USART7, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT016_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART7_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT107_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART7_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT106_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART7_TI, \ }, \ } @@ -445,8 +446,8 @@ extern "C" { .timeout_bits = 20UL, \ .irq_config = \ { \ - .irq_num = INT009_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ .int_src = INT_SRC_USART7_RTO, \ }, \ } @@ -459,8 +460,8 @@ extern "C" { { \ .irq_config = \ { \ - .irq_num = INT105_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ .int_src = INT_SRC_USART6_TCI, \ }, \ } @@ -494,20 +495,20 @@ extern "C" { .clock = FCG3_PERIPH_USART8, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT017_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART8_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT109_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART8_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT108_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART8_TI, \ }, \ } @@ -523,20 +524,20 @@ extern "C" { .clock = FCG3_PERIPH_USART9, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT112_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART9_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT110_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART9_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT111_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART9_TI, \ }, \ } @@ -552,20 +553,20 @@ extern "C" { .clock = FCG3_PERIPH_USART10, \ .rxerr_irq.irq_config = \ { \ - .irq_num = INT115_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ .int_src = INT_SRC_USART7_EI, \ }, \ .rx_irq.irq_config = \ { \ - .irq_num = INT114_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ .int_src = INT_SRC_USART7_RI, \ }, \ .tx_irq.irq_config = \ { \ - .irq_num = INT113_IRQn, \ - .irq_prio = DDL_IRQ_PRIO_DEFAULT, \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ .int_src = INT_SRC_USART7_TI, \ }, \ } diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h index 4c72df565b..326fb6bcdf 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h @@ -18,14 +18,14 @@ extern "C" { #endif -#include "config/dma_config.h" -#include "config/uart_config.h" -#include "config/spi_config.h" -#include "config/adc_config.h" -#include "config/tim_config.h" -#include "config/gpio_config.h" -#include "config/eth_config.h" -#include "config/can_config.h" +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "tim_config.h" +#include "gpio_config.h" +#include "eth_config.h" +#include "can_config.h" #ifdef __cplusplus } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c index d5bef0396f..61bffd7906 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c @@ -20,44 +20,44 @@ #ifdef RT_USING_ADC typedef struct { - struct rt_adc_device adc_dev; - CM_ADC_TypeDef *hc32_adc_instance; - struct hc32_adc_init_type init; -} hc32_adc_device; + struct rt_adc_device rt_adc; + CM_ADC_TypeDef *instance; + struct adc_dev_init_params init; +} adc_device; #if !defined(BSP_USING_ADC1) && !defined(BSP_USING_ADC2) && !defined(BSP_USING_ADC3) #error "Please define at least one BSP_USING_ADCx" #endif -static hc32_adc_device g_hc32_devs[] = +static adc_device g_adc_dev_array[] = { #ifdef BSP_USING_ADC1 { {0}, CM_ADC1, - ADC1_CONFIG, + ADC1_INIT_PARAMS, }, #endif #ifdef BSP_USING_ADC2 { {0}, CM_ADC2, - ADC2_CONFIG, + ADC2_INIT_PARAMS, }, #endif #ifdef BSP_USING_ADC3 { {0}, CM_ADC3, - ADC3_CONFIG, + ADC3_INIT_PARAMS, }, #endif }; -static void internal_trigger0_set(hc32_adc_device *dev) +static void _adc_internal_trigger0_set(adc_device *p_adc_dev) { uint32_t u32TriggerSel; - rt_bool_t is_internal_trig0_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1); + rt_bool_t is_internal_trig0_enabled = (p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1); if (is_internal_trig0_enabled == RT_FALSE) { @@ -65,7 +65,7 @@ static void internal_trigger0_set(hc32_adc_device *dev) } #if defined(HC32F4A0) - switch ((rt_uint32_t)dev->hc32_adc_instance) + switch ((rt_uint32_t)p_adc_dev->instance) { case (rt_uint32_t)CM_ADC1: u32TriggerSel = AOS_ADC1_0; @@ -79,16 +79,16 @@ static void internal_trigger0_set(hc32_adc_device *dev) default: break; } - AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable); - AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable); + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable); + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable); #endif - AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig0_sel); + AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig0_sel); } -static void internal_trigger1_set(hc32_adc_device *dev) +static void _adc_internal_trigger1_set(adc_device *p_adc_dev) { uint32_t u32TriggerSel; - rt_bool_t is_internal_trig1_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1); + rt_bool_t is_internal_trig1_enabled = (p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1); if (is_internal_trig1_enabled == RT_FALSE) { @@ -96,7 +96,7 @@ static void internal_trigger1_set(hc32_adc_device *dev) } #if defined(HC32F4A0) - switch ((rt_uint32_t)dev->hc32_adc_instance) + switch ((rt_uint32_t)p_adc_dev->instance) { case (rt_uint32_t)CM_ADC1: u32TriggerSel = AOS_ADC1_1; @@ -110,22 +110,20 @@ static void internal_trigger1_set(hc32_adc_device *dev) default: break; } - AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable); - AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable); + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable); + AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable); #endif - AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig1_sel); + AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig1_sel); } -static rt_err_t hc32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +static rt_err_t _adc_enable(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) { - hc32_adc_device *adc; - - adc = rt_container_of(device, hc32_adc_device, adc_dev); - ADC_ChCmd(adc->hc32_adc_instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled); + adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc); + ADC_ChCmd(p_adc_dev->instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled); return 0; } -static rt_err_t hc32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t _adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) { rt_err_t rt_ret = RT_ERROR; @@ -134,81 +132,93 @@ static rt_err_t hc32_adc_convert(struct rt_adc_device *device, rt_uint32_t chann return -RT_EINVAL; } - hc32_adc_device *adc; - adc = rt_container_of(device, hc32_adc_device, adc_dev); - - if (adc->init.hard_trig_enable == RT_FALSE && adc->hc32_adc_instance->STR == 0) + adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc); + if (p_adc_dev->init.hard_trig_enable == RT_FALSE && p_adc_dev->instance->STR == 0) { - ADC_Start(adc->hc32_adc_instance); + ADC_Start(p_adc_dev->instance); } uint32_t start_time = rt_tick_get(); do { - if (ADC_GetStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA) == SET) + if (ADC_GetStatus(p_adc_dev->instance, ADC_FLAG_EOCA) == SET) { - ADC_ClearStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA); + ADC_ClearStatus(p_adc_dev->instance, ADC_FLAG_EOCA); rt_ret = LL_OK; break; } } - while ((rt_tick_get() - start_time) < adc->init.eoc_poll_time_max); + while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max); if (rt_ret == LL_OK) { /* Get any ADC value of sequence A channel that needed. */ - *value = ADC_GetValue(adc->hc32_adc_instance, channel); + *value = ADC_GetValue(p_adc_dev->instance, channel); } return rt_ret; } -static struct rt_adc_ops g_hc32_adc_ops = +static struct rt_adc_ops g_adc_ops = { - hc32_adc_enabled, - hc32_adc_convert, + _adc_enable, + _adc_convert, }; +static void _adc_clock_enable(void) +{ +#if defined(HC32F4A0) +#if defined(BSP_USING_ADC1) + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE); +#endif +#if defined(BSP_USING_ADC2) + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE); +#endif +#if defined(BSP_USING_ADC3) + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE); +#endif +#endif +} + extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx); -extern void rt_hw_board_adc_clock_init(void); static int rt_hw_adc_init(void) { int ret, i = 0; stc_adc_init_t stcAdcInit = {0}; int32_t ll_ret = 0; - rt_hw_board_adc_clock_init(); - uint32_t dev_cnt = sizeof(g_hc32_devs) / sizeof(g_hc32_devs[0]); + _adc_clock_enable(); + uint32_t dev_cnt = sizeof(g_adc_dev_array) / sizeof(g_adc_dev_array[0]); for (; i < dev_cnt; i++) { - ADC_DeInit(g_hc32_devs[i].hc32_adc_instance); + ADC_DeInit(g_adc_dev_array[i].instance); /* Initializes ADC. */ - stcAdcInit.u16Resolution = g_hc32_devs[i].init.resolution; - stcAdcInit.u16DataAlign = g_hc32_devs[i].init.data_align; - stcAdcInit.u16ScanMode = (g_hc32_devs[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT; - ll_ret = ADC_Init((void *)g_hc32_devs[i].hc32_adc_instance, &stcAdcInit); + stcAdcInit.u16Resolution = g_adc_dev_array[i].init.resolution; + stcAdcInit.u16DataAlign = g_adc_dev_array[i].init.data_align; + stcAdcInit.u16ScanMode = (g_adc_dev_array[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT; + ll_ret = ADC_Init((void *)g_adc_dev_array[i].instance, &stcAdcInit); if (ll_ret != LL_OK) { ret = -RT_ERROR; break; } - ADC_TriggerCmd(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, (en_functional_state_t)g_hc32_devs[i].init.hard_trig_enable); - ADC_TriggerConfig(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, g_hc32_devs[i].init.hard_trig_src); - if (g_hc32_devs[i].init.hard_trig_enable && g_hc32_devs[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) + ADC_TriggerCmd(g_adc_dev_array[i].instance, ADC_SEQ_A, (en_functional_state_t)g_adc_dev_array[i].init.hard_trig_enable); + ADC_TriggerConfig(g_adc_dev_array[i].instance, ADC_SEQ_A, g_adc_dev_array[i].init.hard_trig_src); + if (g_adc_dev_array[i].init.hard_trig_enable && g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) { - internal_trigger0_set(&g_hc32_devs[i]); - internal_trigger1_set(&g_hc32_devs[i]); + _adc_internal_trigger0_set(&g_adc_dev_array[i]); + _adc_internal_trigger1_set(&g_adc_dev_array[i]); } - rt_hw_board_adc_init((void *)g_hc32_devs[i].hc32_adc_instance); - ret = rt_hw_adc_register(&g_hc32_devs[i].adc_dev, \ - (const char *)g_hc32_devs[i].init.name, \ - &g_hc32_adc_ops, (void *)g_hc32_devs[i].hc32_adc_instance); + rt_hw_board_adc_init((void *)g_adc_dev_array[i].instance); + ret = rt_hw_adc_register(&g_adc_dev_array[i].rt_adc, \ + (const char *)g_adc_dev_array[i].init.name, \ + &g_adc_ops, (void *)g_adc_dev_array[i].instance); if (ret != RT_EOK) { /* TODO err handler */ - // LOG_E("failed register %s, err=%d", g_hc32_devs[i].name, ret); + // LOG_E("failed register %s, err=%d", g_adc_dev_array[i].name, ret); } } return ret; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.h b/bsp/hc32/libraries/hc32_drivers/drv_adc.h index c6e956382d..9bf72b6676 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.h @@ -30,7 +30,7 @@ extern "C" /******************************************************************************* * Global type definitions ('typedef') ******************************************************************************/ -struct hc32_adc_init_type +struct adc_dev_init_params { char name[8]; uint16_t resolution; /*!< Specifies the ADC resolution. diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.c b/bsp/hc32/libraries/hc32_drivers/drv_can.c index 56d603ba0c..e86b4b9742 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_can.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.c @@ -20,7 +20,9 @@ #endif #if defined (HC32F4A0) - #define FILTER_COUNT (16) + #define FILTER_COUNT (16) + #define CAN1_INT_SRC (INT_SRC_CAN1_HOST) + #define CAN2_INT_SRC (INT_SRC_CAN2_HOST) #endif enum @@ -34,69 +36,66 @@ enum CAN_INDEX_MAX, }; -struct hc32_baud_rate_tab +struct can_baud_rate_tab { rt_uint32_t baud_rate; stc_can_bit_time_config_t ll_sbt; }; -#if defined (HC32F4A0) -static const struct hc32_baud_rate_tab can_baud_rate_tab[] = +static const struct can_baud_rate_tab g_baudrate_tab[] = { - {CAN1MBaud, {2, 16, 4, 4}}, - {CAN800kBaud, {2, 20, 5, 4}}, - {CAN500kBaud, {4, 16, 4, 4}}, - {CAN250kBaud, {8, 16, 4, 4}}, - {CAN125kBaud, {16, 16, 4, 4}}, - {CAN100kBaud, {20, 16, 4, 4}}, - {CAN50kBaud, {40, 16, 4, 4}}, - {CAN20kBaud, {100, 16, 4, 4}}, - {CAN10kBaud, {200, 16, 4, 4}}, + {CAN1MBaud, CAN_BIT_TIME_CONFIG_1M_BAUD}, + {CAN800kBaud, CAN_BIT_TIME_CONFIG_800K_BAUD}, + {CAN500kBaud, CAN_BIT_TIME_CONFIG_500K_BAUD}, + {CAN250kBaud, CAN_BIT_TIME_CONFIG_250K_BAUD}, + {CAN125kBaud, CAN_BIT_TIME_CONFIG_125K_BAUD}, + {CAN100kBaud, CAN_BIT_TIME_CONFIG_100K_BAUD}, + {CAN50kBaud, CAN_BIT_TIME_CONFIG_50K_BAUD}, + {CAN20kBaud, CAN_BIT_TIME_CONFIG_20K_BAUD}, + {CAN10kBaud, CAN_BIT_TIME_CONFIG_10K_BAUD}, }; -#endif typedef struct { struct rt_can_device rt_can; - struct hc32_can_init_type init; + struct can_dev_init_params init; CM_CAN_TypeDef *instance; stc_can_init_t ll_init; - stc_can_filter_config_t *p_ll_can_filter_cfg; -} hc32_drv_can; +} can_device; -static hc32_drv_can drv_can[] = +static can_device g_can_dev_array[] = { #ifdef BSP_USING_CAN1 { {0}, - CAN1_CONFIG, + CAN1_INIT_PARAMS, .instance = CM_CAN1, }, #endif #ifdef BSP_USING_CAN2 { {0}, - CAN2_CONFIG, + CAN2_INIT_PARAMS, .instance = CM_CAN2, }, #endif }; -static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +static rt_uint32_t _get_can_baud_index(rt_uint32_t baud) { rt_uint32_t len, index; - len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + len = sizeof(g_baudrate_tab) / sizeof(g_baudrate_tab[0]); for (index = 0; index < len; index++) { - if (can_baud_rate_tab[index].baud_rate == baud) + if (g_baudrate_tab[index].baud_rate == baud) return index; } return 0; /* default baud is CAN1MBaud */ } -static rt_uint32_t get_can_work_mode(rt_uint32_t mode) +static rt_uint32_t _get_can_work_mode(rt_uint32_t mode) { rt_uint32_t work_mode; switch (mode) @@ -124,20 +123,20 @@ static rt_uint32_t get_can_work_mode(rt_uint32_t mode) static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg) { rt_uint32_t baud_index; - hc32_drv_can *hc32_can; + can_device *p_can_dev; rt_err_t rt_ret = RT_EOK; RT_ASSERT(can); RT_ASSERT(cfg); - hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); - RT_ASSERT(hc32_can); + p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); + RT_ASSERT(p_can_dev); - hc32_can->ll_init.u8WorkMode = get_can_work_mode(cfg->mode); - baud_index = get_can_baud_index(cfg->baud_rate); - hc32_can->ll_init.stcBitCfg = can_baud_rate_tab[baud_index].ll_sbt; + p_can_dev->ll_init.u8WorkMode = _get_can_work_mode(cfg->mode); + baud_index = _get_can_baud_index(cfg->baud_rate); + p_can_dev->ll_init.stcBitCfg = g_baudrate_tab[baud_index].ll_sbt; /* init can */ - int32_t ret = CAN_Init(hc32_can->instance, &hc32_can->ll_init); + int32_t ret = CAN_Init(p_can_dev->instance, &p_can_dev->ll_init); if (ret != LL_OK) { rt_ret = RT_EINVAL; @@ -146,7 +145,7 @@ static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg return rt_ret; } -static uint16_t get_filter_idx(struct rt_can_filter_config *filter_cfg) +static uint16_t _get_filter_idx(struct rt_can_filter_config *filter_cfg) { uint16_t u16FilterSelected = 0; @@ -179,13 +178,13 @@ static uint16_t get_filter_idx(struct rt_can_filter_config *filter_cfg) static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { - hc32_drv_can *hc32_can; + can_device *p_can_dev; rt_uint32_t argval; struct rt_can_filter_config *filter_cfg; RT_ASSERT(can != RT_NULL); - hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); - RT_ASSERT(hc32_can); + p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); + RT_ASSERT(p_can_dev); switch (cmd) { @@ -194,20 +193,20 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) switch (argval) { case RT_DEVICE_FLAG_INT_RX: - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_WARN, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_FULL, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_OVERRUN, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX_BUF_WARN, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX_BUF_FULL, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX_OVERRUN, DISABLE); break; case RT_DEVICE_FLAG_INT_TX: - CAN_IntCmd(hc32_can->instance, CAN_FLAG_STB_TX, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_PTB_TX, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_STB_TX, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_PTB_TX, DISABLE); break; case RT_DEVICE_CAN_INT_ERR: - CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_INT, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_INT_ARBITR_LOST, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_PASSIVE, DISABLE); - CAN_IntCmd(hc32_can->instance, CAN_INT_BUS_ERR, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_INT, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_ARBITR_LOST, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_PASSIVE, DISABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_BUS_ERR, DISABLE); break; default: break; @@ -218,20 +217,20 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) switch (argval) { case RT_DEVICE_FLAG_INT_RX: - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_WARN, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_FULL, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_OVERRUN, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX_BUF_WARN, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX_BUF_FULL, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_RX_OVERRUN, ENABLE); break; case RT_DEVICE_FLAG_INT_TX: - CAN_IntCmd(hc32_can->instance, CAN_FLAG_STB_TX, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_FLAG_PTB_TX, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_STB_TX, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_FLAG_PTB_TX, ENABLE); break; case RT_DEVICE_CAN_INT_ERR: - CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_INT, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_INT_ARBITR_LOST, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_PASSIVE, ENABLE); - CAN_IntCmd(hc32_can->instance, CAN_INT_BUS_ERR, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_INT, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_ARBITR_LOST, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_PASSIVE, ENABLE); + CAN_IntCmd(p_can_dev->instance, CAN_INT_BUS_ERR, ENABLE); break; default: break; @@ -249,17 +248,17 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) RT_ASSERT(filter_cfg->count <= FILTER_COUNT); /* get default filter */ - if (hc32_can->p_ll_can_filter_cfg) + if (p_can_dev->ll_init.pstcFilter) { - hc32_can->ll_init.u16FilterSelect = get_filter_idx(filter_cfg); + p_can_dev->ll_init.u16FilterSelect = _get_filter_idx(filter_cfg); for (int i = 0; i < filter_cfg->count; i++) { - hc32_can->p_ll_can_filter_cfg[i].u32ID = filter_cfg->items[i].id; - hc32_can->p_ll_can_filter_cfg[i].u32IDMask = filter_cfg->items[i].mask; - hc32_can->p_ll_can_filter_cfg[i].u32IDType = filter_cfg->items[i].ide; + p_can_dev->ll_init.pstcFilter[i].u32ID = filter_cfg->items[i].id; + p_can_dev->ll_init.pstcFilter[i].u32IDMask = filter_cfg->items[i].mask; + p_can_dev->ll_init.pstcFilter[i].u32IDType = filter_cfg->items[i].ide; } } - (void)CAN_Init(hc32_can->instance, &hc32_can->ll_init); + (void)CAN_Init(p_can_dev->instance, &p_can_dev->ll_init); break; } case RT_CAN_CMD_SET_MODE: @@ -271,10 +270,10 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { return -RT_ERROR; } - if (argval != hc32_can->rt_can.config.mode) + if (argval != p_can_dev->rt_can.config.mode) { - hc32_can->rt_can.config.mode = argval; - _can_config(can, &hc32_can->rt_can.config); + p_can_dev->rt_can.config.mode = argval; + _can_config(can, &p_can_dev->rt_can.config); } break; case RT_CAN_CMD_SET_BAUD: @@ -291,10 +290,10 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { return -RT_ERROR; } - if (argval != hc32_can->rt_can.config.baud_rate) + if (argval != p_can_dev->rt_can.config.baud_rate) { - hc32_can->rt_can.config.baud_rate = argval; - _can_config(can, &hc32_can->rt_can.config); + p_can_dev->rt_can.config.baud_rate = argval; + _can_config(can, &p_can_dev->rt_can.config); } break; case RT_CAN_CMD_SET_PRIV: @@ -304,21 +303,21 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { return -RT_ERROR; } - if (argval != hc32_can->rt_can.config.privmode) + if (argval != p_can_dev->rt_can.config.privmode) { - hc32_can->rt_can.config.privmode = argval; - return _can_config(can, &hc32_can->rt_can.config); + p_can_dev->rt_can.config.privmode = argval; + return _can_config(can, &p_can_dev->rt_can.config); } break; case RT_CAN_CMD_GET_STATUS: { struct rt_can_status *rt_can_stat = (struct rt_can_status *)arg; stc_can_error_info_t stcErr = {0}; - CAN_GetErrorInfo(hc32_can->instance, &stcErr); + CAN_GetErrorInfo(p_can_dev->instance, &stcErr); rt_can_stat->rcverrcnt = stcErr.u8RxErrorCount; rt_can_stat->snderrcnt = stcErr.u8TxErrorCount; rt_can_stat->lasterrtype = stcErr.u8ErrorType; - rt_can_stat->errcode = CAN_GetStatusValue(hc32_can->instance); + rt_can_stat->errcode = CAN_GetStatusValue(p_can_dev->instance); } break; @@ -336,10 +335,9 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t int32_t ll_ret; RT_ASSERT(can != RT_NULL); - hc32_drv_can *hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); - RT_ASSERT(hc32_can); + can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); + RT_ASSERT(p_can_dev); - /*check select mailbox is empty */ stc_tx_frame.u32ID = pmsg->id; if (RT_CAN_DTR == pmsg->rtr) { @@ -353,14 +351,14 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t stc_tx_frame.DLC = pmsg->len & 0x0FU; /* Set up the data field */ rt_memcpy(&stc_tx_frame.au8Data, pmsg->data, sizeof(stc_tx_frame.au8Data)); - - ll_ret = CAN_FillTxFrame(hc32_can->instance, CAN_TX_BUF_PTB, &stc_tx_frame); + ll_ret = CAN_FillTxFrame(p_can_dev->instance, CAN_TX_BUF_PTB, &stc_tx_frame); if (ll_ret != LL_OK) { return RT_ERROR; } /* Request transmission */ - CAN_StartTx(hc32_can->instance, CAN_TX_REQ_PTB); + CAN_StartTx(p_can_dev->instance, CAN_TX_REQ_PTB); + return RT_EOK; } @@ -371,15 +369,15 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) stc_can_rx_frame_t ll_rx_frame; RT_ASSERT(can != RT_NULL); - hc32_drv_can *hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can); - RT_ASSERT(hc32_can); + can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); + RT_ASSERT(p_can_dev); pmsg = (struct rt_can_msg *) buf; - /* get data */ - ll_ret = CAN_GetRxFrame(hc32_can->instance, &ll_rx_frame); + ll_ret = CAN_GetRxFrame(p_can_dev->instance, &ll_rx_frame); if (ll_ret != LL_OK) return -RT_ERROR; + /* get id */ if (CAN_ID_STD == ll_rx_frame.IDE) { @@ -416,124 +414,156 @@ static const struct rt_can_ops _can_ops = _can_recvmsg, }; -static void can_isr(hc32_drv_can *hc32_can) +static void _can_isr(can_device *p_can_dev) { stc_can_error_info_t stcErr; - (void)CAN_GetErrorInfo(hc32_can->instance, &stcErr); + (void)CAN_GetErrorInfo(p_can_dev->instance, &stcErr); - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_BUS_OFF) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_BUS_OFF) == SET) { - DDL_Printf("BUS OFF.\r\n"); + /* BUS OFF. */ } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_OVF) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_OVF) == SET) { - DDL_Printf("RX overflow.\r\n"); - rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_RXOF_IND); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_OVF); + /* RX overflow. */ + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_RXOF_IND); + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_OVF); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TX_BUF_FULL) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_TX_BUF_FULL) == SET) { - DDL_Printf("TX buffer full.\r\n"); + /* TX buffer full. */ } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TX_ABORTED) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_TX_ABORTED) == SET) { - DDL_Printf("TX aborted.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_TX_ABORTED); + /* TX aborted. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_TX_ABORTED); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_ARBITR_LOST) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) == SET) { - rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_FAIL); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_ARBITR_LOST); + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_FAIL); + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_STB_TX) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_STB_TX) == SET) { - DDL_Printf("STB transmitted.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_STB_TX); - rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_DONE); + /* STB transmitted. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_STB_TX); + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_DONE); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_PTB_TX) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_PTB_TX) == SET) { - DDL_Printf("PTB transmitted.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_PTB_TX); - rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_DONE); + /* PTB transmitted. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_PTB_TX); + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_DONE); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX) == SET) { - /* Received frame can be read here. */ - DDL_Printf("Received a frame.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX); - rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_RX_IND); + /* Received a frame. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX); + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_RX_IND); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_WARN) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_WARN) == SET) { - /* Received frames can be read here. */ - DDL_Printf("RX buffer warning.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_WARN); + /* RX buffer warning. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_WARN); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_FULL) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_FULL) == SET) { - /* Received frames can be read here. */ - DDL_Printf("RX buffer full.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_FULL); + /* RX buffer full. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_FULL); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_OVERRUN) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_OVERRUN) == SET) { - DDL_Printf("RX buffer overrun.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_OVERRUN); + /* RX buffer overrun. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_OVERRUN); } - if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TEC_REC_WARN) == SET) + if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_TEC_REC_WARN) == SET) { - DDL_Printf("TEC or REC reached warning limit.\r\n"); - CAN_ClearStatus(hc32_can->instance, CAN_FLAG_TEC_REC_WARN); + /* TEC or REC reached warning limit. */ + CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_TEC_REC_WARN); } - if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_TIME_TRIG) == SET) + if (CAN_TTC_GetStatus(p_can_dev->instance, CAN_TTC_FLAG_TIME_TRIG) == SET) { - DDL_Printf("Time trigger interrupt.\r\n"); - CAN_TTC_ClearStatus(hc32_can->instance, CAN_TTC_FLAG_TIME_TRIG); + /* Time trigger interrupt. */ + CAN_TTC_ClearStatus(p_can_dev->instance, CAN_TTC_FLAG_TIME_TRIG); } - if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_TRIG_ERR) == SET) + if (CAN_TTC_GetStatus(p_can_dev->instance, CAN_TTC_FLAG_TRIG_ERR) == SET) { - DDL_Printf("Trigger error interrupt.\r\n"); + /* Trigger error interrupt. */ } - if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_WATCH_TRIG) == SET) + if (CAN_TTC_GetStatus(p_can_dev->instance, CAN_TTC_FLAG_WATCH_TRIG) == SET) { - DDL_Printf("Watch trigger interrupt.\r\n"); - CAN_TTC_ClearStatus(hc32_can->instance, CAN_TTC_FLAG_WATCH_TRIG); + /* Watch trigger interrupt. */ + CAN_TTC_ClearStatus(p_can_dev->instance, CAN_TTC_FLAG_WATCH_TRIG); } } #if defined(BSP_USING_CAN1) -static void can1_irq_handler(void) +static void _can1_irq_handler(void) { rt_interrupt_enter(); - can_isr(&drv_can[CAN1_INDEX]); + _can_isr(&g_can_dev_array[CAN1_INDEX]); rt_interrupt_leave(); } #endif #if defined(BSP_USING_CAN2) -static void can2_irq_handler(void) +static void _can2_irq_handler(void) { rt_interrupt_enter(); - can_isr(&drv_can[CAN2_INDEX]); + _can_isr(&g_can_dev_array[CAN2_INDEX]); rt_interrupt_leave(); } #endif +static void _can_clock_enable(void) +{ +#if defined(HC32F4A0) +#if defined(BSP_USING_CAN1) + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE); +#endif +#if defined(BSP_USING_CAN2) + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN2, ENABLE); +#endif +#endif +} + +static void _can_irq_config(void) +{ + struct hc32_irq_config irq_config; +#if defined(BSP_USING_CAN1) + irq_config.irq_num = BSP_CAN1_IRQ_NUM; + irq_config.int_src = CAN1_INT_SRC; + irq_config.irq_prio = BSP_CAN1_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + _can1_irq_handler, + RT_TRUE); +#endif +#if defined(BSP_USING_CAN2) + irq_config.irq_num = BSP_CAN2_IRQ_NUM; + irq_config.int_src = CAN2_INT_SRC; + irq_config.irq_prio = BSP_CAN2_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + _can2_irq_handler, + RT_TRUE); +#endif +} + extern rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx); extern void CanPhyEnable(void); int rt_hw_can_init(void) @@ -545,63 +575,33 @@ int rt_hw_can_init(void) rt_can_config.maxhdr = FILTER_COUNT; #endif - struct hc32_irq_config irq_config; -#if defined(BSP_USING_CAN1) - irq_config.irq_num = CAN1_INT_IRQn; - irq_config.int_src = CAN1_INT_SRC; - irq_config.irq_prio = CAN1_INT_PRIO; - /* register interrupt */ - hc32_install_irq_handler(&irq_config, - can1_irq_handler, - RT_TRUE); -#endif -#if defined(BSP_USING_CAN2) - irq_config.irq_num = CAN2_INT_IRQn; - irq_config.int_src = CAN2_INT_SRC; - irq_config.irq_prio = CAN2_INT_PRIO; - /* register interrupt */ - hc32_install_irq_handler(&irq_config, - can2_irq_handler, - RT_TRUE); -#endif - -#if defined(HC32F4A0) -#if defined(BSP_USING_CAN1) - CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); - FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE); -#endif -#if defined(BSP_USING_CAN2) - CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); - FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN2, ENABLE); -#endif -#endif - + _can_irq_config(); + _can_clock_enable(); CanPhyEnable(); int result = RT_EOK; uint32_t i = 0; for (; i < CAN_INDEX_MAX; i++) { - if (drv_can[i].p_ll_can_filter_cfg == RT_NULL) + CAN_StructInit(&g_can_dev_array[i].ll_init); + if (g_can_dev_array[i].ll_init.pstcFilter == RT_NULL) { - drv_can[i].p_ll_can_filter_cfg = (stc_can_filter_config_t *)rt_malloc(sizeof(stc_can_filter_config_t) * FILTER_COUNT); + g_can_dev_array[i].ll_init.pstcFilter = (stc_can_filter_config_t *)rt_malloc(sizeof(stc_can_filter_config_t) * FILTER_COUNT); } - RT_ASSERT((drv_can[i].p_ll_can_filter_cfg != RT_NULL)); + RT_ASSERT((g_can_dev_array[i].ll_init.pstcFilter != RT_NULL)); - rt_memset(drv_can[i].p_ll_can_filter_cfg, 0, sizeof(stc_can_filter_config_t) * FILTER_COUNT); - drv_can[i].p_ll_can_filter_cfg[0].u32ID = 0U; - drv_can[i].p_ll_can_filter_cfg[0].u32IDMask = 0x1FFFFFFF; - drv_can[i].p_ll_can_filter_cfg[0].u32IDType = CAN_ID_STD; - CAN_StructInit(&drv_can[i].ll_init); - drv_can[i].ll_init.pstcFilter = &drv_can[i].p_ll_can_filter_cfg[0]; - drv_can[i].ll_init.u16FilterSelect = CAN_FILTER1; - drv_can[i].rt_can.config = rt_can_config; + rt_memset(g_can_dev_array[i].ll_init.pstcFilter, 0, sizeof(stc_can_filter_config_t) * FILTER_COUNT); + g_can_dev_array[i].ll_init.pstcFilter[0].u32ID = 0U; + g_can_dev_array[i].ll_init.pstcFilter[0].u32IDMask = 0x1FFFFFFF; + g_can_dev_array[i].ll_init.pstcFilter[0].u32IDType = CAN_ID_STD; + g_can_dev_array[i].ll_init.u16FilterSelect = CAN_FILTER1; + g_can_dev_array[i].rt_can.config = rt_can_config; /* register CAN1 device */ - rt_hw_board_can_init(drv_can[i].instance); - rt_hw_can_register(&drv_can[i].rt_can, - drv_can[i].init.name, + rt_hw_board_can_init(g_can_dev_array[i].instance); + rt_hw_can_register(&g_can_dev_array[i].rt_can, + g_can_dev_array[i].init.name, &_can_ops, - &drv_can[i]); + &g_can_dev_array[i]); } return result; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.h b/bsp/hc32/libraries/hc32_drivers/drv_can.h index 2a9f461c3d..e1b11b4605 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_can.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.h @@ -21,8 +21,8 @@ extern "C" { -/* stm32 can device */ -struct hc32_can_init_type +/* hc32 can device */ +struct can_dev_init_params { char *name; };