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[nxp] format imxrt libraries

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This commit is contained in:
Meco Man
2023-02-10 19:13:40 -05:00
committed by guo
parent 2d09749086
commit da533d113e
227 changed files with 542 additions and 542 deletions
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bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/arm_math.h
+1 -1
View File
@@ -77,7 +77,7 @@
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
* For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
* Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
*
*
*
* Examples
* --------
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armcc.h
+3 -3
View File
@@ -58,9 +58,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
@@ -448,7 +448,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armclang.h
+4 -4
View File
@@ -43,9 +43,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
@@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
@@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_gcc.h
+4 -4
View File
@@ -46,9 +46,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
@@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
@@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mbl.h
+1 -1
View File
@@ -59,7 +59,7 @@
\ingroup Cortex_ARMv8MBL
@{
*/
#include "cmsis_version.h"
/* CMSIS definitions */
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mml.h
+9 -9
View File
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS Armv8MML definitions */
#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@@ -90,12 +90,12 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -113,7 +113,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -130,18 +130,18 @@
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -159,12 +159,12 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0.h
+1 -1
View File
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0plus.h
+1 -1
View File
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm3.h
+1 -1
View File
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm33.h
+5 -5
View File
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM33 definitions */
#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@@ -90,7 +90,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -113,7 +113,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -136,7 +136,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -159,7 +159,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm4.h
+1 -1
View File
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
/* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv7.h
+10 -10
View File
@@ -21,13 +21,13 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
@@ -60,7 +60,7 @@
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define ARM_MPU_AP_NONE 0U
#define ARM_MPU_AP_NONE 0U
#define ARM_MPU_AP_PRIV 1U
#define ARM_MPU_AP_URO 2U
#define ARM_MPU_AP_FULL 3U
@@ -79,7 +79,7 @@
/**
* MPU Region Attribute and Size Register Value
*
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -88,7 +88,7 @@
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
@@ -108,7 +108,7 @@ typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
@@ -146,7 +146,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
@@ -157,7 +157,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
@@ -173,7 +173,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
@@ -183,7 +183,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv8.h
+14 -14
View File
@@ -108,7 +108,7 @@ typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
@@ -171,11 +171,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
@@ -222,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
@@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
@@ -244,7 +244,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
@@ -255,10 +255,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
@@ -270,7 +270,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
@@ -282,7 +282,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
@@ -291,7 +291,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
@@ -302,7 +302,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
@@ -312,7 +312,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
@@ -323,7 +323,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/tz_context.h
+9 -9
View File
@@ -30,41 +30,41 @@
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_AOI_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright 2017 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h
+7 -7
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_H_
@@ -99,7 +99,7 @@ typedef struct _l2cache_config
{
/* ------------------------ l2 cachec basic settings ---------------------------- */
l2cache_way_num_t wayNum; /*!< The number of ways. */
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */
/* ------------------------ tag/data ram latency settings ----------------------- */
L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
@@ -109,7 +109,7 @@ typedef struct _l2cache_config
/* ------------------------ Non-secure access settings -------------------------- */
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
/* ------------------------ other settings -------------------------------------- */
l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */
l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */
} l2cache_config_t;
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
@@ -157,7 +157,7 @@ static inline void L1CACHE_InvalidateICache(void)
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 I-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
@@ -214,7 +214,7 @@ static inline void L1CACHE_CleanInvalidateDCache(void)
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 D-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
@@ -280,7 +280,7 @@ void L2CACHE_Init(l2cache_config_t *config);
/*!
* @brief Gets an available default settings for the cache controller.
*
* This function initializes the cache controller configuration structure with default settings.
* This function initializes the cache controller configuration structure with default settings.
* The default values are:
* @code
* config->waysNum = kL2CACHE_8ways;
@@ -290,7 +290,7 @@ void L2CACHE_Init(l2cache_config_t *config);
* config->istrPrefetchEnable = false;
* config->dataPrefetchEnable = false;
* config->nsLockdownEnable = false;
* config->writeAlloc = kL2CACHE_UseAwcache;
* config->writeAlloc = kL2CACHE_UseAwcache;
* @endcode
* @param config Pointer to the configuration structure.
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.h
+8 -8
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -126,7 +126,7 @@ enum _status_groups
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
@@ -371,7 +371,7 @@ _Pragma("diag_suppress=Pm120")
#define AT_QUICKACCESS_SECTION_DATA(func) func
#else
#error Toolchain not supported.
#endif
#endif
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
/* @} */
@@ -525,7 +525,7 @@ _Pragma("diag_suppress=Pm120")
*/
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
@@ -566,15 +566,15 @@ _Pragma("diag_suppress=Pm120")
* @param size The length required to malloc.
* @param alignbytes The alignment size.
* @retval The allocated memory.
*/
*/
void *SDK_Malloc(size_t size, size_t alignbytes);
/*!
* @brief Free memory.
*
* @param ptr The memory to be release.
*/
void SDK_Free(void *ptr);
*/
void SDK_Free(void *ptr);
#if defined(__cplusplus)
}
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2017, NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright 2017 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2017, NXP Semiconductors, Inc.
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enc.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enet.h
+3 -3
View File
@@ -681,9 +681,9 @@ void ENET_GetDefaultConfig(enet_config_t *config);
* The buffer configuration should be prepared for ENET Initialization.
* It is the start address of "ringNum" enet_buffer_config structures.
* To support added multi-ring features in some soc and compatible with the previous
* enet driver version. For single ring supported, this bufferConfig is a buffer
* configure structure pointer, for multi-ring supported and used case, this bufferConfig
* pointer should be a buffer configure structure array pointer.
* enet driver version. For single ring supported, this bufferConfig is a buffer
* configure structure pointer, for multi-ring supported and used case, this bufferConfig
* pointer should be a buffer configure structure array pointer.
* @param macAddr ENET mac address of Ethernet device. This MAC address should be
* provided.
* @param srcClock_Hz The internal module clock source for MII clock.
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_ewm.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EWM_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi_edma.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_SPI_EDMA_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_uart_edma.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_FLEXIO_UART_EDMA_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.c
+1 -1
View File
@@ -169,7 +169,7 @@ void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
* is needed.
* param config allocate configuration.
* retval kStatus_InvalidArgument the argument is invalid
* kStatus_Success allocate success
* kStatus_Success allocate success
*/
status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
{
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.h
+1 -1
View File
@@ -249,7 +249,7 @@ static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable
* is needed.
* @param config allocate configuration.
* @retval kStatus_InvalidArgument the argument is invalid
* kStatus_Success allocate success
* kStatus_Success allocate success
*/
status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config);
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpc.h
+1 -1
View File
@@ -3,7 +3,7 @@
* Copyright 2016 NXP
* All rights reserved.
*
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpt.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_kpp.h
+1 -1
View File
@@ -1,7 +1,7 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_KPP_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_lpi2c_edma.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LPI2C_EDMA_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pmu.h
+3 -3
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PMU_H_
@@ -108,10 +108,10 @@ extern "C" {
*/
/*!
* @brief Get PMU status flags.
* @brief Get PMU status flags.
*
* @param base PMU peripheral base address.
* @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok
* @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok
* and brownout output of 1P1,3P0 and 2P5 is detected.
*/
uint32_t PMU_GetStatusFlags(PMU_Type *base);
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pwm.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PWM_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_qtmr.h
+1 -1
View File
@@ -1,7 +1,7 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_QTMR_H_
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_snvs_lp.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2017, NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_src.h
+3 -3
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -86,8 +86,8 @@ enum _src_reset_status_flags
power-on detection logic. */
#endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software
setting of SYSRESETREQ bit in Application Interrupt and
kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software
setting of SYSRESETREQ bit in Application Interrupt and
Reset Control Register of the ARM core. */
#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbara.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbarb.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/project_template/pin_mux.c
+2 -2
View File
@@ -24,10 +24,10 @@ processor_version: 0.0.11
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_notifier.h
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_sbrk.c
+1 -1
View File
@@ -2,7 +2,7 @@
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if defined(__GNUC__)
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.c
+5 -5
View File
@@ -18,8 +18,8 @@
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.ivt"
#endif
/*************************************
* IVT Data
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
@@ -37,14 +37,14 @@ const ivt image_vector_table = {
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.boot_data"
#endif
/*************************************
* Boot Data
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
0xFFFFFFFF /* empty - extra data word */
};
#endif
bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.h
+13 -13
View File
@@ -17,8 +17,8 @@
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*************************************
* IVT Data
/*************************************
* IVT Data
*************************************/
typedef struct _ivt_ {
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
@@ -56,18 +56,18 @@ typedef struct _ivt_ {
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
/* IVT header */
/* IVT header */
#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */
#define IVT_SIZE 0x2000
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
/* Set resume entry */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t __Vectors[];
extern uint32_t Image$$RW_m_config_text$$Base[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base)
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base)
#elif defined(__MCUXPRESSO)
extern uint32_t __Vectors[];
extern uint32_t __boot_hdr_start__[];
@@ -76,13 +76,13 @@ typedef struct _ivt_ {
#elif defined(__ICCARM__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t m_boot_hdr_conf_start[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start)
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start)
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __FLASH_BASE[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
#define FLASH_BASE ((uint32_t)__FLASH_BASE)
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
#define FLASH_BASE ((uint32_t)__FLASH_BASE)
#endif
#define DCD_ADDRESS dcd_data
@@ -90,14 +90,14 @@ typedef struct _ivt_ {
#define CSF_ADDRESS 0
#define IVT_RSVD (uint32_t)(0x00000000)
/*************************************
* Boot Data
/*************************************
* Boot Data
*************************************/
typedef struct _boot_data_ {
uint32_t start; /* boot start location */
uint32_t size; /* size */
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
uint32_t placeholder; /* placehoder to make even 0x10 size */
uint32_t placeholder; /* placehoder to make even 0x10 size */
}BOOT_DATA_T;
#define FLASH_SIZE BOARD_FLASH_SIZE
bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/arm_math.h
+1 -1
View File
@@ -77,7 +77,7 @@
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
* For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
* Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
*
*
*
* Examples
* --------
bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armcc.h
+3 -3
View File
@@ -62,9 +62,9 @@
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
@@ -472,7 +472,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

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