From da533d113ec9302997499f7314384d0ade5858c8 Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Fri, 10 Feb 2023 19:13:40 -0500 Subject: [PATCH] [nxp] format imxrt libraries --- .../MIMXRT1050/CMSIS/Include/arm_math.h | 2 +- .../MIMXRT1050/CMSIS/Include/cmsis_armcc.h | 6 +-- .../MIMXRT1050/CMSIS/Include/cmsis_armclang.h | 8 ++-- .../MIMXRT1050/CMSIS/Include/cmsis_gcc.h | 8 ++-- .../MIMXRT1050/CMSIS/Include/core_armv8mbl.h | 2 +- .../MIMXRT1050/CMSIS/Include/core_armv8mml.h | 18 ++++---- .../MIMXRT1050/CMSIS/Include/core_cm0.h | 2 +- .../MIMXRT1050/CMSIS/Include/core_cm0plus.h | 2 +- .../MIMXRT1050/CMSIS/Include/core_cm3.h | 2 +- .../MIMXRT1050/CMSIS/Include/core_cm33.h | 10 ++-- .../MIMXRT1050/CMSIS/Include/core_cm4.h | 2 +- .../MIMXRT1050/CMSIS/Include/mpu_armv7.h | 20 ++++---- .../MIMXRT1050/CMSIS/Include/mpu_armv8.h | 28 +++++------ .../MIMXRT1050/CMSIS/Include/tz_context.h | 18 ++++---- .../MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h | 14 +++--- .../MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h | 2 +- .../MIMXRT1052/drivers/fsl_common.h | 16 +++---- .../MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h | 2 +- .../MIMXRT1052/drivers/fsl_dmamux.h | 2 +- .../MIMXRT1052/drivers/fsl_elcdif.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_enc.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_enet.h | 6 +-- .../MIMXRT1050/MIMXRT1052/drivers/fsl_ewm.h | 2 +- .../MIMXRT1052/drivers/fsl_flexio.h | 2 +- .../MIMXRT1052/drivers/fsl_flexio_spi.h | 2 +- .../MIMXRT1052/drivers/fsl_flexio_spi_edma.h | 2 +- .../MIMXRT1052/drivers/fsl_flexio_uart_edma.h | 2 +- .../MIMXRT1052/drivers/fsl_flexram.c | 2 +- .../MIMXRT1052/drivers/fsl_flexram.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_gpc.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_gpt.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_kpp.h | 2 +- .../MIMXRT1052/drivers/fsl_lpi2c_edma.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_pmu.h | 6 +-- .../MIMXRT1050/MIMXRT1052/drivers/fsl_pwm.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_qtmr.h | 2 +- .../MIMXRT1052/drivers/fsl_snvs_lp.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_src.h | 6 +-- .../MIMXRT1050/MIMXRT1052/drivers/fsl_xbara.h | 2 +- .../MIMXRT1050/MIMXRT1052/drivers/fsl_xbarb.h | 2 +- .../MIMXRT1052/project_template/pin_mux.c | 4 +- .../MIMXRT1052/utilities/fsl_notifier.h | 2 +- .../MIMXRT1052/utilities/fsl_sbrk.c | 2 +- .../MIMXRT1052/xip/fsl_flexspi_nor_boot.c | 10 ++-- .../MIMXRT1052/xip/fsl_flexspi_nor_boot.h | 26 +++++------ .../MIMXRT1060/CMSIS/Include/arm_math.h | 2 +- .../MIMXRT1060/CMSIS/Include/cmsis_armcc.h | 6 +-- .../MIMXRT1060/CMSIS/Include/cmsis_armclang.h | 4 +- .../CMSIS/Include/cmsis_armclang_ltm.h | 4 +- .../MIMXRT1060/CMSIS/Include/cmsis_gcc.h | 24 +++++----- .../MIMXRT1060/CMSIS/Include/cmsis_iccarm.h | 2 +- .../MIMXRT1060/CMSIS/Include/core_armv8mbl.h | 2 +- .../MIMXRT1060/CMSIS/Include/core_armv8mml.h | 18 ++++---- .../MIMXRT1060/CMSIS/Include/core_cm0.h | 2 +- .../MIMXRT1060/CMSIS/Include/core_cm0plus.h | 2 +- .../MIMXRT1060/CMSIS/Include/core_cm3.h | 2 +- .../MIMXRT1060/CMSIS/Include/core_cm33.h | 10 ++-- .../MIMXRT1060/CMSIS/Include/core_cm4.h | 2 +- .../MIMXRT1060/CMSIS/Include/core_cm7.h | 12 ++--- .../MIMXRT1060/CMSIS/Include/mpu_armv7.h | 30 ++++++------ .../MIMXRT1060/CMSIS/Include/mpu_armv8.h | 28 +++++------ .../MIMXRT1060/CMSIS/Include/tz_context.h | 18 ++++---- .../MIMXRT1060/MIMXRT1060/drivers/fsl_bee.h | 4 +- .../MIMXRT1060/drivers/fsl_flexram_allocate.c | 2 +- .../MIMXRT1060/drivers/fsl_flexram_allocate.h | 2 +- .../MIMXRT1060/project_template/pin_mux.c | 4 +- .../debug_console/fsl_debug_console_conf.h | 2 +- .../MIMXRT1064/CMSIS/Include/arm_math.h | 2 +- .../MIMXRT1064/CMSIS/Include/cmsis_armcc.h | 6 +-- .../MIMXRT1064/CMSIS/Include/cmsis_armclang.h | 8 ++-- .../MIMXRT1064/CMSIS/Include/cmsis_gcc.h | 8 ++-- .../MIMXRT1064/CMSIS/Include/core_armv8mbl.h | 2 +- .../MIMXRT1064/CMSIS/Include/core_armv8mml.h | 18 ++++---- .../MIMXRT1064/CMSIS/Include/core_cm0.h | 2 +- .../MIMXRT1064/CMSIS/Include/core_cm0plus.h | 2 +- .../MIMXRT1064/CMSIS/Include/core_cm3.h | 2 +- .../MIMXRT1064/CMSIS/Include/core_cm33.h | 10 ++-- .../MIMXRT1064/CMSIS/Include/core_cm4.h | 2 +- .../MIMXRT1064/CMSIS/Include/mpu_armv7.h | 20 ++++---- .../MIMXRT1064/CMSIS/Include/mpu_armv8.h | 28 +++++------ .../MIMXRT1064/CMSIS/Include/tz_context.h | 18 ++++---- .../MIMXRT1064/drivers/fsl_aipstz.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_bee.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_bee.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_cache.c | 16 +++---- .../MIMXRT1064/MIMXRT1064/drivers/fsl_cache.h | 14 +++--- .../MIMXRT1064/MIMXRT1064/drivers/fsl_clock.c | 8 ++-- .../MIMXRT1064/MIMXRT1064/drivers/fsl_clock.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.h | 2 +- .../MIMXRT1064/drivers/fsl_common.h | 14 +++--- .../MIMXRT1064/MIMXRT1064/drivers/fsl_csi.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.h | 2 +- .../MIMXRT1064/drivers/fsl_dmamux.c | 2 +- .../MIMXRT1064/drivers/fsl_dmamux.h | 2 +- .../MIMXRT1064/drivers/fsl_elcdif.c | 2 +- .../MIMXRT1064/drivers/fsl_elcdif.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_enc.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_enc.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_enet.c | 46 +++++++++---------- .../MIMXRT1064/MIMXRT1064/drivers/fsl_enet.h | 6 +-- .../MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.h | 2 +- .../MIMXRT1064/drivers/fsl_flexio.c | 2 +- .../MIMXRT1064/drivers/fsl_flexio.h | 2 +- .../MIMXRT1064/drivers/fsl_flexio_spi.c | 2 +- .../MIMXRT1064/drivers/fsl_flexio_spi.h | 2 +- .../MIMXRT1064/drivers/fsl_flexio_spi_edma.c | 2 +- .../MIMXRT1064/drivers/fsl_flexio_spi_edma.h | 2 +- .../MIMXRT1064/drivers/fsl_flexio_uart.c | 2 +- .../MIMXRT1064/drivers/fsl_flexio_uart.h | 2 +- .../MIMXRT1064/drivers/fsl_flexio_uart_edma.c | 2 +- .../MIMXRT1064/drivers/fsl_flexio_uart_edma.h | 2 +- .../MIMXRT1064/drivers/fsl_flexram.c | 2 +- .../MIMXRT1064/drivers/fsl_flexram.h | 4 +- .../MIMXRT1064/drivers/fsl_flexspi.c | 2 +- .../MIMXRT1064/drivers/fsl_flexspi.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.h | 2 +- .../MIMXRT1064/drivers/fsl_iomuxc.h | 30 ++++++------ .../MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.c | 4 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.h | 2 +- .../MIMXRT1064/drivers/fsl_lpi2c_edma.h | 2 +- .../MIMXRT1064/drivers/fsl_lpi2c_freertos.c | 2 +- .../MIMXRT1064/drivers/fsl_lpi2c_freertos.h | 2 +- .../MIMXRT1064/drivers/fsl_lpspi_freertos.c | 2 +- .../MIMXRT1064/drivers/fsl_lpspi_freertos.h | 2 +- .../MIMXRT1064/drivers/fsl_lpuart_edma.h | 2 +- .../MIMXRT1064/drivers/fsl_lpuart_freertos.c | 2 +- .../MIMXRT1064/drivers/fsl_lpuart_freertos.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.c | 8 ++-- .../MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.h | 2 +- .../MIMXRT1064/drivers/fsl_rtwdog.c | 4 +- .../MIMXRT1064/drivers/fsl_rtwdog.h | 2 +- .../MIMXRT1064/drivers/fsl_snvs_hp.c | 2 +- .../MIMXRT1064/drivers/fsl_snvs_lp.c | 2 +- .../MIMXRT1064/drivers/fsl_snvs_lp.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_spdif.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_src.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_src.h | 6 +-- .../MIMXRT1064/MIMXRT1064/drivers/fsl_trng.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_trng.h | 4 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.c | 10 ++-- .../MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.h | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.c | 2 +- .../MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.h | 2 +- .../MIMXRT1064/project_template/board.c | 4 +- .../MIMXRT1064/project_template/board.h | 6 +-- .../MIMXRT1064/project_template/pin_mux.c | 4 +- .../MIMXRT1064/utilities/fsl_assert.c | 2 +- .../MIMXRT1064/utilities/fsl_notifier.c | 2 +- .../MIMXRT1064/utilities/fsl_notifier.h | 2 +- .../MIMXRT1064/utilities/fsl_sbrk.c | 2 +- .../MIMXRT1064/utilities/fsl_shell.c | 2 +- .../MIMXRT1064/utilities/fsl_shell.h | 2 +- .../MIMXRT1064/utilities/io/fsl_io.h | 4 +- .../MIMXRT1064/utilities/log/fsl_log.h | 2 +- .../MIMXRT1064/xip/fsl_flexspi_nor_boot.c | 10 ++-- .../MIMXRT1064/xip/fsl_flexspi_nor_boot.h | 24 +++++----- bsp/imxrt/libraries/drivers/bsp_wm8960.c | 2 +- bsp/imxrt/libraries/drivers/bsp_wm8960.h | 2 +- bsp/imxrt/libraries/drivers/drv_adc.c | 2 +- bsp/imxrt/libraries/drivers/drv_adc.h | 2 +- bsp/imxrt/libraries/drivers/drv_can.c | 2 +- bsp/imxrt/libraries/drivers/drv_can.h | 2 +- bsp/imxrt/libraries/drivers/drv_common.c | 2 +- bsp/imxrt/libraries/drivers/drv_eth.c | 2 +- bsp/imxrt/libraries/drivers/drv_flexspi.c | 2 +- bsp/imxrt/libraries/drivers/drv_gpio.c | 2 +- bsp/imxrt/libraries/drivers/drv_gpio.h | 2 +- bsp/imxrt/libraries/drivers/drv_hwtimer.c | 2 +- bsp/imxrt/libraries/drivers/drv_hwtimer.h | 2 +- bsp/imxrt/libraries/drivers/drv_i2c.c | 2 +- bsp/imxrt/libraries/drivers/drv_i2c.h | 2 +- bsp/imxrt/libraries/drivers/drv_ksz8081.c | 2 +- bsp/imxrt/libraries/drivers/drv_lcd.c | 2 +- bsp/imxrt/libraries/drivers/drv_lcd.h | 2 +- bsp/imxrt/libraries/drivers/drv_log.h | 2 +- bsp/imxrt/libraries/drivers/drv_lpadc.c | 2 +- bsp/imxrt/libraries/drivers/drv_lpadc.h | 2 +- bsp/imxrt/libraries/drivers/drv_mdio.c | 2 +- bsp/imxrt/libraries/drivers/drv_mdio.h | 2 +- .../libraries/drivers/drv_pulse_encoder.c | 2 +- bsp/imxrt/libraries/drivers/drv_pwm.c | 2 +- bsp/imxrt/libraries/drivers/drv_pwm.h | 2 +- bsp/imxrt/libraries/drivers/drv_rtc.c | 2 +- bsp/imxrt/libraries/drivers/drv_rtc.h | 2 +- bsp/imxrt/libraries/drivers/drv_rtl8211f.c | 2 +- bsp/imxrt/libraries/drivers/drv_sai.c | 2 +- bsp/imxrt/libraries/drivers/drv_sai.h | 2 +- bsp/imxrt/libraries/drivers/drv_sdio.c | 2 +- bsp/imxrt/libraries/drivers/drv_sdram.h | 2 +- bsp/imxrt/libraries/drivers/drv_spi.c | 2 +- bsp/imxrt/libraries/drivers/drv_spi.h | 2 +- bsp/imxrt/libraries/drivers/drv_uart.c | 2 +- bsp/imxrt/libraries/drivers/drv_uart.h | 2 +- bsp/imxrt/libraries/drivers/drv_usbd.c | 2 +- bsp/imxrt/libraries/drivers/drv_usbh.c | 2 +- bsp/imxrt/libraries/drivers/drv_usbh.h | 2 +- bsp/imxrt/libraries/drivers/drv_wdt.c | 2 +- bsp/imxrt/libraries/drivers/drv_wdt.h | 2 +- .../imxrt1050xxx/applications/main.c | 2 +- .../imxrt1050xxx/board/MCUX_Config/pin_mux.c | 4 +- .../templates/imxrt1050xxx/board/board.c | 2 +- .../templates/imxrt1050xxx/board/board.h | 2 +- .../imxrt1064xxx/applications/main.c | 2 +- .../imxrt1064xxx/board/MCUX_Config/pin_mux.c | 4 +- .../templates/imxrt1064xxx/board/board.c | 2 +- .../templates/imxrt1064xxx/board/board.h | 2 +- .../imxrt1064xxx/xip/fsl_flexspi_nor_boot.c | 10 ++-- .../imxrt1064xxx/xip/fsl_flexspi_nor_boot.h | 24 +++++----- 227 files changed, 542 insertions(+), 542 deletions(-) diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/arm_math.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/arm_math.h index 62f87bec87..27c29911e3 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/arm_math.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/arm_math.h @@ -77,7 +77,7 @@ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * + * * * Examples * -------- diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armcc.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armcc.h index 093d35b9e5..97d14ddcd9 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armcc.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armcc.h @@ -58,9 +58,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif @@ -448,7 +448,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __schedule_barrier();\ } while (0U) - + /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armclang.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armclang.h index 5c4c20e877..027ede25fe 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armclang.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_armclang.h @@ -43,9 +43,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_gcc.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_gcc.h index 5d0f07e8ac..092d001f30 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_gcc.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/cmsis_gcc.h @@ -46,9 +46,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mbl.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mbl.h index 47a39893ac..09501ad997 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mbl.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mbl.h @@ -59,7 +59,7 @@ \ingroup Cortex_ARMv8MBL @{ */ - + #include "cmsis_version.h" /* CMSIS definitions */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mml.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mml.h index 0951a1f781..b1c1595a41 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mml.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_armv8mml.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,12 +90,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -130,18 +130,18 @@ #else #define __FPU_USED 0U #endif - + #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -159,12 +159,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0.h index a3f1b9ac33..cd4451220a 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0plus.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0plus.h index f8f30c3496..98cfc2af64 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0plus.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm0plus.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm3.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm3.h index a2c0d08057..8f87f4726c 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm3.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm3.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm33.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm33.h index b1efbcae7c..5072590c0d 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm33.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm33.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,7 +90,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -136,7 +136,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -159,7 +159,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm4.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm4.h index a11a3817a2..3b6faf7eec 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm4.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/core_cm4.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv7.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv7.h index aa180c9e59..c704e9258d 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv7.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv7.h @@ -21,13 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif - + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -60,7 +60,7 @@ #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) -#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_NONE 0U #define ARM_MPU_AP_PRIV 1U #define ARM_MPU_AP_URO 2U #define ARM_MPU_AP_FULL 3U @@ -79,7 +79,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. @@ -88,7 +88,7 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. -*/ +*/ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ @@ -108,7 +108,7 @@ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -146,7 +146,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; @@ -157,7 +157,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; @@ -173,7 +173,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -183,7 +183,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv8.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv8.h index 0ccfc74fe5..43d6fec7a2 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv8.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/mpu_armv8.h @@ -108,7 +108,7 @@ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -171,11 +171,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } @@ -222,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ +{ ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif @@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; @@ -244,7 +244,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); @@ -255,10 +255,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif @@ -270,7 +270,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -282,7 +282,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { @@ -291,7 +291,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - + mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; @@ -302,7 +302,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } - + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } @@ -312,7 +312,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } @@ -323,7 +323,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } diff --git a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/tz_context.h b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/tz_context.h index 0d09749f3a..facc2c9a47 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/tz_context.h +++ b/bsp/imxrt/libraries/MIMXRT1050/CMSIS/Include/tz_context.h @@ -30,41 +30,41 @@ #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H - + #include - + #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif - + /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; - + /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); - + /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - + /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - + /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - + /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - + #endif // TZ_CONTEXT_H diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h index 3138fec3d7..476da05a9a 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_AOI_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h index 4f94124b32..31f5cb491f 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h index f8a72507e2..e34d038efb 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CACHE_H_ @@ -99,7 +99,7 @@ typedef struct _l2cache_config { /* ------------------------ l2 cachec basic settings ---------------------------- */ l2cache_way_num_t wayNum; /*!< The number of ways. */ - l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */ /* ------------------------ tag/data ram latency settings ----------------------- */ L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ @@ -109,7 +109,7 @@ typedef struct _l2cache_config /* ------------------------ Non-secure access settings -------------------------- */ bool nsLockdownEnable; /*!< None-secure lockdown enable. */ /* ------------------------ other settings -------------------------------------- */ - l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ + l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ } l2cache_config_t; #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /******************************************************************************* @@ -157,7 +157,7 @@ static inline void L1CACHE_InvalidateICache(void) * * @param address The start address of the memory to be invalidated. * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. * The startAddr here will be forced to align to L1 I-cache line size if * startAddr is not aligned. For the size_byte, application should make sure the * alignment or make sure the right operation order if the size_byte is not aligned. @@ -214,7 +214,7 @@ static inline void L1CACHE_CleanInvalidateDCache(void) * * @param address The start address of the memory to be invalidated. * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. * The startAddr here will be forced to align to L1 D-cache line size if * startAddr is not aligned. For the size_byte, application should make sure the * alignment or make sure the right operation order if the size_byte is not aligned. @@ -280,7 +280,7 @@ void L2CACHE_Init(l2cache_config_t *config); /*! * @brief Gets an available default settings for the cache controller. * - * This function initializes the cache controller configuration structure with default settings. + * This function initializes the cache controller configuration structure with default settings. * The default values are: * @code * config->waysNum = kL2CACHE_8ways; @@ -290,7 +290,7 @@ void L2CACHE_Init(l2cache_config_t *config); * config->istrPrefetchEnable = false; * config->dataPrefetchEnable = false; * config->nsLockdownEnable = false; - * config->writeAlloc = kL2CACHE_UseAwcache; + * config->writeAlloc = kL2CACHE_UseAwcache; * @endcode * @param config Pointer to the configuration structure. */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h index 8b5b9a87f8..e14a94b2e5 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.h index d8a74ce412..cfd18dbfb4 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.h @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -126,7 +126,7 @@ enum _status_groups kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ @@ -371,7 +371,7 @@ _Pragma("diag_suppress=Pm120") #define AT_QUICKACCESS_SECTION_DATA(func) func #else #error Toolchain not supported. -#endif +#endif #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ /* @} */ @@ -525,7 +525,7 @@ _Pragma("diag_suppress=Pm120") */ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); #endif /* ENABLE_RAM_VECTOR_TABLE. */ - + #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) /*! * @brief Enable specific interrupt for wake-up from deep-sleep mode. @@ -566,15 +566,15 @@ _Pragma("diag_suppress=Pm120") * @param size The length required to malloc. * @param alignbytes The alignment size. * @retval The allocated memory. - */ + */ void *SDK_Malloc(size_t size, size_t alignbytes); - + /*! * @brief Free memory. * * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); + */ + void SDK_Free(void *ptr); #if defined(__cplusplus) } diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h index 86ba500356..e0c52bdc50 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h index cadfe8c76c..c69b4ad3e7 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.h index f458f8de2d..dd6b871cee 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.h index 899069fa84..6a9593441c 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enc.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enc.h index 52b8b1895e..6f9f8b52ee 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enc.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enc.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enet.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enet.h index fc741d009e..38e75d5a90 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enet.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_enet.h @@ -681,9 +681,9 @@ void ENET_GetDefaultConfig(enet_config_t *config); * The buffer configuration should be prepared for ENET Initialization. * It is the start address of "ringNum" enet_buffer_config structures. * To support added multi-ring features in some soc and compatible with the previous - * enet driver version. For single ring supported, this bufferConfig is a buffer - * configure structure pointer, for multi-ring supported and used case, this bufferConfig - * pointer should be a buffer configure structure array pointer. + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. * @param macAddr ENET mac address of Ethernet device. This MAC address should be * provided. * @param srcClock_Hz The internal module clock source for MII clock. diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_ewm.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_ewm.h index 15a9e61d25..4295e0a9c8 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_ewm.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_ewm.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_EWM_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio.h index da74e1f454..3b0098d815 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi.h index 96cea3a940..44d8a7274f 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi_edma.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi_edma.h index 4afecc7d10..79c6e23523 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_spi_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_SPI_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_uart_edma.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_uart_edma.h index da577d0ff9..467293aa2c 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_uart_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexio_uart_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_UART_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.c b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.c index a2f6885358..2e870d982c 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.c +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.c @@ -169,7 +169,7 @@ void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) * is needed. * param config allocate configuration. * retval kStatus_InvalidArgument the argument is invalid - * kStatus_Success allocate success + * kStatus_Success allocate success */ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) { diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.h index 0963e76df6..74c920dd80 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_flexram.h @@ -249,7 +249,7 @@ static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable * is needed. * @param config allocate configuration. * @retval kStatus_InvalidArgument the argument is invalid - * kStatus_Success allocate success + * kStatus_Success allocate success */ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpc.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpc.h index be9368a468..09dbaa15de 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpc.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpc.h @@ -3,7 +3,7 @@ * Copyright 2016 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpt.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpt.h index b01a4515c4..8f5a2ef5c5 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpt.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_gpt.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_kpp.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_kpp.h index d63648046b..ddec92d2c2 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_kpp.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_kpp.h @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_KPP_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_lpi2c_edma.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_lpi2c_edma.h index 04711f2bd4..30d528e555 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_lpi2c_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_lpi2c_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LPI2C_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pmu.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pmu.h index e885646825..e80ec379bf 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pmu.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pmu.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PMU_H_ @@ -108,10 +108,10 @@ extern "C" { */ /*! - * @brief Get PMU status flags. + * @brief Get PMU status flags. * * @param base PMU peripheral base address. - * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok + * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok * and brownout output of 1P1,3P0 and 2P5 is detected. */ uint32_t PMU_GetStatusFlags(PMU_Type *base); diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pwm.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pwm.h index 36e2d3155b..ae93c8cb63 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pwm.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_pwm.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PWM_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_qtmr.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_qtmr.h index 87329499e3..650449e5bf 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_qtmr.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_qtmr.h @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_QTMR_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_snvs_lp.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_snvs_lp.h index bbf2ede992..ca4db3eb3f 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_snvs_lp.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_snvs_lp.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_src.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_src.h index cec5039b50..f397c0fc48 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_src.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_src.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -86,8 +86,8 @@ enum _src_reset_status_flags power-on detection logic. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) - kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software - setting of SYSRESETREQ bit in Application Interrupt and + kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software + setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbara.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbara.h index f3f71d21e4..c60cc82b32 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbara.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbara.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbarb.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbarb.h index ad83f51e59..b459880605 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbarb.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_xbarb.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/project_template/pin_mux.c b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/project_template/pin_mux.c index 5151256924..d0318c7d76 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/project_template/pin_mux.c +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/project_template/pin_mux.c @@ -24,10 +24,10 @@ processor_version: 0.0.11 #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ - * + * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. - * + * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_notifier.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_notifier.h index be512224ca..3d0b6a8384 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_notifier.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_notifier.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_sbrk.c b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_sbrk.c index 753b14359a..9899c90b93 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_sbrk.c +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/utilities/fsl_sbrk.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #if defined(__GNUC__) diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.c index 41b273f70b..d11ab3b0e2 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.c +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.c @@ -18,8 +18,8 @@ #elif defined(__ICCARM__) #pragma location=".boot_hdr.ivt" #endif -/************************************* - * IVT Data +/************************************* + * IVT Data *************************************/ const ivt image_vector_table = { IVT_HEADER, /* IVT Header */ @@ -37,14 +37,14 @@ const ivt image_vector_table = { #elif defined(__ICCARM__) #pragma location=".boot_hdr.boot_data" #endif -/************************************* - * Boot Data +/************************************* + * Boot Data *************************************/ const BOOT_DATA_T boot_data = { FLASH_BASE, /* boot start location */ FLASH_SIZE, /* size */ PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + 0xFFFFFFFF /* empty - extra data word */ }; #endif diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.h index b95411fd83..25280629c5 100644 --- a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.h +++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/xip/fsl_flexspi_nor_boot.h @@ -17,8 +17,8 @@ #define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*@}*/ -/************************************* - * IVT Data +/************************************* + * IVT Data *************************************/ typedef struct _ivt_ { /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields @@ -56,18 +56,18 @@ typedef struct _ivt_ { ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) -/* IVT header */ +/* IVT header */ #define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ #define IVT_SIZE 0x2000 #define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) #define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) /* Set resume entry */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t __Vectors[]; extern uint32_t Image$$RW_m_config_text$$Base[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) -#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) #elif defined(__MCUXPRESSO) extern uint32_t __Vectors[]; extern uint32_t __boot_hdr_start__[]; @@ -76,13 +76,13 @@ typedef struct _ivt_ { #elif defined(__ICCARM__) extern uint32_t __VECTOR_TABLE[]; extern uint32_t m_boot_hdr_conf_start[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) #elif defined(__GNUC__) extern uint32_t __VECTOR_TABLE[]; extern uint32_t __FLASH_BASE[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) #endif #define DCD_ADDRESS dcd_data @@ -90,14 +90,14 @@ typedef struct _ivt_ { #define CSF_ADDRESS 0 #define IVT_RSVD (uint32_t)(0x00000000) -/************************************* - * Boot Data +/************************************* + * Boot Data *************************************/ typedef struct _boot_data_ { uint32_t start; /* boot start location */ uint32_t size; /* size */ uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ - uint32_t placeholder; /* placehoder to make even 0x10 size */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ }BOOT_DATA_T; #define FLASH_SIZE BOARD_FLASH_SIZE diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/arm_math.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/arm_math.h index 62f87bec87..27c29911e3 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/arm_math.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/arm_math.h @@ -77,7 +77,7 @@ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * + * * * Examples * -------- diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armcc.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armcc.h index 59f173ac71..1c9674bc5b 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armcc.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armcc.h @@ -62,9 +62,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif @@ -472,7 +472,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __schedule_barrier();\ } while (0U) - + /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang.h index e917f357a3..8224cdb37b 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang.h @@ -594,7 +594,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -640,7 +640,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang_ltm.h index feec324059..d6b28d430a 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang_ltm.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_armclang_ltm.h @@ -595,7 +595,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -641,7 +641,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_gcc.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_gcc.h index 3ddcc58b69..b111f6248c 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_gcc.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_gcc.h @@ -46,9 +46,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -126,23 +126,23 @@ \details This default implementations initialized all data and additional bss sections relying on .copy.table and .zero.table specified properly in the used linker script. - + */ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) { extern void _start(void) __NO_RETURN; - + typedef struct { uint32_t const* src; uint32_t* dest; uint32_t wlen; } __copy_table_t; - + typedef struct { uint32_t* dest; uint32_t wlen; } __zero_table_t; - + extern const __copy_table_t __copy_table_start__; extern const __copy_table_t __copy_table_end__; extern const __zero_table_t __zero_table_start__; @@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) pTable->dest[i] = pTable->src[i]; } } - + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = 0u; } } - + _start(); } - + #define __PROGRAM_START __cmsis_start #endif @@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -697,7 +697,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ @@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) +#if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_iccarm.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_iccarm.h index 12d68fd9a6..6580cce3ce 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_iccarm.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/cmsis_iccarm.h @@ -8,7 +8,7 @@ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2019 IAR Systems -// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mbl.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mbl.h index 47a39893ac..09501ad997 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mbl.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mbl.h @@ -59,7 +59,7 @@ \ingroup Cortex_ARMv8MBL @{ */ - + #include "cmsis_version.h" /* CMSIS definitions */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mml.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mml.h index 0951a1f781..b1c1595a41 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mml.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_armv8mml.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,12 +90,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -130,18 +130,18 @@ #else #define __FPU_USED 0U #endif - + #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -159,12 +159,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0.h index a3f1b9ac33..cd4451220a 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0plus.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0plus.h index f8f30c3496..98cfc2af64 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0plus.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm0plus.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm3.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm3.h index a2c0d08057..8f87f4726c 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm3.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm3.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm33.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm33.h index b1efbcae7c..5072590c0d 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm33.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm33.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,7 +90,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -136,7 +136,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -159,7 +159,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm4.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm4.h index a11a3817a2..3b6faf7eec 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm4.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm4.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm7.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm7.h index e15eae6f76..368714ec6c 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm7.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/core_cm7.h @@ -2531,10 +2531,10 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { + if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - + __DSB(); do { @@ -2561,10 +2561,10 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsiz __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { + if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - + __DSB(); do { @@ -2591,10 +2591,10 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { + if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - + __DSB(); do { diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv7.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv7.h index 66ef59b4a0..4592d60879 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv7.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv7.h @@ -21,13 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif - + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -79,12 +79,12 @@ /** * MPU Memory Access Attributes -* +* * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ +*/ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ @@ -93,7 +93,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. @@ -110,7 +110,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. @@ -119,7 +119,7 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. -*/ +*/ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) @@ -129,7 +129,7 @@ * - Shareable * - Non-cacheable * - Non-bufferable -*/ +*/ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** @@ -140,7 +140,7 @@ * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** @@ -153,7 +153,7 @@ * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) /** @@ -184,7 +184,7 @@ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -221,7 +221,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; @@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; @@ -248,7 +248,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -258,7 +258,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv8.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv8.h index 0ccfc74fe5..43d6fec7a2 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv8.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/mpu_armv8.h @@ -108,7 +108,7 @@ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -171,11 +171,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } @@ -222,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ +{ ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif @@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; @@ -244,7 +244,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); @@ -255,10 +255,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif @@ -270,7 +270,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -282,7 +282,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { @@ -291,7 +291,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - + mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; @@ -302,7 +302,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } - + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } @@ -312,7 +312,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } @@ -323,7 +323,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } diff --git a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/tz_context.h b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/tz_context.h index 0d09749f3a..facc2c9a47 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/tz_context.h +++ b/bsp/imxrt/libraries/MIMXRT1060/CMSIS/Include/tz_context.h @@ -30,41 +30,41 @@ #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H - + #include - + #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif - + /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; - + /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); - + /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - + /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - + /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - + /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - + #endif // TZ_CONTEXT_H diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_bee.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_bee.h index 201177a41f..0ea8f80963 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_bee.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_bee.h @@ -38,8 +38,8 @@ * - Fixed typos in comments. * - New Features * - Added configuration setting for endian swap, access permission and region security level. - * - Improvements - * - Setting of AES nonce was moved from BEE_SetRegionKey() into separate BEE_SetRegionNonce() function. + * - Improvements + * - Setting of AES nonce was moved from BEE_SetRegionKey() into separate BEE_SetRegionNonce() function. * - Changed handling of region settings. Both regions are configured simultaneously by BEE_SetConfig() function. * Configuration of FAC start and end address using IOMUXC_GPRs was moved to application. * - Default value for region address offset was changed to 0. diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.c index 2cc0fd799a..2c7db7856e 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.c @@ -34,7 +34,7 @@ * is needed. * param config allocate configuration. * retval kStatus_InvalidArgument the argument is invalid - * kStatus_Success allocate success + * kStatus_Success allocate success */ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) { diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.h index 47448afe8d..7c146c08a7 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram_allocate.h @@ -64,7 +64,7 @@ extern "C" { * is needed. * @param config allocate configuration. * @retval kStatus_InvalidArgument the argument is invalid - * kStatus_Success allocate success + * kStatus_Success allocate success */ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/pin_mux.c b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/pin_mux.c index 401ee8c98f..9b8cb78e32 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/pin_mux.c +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/project_template/pin_mux.c @@ -24,10 +24,10 @@ processor_version: 0.0.20 #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ - * + * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. - * + * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); diff --git a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console_conf.h b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console_conf.h index fd235b1e54..a997ab5bcc 100644 --- a/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console_conf.h +++ b/bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/utilities/debug_console/fsl_debug_console_conf.h @@ -19,7 +19,7 @@ * And non-blocking is combine with buffer, no matter bare-metal or rtos. * Below shows how to configure in your project if you want to use non-blocking mode. * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". - * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". * For ARMGCC, open CmakeLists.txt and add the following lines, * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/arm_math.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/arm_math.h index ea9dd26aa8..d6b5b2b1ce 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/arm_math.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/arm_math.h @@ -77,7 +77,7 @@ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * + * * * Examples * -------- diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armcc.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armcc.h index 093d35b9e5..97d14ddcd9 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armcc.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armcc.h @@ -58,9 +58,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif @@ -448,7 +448,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __schedule_barrier();\ } while (0U) - + /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armclang.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armclang.h index 5c4c20e877..027ede25fe 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armclang.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_armclang.h @@ -43,9 +43,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_gcc.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_gcc.h index 5d0f07e8ac..092d001f30 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_gcc.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/cmsis_gcc.h @@ -46,9 +46,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mbl.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mbl.h index 47a39893ac..09501ad997 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mbl.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mbl.h @@ -59,7 +59,7 @@ \ingroup Cortex_ARMv8MBL @{ */ - + #include "cmsis_version.h" /* CMSIS definitions */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mml.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mml.h index 0951a1f781..b1c1595a41 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mml.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_armv8mml.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,12 +90,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -130,18 +130,18 @@ #else #define __FPU_USED 0U #endif - + #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -159,12 +159,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - + #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0.h index a3f1b9ac33..cd4451220a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0plus.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0plus.h index f8f30c3496..98cfc2af64 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0plus.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm0plus.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm3.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm3.h index a2c0d08057..8f87f4726c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm3.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm3.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm33.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm33.h index b1efbcae7c..5072590c0d 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm33.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm33.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -90,7 +90,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -113,7 +113,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -136,7 +136,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -159,7 +159,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm4.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm4.h index a11a3817a2..3b6faf7eec 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm4.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/core_cm4.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv7.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv7.h index aa180c9e59..c704e9258d 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv7.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv7.h @@ -21,13 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif - + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -60,7 +60,7 @@ #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) -#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_NONE 0U #define ARM_MPU_AP_PRIV 1U #define ARM_MPU_AP_URO 2U #define ARM_MPU_AP_FULL 3U @@ -79,7 +79,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. @@ -88,7 +88,7 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. -*/ +*/ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ @@ -108,7 +108,7 @@ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -146,7 +146,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; @@ -157,7 +157,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; @@ -173,7 +173,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -183,7 +183,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv8.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv8.h index 0ccfc74fe5..43d6fec7a2 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv8.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/mpu_armv8.h @@ -108,7 +108,7 @@ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -171,11 +171,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } @@ -222,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ +{ ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif @@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; @@ -244,7 +244,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); @@ -255,10 +255,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif @@ -270,7 +270,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -282,7 +282,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { @@ -291,7 +291,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - + mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; @@ -302,7 +302,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } - + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } @@ -312,7 +312,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } @@ -323,7 +323,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } diff --git a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/tz_context.h b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/tz_context.h index 0d09749f3a..facc2c9a47 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/tz_context.h +++ b/bsp/imxrt/libraries/MIMXRT1064/CMSIS/Include/tz_context.h @@ -30,41 +30,41 @@ #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H - + #include - + #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif - + /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; - + /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); - + /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - + /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - + /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - + /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - + #endif // TZ_CONTEXT_H diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aipstz.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aipstz.c index abb11f31d7..fcb55bfee1 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aipstz.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aipstz.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.c index 50337f8230..8de79d1058 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_aoi.h" diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.h index 3138fec3d7..476da05a9a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_aoi.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_AOI_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.c index ff6d1a0ff3..9bee27f9c3 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.c @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.h index 4f94124b32..31f5cb491f 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_bee.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.c index 3c3ccd16ca..4504ed47d3 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -169,7 +169,7 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way) void L2CACHE_Init(l2cache_config_t *config) { assert (config); - + uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */ uint8_t count; uint32_t auxReg = 0; @@ -180,7 +180,7 @@ void L2CACHE_Init(l2cache_config_t *config) if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK) { L2CACHE_Disable(); - } + } /* Unlock all entries. */ if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) @@ -190,12 +190,12 @@ void L2CACHE_Init(l2cache_config_t *config) for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++) { - L2CACHE_LockdownByWayEnable(count, waysNum, false); + L2CACHE_LockdownByWayEnable(count, waysNum, false); } - + /* Set the ways and way-size etc. */ auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) | - L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | @@ -239,7 +239,7 @@ void L2CACHE_GetDefaultConfig(l2cache_config_t *config) config->istrPrefetchEnable = false; config->dataPrefetchEnable = false; config->nsLockdownEnable = false; - config->writeAlloc = kL2CACHE_UseAwcache; + config->writeAlloc = kL2CACHE_UseAwcache; } void L2CACHE_Enable(void) @@ -399,7 +399,7 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) } __DSB(); __ISB(); -#endif +#endif } void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.h index f8a72507e2..e34d038efb 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cache.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CACHE_H_ @@ -99,7 +99,7 @@ typedef struct _l2cache_config { /* ------------------------ l2 cachec basic settings ---------------------------- */ l2cache_way_num_t wayNum; /*!< The number of ways. */ - l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */ /* ------------------------ tag/data ram latency settings ----------------------- */ L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ @@ -109,7 +109,7 @@ typedef struct _l2cache_config /* ------------------------ Non-secure access settings -------------------------- */ bool nsLockdownEnable; /*!< None-secure lockdown enable. */ /* ------------------------ other settings -------------------------------------- */ - l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ + l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ } l2cache_config_t; #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /******************************************************************************* @@ -157,7 +157,7 @@ static inline void L1CACHE_InvalidateICache(void) * * @param address The start address of the memory to be invalidated. * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. * The startAddr here will be forced to align to L1 I-cache line size if * startAddr is not aligned. For the size_byte, application should make sure the * alignment or make sure the right operation order if the size_byte is not aligned. @@ -214,7 +214,7 @@ static inline void L1CACHE_CleanInvalidateDCache(void) * * @param address The start address of the memory to be invalidated. * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. * The startAddr here will be forced to align to L1 D-cache line size if * startAddr is not aligned. For the size_byte, application should make sure the * alignment or make sure the right operation order if the size_byte is not aligned. @@ -280,7 +280,7 @@ void L2CACHE_Init(l2cache_config_t *config); /*! * @brief Gets an available default settings for the cache controller. * - * This function initializes the cache controller configuration structure with default settings. + * This function initializes the cache controller configuration structure with default settings. * The default values are: * @code * config->waysNum = kL2CACHE_8ways; @@ -290,7 +290,7 @@ void L2CACHE_Init(l2cache_config_t *config); * config->istrPrefetchEnable = false; * config->dataPrefetchEnable = false; * config->nsLockdownEnable = false; - * config->writeAlloc = kL2CACHE_UseAwcache; + * config->writeAlloc = kL2CACHE_UseAwcache; * @endcode * @param config Pointer to the configuration structure. */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.c index 40ba8e2cf1..2b93ad4290 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.c @@ -14,7 +14,7 @@ /******************************************************************************* * Definitions ******************************************************************************/ -/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ #if __FPU_USED @@ -447,7 +447,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) { - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; } else { @@ -468,7 +468,7 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) */ void CLOCK_DisableUsbhs0PhyPllClock(void) { - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } @@ -1212,6 +1212,6 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) */ void CLOCK_DisableUsbhs1PhyPllClock(void) { - CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.h index 3a768049ab..20f8ebcb67 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_clock.h @@ -540,7 +540,7 @@ typedef enum _clock_ip_name kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */ kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT,/*!< CCGR7, CG5 */ kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */ - + } clock_ip_name_t; /*! @brief OSC 24M sorce select */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.c index e7c9ee6573..381254860f 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.h index 8b5b9a87f8..e14a94b2e5 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_cmp.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_common.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_common.h index f3468b412b..f578c5bc14 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_common.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_common.h @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -123,7 +123,7 @@ enum _status_groups kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ }; @@ -348,7 +348,7 @@ _Pragma("diag_suppress=Pm120") #define AT_QUICKACCESS_SECTION_DATA(func) func #else #error Toolchain not supported. -#endif +#endif #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ /* @} */ @@ -532,15 +532,15 @@ _Pragma("diag_suppress=Pm120") * @param size The length required to malloc. * @param alignbytes The alignment size. * @retval The allocated memory. - */ + */ void *SDK_Malloc(size_t size, size_t alignbytes); - + /*! * @brief Free memory. * * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); + */ + void SDK_Free(void *ptr); #if defined(__cplusplus) } diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_csi.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_csi.h index b9fb3eeb81..ac88f970fe 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_csi.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_csi.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.c index 39008aed44..ab00279039 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.h index 86ba500356..e0c52bdc50 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcdc.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.c index c9ef8531dc..9f27782e58 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.c @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.h index 5d0dc2bc8b..1c3552f919 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dcp.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.c index 411c4b64a6..2a301bda1a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.h index f458f8de2d..dd6b871cee 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_dmamux.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.c index 3922e50077..617fd299e5 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.h index 899069fa84..6a9593441c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_elcdif.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.c index 700158238a..a6fce30475 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.h index 52b8b1895e..6f9f8b52ee 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enc.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.c index f5c6613ad2..71b60b0bbc 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.c @@ -2,7 +2,7 @@ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -321,12 +321,12 @@ void ENET_GetDefaultConfig(enet_config_t *config) memset(config, 0, sizeof(enet_config_t)); /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB config->miiMode = kENET_RgmiiMode; #else config->miiMode = kENET_RmiiMode; #endif - config->miiSpeed = kENET_MiiSpeed100M; + config->miiSpeed = kENET_MiiSpeed100M; config->miiDuplex = kENET_MiiFullDuplex; config->ringNum = 1; @@ -487,7 +487,7 @@ static void ENET_SetMacController(ENET_Type *base, ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | - ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; /* Set the RGMII or RMII, MII mode and control register. */ #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB @@ -583,11 +583,11 @@ static void ENET_SetMacController(ENET_Type *base, /* Initializes the ring 0. */ #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); - base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); #else base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; -#endif +#endif base->MRBR = bufferConfig->rxBuffSizeAlign; #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB @@ -602,7 +602,7 @@ static void ENET_SetMacController(ENET_Type *base, base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); #else base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; - base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; + base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; #endif base->MRBR1 = buffCfg->rxBuffSizeAlign; /* Enable the DMAC for ring 1 and with no rx classification set. */ @@ -1168,14 +1168,14 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache invalidate maintain. */ DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enet_ptp_time_data_t ptpTimestamp; - bool isPtpEventMessage = false; + bool isPtpEventMessage = false; /* Parse the PTP message according to the header message. */ isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ @@ -1236,8 +1236,8 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ } @@ -1388,7 +1388,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); #else address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ if (sizeleft > handle->txBuffSizeAlign[0]) { /* Data copy. */ @@ -1413,10 +1413,10 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL /* Add the cache clean maintain. */ DCACHE_CleanByRange(address, sizeleft); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ curBuffDescrip->length = sizeleft; /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; /* Active the transmit buffer descriptor. */ ENET_ActiveSend(base, 0); @@ -1534,7 +1534,7 @@ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, u if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) { return kStatus_ENET_RxFrameError; - } + } /* Find the last buffer descriptor. */ if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) { @@ -1985,7 +1985,7 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat return kStatus_ENET_TxFrameFail; } -#if FSL_FEATURE_ENET_QUEUE > 1 +#if FSL_FEATURE_ENET_QUEUE > 1 status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint32_t ringId) { @@ -2077,7 +2077,7 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt #if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) { - buffer += ENET_FRAME_VLAN_TAGLEN; + buffer += ENET_FRAME_VLAN_TAGLEN; } #endif /* FSL_FEATURE_ENET_HAS_AVB */ } @@ -2419,7 +2419,7 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); if (isPtpEventMessage) { - /* Only store tx timestamp for ptp event message. */ + /* Only store tx timestamp for ptp event message. */ do { /* Increase current buffer descriptor to the next one. */ @@ -2486,7 +2486,7 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui else { handle->txBdDirtyTime[ringId]++; - } + } } return kStatus_Success; } @@ -2848,7 +2848,7 @@ void ENET_DriverIRQHandler(void) exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); -#endif +#endif /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) @@ -2859,7 +2859,7 @@ void ENET_DriverIRQHandler(void) #endif -#if defined(ENET1) +#if defined(ENET1) void ENET1_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(ENET1); @@ -2884,7 +2884,7 @@ void ENET2_DriverIRQHandler(void) #endif -#if defined(CONNECTIVITY__ENET0) +#if defined(CONNECTIVITY__ENET0) void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) { ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.h index fc741d009e..38e75d5a90 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_enet.h @@ -681,9 +681,9 @@ void ENET_GetDefaultConfig(enet_config_t *config); * The buffer configuration should be prepared for ENET Initialization. * It is the start address of "ringNum" enet_buffer_config structures. * To support added multi-ring features in some soc and compatible with the previous - * enet driver version. For single ring supported, this bufferConfig is a buffer - * configure structure pointer, for multi-ring supported and used case, this bufferConfig - * pointer should be a buffer configure structure array pointer. + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. * @param macAddr ENET mac address of Ethernet device. This MAC address should be * provided. * @param srcClock_Hz The internal module clock source for MII clock. diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.c index a8ca2412ed..a83883e19c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.h index 15a9e61d25..4295e0a9c8 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_ewm.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_EWM_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.c index b5d9c86327..339c6d4459 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.h index cd9fbfe5c5..f9c259b00b 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.c index c2ef8a7c65..fa5847948a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.h index 96cea3a940..44d8a7274f 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.c index f6f28685a0..5c79a19f4c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.h index 4afecc7d10..79c6e23523 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_spi_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_SPI_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.c index 35e318570d..d6c8f378c2 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.c @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.h index 37b85c644d..2b08169b9f 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart.h @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.c index 3fa908053e..e8f881af05 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.h index da577d0ff9..467293aa2c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexio_uart_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_UART_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.c index 4aac150d37..671a9e5de1 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.c @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.h index 9fdce9f87f..0c9f074549 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexram.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -278,7 +278,7 @@ static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAd * is needed. * @param config allocate configuration. * @retval kStatus_InvalidArgument the argument is invalid - * kStatus_Success allocate success + * kStatus_Success allocate success */ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.c index 60024d9126..39a6774e03 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.h index 79aaf26415..9a9ff657da 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_flexspi.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.c index 60a80214fd..3413f1d58a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.c @@ -3,7 +3,7 @@ * Copyright 2016 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.h index be9368a468..09dbaa15de 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpc.h @@ -3,7 +3,7 @@ * Copyright 2016 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.c index 234f668837..536ea91aee 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.h index b01a4515c4..8f5a2ef5c5 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_gpt.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_iomuxc.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_iomuxc.h index d57063526c..95d7499aaa 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_iomuxc.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_iomuxc.h @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -1213,16 +1213,16 @@ typedef enum _iomuxc_gpr_mode kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, - kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, + kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, } iomuxc_gpr_mode_t; typedef enum _iomuxc_gpr_saimclk { kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, - kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, } iomuxc_gpr_saimclk_t; typedef enum _iomuxc_mqs_pwm_oversample_rate @@ -1345,17 +1345,17 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; } else { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; } } /*! - * @brief Enters or exit MQS software reset. + * @brief Enters or exit MQS software reset. * * @param base The IOMUXC GPR base address. * @param enable Enter or exit MQS software reset. @@ -1364,17 +1364,17 @@ static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enab { if (enable) { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; } else { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; } } /*! - * @brief Enables or disables MQS. + * @brief Enables or disables MQS. * * @param base The IOMUXC GPR base address. * @param enable Enable or disable the MQS. @@ -1383,16 +1383,16 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) { if (enable) { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; } else { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; } } /*! - * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. * * @param base The IOMUXC GPR base address. * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". @@ -1402,7 +1402,7 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) { uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); - + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); } diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.c index 9abdd4ced7..ad05c32bd5 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.c @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -152,7 +152,7 @@ void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) } } } - + /* Return all columns to 0 in preparation for standby mode. */ base->KPDR &= ~KPP_KPDR_KCD_MASK; diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.h index d63648046b..ddec92d2c2 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_kpp.h @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_KPP_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_edma.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_edma.h index 04711f2bd4..30d528e555 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LPI2C_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.c index aab1765492..ffee832cfd 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.h index e6cb94f53c..4e49e7fe4c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpi2c_freertos.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __FSL_LPI2C_FREERTOS_H__ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.c index 22216ae31d..1c3c6b9d1e 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.h index 11f20d5f89..5b1433c6e2 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpspi_freertos.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __FSL_LPSPI_FREERTOS_H__ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_edma.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_edma.h index 3d6e25b7c9..b4f971a4f8 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_edma.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LPUART_EDMA_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.c index f989f125f8..502bca35f6 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.h index afeafdad21..9f47e0b216 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_lpuart_freertos.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __FSL_LPUART_RTOS_H__ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.c index f591f1865b..82146998e7 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_pmu.h" diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.h index 49f3f854ba..e8627a4440 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pmu.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PMU_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.c index aecd02fc01..f4cd415b39 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.h index 36e2d3155b..ae93c8cb63 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pwm.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PWM_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.c index 6e1edc357f..250439c47f 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.h index 870cf97fbb..f1ba8d410a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_pxp.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductors, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.c index c18fc91f41..68e9140d9a 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.c @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -65,7 +65,7 @@ void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_conf /* Enable the module clock */ CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - + /* Setup the counter sources */ base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource)); @@ -74,7 +74,7 @@ void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_conf /* Setup debug mode */ base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode); - + base->CHANNEL[channel].FILT &= ~( TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK); /* Setup input filter */ base->CHANNEL[channel].FILT = (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod)); @@ -164,7 +164,7 @@ status_t QTMR_SetupPwm( */ reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); base->CHANNEL[channel].CTRL = reg; - + return kStatus_Success; } diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.h index 87329499e3..650449e5bf 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_qtmr.h @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_QTMR_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.c index 56f70572ad..a654dc33d6 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,7 +50,7 @@ void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) uint32_t value = 0U; uint32_t primaskValue = 0U; - + value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | RTWDOG_CS_INT(config->enableInterrupt) | RTWDOG_CS_WIN(config->enableWindowMode) | RTWDOG_CS_UPDATE(config->enableUpdate) | RTWDOG_CS_DBG(config->workMode.enableDebug) | RTWDOG_CS_STOP(config->workMode.enableStop) | diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.h index 333ac7761b..75c7c46750 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_rtwdog.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_RTWDOG_H_ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_hp.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_hp.c index 00ffbbced7..e4525c1d41 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_hp.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_hp.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.c index c5dddbfd20..e1def79c51 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.h index 97e56eb8d0..dc8e68ee19 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_snvs_lp.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_spdif.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_spdif.c index 2ec785ce97..c837c7d6c0 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_spdif.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_spdif.c @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP Semiconductor, Inc. * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.c index a00691b6c7..6b9707ad8f 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.c @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.h index cec5039b50..f397c0fc48 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_src.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -86,8 +86,8 @@ enum _src_reset_status_flags power-on detection logic. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) - kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software - setting of SYSRESETREQ bit in Application Interrupt and + kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software + setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.c index a182e5e7f5..5d83ac6eec 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_trng.h" diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.h index e29ab0c60c..0ffada368c 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_trng.h @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_TRNG_DRIVER_H_ @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ -/*! @brief TRNG driver version 2.0.2. +/*! @brief TRNG driver version 2.0.2. * * Current version: 2.0.2 * diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.c index b107d60c7c..140978828e 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -126,7 +126,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Set active edge for edge detection, set interrupt or DMA function. */ switch ((uint16_t)output) { -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 case kXBARA1_OutputDmaChMuxReq30: #else case kXBARA_OutputDmamux18: @@ -142,7 +142,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Write regVal value into CTRL0 register */ base->CTRL0 = regVal; break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 case kXBARA1_OutputDmaChMuxReq31: #else case kXBARA_OutputDmamux19: @@ -158,7 +158,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Write regVal value into CTRL0 register */ base->CTRL0 = regVal; break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 case kXBARA1_OutputDmaChMuxReq94: #else case kXBARA_OutputDmamux20: @@ -174,7 +174,7 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, /* Write regVal value into CTRL1 register */ base->CTRL1 = regVal; break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 +#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 case kXBARA1_OutputDmaChMuxReq95: #else case kXBARA_OutputDmamux21: diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.h index f3f71d21e4..c60cc82b32 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbara.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.c index 02e89ed2d5..ec91bf5227 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.h index ad83f51e59..b459880605 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/drivers/fsl_xbarb.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.c index 50f0daddfc..88da299e04 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.c @@ -9,7 +9,7 @@ * @file board.c * @brief Board initialization file. */ - + /* This is an empty template for board specific configuration.*/ #include @@ -19,5 +19,5 @@ * @brief Set up and initialize all required blocks and functions related to the board hardware. */ void BOARD_InitDebugConsole(void) { - /* The user initialization should be placed here */ + /* The user initialization should be placed here */ } diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.h index eafa6e182f..7b246313ce 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/board.h @@ -9,14 +9,14 @@ * @file board.h * @brief Board initialization header file. */ - + /* This is an empty template for board specific configuration.*/ #ifndef _BOARD_H_ #define _BOARD_H_ /** - * @brief The board name + * @brief The board name */ #define BOARD_NAME "board" @@ -25,7 +25,7 @@ extern "C" { #endif /* __cplusplus */ /** - * @brief Initialize board specific settings. + * @brief Initialize board specific settings. */ void BOARD_InitDebugConsole(void); diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/pin_mux.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/pin_mux.c index 777a453587..9f9761d184 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/pin_mux.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/project_template/pin_mux.c @@ -26,10 +26,10 @@ processor_version: 0.0.0 #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ - * + * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. - * + * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_assert.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_assert.c index 9229a31e63..ee5659c85d 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_assert.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_assert.c @@ -3,7 +3,7 @@ * Copyright 2016-2017 NXP * All rights reserved. * -* +* * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.c index 550dd392cd..4c16fdd6ae 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.h index be512224ca..3d0b6a8384 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_notifier.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_sbrk.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_sbrk.c index 753b14359a..9899c90b93 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_sbrk.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_sbrk.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #if defined(__GNUC__) diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.c index 9bc44e2d1d..cc5d8720d7 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.c @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause * * POSIX getopt for Windows diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.h index ea9608ad68..14c7fc2c17 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/fsl_shell.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/io/fsl_io.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/io/fsl_io.h index 84a7533c5b..30b5dbfbd8 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/io/fsl_io.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/io/fsl_io.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause * */ @@ -80,7 +80,7 @@ status_t IO_Deinit(void); * @endcode * * @param ch transfer buffer pointer - * @param size transfer size + * @param size transfer size * @param tx indicate the transfer is TX or RX */ status_t IO_Transfer(uint8_t *ch, size_t size, bool tx); diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/log/fsl_log.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/log/fsl_log.h index 8d8ac972b4..797277b520 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/log/fsl_log.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/utilities/log/fsl_log.h @@ -37,7 +37,7 @@ extern "C" { * @param baudRate, device communicate baudrate * @param clkSrcFreq, device source clock freq * - * @return Indicates whether initialization was successful or not. + * @return Indicates whether initialization was successful or not. * @retval kStatus_Success Execution successfully * @retval kStatus_Fail Execution failure */ diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.c index eb175fac24..2e05990395 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.c +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.c @@ -13,8 +13,8 @@ #elif defined(__ICCARM__) #pragma location=".boot_hdr.ivt" #endif -/************************************* - * IVT Data +/************************************* + * IVT Data *************************************/ const ivt image_vector_table = { IVT_HEADER, /* IVT Header */ @@ -32,14 +32,14 @@ const ivt image_vector_table = { #elif defined(__ICCARM__) #pragma location=".boot_hdr.boot_data" #endif -/************************************* - * Boot Data +/************************************* + * Boot Data *************************************/ const BOOT_DATA_T boot_data = { FLASH_BASE, /* boot start location */ FLASH_SIZE, /* size */ PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + 0xFFFFFFFF /* empty - extra data word */ }; #endif diff --git a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.h index 4ace76c8a1..b22ad21bc0 100644 --- a/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.h +++ b/bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/xip/fsl_flexspi_nor_boot.h @@ -11,8 +11,8 @@ #include #include "board.h" -/************************************* - * IVT Data +/************************************* + * IVT Data *************************************/ typedef struct _ivt_ { /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields @@ -50,7 +50,7 @@ typedef struct _ivt_ { ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) -/* IVT header */ +/* IVT header */ #define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ #define IVT_SIZE 0x2000 #define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) @@ -60,8 +60,8 @@ typedef struct _ivt_ { #if defined(__CC_ARM) extern uint32_t __Vectors[]; extern uint32_t Image$$RW_m_config_text$$Base[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) -#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) #elif defined(__MCUXPRESSO) extern uint32_t __Vectors[]; extern uint32_t __boot_hdr_start__[]; @@ -70,13 +70,13 @@ typedef struct _ivt_ { #elif defined(__ICCARM__) extern uint32_t __VECTOR_TABLE[]; extern uint32_t m_boot_hdr_conf_start[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) #elif defined(__GNUC__) extern uint32_t __VECTOR_TABLE[]; extern uint32_t __FLASH_BASE[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) #endif #define DCD_ADDRESS dcd_data @@ -84,14 +84,14 @@ typedef struct _ivt_ { #define CSF_ADDRESS 0 #define IVT_RSVD (uint32_t)(0x00000000) -/************************************* - * Boot Data +/************************************* + * Boot Data *************************************/ typedef struct _boot_data_ { uint32_t start; /* boot start location */ uint32_t size; /* size */ uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ - uint32_t placeholder; /* placehoder to make even 0x10 size */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ }BOOT_DATA_T; #define FLASH_SIZE BOARD_FLASH_SIZE diff --git a/bsp/imxrt/libraries/drivers/bsp_wm8960.c b/bsp/imxrt/libraries/drivers/bsp_wm8960.c index d77dbcbfea..54498870e6 100644 --- a/bsp/imxrt/libraries/drivers/bsp_wm8960.c +++ b/bsp/imxrt/libraries/drivers/bsp_wm8960.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/bsp_wm8960.h b/bsp/imxrt/libraries/drivers/bsp_wm8960.h index 21f1141634..53d217fd66 100644 --- a/bsp/imxrt/libraries/drivers/bsp_wm8960.h +++ b/bsp/imxrt/libraries/drivers/bsp_wm8960.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_adc.c b/bsp/imxrt/libraries/drivers/drv_adc.c index a973eca26f..519f21bfa1 100644 --- a/bsp/imxrt/libraries/drivers/drv_adc.c +++ b/bsp/imxrt/libraries/drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_adc.h b/bsp/imxrt/libraries/drivers/drv_adc.h index 4de600b483..2aca3ca8d8 100644 --- a/bsp/imxrt/libraries/drivers/drv_adc.h +++ b/bsp/imxrt/libraries/drivers/drv_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_can.c b/bsp/imxrt/libraries/drivers/drv_can.c index 4502de374b..1c233662a5 100644 --- a/bsp/imxrt/libraries/drivers/drv_can.c +++ b/bsp/imxrt/libraries/drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_can.h b/bsp/imxrt/libraries/drivers/drv_can.h index 4f06c04de9..a151c8136f 100644 --- a/bsp/imxrt/libraries/drivers/drv_can.h +++ b/bsp/imxrt/libraries/drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_common.c b/bsp/imxrt/libraries/drivers/drv_common.c index c86c55c9ac..87112ff3ae 100644 --- a/bsp/imxrt/libraries/drivers/drv_common.c +++ b/bsp/imxrt/libraries/drivers/drv_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c index 7454fd18f7..c58e7eb312 100644 --- a/bsp/imxrt/libraries/drivers/drv_eth.c +++ b/bsp/imxrt/libraries/drivers/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_flexspi.c b/bsp/imxrt/libraries/drivers/drv_flexspi.c index e943dde048..0cacdc75f0 100644 --- a/bsp/imxrt/libraries/drivers/drv_flexspi.c +++ b/bsp/imxrt/libraries/drivers/drv_flexspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.c b/bsp/imxrt/libraries/drivers/drv_gpio.c index d88f6b3672..f5d0812d55 100644 --- a/bsp/imxrt/libraries/drivers/drv_gpio.c +++ b/bsp/imxrt/libraries/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.h b/bsp/imxrt/libraries/drivers/drv_gpio.h index 4dc61cb740..0ea8ead068 100644 --- a/bsp/imxrt/libraries/drivers/drv_gpio.h +++ b/bsp/imxrt/libraries/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_hwtimer.c b/bsp/imxrt/libraries/drivers/drv_hwtimer.c index 8197bd3ffe..aae7fa7a18 100644 --- a/bsp/imxrt/libraries/drivers/drv_hwtimer.c +++ b/bsp/imxrt/libraries/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_hwtimer.h b/bsp/imxrt/libraries/drivers/drv_hwtimer.h index be0aca27f0..22dd018347 100644 --- a/bsp/imxrt/libraries/drivers/drv_hwtimer.h +++ b/bsp/imxrt/libraries/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_i2c.c b/bsp/imxrt/libraries/drivers/drv_i2c.c index 6f66a68451..c01af7f5bb 100644 --- a/bsp/imxrt/libraries/drivers/drv_i2c.c +++ b/bsp/imxrt/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_i2c.h b/bsp/imxrt/libraries/drivers/drv_i2c.h index 52e7d91dc1..4ed7546e79 100644 --- a/bsp/imxrt/libraries/drivers/drv_i2c.h +++ b/bsp/imxrt/libraries/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_ksz8081.c b/bsp/imxrt/libraries/drivers/drv_ksz8081.c index 1a4c2aaf2a..5ed5fa3b84 100644 --- a/bsp/imxrt/libraries/drivers/drv_ksz8081.c +++ b/bsp/imxrt/libraries/drivers/drv_ksz8081.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.c b/bsp/imxrt/libraries/drivers/drv_lcd.c index dab6e49594..3a6d7459b7 100644 --- a/bsp/imxrt/libraries/drivers/drv_lcd.c +++ b/bsp/imxrt/libraries/drivers/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.h b/bsp/imxrt/libraries/drivers/drv_lcd.h index 3ed9e90cc1..b5a5c37f28 100644 --- a/bsp/imxrt/libraries/drivers/drv_lcd.h +++ b/bsp/imxrt/libraries/drivers/drv_lcd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_log.h b/bsp/imxrt/libraries/drivers/drv_log.h index e1b61708cc..2d44d4e901 100644 --- a/bsp/imxrt/libraries/drivers/drv_log.h +++ b/bsp/imxrt/libraries/drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_lpadc.c b/bsp/imxrt/libraries/drivers/drv_lpadc.c index 2ef4439509..8f4f9b10be 100644 --- a/bsp/imxrt/libraries/drivers/drv_lpadc.c +++ b/bsp/imxrt/libraries/drivers/drv_lpadc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_lpadc.h b/bsp/imxrt/libraries/drivers/drv_lpadc.h index 4de600b483..2aca3ca8d8 100644 --- a/bsp/imxrt/libraries/drivers/drv_lpadc.h +++ b/bsp/imxrt/libraries/drivers/drv_lpadc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.c b/bsp/imxrt/libraries/drivers/drv_mdio.c index 98f8d3a5c8..0c8076f237 100644 --- a/bsp/imxrt/libraries/drivers/drv_mdio.c +++ b/bsp/imxrt/libraries/drivers/drv_mdio.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.h b/bsp/imxrt/libraries/drivers/drv_mdio.h index 25fab7eb23..5b5c8c1884 100644 --- a/bsp/imxrt/libraries/drivers/drv_mdio.h +++ b/bsp/imxrt/libraries/drivers/drv_mdio.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c b/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c index 53b2911d00..8d0e43013d 100644 --- a/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c +++ b/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_pwm.c b/bsp/imxrt/libraries/drivers/drv_pwm.c index 7cd9739ad2..1a4f0042ab 100644 --- a/bsp/imxrt/libraries/drivers/drv_pwm.c +++ b/bsp/imxrt/libraries/drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_pwm.h b/bsp/imxrt/libraries/drivers/drv_pwm.h index 162ff7e0ee..264d464e76 100644 --- a/bsp/imxrt/libraries/drivers/drv_pwm.h +++ b/bsp/imxrt/libraries/drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_rtc.c b/bsp/imxrt/libraries/drivers/drv_rtc.c index c7e9ad58d2..6ad15416c2 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtc.c +++ b/bsp/imxrt/libraries/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_rtc.h b/bsp/imxrt/libraries/drivers/drv_rtc.h index 7328cf7794..7a3b2aaadf 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtc.h +++ b/bsp/imxrt/libraries/drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_rtl8211f.c b/bsp/imxrt/libraries/drivers/drv_rtl8211f.c index d8bb8ff28a..43e50c7eb9 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtl8211f.c +++ b/bsp/imxrt/libraries/drivers/drv_rtl8211f.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_sai.c b/bsp/imxrt/libraries/drivers/drv_sai.c index 5dcdf52bfc..98c8a99bc7 100644 --- a/bsp/imxrt/libraries/drivers/drv_sai.c +++ b/bsp/imxrt/libraries/drivers/drv_sai.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_sai.h b/bsp/imxrt/libraries/drivers/drv_sai.h index 936f4705c2..6033fd6684 100644 --- a/bsp/imxrt/libraries/drivers/drv_sai.h +++ b/bsp/imxrt/libraries/drivers/drv_sai.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_sdio.c b/bsp/imxrt/libraries/drivers/drv_sdio.c index bac2766639..2a900f3892 100644 --- a/bsp/imxrt/libraries/drivers/drv_sdio.c +++ b/bsp/imxrt/libraries/drivers/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_sdram.h b/bsp/imxrt/libraries/drivers/drv_sdram.h index 159f61a15e..49a111bd76 100644 --- a/bsp/imxrt/libraries/drivers/drv_sdram.h +++ b/bsp/imxrt/libraries/drivers/drv_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_spi.c b/bsp/imxrt/libraries/drivers/drv_spi.c index 8e3957fde9..d0ce55b35d 100644 --- a/bsp/imxrt/libraries/drivers/drv_spi.c +++ b/bsp/imxrt/libraries/drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_spi.h b/bsp/imxrt/libraries/drivers/drv_spi.h index ccd4b00724..c0667709ac 100644 --- a/bsp/imxrt/libraries/drivers/drv_spi.h +++ b/bsp/imxrt/libraries/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_uart.c b/bsp/imxrt/libraries/drivers/drv_uart.c index 72c28f225f..3160e870b4 100644 --- a/bsp/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/imxrt/libraries/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_uart.h b/bsp/imxrt/libraries/drivers/drv_uart.h index 187918b4c1..f4ca385e69 100644 --- a/bsp/imxrt/libraries/drivers/drv_uart.h +++ b/bsp/imxrt/libraries/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_usbd.c b/bsp/imxrt/libraries/drivers/drv_usbd.c index 547e6c5988..77ebd82f2c 100644 --- a/bsp/imxrt/libraries/drivers/drv_usbd.c +++ b/bsp/imxrt/libraries/drivers/drv_usbd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_usbh.c b/bsp/imxrt/libraries/drivers/drv_usbh.c index fd80d6ab54..bf18586159 100644 --- a/bsp/imxrt/libraries/drivers/drv_usbh.c +++ b/bsp/imxrt/libraries/drivers/drv_usbh.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_usbh.h b/bsp/imxrt/libraries/drivers/drv_usbh.h index 7f6fc3dbb9..ab2801e904 100644 --- a/bsp/imxrt/libraries/drivers/drv_usbh.h +++ b/bsp/imxrt/libraries/drivers/drv_usbh.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_wdt.c b/bsp/imxrt/libraries/drivers/drv_wdt.c index 402fc29295..6010754c54 100644 --- a/bsp/imxrt/libraries/drivers/drv_wdt.c +++ b/bsp/imxrt/libraries/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/drivers/drv_wdt.h b/bsp/imxrt/libraries/drivers/drv_wdt.h index 49ddc08245..7f4a5fd31f 100644 --- a/bsp/imxrt/libraries/drivers/drv_wdt.h +++ b/bsp/imxrt/libraries/drivers/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c b/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c index 4365059073..cac77214c1 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/MCUX_Config/pin_mux.c b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/MCUX_Config/pin_mux.c index 9b699b74db..488525497e 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/MCUX_Config/pin_mux.c +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/MCUX_Config/pin_mux.c @@ -25,10 +25,10 @@ pin_labels: #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ - * + * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. - * + * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { } diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c index c93ea67ea4..53fc078d10 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h index 100b932ebd..180a2c6f69 100644 --- a/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h +++ b/bsp/imxrt/libraries/templates/imxrt1050xxx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c b/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c index 12c9d0df52..2095c10651 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/MCUX_Config/pin_mux.c b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/MCUX_Config/pin_mux.c index e72885535a..d484af62a5 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/MCUX_Config/pin_mux.c +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/MCUX_Config/pin_mux.c @@ -30,10 +30,10 @@ pin_labels: #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ - * + * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. - * + * * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { } diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c index 40435501dd..23d3c088aa 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h index 4dd28fd5dd..8ef5219bd1 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.c index eb175fac24..2e05990395 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.c +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.c @@ -13,8 +13,8 @@ #elif defined(__ICCARM__) #pragma location=".boot_hdr.ivt" #endif -/************************************* - * IVT Data +/************************************* + * IVT Data *************************************/ const ivt image_vector_table = { IVT_HEADER, /* IVT Header */ @@ -32,14 +32,14 @@ const ivt image_vector_table = { #elif defined(__ICCARM__) #pragma location=".boot_hdr.boot_data" #endif -/************************************* - * Boot Data +/************************************* + * Boot Data *************************************/ const BOOT_DATA_T boot_data = { FLASH_BASE, /* boot start location */ FLASH_SIZE, /* size */ PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + 0xFFFFFFFF /* empty - extra data word */ }; #endif diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.h index 4ace76c8a1..b22ad21bc0 100644 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.h +++ b/bsp/imxrt/libraries/templates/imxrt1064xxx/xip/fsl_flexspi_nor_boot.h @@ -11,8 +11,8 @@ #include #include "board.h" -/************************************* - * IVT Data +/************************************* + * IVT Data *************************************/ typedef struct _ivt_ { /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields @@ -50,7 +50,7 @@ typedef struct _ivt_ { ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) -/* IVT header */ +/* IVT header */ #define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ #define IVT_SIZE 0x2000 #define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) @@ -60,8 +60,8 @@ typedef struct _ivt_ { #if defined(__CC_ARM) extern uint32_t __Vectors[]; extern uint32_t Image$$RW_m_config_text$$Base[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) -#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) #elif defined(__MCUXPRESSO) extern uint32_t __Vectors[]; extern uint32_t __boot_hdr_start__[]; @@ -70,13 +70,13 @@ typedef struct _ivt_ { #elif defined(__ICCARM__) extern uint32_t __VECTOR_TABLE[]; extern uint32_t m_boot_hdr_conf_start[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) #elif defined(__GNUC__) extern uint32_t __VECTOR_TABLE[]; extern uint32_t __FLASH_BASE[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) #endif #define DCD_ADDRESS dcd_data @@ -84,14 +84,14 @@ typedef struct _ivt_ { #define CSF_ADDRESS 0 #define IVT_RSVD (uint32_t)(0x00000000) -/************************************* - * Boot Data +/************************************* + * Boot Data *************************************/ typedef struct _boot_data_ { uint32_t start; /* boot start location */ uint32_t size; /* size */ uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ - uint32_t placeholder; /* placehoder to make even 0x10 size */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ }BOOT_DATA_T; #define FLASH_SIZE BOARD_FLASH_SIZE