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[bsp][rt1061] 新增飞凌 ok1061-s 开发板 bsp (#7468)
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mainmenu "RT-Thread Configuration"
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "../libraries/Kconfig"
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source "board/Kconfig"
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# OK1061-S 开发板 BSP 说明
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## 简介
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本文档为 RT-Thread 开发团队为飞凌 OK1061-S 开发板提供的 BSP (板级支持包) 说明。
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主要内容如下：
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- 开发板资源介绍
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- BSP 快速上手
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- 进阶使用方法
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 开发板介绍
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OK1061-S 开发板基于 NXP 公司 i.MX RT1061 跨界处理器设计，搭载 ARM Cortex -M7 内核，集微控制器的低功耗、易用性与应用处理器的高性能、高扩展性于一体。底板+核心板分离结构，采用邮票孔封装设计，核心板体积小巧仅30×30×3mm，引脚数量100PIN，间距1.0mm，方便嵌入各种尺寸的设备中。
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运行频率 528MHz(商业级为600MHz)，1MB片上SRAM多达 512KB 可配置为紧耦合存储器 (TCM)，QSPI-Nor Flash 支持容量4MB。底板+核心板分离结构，采用邮票孔封装设计，核心板体积小巧仅30×30×3mm，引脚数量100PIN，间距1.0mm，方便嵌入各种尺寸的设备中。为了更大限度发挥CPU特性，核心板引出CPU大部分功能，同时配备了一系列特别适合实时应用的功能，例如高速GPIO 、CAN-FD，以及同步并行 NAND/NOR/PSRAM 控制器。工业级设计核心板，运行温宽 -40℃~+85℃；为了更加方便客户评估使用，OK1061-S开发板引出UART、Ethernet*2、USB、CAN、CAN FD、HS_GPIO、PWM、ADC等丰富外设功能；支持裸机，FreeRTOS等实时系统。
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开发板外观如下图所示：
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<figure>
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<img src = "./figures/board.png" width=300 ">
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</figure>
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该开发板常用**板载资源**如下：
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- MCU：MIMXRT1061CVL5B，主频 600MHz，1024KB RAM(512 KB 可配置为 TCM)
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- 外部 FLASH：型号 25Q32JVSIQ，4MB
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- 常用接口：RS232、SD 卡接口、以太网接口、USB Host、USB OTG等
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- 调试接口：SWD
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开发板更多详细信息请参考飞凌嵌入式 [OK1061-S 开发板](https://www.forlinx.com/product/rs1061-45.html)。
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## 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :---------- | :----: | :----------------------- |
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| RS232 | 支持 | UART1 |
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| LED | 支持 | |
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| Ethernet | 暂不支持 | |
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| SD 卡 | 暂不支持 | |
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| EEPROM | 暂不支持 | |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | |
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| UART | 支持 | UART1、UART2 |
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| SPI | 暂不支持 | 即将支持 |
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| IIC | 暂不支持 | 即将支持 |
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| ADC | 暂不支持 | 即将支持 |
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| RTC | 暂不支持 | 即将支持 |
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| PWM | 暂不支持 | 即将支持 |
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| CAN | 暂不支持 | 即将支持 |
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## Keil IDE 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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#### 硬件连接
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使用数据线连接开发板到 PC，打开电源开关。
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#### 编译下载
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首先需要将需要将 RT1061 的 FLASH 下载算法（board目录下的 MIMXRT_QSPIFLASH.FLM 文件）拷贝到 `MDK 安装路径/ARM/Flash` 文件夹中。双击 `project.uvprojx` 文件，打开 MDK5 工程，在调试选项里 `Flash Download` 一栏中按照下图所示选择下载算法并保存设置：
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<figure>
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<img src = "./figures/flash.png" width=360>
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</figure>
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编译工程，工程默认配置使用 CMSIS-DAP 下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板。
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#### 运行结果
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下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，蓝色 LED 会周期性闪烁。
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连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 5.0.1 build May 9 2023 15:35:22
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2006 - 2022 Copyright by RT-Thread team
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msh >
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```
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### 进阶使用
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此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
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3. 输入 `pkgs --update` 命令更新软件包。
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4. 输入 `scons --target=mdk5/iar` 命令重新生成工程。
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本章节更多详细的介绍请参考 [IMXRT系列BSP外设驱动使用教程](../docs/IMXRT系列BSP外设驱动使用教程.md)。
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## 联系人信息
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维护人:
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- [xym-ee](https://github.com/xym-ee)
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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if rtconfig.PLATFORM == 'armcc':
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
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# overwrite cflags, because cflags has '--C99'
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CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
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else:
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
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CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM in ['iccarm']:
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env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/libraries'):
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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imxrt_library = 'MIMXRT1061'
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rtconfig.BSP_LIBRARY_TYPE = imxrt_library
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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import rtconfig
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from building import *
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import os
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd]
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# add for startup script
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if rtconfig.PLATFORM in ['gcc']:
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CPPDEFINES = ['__START=entry']
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else:
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CPPDEFINES = []
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
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list = os.listdir(cwd)
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for item in list:
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if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
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group = group + SConscript(os.path.join(item, 'SConscript'))
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Return('group')
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-05-09 xym-ee first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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/* defined the LED pin: GPIO1_IO9 */
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#define LED0_PIN GET_PIN(1,9)
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int main(void)
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{
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/* set LED0 pin mode to output */
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rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
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while (1)
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{
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rt_pin_write(LED0_PIN, PIN_HIGH);
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rt_thread_mdelay(500);
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rt_pin_write(LED0_PIN, PIN_LOW);
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rt_thread_mdelay(500);
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}
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}
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menu "Hardware Drivers Config"
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config SOC_IMXRT1061CVL5A
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bool
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select SOC_IMXRT1060_SERIES
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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menu "On-chip Peripheral Drivers"
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config BSP_USING_DMA
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bool "Enable DMA"
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default n
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config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN
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default y
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menuconfig BSP_USING_LPUART
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bool "Enable UART"
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select RT_USING_SERIAL
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default y
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if BSP_USING_LPUART
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config BSP_USING_LPUART1
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bool "Enable LPUART1"
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default y
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config BSP_LPUART1_RX_USING_DMA
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bool "Enable LPUART1 RX DMA"
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depends on BSP_USING_LPUART1
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select BSP_USING_DMA
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select RT_SERIAL_USING_DMA
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default n
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config BSP_LPUART1_RX_DMA_CHANNEL
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depends on BSP_LPUART1_RX_USING_DMA
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int "Set LPUART1 RX DMA channel (0-32)"
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default 0
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config BSP_LPUART1_TX_USING_DMA
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bool "Enable LPUART1 TX DMA"
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depends on BSP_USING_LPUART1
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select BSP_USING_DMA
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select RT_SERIAL_USING_DMA
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default n
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config BSP_LPUART1_TX_DMA_CHANNEL
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depends on BSP_LPUART1_TX_USING_DMA
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int "Set LPUART1 TX DMA channel (0-32)"
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default 1
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config BSP_USING_LPUART2
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bool "Enable LPUART2"
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default n
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config BSP_LPUART2_RX_USING_DMA
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bool "Enable LPUART2 RX DMA"
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depends on BSP_USING_LPUART2
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select BSP_USING_DMA
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select RT_SERIAL_USING_DMA
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default n
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config BSP_LPUART2_RX_DMA_CHANNEL
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depends on BSP_LPUART2_RX_USING_DMA
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int "Set LPUART2 RX DMA channel (0-32)"
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default 2
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config BSP_LPUART2_TX_USING_DMA
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bool "Enable LPUART2 TX DMA"
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depends on BSP_USING_LPUART2
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select BSP_USING_DMA
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select RT_SERIAL_USING_DMA
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default n
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config BSP_LPUART2_TX_DMA_CHANNEL
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depends on BSP_LPUART2_TX_USING_DMA
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int "Set LPUART2 TX DMA channel (0-32)"
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default 3
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endif
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endmenu
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menu "Onboard Peripheral Drivers"
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config BSP_USING_RS232
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bool "Enable RS232"
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select BSP_USING_LPUART1
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default n
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endmenu
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menu "Board extended module Drivers"
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endmenu
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endmenu
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File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,116 @@
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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||||
* Definitions
|
||||
******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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||||
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/*!
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* @brief This function executes default configuration of clocks.
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*
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||||
*/
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void BOARD_InitBootClocks(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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||||
******************************************************************************/
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||||
/*******************************************************************************
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||||
* Definitions for BOARD_BootClockRUN configuration
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||||
******************************************************************************/
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
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||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 264000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 261818181UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v13.1
|
||||
processor: MIMXRT1061xxxxB
|
||||
package_id: MIMXRT1061CVL5B
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 13.0.2
|
||||
pin_labels:
|
||||
- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BSP_BEEP}
|
||||
- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: BSP_RS485_RE, identifier: CSI_D7}
|
||||
- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: BSP_DS18B20, identifier: CSI_D6}
|
||||
- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: BSP_AP3216C_INT, identifier: CSI_MCLK}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
|
||||
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
|
||||
- {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02}
|
||||
- {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0U);
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,57 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
Binary file not shown.
@@ -0,0 +1,17 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
board.c
|
||||
MCUX_Config/clock_config.c
|
||||
MCUX_Config/pin_mux.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
|
||||
CPPDEFINES = ['CPU_MIMXRT1061CVL5A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-01-05 Bernard first implementation
|
||||
* 2023-05-09 xym-ee port to this bsp
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
#ifdef BSP_USING_DMA
|
||||
#include "fsl_dmamux.h"
|
||||
#include "fsl_edma.h"
|
||||
#endif
|
||||
|
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
/* MPU configuration. */
|
||||
static void BOARD_ConfigMPU(void)
|
||||
{
|
||||
/* Disable I cache and D cache */
|
||||
SCB_DisableICache();
|
||||
SCB_DisableDCache();
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* Region 0 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 1 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 2 setting */
|
||||
// spi flash: normal type, cacheable, no bufferable, no shareable
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 3 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 4 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 5 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 6 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
#if defined(BSP_USING_SDRAM)
|
||||
/* Region 7 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
|
||||
/* Region 8 setting */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||
#endif
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_DMA
|
||||
void imxrt_dma_init(void)
|
||||
{
|
||||
edma_config_t config;
|
||||
|
||||
DMAMUX_Init(DMAMUX);
|
||||
EDMA_GetDefaultConfig(&config);
|
||||
EDMA_Init(DMA0, &config);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
|
||||
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
|
||||
#ifdef BSP_USING_DMA
|
||||
imxrt_dma_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-09-22 Bernard add board.h to this bsp
|
||||
* 2023-05-09 xym-ee port to this bsp
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "clock_config.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __CC_ARM
|
||||
extern int Image$$RTT_HEAP$$ZI$$Base;
|
||||
extern int Image$$RTT_HEAP$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base)
|
||||
#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit)
|
||||
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
extern void __RTT_HEAP_END;
|
||||
#define HEAP_END (&__RTT_HEAP_END)
|
||||
|
||||
#else
|
||||
extern int heap_start;
|
||||
extern int heap_end;
|
||||
#define HEAP_BEGIN (&heap_start)
|
||||
#define HEAP_END (&heap_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
_load_dcdc_trim()
|
||||
{
|
||||
__var ocotp_base;
|
||||
__var ocotp_fuse_bank0_base;
|
||||
__var dcdc_base;
|
||||
__var reg;
|
||||
__var trim_value;
|
||||
__var dcdc_trim_loaded;
|
||||
__var index;
|
||||
|
||||
ocotp_base = 0x401F4000;
|
||||
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
|
||||
dcdc_base = 0x40080000;
|
||||
|
||||
dcdc_trim_loaded = 0;
|
||||
|
||||
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
|
||||
if (reg & (1<<10))
|
||||
{
|
||||
// DCDC: REG0->VBG_TRM
|
||||
trim_value = (reg & (0x1F << 11)) >> 11;
|
||||
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
|
||||
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
|
||||
dcdc_trim_loaded = 1;
|
||||
}
|
||||
|
||||
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
|
||||
if (reg & (1<<30))
|
||||
{
|
||||
index = (reg & (3 << 28)) >> 28;
|
||||
if (index < 4)
|
||||
{
|
||||
// DCDC: REG3->TRG
|
||||
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
|
||||
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
|
||||
dcdc_trim_loaded = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (dcdc_trim_loaded)
|
||||
{
|
||||
// delay 1ms for dcdc to get stable
|
||||
__delay(1);
|
||||
__message "DCDC trim value loaded.\n";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
_load_dcdc_trim();
|
||||
}
|
||||
|
||||
execUserReset()
|
||||
{
|
||||
_load_dcdc_trim();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1062CVJ5A
|
||||
** MIMXRT1062CVL5A
|
||||
** MIMXRT1062DVJ6A
|
||||
** MIMXRT1062DVL6A
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1060RM Rev. B, 07/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b180801
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol m_interrupts_start = 0x60002000;
|
||||
define symbol m_interrupts_end = 0x600023FF;
|
||||
|
||||
define symbol m_text_start = 0x60002400;
|
||||
define symbol m_text_end = 0x607FFFFF;
|
||||
|
||||
define symbol m_data_start = 0x20000000;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x202BFFFF;
|
||||
|
||||
define exported symbol m_boot_hdr_conf_start = 0x60000000;
|
||||
define symbol m_boot_hdr_ivt_start = 0x60001000;
|
||||
define symbol m_boot_hdr_boot_data_start = 0x60001020;
|
||||
define symbol m_boot_hdr_dcd_data_start = 0x60001030;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
|
||||
define exported symbol __RTT_HEAP_END = m_data2_end;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
|
||||
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
|
||||
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
|
||||
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
|
||||
|
||||
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in DATA_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,88 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1062CVJ5A
|
||||
** MIMXRT1062CVL5A
|
||||
** MIMXRT1062DVJ6A
|
||||
** MIMXRT1062DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev. B, 07/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b180819
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x003FDC00
|
||||
|
||||
#define m_data_start 0x20200000
|
||||
#define m_data_size 0x00100000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
|
||||
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
|
||||
}
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 267 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 25 KiB |
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,162 @@
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m7'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
#BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
|
||||
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Os'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
|
||||
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
|
||||
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
|
||||
' -shared -fPIC -nostartfiles -static-libgcc'
|
||||
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU + '.fp.sp'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
|
||||
|
||||
CFLAGS += ' --diag_suppress=66,1296,186,6134'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' --c99'
|
||||
|
||||
POST_ACTION = 'fromelf -z $TARGET'
|
||||
# POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' -D__FPU_PRESENT'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=' + CPU
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=None'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' -Ol'
|
||||
CFLAGS += ' --use_c++_inline'
|
||||
|
||||
AFLAGS = ''
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu ' + CPU
|
||||
AFLAGS += ' --fpu None'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --redirect _Printf=_PrintfTiny'
|
||||
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
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|
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<Header>### uVision Project, (C) Keil Software</Header>
|
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|
||||
<Extensions>
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<cExt>*.c</cExt>
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<aExt>*.s*; *.src; *.a*</aExt>
|
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<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
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||||
<CppX>*.cpp</CppX>
|
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<nMigrate>0</nMigrate>
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<dwHighDateTime>0</dwHighDateTime>
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<TargetName>rtthread</TargetName>
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<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
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<BeepAtEnd>1</BeepAtEnd>
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||||
<RunSim>0</RunSim>
|
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<RunTarget>1</RunTarget>
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<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
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<OPTHX>
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<HexSelection>1</HexSelection>
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<FlashByte>65535</FlashByte>
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<HexRangeLowAddress>0</HexRangeLowAddress>
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<HexRangeHighAddress>0</HexRangeHighAddress>
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<HexOffset>0</HexOffset>
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</OPTHX>
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<OPTLEX>
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<PageWidth>79</PageWidth>
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<PageLength>66</PageLength>
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<TabStop>8</TabStop>
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<ListingPath>.\build\keil\List\</ListingPath>
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</OPTLEX>
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<ListingPage>
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<CreateCListing>1</CreateCListing>
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<CreateAListing>1</CreateAListing>
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<LMap>1</LMap>
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<LComments>1</LComments>
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<OPTFL>
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<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<IsCurrentTarget>1</IsCurrentTarget>
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</OPTFL>
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<CpuCode>8</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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<sLdApp>1</sLdApp>
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<sRwatch>1</sRwatch>
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<sRfunc>1</sRfunc>
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<sRbox>1</sRbox>
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<tRwatch>1</tRwatch>
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<sDll></sDll>
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<sDlgPa></sDlgPa>
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<sIfile></sIfile>
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<tDll></tDll>
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<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
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<tIfile>.\flexspi_nor.ini</tIfile>
|
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<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
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<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
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||||
<Number>0</Number>
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||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC8000 -FD20000000 -FF0MIMXRT106x_QSPI_4KB_SEC -FL0800000 -FS060000000 -FP0($$Device:MIMXRT1061CVL5A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)</Name>
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||||
</SetRegEntry>
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<SetRegEntry>
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<Number>0</Number>
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<Key>CMSIS_AGDI</Key>
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||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC8000 -FD20000000 -FF0MIMXRT106x_QSPI_4KB_SEC -FL0800000 -FS060000000 -FP0($$Device:MIMXRT1061CVL5A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)</Name>
|
||||
</SetRegEntry>
|
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</TargetDriverDllRegistry>
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<Breakpoint/>
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<Tracepoint>
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<THDelay>0</THDelay>
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<DebugFlag>
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<trace>0</trace>
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<periodic>0</periodic>
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<aLwin>0</aLwin>
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<aPa>0</aPa>
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<aLa>0</aLa>
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<aPa1>0</aPa1>
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<aSer4>0</aSer4>
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<StkLoc>0</StkLoc>
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<TrcWin>0</TrcWin>
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<newCpu>0</newCpu>
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<uProt>0</uProt>
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</DebugFlag>
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<LintExecutable></LintExecutable>
|
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<LintConfigFile></LintConfigFile>
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<bLintAuto>0</bLintAuto>
|
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<bAutoGenD>0</bAutoGenD>
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<LntExFlags>0</LntExFlags>
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<pMisraName></pMisraName>
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<pszMrule></pszMrule>
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<pSingCmds></pSingCmds>
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<pMultCmds></pMultCmds>
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<pMisraNamep></pMisraNamep>
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<pszMrulep></pszMrulep>
|
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<pSingCmdsp></pSingCmdsp>
|
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<pMultCmdsp></pMultCmdsp>
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<DebugDescription>
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<Enable>1</Enable>
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<EnableFlashSeq>1</EnableFlashSeq>
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<EnableLog>0</EnableLog>
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<Protocol>2</Protocol>
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<DbgClock>10000000</DbgClock>
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</DebugDescription>
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</TargetOption>
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</Target>
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|
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</ProjectOpt>
|
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File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,121 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
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@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
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@@ -0,0 +1,74 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_xcc.h
|
||||
* @brief CMSIS DSP Core Peripheral Access Layer Header File
|
||||
* @version V1.0
|
||||
* @date 20. January 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CORE_DSP_H_GENERIC
|
||||
#define __CORE_DSP_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#define __BKPT(value) do {} while(0)
|
||||
#define __NOP() do {} while(0)
|
||||
|
||||
#define NVIC_SetPriorityGrouping(value) do {} while(0)
|
||||
#define NVIC_GetPriorityGrouping() do {} while(0)
|
||||
#define NVIC_EnableIRQ(value) do {} while(0)
|
||||
#define NVIC_GetEnableIRQ(value) do {} while(0)
|
||||
#define NVIC_DisableIRQ(value) do {} while(0)
|
||||
#define NVIC_GetPendingIRQ(value) do {} while(0)
|
||||
#define NVIC_SetPendingIRQ(value) do {} while(0)
|
||||
#define NVIC_ClearPendingIRQ(value) do {} while(0)
|
||||
#define NVIC_GetActive(value) do {} while(0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_DSP_H_GENERIC */
|
||||
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@@ -0,0 +1,197 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U
|
||||
#define ARM_MPU_AP_PRIV 1U
|
||||
#define ARM_MPU_AP_URO 2U
|
||||
#define ARM_MPU_AP_FULL 3U
|
||||
#define ARM_MPU_AP_PRO 5U
|
||||
#define ARM_MPU_AP_RO 6U
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(MPU_RASR_ENABLE_Msk))
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,90 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1061CVJ5A
|
||||
** MIMXRT1061CVL5A
|
||||
** MIMXRT1061DVJ6A
|
||||
** MIMXRT1061DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b190312
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x007FDC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_data2_start 0x20200000
|
||||
#define m_data2_size 0x000C0000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,100 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1061CVJ5A
|
||||
** MIMXRT1061CVL5A
|
||||
** MIMXRT1061DVJ6A
|
||||
** MIMXRT1061DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b190312
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x007FDC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x01E00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x20200000
|
||||
#define m_data3_size 0x000C0000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,71 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1061CVJ5A
|
||||
** MIMXRT1061CVL5A
|
||||
** MIMXRT1061DVJ6A
|
||||
** MIMXRT1061DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b190312
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_data2_start 0x20200000
|
||||
#define m_data2_size 0x000C0000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,81 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1061CVJ5A
|
||||
** MIMXRT1061CVL5A
|
||||
** MIMXRT1061DVJ6A
|
||||
** MIMXRT1061DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b190312
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x00000400
|
||||
#define m_text_size 0x0001FC00
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x01E00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x20200000
|
||||
#define m_data3_size 0x000C0000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,81 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1061CVJ5A
|
||||
** MIMXRT1061CVL5A
|
||||
** MIMXRT1061DVJ6A
|
||||
** MIMXRT1061DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b190312
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_interrupts_start 0x80000000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x80000400
|
||||
#define m_text_size 0x001FFC00
|
||||
|
||||
#define m_data_start 0x20200000
|
||||
#define m_data_size 0x000C0000
|
||||
|
||||
#define m_data2_start 0x20000000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
#define m_data3_start 0x80200000
|
||||
#define m_data3_size 0x01C00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
}
|
||||
Binary file not shown.
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_aipstz.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.aipstz"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* brief Configure the privilege level for master.
|
||||
*
|
||||
* param base AIPSTZ peripheral base pointer
|
||||
* param master Masters for AIPSTZ.
|
||||
* param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t.
|
||||
*/
|
||||
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
|
||||
{
|
||||
uint32_t mask = ((uint32_t)master >> 8) - 1;
|
||||
uint32_t shift = (uint32_t)master & 0xFF;
|
||||
base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Configure the access for peripheral.
|
||||
*
|
||||
* param base AIPSTZ peripheral base pointer
|
||||
* param master Peripheral for AIPSTZ.
|
||||
* param accessControl Configuration is ORed from aipstz_peripheral_access_control_t.
|
||||
*/
|
||||
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
|
||||
{
|
||||
volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
|
||||
uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
|
||||
uint32_t shift = (uint32_t)peripheral & 0xFF;
|
||||
|
||||
*reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
|
||||
}
|
||||
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_AIPSTZ_H_
|
||||
#define _FSL_AIPSTZ_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup aipstz
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of AIPSTZ privilege configuration.*/
|
||||
typedef enum _aipstz_master_privilege_level
|
||||
{
|
||||
kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
|
||||
kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
|
||||
kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
|
||||
kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
|
||||
} aipstz_master_privilege_level_t;
|
||||
|
||||
/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
|
||||
typedef enum _aipstz_master
|
||||
{
|
||||
kAIPSTZ_Master0 = (0x400U | 28U),
|
||||
kAIPSTZ_Master1 = (0x400U | 24U),
|
||||
kAIPSTZ_Master2 = (0x400U | 20U),
|
||||
kAIPSTZ_Master3 = (0x400U | 16U),
|
||||
kAIPSTZ_Master5 = (0x400U | 8U)
|
||||
} aipstz_master_t;
|
||||
|
||||
/*! @brief List of AIPSTZ peripheral access control configuration.*/
|
||||
typedef enum _aipstz_peripheral_access_control
|
||||
{
|
||||
kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
|
||||
kAIPSTZ_PeripheralWriteProtected = (1U << 1),
|
||||
kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
|
||||
kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
|
||||
} aipstz_peripheral_access_control_t;
|
||||
|
||||
/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and
|
||||
* shift for lower 8 bits.*/
|
||||
typedef enum _aipstz_peripheral
|
||||
{
|
||||
kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
|
||||
} aipstz_peripheral_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configure the privilege level for master.
|
||||
*
|
||||
* @param base AIPSTZ peripheral base pointer
|
||||
* @param master Masters for AIPSTZ.
|
||||
* @param privilegeConfig Configuration is ORed from @aipstz_master_privilege_level_t.
|
||||
*/
|
||||
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig);
|
||||
|
||||
/*!
|
||||
* @brief Configure the access for peripheral.
|
||||
*
|
||||
* @param base AIPSTZ peripheral base pointer
|
||||
* @param master Peripheral for AIPSTZ.
|
||||
* @param accessControl Configuration is ORed from @aipstz_peripheral_access_control_t.
|
||||
*/
|
||||
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_AIPSTZ_H_ */
|
||||
@@ -0,0 +1,199 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include "fsl_aoi.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.aoi"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to aoi bases for each instance. */
|
||||
static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to aoi clocks for each instance. */
|
||||
static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for AOI module.
|
||||
*
|
||||
* @param base AOI peripheral base address
|
||||
*
|
||||
* @return The AOI instance
|
||||
*/
|
||||
static uint32_t AOI_GetInstance(AOI_Type *base);
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t AOI_GetInstance(AOI_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++)
|
||||
{
|
||||
if (s_aoiBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_aoiBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes an AOI instance for operation.
|
||||
*
|
||||
* This function un-gates the AOI clock.
|
||||
*
|
||||
* param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Init(AOI_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the clock gate from clock manager. */
|
||||
CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Deinitializes an AOI instance for operation.
|
||||
*
|
||||
* This function shutdowns AOI module.
|
||||
*
|
||||
* param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Deinit(AOI_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the clock gate from clock manager */
|
||||
CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Gets the Boolean evaluation associated.
|
||||
*
|
||||
* This function returns the Boolean evaluation associated.
|
||||
*
|
||||
* Example:
|
||||
code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
|
||||
endcode
|
||||
*
|
||||
* param base AOI peripheral address.
|
||||
* param event Index of the event which will be set of type aoi_event_t.
|
||||
* param config Selected input configuration .
|
||||
*/
|
||||
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
|
||||
{
|
||||
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
|
||||
assert(config != NULL);
|
||||
|
||||
uint16_t value = 0;
|
||||
/* Read BFCRT01 register at event index. */
|
||||
value = base->BFCRT[event].BFCRT01;
|
||||
|
||||
config->PT0AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT);
|
||||
config->PT0BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT);
|
||||
config->PT0CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT);
|
||||
config->PT0DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT);
|
||||
|
||||
config->PT1AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT);
|
||||
config->PT1BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT);
|
||||
config->PT1CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT);
|
||||
config->PT1DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT);
|
||||
|
||||
/* Read BFCRT23 register at event index. */
|
||||
value = 0;
|
||||
value = base->BFCRT[event].BFCRT23;
|
||||
|
||||
config->PT2AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT);
|
||||
config->PT2BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT);
|
||||
config->PT2CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT);
|
||||
config->PT2DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT);
|
||||
|
||||
config->PT3AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT);
|
||||
config->PT3BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT);
|
||||
config->PT3CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT);
|
||||
config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Configures an AOI event.
|
||||
*
|
||||
* This function configures an AOI event according
|
||||
* to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D)
|
||||
* of all product terms (0, 1, 2, and 3) of a desired event.
|
||||
*
|
||||
* Example:
|
||||
code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
|
||||
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
|
||||
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT0DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT1AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT2AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT3AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3DC = kAOI_LogicOne;
|
||||
|
||||
AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
|
||||
endcode
|
||||
*
|
||||
* param base AOI peripheral address.
|
||||
* param event Event which will be configured of type aoi_event_t.
|
||||
* param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
|
||||
* filling out the members of this structure and passing the pointer to this function.
|
||||
*/
|
||||
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
|
||||
{
|
||||
assert(eventConfig != NULL);
|
||||
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
|
||||
|
||||
uint16_t value = 0;
|
||||
/* Calculate value to configure product term 0, 1 */
|
||||
value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) |
|
||||
AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) |
|
||||
AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) |
|
||||
AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC);
|
||||
/* Write value to register */
|
||||
base->BFCRT[event].BFCRT01 = value;
|
||||
|
||||
/* Reset and calculate value to configure product term 2, 3 */
|
||||
value = 0;
|
||||
value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) |
|
||||
AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) |
|
||||
AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) |
|
||||
AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC);
|
||||
/* Write value to register */
|
||||
base->BFCRT[event].BFCRT23 = value;
|
||||
}
|
||||
@@ -0,0 +1,186 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_AOI_H_
|
||||
#define _FSL_AOI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup aoi
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifndef AOI
|
||||
#define AOI AOI0 /*!< AOI peripheral address */
|
||||
#endif
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief AOI input configurations.
|
||||
*
|
||||
* The selection item represents the Boolean evaluations.
|
||||
*/
|
||||
typedef enum _aoi_input_config
|
||||
{
|
||||
kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */
|
||||
kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */
|
||||
kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */
|
||||
kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */
|
||||
} aoi_input_config_t;
|
||||
|
||||
/*!
|
||||
* @brief AOI event indexes, where an event is the collection of the four product
|
||||
* terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
|
||||
*/
|
||||
typedef enum _aoi_event
|
||||
{
|
||||
kAOI_Event0 = 0x0U, /*!< Event 0 index */
|
||||
kAOI_Event1 = 0x1U, /*!< Event 1 index */
|
||||
kAOI_Event2 = 0x2U, /*!< Event 2 index */
|
||||
kAOI_Event3 = 0x3U /*!< Event 3 index */
|
||||
} aoi_event_t;
|
||||
|
||||
/*!
|
||||
* @brief AOI event configuration structure
|
||||
*
|
||||
* Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make
|
||||
* whole event configuration.
|
||||
*/
|
||||
typedef struct _aoi_event_config
|
||||
{
|
||||
aoi_input_config_t PT0AC; /*!< Product term 0 input A */
|
||||
aoi_input_config_t PT0BC; /*!< Product term 0 input B */
|
||||
aoi_input_config_t PT0CC; /*!< Product term 0 input C */
|
||||
aoi_input_config_t PT0DC; /*!< Product term 0 input D */
|
||||
aoi_input_config_t PT1AC; /*!< Product term 1 input A */
|
||||
aoi_input_config_t PT1BC; /*!< Product term 1 input B */
|
||||
aoi_input_config_t PT1CC; /*!< Product term 1 input C */
|
||||
aoi_input_config_t PT1DC; /*!< Product term 1 input D */
|
||||
aoi_input_config_t PT2AC; /*!< Product term 2 input A */
|
||||
aoi_input_config_t PT2BC; /*!< Product term 2 input B */
|
||||
aoi_input_config_t PT2CC; /*!< Product term 2 input C */
|
||||
aoi_input_config_t PT2DC; /*!< Product term 2 input D */
|
||||
aoi_input_config_t PT3AC; /*!< Product term 3 input A */
|
||||
aoi_input_config_t PT3BC; /*!< Product term 3 input B */
|
||||
aoi_input_config_t PT3CC; /*!< Product term 3 input C */
|
||||
aoi_input_config_t PT3DC; /*!< Product term 3 input D */
|
||||
} aoi_event_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @name AOI Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes an AOI instance for operation.
|
||||
*
|
||||
* This function un-gates the AOI clock.
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Init(AOI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes an AOI instance for operation.
|
||||
*
|
||||
* This function shutdowns AOI module.
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Deinit(AOI_Type *base);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name AOI Get Set Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the Boolean evaluation associated.
|
||||
*
|
||||
* This function returns the Boolean evaluation associated.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
|
||||
@endcode
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
* @param event Index of the event which will be set of type aoi_event_t.
|
||||
* @param config Selected input configuration .
|
||||
*/
|
||||
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures an AOI event.
|
||||
*
|
||||
* This function configures an AOI event according
|
||||
* to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D)
|
||||
* of all product terms (0, 1, 2, and 3) of a desired event.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
|
||||
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
|
||||
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT0DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT1AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT2AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT3AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3DC = kAOI_LogicOne;
|
||||
|
||||
AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
|
||||
@endcode
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
* @param event Event which will be configured of type aoi_event_t.
|
||||
* @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
|
||||
* filling out the members of this structure and passing the pointer to this function.
|
||||
*/
|
||||
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!* @} */
|
||||
|
||||
#endif /* _FSL_AOI_H_*/
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,147 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#define SDK_MEM_MAGIC_NUMBER 12345U
|
||||
|
||||
typedef struct _mem_align_control_block
|
||||
{
|
||||
uint16_t identifier; /*!< Identifier for the memory control block. */
|
||||
uint16_t offset; /*!< offset from aligned address to real address */
|
||||
} mem_align_cb_t;
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.common"
|
||||
#endif
|
||||
|
||||
#ifndef __GIC_PRIO_BITS
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||
{
|
||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
extern uint32_t Image$$RW_m_data$$Base[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
|
||||
uint32_t n;
|
||||
uint32_t ret;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* Copy the vector table from ROM to RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* Point the VTOR to the position of vector table */
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
ret = __VECTOR_RAM[irq + 16];
|
||||
/* make sure the __VECTOR_RAM is noncachable */
|
||||
__VECTOR_RAM[irq + 16] = irqHandler;
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
#endif /* __GIC_PRIO_BITS. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
|
||||
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
|
||||
uint32_t index = 0;
|
||||
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERSET[index] = 1u << intNumber;
|
||||
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||
}
|
||||
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
|
||||
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||
uint32_t index = 0;
|
||||
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERCLR[index] = 1u << intNumber;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||
{
|
||||
mem_align_cb_t *p_cb = NULL;
|
||||
uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
|
||||
void *p_align_addr, *p_addr = malloc(alignedsize);
|
||||
|
||||
if (!p_addr)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
|
||||
|
||||
p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U);
|
||||
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
|
||||
p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
|
||||
|
||||
return (void *)p_align_addr;
|
||||
}
|
||||
|
||||
void SDK_Free(void *ptr)
|
||||
{
|
||||
mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U);
|
||||
|
||||
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
free((void *)((uint32_t)ptr - p_cb->offset));
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_dmamux.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.dmamux"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Get instance number for DMAMUX.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
*/
|
||||
static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Array to map DMAMUX instance number to base pointer. */
|
||||
static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Array to map DMAMUX instance number to clock name. */
|
||||
static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++)
|
||||
{
|
||||
if (s_dmamuxBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_dmamuxBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function ungates the DMAMUX clock.
|
||||
*
|
||||
* param base DMAMUX peripheral base address.
|
||||
*
|
||||
*/
|
||||
void DMAMUX_Init(DMAMUX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Deinitializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function gates the DMAMUX clock.
|
||||
*
|
||||
* param base DMAMUX peripheral base address.
|
||||
*/
|
||||
void DMAMUX_Deinit(DMAMUX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
@@ -0,0 +1,177 @@
|
||||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_DMAMUX_H_
|
||||
#define _FSL_DMAMUX_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup dmamux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief DMAMUX driver version 2.0.3. */
|
||||
#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* @name DMAMUX Initialization and de-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function ungates the DMAMUX clock.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
*
|
||||
*/
|
||||
void DMAMUX_Init(DMAMUX_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the DMAMUX peripheral.
|
||||
*
|
||||
* This function gates the DMAMUX clock.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
*/
|
||||
void DMAMUX_Deinit(DMAMUX_Type *base);
|
||||
|
||||
/* @} */
|
||||
/*!
|
||||
* @name DMAMUX Channel Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the DMAMUX channel.
|
||||
*
|
||||
* This function enables the DMAMUX channel.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the DMAMUX channel.
|
||||
*
|
||||
* This function disables the DMAMUX channel.
|
||||
*
|
||||
* @note The user must disable the DMAMUX channel before configuring it.
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configures the DMAMUX channel source.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
* @param source Channel source, which is used to trigger the DMA transfer.
|
||||
*/
|
||||
static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
|
||||
/*!
|
||||
* @brief Enables the DMAMUX period trigger.
|
||||
*
|
||||
* This function enables the DMAMUX period trigger feature.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the DMAMUX period trigger.
|
||||
*
|
||||
* This function disables the DMAMUX period trigger.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
*/
|
||||
static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK;
|
||||
}
|
||||
#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
|
||||
|
||||
#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
|
||||
/*!
|
||||
* @brief Enables the DMA channel to be always ON.
|
||||
*
|
||||
* This function enables the DMAMUX channel always ON feature.
|
||||
*
|
||||
* @param base DMAMUX peripheral base address.
|
||||
* @param channel DMAMUX channel number.
|
||||
* @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
|
||||
*/
|
||||
static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
|
||||
|
||||
if (enable)
|
||||
{
|
||||
base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* _FSL_DMAMUX_H_ */
|
||||
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