Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-03-28 02:03:20 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #3328 from wangyq2018/es32f0654

Browse Source 
[bsp]update essemi/es32f0654.
This commit is contained in:
Bernard Xiong
2020-01-14 11:59:14 +08:00
committed by GitHub
parent 4886a7fb5f 696b130afe
commit b5caf6f5ef
151 changed files with 21659 additions and 27693 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
bsp/es32f0654/drivers/drv_pm.c
View File

@@ -1,74 +0,0 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-01 wangyq the first version
* 2019-05-06 Zero-Free adapt to the new power management interface
*/
#include <rthw.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_pm.h"
#include <ald_pmu.h>
#ifdef RT_USING_PM
static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode)
{
switch (mode)
{
case PM_SLEEP_MODE_NONE:
break;
case PM_SLEEP_MODE_IDLE:
__WFI();
break;
case PM_SLEEP_MODE_LIGHT:
break;
case PM_SLEEP_MODE_DEEP:
pmu_stop2_enter();
break;
case PM_SLEEP_MODE_STANDBY:
pmu_standby_enter(PMU_STANDBY_PORT_NONE);
break;
case PM_SLEEP_MODE_SHUTDOWN:
break;
default:
RT_ASSERT(0);
break;
}
}
static int drv_hw_pm_init(void)
{
static const struct rt_pm_ops _ops =
{
_drv_pm_enter,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL
};
rt_uint8_t timer_mask = 0;
/* initialize timer mask(no need tickless) */
timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
/* initialize system pm module */
rt_system_pm_init(&_ops, timer_mask, RT_NULL);
return 0;
}
INIT_BOARD_EXPORT(drv_hw_pm_init);
#endif

BIN
bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf
View File

Binary file not shown.

793
bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf
View File

File diff suppressed because it is too large Load Diff

6665
bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h
View File

File diff suppressed because it is too large Load Diff

1763
bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h
View File

File diff suppressed because it is too large Load Diff

1937
bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h
View File

File diff suppressed because it is too large Load Diff

2512
bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h
View File

File diff suppressed because it is too large Load Diff

707
bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h
View File

File diff suppressed because it is too large Load Diff

14
bsp/es32f0654/libraries/CMSIS/index.html
View File

@@ -1,14 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Redirect to the CMSIS main page after 0 seconds</title>
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
</body>
</html>

374
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h
View File

@@ -1,374 +0,0 @@
/**
*********************************************************************************
*
* @file ald_acmp.h
* @brief Header file of ACMP module driver.
*
* @version V1.0
* @date 13 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_ACMP_H__
#define __ALD_ACMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup ACMP
* @{
*/
/** @defgroup ACMP_Public_Types ACMP Public Types
* @{
*/
/**
* @brief Acmp interrupt
*/
typedef enum
{
ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */
ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */
} acmp_it_t;
/**
* @brief Acmp interrupt
*/
typedef enum
{
ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_flag_t;
/**
* @brief Acmp interrupt flag
*/
typedef enum
{
ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_status_t;
/**
* @brief Acmp positive input
*/
typedef enum
{
ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */
} acmp_pos_input_t;
/**
* @brief Acmp negative input
*/
typedef enum
{
ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10, /**< VDD as negative input */
ACMP_NEG_CAP = 11, /**< Capacitive as negative input */
ACMP_NEG_DAC0_CH0 = 12, /**< DAC0 channel 0 as negative input */
ACMP_NEG_DAC0_CH1 = 13, /**< DAC0 channel 1 as negative input */
} acmp_neg_input_t;
/**
* @brief Acmp mode
*/
typedef enum
{
ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */
ACMP_LOW_POWER = 1, /**< Low power mode */
ACMP_MIDDLE_POWER = 2, /**< Middle power mode */
ACMP_HIGH_POWER = 3, /**< High power mode */
} acmp_mode_t;
/**
* @brief Acmp warm-up time
*/
typedef enum
{
ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */
} acmp_warm_time_t;
/**
* @brief Acmp hysteresis level
*/
typedef enum
{
ACMP_HYST_0 = 0, /**< No hysteresis */
ACMP_HYST_15 = 1, /**< 15mV hysteresis */
ACMP_HYST_22 = 2, /**< 22mV hysteresis */
ACMP_HYST_29 = 3, /**< 29mV hysteresis */
ACMP_HYST_36 = 4, /**< 36mV hysteresis */
ACMP_HYST_43 = 5, /**< 43mV hysteresis */
ACMP_HYST_50 = 6, /**< 50mV hysteresis */
ACMP_HYST_57 = 7, /**< 57mV hysteresis */
} acmp_hystsel_t;
/**
* @brief Acmp inactive state
*/
typedef enum
{
ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */
} acmp_inactval_t;
/**
* @brief which edges set up interrupt
*/
typedef enum
{
ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */
} acmp_edge_t;
/**
* @brief Acmp output function
*/
typedef enum
{
ACMP_OUT_DISABLE = 0, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1, /**< Enable acmp output */
} acmp_out_func_t;
/**
* @brief Acmp warm-up interrupt function
*/
typedef enum
{
ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */
} acmp_warm_it_func;
/**
* @brief Acmp gpio output invert
*/
typedef enum
{
ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */
} acmp_invert_t;
/**
* @brief The location of the acmp i/o pin
*/
typedef enum
{
ACMP_LOCATION_O = 0, /**< Location 0 */
ACMP_LOCATION_1 = 1, /**< Location 1 */
ACMP_LOCATION_2 = 2, /**< Location 2 */
} acmp_location_t;
/**
* @brief Acmp output config structure definition
*/
typedef struct
{
acmp_out_func_t out_func; /**< Acmp output function */
acmp_invert_t gpio_inv; /**< If invert gpio output */
acmp_location_t location; /**< The location of acmp I/0 pin */
} acmp_output_config_t;
/**
* @brief Acmp init structure definition
*/
typedef struct
{
acmp_mode_t mode; /**< Acmp operation mode */
acmp_warm_time_t warm_time; /**< Acmp warm up time */
acmp_hystsel_t hystsel; /**< Acmp hysteresis level */
acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */
acmp_pos_input_t pos_port; /**< Acmp positive port select */
acmp_neg_input_t neg_port; /**< Acmp negative port select */
acmp_inactval_t inactval; /**< Acmp inavtive output value */
acmp_edge_t edge; /** Select edges to set interrupt flag */
uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */
} acmp_init_t;
/**
* @brief ACMP Handle Structure definition
*/
typedef struct acmp_handle_s
{
ACMP_TypeDef *perh; /**< Register base address */
acmp_init_t init; /**< ACMP required parameters */
lock_state_t lock; /**< Locking object */
void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */
void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */
} acmp_handle_t;
/**
* @}
*/
/** @defgroup ACMP_Public_Macros ACMP Public Macros
* @{
*/
#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
/**
* @}
*/
/** @defgroup ACMP_Private_Macros ACMP Private Macros
* @{
*/
#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \
((x) == ACMP1))
#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \
((x) == ACMP_LOW_POWER) || \
((x) == ACMP_MIDDLE_POWER) || \
((x) == ACMP_HIGH_POWER))
#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \
((x) == ACMP_IT_WARMUP))
#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \
((x) == ACMP_FLAG_WARMUP))
#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \
((x) == ACMP_STATUS_WARMUP))
#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \
((x) == ACMP_POS_CH1) || \
((x) == ACMP_POS_CH2) || \
((x) == ACMP_POS_CH3) || \
((x) == ACMP_POS_CH4) || \
((x) == ACMP_POS_CH5) || \
((x) == ACMP_POS_CH6) || \
((x) == ACMP_POS_CH7))
#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \
((x) == ACMP_NEG_CH1) || \
((x) == ACMP_NEG_CH2) || \
((x) == ACMP_NEG_CH3) || \
((x) == ACMP_NEG_CH4) || \
((x) == ACMP_NEG_CH5) || \
((x) == ACMP_NEG_CH6) || \
((x) == ACMP_NEG_CH7) || \
((x) == ACMP_NEG_1V25) || \
((x) == ACMP_NEG_2V5) || \
((x) == ACMP_NEG_VDD) || \
((x) == ACMP_NEG_CAP) || \
((x) == ACMP_NEG_DAC0_CH0) || \
((x) == ACMP_NEG_DAC0_CH1))
#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \
((x) == ACMP_8_PCLK) || \
((x) == ACMP_16_PCLK) || \
((x) == ACMP_32_PCLK) || \
((x) == ACMP_64_PCLK) || \
((x) == ACMP_128_PCLK) || \
((x) == ACMP_256_PCLK) || \
((x) == ACMP_512_PCLK))
#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \
((x) == ACMP_HYST_15) || \
((x) == ACMP_HYST_22) || \
((x) == ACMP_HYST_29) || \
((x) == ACMP_HYST_36) || \
((x) == ACMP_HYST_43) || \
((x) == ACMP_HYST_50) || \
((x) == ACMP_HYST_57))
#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \
((x) == ACMP_INACTVAL_HIGH))
#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \
((x) == ACMP_EDGE_FALL) || \
((x) == ACMP_EDGE_RISE) || \
((x) == ACMP_EDGE_ALL))
#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \
((x) == ACMP_OUT_ENABLE))
#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \
((x) == ACMP_GPIO_INV))
#define IS_ACMP_LOCATION_TYPE(x) (((x) == ACMP_LOCATION_O) || \
((x) == ACMP_LOCATION_1) || \
((x) == ACMP_LOCATION_2))
#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \
((x) == ACMP_WARM_ENABLE))
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions
* @{
*/
/** @addtogroup ACMP_Public_Functions_Group1
* @{
*/
ald_status_t acmp_init(acmp_handle_t *hperh);
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions_Group2
* @{
*/
ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
ald_status_t acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it);
it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag);
/**
* @}
*/
/** @addtogroup ACMP_Public_Functions_Group3
* @{
*/
void acmp_irq_handle(acmp_handle_t *hperh);
ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config);
uint8_t acmp_out_result(acmp_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
extern "C"
}
#endif
#endif

585
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h
View File

File diff suppressed because it is too large Load Diff

186
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
View File

@@ -1,186 +0,0 @@
/**
*********************************************************************************
*
* @file ald_bkpc.h
* @brief Header file of BKPC module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_BKPC_H__
#define __ALD_BKPC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup BKPC
* @{
*/
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55))
#define BKPC_LRC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup BKPC_Public_Types BKPC Public Types
* @{
*/
/**
* @brief BKPC ldo output select
*/
typedef enum
{
BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief BKPC BOR voltage select
*/
typedef enum
{
BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */
BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */
BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */
BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */
BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */
BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */
BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */
BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */
BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */
BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */
BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */
BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */
BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */
BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */
BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */
BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */
} bkpc_bor_vol_t;
/**
* @}
*/
/**
* @defgroup BKPC_Private_Macros BKPC Private Macros
* @{
*/
#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \
((x) == BKPC_BOR_VOL_2_0) || \
((x) == BKPC_BOR_VOL_2_1) || \
((x) == BKPC_BOR_VOL_2_2) || \
((x) == BKPC_BOR_VOL_2_3) || \
((x) == BKPC_BOR_VOL_2_4) || \
((x) == BKPC_BOR_VOL_2_5) || \
((x) == BKPC_BOR_VOL_2_6) || \
((x) == BKPC_BOR_VOL_2_8) || \
((x) == BKPC_BOR_VOL_3_0) || \
((x) == BKPC_BOR_VOL_3_1) || \
((x) == BKPC_BOR_VOL_3_3) || \
((x) == BKPC_BOR_VOL_3_6) || \
((x) == BKPC_BOR_VOL_3_7) || \
((x) == BKPC_BOR_VOL_4_0) || \
((x) == BKPC_BOR_VOL_4_3))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions
* @{
*/
/** @addtogroup BKPC_Public_Functions_Group1
* @{
*/
/* control functions */
extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions_Group2
* @{
*/
/* IO operation functions */
extern void bkpc_write_ram(uint8_t idx, uint32_t value);
extern uint32_t bkpc_read_ram(uint8_t idx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_BKPC_H__ */

485
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h
View File

@@ -1,485 +0,0 @@
/**
******************************************************************************
* @file ald_can.h
* @brief Header file of CAN Module driver.
*
* @version V1.0
* @date 16 Apr 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
******************************************************************************
*/
#ifndef __ALD_CAN_H
#define __ALD_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CAN
* @{
*/
/** @defgroup CAN_Public_Types CAN Public Types
* @{
*/
/**
* @brief ALD State structures definition
*/
typedef enum
{
CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */
CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */
CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */
CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */
CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */
CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */
CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */
CAN_STATE_ERROR = 0x04, /**< CAN error state */
} can_state_t;
/**
* @brief CAN Error Code
*/
typedef enum
{
CAN_ERROR_NONE = 0x00, /**< No error */
CAN_ERROR_EWG = 0x01, /**< EWG error */
CAN_ERROR_EPV = 0x02, /**< EPV error */
CAN_ERROR_BOF = 0x04, /**< BOF error */
CAN_ERROR_STF = 0x08, /**< Stuff error */
CAN_ERROR_FOR = 0x10, /**< Form error */
CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */
CAN_ERROR_BR = 0x40, /**< Bit recessive */
CAN_ERROR_BD = 0x80, /**< LEC dominant */
CAN_ERROR_CRC = 0x100, /**< LEC transfer error */
} can_error_t;
/**
* @brief CAN Operating Mode
*/
typedef enum
{
CAN_MODE_NORMAL = 0x00, /**< Normal mode */
CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */
CAN_MODE_SILENT = 0x02, /**< Silent mode */
CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */
} can_operate_mode_t;
/**
* @brief CAN Synchronization Jump Width
*/
typedef enum
{
CAN_SJW_1 = 0x0, /**< 1 time quantum */
CAN_SJW_2 = 0x1, /**< 2 time quantum */
CAN_SJW_3 = 0x2, /**< 3 time quantum */
CAN_SJW_4 = 0x3, /**< 4 time quantum */
} can_sjw_t;
/**
* @brief CAN Time Quantum in Bit Segment 1
*/
typedef enum
{
CAN_SEG1_1 = 0x0, /**< 1 time quantum */
CAN_SEG1_2 = 0x1, /**< 2 time quantum */
CAN_SEG1_3 = 0x2, /**< 3 time quantum */
CAN_SEG1_4 = 0x3, /**< 4 time quantum */
CAN_SEG1_5 = 0x4, /**< 5 time quantum */
CAN_SEG1_6 = 0x5, /**< 6 time quantum */
CAN_SEG1_7 = 0x6, /**< 7 time quantum */
CAN_SEG1_8 = 0x7, /**< 8 time quantum */
CAN_SEG1_9 = 0x8, /**< 9 time quantum */
CAN_SEG1_10 = 0x9, /**< 10 time quantum */
CAN_SEG1_11 = 0xA, /**< 11 time quantum */
CAN_SEG1_12 = 0xB, /**< 12 time quantum */
CAN_SEG1_13 = 0xC, /**< 13 time quantum */
CAN_SEG1_14 = 0xD, /**< 14 time quantum */
CAN_SEG1_15 = 0xE, /**< 15 time quantum */
CAN_SEG1_16 = 0xF, /**< 16 time quantum */
} can_seg1_t;
/**
* @brief CAN Time Quantum in Bit Segment 2
*/
typedef enum
{
CAN_SEG2_1 = 0x0, /**< 1 time quantum */
CAN_SEG2_2 = 0x1, /**< 2 time quantum */
CAN_SEG2_3 = 0x2, /**< 3 time quantum */
CAN_SEG2_4 = 0x3, /**< 4 time quantum */
CAN_SEG2_5 = 0x4, /**< 5 time quantum */
CAN_SEG2_6 = 0x5, /**< 6 time quantum */
CAN_SEG2_7 = 0x6, /**< 7 time quantum */
CAN_SEG2_8 = 0x7, /**< 8 time quantum */
} can_seg2_t;
/**
* @brief CAN Filter Mode
*/
typedef enum
{
CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */
CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */
} can_filter_mode_t;
/**
* @brief CAN Filter Scale
*/
typedef enum
{
CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */
CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */
} can_filter_scale_t;
/**
* @brief CAN Filter fifo
*/
typedef enum
{
CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */
CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */
} can_filter_fifo_t;
/**
* @brief CAN Identifier Type
*/
typedef enum
{
CAN_ID_STD = 0x0, /**< Standard Id */
CAN_ID_EXT = 0x1, /**< Extended Id */
} can_id_type_t;
/**
* @brief CAN Remote Transmission Request
*/
typedef enum
{
CAN_RTR_DATA = 0x0, /**< Data frame */
CAN_RTR_REMOTE = 0x1, /**< Remote frame */
} can_remote_req_t;
/**
* @brief CAN Transmit Constants
*/
typedef enum
{
CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */
CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */
CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */
CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */
} can_tx_mailbox_t;
/**
* @brief CAN Receive fifo Number
*/
typedef enum
{
CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */
CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */
} can_rx_fifo_t;
/**
* @brief CAN Flags
*/
typedef enum
{
CAN_FLAG_SLAK = (1U << 1), /**< Sleep acknowledge flag */
CAN_FLAG_WKU = (1U << 3), /**< Wake up flag */
CAN_FLAG_SLAKI = (1U << 4), /**< Sleep acknowledge flag */
CAN_FLAG_RQCP0 = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */
CAN_FLAG_TXOK0 = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */
CAN_FLAG_RQCP1 = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */
CAN_FLAG_TXOK1 = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */
CAN_FLAG_RQCP2 = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */
CAN_FLAG_TXOK2 = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */
CAN_FLAG_TME0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */
CAN_FLAG_TME1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */
CAN_FLAG_TME2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */
CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */
CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */
CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */
CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */
CAN_FLAG_EWG = (4U << 20) | (1U << 0), /**< Error warning flag */
CAN_FLAG_EPV = (4U << 20) | (1U << 1), /**< Error passive flag */
CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */
} can_flag_t;
/**
* @brief CAN Interrupts
*/
typedef enum
{
CAN_IT_TME = (1U << 0), /**< Transmit mailbox empty interrupt bit */
CAN_IT_FMP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */
CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */
CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */
CAN_IT_FMP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */
CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */
CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */
CAN_IT_EWG = (1U << 8), /**< Error warning interrupt bit */
CAN_IT_EPV = (1U << 9), /**< Error passive interrupt bit */
CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */
CAN_IT_LEC = (1U << 11), /**< Last error code interrupt bit */
CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */
CAN_IT_WKU = (1U << 16), /**< wake-up interrupt bit */
CAN_IT_SLK = (1U << 17), /**< sleep interrupt bit */
} can_it_t;
/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t id_high; /**< Specifies the filter identification number */
uint32_t id_low; /**< Specifies the filter identification number */
uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */
uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */
can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */
uint32_t number; /**< Specifies the filter which will be initialized. */
can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */
can_filter_scale_t scale; /**< Specifies the filter scale. */
type_func_t active; /**< Enable or disable the filter. */
uint32_t bank_number; /**< Select the start slave bank filter. */
} can_filter_t;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t psc; /**< Specifies the length of a time quantum. */
can_operate_mode_t mode; /**< Specifies the CAN operating mode. */
can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is
allowed to lengthen or shorten a bit to perform resynchronization. */
can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */
can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */
type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */
type_func_t abom; /**< Enable or disable the automatic bus-off management. */
type_func_t awk; /**< Enable or disable the automatic wake-up mode. */
type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */
type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */
type_func_t txmp; /**< Enable or disable the transmit fifo priority. */
} can_init_t;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t std; /**< Specifies the standard identifier. */
uint32_t ext; /**< Specifies the extended identifier. */
can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */
can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */
uint32_t len; /**< Specifies the length of the frame that will be transmitted. */
uint8_t data[8]; /**< Contains the data to be transmitted. */
} can_tx_msg_t;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t std; /**< Specifies the standard identifier. */
uint32_t ext; /**< Specifies the extended identifier. */
can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */
can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */
uint32_t len; /**< Specifies the length of the frame that will be received. */
uint8_t data[8]; /**< Contains the data to be received. */
uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */
can_rx_fifo_t num; /**< Specifies the receive fifo number. */
} can_rx_msg_t;
/**
* @brief CAN handle Structure definition
*/
typedef struct can_handle_s
{
CAN_TypeDef *perh; /**< Register base address */
can_init_t init; /**< CAN required parameters */
can_rx_msg_t *rx_msg; /**< Pointer to receive message */
lock_state_t lock; /**< CAN locking object */
can_state_t state; /**< CAN communication state */
can_error_t err; /**< CAN Error code */
void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct can_handle_s *arg); /**< error callback */
} can_handle_t;
/**
* @}
*/
/** @defgroup CAN_Public_Macro CAN Public Macros
* @{
*/
#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET)
#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \
(READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK)))
#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))
/**
* @}
*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_ALL(x) ((x) == CAN0)
#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13)
#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \
((x) == CAN_MODE_LOOPBACK) || \
((x) == CAN_MODE_SILENT) || \
((x) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \
((x) == CAN_SJW_2) || \
((x) == CAN_SJW_3) || \
((x) == CAN_SJW_4))
#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16)
#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8)
#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \
((x) == CAN_FILTER_MODE_LIST))
#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \
((x) == CAN_FILTER_SCALE_32))
#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \
((x) == CAN_FILTER_FIFO1))
#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \
((x) == CAN_ID_EXT))
#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))
#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))
#define IS_CAN_BANKNUMBER(x) ((x) <= 28)
#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE)
#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF))
#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF))
#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08))
#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024))
#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLAK) || \
((x) == CAN_FLAG_WKU) || \
((x) == CAN_FLAG_SLAKI) || \
((x) == CAN_FLAG_RQCP0) || \
((x) == CAN_FLAG_TXOK0) || \
((x) == CAN_FLAG_RQCP1) || \
((x) == CAN_FLAG_TXOK1) || \
((x) == CAN_FLAG_RQCP2) || \
((x) == CAN_FLAG_TXOK2) || \
((x) == CAN_FLAG_TME0) || \
((x) == CAN_FLAG_TME1) || \
((x) == CAN_FLAG_TME2) || \
((x) == CAN_FLAG_FF0) || \
((x) == CAN_FLAG_FOV0) || \
((x) == CAN_FLAG_FF1) || \
((x) == CAN_FLAG_FOV1) || \
((x) == CAN_FLAG_EWG) || \
((x) == CAN_FLAG_EPV) || \
((x) == CAN_FLAG_BOF))
#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_WKU) || \
((x) == CAN_FLAG_SLAKI) || \
((x) == CAN_FLAG_RQCP0) || \
((x) == CAN_FLAG_RQCP1) || \
((x) == CAN_FLAG_RQCP2) || \
((x) == CAN_FLAG_FF0) || \
((x) == CAN_FLAG_FOV0) || \
((x) == CAN_FLAG_FF1) || \
((x) == CAN_FLAG_FOV1))
#define IS_CAN_IT(x) (((x) == CAN_IT_TME) || \
((x) == CAN_IT_FMP0) || \
((x) == CAN_IT_FF0) || \
((x) == CAN_IT_FOV0) || \
((x) == CAN_IT_FMP1) || \
((x) == CAN_IT_FF1) || \
((x) == CAN_IT_FOV1) || \
((x) == CAN_IT_EWG) || \
((x) == CAN_IT_EPV) || \
((x) == CAN_IT_BOF) || \
((x) == CAN_IT_LEC) || \
((x) == CAN_IT_ERR) || \
((x) == CAN_IT_WKU) || \
((x) == CAN_IT_SLK))
#define CAN_TIMEOUT_VALUE 100
#define CAN_STATE_TX_MASK (1U << 4)
#define CAN_STATE_RX_MASK (1U << 5)
/**
* @}
*/
/** @addtogroup CAN_Public_Functions
* @{
*/
/** @addtogroup CAN_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void can_reset(can_handle_t *hperh);
ald_status_t can_init(can_handle_t *hperh);
ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config);
/**
* @}
*/
/** @addtogroup CAN_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout);
ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg);
ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout);
ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg);
/**
* @}
*/
/** @addtogroup CAN_Public_Functions_Group3
* @{
*/
/* Control function */
ald_status_t can_sleep(can_handle_t *hperh);
ald_status_t can_wake_up(can_handle_t *hperh);
void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box);
void can_irq_handler(can_handle_t *hperh);
type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box);
void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state);
it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it);
flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag);
void can_clear_flag_status(can_handle_t *hperh, can_flag_t flag);
/**
* @}
*/
/** @addtogroup CAN_Public_Functions_Group4
* @{
*/
/* State and Error functions */
can_state_t can_get_state(can_handle_t *hperh);
can_error_t can_get_error(can_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_CAN_H */

632
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h
View File

File diff suppressed because it is too large Load Diff

197
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h
View File

@@ -1,197 +0,0 @@
/**
*********************************************************************************
*
* @file ald_crc.h
* @brief Header file of CRC module driver.
*
* @version V1.0
* @date 6 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRC_H__
#define __ALD_CRC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Public_Types CRC Public Types
* @{
*/
/**
* @brief CRC mode
*/
typedef enum
{
CRC_MODE_CCITT = 0, /**< Ccitt */
CRC_MODE_8 = 1, /**< Crc8 */
CRC_MODE_16 = 2, /**< Crc16 */
CRC_MODE_32 = 3, /**< Crc32 */
} crc_mode_t;
/**
* @brief CRC input length
*/
typedef enum
{
CRC_LEN_AUTO = 0, /**< Auto */
CRC_DATASIZE_8 = 1, /**< Byte */
CRC_DATASIZE_16 = 2, /**< Half word */
CRC_DATASIZE_32 = 3, /**< Word */
} crc_datasize_t;
/**
* @brief CRC whether write error or no
*/
typedef enum
{
CRC_WERR_NO = 0, /**< No error */
CRC_WERR_ERR = 1, /**< Error */
} crc_werr_t;
/**
* @brief CRC state structures definition
*/
typedef enum
{
CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4, /**< Error */
} crc_state_t;
/**
* @brief CRC init structure definition
*/
typedef struct
{
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
type_func_t chs_rev; /**< CRC check sum reverse or no */
type_func_t chs_inv; /**< CRC check sum inverse or no */
uint32_t seed; /**< CRC seed */
} crc_init_t;
/**
* @brief CRC Handle Structure definition
*/
typedef struct crc_handle_s
{
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */
uint32_t *cal_res; /**< The pointer of result */
#ifdef ALD_DMA
dma_handle_t hdma; /**< CRC DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
crc_state_t state; /**< CRC operation state */
void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
} crc_handle_t;
/**
* @}
*/
/** @defgroup CRC_Public_Macros CRC Public Macros
* @{
*/
#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
/**
* @}
*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_CRC(x) ((x) == CRC)
#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
/**
* @}
*/
/** @addtogroup CRC_Public_Functions
* @{
*/
/** @addtogroup CRC_Public_Functions_Group1
* @{
*/
ald_status_t crc_init(crc_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRC_Public_Functions_Group2
* @{
*/
uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
/**
* @}
*/
#ifdef ALD_DMA
/** @addtogroup CRC_Public_Functions_Group3
* @{
*/
ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
ald_status_t crc_dma_pause(crc_handle_t *hperh);
ald_status_t crc_dma_resume(crc_handle_t *hperh);
ald_status_t crc_dma_stop(crc_handle_t *hperh);
/**
* @}
*/
#endif
/** @addtogroup CRC_Public_Functions_Group4
* @{
*/
crc_state_t crc_get_state(crc_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_CRC_H__ */

264
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h
View File

@@ -1,264 +0,0 @@
/**
*********************************************************************************
*
* @file ald_crypt.h
* @brief Header file of CRYPT module driver.
*
* @version V1.0
* @date 7 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRYPT_H__
#define __ALD_CRYPT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRYPT
* @{
*/
/** @defgroup CRYPT_Public_Types CRYPT Public Types
* @{
*/
/**
* @brief CRYPT encrypt or decrypt select
*/
typedef enum
{
CRYPT_DECRYPT = 0, /**< Decrypt */
CRYPT_ENCRYPT = 1, /**< Encrypt */
} crypt_encs_t;
/**
* @brief CRYPT mode select
*/
typedef enum
{
CRYPT_MODE_ECB = 0, /**< ECB */
CRYPT_MODE_CBC = 1, /**< CBC */
CRYPT_MODE_CTR = 2, /**< CTR */
} crypt_mode_t;
/**
* @brief CRYPT data type
*/
typedef enum
{
CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */
} crypt_datatype_t;
/**
* @brief CRYPT interrupt
*/
typedef enum
{
CRYPT_IT_IT = 0x80, /**< Interrupt */
} crypt_it_t;
/**
* @brief CRYPT interrupt flag
*/
typedef enum
{
CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100, /**< Complete flag */
} crypt_flag_t;
/**
* @brief CRYPT state structures definition
*/
typedef enum
{
CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4, /**< Error */
} crypt_state_t;
/**
* @brief CRYPT data type
*/
typedef enum
{
DATA_32_BIT = 0, /**< 32 bit data,don't swap */
DATA_16_BIT = 1, /**< 16 bit data,swap */
DATA_8_BIT = 2, /**< 8 bit data,swap */
DATA_1_BIT = 3, /**< 1 bit data, swap */
} crypt_data_t;
/**
* @brief CRYPT init structure definition
*/
typedef struct
{
crypt_mode_t mode; /**< Crypt mode */
crypt_data_t type; /**< Data type select */
} crypt_init_t;
/**
* @brief CRYPT Handle Structure definition
*/
typedef struct crypt_handle_s
{
CRYPT_TypeDef *perh; /**< Register base address */
crypt_init_t init; /**< CRYPT required parameters */
#ifdef ALD_DMA
dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */
dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */
#endif
uint8_t *plain_text; /**< Pointer to plain text */
uint8_t *cipher_text; /**< Pointer to cipher text */
uint32_t size; /**< The size of crypt data buf */
uint32_t count; /**< The count of crypt data buf */
uint32_t step; /**< The step of once crypt 4(aes) */
uint32_t dir; /**< ENCRYPT or DECRYPT */
uint32_t iv[4]; /**< The iv of crypt */
uint32_t key[4]; /**< The key of crypt */
lock_state_t lock; /**< Locking object */
crypt_state_t state; /**< CRYPT operation state */
void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */
void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */
} crypt_handle_t;
/**
* @}
*/
/** @defgroup CRYPT_Public_Macros CRYPT Public Macros
* @{
*/
#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \
(handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)
/**
* @}
*/
/** @defgroup CRYPT_Private_Macros CRYPT Private Macros
* @{
*/
#define IS_CRYPT(x) ((x) == CRYPT)
#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \
((x) == CRYPT_MODE_CBC) || \
((x) == CRYPT_MODE_CTR))
#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \
((x) == CRYPT_FLAG_DONE))
#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \
((x) == IV_4_LEN))
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions
* @{
*/
/** @addtogroup CRYPT_Public_Functions_Group1
* @{
*/
ald_status_t crypt_init(crypt_handle_t *hperh);
ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key);
ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key);
ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv);
ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group2
* @{
*/
ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag);
ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
#ifdef ALD_DMA
ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
#endif
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group3
* @{
*/
#ifdef ALD_DMA
ald_status_t crypt_dma_pause(crypt_handle_t *hperh);
ald_status_t crypt_dma_resume(crypt_handle_t *hperh);
ald_status_t crypt_dma_stop(crypt_handle_t *hperh);
#endif
void crypt_irq_handle(crypt_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group4
* @{
*/
void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state);
flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it);
/**
* @}
*/
/** @addtogroup CRYPT_Public_Functions_Group5
* @{
*/
crypt_state_t crypt_get_state(crypt_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

389
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h
View File

@@ -1,389 +0,0 @@
/**
*********************************************************************************
*
* @file ald_dma.h
* @brief DMA module Library.
*
* @version V1.0
* @date 09 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_DMA_H__
#define __ALD_DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup DMA
* @{
*/
/**
* @defgroup DMA_Public_Macros DMA Public Macros
* @{
*/
#define DMA_CH_COUNT 6
#define DMA_ERR 31
/**
* @}
*/
/**
* @defgroup DMA_Public_Types DMA Public Types
* @{
*/
/**
* @brief Input source to DMA channel
*/
typedef enum
{
DMA_MSEL_NONE = 0x0, /**< NONE */
DMA_MSEL_GPIO = 0x1, /**< GPIO */
DMA_MSEL_CRYPT = 0x2, /**< CRYPT */
DMA_MSEL_ACMP = 0x3, /**< ACMP */
DMA_MSEL_DAC0 = 0x4, /**< DAC0 */
DMA_MSEL_ADC0 = 0x6, /**< ADC0 */
DMA_MSEL_CRC = 0x7, /**< CRC */
DMA_MSEL_UART0 = 0x8, /**< UART0 */
DMA_MSEL_UART1 = 0x9, /**< UART1 */
DMA_MSEL_UART2 = 0xA, /**< UART2 */
DMA_MSEL_UART3 = 0xB, /**< UART3 */
DMA_MSEL_USART0 = 0xC, /**< USART0 */
DMA_MSEL_USART1 = 0xD, /**< USART1 */
DMA_MSEL_SPI0 = 0xE, /**< SPI0 */
DMA_MSEL_SPI1 = 0xF, /**< SPI1 */
DMA_MSEL_I2C0 = 0x10, /**< I2C0 */
DMA_MSEL_I2C1 = 0x11, /**< I2C1 */
DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */
DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */
DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */
DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */
DMA_MSEL_RTC = 0x16, /**< RTC */
DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */
DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */
DMA_MSEL_DMA = 0x19, /**< DMA */
DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */
DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */
DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */
DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */
DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */
DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */
DMA_MSEL_PIS = 0x20, /**< PIS */
DMA_MSEL_TRNG = 0x21, /**< TRNG */
} dma_msel_t;
/**
* @brief Input signal to DMA channel
*/
typedef enum
{
DMA_MSIGSEL_NONE = 0x0, /**< NONE */
DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */
DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */
DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */
DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */
DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */
DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */
DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */
DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */
DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */
DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */
DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */
DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */
DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */
DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */
DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */
DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */
DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */
DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */
DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */
DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */
DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */
DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */
DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */
DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */
DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */
DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */
DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */
DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */
DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */
DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */
DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */
DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */
DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */
DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */
DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */
DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */
DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */
DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */
DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */
DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */
DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */
DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */
DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */
DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */
DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */
DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */
DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */
DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */
DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */
DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */
DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */
DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */
DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */
DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */
DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */
DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */
} dma_msigsel_t;
/**
* @brief DMA Descriptor control type
*/
typedef union
{
struct
{
uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */
uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */
uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */
uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */
uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */
uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */
uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */
uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */
uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */
};
uint32_t word;
} dma_ctrl_t;
/**
* @brief Channel control data structure
*/
typedef struct
{
void *src; /**< Source data end pointer */
void *dst; /**< Destination data end pointer */
dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */
uint32_t use; /**< Reserve for user */
} dma_descriptor_t;
/**
* @brief data increment
*/
typedef enum
{
DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */
DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */
DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */
DMA_DATA_INC_NONE = 0x3, /**< No increment */
} dma_data_inc_t;
/**
* @brief Data size
*/
typedef enum
{
DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */
DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */
DMA_DATA_SIZE_WORD = 0x2, /**< Word */
} dma_data_size_t;
/**
* @brief The operating mode of the DMA cycle
*/
typedef enum
{
DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */
DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */
DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */
DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */
DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */
DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */
} dma_cycle_ctrl_t;
/**
* @brief Control how many DMA transfers can occur
* before the controller re-arbitrates
*/
typedef enum
{
DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */
DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */
DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */
DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */
DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */
DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */
DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */
DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */
DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */
DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */
DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */
} dma_arbiter_config_t;
/**
* @brief Callback function pointer and param
*/
typedef struct
{
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void *arg); /**< DMA occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_call_back_t;
/**
* @brief DMA channal configure structure
*/
typedef struct
{
void *src; /**< Source data begin pointer */
void *dst; /**< Destination data begin pointer */
uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */
dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */
dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */
dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */
dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
type_func_t primary; /**< Use primary descriptor or alternate descriptor */
type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */
type_func_t high_prio; /**< High priority or default priority */
type_func_t iterrupt; /**< Enable/disable interrupt */
dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */
dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */
uint8_t channel; /**< Channel index */
} dma_config_t;
/**
* @brief DMA handle structure definition
*/
typedef struct
{
DMA_TypeDef *perh; /**< DMA registers base address */
dma_config_t config; /**< Channel configure structure. @ref dma_config_t */
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_handle_t;
/**
* @}
*/
/**
* @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG)
#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF)
#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \
((x) == DMA_DATA_INC_HALFWORD) || \
((x) == DMA_DATA_INC_WORD) || \
((x) == DMA_DATA_INC_NONE))
#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \
((x) == DMA_DATA_SIZE_HALFWORD) || \
((x) == DMA_DATA_SIZE_WORD))
#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \
((x) == DMA_CYCLE_CTRL_BASIC) || \
((x) == DMA_CYCLE_CTRL_AUTO) || \
((x) == DMA_CYCLE_CTRL_PINGPONG) || \
((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \
((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER))
#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \
((x) == DMA_R_POWER_2) || \
((x) == DMA_R_POWER_4) || \
((x) == DMA_R_POWER_8) || \
((x) == DMA_R_POWER_16) || \
((x) == DMA_R_POWER_32) || \
((x) == DMA_R_POWER_64) || \
((x) == DMA_R_POWER_128) || \
((x) == DMA_R_POWER_256) || \
((x) == DMA_R_POWER_512) || \
((x) == DMA_R_POWER_1024))
#define IS_DMA(x) ((x) == DMA0)
#define IS_DMA_CHANNEL(x) ((x) <= 5)
#define IS_DMA_DATA_SIZE(x) ((x) <= 1024)
#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31))
/**
* @}
*/
/**
* @addtogroup DMA_Public_Functions
* @{
*/
/** @addtogroup DMA_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void dma_reset(DMA_TypeDef *DMAx);
extern void dma_init(DMA_TypeDef *DMAx);
extern void dma_config_struct(dma_config_t *p);
/**
* @}
*/
/** @addtogroup DMA_Public_Functions_Group2
* @{
*/
/* Configure DMA channel functions */
extern void dma_config_auto(dma_handle_t *hperh);
extern void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
uint16_t size, uint8_t channel, void (*cbk)(void *arg));
extern void dma_config_basic(dma_handle_t *hperh);
extern void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
/**
* @}
*/
/** @addtogroup DMA_Public_Functions_Group3
* @{
*/
/* DMA control functions */
extern void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
extern void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
extern it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
extern flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
extern void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
void dma0_irq_cbk(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__ALD_DMA_H__ */

122
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h
View File

@@ -1,122 +0,0 @@
/**
*********************************************************************************
*
* @file ald_flash.h
* @brief Header file of FLASH driver
*
* @version V1.0
* @date 20 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_FLASH_H__
#define __ALD_FLASH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup FLASH
* @{
*/
/**
* @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#define FLASH_REG_UNLOCK() \
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
} \
} while (0)
#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_BASE_ADDR 0x00000000
#define FLASH_PAGE_SIZE 1024UL
#define FLASH_WORD_SIZE 8UL
#define FLASH_TOTAL_SIZE 256UL
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
#define INFO_PAGE_SIZE 1024UL
#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#ifdef USE_FLASH_FIFO
#define FLASH_FIFO 1
#else
#define FLASH_FIFO 0
#endif
/**
* @}
*/
/** @defgroup FLASH_Private_Types FLASH Private Types
* @{
*/
typedef enum
{
FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */
} flash_cmd_type;
typedef enum
{
OP_FLASH = 0, /**< Operate Pragram area */
OP_INFO = 1, /**< Operate info area */
} op_cmd_type;
/**
* @}
*/
/** @addtogroup Flash_Public_Functions
* @{
*/
ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
ald_status_t flash_erase(uint32_t addr, uint16_t len);
ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_FLASH_H__ */

288
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h
View File

@@ -1,288 +0,0 @@
/**
*********************************************************************************
*
* @file ald_gpio.h
* @brief Header file of GPIO module driver
*
* @version V1.0
* @date 07 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_GPIO_H__
#define __ALD_GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup GPIO
* @{
*/
/**
* @defgroup GPIO_Public_Macros GPIO Public Macros
* @{
*/
#define GPIO_PIN_0 (1U << 0)
#define GPIO_PIN_1 (1U << 1)
#define GPIO_PIN_2 (1U << 2)
#define GPIO_PIN_3 (1U << 3)
#define GPIO_PIN_4 (1U << 4)
#define GPIO_PIN_5 (1U << 5)
#define GPIO_PIN_6 (1U << 6)
#define GPIO_PIN_7 (1U << 7)
#define GPIO_PIN_8 (1U << 8)
#define GPIO_PIN_9 (1U << 9)
#define GPIO_PIN_10 (1U << 10)
#define GPIO_PIN_11 (1U << 11)
#define GPIO_PIN_12 (1U << 12)
#define GPIO_PIN_13 (1U << 13)
#define GPIO_PIN_14 (1U << 14)
#define GPIO_PIN_15 (1U << 15)
#define GPIO_PIN_ALL (0xFFFF)
/**
* @}
*/
/**
* @defgroup GPIO_Public_Types GPIO Public Types
* @{
*/
/**
* @brief GPIO mode
*/
typedef enum
{
GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1, /**< Input */
GPIO_MODE_OUTPUT = 0x2, /**< Output */
} gpio_mode_t;
/**
* @brief GPIO open-drain or push-pull
*/
typedef enum
{
GPIO_PUSH_PULL = 0x0, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */
GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */
} gpio_odos_t;
/**
* @brief GPIO push-up or push-down
*/
typedef enum
{
GPIO_FLOATING = 0x0,/**< Floating */
GPIO_PUSH_UP = 0x1,/**< Push-Up */
GPIO_PUSH_DOWN = 0x2,/**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */
} gpio_push_t;
/**
* @brief GPIO output drive
*/
typedef enum
{
GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */
} gpio_out_drive_t;
/**
* @brief GPIO filter
*/
typedef enum
{
GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */
} gpio_filter_t;
/**
* @brief GPIO type
*/
typedef enum
{
GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1, /**< TTL Type */
} gpio_type_t;
/**
* @brief GPIO functions
*/
typedef enum
{
GPIO_FUNC_0 = 0, /**< function #0 */
GPIO_FUNC_1 = 1, /**< function #1 */
GPIO_FUNC_2 = 2, /**< function #2 */
GPIO_FUNC_3 = 3, /**< function #3 */
GPIO_FUNC_4 = 4, /**< function #4 */
GPIO_FUNC_5 = 5, /**< function #5 */
GPIO_FUNC_6 = 6, /**< function #6 */
GPIO_FUNC_7 = 7, /**< function #7 */
} gpio_func_t;
/**
* @brief GPIO Init Structure definition
*/
typedef struct
{
gpio_mode_t mode; /**< Specifies the operating mode for the selected pins.
This parameter can be any value of @ref gpio_mode_t */
gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins.
This parameter can be a value of @ref gpio_odos_t */
gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins.
This parameter can be a value of @ref gpio_push_t */
gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins.
This parameter can be a value of @ref gpio_out_drive_t */
gpio_filter_t flt; /**< Specifies the input filter for the selected pins.
This parameter can be a value of @ref gpio_filter_t */
gpio_type_t type; /**< Specifies the type for the selected pins.
This parameter can be a value of @ref gpio_type_t */
gpio_func_t func; /**< Specifies the function for the selected pins.
This parameter can be a value of @ref gpio_func_t */
} gpio_init_t;
/**
* @brief EXTI trigger style
*/
typedef enum
{
EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */
} exti_trigger_style_t;
/**
* @brief EXTI filter clock select
*/
typedef enum
{
EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */
} exti_filter_clock_t;
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
type_func_t filter; /**< Enable filter. */
exti_filter_clock_t cks; /**< Filter clock select. */
uint8_t filter_time; /**< Filter duration */
} exti_init_t;
/**
* @}
*/
/**
* @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define PIN_MASK 0xFFFF
#define UNLOCK_KEY 0x55AA
#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \
(GPIOx == GPIOB) || \
(GPIOx == GPIOC) || \
(GPIOx == GPIOD) || \
(GPIOx == GPIOE) || \
(GPIOx == GPIOF) || \
(GPIOx == GPIOG) || \
(GPIOx == GPIOH))
#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \
((x) == GPIO_MODE_INPUT) || \
((x) == GPIO_MODE_OUTPUT))
#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \
((x) == GPIO_OPEN_DRAIN) || \
((x) == GPIO_OPEN_SOURCE))
#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \
((x) == GPIO_PUSH_UP) || \
((x) == GPIO_PUSH_DOWN) || \
((x) == GPIO_PUSH_UP_DOWN))
#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \
((x) == GPIO_OUT_DRIVE_STRONG))
#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \
((x) == GPIO_FILTER_ENABLE))
#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \
((x) == GPIO_TYPE_CMOS))
#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \
((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
((x) == EXTI_TRIGGER_BOTH_EDGE))
#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \
((x) == EXTI_FILTER_CLOCK_32K))
#define IS_GPIO_FUNC(x) ((x) <= 7)
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions
* @{
*/
/** @addtogroup GPIO_Public_Functions_Group1
* @{
*/
void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init);
void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_func_default(GPIO_TypeDef *GPIOx);
void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init);
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions_Group2
* @{
*/
uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val);
void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin);
void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
uint16_t gpio_read_port(GPIO_TypeDef *GPIOx);
void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val);
/**
* @}
*/
/** @addtogroup GPIO_Public_Functions_Group3
* @{
*/
void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status);
flag_status_t gpio_exti_get_flag_status(uint16_t pin);
void gpio_exti_clear_flag_status(uint16_t pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_GPIO_H__ */

534
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h
View File

File diff suppressed because it is too large Load Diff

633
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h
View File

File diff suppressed because it is too large Load Diff

241
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h
View File

@@ -1,241 +0,0 @@
/**
*********************************************************************************
*
* @file ald_pmu.h
* @brief Header file of PMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_PMU_H__
#define __ALD_PMU_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_syscfg.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup PMU
* @{
*/
/** @defgroup PMU_Public_Macros PMU Public Macros
* @{
*/
#define PMU_SRAM0_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM0_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
/**
* @}
*/
/** @defgroup PMU_Public_Types PMU Public Types
* @{
*/
/**
* @brief Standby wakeup port select
*/
typedef enum
{
PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */
PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */
PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */
PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */
PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */
PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */
PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */
PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */
PMU_STANDBY_PORT_NONE = 0xF, /**< NONE */
} pmu_standby_wakeup_sel_t;
/**
* @brief Low power mode
*/
typedef enum
{
PMU_LP_STOP1 = 0x0, /**< Stop1 */
PMU_LP_STOP2 = 0x1, /**< Stop2 */
PMU_LP_STANDBY = 0x2, /**< Standby */
} pmu_lp_mode_t;
typedef enum
{
PMU_SR_WUF = (1U << 0),
PMU_SR_STANDBYF = (1U << 1),
} pmu_status_t;
/**
* @brief LVD voltage select
*/
typedef enum
{
PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */
} pmu_lvd_voltage_sel_t;
/**
* @brief LVD trigger mode
*/
typedef enum
{
PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */
} pmu_lvd_trigger_mode_t;
/**
* @}
*/
/**
* @defgroup PMU_Private_Macros PMU Private Macros
* @{
*/
#define IS_PMU_STANDBY_PORT_SEL(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \
((x) == PMU_STANDBY_PORT_SEL_PA1) || \
((x) == PMU_STANDBY_PORT_SEL_PA2) || \
((x) == PMU_STANDBY_PORT_SEL_PA3) || \
((x) == PMU_STANDBY_PORT_SEL_PA4) || \
((x) == PMU_STANDBY_PORT_SEL_PA5) || \
((x) == PMU_STANDBY_PORT_SEL_PA6) || \
((x) == PMU_STANDBY_PORT_SEL_PA7) || \
((x) == PMU_STANDBY_PORT_NONE))
#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
((x) == PMU_LP_STOP2) || \
((x) == PMU_LP_STANDBY))
#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \
((x) == PMU_SR_STANDBYF))
#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \
((x) == PMU_LVD_VOL_SEL_2_1) || \
((x) == PMU_LVD_VOL_SEL_2_2) || \
((x) == PMU_LVD_VOL_SEL_2_4) || \
((x) == PMU_LVD_VOL_SEL_2_6) || \
((x) == PMU_LVD_VOL_SEL_2_8) || \
((x) == PMU_LVD_VOL_SEL_3_0) || \
((x) == PMU_LVD_VOL_SEL_3_6) || \
((x) == PMU_LVD_VOL_SEL_4_0) || \
((x) == PMU_LVD_VOL_SEL_4_6) || \
((x) == PMU_LVD_VOL_SEL_2_3) || \
((x) == PMU_LVD_VOL_SEL_EXT))
#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
((x) == PMU_LVD_TRIGGER_RISING_FALLING))
/**
* @}
*/
/** @addtogroup PMU_Public_Functions
* @{
*/
/** @addtogroup PMU_Public_Functions_Group1
* @{
*/
/* Low power mode select */
__STATIC_INLINE__ void __sleep()
{
__WFI();
}
__STATIC_INLINE__ void __sleep_deep()
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
}
void pmu_stop1_enter(void);
void pmu_stop2_enter(void);
void pmu_standby_enter(pmu_standby_wakeup_sel_t port);
flag_status_t pmu_get_status(pmu_status_t sr);
void pmu_clear_status(pmu_status_t sr);
/**
* @}
*/
/** @addtogroup PMU_Public_Functions_Group2
* @{
*/
/* LVD configure */
void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
void lvd_irq_cbk(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_PMU_H__ */

265
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h
View File

@@ -1,265 +0,0 @@
/**
*********************************************************************************
*
* @file ald_rmu.h
* @brief Header file of RMU module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_RMU_H__
#define __ALD_RMU_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup RMU
* @{
*/
/** @defgroup RMU_Public_Types RMU Public Types
* @{
*/
/**
* @brief RMU BOR fliter
*/
typedef enum
{
RMU_BORFLT_1 = 0x1, /**< 1 cycle */
RMU_BORFLT_2 = 0x2, /**< 2 cycles */
RMU_BORFLT_3 = 0x3, /**< 3 cycles */
RMU_BORFLT_4 = 0x4, /**< 4 cycles */
RMU_BORFLT_5 = 0x5, /**< 5 cycles */
RMU_BORFLT_6 = 0x6, /**< 6 cycles */
RMU_BORFLT_7 = 0x7, /**< 7 cycles */
} rmu_bor_filter_t;
/**
* @brief RMU BOR voltage
*/
typedef enum
{
RMU_VOL_1_7 = 0x0, /**< 1.7V */
RMU_VOL_2_0 = 0x1, /**< 2.0V */
RMU_VOL_2_1 = 0x2, /**< 2.1V */
RMU_VOL_2_2 = 0x3, /**< 2.2V */
RMU_VOL_2_3 = 0x4, /**< 2.3V */
RMU_VOL_2_4 = 0x5, /**< 2.4V */
RMU_VOL_2_5 = 0x6, /**< 2.5V */
RMU_VOL_2_6 = 0x7, /**< 2.6V */
RMU_VOL_2_8 = 0x8, /**< 2.8V */
RMU_VOL_3_0 = 0x9, /**< 3.0V */
RMU_VOL_3_1 = 0xA, /**< 3.1V */
RMU_VOL_3_3 = 0xB, /**< 3.3V */
RMU_VOL_3_6 = 0xC, /**< 3.6V */
RMU_VOL_3_7 = 0xD, /**< 3.7V */
RMU_VOL_4_0 = 0xE, /**< 4.0V */
RMU_VOL_4_3 = 0xF, /**< 4.3V */
} rmu_bor_vol_t;
/**
* @brief RMU reset status
*/
typedef enum
{
RMU_RST_POR = (1U << 0), /**< POR */
RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */
RMU_RST_BOR = (1U << 2), /**< BOR */
RMU_RST_NMRST = (1U << 3), /**< NMRST */
RMU_RST_IWDT = (1U << 4), /**< IWDT */
RMU_RST_WWDT = (1U << 5), /**< WWDT */
RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */
RMU_RST_CHIP = (1U << 7), /**< CHIP */
RMU_RST_MCU = (1U << 8), /**< MCU */
RMU_RST_CPU = (1U << 9), /**< CPU */
RMU_RST_CFG = (1U << 10), /**< CFG */
RMU_RST_CFGERR = (1U << 16), /**< CFG Error */
} rmu_state_t;
/**
* @brief RMU periperal select bit
*/
typedef enum
{
RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */
RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */
RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */
RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */
RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */
RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */
RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */
RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */
RMU_PERH_TIM0 = (1U << 0) | (1U << 28), /**< APB1: TIM0 */
RMU_PERH_TIM1 = (1U << 1) | (1U << 28), /**< APB1: TIM1 */
RMU_PERH_TIM2 = (1U << 2) | (1U << 28), /**< APB1: TIM2 */
RMU_PERH_TIM3 = (1U << 3) | (1U << 28), /**< APB1: TIM3 */
RMU_PERH_TIM4 = (1U << 4) | (1U << 28), /**< APB1: TIM4 */
RMU_PERH_TIM5 = (1U << 5) | (1U << 28), /**< APB1: TIM5 */
RMU_PERH_TIM6 = (1U << 6) | (1U << 28), /**< APB1: TIM6 */
RMU_PERH_TIM7 = (1U << 7) | (1U << 28), /**< APB1: TIM7 */
RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */
RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */
RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */
RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */
RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */
RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */
RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */
RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */
RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */
RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */
RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */
RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */
RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */
RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */
RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */
RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */
RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */
RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */
RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */
RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */
RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */
RMU_PERH_TEMP = (1U << 16) | (1U << 29), /**< APB2: TEMP */
RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */
RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */
} rmu_peripheral_t;
/**
* @}
*/
/**
* @defgroup RMU_Private_Macros RMU Private Macros
* @{
*/
#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \
((x) == RMU_BORFLT_2) || \
((x) == RMU_BORFLT_3) || \
((x) == RMU_BORFLT_4) || \
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_1) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_3) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_5) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_1) || \
((x) == RMU_VOL_3_3) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_7) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_3))
#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR))
#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG))
#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \
((x) == RMU_PERH_CRC) || \
((x) == RMU_PERH_CALC) || \
((x) == RMU_PERH_CRYPT) || \
((x) == RMU_PERH_TRNG) || \
((x) == RMU_PERH_PIS) || \
((x) == RMU_PERH_CHIP) || \
((x) == RMU_PERH_CPU) || \
((x) == RMU_PERH_TIM0) || \
((x) == RMU_PERH_TIM1) || \
((x) == RMU_PERH_TIM2) || \
((x) == RMU_PERH_TIM3) || \
((x) == RMU_PERH_TIM4) || \
((x) == RMU_PERH_TIM5) || \
((x) == RMU_PERH_TIM6) || \
((x) == RMU_PERH_TIM7) || \
((x) == RMU_PERH_UART0) || \
((x) == RMU_PERH_UART1) || \
((x) == RMU_PERH_UART2) || \
((x) == RMU_PERH_UART3) || \
((x) == RMU_PERH_USART0) || \
((x) == RMU_PERH_USART1) || \
((x) == RMU_PERH_SPI0) || \
((x) == RMU_PERH_SPI1) || \
((x) == RMU_PERH_SPI2) || \
((x) == RMU_PERH_I2C0) || \
((x) == RMU_PERH_I2C1) || \
((x) == RMU_PERH_CAN0) || \
((x) == RMU_PERH_LPTIM0) || \
((x) == RMU_PERH_LPUART0) || \
((x) == RMU_PERH_ADC0) || \
((x) == RMU_PERH_ADC1) || \
((x) == RMU_PERH_ACMP0) || \
((x) == RMU_PERH_ACMP1) || \
((x) == RMU_PERH_OPAMP) || \
((x) == RMU_PERH_DAC0) || \
((x) == RMU_PERH_WWDT) || \
((x) == RMU_PERH_LCD) || \
((x) == RMU_PERH_IWDT) || \
((x) == RMU_PERH_RTC) || \
((x) == RMU_PERH_TEMP) || \
((x) == RMU_PERH_BKPC) || \
((x) == RMU_PERH_BKPRAM))
/**
* @}
*/
/** @addtogroup RMU_Public_Functions
* @{
*/
void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
flag_status_t rmu_get_reset_status(rmu_state_t state);
void rmu_clear_reset_status(rmu_state_t state);
void rmu_reset_periperal(rmu_peripheral_t perh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_RMU_H__ */

699
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h
View File

File diff suppressed because it is too large Load Diff

279
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h
View File

@@ -1,279 +0,0 @@
/**
*********************************************************************************
*
* @file ald_usart.h
* @brief Header file of SMARTCARD driver module.
*
* @version V1.0
* @date 25 Apr 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SMARTCARD_H__
#define __ALD_SMARTCARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
#include "ald_usart.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup SMARTCARD
* @{
*/
/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants
* @{
*/
/**
* @brief SMARTCARD error codes
*/
typedef enum
{
SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
} smartcard_error_t;
/**
* @brief SMARTCARD Prescaler
*/
typedef enum
{
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */
} smartcard_prescaler_t;
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types
* @{
*/
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
{
uint32_t baud; /**< This member configures the SmartCard communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
usart_parity_t parity; /**< Specifies the parity mode.
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */
usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/
usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref usart_last_bit_t */
smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
to provide the smartcard clock. The value given in the register (5 significant bits)
is multiplied by 2 to give the division factor of the source clock frequency. */
uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */
} smartcard_init_t;
/**
* @brief ALD state structures definition
*/
typedef enum
{
SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04 /**< Error */
} smartcard_state_t;
/**
* @brief SMARTCARD handle structure definition
*/
typedef struct smartcard_handle_s
{
USART_TypeDef *perh; /**< USART registers base address */
smartcard_init_t init; /**< SmartCard communication parameters */
uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */
uint16_t tx_size; /**< SmartCard Tx Transfer size */
uint16_t tx_count; /**< SmartCard Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */
uint16_t rx_size; /**< SmartCard Rx Transfer size */
uint16_t rx_count; /**< SmartCard Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
smartcard_state_t state; /**< SmartCard communication state */
uint32_t err_code; /**< SmartCard Error code */
void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */
} smartcard_handle_t;
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros
* @{
*/
/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset
* @{
*/
#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET)
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data
* @{
*/
#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA)
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable
* @{
*/
#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
* @}
*/
/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable
* @{
*/
#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions
* @{
*/
/** @addtogroup SMARTCARD_Public_Functions_Group1
* @{
*/
/* Initialization functions */
ald_status_t smartcard_init(smartcard_handle_t *hperh);
ald_status_t smartcard_reset(smartcard_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
#endif
void smartcard_irq_handle(smartcard_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SMARTCARD_Public_Functions_Group3
* @{
*/
/* Peripheral State and Errors functions functions */
smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh);
uint32_t smartcard_get_error(smartcard_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_SMARTCARD_H__ */

377
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h
View File

@@ -1,377 +0,0 @@
/**
*********************************************************************************
*
* @file ald_spi.c
* @brief Header file of SPI module driver.
*
* @version V1.0
* @date 13 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_SPI_H__
#define __ALD_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Public_Types SPI Public Types
* @{
*/
/**
* @brief clock phase
*/
typedef enum
{
SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */
} spi_cpha_t;
/**
* @brief clock polarity
*/
typedef enum
{
SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */
} spi_cpol_t;
/**
* @brief master selection
*/
typedef enum
{
SPI_MODE_SLAVER = 0, /**< Slave mode */
SPI_MODE_MASTER = 1, /**< Master mode */
} spi_mode_t;
/**
* @brief baud rate control
*/
typedef enum
{
SPI_BAUD_2 = 0, /**< fpclk/2 */
SPI_BAUD_4 = 1, /**< fpclk/4 */
SPI_BAUD_8 = 2, /**< fpclk/8 */
SPI_BAUD_16 = 3, /**< fpclk/16 */
SPI_BAUD_32 = 4, /**< fpclk/32 */
SPI_BAUD_64 = 5, /**< fpclk/64 */
SPI_BAUD_128 = 6, /**< fpclk/128 */
SPI_BAUD_256 = 7, /**< fpclk/256 */
} spi_baud_t;
/**
* @brief frame format
*/
typedef enum
{
SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */
} spi_firstbit_t;
/**
* @brief data frame format
*/
typedef enum
{
SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */
} spi_datasize_t;
/**
* @brief interrupt control
*/
typedef enum
{
SPI_IT_ERR = (1U << 5), /**< error interrupt */
SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */
SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */
} spi_it_t;
/**
* @brief interrupt flag
*/
typedef enum
{
SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */
SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */
SPI_IF_CRCERR = (1U << 4), /**< crc error flag */
SPI_IF_MODF = (1U << 5), /**< mode fault */
SPI_IF_OVE = (1U << 6), /**< overrun flag */
SPI_IF_BUSY = (1U << 7), /**< busy flag */
} spi_flag_t;
/**
* @brief SPI error status
*/
typedef enum
{
SPI_ERROR_NONE = 0, /**< none */
SPI_ERROR_MODF = 1, /**< mode fault */
SPI_ERROR_CRC = 2, /**< crc error */
SPI_ERROR_OVE = 4, /**< overrun error */
SPI_ERROR_DMA = 8, /**< dma error */
SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */
} spi_error_t;
/**
* @brief SPI state structures definition
*/
typedef enum
{
SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */
SPI_STATE_ERROR = 0x04, /**< Error */
} spi_state_t;
/**
* @brief SPI direction definition
*/
typedef enum
{
SPI_DIRECTION_2LINES = 0, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */
} spi_direction_t;
/**
* @brief SPI dma request definition
*/
typedef enum
{
SPI_DMA_REQ_TX = 0, /**< TX dma request */
SPI_DMA_REQ_RX = 1, /**< RX dma request */
} spi_dma_req_t;
/**
* @brief SPI TXE/RXNE status definition
*/
typedef enum
{
SPI_SR_TXBE = 0, /**< SR.TXE set */
SPI_SR_RXBNE = 1, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */
} spi_sr_status_t;
/**
* @brief SPI init structure definition
*/
typedef struct
{
spi_mode_t mode; /**< SPI mode */
spi_direction_t dir; /**< SPI direction */
spi_datasize_t data_size; /**< SPI data size */
spi_baud_t baud; /**< SPI baudrate prescaler */
spi_cpha_t phase; /**< SPI clock phase */
spi_cpol_t polarity; /**< SPI clock polarity */
spi_firstbit_t first_bit; /**< SPI first bit */
type_func_t ss_en; /**< SPI ssm enable or disable */
type_func_t crc_calc; /**< SPI crc calculation */
uint16_t crc_poly; /**< SPI crc polynomial */
} spi_init_t;
/**
* @brief SPI handle structure definition
*/
typedef struct spi_handle_s
{
SPI_TypeDef *perh; /**< SPI registers base address */
spi_init_t init; /**< SPI communication parameters */
uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
uint16_t tx_size; /**< SPI Tx transfer size */
uint16_t tx_count; /**< SPI Tx transfer counter */
uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */
uint16_t rx_size; /**< SPI Rx Transfer size */
uint16_t rx_count; /**< SPI Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */
dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
spi_state_t state; /**< SPI communication state */
uint32_t err_code; /**< SPI error code */
void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */
void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */
void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */
} spi_handle_t;
/**
* @}
*/
/** @defgroup SPI_Public_Macros SPI Public Macros
* @{
*/
#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET)
#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define SPI_CRC_RESET(x) \
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)
#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
/**
* @}
*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
#define IS_SPI(x) (((x) == SPI0) || \
((x) == SPI1) || \
((x) == SPI2))
#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \
((x) == SPI_CPHA_SECOND))
#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \
((x) == SPI_CPOL_HIGH))
#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \
((x) == SPI_MODE_MASTER))
#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \
((x) == SPI_BAUD_4) || \
((x) == SPI_BAUD_8) || \
((x) == SPI_BAUD_16) || \
((x) == SPI_BAUD_32) || \
((x) == SPI_BAUD_64) || \
((x) == SPI_BAUD_128) || \
((x) == SPI_BAUD_256))
#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \
((x) == SPI_DATA_SIZE_16))
#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \
((x) == SPI_BID_TX))
#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \
((x) == SPI_BIDMODE_SOLE))
#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \
((x) == SPI_DIRECTION_2LINES_RXONLY) || \
((x) == SPI_DIRECTION_1LINE) || \
((x) == SPI_DIRECTION_1LINE_RX))
#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \
((x) == SPI_DMA_REQ_RX))
#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \
((x) == SPI_SR_RXBNE) || \
((x) == SPI_SR_TXBE_RXBNE))
#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \
((x) == SPI_IT_RXBNE) || \
((x) == SPI_IT_TXBE))
#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \
((x) == SPI_IF_TXBE) || \
((x) == SPI_IF_CRCERR) || \
((x) == SPI_IF_MODF) || \
((x) == SPI_IF_OVE) || \
((x) == SPI_IF_BUSY))
/**
* @}
*/
/** @addtogroup SPI_Public_Functions
* @{
*/
/** @addtogroup SPI_Public_Functions_Group1
* @{
*/
ald_status_t spi_init(spi_handle_t *hperh);
void spi_reset(spi_handle_t *hperh);
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group2
* @{
*/
int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data);
uint8_t spi_recv_byte_fast(spi_handle_t *hperh);
ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
ald_status_t spi_dma_pause(spi_handle_t *hperh);
ald_status_t spi_dma_resume(spi_handle_t *hperh);
ald_status_t spi_dma_stop(spi_handle_t *hperh);
#endif
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group3
* @{
*/
void spi_irq_handle(spi_handle_t *hperh);
void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state);
void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed);
void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state);
it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it);
flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag);
void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag);
/**
* @}
*/
/** @addtogroup SPI_Public_Functions_Group4
* @{
*/
spi_state_t spi_get_state(spi_handle_t *hperh);
uint32_t spi_get_error(spi_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

203
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h
View File

@@ -1,203 +0,0 @@
/**
*********************************************************************************
*
* @file ald_temp.h
* @brief Header file of TEMP module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TEMP_H__
#define __ALD_TEMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TEMP
* @{
*/
/** @defgroup TEMP_Public_Macros TEMP Public Macros
* @{
*/
#define TEMP_LOCK() (WRITE_REG(TEMP->WPR, 0x0))
#define TEMP_UNLOCK() (WRITE_REG(TEMP->WPR, 0xA55A9669))
#define TEMP_ENABLE() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_DISABLE() \
do { \
TEMP_UNLOCK(); \
CLEAR_BIT(TEMP->CR, TEMP_CR_EN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_REQ_ENABLE() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_REQ_DISABLE() \
do { \
TEMP_UNLOCK(); \
CLEAR_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_CTN_ENABLE() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_CTN_DISABLE() \
do { \
TEMP_UNLOCK(); \
CLEAR_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \
TEMP_LOCK(); \
} while (0)
#define TEMP_RESET() \
do { \
TEMP_UNLOCK(); \
SET_BIT(TEMP->CR, TEMP_CR_RST_MSK); \
TEMP_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup TEMP_Public_Types TEMP Public Types
* @{
*/
/**
* @brief Temperature update time
*/
typedef enum
{
TEMP_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */
TEMP_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */
TEMP_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */
TEMP_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */
TEMP_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */
} temp_update_cycle_t;
/**
* @brief Temperature output mode
*/
typedef enum
{
TEMP_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */
TEMP_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */
TEMP_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */
TEMP_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */
TEMP_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */
} temp_output_mode_t;
/**
* @brief Source select
*/
typedef enum
{
TEMP_SOURCE_LOSC = 0x0, /**< LOSC */
TEMP_SOURCE_LRC = 0x1, /**< LRC */
TEMP_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */
TEMP_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */
} temp_source_sel_t;
/**
* @brief TEMP init structure definition
*/
typedef struct
{
temp_update_cycle_t cycle; /**< Temperature update time */
temp_output_mode_t mode; /**< Temperature output mode */
uint8_t ctn; /**< Continue mode */
uint8_t psc; /**< Perscaler */
} temp_init_t;
/**
* @brief Define callback function type
*/
typedef void (*temp_cbk)(uint16_t value, ald_status_t status);
/**
* @}
*/
/**
* @defgroup TEMP_Private_Macros TEMP Private Macros
* @{
*/
#define IS_TEMP_UPDATE_CYCLE(x) (((x) == TEMP_UPDATE_CYCLE_3) || \
((x) == TEMP_UPDATE_CYCLE_4) || \
((x) == TEMP_UPDATE_CYCLE_5) || \
((x) == TEMP_UPDATE_CYCLE_6) || \
((x) == TEMP_UPDATE_CYCLE_7))
#define IS_TEMP_OUTPUT_MODE(x) (((x) == TEMP_OUTPUT_MODE_200) || \
((x) == TEMP_OUTPUT_MODE_400) || \
((x) == TEMP_OUTPUT_MODE_800) || \
((x) == TEMP_OUTPUT_MODE_1600) || \
((x) == TEMP_OUTPUT_MODE_3200))
#define IS_TEMP_SOURCE_SEL(x) (((x) == TEMP_SOURCE_LOSC) || \
((x) == TEMP_SOURCE_LRC) || \
((x) == TEMP_SOURCE_HRC_DIV_1M ) || \
((x) == TEMP_SOURCE_HOSC_DIV_1M))
/**
* @}
*/
/** @addtogroup TEMP_Public_Functions
* @{
*/
/** @addtogroup TEMP_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void temp_init(temp_init_t *init);
extern void temp_source_selcet(temp_source_sel_t sel);
/**
* @}
*/
/** @addtogroup TEMP_Public_Functions_Group2
* @{
*/
/* Control functions */
extern ald_status_t temp_get_value(uint16_t *temp);
extern void temp_get_value_by_it(temp_cbk cbk);
void temp_irq_handle(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TEMP_H__ */

1130
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h
View File

File diff suppressed because it is too large Load Diff

182
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h
View File

@@ -1,182 +0,0 @@
/**
*********************************************************************************
*
* @file ald_trng.h
* @brief Header file of TRNG module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TRNG_H__
#define __ALD_TRNG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TRNG
* @{
*/
/** @defgroup TRNG_Public_Macros TRNG Public Macros
* @{
*/
#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
/**
* @}
*/
/** @defgroup TRNG_Public_Types TRNG Public Types
* @{
*/
/**
* @brief Data width
*/
typedef enum
{
TRNG_DSEL_1B = 0x0, /**< 1-bit */
TRNG_DSEL_8B = 0x1, /**< 8-bit */
TRNG_DSEL_16B = 0x2, /**< 16-bit */
TRNG_DSEL_32B = 0x3, /**< 32-bit */
} trng_data_width_t;
/**
* @brief seed type
*/
typedef enum
{
TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */
TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */
TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */
TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */
} trng_seed_type_t;
/**
* @brief TRNG init structure definition
*/
typedef struct
{
trng_data_width_t data_width; /**< The width of data */
trng_seed_type_t seed_type; /**< The seed type */
uint32_t seed; /**< The value of seed */
uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
uint8_t adjc; /**< Adjust parameter */
uint8_t posten;
} trng_init_t;
/**
* @brief State type
*/
typedef enum
{
TRNG_STATUS_START = (1U << 0), /**< Start state */
TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */
TRNG_STATUS_SERR = (1U << 2), /**< Error state */
} trng_status_t;
/**
* @brief Interrupt type
*/
typedef enum
{
TRNG_IT_START = (1U << 0), /**< Start */
TRNG_IT_DAVLD = (1U << 1), /**< Data valid */
TRNG_IT_SERR = (1U << 2), /**< Error */
} trng_it_t;
/**
* @brief Interrupt flag type
*/
typedef enum
{
TRNG_IF_START = (1U << 0), /**< Start */
TRNG_IF_DAVLD = (1U << 1), /**< Data valid */
TRNG_IF_SERR = (1U << 2), /**< Error */
} trng_flag_t;
/**
* @}
*/
/**
* @defgroup TRNG_Private_Macros TRNG Private Macros
* @{
*/
#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \
((x) == TRNG_DSEL_8B) || \
((x) == TRNG_DSEL_16B) || \
((x) == TRNG_DSEL_32B))
#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \
((x) == TRNG_SEED_TYPE_1) || \
((x) == TRNG_SEED_TYPE_LAST) || \
((x) == TRNG_SEED_TYPE_SEED))
#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \
((x) == TRNG_STATUS_DAVLD) || \
((x) == TRNG_STATUS_SERR))
#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \
((x) == TRNG_IT_DAVLD) || \
((x) == TRNG_IT_SERR))
#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \
((x) == TRNG_IF_DAVLD) || \
((x) == TRNG_IF_SERR))
#define IS_TRNG_ADJC(x) ((x) < 4)
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions
* @{
*/
/** @addtogroup TRNG_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void trng_init(trng_init_t *init);
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions_Group2
* @{
*/
/* Control functions */
extern uint32_t trng_get_result(void);
extern void trng_interrupt_config(trng_it_t it, type_func_t state);
extern flag_status_t trng_get_status(trng_status_t status);
extern it_status_t trng_get_it_status(trng_it_t it);
extern flag_status_t trng_get_flag_status(trng_flag_t flag);
extern void trng_clear_flag_status(trng_flag_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TRNG_H__ */

478
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h
View File

@@ -1,478 +0,0 @@
/**
*********************************************************************************
*
* @file ald_uart.h
* @brief Header file of UART module library.
*
* @version V1.0
* @date 21 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_UART_H__
#define __ALD_UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup UART
* @{
*/
/**
* @defgroup UART_Public_Macros UART Public Macros
* @{
*/
#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK))
#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK))
#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK))
#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
/**
* @}
*/
/** @defgroup UART_Public_Types UART Public Types
* @{
*/
/**
* @brief UART word length
*/
typedef enum
{
UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */
UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */
UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */
UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */
} uart_word_length_t;
/**
* @brief UART stop bits
*/
typedef enum
{
UART_STOP_BITS_1 = 0x0, /**< 1-bits */
UART_STOP_BITS_2 = 0x1, /**< 2-bits */
UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */
UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */
} uart_stop_bits_t;
/**
* @brief UART parity
*/
typedef enum
{
UART_PARITY_NONE = 0x0, /**< Not parity */
UART_PARITY_ODD = 0x1, /**< Odd parity */
UART_PARITY_EVEN = 0x3, /**< Even parity */
} uart_parity_t;
/**
* @brief UART mode
*/
typedef enum
{
UART_MODE_UART = 0x0, /**< UART */
UART_MODE_LIN = 0x1, /**< LIN */
UART_MODE_IrDA = 0x2, /**< IrDA */
UART_MODE_RS485 = 0x3, /**< RS485 */
UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */
} uart_mode_t;
/**
* @brief UART hardware flow control
*/
typedef enum
{
UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */
UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */
} uart_hw_flow_ctl_t;
/**
* @brief ALD UART state
*/
typedef enum
{
UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
UART_STATE_TIMEOUT = 0x03, /**< Timeout state */
UART_STATE_ERROR = 0x04, /**< Error */
} uart_state_t;
/**
* @brief UART error codes
*/
typedef enum
{
UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
} uart_error_t;
/**
* @brief UART init structure definition
*/
typedef struct
{
uint32_t baud; /**< Specifies the uart communication baud rate */
uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
uart_parity_t parity; /**< Specifies the parity mode */
uart_mode_t mode; /**< Specifies uart mode */
uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
} uart_init_t;
/**
* @brief UART handle structure definition
*/
typedef struct uart_handle_s
{
UART_TypeDef *perh; /**< UART registers base address */
uart_init_t init; /**< UART communication parameters */
uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */
uint16_t tx_size; /**< UART Tx Transfer size */
uint16_t tx_count; /**< UART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */
uint16_t rx_size; /**< UART Rx Transfer size */
uint16_t rx_count; /**< UART Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
uart_state_t state; /**< UART communication state */
uart_error_t err_code; /**< UART Error code */
void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */
} uart_handle_t;
/**
* @brief UART RS485 configure structure definition
*/
typedef struct
{
type_func_t normal; /**< Normal mode */
type_func_t dir; /**< Auto-direction mode */
type_func_t invert; /**< Address detection invert */
uint8_t addr; /**< Address for compare */
} uart_rs485_config_t;
/**
* @brief LIN detection break length
*/
typedef enum
{
LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */
LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */
} uart_lin_break_len_t;
/**
* @brief UART TXFIFO size
*/
typedef enum
{
UART_TXFIFO_EMPTY = 0x0, /**< Empty */
UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */
UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */
UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */
} uart_txfifo_t;
/**
* @brief UART RXFIFO size
*/
typedef enum
{
UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */
UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */
UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */
UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */
} uart_rxfifo_t;
/**
* @brief UART auto-baud mode
*/
typedef enum
{
UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */
UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */
UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */
} uart_auto_baud_mode_t;
/**
* @brief UART status types
*/
typedef enum
{
UART_STATUS_DR = (1U << 0), /**< Data ready */
UART_STATUS_OE = (1U << 1), /**< Overrun error */
UART_STATUS_PE = (1U << 2), /**< Parity error */
UART_STATUS_FE = (1U << 3), /**< Framing error */
UART_STATUS_BI = (1U << 4), /**< Break interrupt */
UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */
UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */
UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */
UART_STATUS_BUSY = (1U << 8), /**< UART busy */
UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */
UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */
UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */
UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */
UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */
UART_STATUS_CTS = (1U << 15), /**< Clear to send */
} uart_status_t;
/**
* @brief UART interrupt types
*/
typedef enum
{
UART_IT_RXRD = (1U << 0), /**< Receive data available */
UART_IT_TXS = (1U << 1), /**< Tx empty status */
UART_IT_RXS = (1U << 2), /**< Rx line status */
UART_IT_MDS = (1U << 3), /**< Modem status */
UART_IT_RTO = (1U << 4), /**< Receiver timeout */
UART_IT_BZ = (1U << 5), /**< Busy status */
UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */
UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */
UART_IT_LINBK = (1U << 8), /**< Lin break detection */
UART_IT_TC = (1U << 9), /**< Transmission complete */
UART_IT_EOB = (1U << 10), /**< End of block */
UART_IT_CM = (1U << 11), /**< Character match */
} uart_it_t;
/**
* @brief UART flags types
*/
typedef enum
{
UART_IF_RXRD = (1U << 0), /**< Receive data available */
UART_IF_TXS = (1U << 1), /**< Tx empty status */
UART_IF_RXS = (1U << 2), /**< Rx line status */
UART_IF_MDS = (1U << 3), /**< Modem status */
UART_IF_RTO = (1U << 4), /**< Receiver timeout */
UART_IF_BZ = (1U << 5), /**< Busy status */
UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */
UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */
UART_IF_LINBK = (1U << 8), /**< Lin break detection */
UART_IF_TC = (1U << 9), /**< Transmission complete */
UART_IF_EOB = (1U << 10), /**< End of block */
UART_IF_CM = (1U << 11), /**< Character match */
} uart_flag_t;
/**
* @}
*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
#define IS_UART_ALL(x) (((x) == UART0) || \
((x) == UART1) || \
((x) == UART2) || \
((x) == UART3))
#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \
((x) == UART_WORD_LENGTH_6B) || \
((x) == UART_WORD_LENGTH_7B) || \
((x) == UART_WORD_LENGTH_8B))
#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \
((x) == UART_STOP_BITS_2) || \
((x) == UART_STOP_BITS_0_5) || \
((x) == UART_STOP_BITS_1_5))
#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \
((x) == UART_PARITY_ODD) || \
((x) == UART_PARITY_EVEN))
#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \
((x) == UART_MODE_LIN) || \
((x) == UART_MODE_IrDA) || \
((x) == UART_MODE_RS485) || \
((x) == UART_MODE_HDSEL))
#define IS_UART_HARDWARE_FLOW_CONTROL(x) \
(((x) == UART_HW_FLOW_CTL_DISABLE) || \
((x) == UART_HW_FLOW_CTL_ENABLE))
#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \
((x) == LIN_BREAK_LEN_11B))
#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \
((x) == UART_TXFIFO_2BYTE) || \
((x) == UART_TXFIFO_4BYTE) || \
((x) == UART_TXFIFO_8BYTE))
#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \
((x) == UART_RXFIFO_4BYTE) || \
((x) == UART_RXFIFO_8BYTE) || \
((x) == UART_RXFIFO_14BYTE))
#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \
((x) == UART_ABRMOD_1) || \
((x) == UART_ABRMOD_0_TO_1))
#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \
((x) == UART_STATUS_OE) || \
((x) == UART_STATUS_PE) || \
((x) == UART_STATUS_FE) || \
((x) == UART_STATUS_BI) || \
((x) == UART_STATUS_TBEM) || \
((x) == UART_STATUS_TEM) || \
((x) == UART_STATUS_RFE) || \
((x) == UART_STATUS_BUSY) || \
((x) == UART_STATUS_TFNF) || \
((x) == UART_STATUS_TFEM) || \
((x) == UART_STATUS_RFNE) || \
((x) == UART_STATUS_RFF) || \
((x) == UART_STATUS_DCTS) || \
((x) == UART_STATUS_CTS))
#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \
((x) == UART_IT_TXS) || \
((x) == UART_IT_RXS) || \
((x) == UART_IT_MDS) || \
((x) == UART_IT_RTO) || \
((x) == UART_IT_BZ) || \
((x) == UART_IT_ABE) || \
((x) == UART_IT_ABTO) || \
((x) == UART_IT_LINBK) || \
((x) == UART_IT_TC) || \
((x) == UART_IT_EOB) || \
((x) == UART_IT_CM))
#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \
((x) == UART_IF_TXS) || \
((x) == UART_IF_RXS) || \
((x) == UART_IF_MDS) || \
((x) == UART_IF_RTO) || \
((x) == UART_IF_BZ) || \
((x) == UART_IF_ABE) || \
((x) == UART_IF_ABTO) || \
((x) == UART_IF_LINBK) || \
((x) == UART_IF_TC) || \
((x) == UART_IF_EOB) || \
((x) == UART_IF_CM))
#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
#define IS_UART_DATA(x) ((x) <= 0x1FF)
#define UART_STATE_TX_MASK (1U << 4)
#define UART_STATE_RX_MASK (1U << 5)
/**
* @}
*/
/** @addtogroup UART_Public_Functions
* @{
*/
/** @addtogroup UART_Public_Functions_Group1
* @{
*/
/* Initialization functions */
void uart_init(uart_handle_t *hperh);
void uart_reset(uart_handle_t *hperh);
void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group2
* @{
*/
/* IO operation functions */
ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t uart_dma_pause(uart_handle_t *hperh);
ald_status_t uart_dma_resume(uart_handle_t *hperh);
ald_status_t uart_dma_stop(uart_handle_t *hperh);
#endif
void uart_irq_handle(uart_handle_t *hperh);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group3
* @{
*/
/* Peripheral Control functions */
void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
void uart_dma_req_config(uart_handle_t *hperh, type_func_t state);
void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
void uart_lin_send_break(uart_handle_t *hperh);
void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status);
flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
/**
* @}
*/
/** @addtogroup UART_Public_Functions_Group4
* @{
*/
/* Peripheral State and Errors functions */
uart_state_t uart_get_state(uart_handle_t *hperh);
uint32_t uart_get_error(uart_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_UART_H__ */

580
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h
View File

File diff suppressed because it is too large Load Diff

14
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html
View File

@@ -1,14 +0,0 @@
<!doctype html>
<html>
<head>
<meta charset='UTF-8'><meta name='viewport' content='width=device-width initial-scale=1'>
<title>ReleaseNote</title></head>
<body><h1>ES32F065x MD Release Note</h1>
<h2>V1.00 2018-12-26</h2>
<ol start='' >
<li>First release</li>
</ol>
<p>&nbsp;</p>
</body>
</html>

213
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c
View File

@@ -1,213 +0,0 @@
/**
*********************************************************************************
*
* @file ald_temp.c
* @brief TEMP module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_temp.h"
#include "ald_bkpc.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup TEMP TEMP
* @brief TEMP module driver
* @{
*/
#ifdef ALD_TEMP
/** @defgroup TEMP_Private_Variables TEMP Private Variables
* @{
*/
temp_cbk __temp_cbk;
/**
* @}
*/
/** @defgroup TEMP_Public_Functions TEMP Public Functions
* @{
*/
/** @addtogroup TEMP_Public_Functions_Group1 Initialization functions
* @brief Initialization functions
*
* @verbatim
==============================================================================
##### Initialization functions #####
==============================================================================
[..] This section provides functions allowing to initialize the TEMP:
(+) This parameters can be configured:
(++) Update Cycle
(++) Output Mode
(++) Perscaler
(+) Select TEMP source clock(default LOSC)
@endverbatim
* @{
*/
/**
* @brief Initializes the TEMP according to the specified
* parameters in the temp_init_t.
* @param init: Pointer to a temp_init_t structure that contains
* the configuration information.
* @retval None
*/
void temp_init(temp_init_t *init)
{
assert_param(IS_TEMP_UPDATE_CYCLE(init->cycle));
assert_param(IS_TEMP_OUTPUT_MODE(init->mode));
TEMP_UNLOCK();
MODIFY_REG(TEMP->CR, TEMP_CR_TSU_MSK, init->cycle << TEMP_CR_TSU_POSS);
MODIFY_REG(TEMP->CR, TEMP_CR_TOM_MSK, init->mode << TEMP_CR_TOM_POSS);
MODIFY_REG(TEMP->CR, TEMP_CR_CTN_MSK, init->ctn << TEMP_CR_CTN_POS);
MODIFY_REG(TEMP->PSR, TEMP_PSR_PRS_MSK, init->psc << TEMP_PSR_PRS_POSS);
TEMP_LOCK();
return;
}
/**
* @brief Configure the TEMP source.
* @param sel: TEMP source type.
* @retval None
*/
void temp_source_selcet(temp_source_sel_t sel)
{
assert_param(IS_TEMP_SOURCE_SEL(sel));
BKPC_UNLOCK();
MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TEMPCS_MSK, sel << BKPC_PCCR_TEMPCS_POSS);
if (sel == TEMP_SOURCE_LOSC)
{
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
}
else if (sel == TEMP_SOURCE_LRC)
{
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
}
else
{
; /* do nothing */
}
BKPC_LOCK();
return;
}
/**
* @}
*/
/** @addtogroup TEMP_Public_Functions_Group2 Peripheral Control functions
* @brief Peripheral Control functions
*
* @verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) temp_get_value() API can get the current temperature.
(+) temp_get_value_by_it() API can get the current temperature by interrupt.
(+) temp_irq_handle() API can handle the interrupt request.
@endverbatim
* @{
*/
/**
* @brief Get the current temperature
* @param temp: The value of current temperature.
* @retval ALD status:
* @arg @ref OK The value is valid
* @arg @ref ERROR The value is invalid
*/
ald_status_t temp_get_value(uint16_t *temp)
{
TEMP_UNLOCK();
SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
SET_BIT(TEMP->CR, TEMP_CR_EN_MSK);
TEMP_LOCK();
while (!(READ_BIT(TEMP->IF, TEMP_IF_TEMP_MSK)));
TEMP_UNLOCK();
SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
TEMP_LOCK();
if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK))
return ERROR;
*temp = READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS);
return OK;
}
/**
* @brief Get the current temperature by interrupt
* @param cbk: The callback function
* @retval None
*/
void temp_get_value_by_it(temp_cbk cbk)
{
__temp_cbk = cbk;
TEMP_UNLOCK();
SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
SET_BIT(TEMP->IE, TEMP_IE_TEMP_MSK);
SET_BIT(TEMP->CR, TEMP_CR_EN_MSK);
TEMP_LOCK();
return;
}
/**
* @brief This function handles TEMP interrupt request.
* @retval None
*/
void temp_irq_handle(void)
{
TEMP_UNLOCK();
SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
TEMP_LOCK();
if (__temp_cbk == NULL)
return;
if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK))
{
__temp_cbk(0, ERROR);
return;
}
__temp_cbk(READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS), OK);
return;
}
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_TEMP */
/**
* @}
*/
/**
* @}
*/

222
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c
View File

@@ -1,222 +0,0 @@
/**
*********************************************************************************
*
* @file ald_trng.c
* @brief TRNG module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#include "ald_trng.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @defgroup TRNG TRNG
* @brief TRNG module driver
* @{
*/
#ifdef ALD_TRNG
/** @defgroup TRNG_Public_Functions TRNG Public Functions
* @{
*/
/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions
* @brief Initialization functions
*
* @verbatim
==============================================================================
##### Initialization functions #####
==============================================================================
[..] This section provides functions allowing to initialize the TRNG:
(+) This parameters can be configured:
(++) Word Width
(++) Seed Type
(++) Seed
(++) Start Time
(++) Adjust parameter
@endverbatim
* @{
*/
/**
* @brief Initializes the TRNG according to the specified
* parameters in the trng_init_t.
* @param init: Pointer to a trng_init_t structure that contains
* the configuration information.
* @retval None
*/
void trng_init(trng_init_t *init)
{
assert_param(IS_TRNG_DATA_WIDTH(init->data_width));
assert_param(IS_TRNG_SEED_TYPE(init->seed_type));
assert_param(IS_TRNG_ADJC(init->adjc));
SET_BIT(TRNG->CR, TRNG_CR_TRNGSEL_MSK);
MODIFY_REG(TRNG->CR, TRNG_CR_DSEL_MSK, (init->data_width) << TRNG_CR_DSEL_POSS);
MODIFY_REG(TRNG->CR, TRNG_CR_SDSEL_MSK, (init->seed_type) << TRNG_CR_SDSEL_POSS);
MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (init->adjc) << TRNG_CR_ADJC_POSS);
if (init->adjc == 0)
{
MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (0) << TRNG_CR_ADJC_POSS);
}
else
{
MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (1) << TRNG_CR_ADJC_POSS);
}
WRITE_REG(TRNG->SEED, init->seed);
MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (init->t_start) << TRNG_CFGR_TSTART_POSS);
MODIFY_REG(TRNG->CR, TRNG_CR_POSTEN_MSK, (init->posten) << TRNG_CR_POSTEN_MSK);
return;
}
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions
* @brief Peripheral Control functions
*
* @verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) trng_get_result() API can Get the result.
(+) trng_interrupt_config() API can be helpful to configure TRNG interrupt source.
(+) trng_get_it_status() API can get the status of interrupt source.
(+) trng_get_status() API can get the status of SR register.
(+) trng_get_flag_status() API can get the status of interrupt flag.
(+) trng_clear_flag_status() API can clear interrupt flag.
@endverbatim
* @{
*/
/**
* @brief Get the result.
* @retval The resultl
*/
uint32_t trng_get_result(void)
{
return (uint32_t)TRNG->DR;
}
/**
* @brief Enable/disable the specified interrupts.
* @param it: Specifies the interrupt sources to be enabled or disabled.
* This parameter can be one of the @ref trng_it_t.
* @param state: New state of the specified interrupts.
* This parameter can be:
* @arg ENABLE
* @arg DISABLE
* @retval None
*/
void trng_interrupt_config(trng_it_t it, type_func_t state)
{
assert_param(IS_TRNG_IT(it));
assert_param(IS_FUNC_STATE(state));
if (state)
SET_BIT(TRNG->IER, it);
else
CLEAR_BIT(TRNG->IER, it);
return;
}
/**
* @brief Get the status of SR register.
* @param status: Specifies the TRNG status type.
* This parameter can be one of the @ref trng_status_t.
* @retval Status:
* - 0: RESET
* - 1: SET
*/
flag_status_t trng_get_status(trng_status_t status)
{
assert_param(IS_TRNG_STATUS(status));
if (READ_BIT(TRNG->SR, status))
return SET;
return RESET;
}
/**
* @brief Get the status of interrupt source.
* @param it: Specifies the interrupt source.
* This parameter can be one of the @ref trng_it_t.
* @retval Status:
* - 0: RESET
* - 1: SET
*/
it_status_t trng_get_it_status(trng_it_t it)
{
assert_param(IS_TRNG_IT(it));
if (READ_BIT(TRNG->IER, it))
return SET;
return RESET;
}
/**
* @brief Get the status of interrupt flag.
* @param flag: Specifies the interrupt flag.
* This parameter can be one of the @ref trng_flag_t.
* @retval Status:
* - 0: RESET
* - 1: SET
*/
flag_status_t trng_get_flag_status(trng_flag_t flag)
{
assert_param(IS_TRNG_FLAG(flag));
if (READ_BIT(TRNG->IFR, flag))
return SET;
return RESET;
}
/**
* @brief Clear the interrupt flag.
* @param flag: Specifies the interrupt flag.
* This parameter can be one of the @ref trng_flag_t.
* @retval None
*/
void trng_clear_flag_status(trng_flag_t flag)
{
assert_param(IS_TRNG_FLAG(flag));
WRITE_REG(TRNG->IFCR, flag);
return;
}
/**
* @}
*/
/**
* @}
*/
#endif /* ALD_TRNG */
/**
* @}
*/
/**
* @}
*/

113
bsp/es32f0654/.config → bsp/essemi/es32f0654/.config
View File

@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
CONFIG_RT_VER_NUM=0x40001
CONFIG_RT_VER_NUM=0x40002
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
@@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
@@ -120,7 +123,6 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
@@ -128,10 +130,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using WiFi
#
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
@@ -145,6 +147,7 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_LIBC_USING_TIME is not set
#
# Network
@@ -155,16 +158,16 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
@@ -178,7 +181,6 @@ CONFIG_RT_USING_PIN=y
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
@@ -192,10 +194,13 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
@@ -213,10 +218,14 @@ CONFIG_RT_USING_PIN=y
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
@@ -225,6 +234,21 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
#
# security packages
@@ -245,6 +269,9 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
@@ -253,6 +280,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
#
# system packages
@@ -266,17 +299,42 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_LCD_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
#
# miscellaneous packages
@@ -287,13 +345,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
@@ -302,11 +362,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
CONFIG_SOC_ES32F0654LT=y
#
@@ -350,7 +414,6 @@ CONFIG_BSP_USING_UART2=y
# HWtimer Drivers
#
# CONFIG_BSP_USING_HWTIMER0 is not set
# CONFIG_BSP_USING_HWTIMER1 is not set
# CONFIG_BSP_USING_HWTIMER2 is not set
# CONFIG_BSP_USING_HWTIMER3 is not set

2
bsp/es32f0654/Kconfig → bsp/essemi/es32f0654/Kconfig
View File

@@ -8,7 +8,7 @@ config BSP_DIR
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
default "../../.."
config PKGS_DIR
string

1
bsp/es32f0654/README.md → bsp/essemi/es32f0654/README.md
View File

@@ -40,6 +40,7 @@ ES-PDS-ES32F0654-V1.1
| UART | 支持 | UART0/1/2/3 |
| SPI | 支持 | SPI0/1 |
| I2C | 支持 | I2C0/1 |
| CAN | 支持 | CAN0 |
| PWM | 支持 | PWM0/1/2/3 |
| TIMER | 支持 | TIMER0/1/2/3 |
| RTC | 支持 | RTC |

0
bsp/es32f0654/SConscript → bsp/essemi/es32f0654/SConscript
View File

2
bsp/es32f0654/SConstruct → bsp/essemi/es32f0654/SConstruct
View File

@@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:

0
bsp/es32f0654/applications/SConscript → bsp/essemi/es32f0654/applications/SConscript
View File

0
bsp/es32f0654/applications/main.c → bsp/essemi/es32f0654/applications/main.c
View File

7
bsp/es32f0654/drivers/Kconfig → bsp/essemi/es32f0654/drivers/Kconfig
View File

@@ -56,6 +56,13 @@ menu "Hardware Drivers Config"
default n
endmenu
menu "CAN Drivers"
config BSP_USING_CAN
bool "Enable CAN BUS PA11/PA12(RX/TX)"
select RT_USING_CAN
default n
endmenu
menu "PWM Drivers"
config BSP_USING_PWM0
bool "Using PWM0 PA08/PA09/PA10/PA11"

4
bsp/es32f0654/drivers/SConscript → bsp/essemi/es32f0654/drivers/SConscript
View File

@@ -23,6 +23,10 @@ if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'):
if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
src += ['drv_i2c.c']
# add can driver code
if GetDepend('BSP_USING_CAN'):
src += ['drv_can.c']
# add spi flash driver code
if GetDepend('BSP_USING_SPI_FLASH'):
src += ['drv_spiflash.c']

11
bsp/es32f0654/drivers/board.c → bsp/essemi/es32f0654/drivers/board.c
View File

@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-23 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -43,10 +44,10 @@ void NVIC_Configuration(void)
void SystemClock_Config(void)
{
/* hosc 12MHz, from hosc/3 pll to 48MHz */
cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
/* MCLK 48MHz*/
cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
}
/*******************************************************************************
@@ -59,14 +60,14 @@ void SystemClock_Config(void)
void SysTick_Configuration(void)
{
/* ticks = sysclk / RT_TICK_PER_SECOND */
SysTick_Config(cmu_get_sys_clock() / RT_TICK_PER_SECOND);
SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND);
}
/**
* This is the timer interrupt service routine.
*
*/
void systick_irq_cbk(void)
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@@ -113,7 +114,7 @@ void rt_hw_us_delay(rt_uint32_t us)
unsigned int start, now, delta, reload, us_tick;
start = SysTick->VAL;
reload = SysTick->LOAD;
us_tick = cmu_get_sys_clock() / 1000000UL;
us_tick = ald_cmu_get_sys_clock() / 1000000UL;
do
{
now = SysTick->VAL;

0
bsp/es32f0654/drivers/board.h → bsp/essemi/es32f0654/drivers/board.h
View File

56
bsp/es32f0654/drivers/drv_adc.c → bsp/essemi/es32f0654/drivers/drv_adc.c
View File

@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-04-03 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -58,67 +59,67 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
{
case 0:
es32f0_channel = ADC_CHANNEL_0;
gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
break;
case 1:
es32f0_channel = ADC_CHANNEL_1;
gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
break;
case 2:
es32f0_channel = ADC_CHANNEL_2;
gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
break;
case 3:
es32f0_channel = ADC_CHANNEL_3;
gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
break;
case 4:
es32f0_channel = ADC_CHANNEL_4;
gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
break;
case 5:
es32f0_channel = ADC_CHANNEL_5;
gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
break;
case 6:
es32f0_channel = ADC_CHANNEL_6;
gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
break;
case 7:
es32f0_channel = ADC_CHANNEL_7;
gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
break;
case 8:
es32f0_channel = ADC_CHANNEL_8;
gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
break;
case 9:
es32f0_channel = ADC_CHANNEL_9;
gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
break;
case 10:
es32f0_channel = ADC_CHANNEL_10;
gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
break;
case 11:
es32f0_channel = ADC_CHANNEL_11;
gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
break;
case 12:
es32f0_channel = ADC_CHANNEL_12;
gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
break;
case 13:
es32f0_channel = ADC_CHANNEL_13;
gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
break;
case 14:
es32f0_channel = ADC_CHANNEL_14;
gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
break;
case 15:
es32f0_channel = ADC_CHANNEL_15;
gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
break;
case 16:
es32f0_channel = ADC_CHANNEL_16;
@@ -139,21 +140,21 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
adc_channel_conf_t nm_config;
adc_nch_conf_t nm_config;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
/* config adc channel */
nm_config.channel = es32f0_adc_get_channel(channel);
nm_config.rank = ADC_NC_RANK_1;
nm_config.sampling_time = ADC_SAMPLETIME_4;
adc_normal_channel_config(_hadc, &nm_config);
nm_config.rank = ADC_NCH_RANK_1;
nm_config.samp_time = ADC_SAMPLETIME_4;
ald_adc_normal_channel_config(_hadc, &nm_config);
adc_normal_start(_hadc);
ald_adc_normal_start(_hadc);
if (adc_normal_poll_for_conversion(_hadc, 5000) == OK)
*value = adc_normal_get_value(_hadc);
if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK)
*value = ald_adc_normal_get_value(_hadc);
return RT_EOK;
}
@@ -172,17 +173,16 @@ int rt_hw_adc_init(void)
/* adc function initialization */
_h_adc0.perh = ADC0;
_h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan_mode = ADC_SCAN_DISABLE;
_h_adc0.init.scan_mode = DISABLE;
_h_adc0.init.cont_mode = DISABLE;
_h_adc0.init.conv_nbr = ADC_NM_NBR_1;
_h_adc0.init.disc_mode = DISABLE;
_h_adc0.init.disc_mode = ADC_ALL_DISABLE;
_h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
_h_adc0.init.conv_res = ADC_CONV_RES_10;
_h_adc0.init.clk_div = ADC_CKDIV_128;
_h_adc0.init.nche_mode = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
_h_adc0.init.pos_ref = ADC_POS_REF_VDD;
adc_init(&_h_adc0);
ald_adc_init(&_h_adc0);
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);

0
bsp/es32f0654/drivers/drv_adc.h → bsp/essemi/es32f0654/drivers/drv_adc.h
View File

605
bsp/essemi/es32f0654/drivers/drv_can.c Normal file
View File

File diff suppressed because it is too large Load Diff

37
bsp/essemi/es32f0654/drivers/drv_can.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-11-09 wangyq the first version
*/
#ifndef DRV_CAN_H__
#define DRV_CAN_H__
#include <board.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <ald_can.h>
#include <ald_gpio.h>
struct es32f0_baud_rate_tab
{
rt_uint32_t baud_rate;
rt_uint32_t config_data;
};
/* es32f0 can device */
struct es32f0_can
{
can_handle_t CanHandle;
can_filter_t FilterConfig;
struct rt_can_device device; /* inherit from can device */
};
int rt_hw_can_init(void);
#endif /*DRV_CAN_H__ */

23
bsp/es32f0654/drivers/drv_gpio.c → bsp/essemi/es32f0654/drivers/drv_gpio.c
View File

@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-23 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -167,7 +168,7 @@ void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
return;
}
gpio_write_pin(index->gpio, index->pin, value);
ald_gpio_write_pin(index->gpio, index->pin, value);
}
int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
@@ -180,7 +181,7 @@ int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
{
return value;
}
value = gpio_read_pin(index->gpio, index->pin);
value = ald_gpio_read_pin(index->gpio, index->pin);
return value;
}
@@ -233,7 +234,7 @@ void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
gpio_initstruct.pupd = GPIO_FLOATING;
gpio_initstruct.odos = GPIO_OPEN_DRAIN;
}
gpio_init(index->gpio, index->pin, &gpio_initstruct);
ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
}
rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
@@ -360,7 +361,7 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
return RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
/* Configure GPIO_InitStructure */
gpio_initstruct.mode = GPIO_MODE_INPUT;
gpio_initstruct.func = GPIO_FUNC_1;
@@ -368,18 +369,18 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
{
case PIN_IRQ_MODE_RISING:
gpio_initstruct.pupd = GPIO_PUSH_DOWN;
gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
break;
case PIN_IRQ_MODE_FALLING:
gpio_initstruct.pupd = GPIO_PUSH_UP;
gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
break;
case PIN_IRQ_MODE_RISING_FALLING:
gpio_initstruct.pupd = GPIO_FLOATING;
gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
break;
}
gpio_init(index->gpio, index->pin, &gpio_initstruct);
ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
NVIC_EnableIRQ(irqmap->irqno);
rt_hw_interrupt_enable(level);
}
@@ -412,7 +413,7 @@ const static struct rt_pin_ops _es32f0_pin_ops =
int rt_hw_pin_init(void)
{
int result;
cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
return result;
}
@@ -439,9 +440,9 @@ rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
if (gpio_exti_get_flag_status(GPIO_Pin) != RESET)
if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
{
gpio_exti_clear_flag_status(GPIO_Pin);
ald_gpio_exti_clear_flag_status(GPIO_Pin);
pin_irq_hdr(GPIO_Pin);
}
}

Some files were not shown because too many files have changed in this diff Show More