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[bsp]1.update es32f0654 libraries.

Browse Source 
2.adapt to the new power management interface.
         3.rename es32f0654 folder to essemi_es32f0654 folder.
	 4.add can driver.
This commit is contained in:
wangyq2018 committed 2020-01-13 10:22:18 +08:00
1 parent 383509e220
commit 696b130afe
151 files changed
+21659 -27693
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bsp/es32f0654/drivers/drv_pm.c
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/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-01 wangyq the first version
* 2019-05-06 Zero-Free adapt to the new power management interface
*/
#include <rthw.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_pm.h"
#include <ald_pmu.h>
#ifdef RT_USING_PM
static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode)
{
switch (mode)
{
case PM_SLEEP_MODE_NONE:
break;
case PM_SLEEP_MODE_IDLE:
__WFI();
break;
case PM_SLEEP_MODE_LIGHT:
break;
case PM_SLEEP_MODE_DEEP:
pmu_stop2_enter();
break;
case PM_SLEEP_MODE_STANDBY:
pmu_standby_enter(PMU_STANDBY_PORT_NONE);
break;
case PM_SLEEP_MODE_SHUTDOWN:
break;
default:
RT_ASSERT(0);
break;
}
}
static int drv_hw_pm_init(void)
{
static const struct rt_pm_ops _ops =
{
_drv_pm_enter,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL
};
rt_uint8_t timer_mask = 0;
/* initialize timer mask(no need tickless) */
timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
/* initialize system pm module */
rt_system_pm_init(&_ops, timer_mask, RT_NULL);
return 0;
}
INIT_BOARD_EXPORT(drv_hw_pm_init);
#endif
bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf
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bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf
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bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h
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bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h
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bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h
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bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h
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bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h
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bsp/es32f0654/libraries/CMSIS/index.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Redirect to the CMSIS main page after 0 seconds</title>
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
<meta name="keywords" content="automatic redirection">
</head>
<body>
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
</body>
</html>
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
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/**
*********************************************************************************
*
* @file ald_bkpc.h
* @brief Header file of BKPC module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_BKPC_H__
#define __ALD_BKPC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup BKPC
* @{
*/
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55))
#define BKPC_LRC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup BKPC_Public_Types BKPC Public Types
* @{
*/
/**
* @brief BKPC ldo output select
*/
typedef enum
{
BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief BKPC BOR voltage select
*/
typedef enum
{
BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */
BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */
BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */
BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */
BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */
BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */
BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */
BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */
BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */
BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */
BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */
BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */
BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */
BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */
BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */
BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */
} bkpc_bor_vol_t;
/**
* @}
*/
/**
* @defgroup BKPC_Private_Macros BKPC Private Macros
* @{
*/
#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \
((x) == BKPC_BOR_VOL_2_0) || \
((x) == BKPC_BOR_VOL_2_1) || \
((x) == BKPC_BOR_VOL_2_2) || \
((x) == BKPC_BOR_VOL_2_3) || \
((x) == BKPC_BOR_VOL_2_4) || \
((x) == BKPC_BOR_VOL_2_5) || \
((x) == BKPC_BOR_VOL_2_6) || \
((x) == BKPC_BOR_VOL_2_8) || \
((x) == BKPC_BOR_VOL_3_0) || \
((x) == BKPC_BOR_VOL_3_1) || \
((x) == BKPC_BOR_VOL_3_3) || \
((x) == BKPC_BOR_VOL_3_6) || \
((x) == BKPC_BOR_VOL_3_7) || \
((x) == BKPC_BOR_VOL_4_0) || \
((x) == BKPC_BOR_VOL_4_3))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions
* @{
*/
/** @addtogroup BKPC_Public_Functions_Group1
* @{
*/
/* control functions */
extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions_Group2
* @{
*/
/* IO operation functions */
extern void bkpc_write_ram(uint8_t idx, uint32_t value);
extern uint32_t bkpc_read_ram(uint8_t idx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_BKPC_H__ */
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h
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/**
*********************************************************************************
*
* @file ald_crc.h
* @brief Header file of CRC module driver.
*
* @version V1.0
* @date 6 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_CRC_H__
#define __ALD_CRC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
#include "ald_dma.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Public_Types CRC Public Types
* @{
*/
/**
* @brief CRC mode
*/
typedef enum
{
CRC_MODE_CCITT = 0, /**< Ccitt */
CRC_MODE_8 = 1, /**< Crc8 */
CRC_MODE_16 = 2, /**< Crc16 */
CRC_MODE_32 = 3, /**< Crc32 */
} crc_mode_t;
/**
* @brief CRC input length
*/
typedef enum
{
CRC_LEN_AUTO = 0, /**< Auto */
CRC_DATASIZE_8 = 1, /**< Byte */
CRC_DATASIZE_16 = 2, /**< Half word */
CRC_DATASIZE_32 = 3, /**< Word */
} crc_datasize_t;
/**
* @brief CRC whether write error or no
*/
typedef enum
{
CRC_WERR_NO = 0, /**< No error */
CRC_WERR_ERR = 1, /**< Error */
} crc_werr_t;
/**
* @brief CRC state structures definition
*/
typedef enum
{
CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4, /**< Error */
} crc_state_t;
/**
* @brief CRC init structure definition
*/
typedef struct
{
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
type_func_t chs_rev; /**< CRC check sum reverse or no */
type_func_t chs_inv; /**< CRC check sum inverse or no */
uint32_t seed; /**< CRC seed */
} crc_init_t;
/**
* @brief CRC Handle Structure definition
*/
typedef struct crc_handle_s
{
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */
uint32_t *cal_res; /**< The pointer of result */
#ifdef ALD_DMA
dma_handle_t hdma; /**< CRC DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
crc_state_t state; /**< CRC operation state */
void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
} crc_handle_t;
/**
* @}
*/
/** @defgroup CRC_Public_Macros CRC Public Macros
* @{
*/
#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
/**
* @}
*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_CRC(x) ((x) == CRC)
#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
/**
* @}
*/
/** @addtogroup CRC_Public_Functions
* @{
*/
/** @addtogroup CRC_Public_Functions_Group1
* @{
*/
ald_status_t crc_init(crc_handle_t *hperh);
/**
* @}
*/
/** @addtogroup CRC_Public_Functions_Group2
* @{
*/
uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
/**
* @}
*/
#ifdef ALD_DMA
/** @addtogroup CRC_Public_Functions_Group3
* @{
*/
ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
ald_status_t crc_dma_pause(crc_handle_t *hperh);
ald_status_t crc_dma_resume(crc_handle_t *hperh);
ald_status_t crc_dma_stop(crc_handle_t *hperh);
/**
* @}
*/
#endif
/** @addtogroup CRC_Public_Functions_Group4
* @{
*/
crc_state_t crc_get_state(crc_handle_t *hperh);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_CRC_H__ */
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h
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/**
*********************************************************************************
*
* @file ald_flash.h
* @brief Header file of FLASH driver
*
* @version V1.0
* @date 20 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_FLASH_H__
#define __ALD_FLASH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup FLASH
* @{
*/
/**
* @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#define FLASH_REG_UNLOCK() \
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
} \
} while (0)
#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_BASE_ADDR 0x00000000
#define FLASH_PAGE_SIZE 1024UL
#define FLASH_WORD_SIZE 8UL
#define FLASH_TOTAL_SIZE 256UL
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
#define INFO_PAGE_SIZE 1024UL
#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#ifdef USE_FLASH_FIFO
#define FLASH_FIFO 1
#else
#define FLASH_FIFO 0
#endif
/**
* @}
*/
/** @defgroup FLASH_Private_Types FLASH Private Types
* @{
*/
typedef enum
{
FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */
} flash_cmd_type;
typedef enum
{
OP_FLASH = 0, /**< Operate Pragram area */
OP_INFO = 1, /**< Operate info area */
} op_cmd_type;
/**
* @}
*/
/** @addtogroup Flash_Public_Functions
* @{
*/
ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
ald_status_t flash_erase(uint32_t addr, uint16_t len);
ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_FLASH_H__ */
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h
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/**
*********************************************************************************
*
* @file ald_trng.h
* @brief Header file of TRNG module driver.
*
* @version V1.0
* @date 04 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_TRNG_H__
#define __ALD_TRNG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup TRNG
* @{
*/
/** @defgroup TRNG_Public_Macros TRNG Public Macros
* @{
*/
#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
/**
* @}
*/
/** @defgroup TRNG_Public_Types TRNG Public Types
* @{
*/
/**
* @brief Data width
*/
typedef enum
{
TRNG_DSEL_1B = 0x0, /**< 1-bit */
TRNG_DSEL_8B = 0x1, /**< 8-bit */
TRNG_DSEL_16B = 0x2, /**< 16-bit */
TRNG_DSEL_32B = 0x3, /**< 32-bit */
} trng_data_width_t;
/**
* @brief seed type
*/
typedef enum
{
TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */
TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */
TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */
TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */
} trng_seed_type_t;
/**
* @brief TRNG init structure definition
*/
typedef struct
{
trng_data_width_t data_width; /**< The width of data */
trng_seed_type_t seed_type; /**< The seed type */
uint32_t seed; /**< The value of seed */
uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
uint8_t adjc; /**< Adjust parameter */
uint8_t posten;
} trng_init_t;
/**
* @brief State type
*/
typedef enum
{
TRNG_STATUS_START = (1U << 0), /**< Start state */
TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */
TRNG_STATUS_SERR = (1U << 2), /**< Error state */
} trng_status_t;
/**
* @brief Interrupt type
*/
typedef enum
{
TRNG_IT_START = (1U << 0), /**< Start */
TRNG_IT_DAVLD = (1U << 1), /**< Data valid */
TRNG_IT_SERR = (1U << 2), /**< Error */
} trng_it_t;
/**
* @brief Interrupt flag type
*/
typedef enum
{
TRNG_IF_START = (1U << 0), /**< Start */
TRNG_IF_DAVLD = (1U << 1), /**< Data valid */
TRNG_IF_SERR = (1U << 2), /**< Error */
} trng_flag_t;
/**
* @}
*/
/**
* @defgroup TRNG_Private_Macros TRNG Private Macros
* @{
*/
#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \
((x) == TRNG_DSEL_8B) || \
((x) == TRNG_DSEL_16B) || \
((x) == TRNG_DSEL_32B))
#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \
((x) == TRNG_SEED_TYPE_1) || \
((x) == TRNG_SEED_TYPE_LAST) || \
((x) == TRNG_SEED_TYPE_SEED))
#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \
((x) == TRNG_STATUS_DAVLD) || \
((x) == TRNG_STATUS_SERR))
#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \
((x) == TRNG_IT_DAVLD) || \
((x) == TRNG_IT_SERR))
#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \
((x) == TRNG_IF_DAVLD) || \
((x) == TRNG_IF_SERR))
#define IS_TRNG_ADJC(x) ((x) < 4)
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions
* @{
*/
/** @addtogroup TRNG_Public_Functions_Group1
* @{
*/
/* Initialization functions */
extern void trng_init(trng_init_t *init);
/**
* @}
*/
/** @addtogroup TRNG_Public_Functions_Group2
* @{
*/
/* Control functions */
extern uint32_t trng_get_result(void);
extern void trng_interrupt_config(trng_it_t it, type_func_t state);
extern flag_status_t trng_get_status(trng_status_t status);
extern it_status_t trng_get_it_status(trng_it_t it);
extern flag_status_t trng_get_flag_status(trng_flag_t flag);
extern void trng_clear_flag_status(trng_flag_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_TRNG_H__ */
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h
-478
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File diff suppressed because it is too large. Load diff
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h
-580
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File diff suppressed because it is too large. Load diff
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html
-14
View File
@@ -1,14 +0,0 @@
<!doctype html>
<html>
<head>
<meta charset='UTF-8'><meta name='viewport' content='width=device-width initial-scale=1'>
<title>ReleaseNote</title></head>
<body><h1>ES32F065x MD Release Note</h1>
<h2>V1.00 2018-12-26</h2>
<ol start='' >
<li>First release</li>
</ol>
<p>&nbsp;</p>
</body>
</html>
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c
-213
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File diff suppressed because it is too large. Load diff
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c
-222
View File
File diff suppressed because it is too large. Load diff
bsp/es32f0654/.config → bsp/essemi/es32f0654/.config
+88 -25
View File
File diff suppressed because it is too large. Load diff
bsp/es32f0654/Kconfig → bsp/essemi/es32f0654/Kconfig
+1 -1
View File
@@ -8,7 +8,7 @@ config BSP_DIR
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
default "../../.."
config PKGS_DIR
string
bsp/es32f0654/README.md → bsp/essemi/es32f0654/README.md
+1
View File
@@ -40,6 +40,7 @@ ES-PDS-ES32F0654-V1.1
| UART | 支持 | UART0/1/2/3 |
| SPI | 支持 | SPI0/1 |
| I2C | 支持 | I2C0/1 |
| CAN | 支持 | CAN0 |
| PWM | 支持 | PWM0/1/2/3 |
| TIMER | 支持 | TIMER0/1/2/3 |
| RTC | 支持 | RTC |
bsp/es32f0654/SConscript → bsp/essemi/es32f0654/SConscript
View File
File renamed without changes.
bsp/es32f0654/SConstruct → bsp/essemi/es32f0654/SConstruct
+1 -1
View File
@@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
bsp/es32f0654/applications/SConscript → bsp/essemi/es32f0654/applications/SConscript
View File
File renamed without changes.
bsp/es32f0654/applications/main.c → bsp/essemi/es32f0654/applications/main.c
View File
File renamed without changes.
bsp/es32f0654/drivers/Kconfig → bsp/essemi/es32f0654/drivers/Kconfig
+7
View File
@@ -56,6 +56,13 @@ menu "Hardware Drivers Config"
default n
endmenu
menu "CAN Drivers"
config BSP_USING_CAN
bool "Enable CAN BUS PA11/PA12(RX/TX)"
select RT_USING_CAN
default n
endmenu
menu "PWM Drivers"
config BSP_USING_PWM0
bool "Using PWM0 PA08/PA09/PA10/PA11"
bsp/es32f0654/drivers/SConscript → bsp/essemi/es32f0654/drivers/SConscript
+4
View File
@@ -23,6 +23,10 @@ if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'):
if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
src += ['drv_i2c.c']
# add can driver code
if GetDepend('BSP_USING_CAN'):
src += ['drv_can.c']
# add spi flash driver code
if GetDepend('BSP_USING_SPI_FLASH'):
src += ['drv_spiflash.c']
bsp/es32f0654/drivers/board.c → bsp/essemi/es32f0654/drivers/board.c
+6 -5
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-23 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -43,10 +44,10 @@ void NVIC_Configuration(void)
void SystemClock_Config(void)
{
/* hosc 12MHz, from hosc/3 pll to 48MHz */
cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
/* MCLK 48MHz*/
cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
}
/*******************************************************************************
@@ -59,14 +60,14 @@ void SystemClock_Config(void)
void SysTick_Configuration(void)
{
/* ticks = sysclk / RT_TICK_PER_SECOND */
SysTick_Config(cmu_get_sys_clock() / RT_TICK_PER_SECOND);
SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND);
}
/**
* This is the timer interrupt service routine.
*
*/
void systick_irq_cbk(void)
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@@ -113,7 +114,7 @@ void rt_hw_us_delay(rt_uint32_t us)
unsigned int start, now, delta, reload, us_tick;
start = SysTick->VAL;
reload = SysTick->LOAD;
us_tick = cmu_get_sys_clock() / 1000000UL;
us_tick = ald_cmu_get_sys_clock() / 1000000UL;
do
{
now = SysTick->VAL;
bsp/es32f0654/drivers/board.h → bsp/essemi/es32f0654/drivers/board.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_adc.c → bsp/essemi/es32f0654/drivers/drv_adc.c
+28 -28
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-04-03 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -58,67 +59,67 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
{
case 0:
es32f0_channel = ADC_CHANNEL_0;
gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
break;
case 1:
es32f0_channel = ADC_CHANNEL_1;
gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
break;
case 2:
es32f0_channel = ADC_CHANNEL_2;
gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
break;
case 3:
es32f0_channel = ADC_CHANNEL_3;
gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
break;
case 4:
es32f0_channel = ADC_CHANNEL_4;
gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
break;
case 5:
es32f0_channel = ADC_CHANNEL_5;
gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
break;
case 6:
es32f0_channel = ADC_CHANNEL_6;
gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
break;
case 7:
es32f0_channel = ADC_CHANNEL_7;
gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
break;
case 8:
es32f0_channel = ADC_CHANNEL_8;
gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
break;
case 9:
es32f0_channel = ADC_CHANNEL_9;
gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
break;
case 10:
es32f0_channel = ADC_CHANNEL_10;
gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
break;
case 11:
es32f0_channel = ADC_CHANNEL_11;
gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
break;
case 12:
es32f0_channel = ADC_CHANNEL_12;
gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
break;
case 13:
es32f0_channel = ADC_CHANNEL_13;
gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
break;
case 14:
es32f0_channel = ADC_CHANNEL_14;
gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
break;
case 15:
es32f0_channel = ADC_CHANNEL_15;
gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
break;
case 16:
es32f0_channel = ADC_CHANNEL_16;
@@ -139,21 +140,21 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
adc_channel_conf_t nm_config;
adc_nch_conf_t nm_config;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
/* config adc channel */
nm_config.channel = es32f0_adc_get_channel(channel);
nm_config.rank = ADC_NC_RANK_1;
nm_config.sampling_time = ADC_SAMPLETIME_4;
adc_normal_channel_config(_hadc, &nm_config);
nm_config.rank = ADC_NCH_RANK_1;
nm_config.samp_time = ADC_SAMPLETIME_4;
ald_adc_normal_channel_config(_hadc, &nm_config);
adc_normal_start(_hadc);
ald_adc_normal_start(_hadc);
if (adc_normal_poll_for_conversion(_hadc, 5000) == OK)
*value = adc_normal_get_value(_hadc);
if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK)
*value = ald_adc_normal_get_value(_hadc);
return RT_EOK;
}
@@ -172,17 +173,16 @@ int rt_hw_adc_init(void)
/* adc function initialization */
_h_adc0.perh = ADC0;
_h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan_mode = ADC_SCAN_DISABLE;
_h_adc0.init.scan_mode = DISABLE;
_h_adc0.init.cont_mode = DISABLE;
_h_adc0.init.conv_nbr = ADC_NM_NBR_1;
_h_adc0.init.disc_mode = DISABLE;
_h_adc0.init.disc_mode = ADC_ALL_DISABLE;
_h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
_h_adc0.init.conv_res = ADC_CONV_RES_10;
_h_adc0.init.clk_div = ADC_CKDIV_128;
_h_adc0.init.nche_mode = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
_h_adc0.init.pos_ref = ADC_POS_REF_VDD;
adc_init(&_h_adc0);
ald_adc_init(&_h_adc0);
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);
bsp/es32f0654/drivers/drv_adc.h → bsp/essemi/es32f0654/drivers/drv_adc.h
View File
File renamed without changes.
bsp/essemi/es32f0654/drivers/drv_can.c
+605
View File
File diff suppressed because it is too large. Load diff
bsp/essemi/es32f0654/drivers/drv_can.h
+37
View File
@@ -0,0 +1,37 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-11-09 wangyq the first version
*/
#ifndef DRV_CAN_H__
#define DRV_CAN_H__
#include <board.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <ald_can.h>
#include <ald_gpio.h>
struct es32f0_baud_rate_tab
{
rt_uint32_t baud_rate;
rt_uint32_t config_data;
};
/* es32f0 can device */
struct es32f0_can
{
can_handle_t CanHandle;
can_filter_t FilterConfig;
struct rt_can_device device; /* inherit from can device */
};
int rt_hw_can_init(void);
#endif /*DRV_CAN_H__ */
bsp/es32f0654/drivers/drv_gpio.c → bsp/essemi/es32f0654/drivers/drv_gpio.c
+12 -11
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-23 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -167,7 +168,7 @@ void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
return;
}
gpio_write_pin(index->gpio, index->pin, value);
ald_gpio_write_pin(index->gpio, index->pin, value);
}
int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
@@ -180,7 +181,7 @@ int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
{
return value;
}
value = gpio_read_pin(index->gpio, index->pin);
value = ald_gpio_read_pin(index->gpio, index->pin);
return value;
}
@@ -233,7 +234,7 @@ void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
gpio_initstruct.pupd = GPIO_FLOATING;
gpio_initstruct.odos = GPIO_OPEN_DRAIN;
}
gpio_init(index->gpio, index->pin, &gpio_initstruct);
ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
}
rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
@@ -360,7 +361,7 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
return RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
/* Configure GPIO_InitStructure */
gpio_initstruct.mode = GPIO_MODE_INPUT;
gpio_initstruct.func = GPIO_FUNC_1;
@@ -368,18 +369,18 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
{
case PIN_IRQ_MODE_RISING:
gpio_initstruct.pupd = GPIO_PUSH_DOWN;
gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
break;
case PIN_IRQ_MODE_FALLING:
gpio_initstruct.pupd = GPIO_PUSH_UP;
gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
break;
case PIN_IRQ_MODE_RISING_FALLING:
gpio_initstruct.pupd = GPIO_FLOATING;
gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
break;
}
gpio_init(index->gpio, index->pin, &gpio_initstruct);
ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
NVIC_EnableIRQ(irqmap->irqno);
rt_hw_interrupt_enable(level);
}
@@ -412,7 +413,7 @@ const static struct rt_pin_ops _es32f0_pin_ops =
int rt_hw_pin_init(void)
{
int result;
cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
return result;
}
@@ -439,9 +440,9 @@ rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
if (gpio_exti_get_flag_status(GPIO_Pin) != RESET)
if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
{
gpio_exti_clear_flag_status(GPIO_Pin);
ald_gpio_exti_clear_flag_status(GPIO_Pin);
pin_irq_hdr(GPIO_Pin);
}
}
bsp/es32f0654/drivers/drv_gpio.h → bsp/essemi/es32f0654/drivers/drv_gpio.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_hwtimer.c → bsp/essemi/es32f0654/drivers/drv_hwtimer.c
+24 -23
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-3-19 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -30,12 +31,12 @@ static struct es32f0_hwtimer_dev hwtimer0;
void BS16T0_Handler(void)
{
timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer0.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode)
{
timer_base_stop(hwtimer0.hwtimer_periph);
ald_timer_base_stop(hwtimer0.hwtimer_periph);
}
}
#endif
@@ -46,15 +47,15 @@ static struct es32f0_hwtimer_dev hwtimer1;
void BS16T1_UART2_Handler(void)
{
/* if BS16T1 it */
if (timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
{
timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer1.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
{
timer_base_stop(hwtimer1.hwtimer_periph);
ald_timer_base_stop(hwtimer1.hwtimer_periph);
}
}
}
@@ -66,15 +67,15 @@ static struct es32f0_hwtimer_dev hwtimer2;
void BS16T2_UART3_Handler(void)
{
/* if BS16T2 it */
if (timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) &&
timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE))
if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) &&
ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE))
{
timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE);
ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer2.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode)
{
timer_base_stop(hwtimer2.hwtimer_periph);
ald_timer_base_stop(hwtimer2.hwtimer_periph);
}
}
}
@@ -86,15 +87,15 @@ static struct es32f0_hwtimer_dev hwtimer3;
void BS16T3_DAC0_Handler(void)
{
/* if BS16T3 it */
if (timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) &&
timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE))
if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) &&
ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE))
{
timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE);
ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer3.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode)
{
timer_base_stop(hwtimer3.hwtimer_periph);
ald_timer_base_stop(hwtimer3.hwtimer_periph);
}
}
}
@@ -116,13 +117,13 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
if (1 == state)
{
timer_base_init(hwtimer->hwtimer_periph);
timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
ald_timer_base_init(hwtimer->hwtimer_periph);
ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
NVIC_EnableIRQ(hwtimer->IRQn);
}
hwtimer->parent.freq = cmu_get_pclk1_clock();
es32f0_hwtimer_info.maxfreq = cmu_get_pclk1_clock();
es32f0_hwtimer_info.minfreq = cmu_get_pclk1_clock();
hwtimer->parent.freq = ald_cmu_get_pclk1_clock();
es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock();
es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock();
}
static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
@@ -134,7 +135,7 @@ static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
RT_ASSERT(hwtimer != RT_NULL);
WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
timer_base_start(hwtimer->hwtimer_periph);
ald_timer_base_start(hwtimer->hwtimer_periph);
return RT_EOK;
}
@@ -145,7 +146,7 @@ static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
RT_ASSERT(hwtimer != RT_NULL);
timer_base_stop(hwtimer->hwtimer_periph);
ald_timer_base_stop(hwtimer->hwtimer_periph);
}
static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
@@ -174,14 +175,14 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
{
case HWTIMER_CTRL_FREQ_SET:
freq = *(rt_uint32_t *)args;
if (freq != cmu_get_pclk1_clock())
if (freq != ald_cmu_get_pclk1_clock())
{
ret = -RT_ERROR;
}
break;
case HWTIMER_CTRL_STOP:
timer_base_stop(hwtimer->hwtimer_periph);
ald_timer_base_stop(hwtimer->hwtimer_periph);
break;
default:
bsp/es32f0654/drivers/drv_hwtimer.h → bsp/essemi/es32f0654/drivers/drv_hwtimer.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_i2c.c → bsp/essemi/es32f0654/drivers/drv_i2c.c
+9 -8
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-24 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -45,10 +46,10 @@ static void _i2c_init(void)
_h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE;
_h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE;
i2c_reset(&_h_i2c0);
i2c_init(&_h_i2c0);
ald_i2c_reset(&_h_i2c0);
ald_i2c_init(&_h_i2c0);
/* I2C0_SCL->PB8, I2C0_SDA->PB9 */
gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
#endif
#ifdef BSP_USING_I2C1
@@ -61,10 +62,10 @@ static void _i2c_init(void)
_h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE;
_h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE;
i2c_reset(&_h_i2c1);
i2c_init(&_h_i2c1);
ald_i2c_reset(&_h_i2c1);
ald_i2c_init(&_h_i2c1);
/* I2C1_SCL->PB10, I2C1_SDA->PB11 */
gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct);
ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct);
#endif
}
@@ -81,7 +82,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus,
msg = &msgs[i];
if (msg->flags & RT_I2C_RD)
{
if (i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
{
i2c_dbg("i2c bus write failed,i2c bus stop!\n");
goto out;
@@ -89,7 +90,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus,
}
else
{
if (i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
{
i2c_dbg("i2c bus write failed,i2c bus stop!\n");
goto out;
bsp/es32f0654/drivers/drv_i2c.h → bsp/essemi/es32f0654/drivers/drv_i2c.h
View File
File renamed without changes.
bsp/essemi/es32f0654/drivers/drv_pm.c
+226
View File
File diff suppressed because it is too large. Load diff
bsp/es32f0654/drivers/drv_pm.h → bsp/essemi/es32f0654/drivers/drv_pm.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_pwm.c → bsp/essemi/es32f0654/drivers/drv_pwm.c
+23 -22
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-03-11 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -18,7 +19,7 @@
static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
{
uint64_t _arr = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 /
uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
(timer_initstruct->init.prescaler + 1);
WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
@@ -27,7 +28,7 @@ static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns)
{
uint64_t tmp = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 /
uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
(timer_initstruct->init.prescaler + 1);
if (ch == TIMER_CHANNEL_1)
@@ -87,11 +88,11 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
switch (cmd)
{
case PWM_CMD_ENABLE:
timer_pwm_start(timer_initstruct, pwm_channel);
ald_timer_pwm_start(timer_initstruct, pwm_channel);
break;
case PWM_CMD_DISABLE:
timer_pwm_stop(timer_initstruct, pwm_channel);
ald_timer_pwm_stop(timer_initstruct, pwm_channel);
break;
case PWM_CMD_SET:
@@ -105,13 +106,13 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
while (timer_initstruct->init.period > 0xFFFF);
/* update prescaler */
WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler);
timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse);
timer_initstruct->perh->CCEP = _ccep;
break;
case PWM_CMD_GET:
cfg->pulse = timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
READ_REG(timer_initstruct->perh->AR);
break;
@@ -143,14 +144,14 @@ int rt_hw_pwm_init(void)
static timer_handle_t timer_initstruct0;
timer_initstruct0.perh = AD16C4T0;
timer_pwm_init(&timer_initstruct0);
ald_timer_pwm_init(&timer_initstruct0);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_2;
gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure);
gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure);
gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure);
gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops,
&timer_initstruct0);
@@ -161,14 +162,14 @@ int rt_hw_pwm_init(void)
static timer_handle_t timer_initstruct1;
timer_initstruct1.perh = GP16C4T0;
timer_pwm_init(&timer_initstruct1);
ald_timer_pwm_init(&timer_initstruct1);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_2;
gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops,
&timer_initstruct1);
@@ -179,12 +180,12 @@ int rt_hw_pwm_init(void)
static timer_handle_t timer_initstruct2;
timer_initstruct2.perh = GP16C2T0;
timer_pwm_init(&timer_initstruct2);
ald_timer_pwm_init(&timer_initstruct2);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_2;
gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops,
&timer_initstruct2);
@@ -195,12 +196,12 @@ int rt_hw_pwm_init(void)
static timer_handle_t timer_initstruct3;
timer_initstruct3.perh = GP16C2T1;
timer_pwm_init(&timer_initstruct3);
ald_timer_pwm_init(&timer_initstruct3);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_3;
gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure);
gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops,
&timer_initstruct3);
bsp/es32f0654/drivers/drv_pwm.h → bsp/essemi/es32f0654/drivers/drv_pwm.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_rtc.c → bsp/essemi/es32f0654/drivers/drv_rtc.c
+6 -5
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-03-22 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -25,7 +26,7 @@ static void __rtc_init(rtc_init_t *init)
assert_param(IS_RTC_OUTPUT_SEL(init->output));
assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
rtc_reset();
ald_rtc_reset();
RTC_UNLOCK();
MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
@@ -51,7 +52,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
rtc_get_date_time(&date, &time, RTC_FORMAT_DEC);
ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC);
time_temp.tm_sec = time.second;
time_temp.tm_min = time.minute;
time_temp.tm_hour = time.hour;
@@ -77,8 +78,8 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
date.year = time_temp.tm_year + 1900 - 2000;
date.month = time_temp.tm_mon + 1;
date.day = time_temp.tm_mday;
rtc_set_time(&time, RTC_FORMAT_DEC);
rtc_set_date(&date, RTC_FORMAT_DEC);
ald_rtc_set_time(&time, RTC_FORMAT_DEC);
ald_rtc_set_date(&date, RTC_FORMAT_DEC);
/* start RTC */
RTC_UNLOCK();
SET_BIT(RTC->CON, RTC_CON_GO_MSK);
@@ -118,7 +119,7 @@ int rt_hw_rtc_init(void)
/* enable external 32.768kHz */
CMU_LOSC_ENABLE();
cmu_losc_safe_config(ENABLE);
ald_cmu_losc_safe_config(ENABLE);
/* set default time */
RTC_UNLOCK();
WRITE_REG(RTC->TIME, 0x134251);
bsp/es32f0654/drivers/drv_rtc.h → bsp/essemi/es32f0654/drivers/drv_rtc.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_spi.c → bsp/essemi/es32f0654/drivers/drv_spi.c
+20 -19
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-24 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rtthread.h>
@@ -80,14 +81,14 @@ rt_err_t spi_configure(struct rt_spi_device *device,
}
/* config spi clock */
if (cfg->max_hz >= cmu_get_pclk1_clock() / 2)
if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
{
/* pclk1 max speed 48MHz, spi master max speed 10MHz */
if (cmu_get_pclk1_clock() / 2 <= 10000000)
if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
{
hspi->init.baud = SPI_BAUD_2;
}
else if (cmu_get_pclk1_clock() / 4 <= 10000000)
else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
{
hspi->init.baud = SPI_BAUD_4;
}
@@ -96,10 +97,10 @@ rt_err_t spi_configure(struct rt_spi_device *device,
hspi->init.baud = SPI_BAUD_8;
}
}
else if (cfg->max_hz >= cmu_get_pclk1_clock() / 4)
else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
{
/* pclk1 max speed 48MHz, spi master max speed 10MHz */
if (cmu_get_pclk1_clock() / 4 <= 10000000)
if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
{
hspi->init.baud = SPI_BAUD_4;
}
@@ -108,23 +109,23 @@ rt_err_t spi_configure(struct rt_spi_device *device,
hspi->init.baud = SPI_BAUD_8;
}
}
else if (cfg->max_hz >= cmu_get_pclk1_clock() / 8)
else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
{
hspi->init.baud = SPI_BAUD_8;
}
else if (cfg->max_hz >= cmu_get_pclk1_clock() / 16)
else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
{
hspi->init.baud = SPI_BAUD_16;
}
else if (cfg->max_hz >= cmu_get_pclk1_clock() / 32)
else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
{
hspi->init.baud = SPI_BAUD_32;
}
else if (cfg->max_hz >= cmu_get_pclk1_clock() / 64)
else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
{
hspi->init.baud = SPI_BAUD_64;
}
else if (cfg->max_hz >= cmu_get_pclk1_clock() / 128)
else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
{
hspi->init.baud = SPI_BAUD_128;
}
@@ -132,7 +133,7 @@ rt_err_t spi_configure(struct rt_spi_device *device,
{
hspi->init.baud = SPI_BAUD_256;
}
spi_init(hspi);
ald_spi_init(hspi);
return RT_EOK;
}
@@ -157,7 +158,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
{
rt_pin_write(cs->pin, 0);
}
res = spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
@@ -173,7 +174,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
{
rt_pin_write(cs->pin, 0);
}
res = spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
@@ -189,8 +190,8 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
{
rt_pin_write(cs->pin, 0);
}
res = spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
(rt_int32_t)message->length, SPITIMEOUT);
res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
(rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
@@ -230,11 +231,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB3->SPI0_SCK, PB5->SPI0_MOSI */
gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
/* PB4->SPI0_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
}
else if (SPIx == SPI1)
{
@@ -250,11 +251,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB13->SPI1_SCK, PB15->SPI1_MOSI */
gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
/* PB14->SPI1_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
}
else
{
bsp/es32f0654/drivers/drv_spi.h → bsp/essemi/es32f0654/drivers/drv_spi.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_spiflash.c → bsp/essemi/es32f0654/drivers/drv_spiflash.c
+1
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-02-15 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rtthread.h>
bsp/es32f0654/drivers/drv_spiflash.h → bsp/essemi/es32f0654/drivers/drv_spiflash.h
View File
File renamed without changes.
bsp/es32f0654/drivers/drv_uart.c → bsp/essemi/es32f0654/drivers/drv_uart.c
+13 -12
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2019-01-23 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
@@ -43,38 +44,38 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial
#ifdef BSP_USING_UART0
gpio_initstructure.func = GPIO_FUNC_3;
gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure);
/* Initialize rx pin ,the same as txpin except mode */
gpio_initstructure.mode = GPIO_MODE_INPUT;
gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure);
#endif /* uart0 gpio init */
#ifdef BSP_USING_UART1
gpio_initstructure.func = GPIO_FUNC_3;
gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure);
/* Initialize rx pin ,the same as txpin except mode */
gpio_initstructure.mode = GPIO_MODE_INPUT;
gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure);
#endif /* uart1 gpio init */
#ifdef BSP_USING_UART2
gpio_initstructure.func = GPIO_FUNC_5;
gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure);
/* Initialize rx pin ,the same as txpin except mode */
gpio_initstructure.mode = GPIO_MODE_INPUT;
gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure);
ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure);
#endif /* uart2 gpio init */
#ifdef BSP_USING_UART3
gpio_initstructure.func = GPIO_FUNC_4;
gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure);
/* Initialize rx pin ,the same as txpin except mode */
gpio_initstructure.mode = GPIO_MODE_INPUT;
gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure);
ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure);
#endif /* uart3 gpio init */
uart->huart.init.mode = UART_MODE_UART;
@@ -82,7 +83,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial
uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5);
uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE;
uart_init(&uart->huart);
ald_uart_init(&uart->huart);
if (cfg->bit_order == BIT_ORDER_MSB)
{
@@ -103,7 +104,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial
}
/* enable rx int */
uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
return RT_EOK;
}
@@ -120,14 +121,14 @@ static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *
/* disable rx irq */
NVIC_DisableIRQ(uart->irq);
/* disable interrupt */
uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irq);
/* enable interrupt */
uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
break;
}
bsp/es32f0654/drivers/drv_uart.h → bsp/essemi/es32f0654/drivers/drv_uart.h
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bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h
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bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s → bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s
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bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s → bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s
+171 -171
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bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c → bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h
+355
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h
+572
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
+186
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@@ -0,0 +1,186 @@
/**
*********************************************************************************
*
* @file ald_bkpc.h
* @brief Header file of BKPC module driver.
*
* @version V1.0
* @date 15 Dec 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
********************************************************************************
*/
#ifndef __ALD_BKPC_H__
#define __ALD_BKPC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup BKPC
* @{
*/
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55))
#define BKPC_LRC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
/**
* @}
*/
/** @defgroup BKPC_Public_Types BKPC Public Types
* @{
*/
/**
* @brief BKPC ldo output select
*/
typedef enum
{
BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief BKPC BOR voltage select
*/
typedef enum
{
BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */
BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */
BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */
BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */
BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */
BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */
BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */
BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */
BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */
BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */
BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */
BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */
BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */
BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */
BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */
BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */
} bkpc_bor_vol_t;
/**
* @}
*/
/**
* @defgroup BKPC_Private_Macros BKPC Private Macros
* @{
*/
#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \
((x) == BKPC_BOR_VOL_2_0) || \
((x) == BKPC_BOR_VOL_2_1) || \
((x) == BKPC_BOR_VOL_2_2) || \
((x) == BKPC_BOR_VOL_2_3) || \
((x) == BKPC_BOR_VOL_2_4) || \
((x) == BKPC_BOR_VOL_2_5) || \
((x) == BKPC_BOR_VOL_2_6) || \
((x) == BKPC_BOR_VOL_2_8) || \
((x) == BKPC_BOR_VOL_3_0) || \
((x) == BKPC_BOR_VOL_3_1) || \
((x) == BKPC_BOR_VOL_3_3) || \
((x) == BKPC_BOR_VOL_3_6) || \
((x) == BKPC_BOR_VOL_3_7) || \
((x) == BKPC_BOR_VOL_4_0) || \
((x) == BKPC_BOR_VOL_4_3))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions
* @{
*/
/** @addtogroup BKPC_Public_Functions_Group1
* @{
*/
/* control functions */
extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
/**
* @}
*/
/** @addtogroup BKPC_Public_Functions_Group2
* @{
*/
/* IO operation functions */
extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value);
extern uint32_t ald_bkpc_read_ram(uint8_t idx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_BKPC_H__ */
bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h → bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h
+4 -4
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@@ -35,10 +35,10 @@ extern "C" {
/** @addtogroup CALC_Public_Functions
* @{
*/
extern uint32_t calc_sqrt(uint32_t data);
extern uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
extern int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
extern flag_status_t calc_get_dz_status(void);
extern uint32_t ald_calc_sqrt(uint32_t data);
extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
extern flag_status_t ald_calc_get_dz_status(void);
/**
* @}
*/
bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h
+491
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h
+653
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h → bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h
+202
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h
+264
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bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h → bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h
+24 -24
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@@ -43,10 +43,10 @@ extern "C" {
*/
typedef enum
{
DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */
DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */
} dbgc_mode_t;
/**
@@ -54,21 +54,21 @@ typedef enum
*/
typedef enum
{
DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1u << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */
DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */
DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */
DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1u << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */
DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */
DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */
} dbgc_perh_t;
/**
* @}
@@ -81,7 +81,7 @@ typedef enum
* @brief Gets version.
* @retval Version
*/
__INLINE uint32_t dbgc_get_rev_id(void)
__INLINE uint32_t ald_dbgc_get_rev_id(void)
{
return (DBGC->IDCODE >> 16);
}
@@ -90,7 +90,7 @@ __INLINE uint32_t dbgc_get_rev_id(void)
* @brief Gets core id.
* @retval Core id
*/
__INLINE uint32_t dbgc_get_core_id(void)
__INLINE uint32_t ald_dbgc_get_core_id(void)
{
return (DBGC->IDCODE >> 12) & 0xF;
}
@@ -99,7 +99,7 @@ __INLINE uint32_t dbgc_get_core_id(void)
* @brief Gets device id
* @retval device id
*/
__INLINE uint32_t dbgc_get_device_id(void)
__INLINE uint32_t ald_dbgc_get_device_id(void)
{
return DBGC->IDCODE & 0xFFF;
}
@@ -110,7 +110,7 @@ __INLINE uint32_t dbgc_get_device_id(void)
* @param state: ENABLE/DISABLE
* @retval None
*/
__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
{
if (state)
SET_BIT(DBGC->CR, mode);
@@ -124,7 +124,7 @@ __INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
* @param state: ENABLE/DISABLE
* @retval None
*/
__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
{
if ((perh >> 16) & 0x1)
{
bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h
+409
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bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h
+129
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@@ -0,0 +1,129 @@
/**
*********************************************************************************
*
* @file ald_flash.h
* @brief Header file of FLASH driver
*
* @version V1.0
* @date 20 Nov 2017
* @author AE Team
* @note
*
* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
*
*********************************************************************************
*/
#ifndef __ALD_FLASH_H__
#define __ALD_FLASH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "utils.h"
/** @addtogroup ES32FXXX_ALD
* @{
*/
/** @addtogroup FLASH
* @{
*/
/**
* @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#define FLASH_REG_UNLOCK() \
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
} \
} while (0)
#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_BASE_ADDR 0x00000000
#define FLASH_PAGE_SIZE 1024UL
#define FLASH_WORD_SIZE 8UL
#define FLASH_TOTAL_SIZE 256UL
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
#define INFO_PAGE_SIZE 1024UL
#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#ifdef USE_FLASH_FIFO
#define FLASH_FIFO 1
#else
#define FLASH_FIFO 0
#endif
/**
* @}
*/
/** @defgroup FLASH_Private_Types FLASH Private Types
* @{
*/
typedef enum
{
FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */
} flash_cmd_type;
typedef enum
{
OP_FLASH = 0, /**< Operate Pragram area */
OP_INFO = 1, /**< Operate info area */
} op_cmd_type;
/**
* @}
*/
/** @addtogroup Flash_Private_Functions
* @{
*/
ald_status_t flash_page_erase(uint32_t addr);
ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo);
/**
* @}
*/
/** @addtogroup Flash_Public_Functions
* @{
*/
ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
ald_status_t ald_flash_erase(uint32_t addr, uint16_t len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ALD_FLASH_H__ */
bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h
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