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Merge pull request #30 from RT-Thread/master

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This commit is contained in:
Meco Jianting Man
2021-03-24 00:26:05 +08:00
committed by GitHub
parent 061182271f 50bf490263
commit 8fccef5894
789 changed files with 13303 additions and 13180 deletions
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7
bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig
View File

@@ -167,11 +167,16 @@ menu "On-chip Peripheral Drivers"
default n
endif
config BSP_USING_ONCHIP_RTC
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
config RTC_USING_INTERNAL_CLK
bool "Using internal clock RTC"
default y
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"

2
bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py
View File

@@ -41,7 +41,7 @@ if PLATFORM == 'gcc':
# DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32'
# CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
CFLAGS = DEVICE
CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = ''

47
bsp/bluetrum/libraries/hal_drivers/drv_rtc.c
View File

@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2021-01-28 greedyhao first version
* 2021-03-19 iysheng modify just set time first power up
*/
#include "board.h"
@@ -95,30 +96,44 @@ uint8_t irtc_sfr_read(uint32_t cmd)
IRTC_EXIT_CRITICAL();
}
static void _init_rtc_clock(void)
{
uint8_t rtccon0;
uint8_t rtccon2;
rtccon0 = irtc_sfr_read(RTCCON0_CMD);
rtccon2 = irtc_sfr_read(RTCCON2_CMD);
#ifdef RTC_USING_INTERNAL_CLK
rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE;
rtccon0 |= RTC_CON0_INTERNAL_32K;
rtccon2 | RTC_CON2_32K_SELECT;
#else
rtccon0 |= RTC_CON0_XOSC32K_ENABLE;
rtccon0 &= ~RTC_CON0_INTERNAL_32K;
rtccon2 & ~RTC_CON2_32K_SELECT;
#endif
irtc_sfr_write(RTCCON0_CMD, rtccon0);
irtc_sfr_write(RTCCON2_CMD, rtccon2);
}
void hal_rtc_init(void)
{
time_t sec = 0;
struct tm tm_new = {0};
uint8_t temp;
uint8_t temp = irtc_sfr_read(RTCCON0_CMD);
temp &= ~RTC_CON0_XOSC32K_ENABLE;
temp |= RTC_CON0_EXTERNAL_32K;
irtc_sfr_write(RTCCON0_CMD, temp);
temp = irtc_sfr_read(RTCCON2_CMD);
irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT);
_init_rtc_clock();
temp = irtc_sfr_read(RTCCON0_CMD);
if (temp & BIT(7)) {
temp &= ~BIT(7);
if (temp & RTC_CON0_PWRUP_FIRST) {
temp &= ~RTC_CON0_PWRUP_FIRST;
irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */
tm_new.tm_mday = 29;
tm_new.tm_mon = 1 - 1;
tm_new.tm_year = 2021 - 1900;
sec = timegm(&tm_new);
irtc_time_write(RTCCNT_CMD, sec);
}
tm_new.tm_mday = 29;
tm_new.tm_mon = 1 - 1;
tm_new.tm_year = 2021 - 1900;
sec = timegm(&tm_new);
irtc_time_write(RTCCNT_CMD, sec);
}
/************** HAL End *******************/

2
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h
View File

@@ -34,7 +34,7 @@ enum
// RTCCON0
#define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */
#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */
#define RTC_CON0_INTERNAL_32K (0x01u << 6) /*!< Internal 32K select */
#define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */
#define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */
#define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */

4
bsp/lpc1114/driver/board.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,7 +33,7 @@
#define NVIC_ISPR HWREG32(SCB_BASE + 0x200)
#define NVIC_ICPR HWREG32(SCB_BASE + 0x280)
#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
extern unsigned char __bss_end__[];
extern unsigned char _ram_end[];

2
bsp/lpc1114/driver/drv_uart.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

36
bsp/lpc176x/applications/application.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -38,44 +38,44 @@ extern int lwip_system_init(void);
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
/* initialize platform */
platform_init();
/* initialize platform */
platform_init();
#ifdef RT_USING_LWIP
/* register Ethernet interface device */
lpc17xx_emac_hw_init();
/* initialize lwip stack */
/* register ethernetif device */
eth_system_device_init();
/* register ethernetif device */
eth_system_device_init();
/* initialize lwip system */
lwip_system_init();
rt_kprintf("TCP/IP initialized!\n");
/* initialize lwip system */
lwip_system_init();
rt_kprintf("TCP/IP initialized!\n");
#endif
/* Filesystem Initialization */
#ifdef RT_USING_DFS
rt_hw_sdcard_init();
/* initialize the device file system */
dfs_init();
/* initialize the device file system */
dfs_init();
#ifdef RT_USING_DFS_ELMFAT
/* initialize the elm chan FatFS file system*/
elm_init();
/* initialize the elm chan FatFS file system*/
elm_init();
#endif
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
rt_kprintf("File System initialized!\n");
else
rt_kprintf("File System init failed!\n");
rt_kprintf("File System init failed!\n");
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
/* initialize finsh */
finsh_system_init();
#endif
}
@@ -84,8 +84,8 @@ int rt_application_init()
rt_thread_t tid;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;

8
bsp/lpc176x/applications/platform.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
void platform_init(void)
{
#ifdef RT_USING_MEMHEAP
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
#ifdef RT_USING_LWIP
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
#else
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
#endif
#endif
}

2
bsp/lpc176x/applications/platform.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

56
bsp/lpc176x/applications/startup.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,28 +33,28 @@ extern int __bss_end;
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
#endif
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize application */
rt_application_init();
/* initialize application */
rt_application_init();
/* initialize timer */
rt_system_timer_init();
@@ -62,25 +62,25 @@ void rtthread_startup(void)
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
return 0;
}
/*@}*/

34
bsp/lpc176x/drivers/board.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -29,13 +29,13 @@
*/
void rt_hw_timer_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
}
void SysTick_Handler(void)
@@ -48,24 +48,24 @@ void SysTick_Handler(void)
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
/* initialize systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
/* initialize systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_UART0
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

2
bsp/lpc176x/drivers/board.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

714
bsp/lpc176x/drivers/emac.c
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File diff suppressed because it is too large Load Diff

11
bsp/lpc176x/drivers/emac.h
View File

@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
@@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE 0x20080000
#define RX_DESC_BASE 0x20080000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)

2
bsp/lpc176x/drivers/led.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/lpc176x/drivers/sd.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
if (dev->user_data == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize;
geometry->block_size = ((SDCFG *)dev->user_data)->blocksize;
geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt;

229
bsp/lpc176x/drivers/spi.c
View File

@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include "LPC17xx.h" /* LPC17xx definitions */
#include "spi.h"
@@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
/* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
void LPC17xx_SPI_Init (void)
{
uint32_t dummy;
uint32_t dummy;
dummy = dummy; // avoid warning
dummy = dummy; // avoid warning
#if 0
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
#else
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */
LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/
LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */
LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/
LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */
LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */
LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */
#endif
/* PCLK_SSP0=CCLK */
LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */
/* PCLK_SSP0=CCLK */
LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */
LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */
LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */
LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
/* wait for busy gone */
while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* wait for busy gone */
while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* drain SPI RX FIFO */
while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
{
dummy = LPC_SSP0->DR;
}
/* drain SPI RX FIFO */
while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
{
dummy = LPC_SSP0->DR;
}
}
/* Close SSP0 */
void LPC17xx_SPI_DeInit( void )
{
// disable SPI
LPC_SSP0->CR1 = 0;
// disable SPI
LPC_SSP0->CR1 = 0;
#if 0
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
#else
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
#endif
// disable SSP power
LPC_SC->PCONP &= ~(1 << 21);
// disable SSP power
LPC_SC->PCONP &= ~(1 << 21);
}
/* Set a SSP0 clock speed to desired value. */
void LPC17xx_SPI_SetSpeed (uint8_t speed)
{
speed &= 0xFE;
if ( speed < 2 ) {
speed = 2 ;
}
LPC_SSP0->CPSR = speed;
speed &= 0xFE;
if ( speed < 2 ) {
speed = 2 ;
}
LPC_SSP0->CPSR = speed;
}
/* SSEL: low */
void LPC17xx_SPI_Select ()
{
#if 0
LPC_GPIO0->FIOPIN &= ~(1<<16);
LPC_GPIO0->FIOPIN &= ~(1<<16);
#else
LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */
LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */
#endif
}
@@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
void LPC17xx_SPI_DeSelect ()
{
#if 0
LPC_GPIO0->FIOPIN |= (1<<16);
LPC_GPIO0->FIOPIN |= (1<<16);
#else
LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */
LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */
#endif
}
/* Send one byte then recv one byte of response. */
static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s)
{
uint8_t byte_r;
uint8_t byte_r;
LPC_SSP0->DR = byte_s;
while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */
byte_r = LPC_SSP0->DR;
LPC_SSP0->DR = byte_s;
while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */
byte_r = LPC_SSP0->DR;
return byte_r; /* Return received value */
return byte_r; /* Return received value */
}
/* Send one byte */
void LPC17xx_SPI_SendByte (uint8_t data)
{
LPC17xx_SPI_SendRecvByte (data);
LPC17xx_SPI_SendRecvByte (data);
}
/* Recv one byte */
uint8_t LPC17xx_SPI_RecvByte ()
{
return LPC17xx_SPI_SendRecvByte (0xFF);
return LPC17xx_SPI_SendRecvByte (0xFF);
}
/* Release SSP0 */
void LPC17xx_SPI_Release (void)
{
LPC17xx_SPI_DeSelect ();
LPC17xx_SPI_RecvByte ();
LPC17xx_SPI_DeSelect ();
LPC17xx_SPI_RecvByte ();
}
@@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
#define FIFO_ELEM 8
/* Receive btr (must be multiple of 4) bytes of data and store in buff. */
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
{
uint32_t hwtr, startcnt, i, rec;
uint32_t hwtr, startcnt, i, rec;
hwtr = btr/2; /* byte number in unit of short */
if ( btr < FIFO_ELEM ) {
startcnt = hwtr;
} else {
startcnt = FIFO_ELEM;
}
hwtr = btr/2; /* byte number in unit of short */
if ( btr < FIFO_ELEM ) {
startcnt = hwtr;
} else {
startcnt = FIFO_ELEM;
}
LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */
LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */
for ( i = startcnt; i; i-- ) {
LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
for ( i = startcnt; i; i-- ) {
LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
do {
while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
// wait for data in RX FIFO (RNE set)
}
rec = LPC_SSP0->DR;
if ( i < ( hwtr - startcnt ) ) {
LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
*buff++ = (uint8_t)(rec>>8);
*buff++ = (uint8_t)(rec);
i++;
} while ( i < hwtr );
do {
while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
// wait for data in RX FIFO (RNE set)
}
rec = LPC_SSP0->DR;
if ( i < ( hwtr - startcnt ) ) {
LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
*buff++ = (uint8_t)(rec>>8);
*buff++ = (uint8_t)(rec);
i++;
} while ( i < hwtr );
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
}
/* Send 512 bytes of data block (stored in buff). */
void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff)
{
uint32_t cnt;
uint16_t data;
uint32_t cnt;
uint16_t data;
LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */
LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */
/* fill the FIFO unless it is full */
for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
{
/* wait for TX FIFO not full (TNF) */
while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
/* fill the FIFO unless it is full */
for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
{
/* wait for TX FIFO not full (TNF) */
while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
data = (*buff++) << 8;
data |= *buff++;
LPC_SSP0->DR = data;
}
data = (*buff++) << 8;
data |= *buff++;
LPC_SSP0->DR = data;
}
/* wait for BSY gone */
while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* wait for BSY gone */
while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* drain receive FIFO */
while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
data = LPC_SSP0->DR;
}
/* drain receive FIFO */
while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
data = LPC_SSP0->DR;
}
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
}
#endif /* USE_FIFO */

25
bsp/lpc176x/drivers/spi.h
View File

@@ -1,17 +1,26 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_SPI_H__
#define __LPC17XX_SPI_H__
#include <stdint.h>
#include <stdbool.h>
// if not use FIFO, R: 600kB/s, W: 500kB/s
// if use FIFO, R: 1.2MB/s, W: 800kB/s
// if not use FIFO, R: 600kB/s, W: 500kB/s
// if use FIFO, R: 1.2MB/s, W: 800kB/s
#define USE_FIFO 1
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
#define SPI_SPEED_20MHz 4 /* => 18MHz */
#define SPI_SPEED_25MHz 4 /* => 18MHz */
#define SPI_SPEED_400kHz 180 /* => 400kHz */
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
#define SPI_SPEED_20MHz 4 /* => 18MHz */
#define SPI_SPEED_25MHz 4 /* => 18MHz */
#define SPI_SPEED_400kHz 180 /* => 400kHz */
/* external functions */
void LPC17xx_SPI_Init (void);
@@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
uint8_t LPC17xx_SPI_RecvByte (void);
#if USE_FIFO
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff);
#endif
#endif // __LPC17XX_SPI_H__
#endif // __LPC17XX_SPI_H__

10
bsp/lpc176x/drivers/uart.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
struct rt_uart_lpc *uart = &uart_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = LPC_UART->IIR;
@@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
{
iir = LPC_UART->LSR; //oe pe fe oe read for clear interrupt
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
}

52
bsp/lpc176x/rtconfig.h
View File

@@ -4,17 +4,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
@@ -29,11 +29,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
@@ -67,15 +67,15 @@
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@@ -87,7 +87,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
@@ -102,16 +102,16 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
#define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_CODE_PAGE" description="specifies the OEM code page to be used on the target system" default="936">
// <item description="Japanese Shift-JIS (DBCS, OEM, Windows)">932</item>
// <item description="Simplified Chinese GBK (DBCS, OEM, Windows)">936</item>
@@ -142,7 +142,7 @@
// </integer>
#define RT_DFS_ELM_CODE_PAGE 437
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@@ -152,7 +152,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@@ -168,29 +168,29 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR "192.168.1.30"
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />

84
bsp/lpc178x/applications/application.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter)
#ifdef RT_USING_RTGUI
{
extern void rtgui_system_server_init(void);
extern void application_init(void);
extern void rtgui_system_server_init(void);
extern void application_init(void);
rt_device_t lcd;
rt_device_t lcd;
/* init lcd */
rt_hw_lcd_init();
/* init lcd */
rt_hw_lcd_init();
/* find lcd device */
lcd = rt_device_find("lcd");
if (lcd != RT_NULL)
{
/* set lcd device as rtgui graphic driver */
rtgui_graphic_set_device(lcd);
/* find lcd device */
lcd = rt_device_find("lcd");
if (lcd != RT_NULL)
{
/* set lcd device as rtgui graphic driver */
rtgui_graphic_set_device(lcd);
/* init rtgui system server */
rtgui_system_server_init();
/* init rtgui system server */
rtgui_system_server_init();
/* startup rtgui in demo of RT-Thread/GUI examples */
application_init();
}
/* startup rtgui in demo of RT-Thread/GUI examples */
application_init();
}
}
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
/* initialize finsh */
finsh_system_init();
#endif
}
@@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter)
int rt_application_init(void)
{
rt_thread_t tid;
rt_thread_t tid;
rt_thread_init(&thread_led,
"led",
rt_thread_entry_led,
RT_NULL,
&thread_led_stack[0],
sizeof(thread_led_stack),11,5);
rt_thread_startup(&thread_led);
rt_thread_init(&thread_led,
"led",
rt_thread_entry_led,
RT_NULL,
&thread_led_stack[0],
sizeof(thread_led_stack),11,5);
rt_thread_startup(&thread_led);
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;
return 0;
}
#if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH)
@@ -170,20 +170,20 @@ int rt_application_init(void)
void key(rt_uint32_t key)
{
struct rtgui_event_kbd ekbd;
struct rtgui_event_kbd ekbd;
RTGUI_EVENT_KBD_INIT(&ekbd);
ekbd.mod = RTGUI_KMOD_NONE;
ekbd.unicode = 0;
ekbd.key = key;
RTGUI_EVENT_KBD_INIT(&ekbd);
ekbd.mod = RTGUI_KMOD_NONE;
ekbd.unicode = 0;
ekbd.key = key;
ekbd.type = RTGUI_KEYDOWN;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
ekbd.type = RTGUI_KEYDOWN;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
rt_thread_delay(2);
rt_thread_delay(2);
ekbd.type = RTGUI_KEYUP;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
ekbd.type = RTGUI_KEYUP;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
}
FINSH_FUNCTION_EXPORT(key, send a key to gui server);
#endif

64
bsp/lpc178x/applications/startup.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -37,11 +37,11 @@ extern int __bss_end;
*******************************************************************************/
void assert_failed(u8* file, u32 line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
while (1) ;
}
#endif
@@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line)
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
#else
rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
#endif
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
#else
rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize application */
rt_application_init();
/* initialize application */
rt_application_init();
/* initialize timer */
rt_system_timer_init();
@@ -79,23 +79,23 @@ void rtthread_startup(void)
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
return 0;
}

2
bsp/lpc178x/drivers/board.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/lpc178x/drivers/board.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -31,7 +31,7 @@
//#define RT_USING_UART2
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </RDTConfigurator>

340
bsp/lpc178x/drivers/drv_glcd.c
View File

@@ -37,14 +37,14 @@
#define C_GLCD_LINES_PER_FRAME (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
#define C_GLCD_PIX_CLK (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME)
//LPC_LCD_TypeDef * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
//LPC_LCD_TypeDef * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
//LPC_SC_TypeDef * const g_pSC = ((LPC_SC_TypeDef*) LPC_SC_BASE);
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define SDRAM_BASE_ADDR SDRAM_BASE
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define SDRAM_BASE_ADDR SDRAM_BASE
#define LCD_VRAM_BASE_ADDR ((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
#define LCD_CURSOR_BASE_ADDR ((unsigned long)0x20088800)
#define LCD_VRAM_BASE_ADDR ((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
#define LCD_CURSOR_BASE_ADDR ((unsigned long)0x20088800)
static pFontType_t pCurrFont = NULL;
@@ -155,18 +155,18 @@ void GLCD_Move_Cursor(int x, int y)
*************************************************************************/
void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
{
unsigned long i ;
unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR;
unsigned long i ;
unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR;
pDst += cursor*64;
pDst += cursor*64;
for(i = 0; i < size ; i++)
// *pDst++ = *pCursor++;
{
*pDst = *pCursor;
pDst++;
pCursor++;
}
for(i = 0; i < size ; i++)
// *pDst++ = *pCursor++;
{
*pDst = *pCursor;
pDst++;
pCursor++;
}
}
/*************************************************************************
* Function Name: GLCD_Init
@@ -179,101 +179,101 @@ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
*************************************************************************/
void GLCD_Init (void* VRAMBase)
{
// unsigned long i;
// Assign pins
LPC_IOCON->P2_9 = 0x06; // VD3, R0
LPC_IOCON->P2_6 = 0x07; // VD4, R1
LPC_IOCON->P2_7 = 0x07; // VD5, R2
LPC_IOCON->P4_28 = 0x05; // VD6, R3
LPC_IOCON->P4_29 = 0x05; // VD7, R4
// unsigned long i;
// Assign pins
LPC_IOCON->P2_9 = 0x06; // VD3, R0
LPC_IOCON->P2_6 = 0x07; // VD4, R1
LPC_IOCON->P2_7 = 0x07; // VD5, R2
LPC_IOCON->P4_28 = 0x05; // VD6, R3
LPC_IOCON->P4_29 = 0x05; // VD7, R4
LPC_IOCON->P1_20 = 0x07; // VD10, G0
LPC_IOCON->P1_21 = 0x07; // VD11, G1
LPC_IOCON->P1_22 = 0x07; // VD12, G2
LPC_IOCON->P1_23 = 0x07; // VD13, G3
LPC_IOCON->P1_24 = 0x07; // VD14, G4
LPC_IOCON->P1_25 = 0x07; // VD15, G5
LPC_IOCON->P1_20 = 0x07; // VD10, G0
LPC_IOCON->P1_21 = 0x07; // VD11, G1
LPC_IOCON->P1_22 = 0x07; // VD12, G2
LPC_IOCON->P1_23 = 0x07; // VD13, G3
LPC_IOCON->P1_24 = 0x07; // VD14, G4
LPC_IOCON->P1_25 = 0x07; // VD15, G5
LPC_IOCON->P2_13 = 0x07; // VD19, B0
LPC_IOCON->P1_26 = 0x07; // VD20, B1
LPC_IOCON->P1_27 = 0x07; // VD21, B2
LPC_IOCON->P1_28 = 0x07; // VD22, B3
LPC_IOCON->P1_29 = 0x07; // VD23, B4
LPC_IOCON->P2_13 = 0x07; // VD19, B0
LPC_IOCON->P1_26 = 0x07; // VD20, B1
LPC_IOCON->P1_27 = 0x07; // VD21, B2
LPC_IOCON->P1_28 = 0x07; // VD22, B3
LPC_IOCON->P1_29 = 0x07; // VD23, B4
LPC_IOCON->P2_2 = 0x07; // DCLK
LPC_IOCON->P2_0 = 0x07; // DSIP(power)
LPC_IOCON->P2_5 = 0x07; // HSYNC
LPC_IOCON->P2_3 = 0x07; // VSYNC
LPC_IOCON->P2_4 = 0x07; // DataEn
LPC_IOCON->P2_2 = 0x07; // DCLK
LPC_IOCON->P2_0 = 0x07; // DSIP(power)
LPC_IOCON->P2_5 = 0x07; // HSYNC
LPC_IOCON->P2_3 = 0x07; // VSYNC
LPC_IOCON->P2_4 = 0x07; // DataEn
// LPC_IOCON->P5_4 = 0x00; // Backlight
// LPC_IOCON->P5_4 = 0x00; // Backlight
// >>> debug >>>
// >>> debug >>>
// <<< debug <<<
// <<< debug <<<
/*Back light enable*/
// LPC_GPIO5->DIR = (1<<4);
// LPC_GPIO5->SET= (5<<4);
/*Back light enable*/
// LPC_GPIO5->DIR = (1<<4);
// LPC_GPIO5->SET= (5<<4);
//Turn on LCD clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
//Turn on LCD clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
// Disable cursor
LPC_LCD->CRSR_CTRL &=~(1<<0);
// Disable cursor
LPC_LCD->CRSR_CTRL &=~(1<<0);
// disable GLCD controller
LPC_LCD->CTRL = 0;
// RGB888
LPC_LCD->CTRL &= ~(0x07 <<1);
LPC_LCD->CTRL |= (6<<1);
// disable GLCD controller
LPC_LCD->CTRL = 0;
// RGB888
LPC_LCD->CTRL &= ~(0x07 <<1);
LPC_LCD->CTRL |= (6<<1);
// TFT panel
LPC_LCD->CTRL |= (1<<5);
// single panel
LPC_LCD->CTRL &= ~(1<<7);
// notmal output
LPC_LCD->CTRL &= ~(1<<8);
// little endian byte order
LPC_LCD->CTRL &= ~(1<<9);
// little endian pix order
LPC_LCD->CTRL &= ~(1<<10);
// disable power
LPC_LCD->CTRL &= ~(1<<11);
// init pixel clock
// g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
// bypass inrenal clk divider
LPC_LCD->POL |=(1<<26);
// clock source for the LCD block is HCLK
LPC_LCD->POL &= ~(1<<5);
// LCDFP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<11);
// LCDLP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<12);
// data is driven out into the LCD on the falling edge
LPC_LCD->POL &= ~(1<<13);
// active high
LPC_LCD->POL &= ~(1<<14);
LPC_LCD->POL &= ~(0x3FF <<16);
LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
// TFT panel
LPC_LCD->CTRL |= (1<<5);
// single panel
LPC_LCD->CTRL &= ~(1<<7);
// notmal output
LPC_LCD->CTRL &= ~(1<<8);
// little endian byte order
LPC_LCD->CTRL &= ~(1<<9);
// little endian pix order
LPC_LCD->CTRL &= ~(1<<10);
// disable power
LPC_LCD->CTRL &= ~(1<<11);
// init pixel clock
// g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
// bypass inrenal clk divider
LPC_LCD->POL |=(1<<26);
// clock source for the LCD block is HCLK
LPC_LCD->POL &= ~(1<<5);
// LCDFP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<11);
// LCDLP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<12);
// data is driven out into the LCD on the falling edge
LPC_LCD->POL &= ~(1<<13);
// active high
LPC_LCD->POL &= ~(1<<14);
LPC_LCD->POL &= ~(0x3FF <<16);
LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
// init Horizontal Timing
LPC_LCD->TIMH = 0; //reset TIMH before set value
LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
// init Horizontal Timing
LPC_LCD->TIMH = 0; //reset TIMH before set value
LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
// init Vertical Timing
LPC_LCD->TIMV = 0; //reset TIMV value before setting
LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
// Frame Base Address doubleword aligned
LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ;
LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ;
// init Vertical Timing
LPC_LCD->TIMV = 0; //reset TIMV value before setting
LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
// Frame Base Address doubleword aligned
LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ;
LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ;
}
/*************************************************************************
@@ -287,13 +287,13 @@ void GLCD_Init (void* VRAMBase)
*************************************************************************/
void GLCD_SetPallet (const unsigned long * pPallete)
{
unsigned long i;
unsigned long * pDst = (unsigned long *)LPC_LCD->PAL;
// //assert(pPallete);
for (i = 0; i < 128; i++)
{
*pDst++ = *pPallete++;
}
unsigned long i;
unsigned long * pDst = (unsigned long *)LPC_LCD->PAL;
// //assert(pPallete);
for (i = 0; i < 128; i++)
{
*pDst++ = *pPallete++;
}
}
/*************************************************************************
@@ -307,7 +307,7 @@ void GLCD_SetPallet (const unsigned long * pPallete)
*************************************************************************/
void GLCD_Ctrl (Bool bEna)
{
volatile unsigned long i;
volatile unsigned long i;
if (bEna)
{
// LCD_CTRL_bit.LcdEn = 1;
@@ -473,7 +473,7 @@ Bool GLCD_TextCalcWindow (unsigned long * pXL, unsigned long * pXR,
*pXR = XL_Win + ((TextX_Pos+1)*pCurrFont->H_Size) - 1;
if(*pXR > XR_Win)
{
*pH_Size -= *pXR - XR_Win;
*pH_Size -= *pXR - XR_Win;
*pXR = XR_Win;
}
@@ -514,19 +514,19 @@ unsigned long i, j, k;
++TextY_Pos;
break;
case '\r': // go to begin of this line (Carriage Return)
// clear from current position to end of line
while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
// clear from current position to end of line
while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
LCD_SET_WINDOW(xl,xr,yu,yd);
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
TextX_Pos = 0;
break;
case '\b': // go back one position (BackSpace)
@@ -534,45 +534,45 @@ unsigned long i, j, k;
{
--TextX_Pos;
// del current position
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
LCD_SET_WINDOW(xl,xr,yu,yd);
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
}
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
}
}
break;
case '\t': // go to next Horizontal Tab stop
WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize);
for(k = 0; k < WhiteSpaceNumb; ++k)
{
WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize);
for(k = 0; k < WhiteSpaceNumb; ++k)
{
LCD_SET_WINDOW(xl,xr,yu,yd);
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
else
{
break;
}
}
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
else
{
break;
}
}
break;
case '\f': // go to top of page (Form Feed)
// clear entire window
H_Size = XR_Win - XL_Win;
V_Size = YD_Win - YU_Win;
// clear entire window
H_Size = XR_Win - XL_Win;
V_Size = YD_Win - YU_Win;
// set character window X left, Y right
LCD_SET_WINDOW(XL_Win,XR_Win,YU_Win,YD_Win);
// Fill window with background font color
@@ -584,7 +584,7 @@ unsigned long i, j, k;
}
}
TextX_Pos = TextY_Pos = 0;
TextX_Pos = TextY_Pos = 0;
break;
case '\a': // signal an alert (BELl)
TEXT_BEL1_FUNC();
@@ -593,37 +593,37 @@ unsigned long i, j, k;
// Calculate the current character base address from stream
// and the character position
if((c < pCurrFont->CharacterOffset) &&
(c >= pCurrFont->CharactersNuber))
{
c = 0;
(c >= pCurrFont->CharactersNuber))
{
c = 0;
}
else
{
c -= pCurrFont->CharacterOffset;
c -= pCurrFont->CharacterOffset;
}
pSrc = pCurrFont->pFontStream + (H_Line * pCurrFont->V_Size * c);
// Calculate character window and fit it in the text window
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
// set character window X left, Y right
LCD_SET_WINDOW(xl,xr,yu,yd);
// Send char data
for(i = 0; i < V_Size; ++i)
{
// set character window X left, Y right
LCD_SET_WINDOW(xl,xr,yu,yd);
// Send char data
for(i = 0; i < V_Size; ++i)
{
SrcInc = H_Line;
for(j = 0; j < H_Size; ++j)
{
Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour;
LCD_WRITE_PIXEL(Temp);
if((j&0x7) == 7)
{
++pSrc;
{
Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour;
LCD_WRITE_PIXEL(Temp);
if((j&0x7) == 7)
{
++pSrc;
--SrcInc;
}
}
}
}
// next line of character
pSrc += SrcInc;
}
pSrc += SrcInc;
}
}
++TextX_Pos;
}

12
bsp/lpc178x/drivers/drv_glcd.h
View File

@@ -33,7 +33,7 @@ typedef unsigned long Boolean;
/**
* @brief A struct for Bitmap on LCD screen
*/
typedef struct _Bmp_t
typedef struct _Bmp_t
{
U32 H_Size;
U32 V_Size;
@@ -47,8 +47,8 @@ typedef struct _Bmp_t
/**
* @brief A struct for Font Type on LCD screen
*/
typedef struct _FontType_t
typedef struct _FontType_t
{
U32 H_Size;
U32 V_Size;
@@ -62,9 +62,9 @@ typedef U32 LdcPixel_t, *pLdcPixel_t;
#define C_GLCD_REFRESH_FREQ (60HZ)
#define C_GLCD_H_SIZE 480
#define C_GLCD_H_PULSE 2 //
#define C_GLCD_H_FRONT_PORCH 5 //
#define C_GLCD_H_BACK_PORCH 40 //
#define C_GLCD_H_PULSE 2 //
#define C_GLCD_H_FRONT_PORCH 5 //
#define C_GLCD_H_BACK_PORCH 40 //
#define C_GLCD_V_SIZE 272
#define C_GLCD_V_PULSE 2
#define C_GLCD_V_FRONT_PORCH 8

712
bsp/lpc178x/drivers/emac.c
View File

File diff suppressed because it is too large Load Diff

11
bsp/lpc178x/drivers/emac.h
View File

@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
@@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE 0x20000000
#define RX_DESC_BASE 0x20000000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)

376
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
View File

@@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_clkpwr.c 2011-06-02
* $Id$ lpc177x_8x_clkpwr.c 2011-06-02
*//**
* @file lpc177x_8x_clkpwr.c
* @brief Contains all functions support for Clock and Power Control
* firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_clkpwr.c
* @brief Contains all functions support for Clock and Power Control
* firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@@ -41,253 +41,253 @@ uint32_t SPIFIFrequency = 0;
*/
/*********************************************************************//**
* @brief Set value of each Peripheral Clock Selection
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @param[in] DivVal Value of divider. This value should be set as follows:
* - CPU clock: DivVal must be in range: 0..31
* - Peripheral clock: DivVal must be in range: 0..31
* - EMC clock: DivVal must be:
* + 0: The EMC uses the same clock as the CPU
* + 1: The EMC uses a clock at half the rate of the CPU
* - USB clock: DivVal must be:
* + 0: the divider is turned off, no clock will
* be provided to the USB subsystem
* + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
* + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
* @brief Set value of each Peripheral Clock Selection
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @param[in] DivVal Value of divider. This value should be set as follows:
* - CPU clock: DivVal must be in range: 0..31
* - Peripheral clock: DivVal must be in range: 0..31
* - EMC clock: DivVal must be:
* + 0: The EMC uses the same clock as the CPU
* + 1: The EMC uses a clock at half the rate of the CPU
* - USB clock: DivVal must be:
* + 0: the divider is turned off, no clock will
* be provided to the USB subsystem
* + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
* + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
* @return none
* Note: Pls assign right DivVal, this function will not check if it is illegal.
**********************************************************************/
void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
{
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
LPC_SC->CCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_PER:
LPC_SC->PCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_EMC:
LPC_SC->EMCCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_USB:
LPC_SC->USBCLKSEL &= ~(0x0000001F);
LPC_SC->USBCLKSEL |= DivVal;
break;
default:
while(1);//Error Loop;
}
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
LPC_SC->CCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_PER:
LPC_SC->PCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_EMC:
LPC_SC->EMCCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_USB:
LPC_SC->USBCLKSEL &= ~(0x0000001F);
LPC_SC->USBCLKSEL |= DivVal;
break;
default:
while(1);//Error Loop;
}
}
/*********************************************************************//**
* @brief Get current clock value
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @brief Get current clock value
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
**********************************************************************/
uint32_t CLKPWR_GetCLK (uint8_t ClkType)
{
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
return SystemCoreClock;
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
return SystemCoreClock;
case CLKPWR_CLKTYPE_PER:
return PeripheralClock;
case CLKPWR_CLKTYPE_PER:
return PeripheralClock;
case CLKPWR_CLKTYPE_EMC:
return EMCClock;
case CLKPWR_CLKTYPE_EMC:
return EMCClock;
case CLKPWR_CLKTYPE_USB:
return USBClock;
case CLKPWR_CLKTYPE_USB:
return USBClock;
default:
while(1);//error loop
}
default:
while(1);//error loop
}
}
/*********************************************************************//**
* @brief Configure power supply for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_PCONP_PCLCD : LCD
* - CLKPWR_PCONP_PCTIM0 : Timer 0
- CLKPWR_PCONP_PCTIM1 : Timer 1
- CLKPWR_PCONP_PCUART0 : UART 0
- CLKPWR_PCONP_PCUART1 : UART 1
- CLKPWR_PCONP_PCPWM0 : PWM 0
- CLKPWR_PCONP_PCPWM1 : PWM 1
- CLKPWR_PCONP_PCI2C0 : I2C 0
- CLKPWR_PCONP_PCUART4 : UART4
- CLKPWR_PCONP_PCRTC : RTC
- CLKPWR_PCONP_PCSSP1 : SSP 1
- CLKPWR_PCONP_PCEMC : EMC
- CLKPWR_PCONP_PCADC : ADC
- CLKPWR_PCONP_PCAN1 : CAN 1
- CLKPWR_PCONP_PCAN2 : CAN 2
- CLKPWR_PCONP_PCGPIO : GPIO
- CLKPWR_PCONP_PCMC : MCPWM
- CLKPWR_PCONP_PCQEI : QEI
- CLKPWR_PCONP_PCI2C1 : I2C 1
- CLKPWR_PCONP_PCSSP2 : SSP 2
- CLKPWR_PCONP_PCSSP0 : SSP 0
- CLKPWR_PCONP_PCTIM2 : Timer 2
- CLKPWR_PCONP_PCTIM3 : Timer 3
- CLKPWR_PCONP_PCUART2 : UART 2
- CLKPWR_PCONP_PCUART3 : UART 3
- CLKPWR_PCONP_PCI2C2 : I2C 2
- CLKPWR_PCONP_PCI2S : I2S
- CLKPWR_PCONP_PCSDC : SDC
- CLKPWR_PCONP_PCGPDMA : GPDMA
- CLKPWR_PCONP_PCENET : Ethernet
- CLKPWR_PCONP_PCUSB : USB
* @brief Configure power supply for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_PCONP_PCLCD : LCD
* - CLKPWR_PCONP_PCTIM0 : Timer 0
- CLKPWR_PCONP_PCTIM1 : Timer 1
- CLKPWR_PCONP_PCUART0 : UART 0
- CLKPWR_PCONP_PCUART1 : UART 1
- CLKPWR_PCONP_PCPWM0 : PWM 0
- CLKPWR_PCONP_PCPWM1 : PWM 1
- CLKPWR_PCONP_PCI2C0 : I2C 0
- CLKPWR_PCONP_PCUART4 : UART4
- CLKPWR_PCONP_PCRTC : RTC
- CLKPWR_PCONP_PCSSP1 : SSP 1
- CLKPWR_PCONP_PCEMC : EMC
- CLKPWR_PCONP_PCADC : ADC
- CLKPWR_PCONP_PCAN1 : CAN 1
- CLKPWR_PCONP_PCAN2 : CAN 2
- CLKPWR_PCONP_PCGPIO : GPIO
- CLKPWR_PCONP_PCMC : MCPWM
- CLKPWR_PCONP_PCQEI : QEI
- CLKPWR_PCONP_PCI2C1 : I2C 1
- CLKPWR_PCONP_PCSSP2 : SSP 2
- CLKPWR_PCONP_PCSSP0 : SSP 0
- CLKPWR_PCONP_PCTIM2 : Timer 2
- CLKPWR_PCONP_PCTIM3 : Timer 3
- CLKPWR_PCONP_PCUART2 : UART 2
- CLKPWR_PCONP_PCUART3 : UART 3
- CLKPWR_PCONP_PCI2C2 : I2C 2
- CLKPWR_PCONP_PCI2S : I2S
- CLKPWR_PCONP_PCSDC : SDC
- CLKPWR_PCONP_PCGPDMA : GPDMA
- CLKPWR_PCONP_PCENET : Ethernet
- CLKPWR_PCONP_PCUSB : USB
*
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
*
* @return none
**********************************************************************/
void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
{
if (NewState == ENABLE)
{
LPC_SC->PCONP |= PPType;
}
else if (NewState == DISABLE)
{
LPC_SC->PCONP &= ~PPType;
}
if (NewState == ENABLE)
{
LPC_SC->PCONP |= PPType;
}
else if (NewState == DISABLE)
{
LPC_SC->PCONP &= ~PPType;
}
}
#if 0
// nxp21346
/*********************************************************************//**
* @brief Configure hardware reset for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_RSTCON0_LCD : LCD
* - CLKPWR_RSTCON0_TIM0 : Timer 0
- CLKPWR_RSTCON0_TIM1 : Timer 1
- CLKPWR_RSTCON0_UART0 : UART 0
- CLKPWR_RSTCON0_UART1 : UART 1
- CLKPWR_RSTCON0_PWM0 : PWM 0
- CLKPWR_RSTCON0_PWM1 : PWM 1
- CLKPWR_RSTCON0_I2C0 : I2C 0
- CLKPWR_RSTCON0_UART4 : UART 4
- CLKPWR_RSTCON0_RTC : RTC
- CLKPWR_RSTCON0_SSP1 : SSP 1
- CLKPWR_RSTCON0_EMC : EMC
- CLKPWR_RSTCON0_ADC : ADC
- CLKPWR_RSTCON0_CAN1 : CAN 1
- CLKPWR_RSTCON0_CAN2 : CAN 2
- CLKPWR_RSTCON0_GPIO : GPIO
- CLKPWR_RSTCON0_MCPWM : MCPWM
- CLKPWR_RSTCON0_QEI : QEI
- CLKPWR_RSTCON0_I2C1 : I2C 1
- CLKPWR_RSTCON0_SSP2 : SSP 2
- CLKPWR_RSTCON0_SSP0 : SSP 0
- CLKPWR_RSTCON0_TIM2 : Timer 2
- CLKPWR_RSTCON0_TIM3 : Timer 3
- CLKPWR_RSTCON0_UART2 : UART 2
- CLKPWR_RSTCON0_UART3 : UART 3
- CLKPWR_RSTCON0_I2C2 : I2C 2
- CLKPWR_RSTCON0_I2S : I2S
- CLKPWR_RSTCON0_SDC : SDC
- CLKPWR_RSTCON0_GPDMA : GPDMA
- CLKPWR_RSTCON0_ENET : Ethernet
- CLKPWR_RSTCON0_USB : USB
* @brief Configure hardware reset for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_RSTCON0_LCD : LCD
* - CLKPWR_RSTCON0_TIM0 : Timer 0
- CLKPWR_RSTCON0_TIM1 : Timer 1
- CLKPWR_RSTCON0_UART0 : UART 0
- CLKPWR_RSTCON0_UART1 : UART 1
- CLKPWR_RSTCON0_PWM0 : PWM 0
- CLKPWR_RSTCON0_PWM1 : PWM 1
- CLKPWR_RSTCON0_I2C0 : I2C 0
- CLKPWR_RSTCON0_UART4 : UART 4
- CLKPWR_RSTCON0_RTC : RTC
- CLKPWR_RSTCON0_SSP1 : SSP 1
- CLKPWR_RSTCON0_EMC : EMC
- CLKPWR_RSTCON0_ADC : ADC
- CLKPWR_RSTCON0_CAN1 : CAN 1
- CLKPWR_RSTCON0_CAN2 : CAN 2
- CLKPWR_RSTCON0_GPIO : GPIO
- CLKPWR_RSTCON0_MCPWM : MCPWM
- CLKPWR_RSTCON0_QEI : QEI
- CLKPWR_RSTCON0_I2C1 : I2C 1
- CLKPWR_RSTCON0_SSP2 : SSP 2
- CLKPWR_RSTCON0_SSP0 : SSP 0
- CLKPWR_RSTCON0_TIM2 : Timer 2
- CLKPWR_RSTCON0_TIM3 : Timer 3
- CLKPWR_RSTCON0_UART2 : UART 2
- CLKPWR_RSTCON0_UART3 : UART 3
- CLKPWR_RSTCON0_I2C2 : I2C 2
- CLKPWR_RSTCON0_I2S : I2S
- CLKPWR_RSTCON0_SDC : SDC
- CLKPWR_RSTCON0_GPDMA : GPDMA
- CLKPWR_RSTCON0_ENET : Ethernet
- CLKPWR_RSTCON0_USB : USB
*
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
*
* @return none
**********************************************************************/
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
{
if(PType < 32)
{
if(NewState == ENABLE)
LPC_SC->RSTCON0 |=(1<<PType);
else
LPC_SC->RSTCON0 &=~(1<<PType);
}
else
{
if(NewState == ENABLE)
LPC_SC->RSTCON1 |= (1<<(PType - 31));
else
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
}
if(PType < 32)
{
if(NewState == ENABLE)
LPC_SC->RSTCON0 |=(1<<PType);
else
LPC_SC->RSTCON0 &=~(1<<PType);
}
else
{
if(NewState == ENABLE)
LPC_SC->RSTCON1 |= (1<<(PType - 31));
else
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
}
}
// nxp21346
#endif
/*********************************************************************//**
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_Sleep(void)
{
LPC_SC->PCON = 0x00;
/* Sleep Mode*/
__WFI();
LPC_SC->PCON = 0x00;
/* Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_DeepSleep(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x8;
/* Deep Sleep Mode*/
__WFI();
SCB->SCR = 0x4;
LPC_SC->PCON = 0x8;
/* Deep Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_PowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x09;
/* Power Down Mode*/
__WFI();
SCB->SCR = 0x4;
LPC_SC->PCON = 0x09;
/* Power Down Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_DeepPowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x03;
/* Deep Power Down Mode*/
__WFI();
SCB->SCR = 0x4;
LPC_SC->PCON = 0x03;
/* Deep Power Down Mode*/
__WFI();
}
/**

172
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
View File

@@ -1,14 +1,14 @@
/**********************************************************************
* $Id$ lpc177x_8x_clkpwr.h 2011-06-02
* $Id$ lpc177x_8x_clkpwr.h 2011-06-02
*//**
* @file lpc177x_8x_clkpwr.h
* @brief Contains all macro definitions and function prototypes
* support for Clock and Power Control firmware library on
* LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_clkpwr.h
* @brief Contains all macro definitions and function prototypes
* support for Clock and Power Control firmware library on
* LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@@ -26,7 +26,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CLKPWR Clock Power
/** @defgroup CLKPWR Clock Power
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@@ -52,163 +52,163 @@ extern "C"
/********************************************************************
* Clock Source Selection Definitions
**********************************************************************/
#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1))
#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1))
/********************************************************************
* Clock type/domain Definitions (calculated from input and pre-configuration
* parameter(s)
**********************************************************************/
#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0))
#define CLKPWR_CLKTYPE_PER ((uint32_t)(1))
#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2))
#define CLKPWR_CLKTYPE_USB ((uint32_t)(3))
#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0))
#define CLKPWR_CLKTYPE_PER ((uint32_t)(1))
#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2))
#define CLKPWR_CLKTYPE_USB ((uint32_t)(3))
/********************************************************************
* Power Control for Peripherals Definitions
**********************************************************************/
/** LCD controller power/clock control bit */
#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0))
#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0))
/** Timer/Counter 0 power/clock control bit */
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
/* Timer/Counter 1 power/clock control bit */
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
/** UART0 power/clock control bit */
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
/** UART1 power/clock control bit */
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
/** PWM0 power/clock control bit */
#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5))
#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5))
/** PWM1 power/clock control bit */
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
/** The I2C0 interface power/clock control bit */
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
/** UART4 power/clock control bit */
#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8))
#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8))
/** The RTC power/clock control bit */
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
/** The SSP1 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
/** External Memory controller power/clock control bit */
#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11))
#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11))
/** A/D converter 0 (ADC0) power/clock control bit */
#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12))
#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12))
/** CAN Controller 1 power/clock control bit */
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
/** CAN Controller 2 power/clock control bit */
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
/** GPIO power/clock control bit */
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
/** Motor Control PWM */
#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17))
#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17))
/** Quadrature Encoder Interface power/clock control bit */
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
/** The I2C1 interface power/clock control bit */
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
/** The SSP2 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20))
#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20))
/** The SSP0 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
/** Timer 2 power/clock control bit */
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
/** Timer 3 power/clock control bit */
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
/** UART 2 power/clock control bit */
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
/** UART 3 power/clock control bit */
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
/** I2C interface 2 power/clock control bit */
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
/** I2S interface power/clock control bit*/
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
/** SD card interface power/clock control bit */
#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28))
#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28))
/** GP DMA function power/clock control bit*/
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
/** Ethernet block power/clock control bit*/
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
/** USB interface power/clock control bit*/
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
/********************************************************************
* Power Control for Peripherals Definitions
**********************************************************************/
#define CLKPWR_RSTCON0_LCD ((uint32_t)(0))
#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2))
#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3))
#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4))
#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6))
#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7))
#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8))
#define CLKPWR_RSTCON0_RTC ((uint32_t)(9))
#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10))
#define CLKPWR_RSTCON0_EMC ((uint32_t)(11))
#define CLKPWR_RSTCON0_ADC ((uint32_t)(12))
#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14))
#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15))
#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17))
#define CLKPWR_RSTCON0_QEI ((uint32_t)(18))
#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19))
#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21))
#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23))
#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24))
#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25))
#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26))
#define CLKPWR_RSTCON0_I2S ((uint32_t)(27))
#define CLKPWR_RSTCON0_SDC ((uint32_t)(28))
#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29))
#define CLKPWR_RSTCON0_ENET ((uint32_t)(30))
#define CLKPWR_RSTCON0_USB ((uint32_t)(31))
#define CLKPWR_RSTCON0_LCD ((uint32_t)(0))
#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2))
#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3))
#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4))
#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6))
#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7))
#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8))
#define CLKPWR_RSTCON0_RTC ((uint32_t)(9))
#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10))
#define CLKPWR_RSTCON0_EMC ((uint32_t)(11))
#define CLKPWR_RSTCON0_ADC ((uint32_t)(12))
#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14))
#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15))
#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17))
#define CLKPWR_RSTCON0_QEI ((uint32_t)(18))
#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19))
#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21))
#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23))
#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24))
#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25))
#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26))
#define CLKPWR_RSTCON0_I2S ((uint32_t)(27))
#define CLKPWR_RSTCON0_SDC ((uint32_t)(28))
#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29))
#define CLKPWR_RSTCON0_ENET ((uint32_t)(30))
#define CLKPWR_RSTCON0_USB ((uint32_t)(31))
#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32))
#define CLKPWR_RSTCON1_DAC ((uint32_t)(33))
#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34))
#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32))
#define CLKPWR_RSTCON1_DAC ((uint32_t)(33))
#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34))
/**
* @}
*/
/* External clock variable from system_LPC177x_8x.h */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock Frequency */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock Frequency */
/* External clock variable from lpc177x_8x_clkpwr.h */
extern uint32_t USBClock; /*!< USB Frequency */
extern uint32_t USBClock; /*!< USB Frequency */
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions

496
bsp/lpc178x/drivers/lpc177x_8x_emc.c
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bsp/lpc178x/drivers/lpc177x_8x_emc.h
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@@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_emc.h 2011-06-02
* $Id$ lpc177x_8x_emc.h 2011-06-02
*//**
* @file lpc177x_8x_emc.h
* @brief Contains all macro definitions and function prototypes
* support for EMC firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_emc.h
* @brief Contains all macro definitions and function prototypes
* support for EMC firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@@ -25,7 +25,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EMC EMC (External Memory Controller)
/** @defgroup EMC EMC (External Memory Controller)
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@@ -45,233 +45,233 @@
* EMC Control Register (EMCControl)
**********************************************************************/
/* Control register mask */
#define EMC_Control_MASK ((uint32_t )0x07)
#define EMC_Control_MASK ((uint32_t )0x07)
/* Control register EMC: Enable control. */
#define EMC_Control_E ((uint32_t )(1<<0))
#define EMC_Control_E ((uint32_t )(1<<0))
/* Control register EMC: Address mirror control. */
#define EMC_Control_M ((uint32_t )(1<<1))
#define EMC_Control_M ((uint32_t )(1<<1))
/* Control register EMC: Low-power mode control. */
#define EMC_Control_L ((uint32_t )(1<<2))
#define EMC_Control_L ((uint32_t )(1<<2))
/***********************************************************************
* EMC Status Register (EMCStatus)
**********************************************************************/
/* Status register mask */
#define EMC_Status_MASK ((uint32_t )0x07)
#define EMC_Status_MASK ((uint32_t )0x07)
/* Status register EMC: Busy. */
#define EMC_Status_B ((uint32_t )(1<<0))
#define EMC_Status_B ((uint32_t )(1<<0))
/* Status register EMC: Write buffer status. */
#define EMC_Status_S ((uint32_t )(1<<1))
#define EMC_Status_S ((uint32_t )(1<<1))
/* Status register EMC: Self-refresh acknowledge.. */
#define EMC_Status_SA ((uint32_t )(1<<2))
#define EMC_Status_SA ((uint32_t )(1<<2))
/***********************************************************************
* EMC Configuration register (EMCConfig)
**********************************************************************/
/* EMC Configuration register : Enable control. */
#define EMC_Config_Endian_Mode ((uint32_t )(1<<0))
#define EMC_Config_Endian_Mode ((uint32_t )(1<<0))
/* EMC Configuration register: CCLK. */
#define EMC_Config_CCLK ((uinr32_t)(1<<8))
#define EMC_Config_CCLK ((uinr32_t)(1<<8))
/* EMC Configuration register mask */
#define EMC_Config_MASK ((uint32_t)(0x101))
#define EMC_Config_MASK ((uint32_t)(0x101))
/***********************************************************************
* Dynamic Memory Control register (EMCDynamicControl)
**********************************************************************/
/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
#define EMC_DynamicControl_CE ((uint32_t )(1<<0))
#define EMC_DynamicControl_CE ((uint32_t )(1<<0))
/* Dynamic Memory Control register EMC: Dynamic memory clock control */
#define EMC_DynamicControl_CS ((uint32_t )(1<<1))
#define EMC_DynamicControl_CS ((uint32_t )(1<<1))
/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
#define EMC_DynamicControl_SR ((uint32_t )(1<<2))
#define EMC_DynamicControl_SR ((uint32_t )(1<<2))
/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
#define EMC_DynamicControl_MMC ((uint32_t )(1<<5))
#define EMC_DynamicControl_MMC ((uint32_t )(1<<5))
/* Dynamic Memory Control register EMC: SDRAM initialization*/
#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7))
#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7))
/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
#define EMC_DynamicControl_DP ((uint32_t ) (1<<13))
#define EMC_DynamicControl_DP ((uint32_t ) (1<<13))
/***********************************************************************
* Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
**********************************************************************/
/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
/***********************************************************************
* Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
**********************************************************************/
/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
/***********************************************************************
* Dynamic Memory Percentage Command Period register (EMCDynamictRP)
**********************************************************************/
/* EMCDynamictRP register EMC: Precharge command period (tRP). */
#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
**********************************************************************/
/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
**********************************************************************/
/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
**********************************************************************/
/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Write Recovery Time register (EMCDynamictWR)
**********************************************************************/
/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
/***********************************************************************
* Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
**********************************************************************/
/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
/***********************************************************************
* Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
**********************************************************************/
/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
**********************************************************************/
/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
**********************************************************************/
/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
**********************************************************************/
/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Extended Wait Register (EMCStaticExtendedWait)
**********************************************************************/
/* StaticExtendedWait register EMC: External wait time out. */
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
/***********************************************************************
* Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
**********************************************************************/
/* DynamicConfig register EMC: Memory device (MD). */
#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3))
#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3))
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7))
#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7))
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14))
#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14))
/* DynamicConfig register EMC: Buffer enable */
#define EMC_DynamicConfig_B ((uint32_t )(1 << 19))
#define EMC_DynamicConfig_B ((uint32_t )(1 << 19))
/* DynamicConfig register EMC: Write protect (P) */
#define EMC_DynamicConfig_P ((uint32_t )(1 << 20))
#define EMC_DynamicConfig_P ((uint32_t )(1 << 20))
/***********************************************************************
* Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
**********************************************************************/
/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03))
#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03))
/* DynamicRASCAS register EMC: CAS latency (CAS)*/
#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8))
#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8))
/***********************************************************************
* Static Memory Configuration registers (EMCStaticConfig0-3)
**********************************************************************/
/* StaticConfig register EMC: Memory width (MW). */
#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03))
#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03))
/* StaticConfig register EMC: Memory width 8bit . */
#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0))
#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0))
/* StaticConfig register EMC: Memory width 16bit . */
#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1))
#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1))
/* StaticConfig register EMC: Memory width 32bit . */
#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2))
#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2))
/* StaticConfig register EMC: Page mode (PM) */
#define EMC_StaticConfig_PM ((uint32_t )(1 << 3))
#define EMC_StaticConfig_PM ((uint32_t )(1 << 3))
/* StaticConfig register EMC: Chip select polarity (PC) */
#define EMC_StaticConfig_PC ((uint32_t )(1 << 6))
#define EMC_StaticConfig_PC ((uint32_t )(1 << 6))
/* StaticConfig register EMC: Byte lane state (PB) */
#define EMC_StaticConfig_PB ((uint32_t )(1 << 7))
#define EMC_StaticConfig_PB ((uint32_t )(1 << 7))
/* StaticConfig register EMC: Extended wait (EW) */
#define EMC_StaticConfig_EW ((uint32_t )(1 << 8))
#define EMC_StaticConfig_EW ((uint32_t )(1 << 8))
/* StaticConfig register EMC: Buffer enable (B) */
#define EMC_StaticConfig_B ((uint32_t )(1 << 19))
#define EMC_StaticConfig_B ((uint32_t )(1 << 19))
/* StaticConfig register EMC: Write protect (P) */
#define EMC_StaticConfig_P ((uint32_t )(1 << 20))
#define EMC_StaticConfig_P ((uint32_t )(1 << 20))
/***********************************************************************
* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
**********************************************************************/
/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
**********************************************************************/
/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Static Memory Read Delay registers (EMCStaticWaitRd0-3)
**********************************************************************/
/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
read first access wait state (WAITRD) */
#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
**********************************************************************/
/* StaticwaitPage register EMC: Asynchronous page mode read after the first
read wait states (WAITPAGE). */
#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Write Delay registers (EMCStaticWaitwr0-3)
**********************************************************************/
/* StaticWaitwr register EMC: Write wait states (WAITWR). */
#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
**********************************************************************/
/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Delay Control register (EMCDLYCTL)
**********************************************************************/
#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
/***********************************************************************
* EMC Calibration register (EMCCAL)
**********************************************************************/
#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
#define EMC_CAL_START ((uint32_t)(1<<14))
#define EMC_CAL_DONE ((uint32_t)(1<<15))
#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
#define EMC_CAL_START ((uint32_t)(1<<14))
#define EMC_CAL_DONE ((uint32_t)(1<<15))
#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0))
#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1))
#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0))
#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1))
/**
* @}

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bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
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bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
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/**********************************************************************
* $Id$ lpc177x_8x_pinsel.h 2011-06-02
* $Id$ lpc177x_8x_pinsel.h 2011-06-02
*//**
* @file lpc177x_8x_pinsel.h
* @brief Contains all macro definitions and function prototypes
* support for Pin-connection block firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_pinsel.h
* @brief Contains all macro definitions and function prototypes
* support for Pin-connection block firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@@ -25,7 +25,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup PINSEL Pin Selection
/** @defgroup PINSEL Pin Selection
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@@ -44,160 +44,160 @@
*/
/* Macros define IOCON bits */
#define IOCON_MODE_PLAIN ((0<<3))
#define IOCON_MODE_PULLDOWN ((1<<3))
#define IOCON_MODE_PULLUP ((2<<3))
#define IOCON_MODE_REPEATER ((3<<3))
#define IOCON_HYS ((1<<5))
#define IOCON_SLEW ((1<<6))
#define IOCON_INBUF ((1<<7))
#define IOCON_I2CMODE_FAST ((0<<8))
#define IOCON_I2CMODE_OPENDRAIN ((1<<8))
#define IOCON_I2CMODE_FASTPLUS ((2<<8))
#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8))
#define IOCON_ODMODE ((1<<10))
#define IOCON_MODE_PLAIN ((0<<3))
#define IOCON_MODE_PULLDOWN ((1<<3))
#define IOCON_MODE_PULLUP ((2<<3))
#define IOCON_MODE_REPEATER ((3<<3))
#define IOCON_HYS ((1<<5))
#define IOCON_SLEW ((1<<6))
#define IOCON_INBUF ((1<<7))
#define IOCON_I2CMODE_FAST ((0<<8))
#define IOCON_I2CMODE_OPENDRAIN ((1<<8))
#define IOCON_I2CMODE_FASTPLUS ((2<<8))
#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8))
#define IOCON_ODMODE ((1<<10))
/* Macros define for LOC registers */
#define LOC_CAN_RD_1_P0_0 ((0)) /**< Input for CAN_RD_1 comes from P0.0 */
#define LOC_CAN_RD_1_P0_21 ((1)) /**< Input for CAN_RD_1 comes from P0.21 */
#define LOC_CAN_RD_2_P2_7 ((0)) /**< Input for CAN_RD_2 comes from P2.7 */
#define LOC_CAN_RD_2_P0_4 ((1)) /**< Input for CAN_RD_2 comes from P0.4 */
#define LOC_ENET_MDIO_P2_9 ((0)) /**< Input for ENET_MDIO comes from P2.9 */
#define LOC_ENET_MDIO_P1_17 ((1)) /**< Input for ENET_MDIO comes from P1.17 */
#define LOC_EINT_0_P0_29 ((0)) /**< Input for EINT_0 comes from P0.29 */
#define LOC_EINT_0_P2_10 ((1)) /**< Input for EINT_0 comes from P2.10 */
#define LOC_EINT_1_P0_30 ((0)) /**< Input for EINT_1 comes from P0.30 */
#define LOC_EINT_1_P2_11 ((1)) /**< Input for EINT_1 comes from P2.11 */
#define LOC_I2C0_SCL_P1_31 ((0)) /**< Input for I2C0_SCL comes from P1.31 */
#define LOC_I2C0_SCL_P0_28 ((1)) /**< Input for I2C0_SCL comes from P0.28 */
#define LOC_I2C0_SCL_P5_3 ((2)) /**< Input for I2C0_SCL comes from P5.3 */
#define LOC_I2C0_SDA_P1_30 ((0)) /**< Input for I2C0_SDA comes from P1.30 */
#define LOC_I2C0_SDA_P0_27 ((1)) /**< Input for I2C0_SDA comes from P0.27 */
#define LOC_I2C0_SDA_P5_2 ((2)) /**< Input for I2C0_SDA comes from P5.2 */
#define LOC_I2C1_SCL_P0_1 ((0)) /**< Input for I2C1_SCL comes from P0.1 */
#define LOC_I2C1_SCL_P2_15 ((1)) /**< Input for I2C1_SCL comes from P2.15 */
#define LOC_I2C1_SCL_P0_20 ((2)) /**< Input for I2C1_SCL comes from P0.20 */
#define LOC_I2C1_SDA_P2_14 ((0)) /**< Input for I2C1_SDA comes from P2.14 */
#define LOC_I2C1_SDA_P0_0 ((1)) /**< Input for I2C1_SDA comes from P0.0 */
#define LOC_I2C1_SDA_P0_19 ((2)) /**< Input for I2C1_SDA comes from P0.19 */
#define LOC_I2C2_SCL_P2_31 ((0)) /**< Input for I2C2_SCL comes from P2.31 */
#define LOC_I2C2_SCL_P0_11 ((1)) /**< Input for I2C2_SCL comes from P0.11 */
#define LOC_I2C2_SCL_P4_21 ((2)) /**< Input for I2C2_SCL comes from P4.21 */
#define LOC_I2C2_SCL_P4_29 ((3)) /**< Input for I2C2_SCL comes from P4.29 */
#define LOC_I2C2_SDA_P2_30 ((0)) /**< Input for I2C2_SDA comes from P2.30 */
#define LOC_I2C2_SDA_P0_10 ((1)) /**< Input for I2C2_SDA comes from P0.10 */
#define LOC_I2C2_SDA_P4_20 ((2)) /**< Input for I2C2_SDA comes from P4.20 */
#define LOC_I2C2_SDA_P1_15 ((3)) /**< Input for I2C2_SDA comes from P1.15 */
#define LOC_I2S_RX_SCK_P0_23 ((0)) /**< Input for I2S_RX_SCK comes from P0.23 */
#define LOC_I2S_RX_SCK_P0_4 ((1)) /**< Input for I2S_RX_SCK comes from P0.4 */
#define LOC_I2S_RX_SDA_P0_25 ((0)) /**< Input for I2S_RX_SDA comes from P0.25 */
#define LOC_I2S_RX_SDA_P0_6 ((1)) /**< Input for I2S_RX_SDA comes from P0.6 */
#define LOC_I2S_RX_WS_P0_24 ((0)) /**< Input for I2S_RX_WS comes from P0.24 */
#define LOC_I2S_RX_WS_P0_5 ((1)) /**< Input for I2S_RX_WS comes from P0.5 */
#define LOC_I2S_TX_SCK_P2_11 ((0)) /**< Input for I2S_TX_SCK comes from P2.11 */
#define LOC_I2S_TX_SCK_P0_7 ((1)) /**< Input for I2S_TX_SCK comes from P0.7 */
#define LOC_I2S_TX_WS_P2_12 ((0)) /**< Input for I2S_TX_WS comes from P2.12 */
#define LOC_I2S_TX_WS_P0_8 ((1)) /**< Input for I2S_TX_WS comes from P0.8 */
#define LOC_PWM0_CAP_0_P1_12 ((0)) /**< Input for PWM0_CAP_0 comes from P1.12 */
#define LOC_PWM0_CAP_0_P3_22 ((1)) /**< Input for PWM0_CAP_0 comes from P3.22 */
#define LOC_PWM1_CAP_0_P3_23 ((0)) /**< Input for PWM1_CAP_0 comes from P3.23 */
#define LOC_PWM1_CAP_0_P1_28 ((1)) /**< Input for PWM1_CAP_0 comes from P1.28 */
#define LOC_PWM1_CAP_0_P2_6 ((2)) /**< Input for PWM1_CAP_0 comes from P2.6 */
#define LOC_SD_CMD_P0_20 ((0)) /**< Input for SD_CMD comes from P0.20 */
#define LOC_SD_CMD_P1_3 ((1)) /**< Input for SD_CMD comes from P1.3 */
#define LOC_SD_DAT_0_P0_22 ((0)) /**< Input for SD_DAT_0 comes from P0.22 */
#define LOC_SD_DAT_0_P1_6 ((1)) /**< Input for SD_DAT_0 comes from P1.6 */
#define LOC_SD_DAT_1_P2_11 ((0)) /**< Input for SD_DAT_1 comes from P2.11 */
#define LOC_SD_DAT_1_P1_7 ((1)) /**< Input for SD_DAT_1 comes from P1.7 */
#define LOC_SD_DAT_2_P2_12 ((0)) /**< Input for SD_DAT_2 comes from P2.12 */
#define LOC_SD_DAT_2_P1_11 ((1)) /**< Input for SD_DAT_2 comes from P1.11 */
#define LOC_SD_DAT_3_P2_13 ((0)) /**< Input for SD_DAT_3 comes from P2.13 */
#define LOC_SD_DAT_3_P1_12 ((1)) /**< Input for SD_DAT_3 comes from P1.12 */
#define LOC_SSP0_MISO_P2_26 ((0)) /**< Input for SSP0_MISO comes from P2.26 */
#define LOC_SSP0_MISO_P1_23 ((1)) /**< Input for SSP0_MISO comes from P1_23 */
#define LOC_SSP0_MISO_P0_17 ((2)) /**< Input for SSP0_MISO comes from P0_17 */
#define LOC_SSP0_MOSI_P2_27 ((0)) /**< Input for SSP0_MOSI comes from P2.27 */
#define LOC_SSP0_MOSI_P1_24 ((1)) /**< Input for SSP0_MOSI comes from P1.24 */
#define LOC_SSP0_MOSI_P0_18 ((2)) /**< Input for SSP0_MOSI comes from P0.18 */
#define LOC_SSP0_SCK_P1_20 ((0)) /**< Input for SSP0_SCK comes from P1.20 */
#define LOC_SSP0_SCK_P2_22 ((1)) /**< Input for SSP0_SCK comes from P2.22 */
#define LOC_SSP0_SCK_P0_15 ((2)) /**< Input for SSP0_SCK comes from P0_15 */
#define LOC_SSP0_SSEL_P2_23 ((0)) /**< Input for SSP0_SSEL comes from P2.23 */
#define LOC_SSP0_SSEL_P1_21 ((1)) /**< Input for SSP0_SSEL comes from P1.21 */
#define LOC_SSP0_SSEL_P1_28 ((2)) /**< Input for SSP0_SSEL comes from P1.28 */
#define LOC_SSP0_SSEL_P0_16 ((3)) /**< Input for SSP0_SSEL comes from P0.16 */
#define LOC_SSP1_MISO_P0_12 ((0)) /**< Input for SSP1_MISO comes from P0.12 */
#define LOC_SSP1_MISO_P1_18 ((1)) /**< Input for SSP1_MISO comes from P1.18 */
#define LOC_SSP1_MISO_P4_22 ((2)) /**< Input for SSP1_MISO comes from P4_22 */
#define LOC_SSP1_MISO_P0_8 ((3)) /**< Input for SSP1_MISO comes from P0.8 */
#define LOC_SSP1_MOSI_P0_13 ((0)) /**< Input for SSP1_MOSI comes from P0.13 */
#define LOC_SSP1_MOSI_P1_22 ((1)) /**< Input for SSP1_MOSI comes from P1.22 */
#define LOC_SSP1_MOSI_P4_23 ((2)) /**< Input for SSP1_MOSI comes from P4.23 */
#define LOC_SSP1_MOSI_P0_9 ((3)) /**< Input for SSP1_MOSI comes from P0.9 */
#define LOC_SSP1_SCK_P1_31 ((0)) /**< Input for SSP1_SCK comes from P1.31 */
#define LOC_SSP1_SCK_P1_19 ((1)) /**< Input for SSP1_SCK comes from P1.19 */
#define LOC_SSP1_SCK_P4_20 ((2)) /**< Input for SSP1_SCK comes from P4_20 */
#define LOC_SSP1_SCK_P0_7 ((3)) /**< Input for SSP1_SCK comes from P0_7 */
#define LOC_SSP1_SSEL_P0_14 ((0)) /**< Input for SSP1_SSEL comes from P0.14 */
#define LOC_SSP1_SSEL_P1_26 ((1)) /**< Input for SSP1_SSEL comes from P1.26 */
#define LOC_SSP1_SSEL_P4_21 ((2)) /**< Input for SSP1_SSEL comes from P4.21 */
#define LOC_SSP1_SSEL_P0_6 ((3)) /**< Input for SSP1_SSEL comes from P0.6 */
#define LOC_SSP2_MISO_P1_4 ((1)) /**< Input for SSP2_MISO comes from P1.4 */
#define LOC_SSP2_MOSI_P1_1 ((1)) /**< Input for SSP2_MOSI comes from P1.1 */
#define LOC_SSP2_SCK_P1_0 ((1)) /**< Input for SSP2_SCK comes from P1.0 */
#define LOC_SSP2_SSEL_P1_8 ((1)) /**< Input for SSP2_SSEL comes from P1.8 */
#define LOC_T0_CAP_0_P3_23 ((0)) /**< Input for T0_CAP_0 comes from P3.23 */
#define LOC_T0_CAP_0_P1_26 ((1)) /**< Input for T0_CAP_0 comes from P1.26 */
#define LOC_T0_CAP_1_P3_24 ((0)) /**< Input for T0_CAP_1 comes from P3.24 */
#define LOC_T0_CAP_1_P1_27 ((1)) /**< Input for T0_CAP_1 comes from P1.27 */
#define LOC_T1_CAP_0_P1_18 ((0)) /**< Input for T1_CAP_0 comes from P1.18 */
#define LOC_T1_CAP_0_P3_27 ((1)) /**< Input for T1_CAP_0 comes from P3.27 */
#define LOC_T1_CAP_1_P3_28 ((0)) /**< Input for T1_CAP_1 comes from P3.28 */
#define LOC_T1_CAP_1_P1_19 ((1)) /**< Input for T1_CAP_1 comes from P1.19 */
#define LOC_T2_CAP_0_P2_14 ((0)) /**< Input for T2_CAP_0 comes from P2.14 */
#define LOC_T2_CAP_0_P2_6 ((1)) /**< Input for T2_CAP_0 comes from P2.6 */
#define LOC_T2_CAP_0_P0_4 ((2)) /**< Input for T2_CAP_0 comes from P0.4 */
#define LOC_T2_CAP_0_P1_14 ((3)) /**< Input for T2_CAP_0 comes from P1.14 */
#define LOC_T2_CAP_1_P2_15 ((0)) /**< Input for T2_CAP_1 comes from P2.15 */
#define LOC_T2_CAP_1_P0_5 ((1)) /**< Input for T2_CAP_1 comes from P0.5 */
#define LOC_T3_CAP_0_P0_23 ((0)) /**< Input for T3_CAP_0 comes from P0.23 */
#define LOC_T3_CAP_0_P2_22 ((1)) /**< Input for T3_CAP_0 comes from P2.22 */
#define LOC_T3_CAP_0_P1_10 ((2)) /**< Input for T3_CAP_0 comes from P1.10 */
#define LOC_T3_CAP_1_P0_24 ((0)) /**< Input for T3_CAP_1 comes from P0.24 */
#define LOC_T3_CAP_1_P2_23 ((1)) /**< Input for T3_CAP_1 comes from P2.23 */
#define LOC_T3_CAP_1_P1_0 ((2)) /**< Input for T3_CAP_1 comes from P1.0 */
#define LOC_U0_RXD_P0_1 ((0)) /**< Input for U0_RXD comes from P0.1 */
#define LOC_U0_RXD_P0_3 ((1)) /**< Input for U0_RXD comes from P0.3 */
#define LOC_U1_CTS_P0_17 ((0)) /**< Input for U1_CTS comes from P0.17 */
#define LOC_U1_CTS_P2_8 ((1)) /**< Input for U1_CTS comes from P2.8 */
#define LOC_U1_CTS_P2_2 ((2)) /**< Input for U1_CTS comes from P2.2 */
#define LOC_U1_CTS_P3_18 ((3)) /**< Input for U1_CTS comes from P3.18 */
#define LOC_U1_DCD_P0_18 ((0)) /**< Input for U1_DCD comes from P0.18 */
#define LOC_U1_DCD_P2_3 ((1)) /**< Input for U1_DCD comes from P2.3 */
#define LOC_U1_DCD_P3_19 ((2)) /**< Input for U1_DCD comes from P3_19 */
#define LOC_U1_DSR_P0_19 ((0)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_DSR_P2_4 ((1)) /**< Input for U1_DSR comes from P2.4 */
#define LOC_U1_DSR_P3_20 ((2)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_RI_P0_21 ((0)) /**< Input for U1_RI comes from P0.21 */
#define LOC_U1_RI_P2_6 ((1)) /**< Input for U1_RI comes from P2.6 */
#define LOC_U1_RI_P3_22 ((2)) /**< Input for U1_RI comes from P3.22 */
#define LOC_U1_RXD_P0_16 ((0)) /**< Input for U1_RXD comes from P0.16 */
#define LOC_U1_RXD_P3_17 ((1)) /**< Input for U1_RXD comes from P3.17 */
#define LOC_U1_RXD_P2_1 ((2)) /**< Input for U1_RXD comes from P2.1 */
#define LOC_U2_RXD_P0_11 ((0)) /**< Input for U2_RXD comes from P0.11 */
#define LOC_U2_RXD_P4_23 ((1)) /**< Input for U2_RXD comes from P4.23 */
#define LOC_U2_RXD_P2_9 ((2)) /**< Input for U2_RXD comes from P2.9 */
#define LOC_U3_RXD_P0_26 ((0)) /**< Input for U3_RXD comes from P0.26 */
#define LOC_U3_RXD_P0_1 ((1)) /**< Input for U3_RXD comes from P0.1 */
#define LOC_U3_RXD_P4_29 ((2)) /**< Input for U3_RXD comes from P4.29 */
#define LOC_U3_RXD_P0_3 ((3)) /**< Input for U3_RXD comes from P0.3 */
#define LOC_U4_RXD_P2_9 ((0)) /**< Input for U4_RXD comes from P2.9 */
#define LOC_U4_RXD_P5_3 ((1)) /**< Input for U4_RXD comes from P5.3 */
#define LOC_USB_SCL_P0_28 ((0)) /**< Input for USB_SCL comes from P0.28 */
#define LOC_USB_SCL_P1_28 ((1)) /**< Input for USB_SCL comes from P1.28 */
#define LOC_USB_SDA_P0_27 ((0)) /**< Input for USB_SDA comes from P0.27 */
#define LOC_USB_SDA_P1_29 ((1)) /**< Input for USB_SDA comes from P1.29 */
#define LOC_CAN_RD_1_P0_0 ((0)) /**< Input for CAN_RD_1 comes from P0.0 */
#define LOC_CAN_RD_1_P0_21 ((1)) /**< Input for CAN_RD_1 comes from P0.21 */
#define LOC_CAN_RD_2_P2_7 ((0)) /**< Input for CAN_RD_2 comes from P2.7 */
#define LOC_CAN_RD_2_P0_4 ((1)) /**< Input for CAN_RD_2 comes from P0.4 */
#define LOC_ENET_MDIO_P2_9 ((0)) /**< Input for ENET_MDIO comes from P2.9 */
#define LOC_ENET_MDIO_P1_17 ((1)) /**< Input for ENET_MDIO comes from P1.17 */
#define LOC_EINT_0_P0_29 ((0)) /**< Input for EINT_0 comes from P0.29 */
#define LOC_EINT_0_P2_10 ((1)) /**< Input for EINT_0 comes from P2.10 */
#define LOC_EINT_1_P0_30 ((0)) /**< Input for EINT_1 comes from P0.30 */
#define LOC_EINT_1_P2_11 ((1)) /**< Input for EINT_1 comes from P2.11 */
#define LOC_I2C0_SCL_P1_31 ((0)) /**< Input for I2C0_SCL comes from P1.31 */
#define LOC_I2C0_SCL_P0_28 ((1)) /**< Input for I2C0_SCL comes from P0.28 */
#define LOC_I2C0_SCL_P5_3 ((2)) /**< Input for I2C0_SCL comes from P5.3 */
#define LOC_I2C0_SDA_P1_30 ((0)) /**< Input for I2C0_SDA comes from P1.30 */
#define LOC_I2C0_SDA_P0_27 ((1)) /**< Input for I2C0_SDA comes from P0.27 */
#define LOC_I2C0_SDA_P5_2 ((2)) /**< Input for I2C0_SDA comes from P5.2 */
#define LOC_I2C1_SCL_P0_1 ((0)) /**< Input for I2C1_SCL comes from P0.1 */
#define LOC_I2C1_SCL_P2_15 ((1)) /**< Input for I2C1_SCL comes from P2.15 */
#define LOC_I2C1_SCL_P0_20 ((2)) /**< Input for I2C1_SCL comes from P0.20 */
#define LOC_I2C1_SDA_P2_14 ((0)) /**< Input for I2C1_SDA comes from P2.14 */
#define LOC_I2C1_SDA_P0_0 ((1)) /**< Input for I2C1_SDA comes from P0.0 */
#define LOC_I2C1_SDA_P0_19 ((2)) /**< Input for I2C1_SDA comes from P0.19 */
#define LOC_I2C2_SCL_P2_31 ((0)) /**< Input for I2C2_SCL comes from P2.31 */
#define LOC_I2C2_SCL_P0_11 ((1)) /**< Input for I2C2_SCL comes from P0.11 */
#define LOC_I2C2_SCL_P4_21 ((2)) /**< Input for I2C2_SCL comes from P4.21 */
#define LOC_I2C2_SCL_P4_29 ((3)) /**< Input for I2C2_SCL comes from P4.29 */
#define LOC_I2C2_SDA_P2_30 ((0)) /**< Input for I2C2_SDA comes from P2.30 */
#define LOC_I2C2_SDA_P0_10 ((1)) /**< Input for I2C2_SDA comes from P0.10 */
#define LOC_I2C2_SDA_P4_20 ((2)) /**< Input for I2C2_SDA comes from P4.20 */
#define LOC_I2C2_SDA_P1_15 ((3)) /**< Input for I2C2_SDA comes from P1.15 */
#define LOC_I2S_RX_SCK_P0_23 ((0)) /**< Input for I2S_RX_SCK comes from P0.23 */
#define LOC_I2S_RX_SCK_P0_4 ((1)) /**< Input for I2S_RX_SCK comes from P0.4 */
#define LOC_I2S_RX_SDA_P0_25 ((0)) /**< Input for I2S_RX_SDA comes from P0.25 */
#define LOC_I2S_RX_SDA_P0_6 ((1)) /**< Input for I2S_RX_SDA comes from P0.6 */
#define LOC_I2S_RX_WS_P0_24 ((0)) /**< Input for I2S_RX_WS comes from P0.24 */
#define LOC_I2S_RX_WS_P0_5 ((1)) /**< Input for I2S_RX_WS comes from P0.5 */
#define LOC_I2S_TX_SCK_P2_11 ((0)) /**< Input for I2S_TX_SCK comes from P2.11 */
#define LOC_I2S_TX_SCK_P0_7 ((1)) /**< Input for I2S_TX_SCK comes from P0.7 */
#define LOC_I2S_TX_WS_P2_12 ((0)) /**< Input for I2S_TX_WS comes from P2.12 */
#define LOC_I2S_TX_WS_P0_8 ((1)) /**< Input for I2S_TX_WS comes from P0.8 */
#define LOC_PWM0_CAP_0_P1_12 ((0)) /**< Input for PWM0_CAP_0 comes from P1.12 */
#define LOC_PWM0_CAP_0_P3_22 ((1)) /**< Input for PWM0_CAP_0 comes from P3.22 */
#define LOC_PWM1_CAP_0_P3_23 ((0)) /**< Input for PWM1_CAP_0 comes from P3.23 */
#define LOC_PWM1_CAP_0_P1_28 ((1)) /**< Input for PWM1_CAP_0 comes from P1.28 */
#define LOC_PWM1_CAP_0_P2_6 ((2)) /**< Input for PWM1_CAP_0 comes from P2.6 */
#define LOC_SD_CMD_P0_20 ((0)) /**< Input for SD_CMD comes from P0.20 */
#define LOC_SD_CMD_P1_3 ((1)) /**< Input for SD_CMD comes from P1.3 */
#define LOC_SD_DAT_0_P0_22 ((0)) /**< Input for SD_DAT_0 comes from P0.22 */
#define LOC_SD_DAT_0_P1_6 ((1)) /**< Input for SD_DAT_0 comes from P1.6 */
#define LOC_SD_DAT_1_P2_11 ((0)) /**< Input for SD_DAT_1 comes from P2.11 */
#define LOC_SD_DAT_1_P1_7 ((1)) /**< Input for SD_DAT_1 comes from P1.7 */
#define LOC_SD_DAT_2_P2_12 ((0)) /**< Input for SD_DAT_2 comes from P2.12 */
#define LOC_SD_DAT_2_P1_11 ((1)) /**< Input for SD_DAT_2 comes from P1.11 */
#define LOC_SD_DAT_3_P2_13 ((0)) /**< Input for SD_DAT_3 comes from P2.13 */
#define LOC_SD_DAT_3_P1_12 ((1)) /**< Input for SD_DAT_3 comes from P1.12 */
#define LOC_SSP0_MISO_P2_26 ((0)) /**< Input for SSP0_MISO comes from P2.26 */
#define LOC_SSP0_MISO_P1_23 ((1)) /**< Input for SSP0_MISO comes from P1_23 */
#define LOC_SSP0_MISO_P0_17 ((2)) /**< Input for SSP0_MISO comes from P0_17 */
#define LOC_SSP0_MOSI_P2_27 ((0)) /**< Input for SSP0_MOSI comes from P2.27 */
#define LOC_SSP0_MOSI_P1_24 ((1)) /**< Input for SSP0_MOSI comes from P1.24 */
#define LOC_SSP0_MOSI_P0_18 ((2)) /**< Input for SSP0_MOSI comes from P0.18 */
#define LOC_SSP0_SCK_P1_20 ((0)) /**< Input for SSP0_SCK comes from P1.20 */
#define LOC_SSP0_SCK_P2_22 ((1)) /**< Input for SSP0_SCK comes from P2.22 */
#define LOC_SSP0_SCK_P0_15 ((2)) /**< Input for SSP0_SCK comes from P0_15 */
#define LOC_SSP0_SSEL_P2_23 ((0)) /**< Input for SSP0_SSEL comes from P2.23 */
#define LOC_SSP0_SSEL_P1_21 ((1)) /**< Input for SSP0_SSEL comes from P1.21 */
#define LOC_SSP0_SSEL_P1_28 ((2)) /**< Input for SSP0_SSEL comes from P1.28 */
#define LOC_SSP0_SSEL_P0_16 ((3)) /**< Input for SSP0_SSEL comes from P0.16 */
#define LOC_SSP1_MISO_P0_12 ((0)) /**< Input for SSP1_MISO comes from P0.12 */
#define LOC_SSP1_MISO_P1_18 ((1)) /**< Input for SSP1_MISO comes from P1.18 */
#define LOC_SSP1_MISO_P4_22 ((2)) /**< Input for SSP1_MISO comes from P4_22 */
#define LOC_SSP1_MISO_P0_8 ((3)) /**< Input for SSP1_MISO comes from P0.8 */
#define LOC_SSP1_MOSI_P0_13 ((0)) /**< Input for SSP1_MOSI comes from P0.13 */
#define LOC_SSP1_MOSI_P1_22 ((1)) /**< Input for SSP1_MOSI comes from P1.22 */
#define LOC_SSP1_MOSI_P4_23 ((2)) /**< Input for SSP1_MOSI comes from P4.23 */
#define LOC_SSP1_MOSI_P0_9 ((3)) /**< Input for SSP1_MOSI comes from P0.9 */
#define LOC_SSP1_SCK_P1_31 ((0)) /**< Input for SSP1_SCK comes from P1.31 */
#define LOC_SSP1_SCK_P1_19 ((1)) /**< Input for SSP1_SCK comes from P1.19 */
#define LOC_SSP1_SCK_P4_20 ((2)) /**< Input for SSP1_SCK comes from P4_20 */
#define LOC_SSP1_SCK_P0_7 ((3)) /**< Input for SSP1_SCK comes from P0_7 */
#define LOC_SSP1_SSEL_P0_14 ((0)) /**< Input for SSP1_SSEL comes from P0.14 */
#define LOC_SSP1_SSEL_P1_26 ((1)) /**< Input for SSP1_SSEL comes from P1.26 */
#define LOC_SSP1_SSEL_P4_21 ((2)) /**< Input for SSP1_SSEL comes from P4.21 */
#define LOC_SSP1_SSEL_P0_6 ((3)) /**< Input for SSP1_SSEL comes from P0.6 */
#define LOC_SSP2_MISO_P1_4 ((1)) /**< Input for SSP2_MISO comes from P1.4 */
#define LOC_SSP2_MOSI_P1_1 ((1)) /**< Input for SSP2_MOSI comes from P1.1 */
#define LOC_SSP2_SCK_P1_0 ((1)) /**< Input for SSP2_SCK comes from P1.0 */
#define LOC_SSP2_SSEL_P1_8 ((1)) /**< Input for SSP2_SSEL comes from P1.8 */
#define LOC_T0_CAP_0_P3_23 ((0)) /**< Input for T0_CAP_0 comes from P3.23 */
#define LOC_T0_CAP_0_P1_26 ((1)) /**< Input for T0_CAP_0 comes from P1.26 */
#define LOC_T0_CAP_1_P3_24 ((0)) /**< Input for T0_CAP_1 comes from P3.24 */
#define LOC_T0_CAP_1_P1_27 ((1)) /**< Input for T0_CAP_1 comes from P1.27 */
#define LOC_T1_CAP_0_P1_18 ((0)) /**< Input for T1_CAP_0 comes from P1.18 */
#define LOC_T1_CAP_0_P3_27 ((1)) /**< Input for T1_CAP_0 comes from P3.27 */
#define LOC_T1_CAP_1_P3_28 ((0)) /**< Input for T1_CAP_1 comes from P3.28 */
#define LOC_T1_CAP_1_P1_19 ((1)) /**< Input for T1_CAP_1 comes from P1.19 */
#define LOC_T2_CAP_0_P2_14 ((0)) /**< Input for T2_CAP_0 comes from P2.14 */
#define LOC_T2_CAP_0_P2_6 ((1)) /**< Input for T2_CAP_0 comes from P2.6 */
#define LOC_T2_CAP_0_P0_4 ((2)) /**< Input for T2_CAP_0 comes from P0.4 */
#define LOC_T2_CAP_0_P1_14 ((3)) /**< Input for T2_CAP_0 comes from P1.14 */
#define LOC_T2_CAP_1_P2_15 ((0)) /**< Input for T2_CAP_1 comes from P2.15 */
#define LOC_T2_CAP_1_P0_5 ((1)) /**< Input for T2_CAP_1 comes from P0.5 */
#define LOC_T3_CAP_0_P0_23 ((0)) /**< Input for T3_CAP_0 comes from P0.23 */
#define LOC_T3_CAP_0_P2_22 ((1)) /**< Input for T3_CAP_0 comes from P2.22 */
#define LOC_T3_CAP_0_P1_10 ((2)) /**< Input for T3_CAP_0 comes from P1.10 */
#define LOC_T3_CAP_1_P0_24 ((0)) /**< Input for T3_CAP_1 comes from P0.24 */
#define LOC_T3_CAP_1_P2_23 ((1)) /**< Input for T3_CAP_1 comes from P2.23 */
#define LOC_T3_CAP_1_P1_0 ((2)) /**< Input for T3_CAP_1 comes from P1.0 */
#define LOC_U0_RXD_P0_1 ((0)) /**< Input for U0_RXD comes from P0.1 */
#define LOC_U0_RXD_P0_3 ((1)) /**< Input for U0_RXD comes from P0.3 */
#define LOC_U1_CTS_P0_17 ((0)) /**< Input for U1_CTS comes from P0.17 */
#define LOC_U1_CTS_P2_8 ((1)) /**< Input for U1_CTS comes from P2.8 */
#define LOC_U1_CTS_P2_2 ((2)) /**< Input for U1_CTS comes from P2.2 */
#define LOC_U1_CTS_P3_18 ((3)) /**< Input for U1_CTS comes from P3.18 */
#define LOC_U1_DCD_P0_18 ((0)) /**< Input for U1_DCD comes from P0.18 */
#define LOC_U1_DCD_P2_3 ((1)) /**< Input for U1_DCD comes from P2.3 */
#define LOC_U1_DCD_P3_19 ((2)) /**< Input for U1_DCD comes from P3_19 */
#define LOC_U1_DSR_P0_19 ((0)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_DSR_P2_4 ((1)) /**< Input for U1_DSR comes from P2.4 */
#define LOC_U1_DSR_P3_20 ((2)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_RI_P0_21 ((0)) /**< Input for U1_RI comes from P0.21 */
#define LOC_U1_RI_P2_6 ((1)) /**< Input for U1_RI comes from P2.6 */
#define LOC_U1_RI_P3_22 ((2)) /**< Input for U1_RI comes from P3.22 */
#define LOC_U1_RXD_P0_16 ((0)) /**< Input for U1_RXD comes from P0.16 */
#define LOC_U1_RXD_P3_17 ((1)) /**< Input for U1_RXD comes from P3.17 */
#define LOC_U1_RXD_P2_1 ((2)) /**< Input for U1_RXD comes from P2.1 */
#define LOC_U2_RXD_P0_11 ((0)) /**< Input for U2_RXD comes from P0.11 */
#define LOC_U2_RXD_P4_23 ((1)) /**< Input for U2_RXD comes from P4.23 */
#define LOC_U2_RXD_P2_9 ((2)) /**< Input for U2_RXD comes from P2.9 */
#define LOC_U3_RXD_P0_26 ((0)) /**< Input for U3_RXD comes from P0.26 */
#define LOC_U3_RXD_P0_1 ((1)) /**< Input for U3_RXD comes from P0.1 */
#define LOC_U3_RXD_P4_29 ((2)) /**< Input for U3_RXD comes from P4.29 */
#define LOC_U3_RXD_P0_3 ((3)) /**< Input for U3_RXD comes from P0.3 */
#define LOC_U4_RXD_P2_9 ((0)) /**< Input for U4_RXD comes from P2.9 */
#define LOC_U4_RXD_P5_3 ((1)) /**< Input for U4_RXD comes from P5.3 */
#define LOC_USB_SCL_P0_28 ((0)) /**< Input for USB_SCL comes from P0.28 */
#define LOC_USB_SCL_P1_28 ((1)) /**< Input for USB_SCL comes from P1.28 */
#define LOC_USB_SDA_P0_27 ((0)) /**< Input for USB_SDA comes from P0.27 */
#define LOC_USB_SDA_P1_29 ((1)) /**< Input for USB_SDA comes from P1.29 */
/**
* @}
@@ -206,32 +206,32 @@
/** @defgroup PINSEL_Public_Types PINSEL Public Types
* @{
*/
typedef enum
{
PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */
PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */
PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */
PINSEL_BASICMODE_REPEATER /**< Repeater mode */
PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */
PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */
PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */
PINSEL_BASICMODE_REPEATER /**< Repeater mode */
}PinSel_BasicMode;
typedef enum
{
/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
PINSEL_I2CMODE_FAST_STANDARD = 0,
/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
PINSEL_I2CMODE_OPENDRAINIO,
/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
PINSEL_I2CMODE_FASTMODEPLUS,
/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
PINSEL_I2CMODE_FAST_STANDARD = 0,
/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
PINSEL_I2CMODE_OPENDRAINIO,
/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
PINSEL_I2CMODE_FASTMODEPLUS,
/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
}PinSel_I2cMode;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup PINSEL_Public_Functions

1914
bsp/lpc178x/drivers/lpc177x_8x_uart.c
View File

File diff suppressed because it is too large Load Diff

514
bsp/lpc178x/drivers/lpc177x_8x_uart.h
View File

File diff suppressed because it is too large Load Diff

90
bsp/lpc178x/drivers/lpc17xx_lcd.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -13,8 +13,8 @@
#include "drv_glcd.h"
#define RT_HW_LCD_WIDTH 480
#define RT_HW_LCD_HEIGHT 272
#define RT_HW_LCD_WIDTH 480
#define RT_HW_LCD_HEIGHT 272
static struct rt_device_graphic_info _lcd_info;
static struct rt_device lcd;
@@ -23,38 +23,38 @@ static struct rt_device lcd;
static rt_err_t rt_lcd_init (rt_device_t dev)
{
PINSEL_ConfigPin(5, 4, 0);
LPC_GPIO5->DIR |= 1<<4;
LPC_GPIO5->CLR = 1<<4;
LPC_GPIO5->SET = 1<<4;
LPC_GPIO5->DIR |= 1<<4;
LPC_GPIO5->CLR = 1<<4;
LPC_GPIO5->SET = 1<<4;
/*Disable LCD controller*/
GLCD_Ctrl (FALSE);
/*Init LCD and copy picture in video RAM*/
GLCD_Init (_lcd_info.framebuffer);
/*Enable LCD*/
GLCD_Ctrl (TRUE);
/*Disable LCD controller*/
GLCD_Ctrl (FALSE);
/*Init LCD and copy picture in video RAM*/
GLCD_Init (_lcd_info.framebuffer);
/*Enable LCD*/
GLCD_Ctrl (TRUE);
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
return RT_EOK;
}
@@ -63,27 +63,27 @@ void rt_hw_lcd_init(void)
{
rt_uint16_t * _rt_framebuffer = RT_NULL;
// _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
// if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
// _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
// if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
_rt_framebuffer = (rt_uint16_t *)0xA0000000;
_rt_framebuffer = (rt_uint16_t *)0xA0000000;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
/* init device structure */
lcd.type = RT_Device_Class_Graphic;
lcd.init = rt_lcd_init;
lcd.open = RT_NULL;
lcd.close = RT_NULL;
lcd.control = rt_lcd_control;
lcd.user_data = (void*)&_lcd_info;
/* init device structure */
lcd.type = RT_Device_Class_Graphic;
lcd.init = rt_lcd_init;
lcd.open = RT_NULL;
lcd.close = RT_NULL;
lcd.control = rt_lcd_control;
lcd.user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
/* register lcd device to RT-Thread */
rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
void lcd_fill(uint8_t * start, uint8_t * end, uint8_t pixel)

36
bsp/lpc178x/drivers/lpc_types.h
View File

@@ -1,15 +1,15 @@
/**********************************************************************
* $Id$ lpc_types.h 2011-06-02
* $Id$ lpc_types.h 2011-06-02
*//**
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@@ -37,7 +37,7 @@
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types Basic Public Data Types
* @{
@@ -71,8 +71,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
*/
typedef enum
{
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_Type;
@@ -98,7 +98,7 @@ typedef int32_t(*PFI)();
*/
#undef _BIT
/** Set bit macro */
#define _BIT(n) (1<<n)
#define _BIT(n) (1<<n)
/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
@@ -161,16 +161,16 @@ typedef uint8_t UNS_8;
typedef int8_t INT_8;
/** SMA type for 16 bit unsigned value */
typedef uint16_t UNS_16;
typedef uint16_t UNS_16;
/** SMA type for 16 bit signed value */
typedef int16_t INT_16;
typedef int16_t INT_16;
/** SMA type for 32 bit unsigned value */
typedef uint32_t UNS_32;
typedef uint32_t UNS_32;
/** SMA type for 32 bit signed value */
typedef int32_t INT_32;
typedef int32_t INT_32;
/** SMA type for 64 bit signed value */
typedef int64_t INT_64;

112
bsp/lpc178x/drivers/sdram.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,10 +12,10 @@
#include "LPC177x_8x.h"
#include "sdram.h"
//LPC_EMC_TypeDef * const g_pEMC = ((LPC_EMC_TypeDef*) LPC_EMC_BASE);
//LPC_IOCON_TypeDef * const LPC_IOCON = ((LPC_IOCON_TypeDef*) LPC_IOCON_BASE);
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define EMC_NS2CLK(ns, nsPerClk) ((ns + nsPerClk - 1) / nsPerClk)
//LPC_EMC_TypeDef * const g_pEMC = ((LPC_EMC_TypeDef*) LPC_EMC_BASE);
//LPC_IOCON_TypeDef * const LPC_IOCON = ((LPC_IOCON_TypeDef*) LPC_IOCON_BASE);
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define EMC_NS2CLK(ns, nsPerClk) ((ns + nsPerClk - 1) / nsPerClk)
static void delayMs(int a,int b)
{
@@ -24,65 +24,65 @@ static void delayMs(int a,int b)
}
/*****************************************************************************
** Function name: delayMs
** Function name: delayMs
**
** Descriptions: Start the timer delay in milo seconds
** until elapsed
** Descriptions: Start the timer delay in milo seconds
** until elapsed
**
** parameters: timer number, Delay value in milo second
** parameters: timer number, Delay value in milo second
**
** Returned value: None
** Returned value: None
**
*****************************************************************************/
//void delayMs(uint8_t timer_num, uint32_t delayInMs)
//{
// if ( timer_num == 0 )
// {
// LPC_TIM0->TCR = 0x02; /* reset timer */
// LPC_TIM0->PR = 0x00; /* set prescaler to zero */
// LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM0->IR = 0xff; /* reset all interrrupts */
// LPC_TIM0->MCR = 0x04; /* stop timer on match */
// LPC_TIM0->TCR = 0x01; /* start timer */
// LPC_TIM0->TCR = 0x02; /* reset timer */
// LPC_TIM0->PR = 0x00; /* set prescaler to zero */
// LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM0->IR = 0xff; /* reset all interrrupts */
// LPC_TIM0->MCR = 0x04; /* stop timer on match */
// LPC_TIM0->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM0->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM0->TCR & 0x01);
// }
// else if ( timer_num == 1 )
// {
// LPC_TIM1->TCR = 0x02; /* reset timer */
// LPC_TIM1->PR = 0x00; /* set prescaler to zero */
// LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM1->IR = 0xff; /* reset all interrrupts */
// LPC_TIM1->MCR = 0x04; /* stop timer on match */
// LPC_TIM1->TCR = 0x01; /* start timer */
// LPC_TIM1->TCR = 0x02; /* reset timer */
// LPC_TIM1->PR = 0x00; /* set prescaler to zero */
// LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM1->IR = 0xff; /* reset all interrrupts */
// LPC_TIM1->MCR = 0x04; /* stop timer on match */
// LPC_TIM1->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM1->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM1->TCR & 0x01);
// }
// else if ( timer_num == 2 )
// {
// LPC_TIM2->TCR = 0x02; /* reset timer */
// LPC_TIM2->PR = 0x00; /* set prescaler to zero */
// LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM2->IR = 0xff; /* reset all interrrupts */
// LPC_TIM2->MCR = 0x04; /* stop timer on match */
// LPC_TIM2->TCR = 0x01; /* start timer */
// LPC_TIM2->TCR = 0x02; /* reset timer */
// LPC_TIM2->PR = 0x00; /* set prescaler to zero */
// LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM2->IR = 0xff; /* reset all interrrupts */
// LPC_TIM2->MCR = 0x04; /* stop timer on match */
// LPC_TIM2->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM2->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM2->TCR & 0x01);
// }
// else if ( timer_num == 3 )
// {
// LPC_TIM3->TCR = 0x02; /* reset timer */
// LPC_TIM3->PR = 0x00; /* set prescaler to zero */
// LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM3->IR = 0xff; /* reset all interrrupts */
// LPC_TIM3->MCR = 0x04; /* stop timer on match */
// LPC_TIM3->TCR = 0x01; /* start timer */
// LPC_TIM3->TCR = 0x02; /* reset timer */
// LPC_TIM3->PR = 0x00; /* set prescaler to zero */
// LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM3->IR = 0xff; /* reset all interrrupts */
// LPC_TIM3->MCR = 0x04; /* stop timer on match */
// LPC_TIM3->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM3->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM3->TCR & 0x01);
// }
// return;
//}
@@ -204,7 +204,7 @@ void SDRAM_Init (void)
{
uint32_t i, dwtemp = dwtemp;
uint16_t wtemp = wtemp;
uint32_t mhz, nsPerClk;
uint32_t mhz, nsPerClk;
/* Enable External Memory Controller power/clock */
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00001010;
@@ -213,10 +213,10 @@ void SDRAM_Init (void)
EMC_GPIO_Init();
mhz = SystemCoreClock / 1000000;
if (LPC_SC->EMCCLKSEL)
mhz >>= 1;
nsPerClk = 1000 / mhz;
mhz = SystemCoreClock / 1000000;
if (LPC_SC->EMCCLKSEL)
mhz >>= 1;
nsPerClk = 1000 / mhz;
LPC_EMC->DynamicRP = EMC_NS2CLK(20, nsPerClk); /* 20ns, */
LPC_EMC->DynamicRAS = /*EMC_NS2CLK(42, nsPerClk);*/ 15; /* 42ns to 100K ns, */
LPC_EMC->DynamicSREX = 1 - 1; /* tSRE, 1clk, */
@@ -225,7 +225,7 @@ void SDRAM_Init (void)
LPC_EMC->DynamicWR = 2 - 1; /* 2CLK, */
LPC_EMC->DynamicRC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRC=63ns(min)*/
LPC_EMC->DynamicRFC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRFC=tRC */
LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, ²»ÖªµÀ£¬ÉèΪ×î¾Ã */
LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, 不知道，设为最久 */
LPC_EMC->DynamicRRD = EMC_NS2CLK(63, nsPerClk); /* 3clk, tRRD=15ns(min) */
LPC_EMC->DynamicMRD = 2 - 1; /* 2clk, tMRD=2clk(min) */
@@ -249,22 +249,22 @@ void SDRAM_Init (void)
#ifdef SDRAM_CONFIG_16BIT
LPC_EMC->DynamicConfig0 = 0x680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
#elif defined SDRAM_CONFIG_32BIT
LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
#endif
delayMs(0, 100);
LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
delayMs(0, 200); /* wait 200ms */
delayMs(0, 200); /* wait 200ms */
LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
/* 64ms/8192=7.8125us, nx16x8.33ns<7.8125us, n<58.6*/
wtemp = 64000000 / (1 << 13);
wtemp -= 16;
wtemp >>= 4;
wtemp = wtemp * mhz / 1000;
wtemp = 64000000 / (1 << 13);
wtemp -= 16;
wtemp >>= 4;
wtemp = wtemp * mhz / 1000;
LPC_EMC->DynamicRefresh = wtemp;
LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
@@ -273,7 +273,7 @@ void SDRAM_Init (void)
wtemp = *((volatile uint16_t *)(SDRAM_BASE | (0x33<<12))); /* 8 burst, 3 CAS latency */
#elif defined SDRAM_CONFIG_32BIT
dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */
dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */
#endif
LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */

9
bsp/lpc178x/drivers/sdram.h
View File

@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef SDRAM_H_INCLUDED
#define SDRAM_H_INCLUDED

310
bsp/lpc178x/drivers/uart.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -25,14 +25,14 @@
struct rt_uart_lpc
{
struct rt_device parent;
struct rt_device parent;
LPC_UART_TypeDef * UART;
IRQn_Type UART_IRQn;
LPC_UART_TypeDef * UART;
IRQn_Type UART_IRQn;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
};
#ifdef RT_USING_UART0
@@ -45,96 +45,96 @@ struct rt_uart_lpc uart1_device;
#ifdef RT_USING_UART0
void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
rt_ubase_t level, iir;
struct rt_uart_lpc* uart = &uart0_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = uart->UART->IIR;
iir = uart->UART->IIR;
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
level = rt_hw_interrupt_disable();
uart->save_index ++;
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
}
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
return;
}
#endif
#ifdef RT_USING_UART1
void UART1_IRQHandler(void)
{
rt_ubase_t level, iir;
rt_ubase_t level, iir;
struct rt_uart_lpc* uart = &uart1_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = uart->UART->IIR;
iir = uart->UART->IIR;
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
level = rt_hw_interrupt_disable();
uart->save_index ++;
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
}
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
return;
}
#endif
static rt_err_t rt_uart_init (rt_device_t dev)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
UART_CFG_Type UART_ConfigStruct;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
UART_CFG_Type UART_ConfigStruct;
#ifdef RT_USING_UART0
if( uart->UART == LPC_UART0 )
if( uart->UART == LPC_UART0 )
{
/*
* Initialize UART0 pin connect
@@ -184,170 +184,170 @@ static rt_err_t rt_uart_init (rt_device_t dev)
#endif
#ifdef RT_USING_UART2
if( uart->UART == LPC_UART2 )
if( uart->UART == LPC_UART2 )
{
}
#endif
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
NVIC_EnableIRQ( uart->UART_IRQn );
}
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
NVIC_EnableIRQ( uart->UART_IRQn );
}
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
NVIC_DisableIRQ( uart->UART_IRQn );
}
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
NVIC_DisableIRQ( uart->UART_IRQn );
}
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(uart != RT_NULL);
rt_uint8_t* ptr;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
char *ptr;
ptr = (char*)buffer;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
char *ptr;
ptr = (char*)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(uart->UART->LSR & UART_LSR_THRE));
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(uart->UART->LSR & UART_LSR_THRE));
UART_SendByte( uart->UART,'\r');
}
}
while (!(uart->UART->LSR & UART_LSR_THRE));
UART_SendByte( uart->UART,*ptr);
ptr ++;
size --;
}
}
else
{
while (!(uart->UART->LSR & UART_LSR_THRE));
UART_SendByte( uart->UART,*ptr);
ptr ++;
size --;
}
}
else
{
UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING);
}
return (rt_size_t) ptr - (rt_size_t) buffer;
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_lpc* uart;
struct rt_uart_lpc* uart;
#ifdef RT_USING_UART0
/* get uart device */
uart = &uart0_device;
uart0_device.UART = LPC_UART0;
uart0_device.UART_IRQn = UART0_IRQn;
/* get uart device */
uart = &uart0_device;
uart0_device.UART = LPC_UART0;
uart0_device.UART_IRQn = UART0_IRQn;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
rt_device_register(&uart->parent,
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
#endif
#ifdef RT_USING_UART1
/* get uart device */
uart = &uart1_device;
uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
uart1_device.UART_IRQn = UART1_IRQn;
/* get uart device */
uart = &uart1_device;
uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
uart1_device.UART_IRQn = UART1_IRQn;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
rt_device_register(&uart->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
#endif
}

56
bsp/lpc178x/rtconfig.h
View File

@@ -5,17 +5,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
@@ -30,11 +30,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
@@ -66,13 +66,13 @@
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
#define RT_USING_DEVICE
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@@ -84,7 +84,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
@@ -99,18 +99,18 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// #define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@@ -120,7 +120,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@@ -136,31 +136,31 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF 2048
#define RT_LWIP_TCP_SND_BUF 2048
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
#define RT_LWIP_TCP_SEG_NUM 4
#define RT_LWIP_TCP_SEG_NUM 4
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
@@ -181,7 +181,7 @@
// <section name="RT_USING_RTGUI" description="RT-Thread/GUI" default="true" >
// #define RT_USING_RTGUI
// <integer name="RTGUI_NAME_MAX" description="the name size of RT-Thread/GUI widget/objects" default="12" />
#define RTGUI_NAME_MAX 12
#define RTGUI_NAME_MAX 12
// <bool name="RTGUI_USING_SMALL_SIZE" description="use small size in RT-Thread/GUI" default="true" />
#define RTGUI_USING_SMALL_SIZE
// <bool name="RTGUI_USING_FONT16" description="support 16 weight font" default="true" />
@@ -191,7 +191,7 @@
// <bool name="RTGUI_USING_FONTHZ" description="support Chinese font" default="true" />
#define RTGUI_USING_FONTHZ
// <integer name="RTGUI_DEFAULT_FONT_SIZE" description="default font size in RT-Thread/GUI" default="16" />
#define RTGUI_DEFAULT_FONT_SIZE 16
#define RTGUI_DEFAULT_FONT_SIZE 16
// <bool name="RTGUI_USING_DFS_FILERW" description="use RT-Thread/DFS as file interface" default="true" />
// #define RTGUI_USING_DFS_FILERW
// <bool name="RTGUI_USING_HZ_BMP" description="use Chinese font bitmap engine" default="true" />

2
bsp/lpc2148/applications/application.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc2148/applications/startup.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

82
bsp/lpc2148/drivers/board.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -25,13 +25,13 @@
*/
void rt_hw_timer_handler(int vector, void *param)
{
rt_tick_increase();
rt_tick_increase();
/* clear interrupt flag */
T0IR |= 0x01;
/* clear interrupt flag */
T0IR |= 0x01;
/* acknowledge Interrupt */
VICVectAddr = 0;
/* acknowledge Interrupt */
VICVectAddr = 0;
}
/**
@@ -42,37 +42,37 @@ void rt_hw_timer_handler(int vector, void *param)
*/
void rt_hw_console_output(const char* str)
{
while (*str)
{
if (*str=='\n')
{
while (!(U0LSR & 0x20));
U0THR = '\r';
}
while (*str)
{
if (*str=='\n')
{
while (!(U0LSR & 0x20));
U0THR = '\r';
}
while (!(U0LSR & 0x20));
U0THR = *str;
while (!(U0LSR & 0x20));
U0THR = *str;
str ++;
}
str ++;
}
}
#define BAUD_RATE 115200
#define U0PINS 0x05
#define BAUD_RATE 115200
#define U0PINS 0x05
void rt_hw_console_init()
{
/* Enable RxD and TxD pins */
PINSEL0 = U0PINS;
/* Enable RxD and TxD pins */
PINSEL0 = U0PINS;
/* 8 bits, no Parity, 1 Stop bit */
U0LCR = 0x83;
/* 8 bits, no Parity, 1 Stop bit */
U0LCR = 0x83;
/* Setup Baudrate */
U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
/* Setup Baudrate */
U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
/* DLAB = 0 */
U0LCR = 0x03;
/* DLAB = 0 */
U0LCR = 0x03;
}
/**
@@ -80,23 +80,23 @@ void rt_hw_console_init()
*/
void rt_hw_board_init(void)
{
/* console init */
rt_hw_console_init();
/* console init */
rt_hw_console_init();
/* prescaler = 0*/
T0PR = 0;
T0PC = 0;
/* prescaler = 0*/
T0PR = 0;
T0PC = 0;
/* reset and enable MR0 interrupt */
T0MCR = 0x3;
T0MR0 = PCLK / RT_TICK_PER_SECOND;
/* reset and enable MR0 interrupt */
T0MCR = 0x3;
T0MR0 = PCLK / RT_TICK_PER_SECOND;
/* enable timer 0 */
T0TCR = 1;
/* enable timer 0 */
T0TCR = 1;
/* install timer handler */
rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0");
rt_hw_interrupt_umask(TIMER0_INT);
/* install timer handler */
rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0");
rt_hw_interrupt_umask(TIMER0_INT);
}
/*@}*/

8
bsp/lpc2148/drivers/board.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,13 +12,13 @@
#define __BOARD_H__
#include <rtthread.h>
#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */
#define PCLK 15000000 /* CCLK/4, use default */
#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */
#define PCLK 15000000 /* CCLK/4, use default */
/* RT_USING_UART */
#define RT_USING_UART1
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
void rt_hw_board_init(void);

88
bsp/lpc2148/drivers/dm9000.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -15,11 +15,11 @@
#define MAX_ADDR_LEN 6
struct rt_dm9000_eth
{
/* inherit from ethernet device */
struct eth_device parent;
/* inherit from ethernet device */
struct eth_device parent;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct rt_dm9000_eth dm9000_device;
@@ -52,67 +52,67 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_dm9000_close(rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_dm9000_control(rt_device_t dev, int cmd, void *args)
{
switch(cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
else return -RT_ERROR;
break;
switch(cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
default :
break;
}
return RT_EOK;
return RT_EOK;
}
/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
{
struct pbuf* q;
rt_uint32_t len;
rt_uint8_t* ptr;
struct pbuf* q;
rt_uint32_t len;
rt_uint8_t* ptr;
for (q = p; q != NULL; q = q->next)
{
len = q->len;
ptr = q->payload;
for (q = p; q != NULL; q = q->next)
{
len = q->len;
ptr = q->payload;
/* write data to device */
}
/* write data to device */
}
return RT_EOK;
return RT_EOK;
}
/* reception packet. */
struct pbuf *rt_dm9000_rx(rt_device_t dev)
{
struct pbuf* p;
rt_uint32_t len;
rt_uint32_t len;
/* init p pointer */
p = RT_NULL;
@@ -149,17 +149,17 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
void rt_hw_dm9000_init()
{
dm9000_device.parent.parent.init = rt_dm9000_init;
dm9000_device.parent.parent.open = rt_dm9000_open;
dm9000_device.parent.parent.close = rt_dm9000_close;
dm9000_device.parent.parent.read = rt_dm9000_read;
dm9000_device.parent.parent.write = rt_dm9000_write;
dm9000_device.parent.parent.control = rt_dm9000_control;
dm9000_device.parent.parent.user_data = RT_NULL;
dm9000_device.parent.parent.init = rt_dm9000_init;
dm9000_device.parent.parent.open = rt_dm9000_open;
dm9000_device.parent.parent.close = rt_dm9000_close;
dm9000_device.parent.parent.read = rt_dm9000_read;
dm9000_device.parent.parent.write = rt_dm9000_write;
dm9000_device.parent.parent.control = rt_dm9000_control;
dm9000_device.parent.parent.user_data = RT_NULL;
dm9000_device.parent.eth_rx = rt_dm9000_rx;
dm9000_device.parent.eth_tx = rt_dm9000_tx;
dm9000_device.parent.eth_rx = rt_dm9000_rx;
dm9000_device.parent.eth_tx = rt_dm9000_tx;
rt_device_register((rt_device_t)&dm9000_device,
"E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
rt_device_register((rt_device_t)&dm9000_device,
"E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
}

82
bsp/lpc2148/drivers/sd.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -22,12 +22,12 @@ static rt_err_t rt_sdcard_init(rt_device_t dev)
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
@@ -48,54 +48,54 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
{
return RT_EOK;
return RT_EOK;
}
void rt_hw_sdcard_init()
{
rt_size_t length;
rt_uint8_t* sector;
rt_uint8_t* sector;
/* sdcard hardware init */
sd.type = RT_Device_Class_Block;
sd.init = rt_sdcard_init;
sd.open = rt_sdcard_open;
sd.close = rt_sdcard_close;
sd.read = rt_sdcard_read;
sd.write = rt_sdcard_write;
sd.control = rt_sdcard_control;
sd.user_data = RT_NULL;
sd.type = RT_Device_Class_Block;
sd.init = rt_sdcard_init;
sd.open = rt_sdcard_open;
sd.close = rt_sdcard_close;
sd.read = rt_sdcard_read;
sd.write = rt_sdcard_write;
sd.control = rt_sdcard_control;
sd.user_data = RT_NULL;
/* get the first sector to read partition table */
sector = (rt_uint8_t*) rt_malloc (512);
if (sector == RT_NULL)
{
rt_kprintf("allocate partition sector buffer failed\n");
return;
}
/* get the first sector to read partition table */
sector = (rt_uint8_t*) rt_malloc (512);
if (sector == RT_NULL)
{
rt_kprintf("allocate partition sector buffer failed\n");
return;
}
length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
if (length == 512)
{
rt_err_t status;
length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
if (length == 512)
{
rt_err_t status;
/* get the first partition */
status = dfs_filesystem_get_partition(&part, sector, 0);
if (status != RT_EOK)
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
}
else
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
/* get the first partition */
status = dfs_filesystem_get_partition(&part, sector, 0);
if (status != RT_EOK)
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
}
else
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
rt_device_register(&sd,
"sd", RT_DEVICE_FLAG_RDWR);
rt_device_register(&sd,
"sd", RT_DEVICE_FLAG_RDWR);
}

450
bsp/lpc2148/drivers/serial.c
View File

File diff suppressed because it is too large Load Diff

46
bsp/lpc2148/rtconfig.h
View File

@@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second*/
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
@@ -62,12 +62,12 @@
#define RT_USING_DEVICE
#define RT_USING_UART1
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: FinSH shell options */
/* Using FinSH as Shell*/
@@ -87,11 +87,11 @@
/* SECTION: DFS options */
/* #define RT_USING_DFS */
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 8
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 8
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* Using lighweight TCP/IP protocol stack*/
@@ -119,21 +119,21 @@
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#endif

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