diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig index 01752dad94..decdf156d7 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig @@ -167,11 +167,16 @@ menu "On-chip Peripheral Drivers" default n endif - config BSP_USING_ONCHIP_RTC + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC select RT_USING_LIBC default n + if BSP_USING_ONCHIP_RTC + config RTC_USING_INTERNAL_CLK + bool "Using internal clock RTC" + default y + endif menuconfig BSP_USING_ADC bool "Enable ADC" diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py index b70a0dc654..0642f6429a 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py @@ -41,7 +41,7 @@ if PLATFORM == 'gcc': # DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant' DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32' # CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' - CFLAGS = DEVICE + CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' CPATH = '' diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c index 99483cb544..4f462e9040 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-01-28 greedyhao first version + * 2021-03-19 iysheng modify just set time first power up */ #include "board.h" @@ -95,30 +96,44 @@ uint8_t irtc_sfr_read(uint32_t cmd) IRTC_EXIT_CRITICAL(); } +static void _init_rtc_clock(void) +{ + uint8_t rtccon0; + uint8_t rtccon2; + + rtccon0 = irtc_sfr_read(RTCCON0_CMD); + rtccon2 = irtc_sfr_read(RTCCON2_CMD); +#ifdef RTC_USING_INTERNAL_CLK + rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE; + rtccon0 |= RTC_CON0_INTERNAL_32K; + rtccon2 | RTC_CON2_32K_SELECT; +#else + rtccon0 |= RTC_CON0_XOSC32K_ENABLE; + rtccon0 &= ~RTC_CON0_INTERNAL_32K; + rtccon2 & ~RTC_CON2_32K_SELECT; +#endif + irtc_sfr_write(RTCCON0_CMD, rtccon0); + irtc_sfr_write(RTCCON2_CMD, rtccon2); +} + void hal_rtc_init(void) { time_t sec = 0; struct tm tm_new = {0}; + uint8_t temp; - uint8_t temp = irtc_sfr_read(RTCCON0_CMD); - temp &= ~RTC_CON0_XOSC32K_ENABLE; - temp |= RTC_CON0_EXTERNAL_32K; - irtc_sfr_write(RTCCON0_CMD, temp); - temp = irtc_sfr_read(RTCCON2_CMD); - irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT); - + _init_rtc_clock(); temp = irtc_sfr_read(RTCCON0_CMD); - if (temp & BIT(7)) { - temp &= ~BIT(7); + if (temp & RTC_CON0_PWRUP_FIRST) { + temp &= ~RTC_CON0_PWRUP_FIRST; irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */ + tm_new.tm_mday = 29; + tm_new.tm_mon = 1 - 1; + tm_new.tm_year = 2021 - 1900; + sec = timegm(&tm_new); + + irtc_time_write(RTCCNT_CMD, sec); } - - tm_new.tm_mday = 29; - tm_new.tm_mon = 1 - 1; - tm_new.tm_year = 2021 - 1900; - sec = timegm(&tm_new); - - irtc_time_write(RTCCNT_CMD, sec); } /************** HAL End *******************/ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h index 6c128567b5..483f3e3f42 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h @@ -34,7 +34,7 @@ enum // RTCCON0 #define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */ -#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */ +#define RTC_CON0_INTERNAL_32K (0x01u << 6) /*!< Internal 32K select */ #define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */ #define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */ #define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */ diff --git a/bsp/lpc1114/driver/board.c b/bsp/lpc1114/driver/board.c index 6f2a4c85a3..03aa631e71 100644 --- a/bsp/lpc1114/driver/board.c +++ b/bsp/lpc1114/driver/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #define NVIC_ISPR HWREG32(SCB_BASE + 0x200) #define NVIC_ICPR HWREG32(SCB_BASE + 0x280) #define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2)) -#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20) +#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20) extern unsigned char __bss_end__[]; extern unsigned char _ram_end[]; diff --git a/bsp/lpc1114/driver/drv_uart.c b/bsp/lpc1114/driver/drv_uart.c index 96cf6f760d..10956140c1 100644 --- a/bsp/lpc1114/driver/drv_uart.c +++ b/bsp/lpc1114/driver/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/applications/application.c b/bsp/lpc176x/applications/application.c index 9facb30aa8..173e2df1bb 100644 --- a/bsp/lpc176x/applications/application.c +++ b/bsp/lpc176x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,44 +38,44 @@ extern int lwip_system_init(void); /* thread phase init */ void rt_init_thread_entry(void *parameter) { - /* initialize platform */ - platform_init(); + /* initialize platform */ + platform_init(); #ifdef RT_USING_LWIP /* register Ethernet interface device */ lpc17xx_emac_hw_init(); /* initialize lwip stack */ - /* register ethernetif device */ - eth_system_device_init(); + /* register ethernetif device */ + eth_system_device_init(); - /* initialize lwip system */ - lwip_system_init(); - rt_kprintf("TCP/IP initialized!\n"); + /* initialize lwip system */ + lwip_system_init(); + rt_kprintf("TCP/IP initialized!\n"); #endif /* Filesystem Initialization */ #ifdef RT_USING_DFS rt_hw_sdcard_init(); - /* initialize the device file system */ - dfs_init(); + /* initialize the device file system */ + dfs_init(); #ifdef RT_USING_DFS_ELMFAT - /* initialize the elm chan FatFS file system*/ - elm_init(); + /* initialize the elm chan FatFS file system*/ + elm_init(); #endif /* mount sd card fat partition 1 as root directory */ if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); + rt_kprintf("File System initialized!\n"); else - rt_kprintf("File System init failed!\n"); + rt_kprintf("File System init failed!\n"); #endif #ifdef RT_USING_FINSH - /* initialize finsh */ - finsh_system_init(); + /* initialize finsh */ + finsh_system_init(); #endif } @@ -84,8 +84,8 @@ int rt_application_init() rt_thread_t tid; tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); if (tid != RT_NULL) rt_thread_startup(tid); return 0; diff --git a/bsp/lpc176x/applications/platform.c b/bsp/lpc176x/applications/platform.c index 4bab858aa4..05ff436e8d 100644 --- a/bsp/lpc176x/applications/platform.c +++ b/bsp/lpc176x/applications/platform.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ static struct rt_memheap _memheap; void platform_init(void) { #ifdef RT_USING_MEMHEAP - /* create memory heap object on 0x2007 C000 - 0x2008 4000*/ + /* create memory heap object on 0x2007 C000 - 0x2008 4000*/ #ifdef RT_USING_LWIP - rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024); + rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024); #else - rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024); + rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024); #endif #endif } diff --git a/bsp/lpc176x/applications/platform.h b/bsp/lpc176x/applications/platform.h index e52e4066c2..25a97d8666 100644 --- a/bsp/lpc176x/applications/platform.h +++ b/bsp/lpc176x/applications/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/applications/startup.c b/bsp/lpc176x/applications/startup.c index 63d5b0f9a5..b9db54c429 100644 --- a/bsp/lpc176x/applications/startup.c +++ b/bsp/lpc176x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,28 +33,28 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - /* initialize memory system */ - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000); - #else - rt_system_heap_init((void*)&__bss_end, (void*)0x10008000); - #endif + /* initialize memory system */ + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000); + #else + rt_system_heap_init((void*)&__bss_end, (void*)0x10008000); + #endif #endif - /* initialize scheduler system */ - rt_system_scheduler_init(); + /* initialize scheduler system */ + rt_system_scheduler_init(); - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); @@ -62,25 +62,25 @@ void rtthread_startup(void) /* initialize timer thread */ rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/lpc176x/drivers/board.c b/bsp/lpc176x/drivers/board.c index c636462a2e..de3e476d55 100644 --- a/bsp/lpc176x/drivers/board.c +++ b/bsp/lpc176x/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,13 +29,13 @@ */ void rt_hw_timer_handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } void SysTick_Handler(void) @@ -48,24 +48,24 @@ void SysTick_Handler(void) */ void rt_hw_board_init() { - /* NVIC Configuration */ + /* NVIC Configuration */ #define NVIC_VTOR_MASK 0x3FFFFF80 #ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); #else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x00000000 */ - SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); + /* Set the Vector Table base location at 0x00000000 */ + SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); #endif - /* initialize systick */ - SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND); - /* set pend exception priority */ - NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1); + /* initialize systick */ + SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1); #ifdef RT_USING_UART0 - rt_hw_uart_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_hw_uart_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif } diff --git a/bsp/lpc176x/drivers/board.h b/bsp/lpc176x/drivers/board.h index 951a2c4cda..1e51e87615 100644 --- a/bsp/lpc176x/drivers/board.h +++ b/bsp/lpc176x/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/drivers/emac.c b/bsp/lpc176x/drivers/emac.c index 27fc55397a..e4f0363626 100644 --- a/bsp/lpc176x/drivers/emac.c +++ b/bsp/lpc176x/drivers/emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,20 +11,20 @@ #include "lwipopts.h" #include -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 -#define EMAC_PHY_100MBIT 2 +#define EMAC_PHY_AUTO 0 +#define EMAC_PHY_10MBIT 1 +#define EMAC_PHY_100MBIT 2 #define MAX_ADDR_LEN 6 struct lpc17xx_emac { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - rt_uint8_t phy_mode; + rt_uint8_t phy_mode; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct lpc17xx_emac lpc17xx_emac_device; static struct rt_semaphore sem_lock; @@ -36,40 +36,40 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ; void ENET_IRQHandler(void) { - rt_uint32_t status; + rt_uint32_t status; /* enter interrupt */ rt_interrupt_enter(); - status = LPC_EMAC->IntStatus; + status = LPC_EMAC->IntStatus; - if (status & INT_RX_DONE) - { - /* Disable EMAC RxDone interrupts. */ - LPC_EMAC->IntEnable = INT_TX_DONE; + if (status & INT_RX_DONE) + { + /* Disable EMAC RxDone interrupts. */ + LPC_EMAC->IntEnable = INT_TX_DONE; - /* a frame has been received */ - eth_device_ready(&(lpc17xx_emac_device.parent)); - } - else if (status & INT_TX_DONE) - { - /* set event */ - rt_event_send(&tx_event, 0x01); - } + /* a frame has been received */ + eth_device_ready(&(lpc17xx_emac_device.parent)); + } + else if (status & INT_TX_DONE) + { + /* set event */ + rt_event_send(&tx_event, 0x01); + } - if (status & INT_RX_OVERRUN) - { - rt_kprintf("rx overrun\n"); - } + if (status & INT_RX_OVERRUN) + { + rt_kprintf("rx overrun\n"); + } - if (status & INT_TX_UNDERRUN) - { - rt_kprintf("tx underrun\n"); - } + if (status & INT_TX_UNDERRUN) + { + rt_kprintf("tx underrun\n"); + } + + /* Clear the interrupt. */ + LPC_EMAC->IntClear = status; - /* Clear the interrupt. */ - LPC_EMAC->IntClear = status; - /* leave interrupt */ rt_interrupt_leave(); } @@ -77,440 +77,440 @@ void ENET_IRQHandler(void) /* phy write */ static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value) { - unsigned int tout; + unsigned int tout; - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MWTD = Value; + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Value; - /* Wait utill operation completed */ - tout = 0; - for (tout = 0; tout < MII_WR_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } + /* Wait utill operation completed */ + tout = 0; + for (tout = 0; tout < MII_WR_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } } /* phy read */ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) { - rt_uint32_t tout; + rt_uint32_t tout; - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MCMD = MCMD_READ; + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; - /* Wait until operation completed */ - tout = 0; - for (tout = 0; tout < MII_RD_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } - LPC_EMAC->MCMD = 0; - return (LPC_EMAC->MRDD); + /* Wait until operation completed */ + tout = 0; + for (tout = 0; tout < MII_RD_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } + LPC_EMAC->MCMD = 0; + return (LPC_EMAC->MRDD); } /* init rx descriptor */ rt_inline void rx_descr_init (void) { - rt_uint32_t i; + rt_uint32_t i; - for (i = 0; i < NUM_RX_FRAG; i++) - { - RX_DESC_PACKET(i) = RX_BUF(i); - RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); - RX_STAT_INFO(i) = 0; - RX_STAT_HASHCRC(i) = 0; - } + for (i = 0; i < NUM_RX_FRAG; i++) + { + RX_DESC_PACKET(i) = RX_BUF(i); + RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); + RX_STAT_INFO(i) = 0; + RX_STAT_HASHCRC(i) = 0; + } - /* Set EMAC Receive Descriptor Registers. */ - LPC_EMAC->RxDescriptor = RX_DESC_BASE; - LPC_EMAC->RxStatus = RX_STAT_BASE; - LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxDescriptor = RX_DESC_BASE; + LPC_EMAC->RxStatus = RX_STAT_BASE; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; - /* Rx Descriptors Point to 0 */ - LPC_EMAC->RxConsumeIndex = 0; + /* Rx Descriptors Point to 0 */ + LPC_EMAC->RxConsumeIndex = 0; } /* init tx descriptor */ rt_inline void tx_descr_init (void) { - rt_uint32_t i; + rt_uint32_t i; - for (i = 0; i < NUM_TX_FRAG; i++) - { - TX_DESC_PACKET(i) = TX_BUF(i); - TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); - TX_STAT_INFO(i) = 0; - } + for (i = 0; i < NUM_TX_FRAG; i++) + { + TX_DESC_PACKET(i) = TX_BUF(i); + TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); + TX_STAT_INFO(i) = 0; + } - /* Set EMAC Transmit Descriptor Registers. */ - LPC_EMAC->TxDescriptor = TX_DESC_BASE; - LPC_EMAC->TxStatus = TX_STAT_BASE; - LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxDescriptor = TX_DESC_BASE; + LPC_EMAC->TxStatus = TX_STAT_BASE; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; - /* Tx Descriptors Point to 0 */ - LPC_EMAC->TxProduceIndex = 0; + /* Tx Descriptors Point to 0 */ + LPC_EMAC->TxProduceIndex = 0; } static rt_err_t lpc17xx_emac_init(rt_device_t dev) { - /* Initialize the EMAC ethernet controller. */ - rt_uint32_t regv, tout, id1, id2; + /* Initialize the EMAC ethernet controller. */ + rt_uint32_t regv, tout, id1, id2; - /* Power Up the EMAC controller. */ - LPC_SC->PCONP |= 0x40000000; + /* Power Up the EMAC controller. */ + LPC_SC->PCONP |= 0x40000000; - /* Enable P1 Ethernet Pins. */ - LPC_PINCON->PINSEL2 = 0x50150105; - LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; + /* Enable P1 Ethernet Pins. */ + LPC_PINCON->PINSEL2 = 0x50150105; + LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; - /* Reset all EMAC internal modules. */ - LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | - MAC1_SIM_RES | MAC1_SOFT_RES; - LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | + MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; - /* A short delay after reset. */ - for (tout = 100; tout; tout--); + /* A short delay after reset. */ + for (tout = 100; tout; tout--); - /* Initialize MAC control registers. */ - LPC_EMAC->MAC1 = MAC1_PASS_ALL; - LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; - LPC_EMAC->MAXF = ETH_MAX_FLEN; - LPC_EMAC->CLRT = CLRT_DEF; - LPC_EMAC->IPGR = IPGR_DEF; + /* Initialize MAC control registers. */ + LPC_EMAC->MAC1 = MAC1_PASS_ALL; + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; - /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ - /* Enable Reduced MII interface. */ - LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; - for (tout = 100; tout; tout--); - LPC_EMAC->MCFG = MCFG_CLK_DIV20; + /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ + /* Enable Reduced MII interface. */ + LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; + for (tout = 100; tout; tout--); + LPC_EMAC->MCFG = MCFG_CLK_DIV20; - /* Enable Reduced MII interface. */ - LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; + /* Enable Reduced MII interface. */ + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; - /* Reset Reduced MII Logic. */ - LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; - for (tout = 100; tout; tout--); - LPC_EMAC->SUPP = SUPP_SPEED; + /* Reset Reduced MII Logic. */ + LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; + for (tout = 100; tout; tout--); + LPC_EMAC->SUPP = SUPP_SPEED; - /* Put the PHY in reset mode */ - write_PHY (PHY_REG_BMCR, 0x8000); - for (tout = 1000; tout; tout--); + /* Put the PHY in reset mode */ + write_PHY (PHY_REG_BMCR, 0x8000); + for (tout = 1000; tout; tout--); - /* Wait for hardware reset to end. */ - for (tout = 0; tout < 10000; tout++) - { - regv = read_PHY (PHY_REG_BMCR); - if (!(regv & 0x8000)) - { - /* Reset complete */ - break; - } - } - if (tout >= 10000) - { - //return -RT_ERROR; /* reset failed */ - rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout); - } + /* Wait for hardware reset to end. */ + for (tout = 0; tout < 10000; tout++) + { + regv = read_PHY (PHY_REG_BMCR); + if (!(regv & 0x8000)) + { + /* Reset complete */ + break; + } + } + if (tout >= 10000) + { + //return -RT_ERROR; /* reset failed */ + rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout); + } - /* Check if this is a DP83848C PHY. */ - id1 = read_PHY (PHY_REG_IDR1); - id2 = read_PHY (PHY_REG_IDR2); + /* Check if this is a DP83848C PHY. */ + id1 = read_PHY (PHY_REG_IDR1); + id2 = read_PHY (PHY_REG_IDR2); - if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) - { - // return -RT_ERROR; - rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0))); - } - else - { - /* Configure the PHY device */ - /* Configure the PHY device */ - switch (lpc17xx_emac_device.phy_mode) - { - case EMAC_PHY_AUTO: - /* Use auto negotiation about the link speed. */ - write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); - /* Wait to complete Auto_Negotiation. */ - for (tout = 0; tout < 200000; tout++) - { - regv = read_PHY (PHY_REG_BMSR); - if (regv & 0x0020) - { - /* Auto negotiation Complete. */ - break; - } - } - if(tout >= 200000) - { - rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout); - } - break; - case EMAC_PHY_10MBIT: - /* Connect at 10MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); - break; - case EMAC_PHY_100MBIT: - /* Connect at 100MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); - break; - } - } - //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed + if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) + { + // return -RT_ERROR; + rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0))); + } + else + { + /* Configure the PHY device */ + /* Configure the PHY device */ + switch (lpc17xx_emac_device.phy_mode) + { + case EMAC_PHY_AUTO: + /* Use auto negotiation about the link speed. */ + write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); + /* Wait to complete Auto_Negotiation. */ + for (tout = 0; tout < 200000; tout++) + { + regv = read_PHY (PHY_REG_BMSR); + if (regv & 0x0020) + { + /* Auto negotiation Complete. */ + break; + } + } + if(tout >= 200000) + { + rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout); + } + break; + case EMAC_PHY_10MBIT: + /* Connect at 10MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); + break; + case EMAC_PHY_100MBIT: + /* Connect at 100MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); + break; + } + } + //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed - /* Check the link status. */ - for (tout = 0; tout < 100; tout++) - { - regv = read_PHY (PHY_REG_STS); - if (regv & 0x0001) - { - /* Link is on. */ - break; - } - } - if (tout >= 100) - { - //return -RT_ERROR; - rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout); - } - /* Configure Full/Half Duplex mode. */ - if (regv & 0x0004) - { - /* Full duplex is enabled. */ - LPC_EMAC->MAC2 |= MAC2_FULL_DUP; - LPC_EMAC->Command |= CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_FULL_DUP; - } - else - { - /* Half duplex mode. */ - LPC_EMAC->IPGT = IPGT_HALF_DUP; - } + /* Check the link status. */ + for (tout = 0; tout < 100; tout++) + { + regv = read_PHY (PHY_REG_STS); + if (regv & 0x0001) + { + /* Link is on. */ + break; + } + } + if (tout >= 100) + { + //return -RT_ERROR; + rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout); + } + /* Configure Full/Half Duplex mode. */ + if (regv & 0x0004) + { + /* Full duplex is enabled. */ + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } + else + { + /* Half duplex mode. */ + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } - /* Configure 100MBit/10MBit mode. */ - if (regv & 0x0002) - { - /* 10MBit mode. */ - LPC_EMAC->SUPP = 0; - } - else - { - /* 100MBit mode. */ - LPC_EMAC->SUPP = SUPP_SPEED; - } + /* Configure 100MBit/10MBit mode. */ + if (regv & 0x0002) + { + /* 10MBit mode. */ + LPC_EMAC->SUPP = 0; + } + else + { + /* 100MBit mode. */ + LPC_EMAC->SUPP = SUPP_SPEED; + } - /* Set the Ethernet MAC Address registers */ - LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; - LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; - LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; + /* Set the Ethernet MAC Address registers */ + LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; + LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; + LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; - /* Initialize Tx and Rx DMA Descriptors */ - rx_descr_init (); - tx_descr_init (); + /* Initialize Tx and Rx DMA Descriptors */ + rx_descr_init (); + tx_descr_init (); - /* Receive Broadcast and Perfect Match Packets */ - LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; + /* Receive Broadcast and Perfect Match Packets */ + LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; - /* Reset all interrupts */ - LPC_EMAC->IntClear = 0xFFFF; + /* Reset all interrupts */ + LPC_EMAC->IntClear = 0xFFFF; - /* Enable EMAC interrupts. */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + /* Enable EMAC interrupts. */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - /* Enable receive and transmit mode of MAC Ethernet core */ - LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); - LPC_EMAC->MAC1 |= MAC1_REC_EN; + /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); + LPC_EMAC->MAC1 |= MAC1_REC_EN; - /* Enable the ENET Interrupt */ - NVIC_EnableIRQ(ENET_IRQn); + /* Enable the ENET Interrupt */ + NVIC_EnableIRQ(ENET_IRQn); - return RT_EOK; + return RT_EOK; } static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t lpc17xx_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /* EtherNet Device Interface */ /* transmit packet. */ rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_uint32_t Index, IndexNext; - struct pbuf *q; - rt_uint8_t *ptr; + rt_uint32_t Index, IndexNext; + struct pbuf *q; + rt_uint8_t *ptr; - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; - /* check whether block is full */ - while (IndexNext == LPC_EMAC->TxConsumeIndex) - { - rt_err_t result; - rt_uint32_t recved; - - /* there is no block yet, wait a flag */ - result = rt_event_recv(&tx_event, 0x01, - RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); + /* check whether block is full */ + while (IndexNext == LPC_EMAC->TxConsumeIndex) + { + rt_err_t result; + rt_uint32_t recved; - RT_ASSERT(result == RT_EOK); - } + /* there is no block yet, wait a flag */ + result = rt_event_recv(&tx_event, 0x01, + RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + } - /* get produce index */ - Index = LPC_EMAC->TxProduceIndex; + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) - IndexNext = 0; + /* get produce index */ + Index = LPC_EMAC->TxProduceIndex; - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)TX_BUF(Index); - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) + IndexNext = 0; - TX_DESC_CTRL(Index) &= ~0x7ff; - TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)TX_BUF(Index); + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } - /* change index to the next */ - LPC_EMAC->TxProduceIndex = IndexNext; + TX_DESC_CTRL(Index) &= ~0x7ff; + TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* change index to the next */ + LPC_EMAC->TxProduceIndex = IndexNext; - return RT_EOK; + /* unlock EMAC device */ + rt_sem_release(&sem_lock); + + return RT_EOK; } /* reception packet. */ struct pbuf *lpc17xx_emac_rx(rt_device_t dev) { - struct pbuf* p; - rt_uint32_t size; - rt_uint32_t Index; + struct pbuf* p; + rt_uint32_t size; + rt_uint32_t Index; - /* init p pointer */ - p = RT_NULL; + /* init p pointer */ + p = RT_NULL; - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - Index = LPC_EMAC->RxConsumeIndex; - if(Index != LPC_EMAC->RxProduceIndex) - { - size = (RX_STAT_INFO(Index) & 0x7ff)+1; - if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; + Index = LPC_EMAC->RxConsumeIndex; + if(Index != LPC_EMAC->RxProduceIndex) + { + size = (RX_STAT_INFO(Index) & 0x7ff)+1; + if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf* q; - rt_uint8_t *ptr; + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf* q; + rt_uint8_t *ptr; - ptr = (rt_uint8_t*)RX_BUF(Index); - for (q = p; q != RT_NULL; q= q->next) - { - memcpy(q->payload, ptr, q->len); - ptr += q->len; - } - } - - /* move Index to the next */ - if(++Index > LPC_EMAC->RxDescriptorNumber) - Index = 0; + ptr = (rt_uint8_t*)RX_BUF(Index); + for (q = p; q != RT_NULL; q= q->next) + { + memcpy(q->payload, ptr, q->len); + ptr += q->len; + } + } - /* set consume index */ - LPC_EMAC->RxConsumeIndex = Index; - } - else - { - /* Enable RxDone interrupt */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - } + /* move Index to the next */ + if(++Index > LPC_EMAC->RxDescriptorNumber) + Index = 0; - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* set consume index */ + LPC_EMAC->RxConsumeIndex = Index; + } + else + { + /* Enable RxDone interrupt */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + } - return p; + /* unlock EMAC device */ + rt_sem_release(&sem_lock); + + return p; } int lpc17xx_emac_hw_init(void) { - rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - /* set auto negotiation mode */ - lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; + /* set auto negotiation mode */ + lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; - // OUI 00-60-37 NXP Semiconductors - lpc17xx_emac_device.dev_addr[0] = 0x00; - lpc17xx_emac_device.dev_addr[1] = 0x60; - lpc17xx_emac_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - lpc17xx_emac_device.dev_addr[3] = 0x12; - lpc17xx_emac_device.dev_addr[4] = 0x34; - lpc17xx_emac_device.dev_addr[5] = 0x56; + // OUI 00-60-37 NXP Semiconductors + lpc17xx_emac_device.dev_addr[0] = 0x00; + lpc17xx_emac_device.dev_addr[1] = 0x60; + lpc17xx_emac_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + lpc17xx_emac_device.dev_addr[3] = 0x12; + lpc17xx_emac_device.dev_addr[4] = 0x34; + lpc17xx_emac_device.dev_addr[5] = 0x56; - lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; - lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; - lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; - lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; - lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; - lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; - lpc17xx_emac_device.parent.parent.user_data = RT_NULL; + lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; + lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; + lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; + lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; + lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; + lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; + lpc17xx_emac_device.parent.parent.user_data = RT_NULL; - lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; - lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; + lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; + lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; - eth_device_init(&(lpc17xx_emac_device.parent), "e0"); - return 0; + eth_device_init(&(lpc17xx_emac_device.parent), "e0"); + return 0; } INIT_DEVICE_EXPORT(lpc17xx_emac_hw_init); diff --git a/bsp/lpc176x/drivers/emac.h b/bsp/lpc176x/drivers/emac.h index d0edd25d63..1fc8973249 100644 --- a/bsp/lpc176x/drivers/emac.h +++ b/bsp/lpc176x/drivers/emac.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef __LPC17XX_EMAC_H #define __LPC17XX_EMAC_H @@ -11,7 +20,7 @@ #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ /* EMAC variables located in 16K Ethernet SRAM */ -#define RX_DESC_BASE 0x20080000 +#define RX_DESC_BASE 0x20080000 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) diff --git a/bsp/lpc176x/drivers/led.h b/bsp/lpc176x/drivers/led.h index 658ed16d1c..92f6ff4ffd 100644 --- a/bsp/lpc176x/drivers/led.h +++ b/bsp/lpc176x/drivers/led.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc176x/drivers/sd.c b/bsp/lpc176x/drivers/sd.c index 61e34ba43a..53b57676de 100644 --- a/bsp/lpc176x/drivers/sd.c +++ b/bsp/lpc176x/drivers/sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) { struct rt_device_blk_geometry *geometry; - + geometry = (struct rt_device_blk_geometry *)args; - + if (geometry == RT_NULL) return -RT_ERROR; if (dev->user_data == RT_NULL) return -RT_ERROR; - + geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize; geometry->block_size = ((SDCFG *)dev->user_data)->blocksize; geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt; diff --git a/bsp/lpc176x/drivers/spi.c b/bsp/lpc176x/drivers/spi.c index a6561195c5..ef328bc793 100644 --- a/bsp/lpc176x/drivers/spi.c +++ b/bsp/lpc176x/drivers/spi.c @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include "LPC17xx.h" /* LPC17xx definitions */ #include "spi.h" @@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s); /* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */ void LPC17xx_SPI_Init (void) { - uint32_t dummy; + uint32_t dummy; - dummy = dummy; // avoid warning + dummy = dummy; // avoid warning #if 0 - /* Initialize and enable the SSP0 Interface module. */ - LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */ + /* Initialize and enable the SSP0 Interface module. */ + LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */ - /* SSEL is GPIO, output set to high. */ - LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */ - LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */ - LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */ + /* SSEL is GPIO, output set to high. */ + LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */ + LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */ + LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */ - /* SCK, MISO, MOSI are SSP pins. */ - LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */ - LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */ - LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */ - LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */ + /* SCK, MISO, MOSI are SSP pins. */ + LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */ + LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */ + LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */ + LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */ #else - LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */ + LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */ - /* SSEL is GPIO, output set to high. */ - LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */ - LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/ - LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */ + /* SSEL is GPIO, output set to high. */ + LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */ + LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/ + LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */ - /* P3.26 is SD Card Power Supply Enable Pin */ - LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */ - LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */ + /* P3.26 is SD Card Power Supply Enable Pin */ + LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */ + LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */ - /* SCK, MISO, MOSI are SSP pins. */ - LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */ - LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */ - LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */ - LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */ + /* SCK, MISO, MOSI are SSP pins. */ + LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */ + LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */ + LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */ + LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */ #endif - /* PCLK_SSP0=CCLK */ - LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */ - LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */ + /* PCLK_SSP0=CCLK */ + LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */ + LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */ - LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */ - LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */ + LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */ + LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */ - LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz); + LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz); - /* wait for busy gone */ - while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) ); + /* wait for busy gone */ + while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) ); - /* drain SPI RX FIFO */ - while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) - { - dummy = LPC_SSP0->DR; - } + /* drain SPI RX FIFO */ + while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) + { + dummy = LPC_SSP0->DR; + } } /* Close SSP0 */ void LPC17xx_SPI_DeInit( void ) { - // disable SPI - LPC_SSP0->CR1 = 0; + // disable SPI + LPC_SSP0->CR1 = 0; #if 0 - // Pins to GPIO - LPC_PINCON->PINSEL0 &= ~(3UL<<30); - LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); + // Pins to GPIO + LPC_PINCON->PINSEL0 &= ~(3UL<<30); + LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); #else - LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */ - LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */ + LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */ + LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */ #endif - // disable SSP power - LPC_SC->PCONP &= ~(1 << 21); + // disable SSP power + LPC_SC->PCONP &= ~(1 << 21); } /* Set a SSP0 clock speed to desired value. */ void LPC17xx_SPI_SetSpeed (uint8_t speed) { - speed &= 0xFE; - if ( speed < 2 ) { - speed = 2 ; - } - LPC_SSP0->CPSR = speed; + speed &= 0xFE; + if ( speed < 2 ) { + speed = 2 ; + } + LPC_SSP0->CPSR = speed; } /* SSEL: low */ void LPC17xx_SPI_Select () { #if 0 - LPC_GPIO0->FIOPIN &= ~(1<<16); + LPC_GPIO0->FIOPIN &= ~(1<<16); #else - LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */ + LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */ #endif } @@ -120,41 +129,41 @@ void LPC17xx_SPI_Select () void LPC17xx_SPI_DeSelect () { #if 0 - LPC_GPIO0->FIOPIN |= (1<<16); + LPC_GPIO0->FIOPIN |= (1<<16); #else - LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */ + LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */ #endif } /* Send one byte then recv one byte of response. */ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s) { - uint8_t byte_r; + uint8_t byte_r; - LPC_SSP0->DR = byte_s; - while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */ - byte_r = LPC_SSP0->DR; + LPC_SSP0->DR = byte_s; + while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */ + byte_r = LPC_SSP0->DR; - return byte_r; /* Return received value */ + return byte_r; /* Return received value */ } /* Send one byte */ void LPC17xx_SPI_SendByte (uint8_t data) { - LPC17xx_SPI_SendRecvByte (data); + LPC17xx_SPI_SendRecvByte (data); } /* Recv one byte */ uint8_t LPC17xx_SPI_RecvByte () { - return LPC17xx_SPI_SendRecvByte (0xFF); + return LPC17xx_SPI_SendRecvByte (0xFF); } /* Release SSP0 */ void LPC17xx_SPI_Release (void) { - LPC17xx_SPI_DeSelect (); - LPC17xx_SPI_RecvByte (); + LPC17xx_SPI_DeSelect (); + LPC17xx_SPI_RecvByte (); } @@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void) #define FIFO_ELEM 8 /* Receive btr (must be multiple of 4) bytes of data and store in buff. */ -void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr) +void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr) { - uint32_t hwtr, startcnt, i, rec; + uint32_t hwtr, startcnt, i, rec; - hwtr = btr/2; /* byte number in unit of short */ - if ( btr < FIFO_ELEM ) { - startcnt = hwtr; - } else { - startcnt = FIFO_ELEM; - } + hwtr = btr/2; /* byte number in unit of short */ + if ( btr < FIFO_ELEM ) { + startcnt = hwtr; + } else { + startcnt = FIFO_ELEM; + } - LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */ + LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */ - for ( i = startcnt; i; i-- ) { - LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */ - } + for ( i = startcnt; i; i-- ) { + LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */ + } - do { - while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) { - // wait for data in RX FIFO (RNE set) - } - rec = LPC_SSP0->DR; - if ( i < ( hwtr - startcnt ) ) { - LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */ - } - *buff++ = (uint8_t)(rec>>8); - *buff++ = (uint8_t)(rec); - i++; - } while ( i < hwtr ); + do { + while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) { + // wait for data in RX FIFO (RNE set) + } + rec = LPC_SSP0->DR; + if ( i < ( hwtr - startcnt ) ) { + LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */ + } + *buff++ = (uint8_t)(rec>>8); + *buff++ = (uint8_t)(rec); + i++; + } while ( i < hwtr ); - LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */ + LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */ } /* Send 512 bytes of data block (stored in buff). */ void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff) { - uint32_t cnt; - uint16_t data; + uint32_t cnt; + uint16_t data; - LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */ + LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */ - /* fill the FIFO unless it is full */ - for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ ) - { - /* wait for TX FIFO not full (TNF) */ - while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) ); + /* fill the FIFO unless it is full */ + for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ ) + { + /* wait for TX FIFO not full (TNF) */ + while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) ); - data = (*buff++) << 8; - data |= *buff++; - LPC_SSP0->DR = data; - } + data = (*buff++) << 8; + data |= *buff++; + LPC_SSP0->DR = data; + } - /* wait for BSY gone */ - while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) ); + /* wait for BSY gone */ + while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) ); - /* drain receive FIFO */ - while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) { - data = LPC_SSP0->DR; - } + /* drain receive FIFO */ + while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) { + data = LPC_SSP0->DR; + } - LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */ + LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */ } #endif /* USE_FIFO */ diff --git a/bsp/lpc176x/drivers/spi.h b/bsp/lpc176x/drivers/spi.h index d1d9c14732..bad75d38b4 100644 --- a/bsp/lpc176x/drivers/spi.h +++ b/bsp/lpc176x/drivers/spi.h @@ -1,17 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef __LPC17XX_SPI_H__ #define __LPC17XX_SPI_H__ #include #include -// if not use FIFO, R: 600kB/s, W: 500kB/s -// if use FIFO, R: 1.2MB/s, W: 800kB/s +// if not use FIFO, R: 600kB/s, W: 500kB/s +// if use FIFO, R: 1.2MB/s, W: 800kB/s #define USE_FIFO 1 -/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */ -#define SPI_SPEED_20MHz 4 /* => 18MHz */ -#define SPI_SPEED_25MHz 4 /* => 18MHz */ -#define SPI_SPEED_400kHz 180 /* => 400kHz */ +/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */ +#define SPI_SPEED_20MHz 4 /* => 18MHz */ +#define SPI_SPEED_25MHz 4 /* => 18MHz */ +#define SPI_SPEED_400kHz 180 /* => 400kHz */ /* external functions */ void LPC17xx_SPI_Init (void); @@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data); uint8_t LPC17xx_SPI_RecvByte (void); #if USE_FIFO -void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr); +void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr); void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff); #endif -#endif // __LPC17XX_SPI_H__ +#endif // __LPC17XX_SPI_H__ diff --git a/bsp/lpc176x/drivers/uart.c b/bsp/lpc176x/drivers/uart.c index 231eccb10a..a32952124b 100644 --- a/bsp/lpc176x/drivers/uart.c +++ b/bsp/lpc176x/drivers/uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -56,8 +56,8 @@ void UART0_IRQHandler(void) { rt_ubase_t level, iir; struct rt_uart_lpc *uart = &uart_device; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); /* read IIR and clear it */ iir = LPC_UART->IIR; @@ -91,8 +91,8 @@ void UART0_IRQHandler(void) { iir = LPC_UART->LSR; //oe pe fe oe read for clear interrupt } - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); return; } diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h index 6b28d64d32..5096b2f71d 100644 --- a/bsp/lpc176x/rtconfig.h +++ b/bsp/lpc176x/rtconfig.h @@ -4,17 +4,17 @@ // // -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
#define RT_DEBUG #define RT_DEBUG_COLOR @@ -29,11 +29,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -67,15 +67,15 @@ // #define RT_USING_UART0 // -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 //
//
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" //
// @@ -87,7 +87,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -102,16 +102,16 @@ // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // // 932 // 936 @@ -142,7 +142,7 @@ // #define RT_DFS_ELM_CODE_PAGE 437 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -152,7 +152,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -168,29 +168,29 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_PBUF_NUM 4 +#define RT_LWIP_PBUF_NUM 4 // -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_LWIP_TCP_PCB_NUM 3 // -#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS) +#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS) // -#define RT_LWIP_TCP_WND 2048 +#define RT_LWIP_TCP_WND 2048 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR "192.168.1.30" // diff --git a/bsp/lpc178x/applications/application.c b/bsp/lpc178x/applications/application.c index 9780d42154..b4f437405b 100644 --- a/bsp/lpc178x/applications/application.c +++ b/bsp/lpc178x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter) #ifdef RT_USING_RTGUI { - extern void rtgui_system_server_init(void); - extern void application_init(void); + extern void rtgui_system_server_init(void); + extern void application_init(void); - rt_device_t lcd; + rt_device_t lcd; - /* init lcd */ - rt_hw_lcd_init(); + /* init lcd */ + rt_hw_lcd_init(); - /* find lcd device */ - lcd = rt_device_find("lcd"); - if (lcd != RT_NULL) - { - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); + /* find lcd device */ + lcd = rt_device_find("lcd"); + if (lcd != RT_NULL) + { + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); - /* init rtgui system server */ - rtgui_system_server_init(); + /* init rtgui system server */ + rtgui_system_server_init(); - /* startup rtgui in demo of RT-Thread/GUI examples */ - application_init(); - } + /* startup rtgui in demo of RT-Thread/GUI examples */ + application_init(); + } } #endif #ifdef RT_USING_FINSH - /* initialize finsh */ - finsh_system_init(); + /* initialize finsh */ + finsh_system_init(); #endif } @@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter) int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - rt_thread_init(&thread_led, - "led", - rt_thread_entry_led, - RT_NULL, - &thread_led_stack[0], - sizeof(thread_led_stack),11,5); - rt_thread_startup(&thread_led); + rt_thread_init(&thread_led, + "led", + rt_thread_entry_led, + RT_NULL, + &thread_led_stack[0], + sizeof(thread_led_stack),11,5); + rt_thread_startup(&thread_led); - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) rt_thread_startup(tid); + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) rt_thread_startup(tid); - return 0; + return 0; } #if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH) @@ -170,20 +170,20 @@ int rt_application_init(void) void key(rt_uint32_t key) { - struct rtgui_event_kbd ekbd; + struct rtgui_event_kbd ekbd; - RTGUI_EVENT_KBD_INIT(&ekbd); - ekbd.mod = RTGUI_KMOD_NONE; - ekbd.unicode = 0; - ekbd.key = key; + RTGUI_EVENT_KBD_INIT(&ekbd); + ekbd.mod = RTGUI_KMOD_NONE; + ekbd.unicode = 0; + ekbd.key = key; - ekbd.type = RTGUI_KEYDOWN; - rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); + ekbd.type = RTGUI_KEYDOWN; + rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); - rt_thread_delay(2); + rt_thread_delay(2); - ekbd.type = RTGUI_KEYUP; - rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); + ekbd.type = RTGUI_KEYUP; + rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd)); } FINSH_FUNCTION_EXPORT(key, send a key to gui server); #endif diff --git a/bsp/lpc178x/applications/startup.c b/bsp/lpc178x/applications/startup.c index 07698574b5..8b25e7d405 100644 --- a/bsp/lpc178x/applications/startup.c +++ b/bsp/lpc178x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,11 +37,11 @@ extern int __bss_end; *******************************************************************************/ void assert_failed(u8* file, u32 line) { - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); - while (1) ; + while (1) ; } #endif @@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line) */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - /* initialize memory system */ - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64)); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64)); - #else - rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64)); - #endif + /* initialize memory system */ + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64)); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64)); + #else + rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64)); + #endif #endif - /* initialize scheduler system */ - rt_system_scheduler_init(); + /* initialize scheduler system */ + rt_system_scheduler_init(); - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); @@ -79,23 +79,23 @@ void rtthread_startup(void) /* initialize timer thread */ rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c index df06d7f2f8..c07150e525 100644 --- a/bsp/lpc178x/drivers/board.c +++ b/bsp/lpc178x/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h index 1a6d82e4b7..3c0a7fad71 100644 --- a/bsp/lpc178x/drivers/board.h +++ b/bsp/lpc178x/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ //#define RT_USING_UART2 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" // diff --git a/bsp/lpc178x/drivers/drv_glcd.c b/bsp/lpc178x/drivers/drv_glcd.c index ba02efeb67..6fa9c7b84e 100644 --- a/bsp/lpc178x/drivers/drv_glcd.c +++ b/bsp/lpc178x/drivers/drv_glcd.c @@ -37,14 +37,14 @@ #define C_GLCD_LINES_PER_FRAME (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH) #define C_GLCD_PIX_CLK (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME) -//LPC_LCD_TypeDef * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE); +//LPC_LCD_TypeDef * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE); //LPC_SC_TypeDef * const g_pSC = ((LPC_SC_TypeDef*) LPC_SC_BASE); -#define SDRAM_BASE 0xA0000000 /* CS0 */ -#define SDRAM_BASE_ADDR SDRAM_BASE +#define SDRAM_BASE 0xA0000000 /* CS0 */ +#define SDRAM_BASE_ADDR SDRAM_BASE -#define LCD_VRAM_BASE_ADDR ((unsigned long)SDRAM_BASE_ADDR + 0x00000000) -#define LCD_CURSOR_BASE_ADDR ((unsigned long)0x20088800) +#define LCD_VRAM_BASE_ADDR ((unsigned long)SDRAM_BASE_ADDR + 0x00000000) +#define LCD_CURSOR_BASE_ADDR ((unsigned long)0x20088800) static pFontType_t pCurrFont = NULL; @@ -155,18 +155,18 @@ void GLCD_Move_Cursor(int x, int y) *************************************************************************/ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size) { - unsigned long i ; - unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR; + unsigned long i ; + unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR; - pDst += cursor*64; + pDst += cursor*64; - for(i = 0; i < size ; i++) -// *pDst++ = *pCursor++; - { - *pDst = *pCursor; - pDst++; - pCursor++; - } + for(i = 0; i < size ; i++) +// *pDst++ = *pCursor++; + { + *pDst = *pCursor; + pDst++; + pCursor++; + } } /************************************************************************* * Function Name: GLCD_Init @@ -179,101 +179,101 @@ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size) *************************************************************************/ void GLCD_Init (void* VRAMBase) { - // unsigned long i; - // Assign pins - LPC_IOCON->P2_9 = 0x06; // VD3, R0 - LPC_IOCON->P2_6 = 0x07; // VD4, R1 - LPC_IOCON->P2_7 = 0x07; // VD5, R2 - LPC_IOCON->P4_28 = 0x05; // VD6, R3 - LPC_IOCON->P4_29 = 0x05; // VD7, R4 + // unsigned long i; + // Assign pins + LPC_IOCON->P2_9 = 0x06; // VD3, R0 + LPC_IOCON->P2_6 = 0x07; // VD4, R1 + LPC_IOCON->P2_7 = 0x07; // VD5, R2 + LPC_IOCON->P4_28 = 0x05; // VD6, R3 + LPC_IOCON->P4_29 = 0x05; // VD7, R4 - LPC_IOCON->P1_20 = 0x07; // VD10, G0 - LPC_IOCON->P1_21 = 0x07; // VD11, G1 - LPC_IOCON->P1_22 = 0x07; // VD12, G2 - LPC_IOCON->P1_23 = 0x07; // VD13, G3 - LPC_IOCON->P1_24 = 0x07; // VD14, G4 - LPC_IOCON->P1_25 = 0x07; // VD15, G5 + LPC_IOCON->P1_20 = 0x07; // VD10, G0 + LPC_IOCON->P1_21 = 0x07; // VD11, G1 + LPC_IOCON->P1_22 = 0x07; // VD12, G2 + LPC_IOCON->P1_23 = 0x07; // VD13, G3 + LPC_IOCON->P1_24 = 0x07; // VD14, G4 + LPC_IOCON->P1_25 = 0x07; // VD15, G5 - LPC_IOCON->P2_13 = 0x07; // VD19, B0 - LPC_IOCON->P1_26 = 0x07; // VD20, B1 - LPC_IOCON->P1_27 = 0x07; // VD21, B2 - LPC_IOCON->P1_28 = 0x07; // VD22, B3 - LPC_IOCON->P1_29 = 0x07; // VD23, B4 + LPC_IOCON->P2_13 = 0x07; // VD19, B0 + LPC_IOCON->P1_26 = 0x07; // VD20, B1 + LPC_IOCON->P1_27 = 0x07; // VD21, B2 + LPC_IOCON->P1_28 = 0x07; // VD22, B3 + LPC_IOCON->P1_29 = 0x07; // VD23, B4 - LPC_IOCON->P2_2 = 0x07; // DCLK - LPC_IOCON->P2_0 = 0x07; // DSIP(power) - LPC_IOCON->P2_5 = 0x07; // HSYNC - LPC_IOCON->P2_3 = 0x07; // VSYNC - LPC_IOCON->P2_4 = 0x07; // DataEn + LPC_IOCON->P2_2 = 0x07; // DCLK + LPC_IOCON->P2_0 = 0x07; // DSIP(power) + LPC_IOCON->P2_5 = 0x07; // HSYNC + LPC_IOCON->P2_3 = 0x07; // VSYNC + LPC_IOCON->P2_4 = 0x07; // DataEn -// LPC_IOCON->P5_4 = 0x00; // Backlight +// LPC_IOCON->P5_4 = 0x00; // Backlight - // >>> debug >>> + // >>> debug >>> - // <<< debug <<< + // <<< debug <<< - /*Back light enable*/ -// LPC_GPIO5->DIR = (1<<4); -// LPC_GPIO5->SET= (5<<4); + /*Back light enable*/ +// LPC_GPIO5->DIR = (1<<4); +// LPC_GPIO5->SET= (5<<4); - //Turn on LCD clock - CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE); + //Turn on LCD clock + CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE); - // Disable cursor - LPC_LCD->CRSR_CTRL &=~(1<<0); + // Disable cursor + LPC_LCD->CRSR_CTRL &=~(1<<0); - // disable GLCD controller - LPC_LCD->CTRL = 0; - // RGB888 - LPC_LCD->CTRL &= ~(0x07 <<1); - LPC_LCD->CTRL |= (6<<1); + // disable GLCD controller + LPC_LCD->CTRL = 0; + // RGB888 + LPC_LCD->CTRL &= ~(0x07 <<1); + LPC_LCD->CTRL |= (6<<1); - // TFT panel - LPC_LCD->CTRL |= (1<<5); - // single panel - LPC_LCD->CTRL &= ~(1<<7); - // notmal output - LPC_LCD->CTRL &= ~(1<<8); - // little endian byte order - LPC_LCD->CTRL &= ~(1<<9); - // little endian pix order - LPC_LCD->CTRL &= ~(1<<10); - // disable power - LPC_LCD->CTRL &= ~(1<<11); - // init pixel clock -// g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK); - LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK); - // bypass inrenal clk divider - LPC_LCD->POL |=(1<<26); - // clock source for the LCD block is HCLK - LPC_LCD->POL &= ~(1<<5); - // LCDFP pin is active LOW and inactive HIGH - LPC_LCD->POL |= (1<<11); - // LCDLP pin is active LOW and inactive HIGH - LPC_LCD->POL |= (1<<12); - // data is driven out into the LCD on the falling edge - LPC_LCD->POL &= ~(1<<13); - // active high - LPC_LCD->POL &= ~(1<<14); - LPC_LCD->POL &= ~(0x3FF <<16); - LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16; + // TFT panel + LPC_LCD->CTRL |= (1<<5); + // single panel + LPC_LCD->CTRL &= ~(1<<7); + // notmal output + LPC_LCD->CTRL &= ~(1<<8); + // little endian byte order + LPC_LCD->CTRL &= ~(1<<9); + // little endian pix order + LPC_LCD->CTRL &= ~(1<<10); + // disable power + LPC_LCD->CTRL &= ~(1<<11); + // init pixel clock +// g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK); + LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK); + // bypass inrenal clk divider + LPC_LCD->POL |=(1<<26); + // clock source for the LCD block is HCLK + LPC_LCD->POL &= ~(1<<5); + // LCDFP pin is active LOW and inactive HIGH + LPC_LCD->POL |= (1<<11); + // LCDLP pin is active LOW and inactive HIGH + LPC_LCD->POL |= (1<<12); + // data is driven out into the LCD on the falling edge + LPC_LCD->POL &= ~(1<<13); + // active high + LPC_LCD->POL &= ~(1<<14); + LPC_LCD->POL &= ~(0x3FF <<16); + LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16; - // init Horizontal Timing - LPC_LCD->TIMH = 0; //reset TIMH before set value - LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24; - LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16; - LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8; - LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2; + // init Horizontal Timing + LPC_LCD->TIMH = 0; //reset TIMH before set value + LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24; + LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16; + LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8; + LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2; - // init Vertical Timing - LPC_LCD->TIMV = 0; //reset TIMV value before setting - LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24; - LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16; - LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10; - LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1; - // Frame Base Address doubleword aligned - LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ; - LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ; + // init Vertical Timing + LPC_LCD->TIMV = 0; //reset TIMV value before setting + LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24; + LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16; + LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10; + LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1; + // Frame Base Address doubleword aligned + LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ; + LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ; } /************************************************************************* @@ -287,13 +287,13 @@ void GLCD_Init (void* VRAMBase) *************************************************************************/ void GLCD_SetPallet (const unsigned long * pPallete) { - unsigned long i; - unsigned long * pDst = (unsigned long *)LPC_LCD->PAL; - // //assert(pPallete); - for (i = 0; i < 128; i++) - { - *pDst++ = *pPallete++; - } + unsigned long i; + unsigned long * pDst = (unsigned long *)LPC_LCD->PAL; + // //assert(pPallete); + for (i = 0; i < 128; i++) + { + *pDst++ = *pPallete++; + } } /************************************************************************* @@ -307,7 +307,7 @@ void GLCD_SetPallet (const unsigned long * pPallete) *************************************************************************/ void GLCD_Ctrl (Bool bEna) { - volatile unsigned long i; + volatile unsigned long i; if (bEna) { // LCD_CTRL_bit.LcdEn = 1; @@ -473,7 +473,7 @@ Bool GLCD_TextCalcWindow (unsigned long * pXL, unsigned long * pXR, *pXR = XL_Win + ((TextX_Pos+1)*pCurrFont->H_Size) - 1; if(*pXR > XR_Win) { - *pH_Size -= *pXR - XR_Win; + *pH_Size -= *pXR - XR_Win; *pXR = XR_Win; } @@ -514,19 +514,19 @@ unsigned long i, j, k; ++TextY_Pos; break; case '\r': // go to begin of this line (Carriage Return) - // clear from current position to end of line - while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) - { + // clear from current position to end of line + while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) + { LCD_SET_WINDOW(xl,xr,yu,yd); - for(i = 0; i < V_Size; ++i) - { - for(j = 0; j < H_Size; ++j) - { - LCD_WRITE_PIXEL(TextBackgndColour); - } - } - ++TextX_Pos; - } + for(i = 0; i < V_Size; ++i) + { + for(j = 0; j < H_Size; ++j) + { + LCD_WRITE_PIXEL(TextBackgndColour); + } + } + ++TextX_Pos; + } TextX_Pos = 0; break; case '\b': // go back one position (BackSpace) @@ -534,45 +534,45 @@ unsigned long i, j, k; { --TextX_Pos; // del current position - if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) - { + if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) + { LCD_SET_WINDOW(xl,xr,yu,yd); - for(i = 0; i < V_Size; ++i) - { - for(j = 0; j < H_Size; ++j) - { - LCD_WRITE_PIXEL(TextBackgndColour); - } - } - } + for(i = 0; i < V_Size; ++i) + { + for(j = 0; j < H_Size; ++j) + { + LCD_WRITE_PIXEL(TextBackgndColour); + } + } + } } break; case '\t': // go to next Horizontal Tab stop - WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize); - for(k = 0; k < WhiteSpaceNumb; ++k) - { + WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize); + for(k = 0; k < WhiteSpaceNumb; ++k) + { LCD_SET_WINDOW(xl,xr,yu,yd); - if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) - { - for(i = 0; i < V_Size; ++i) - { - for(j = 0; j < H_Size; ++j) - { - LCD_WRITE_PIXEL(TextBackgndColour); - } - } - ++TextX_Pos; - } - else - { - break; - } - } + if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) + { + for(i = 0; i < V_Size; ++i) + { + for(j = 0; j < H_Size; ++j) + { + LCD_WRITE_PIXEL(TextBackgndColour); + } + } + ++TextX_Pos; + } + else + { + break; + } + } break; case '\f': // go to top of page (Form Feed) - // clear entire window - H_Size = XR_Win - XL_Win; - V_Size = YD_Win - YU_Win; + // clear entire window + H_Size = XR_Win - XL_Win; + V_Size = YD_Win - YU_Win; // set character window X left, Y right LCD_SET_WINDOW(XL_Win,XR_Win,YU_Win,YD_Win); // Fill window with background font color @@ -584,7 +584,7 @@ unsigned long i, j, k; } } - TextX_Pos = TextY_Pos = 0; + TextX_Pos = TextY_Pos = 0; break; case '\a': // signal an alert (BELl) TEXT_BEL1_FUNC(); @@ -593,37 +593,37 @@ unsigned long i, j, k; // Calculate the current character base address from stream // and the character position if((c < pCurrFont->CharacterOffset) && - (c >= pCurrFont->CharactersNuber)) - { - c = 0; + (c >= pCurrFont->CharactersNuber)) + { + c = 0; } else { - c -= pCurrFont->CharacterOffset; + c -= pCurrFont->CharacterOffset; } pSrc = pCurrFont->pFontStream + (H_Line * pCurrFont->V_Size * c); // Calculate character window and fit it in the text window if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size)) { - // set character window X left, Y right - LCD_SET_WINDOW(xl,xr,yu,yd); - // Send char data - for(i = 0; i < V_Size; ++i) - { + // set character window X left, Y right + LCD_SET_WINDOW(xl,xr,yu,yd); + // Send char data + for(i = 0; i < V_Size; ++i) + { SrcInc = H_Line; for(j = 0; j < H_Size; ++j) - { - Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour; - LCD_WRITE_PIXEL(Temp); - if((j&0x7) == 7) - { - ++pSrc; + { + Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour; + LCD_WRITE_PIXEL(Temp); + if((j&0x7) == 7) + { + ++pSrc; --SrcInc; - } - } + } + } // next line of character - pSrc += SrcInc; - } + pSrc += SrcInc; + } } ++TextX_Pos; } diff --git a/bsp/lpc178x/drivers/drv_glcd.h b/bsp/lpc178x/drivers/drv_glcd.h index 1453bd4782..5a28ceb6b3 100644 --- a/bsp/lpc178x/drivers/drv_glcd.h +++ b/bsp/lpc178x/drivers/drv_glcd.h @@ -33,7 +33,7 @@ typedef unsigned long Boolean; /** * @brief A struct for Bitmap on LCD screen */ -typedef struct _Bmp_t +typedef struct _Bmp_t { U32 H_Size; U32 V_Size; @@ -47,8 +47,8 @@ typedef struct _Bmp_t /** * @brief A struct for Font Type on LCD screen */ - -typedef struct _FontType_t + +typedef struct _FontType_t { U32 H_Size; U32 V_Size; @@ -62,9 +62,9 @@ typedef U32 LdcPixel_t, *pLdcPixel_t; #define C_GLCD_REFRESH_FREQ (60HZ) #define C_GLCD_H_SIZE 480 -#define C_GLCD_H_PULSE 2 // -#define C_GLCD_H_FRONT_PORCH 5 // -#define C_GLCD_H_BACK_PORCH 40 // +#define C_GLCD_H_PULSE 2 // +#define C_GLCD_H_FRONT_PORCH 5 // +#define C_GLCD_H_BACK_PORCH 40 // #define C_GLCD_V_SIZE 272 #define C_GLCD_V_PULSE 2 #define C_GLCD_V_FRONT_PORCH 8 diff --git a/bsp/lpc178x/drivers/emac.c b/bsp/lpc178x/drivers/emac.c index a16dc49770..ec48ea8833 100644 --- a/bsp/lpc178x/drivers/emac.c +++ b/bsp/lpc178x/drivers/emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,20 @@ #include "lwipopts.h" #include -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 -#define EMAC_PHY_100MBIT 2 +#define EMAC_PHY_AUTO 0 +#define EMAC_PHY_10MBIT 1 +#define EMAC_PHY_100MBIT 2 #define MAX_ADDR_LEN 6 struct lpc17xx_emac { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - rt_uint8_t phy_mode; + rt_uint8_t phy_mode; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct lpc17xx_emac lpc17xx_emac_device; static struct rt_semaphore sem_lock; @@ -39,39 +39,39 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ; void ENET_IRQHandler(void) { - rt_uint32_t status; + rt_uint32_t status; /* enter interrupt */ rt_interrupt_enter(); - status = LPC_EMAC->IntStatus; + status = LPC_EMAC->IntStatus; - if (status & INT_RX_DONE) - { - /* Disable EMAC RxDone interrupts. */ - LPC_EMAC->IntEnable = INT_TX_DONE; + if (status & INT_RX_DONE) + { + /* Disable EMAC RxDone interrupts. */ + LPC_EMAC->IntEnable = INT_TX_DONE; - /* a frame has been received */ - eth_device_ready(&(lpc17xx_emac_device.parent)); - } - else if (status & INT_TX_DONE) - { - /* set event */ - rt_event_send(&tx_event, 0x01); - } + /* a frame has been received */ + eth_device_ready(&(lpc17xx_emac_device.parent)); + } + else if (status & INT_TX_DONE) + { + /* set event */ + rt_event_send(&tx_event, 0x01); + } - if (status & INT_RX_OVERRUN) - { - rt_kprintf("rx overrun\n"); - } + if (status & INT_RX_OVERRUN) + { + rt_kprintf("rx overrun\n"); + } - if (status & INT_TX_UNDERRUN) - { - rt_kprintf("tx underrun\n"); - } + if (status & INT_TX_UNDERRUN) + { + rt_kprintf("tx underrun\n"); + } - /* Clear the interrupt. */ - LPC_EMAC->IntClear = status; + /* Clear the interrupt. */ + LPC_EMAC->IntClear = status; /* leave interrupt */ rt_interrupt_leave(); @@ -80,84 +80,84 @@ void ENET_IRQHandler(void) /* phy write */ static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value) { - unsigned int tout; + unsigned int tout; - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MWTD = Value; + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Value; - /* Wait utill operation completed */ - tout = 0; - for (tout = 0; tout < MII_WR_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } + /* Wait utill operation completed */ + tout = 0; + for (tout = 0; tout < MII_WR_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } } /* phy read */ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) { - rt_uint32_t tout; + rt_uint32_t tout; - LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; - LPC_EMAC->MCMD = MCMD_READ; + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; - /* Wait until operation completed */ - tout = 0; - for (tout = 0; tout < MII_RD_TOUT; tout++) - { - if ((LPC_EMAC->MIND & MIND_BUSY) == 0) - { - break; - } - } - LPC_EMAC->MCMD = 0; - return (LPC_EMAC->MRDD); + /* Wait until operation completed */ + tout = 0; + for (tout = 0; tout < MII_RD_TOUT; tout++) + { + if ((LPC_EMAC->MIND & MIND_BUSY) == 0) + { + break; + } + } + LPC_EMAC->MCMD = 0; + return (LPC_EMAC->MRDD); } /* init rx descriptor */ rt_inline void rx_descr_init (void) { - rt_uint32_t i; + rt_uint32_t i; - for (i = 0; i < NUM_RX_FRAG; i++) - { - RX_DESC_PACKET(i) = RX_BUF(i); - RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); - RX_STAT_INFO(i) = 0; - RX_STAT_HASHCRC(i) = 0; - } + for (i = 0; i < NUM_RX_FRAG; i++) + { + RX_DESC_PACKET(i) = RX_BUF(i); + RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); + RX_STAT_INFO(i) = 0; + RX_STAT_HASHCRC(i) = 0; + } - /* Set EMAC Receive Descriptor Registers. */ - LPC_EMAC->RxDescriptor = RX_DESC_BASE; - LPC_EMAC->RxStatus = RX_STAT_BASE; - LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxDescriptor = RX_DESC_BASE; + LPC_EMAC->RxStatus = RX_STAT_BASE; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; - /* Rx Descriptors Point to 0 */ - LPC_EMAC->RxConsumeIndex = 0; + /* Rx Descriptors Point to 0 */ + LPC_EMAC->RxConsumeIndex = 0; } /* init tx descriptor */ rt_inline void tx_descr_init (void) { - rt_uint32_t i; + rt_uint32_t i; - for (i = 0; i < NUM_TX_FRAG; i++) - { - TX_DESC_PACKET(i) = TX_BUF(i); - TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); - TX_STAT_INFO(i) = 0; - } + for (i = 0; i < NUM_TX_FRAG; i++) + { + TX_DESC_PACKET(i) = TX_BUF(i); + TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1); + TX_STAT_INFO(i) = 0; + } - /* Set EMAC Transmit Descriptor Registers. */ - LPC_EMAC->TxDescriptor = TX_DESC_BASE; - LPC_EMAC->TxStatus = TX_STAT_BASE; - LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxDescriptor = TX_DESC_BASE; + LPC_EMAC->TxStatus = TX_STAT_BASE; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; - /* Tx Descriptors Point to 0 */ - LPC_EMAC->TxProduceIndex = 0; + /* Tx Descriptors Point to 0 */ + LPC_EMAC->TxProduceIndex = 0; } /* @@ -178,375 +178,375 @@ REF_CLK P1_15 */ static rt_err_t lpc17xx_emac_init(rt_device_t dev) { - /* Initialize the EMAC ethernet controller. */ - rt_uint32_t regv, tout; + /* Initialize the EMAC ethernet controller. */ + rt_uint32_t regv, tout; - /* Power Up the EMAC controller. */ - LPC_SC->PCONP |= (1UL<<30); + /* Power Up the EMAC controller. */ + LPC_SC->PCONP |= (1UL<<30); - /* config RESET */ - PINSEL_ConfigPin(3, 19, 0); - PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN); - LPC_GPIO3->DIR |= 1<<19; - LPC_GPIO3->CLR = 1<<19; + /* config RESET */ + PINSEL_ConfigPin(3, 19, 0); + PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN); + LPC_GPIO3->DIR |= 1<<19; + LPC_GPIO3->CLR = 1<<19; - /* Enable P1 Ethernet Pins. */ - PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */ - PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */ - PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */ - PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */ - PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */ - PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */ - PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */ - PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */ - PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */ - PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */ + /* Enable P1 Ethernet Pins. */ + PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */ + PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */ + PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */ + PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */ + PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */ + PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */ + PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */ + PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */ + PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */ + PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */ - LPC_GPIO3->SET = 1<<19; + LPC_GPIO3->SET = 1<<19; - /* Reset all EMAC internal modules. */ - LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | - MAC1_SIM_RES | MAC1_SOFT_RES; - LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | + MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; - /* A short delay after reset. */ - for (tout = 100; tout; tout--); + /* A short delay after reset. */ + for (tout = 100; tout; tout--); - /* Initialize MAC control registers. */ - LPC_EMAC->MAC1 = MAC1_PASS_ALL; - LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; - LPC_EMAC->MAXF = ETH_MAX_FLEN; - LPC_EMAC->CLRT = CLRT_DEF; - LPC_EMAC->IPGR = IPGR_DEF; + /* Initialize MAC control registers. */ + LPC_EMAC->MAC1 = MAC1_PASS_ALL; + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; - /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ - /* Enable Reduced MII interface. */ - LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; - for (tout = 100; tout; tout--); - LPC_EMAC->MCFG = MCFG_CLK_DIV20; + /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ + /* Enable Reduced MII interface. */ + LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII; + for (tout = 100; tout; tout--); + LPC_EMAC->MCFG = MCFG_CLK_DIV20; - /* Enable Reduced MII interface. */ - LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; + /* Enable Reduced MII interface. */ + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT; - /* Reset Reduced MII Logic. */ - LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; - for (tout = 100; tout; tout--); - LPC_EMAC->SUPP = SUPP_SPEED; + /* Reset Reduced MII Logic. */ + LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED; + for (tout = 100; tout; tout--); + LPC_EMAC->SUPP = SUPP_SPEED; - /* Put the PHY in reset mode */ - write_PHY (PHY_REG_BMCR, 0x8000); - for (tout = 1000; tout; tout--); + /* Put the PHY in reset mode */ + write_PHY (PHY_REG_BMCR, 0x8000); + for (tout = 1000; tout; tout--); -// /* Wait for hardware reset to end. */ -// for (tout = 0; tout < 0x100000; tout++) -// { -// regv = read_PHY (PHY_REG_BMCR); -// if (!(regv & 0x8000)) -// { -// /* Reset complete */ -// break; -// } -// } -// if (tout >= 0x100000) +// /* Wait for hardware reset to end. */ +// for (tout = 0; tout < 0x100000; tout++) +// { +// regv = read_PHY (PHY_REG_BMCR); +// if (!(regv & 0x8000)) +// { +// /* Reset complete */ +// break; +// } +// } +// if (tout >= 0x100000) // { // rt_kprintf("reset failed\r\n"); // return -RT_ERROR; /* reset failed */ // } -// /* Check if this is a DP83848C PHY. */ -// id1 = read_PHY (PHY_REG_IDR1); -// id2 = read_PHY (PHY_REG_IDR2); +// /* Check if this is a DP83848C PHY. */ +// id1 = read_PHY (PHY_REG_IDR1); +// id2 = read_PHY (PHY_REG_IDR2); // -// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) -// return -RT_ERROR; +// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID) +// return -RT_ERROR; - /* Configure the PHY device */ - /* Configure the PHY device */ - switch (lpc17xx_emac_device.phy_mode) - { - case EMAC_PHY_AUTO: - /* Use autonegotiation about the link speed. */ - write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); - /* Wait to complete Auto_Negotiation. */ -// for (tout = 0; tout < 0x100000; tout++) -// { -// regv = read_PHY (PHY_REG_BMSR); -// if (regv & 0x0020) -// { -// /* Autonegotiation Complete. */ -// break; -// } -// } - break; - case EMAC_PHY_10MBIT: - /* Connect at 10MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); - break; - case EMAC_PHY_100MBIT: - /* Connect at 100MBit */ - write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); - break; - } - if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed + /* Configure the PHY device */ + /* Configure the PHY device */ + switch (lpc17xx_emac_device.phy_mode) + { + case EMAC_PHY_AUTO: + /* Use autonegotiation about the link speed. */ + write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); + /* Wait to complete Auto_Negotiation. */ +// for (tout = 0; tout < 0x100000; tout++) +// { +// regv = read_PHY (PHY_REG_BMSR); +// if (regv & 0x0020) +// { +// /* Autonegotiation Complete. */ +// break; +// } +// } + break; + case EMAC_PHY_10MBIT: + /* Connect at 10MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_10M); + break; + case EMAC_PHY_100MBIT: + /* Connect at 100MBit */ + write_PHY (PHY_REG_BMCR, PHY_FULLD_100M); + break; + } + if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed -// /* Check the link status. */ -// for (tout = 0; tout < 0x10000; tout++) -// { -// regv = read_PHY (PHY_REG_STS); -// if (regv & 0x0001) -// { -// /* Link is on. */ -// break; -// } -// } -// if (tout >= 0x10000) return -RT_ERROR; +// /* Check the link status. */ +// for (tout = 0; tout < 0x10000; tout++) +// { +// regv = read_PHY (PHY_REG_STS); +// if (regv & 0x0001) +// { +// /* Link is on. */ +// break; +// } +// } +// if (tout >= 0x10000) return -RT_ERROR; - regv = 0x0004; - /* Configure Full/Half Duplex mode. */ - if (regv & 0x0004) - { - /* Full duplex is enabled. */ - LPC_EMAC->MAC2 |= MAC2_FULL_DUP; - LPC_EMAC->Command |= CR_FULL_DUP; - LPC_EMAC->IPGT = IPGT_FULL_DUP; - } - else - { - /* Half duplex mode. */ - LPC_EMAC->IPGT = IPGT_HALF_DUP; - } + regv = 0x0004; + /* Configure Full/Half Duplex mode. */ + if (regv & 0x0004) + { + /* Full duplex is enabled. */ + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } + else + { + /* Half duplex mode. */ + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } - /* Configure 100MBit/10MBit mode. */ - if (regv & 0x0002) - { - /* 10MBit mode. */ - LPC_EMAC->SUPP = 0; - } - else - { - /* 100MBit mode. */ - LPC_EMAC->SUPP = SUPP_SPEED; - } + /* Configure 100MBit/10MBit mode. */ + if (regv & 0x0002) + { + /* 10MBit mode. */ + LPC_EMAC->SUPP = 0; + } + else + { + /* 100MBit mode. */ + LPC_EMAC->SUPP = SUPP_SPEED; + } - /* Set the Ethernet MAC Address registers */ - LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; - LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; - LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; + /* Set the Ethernet MAC Address registers */ + LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0]; + LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2]; + LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4]; - /* Initialize Tx and Rx DMA Descriptors */ - rx_descr_init (); - tx_descr_init (); + /* Initialize Tx and Rx DMA Descriptors */ + rx_descr_init (); + tx_descr_init (); - /* Receive Broadcast and Perfect Match Packets */ - LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; + /* Receive Broadcast and Perfect Match Packets */ + LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN; - /* Reset all interrupts */ - LPC_EMAC->IntClear = 0xFFFF; + /* Reset all interrupts */ + LPC_EMAC->IntClear = 0xFFFF; - /* Enable EMAC interrupts. */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + /* Enable EMAC interrupts. */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - /* Enable receive and transmit mode of MAC Ethernet core */ - LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); - LPC_EMAC->MAC1 |= MAC1_REC_EN; + /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); + LPC_EMAC->MAC1 |= MAC1_REC_EN; - /* Enable the ENET Interrupt */ - NVIC_EnableIRQ(ENET_IRQn); + /* Enable the ENET Interrupt */ + NVIC_EnableIRQ(ENET_IRQn); - return RT_EOK; + return RT_EOK; } static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t lpc17xx_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /* EtherNet Device Interface */ /* transmit packet. */ rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_uint32_t Index, IndexNext; - struct pbuf *q; - rt_uint8_t *ptr; + rt_uint32_t Index, IndexNext; + struct pbuf *q; + rt_uint8_t *ptr; - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0; - /* check whether block is full */ - while (IndexNext == LPC_EMAC->TxConsumeIndex) - { - rt_err_t result; - rt_uint32_t recved; + /* check whether block is full */ + while (IndexNext == LPC_EMAC->TxConsumeIndex) + { + rt_err_t result; + rt_uint32_t recved; - /* there is no block yet, wait a flag */ - result = rt_event_recv(&tx_event, 0x01, - RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); + /* there is no block yet, wait a flag */ + result = rt_event_recv(&tx_event, 0x01, + RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved); - RT_ASSERT(result == RT_EOK); - } + RT_ASSERT(result == RT_EOK); + } - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - /* get produce index */ - Index = LPC_EMAC->TxProduceIndex; + /* get produce index */ + Index = LPC_EMAC->TxProduceIndex; - /* calculate next index */ - IndexNext = LPC_EMAC->TxProduceIndex + 1; - if(IndexNext > LPC_EMAC->TxDescriptorNumber) - IndexNext = 0; + /* calculate next index */ + IndexNext = LPC_EMAC->TxProduceIndex + 1; + if(IndexNext > LPC_EMAC->TxDescriptorNumber) + IndexNext = 0; - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)TX_BUF(Index); - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)TX_BUF(Index); + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } - TX_DESC_CTRL(Index) &= ~0x7ff; - TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; + TX_DESC_CTRL(Index) &= ~0x7ff; + TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff; - /* change index to the next */ - LPC_EMAC->TxProduceIndex = IndexNext; + /* change index to the next */ + LPC_EMAC->TxProduceIndex = IndexNext; - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* unlock EMAC device */ + rt_sem_release(&sem_lock); - return RT_EOK; + return RT_EOK; } /* reception packet. */ struct pbuf *lpc17xx_emac_rx(rt_device_t dev) { - struct pbuf* p; - rt_uint32_t size; - rt_uint32_t Index; + struct pbuf* p; + rt_uint32_t size; + rt_uint32_t Index; - /* init p pointer */ - p = RT_NULL; + /* init p pointer */ + p = RT_NULL; - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - Index = LPC_EMAC->RxConsumeIndex; - if(Index != LPC_EMAC->RxProduceIndex) - { - size = (RX_STAT_INFO(Index) & 0x7ff)+1; - if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; + Index = LPC_EMAC->RxConsumeIndex; + if(Index != LPC_EMAC->RxProduceIndex) + { + size = (RX_STAT_INFO(Index) & 0x7ff)+1; + if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE; - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); - if (p != RT_NULL) - { - struct pbuf* q; - rt_uint8_t *ptr; + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf* q; + rt_uint8_t *ptr; - ptr = (rt_uint8_t*)RX_BUF(Index); - for (q = p; q != RT_NULL; q= q->next) - { - memcpy(q->payload, ptr, q->len); - ptr += q->len; - } - } + ptr = (rt_uint8_t*)RX_BUF(Index); + for (q = p; q != RT_NULL; q= q->next) + { + memcpy(q->payload, ptr, q->len); + ptr += q->len; + } + } - /* move Index to the next */ - if(++Index > LPC_EMAC->RxDescriptorNumber) - Index = 0; + /* move Index to the next */ + if(++Index > LPC_EMAC->RxDescriptorNumber) + Index = 0; - /* set consume index */ - LPC_EMAC->RxConsumeIndex = Index; - } - else - { - /* Enable RxDone interrupt */ - LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; - } + /* set consume index */ + LPC_EMAC->RxConsumeIndex = Index; + } + else + { + /* Enable RxDone interrupt */ + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; + } - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* unlock EMAC device */ + rt_sem_release(&sem_lock); - return p; + return p; } void lpc17xx_emac_hw_init(void) { - rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - /* set autonegotiation mode */ - lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; + /* set autonegotiation mode */ + lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO; - // OUI 00-60-37 NXP Semiconductors - lpc17xx_emac_device.dev_addr[0] = 0x00; - lpc17xx_emac_device.dev_addr[1] = 0x60; - lpc17xx_emac_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - lpc17xx_emac_device.dev_addr[3] = 0x12; - lpc17xx_emac_device.dev_addr[4] = 0x34; - lpc17xx_emac_device.dev_addr[5] = 0x56; + // OUI 00-60-37 NXP Semiconductors + lpc17xx_emac_device.dev_addr[0] = 0x00; + lpc17xx_emac_device.dev_addr[1] = 0x60; + lpc17xx_emac_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + lpc17xx_emac_device.dev_addr[3] = 0x12; + lpc17xx_emac_device.dev_addr[4] = 0x34; + lpc17xx_emac_device.dev_addr[5] = 0x56; - lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; - lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; - lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; - lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; - lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; - lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; - lpc17xx_emac_device.parent.parent.user_data = RT_NULL; + lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init; + lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open; + lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close; + lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read; + lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write; + lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control; + lpc17xx_emac_device.parent.parent.user_data = RT_NULL; - lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; - lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; + lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx; + lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx; - eth_device_init(&(lpc17xx_emac_device.parent), "e0"); + eth_device_init(&(lpc17xx_emac_device.parent), "e0"); } #ifdef RT_USING_FINSH #include void emac_dump() { - rt_kprintf("Command : %08x\n", LPC_EMAC->Command); - rt_kprintf("Status : %08x\n", LPC_EMAC->Status); - rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus); - rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus); - rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable); - rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus); + rt_kprintf("Command : %08x\n", LPC_EMAC->Command); + rt_kprintf("Status : %08x\n", LPC_EMAC->Status); + rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus); + rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus); + rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable); + rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus); } FINSH_FUNCTION_EXPORT(emac_dump, dump emac register); #endif diff --git a/bsp/lpc178x/drivers/emac.h b/bsp/lpc178x/drivers/emac.h index dafcd36e9b..4b89c8ca82 100644 --- a/bsp/lpc178x/drivers/emac.h +++ b/bsp/lpc178x/drivers/emac.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef __LPC17XX_EMAC_H #define __LPC17XX_EMAC_H @@ -11,7 +20,7 @@ #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ /* EMAC variables located in 16K Ethernet SRAM */ -#define RX_DESC_BASE 0x20000000 +#define RX_DESC_BASE 0x20000000 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) diff --git a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c index ad9bfffeba..3e7abe8b3b 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c +++ b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_clkpwr.c 2011-06-02 +* $Id$ lpc177x_8x_clkpwr.c 2011-06-02 *//** -* @file lpc177x_8x_clkpwr.c -* @brief Contains all functions support for Clock and Power Control -* firmware library on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_clkpwr.c +* @brief Contains all functions support for Clock and Power Control +* firmware library on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -41,253 +41,253 @@ uint32_t SPIFIFrequency = 0; */ /*********************************************************************//** - * @brief Set value of each Peripheral Clock Selection - * @param[in] ClkType clock type that will be divided, should be: - * - CLKPWR_CLKTYPE_CPU : CPU clock - * - CLKPWR_CLKTYPE_PER : Peripheral clock - * - CLKPWR_CLKTYPE_EMC : EMC clock - * - CLKPWR_CLKTYPE_USB : USB clock - * @param[in] DivVal Value of divider. This value should be set as follows: - * - CPU clock: DivVal must be in range: 0..31 - * - Peripheral clock: DivVal must be in range: 0..31 - * - EMC clock: DivVal must be: - * + 0: The EMC uses the same clock as the CPU - * + 1: The EMC uses a clock at half the rate of the CPU - * - USB clock: DivVal must be: - * + 0: the divider is turned off, no clock will - * be provided to the USB subsystem - * + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz - * + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz + * @brief Set value of each Peripheral Clock Selection + * @param[in] ClkType clock type that will be divided, should be: + * - CLKPWR_CLKTYPE_CPU : CPU clock + * - CLKPWR_CLKTYPE_PER : Peripheral clock + * - CLKPWR_CLKTYPE_EMC : EMC clock + * - CLKPWR_CLKTYPE_USB : USB clock + * @param[in] DivVal Value of divider. This value should be set as follows: + * - CPU clock: DivVal must be in range: 0..31 + * - Peripheral clock: DivVal must be in range: 0..31 + * - EMC clock: DivVal must be: + * + 0: The EMC uses the same clock as the CPU + * + 1: The EMC uses a clock at half the rate of the CPU + * - USB clock: DivVal must be: + * + 0: the divider is turned off, no clock will + * be provided to the USB subsystem + * + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz + * + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz * @return none * Note: Pls assign right DivVal, this function will not check if it is illegal. **********************************************************************/ void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal) { - switch(ClkType) - { - case CLKPWR_CLKTYPE_CPU: - LPC_SC->CCLKSEL = DivVal; - SystemCoreClockUpdate(); //Update clock - break; - case CLKPWR_CLKTYPE_PER: - LPC_SC->PCLKSEL = DivVal; - SystemCoreClockUpdate(); //Update clock - break; - case CLKPWR_CLKTYPE_EMC: - LPC_SC->EMCCLKSEL = DivVal; - SystemCoreClockUpdate(); //Update clock - break; - case CLKPWR_CLKTYPE_USB: - LPC_SC->USBCLKSEL &= ~(0x0000001F); - LPC_SC->USBCLKSEL |= DivVal; - break; - default: - while(1);//Error Loop; - } + switch(ClkType) + { + case CLKPWR_CLKTYPE_CPU: + LPC_SC->CCLKSEL = DivVal; + SystemCoreClockUpdate(); //Update clock + break; + case CLKPWR_CLKTYPE_PER: + LPC_SC->PCLKSEL = DivVal; + SystemCoreClockUpdate(); //Update clock + break; + case CLKPWR_CLKTYPE_EMC: + LPC_SC->EMCCLKSEL = DivVal; + SystemCoreClockUpdate(); //Update clock + break; + case CLKPWR_CLKTYPE_USB: + LPC_SC->USBCLKSEL &= ~(0x0000001F); + LPC_SC->USBCLKSEL |= DivVal; + break; + default: + while(1);//Error Loop; + } } /*********************************************************************//** - * @brief Get current clock value - * @param[in] ClkType clock type that will be divided, should be: - * - CLKPWR_CLKTYPE_CPU : CPU clock - * - CLKPWR_CLKTYPE_PER : Peripheral clock - * - CLKPWR_CLKTYPE_EMC : EMC clock - * - CLKPWR_CLKTYPE_USB : USB clock + * @brief Get current clock value + * @param[in] ClkType clock type that will be divided, should be: + * - CLKPWR_CLKTYPE_CPU : CPU clock + * - CLKPWR_CLKTYPE_PER : Peripheral clock + * - CLKPWR_CLKTYPE_EMC : EMC clock + * - CLKPWR_CLKTYPE_USB : USB clock **********************************************************************/ uint32_t CLKPWR_GetCLK (uint8_t ClkType) { - switch(ClkType) - { - case CLKPWR_CLKTYPE_CPU: - return SystemCoreClock; + switch(ClkType) + { + case CLKPWR_CLKTYPE_CPU: + return SystemCoreClock; - case CLKPWR_CLKTYPE_PER: - return PeripheralClock; + case CLKPWR_CLKTYPE_PER: + return PeripheralClock; - case CLKPWR_CLKTYPE_EMC: - return EMCClock; + case CLKPWR_CLKTYPE_EMC: + return EMCClock; - case CLKPWR_CLKTYPE_USB: - return USBClock; + case CLKPWR_CLKTYPE_USB: + return USBClock; - default: - while(1);//error loop - } + default: + while(1);//error loop + } } /*********************************************************************//** - * @brief Configure power supply for each peripheral according to NewState - * @param[in] PPType Type of peripheral used to enable power, - * should be one of the following: - * - CLKPWR_PCONP_PCLCD : LCD - * - CLKPWR_PCONP_PCTIM0 : Timer 0 - - CLKPWR_PCONP_PCTIM1 : Timer 1 - - CLKPWR_PCONP_PCUART0 : UART 0 - - CLKPWR_PCONP_PCUART1 : UART 1 - - CLKPWR_PCONP_PCPWM0 : PWM 0 - - CLKPWR_PCONP_PCPWM1 : PWM 1 - - CLKPWR_PCONP_PCI2C0 : I2C 0 - - CLKPWR_PCONP_PCUART4 : UART4 - - CLKPWR_PCONP_PCRTC : RTC - - CLKPWR_PCONP_PCSSP1 : SSP 1 - - CLKPWR_PCONP_PCEMC : EMC - - CLKPWR_PCONP_PCADC : ADC - - CLKPWR_PCONP_PCAN1 : CAN 1 - - CLKPWR_PCONP_PCAN2 : CAN 2 - - CLKPWR_PCONP_PCGPIO : GPIO - - CLKPWR_PCONP_PCMC : MCPWM - - CLKPWR_PCONP_PCQEI : QEI - - CLKPWR_PCONP_PCI2C1 : I2C 1 - - CLKPWR_PCONP_PCSSP2 : SSP 2 - - CLKPWR_PCONP_PCSSP0 : SSP 0 - - CLKPWR_PCONP_PCTIM2 : Timer 2 - - CLKPWR_PCONP_PCTIM3 : Timer 3 - - CLKPWR_PCONP_PCUART2 : UART 2 - - CLKPWR_PCONP_PCUART3 : UART 3 - - CLKPWR_PCONP_PCI2C2 : I2C 2 - - CLKPWR_PCONP_PCI2S : I2S - - CLKPWR_PCONP_PCSDC : SDC - - CLKPWR_PCONP_PCGPDMA : GPDMA - - CLKPWR_PCONP_PCENET : Ethernet - - CLKPWR_PCONP_PCUSB : USB + * @brief Configure power supply for each peripheral according to NewState + * @param[in] PPType Type of peripheral used to enable power, + * should be one of the following: + * - CLKPWR_PCONP_PCLCD : LCD + * - CLKPWR_PCONP_PCTIM0 : Timer 0 + - CLKPWR_PCONP_PCTIM1 : Timer 1 + - CLKPWR_PCONP_PCUART0 : UART 0 + - CLKPWR_PCONP_PCUART1 : UART 1 + - CLKPWR_PCONP_PCPWM0 : PWM 0 + - CLKPWR_PCONP_PCPWM1 : PWM 1 + - CLKPWR_PCONP_PCI2C0 : I2C 0 + - CLKPWR_PCONP_PCUART4 : UART4 + - CLKPWR_PCONP_PCRTC : RTC + - CLKPWR_PCONP_PCSSP1 : SSP 1 + - CLKPWR_PCONP_PCEMC : EMC + - CLKPWR_PCONP_PCADC : ADC + - CLKPWR_PCONP_PCAN1 : CAN 1 + - CLKPWR_PCONP_PCAN2 : CAN 2 + - CLKPWR_PCONP_PCGPIO : GPIO + - CLKPWR_PCONP_PCMC : MCPWM + - CLKPWR_PCONP_PCQEI : QEI + - CLKPWR_PCONP_PCI2C1 : I2C 1 + - CLKPWR_PCONP_PCSSP2 : SSP 2 + - CLKPWR_PCONP_PCSSP0 : SSP 0 + - CLKPWR_PCONP_PCTIM2 : Timer 2 + - CLKPWR_PCONP_PCTIM3 : Timer 3 + - CLKPWR_PCONP_PCUART2 : UART 2 + - CLKPWR_PCONP_PCUART3 : UART 3 + - CLKPWR_PCONP_PCI2C2 : I2C 2 + - CLKPWR_PCONP_PCI2S : I2S + - CLKPWR_PCONP_PCSDC : SDC + - CLKPWR_PCONP_PCGPDMA : GPDMA + - CLKPWR_PCONP_PCENET : Ethernet + - CLKPWR_PCONP_PCUSB : USB * - * @param[in] NewState New state of Peripheral Power, should be: - * - ENABLE : Enable power for this peripheral - * - DISABLE : Disable power for this peripheral + * @param[in] NewState New state of Peripheral Power, should be: + * - ENABLE : Enable power for this peripheral + * - DISABLE : Disable power for this peripheral * * @return none **********************************************************************/ void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) { - if (NewState == ENABLE) - { - LPC_SC->PCONP |= PPType; - } - else if (NewState == DISABLE) - { - LPC_SC->PCONP &= ~PPType; - } + if (NewState == ENABLE) + { + LPC_SC->PCONP |= PPType; + } + else if (NewState == DISABLE) + { + LPC_SC->PCONP &= ~PPType; + } } #if 0 // nxp21346 /*********************************************************************//** - * @brief Configure hardware reset for each peripheral according to NewState - * @param[in] PPType Type of peripheral used to enable power, - * should be one of the following: - * - CLKPWR_RSTCON0_LCD : LCD - * - CLKPWR_RSTCON0_TIM0 : Timer 0 - - CLKPWR_RSTCON0_TIM1 : Timer 1 - - CLKPWR_RSTCON0_UART0 : UART 0 - - CLKPWR_RSTCON0_UART1 : UART 1 - - CLKPWR_RSTCON0_PWM0 : PWM 0 - - CLKPWR_RSTCON0_PWM1 : PWM 1 - - CLKPWR_RSTCON0_I2C0 : I2C 0 - - CLKPWR_RSTCON0_UART4 : UART 4 - - CLKPWR_RSTCON0_RTC : RTC - - CLKPWR_RSTCON0_SSP1 : SSP 1 - - CLKPWR_RSTCON0_EMC : EMC - - CLKPWR_RSTCON0_ADC : ADC - - CLKPWR_RSTCON0_CAN1 : CAN 1 - - CLKPWR_RSTCON0_CAN2 : CAN 2 - - CLKPWR_RSTCON0_GPIO : GPIO - - CLKPWR_RSTCON0_MCPWM : MCPWM - - CLKPWR_RSTCON0_QEI : QEI - - CLKPWR_RSTCON0_I2C1 : I2C 1 - - CLKPWR_RSTCON0_SSP2 : SSP 2 - - CLKPWR_RSTCON0_SSP0 : SSP 0 - - CLKPWR_RSTCON0_TIM2 : Timer 2 - - CLKPWR_RSTCON0_TIM3 : Timer 3 - - CLKPWR_RSTCON0_UART2 : UART 2 - - CLKPWR_RSTCON0_UART3 : UART 3 - - CLKPWR_RSTCON0_I2C2 : I2C 2 - - CLKPWR_RSTCON0_I2S : I2S - - CLKPWR_RSTCON0_SDC : SDC - - CLKPWR_RSTCON0_GPDMA : GPDMA - - CLKPWR_RSTCON0_ENET : Ethernet - - CLKPWR_RSTCON0_USB : USB + * @brief Configure hardware reset for each peripheral according to NewState + * @param[in] PPType Type of peripheral used to enable power, + * should be one of the following: + * - CLKPWR_RSTCON0_LCD : LCD + * - CLKPWR_RSTCON0_TIM0 : Timer 0 + - CLKPWR_RSTCON0_TIM1 : Timer 1 + - CLKPWR_RSTCON0_UART0 : UART 0 + - CLKPWR_RSTCON0_UART1 : UART 1 + - CLKPWR_RSTCON0_PWM0 : PWM 0 + - CLKPWR_RSTCON0_PWM1 : PWM 1 + - CLKPWR_RSTCON0_I2C0 : I2C 0 + - CLKPWR_RSTCON0_UART4 : UART 4 + - CLKPWR_RSTCON0_RTC : RTC + - CLKPWR_RSTCON0_SSP1 : SSP 1 + - CLKPWR_RSTCON0_EMC : EMC + - CLKPWR_RSTCON0_ADC : ADC + - CLKPWR_RSTCON0_CAN1 : CAN 1 + - CLKPWR_RSTCON0_CAN2 : CAN 2 + - CLKPWR_RSTCON0_GPIO : GPIO + - CLKPWR_RSTCON0_MCPWM : MCPWM + - CLKPWR_RSTCON0_QEI : QEI + - CLKPWR_RSTCON0_I2C1 : I2C 1 + - CLKPWR_RSTCON0_SSP2 : SSP 2 + - CLKPWR_RSTCON0_SSP0 : SSP 0 + - CLKPWR_RSTCON0_TIM2 : Timer 2 + - CLKPWR_RSTCON0_TIM3 : Timer 3 + - CLKPWR_RSTCON0_UART2 : UART 2 + - CLKPWR_RSTCON0_UART3 : UART 3 + - CLKPWR_RSTCON0_I2C2 : I2C 2 + - CLKPWR_RSTCON0_I2S : I2S + - CLKPWR_RSTCON0_SDC : SDC + - CLKPWR_RSTCON0_GPDMA : GPDMA + - CLKPWR_RSTCON0_ENET : Ethernet + - CLKPWR_RSTCON0_USB : USB * - * @param[in] NewState New state of Peripheral Power, should be: - * - ENABLE : Enable power for this peripheral - * - DISABLE : Disable power for this peripheral + * @param[in] NewState New state of Peripheral Power, should be: + * - ENABLE : Enable power for this peripheral + * - DISABLE : Disable power for this peripheral * * @return none **********************************************************************/ void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState) { - if(PType < 32) - { - if(NewState == ENABLE) - LPC_SC->RSTCON0 |=(1<RSTCON0 &=~(1<RSTCON1 |= (1<<(PType - 31)); - else - LPC_SC->RSTCON1 &= ~(1<<(PType - 31)); - } + if(PType < 32) + { + if(NewState == ENABLE) + LPC_SC->RSTCON0 |=(1<RSTCON0 &=~(1<RSTCON1 |= (1<<(PType - 31)); + else + LPC_SC->RSTCON1 &= ~(1<<(PType - 31)); + } } // nxp21346 #endif /*********************************************************************//** - * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None + * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None **********************************************************************/ void CLKPWR_Sleep(void) { - LPC_SC->PCON = 0x00; - /* Sleep Mode*/ - __WFI(); + LPC_SC->PCON = 0x00; + /* Sleep Mode*/ + __WFI(); } /*********************************************************************//** - * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None + * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None **********************************************************************/ void CLKPWR_DeepSleep(void) { /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x8; - /* Deep Sleep Mode*/ - __WFI(); + SCB->SCR = 0x4; + LPC_SC->PCON = 0x8; + /* Deep Sleep Mode*/ + __WFI(); } /*********************************************************************//** - * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None + * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None **********************************************************************/ void CLKPWR_PowerDown(void) { /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x09; - /* Power Down Mode*/ - __WFI(); + SCB->SCR = 0x4; + LPC_SC->PCON = 0x09; + /* Power Down Mode*/ + __WFI(); } /*********************************************************************//** - * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. - * @param[in] None - * @return None + * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. + * @param[in] None + * @return None **********************************************************************/ void CLKPWR_DeepPowerDown(void) { /* Deep-Sleep Mode, set SLEEPDEEP bit */ - SCB->SCR = 0x4; - LPC_SC->PCON = 0x03; - /* Deep Power Down Mode*/ - __WFI(); + SCB->SCR = 0x4; + LPC_SC->PCON = 0x03; + /* Deep Power Down Mode*/ + __WFI(); } /** diff --git a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h index 427ccc0279..b1bf670b52 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h +++ b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h @@ -1,14 +1,14 @@ /********************************************************************** -* $Id$ lpc177x_8x_clkpwr.h 2011-06-02 +* $Id$ lpc177x_8x_clkpwr.h 2011-06-02 *//** -* @file lpc177x_8x_clkpwr.h -* @brief Contains all macro definitions and function prototypes -* support for Clock and Power Control firmware library on -* LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_clkpwr.h +* @brief Contains all macro definitions and function prototypes +* support for Clock and Power Control firmware library on +* LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -26,7 +26,7 @@ **********************************************************************/ /* Peripheral group ----------------------------------------------------------- */ -/** @defgroup CLKPWR Clock Power +/** @defgroup CLKPWR Clock Power * @ingroup LPC177x_8xCMSIS_FwLib_Drivers * @{ */ @@ -52,163 +52,163 @@ extern "C" /******************************************************************** * Clock Source Selection Definitions **********************************************************************/ -#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0)) -#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1)) +#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0)) +#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1)) /******************************************************************** * Clock type/domain Definitions (calculated from input and pre-configuration * parameter(s) **********************************************************************/ -#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0)) -#define CLKPWR_CLKTYPE_PER ((uint32_t)(1)) -#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2)) -#define CLKPWR_CLKTYPE_USB ((uint32_t)(3)) +#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0)) +#define CLKPWR_CLKTYPE_PER ((uint32_t)(1)) +#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2)) +#define CLKPWR_CLKTYPE_USB ((uint32_t)(3)) /******************************************************************** * Power Control for Peripherals Definitions **********************************************************************/ /** LCD controller power/clock control bit */ -#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0)) +#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0)) /** Timer/Counter 0 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) +#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) /* Timer/Counter 1 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) +#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) /** UART0 power/clock control bit */ -#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) +#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) /** UART1 power/clock control bit */ -#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) +#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) /** PWM0 power/clock control bit */ -#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5)) +#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5)) /** PWM1 power/clock control bit */ -#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) +#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) /** The I2C0 interface power/clock control bit */ -#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) +#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) /** UART4 power/clock control bit */ -#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8)) +#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8)) /** The RTC power/clock control bit */ -#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) +#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) /** The SSP1 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) +#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) /** External Memory controller power/clock control bit */ -#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11)) +#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11)) /** A/D converter 0 (ADC0) power/clock control bit */ -#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12)) +#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12)) /** CAN Controller 1 power/clock control bit */ -#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) +#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) /** CAN Controller 2 power/clock control bit */ -#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) +#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) /** GPIO power/clock control bit */ -#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) +#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) /** Motor Control PWM */ -#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17)) +#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17)) /** Quadrature Encoder Interface power/clock control bit */ -#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) +#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) /** The I2C1 interface power/clock control bit */ -#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) +#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) /** The SSP2 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20)) +#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20)) /** The SSP0 interface power/clock control bit */ -#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) +#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) /** Timer 2 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) +#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) /** Timer 3 power/clock control bit */ -#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) +#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) /** UART 2 power/clock control bit */ -#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) +#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) /** UART 3 power/clock control bit */ -#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) +#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) /** I2C interface 2 power/clock control bit */ -#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) +#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) /** I2S interface power/clock control bit*/ -#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) +#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) /** SD card interface power/clock control bit */ -#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28)) +#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28)) /** GP DMA function power/clock control bit*/ -#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) +#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) /** Ethernet block power/clock control bit*/ -#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) +#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) /** USB interface power/clock control bit*/ -#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) +#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) /******************************************************************** * Power Control for Peripherals Definitions **********************************************************************/ -#define CLKPWR_RSTCON0_LCD ((uint32_t)(0)) -#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1)) -#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2)) -#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3)) -#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4)) -#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5)) -#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6)) -#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7)) -#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8)) -#define CLKPWR_RSTCON0_RTC ((uint32_t)(9)) -#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10)) -#define CLKPWR_RSTCON0_EMC ((uint32_t)(11)) -#define CLKPWR_RSTCON0_ADC ((uint32_t)(12)) -#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13)) -#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14)) -#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15)) -#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17)) -#define CLKPWR_RSTCON0_QEI ((uint32_t)(18)) -#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19)) -#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20)) -#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21)) -#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22)) -#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23)) -#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24)) -#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25)) -#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26)) -#define CLKPWR_RSTCON0_I2S ((uint32_t)(27)) -#define CLKPWR_RSTCON0_SDC ((uint32_t)(28)) -#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29)) -#define CLKPWR_RSTCON0_ENET ((uint32_t)(30)) -#define CLKPWR_RSTCON0_USB ((uint32_t)(31)) +#define CLKPWR_RSTCON0_LCD ((uint32_t)(0)) +#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1)) +#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2)) +#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3)) +#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4)) +#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5)) +#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6)) +#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7)) +#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8)) +#define CLKPWR_RSTCON0_RTC ((uint32_t)(9)) +#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10)) +#define CLKPWR_RSTCON0_EMC ((uint32_t)(11)) +#define CLKPWR_RSTCON0_ADC ((uint32_t)(12)) +#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13)) +#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14)) +#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15)) +#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17)) +#define CLKPWR_RSTCON0_QEI ((uint32_t)(18)) +#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19)) +#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20)) +#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21)) +#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22)) +#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23)) +#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24)) +#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25)) +#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26)) +#define CLKPWR_RSTCON0_I2S ((uint32_t)(27)) +#define CLKPWR_RSTCON0_SDC ((uint32_t)(28)) +#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29)) +#define CLKPWR_RSTCON0_ENET ((uint32_t)(30)) +#define CLKPWR_RSTCON0_USB ((uint32_t)(31)) -#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32)) -#define CLKPWR_RSTCON1_DAC ((uint32_t)(33)) -#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34)) +#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32)) +#define CLKPWR_RSTCON1_DAC ((uint32_t)(33)) +#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34)) /** * @} */ - + /* External clock variable from system_LPC177x_8x.h */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ -extern uint32_t EMCClock; /*!< EMC Clock Frequency */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */ +extern uint32_t EMCClock; /*!< EMC Clock Frequency */ /* External clock variable from lpc177x_8x_clkpwr.h */ -extern uint32_t USBClock; /*!< USB Frequency */ +extern uint32_t USBClock; /*!< USB Frequency */ /* Public Functions ----------------------------------------------------------- */ /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions diff --git a/bsp/lpc178x/drivers/lpc177x_8x_emc.c b/bsp/lpc178x/drivers/lpc177x_8x_emc.c index c3009589a3..4047dbf623 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_emc.c +++ b/bsp/lpc178x/drivers/lpc177x_8x_emc.c @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_emc.c 2011-06-02 +* $Id$ lpc177x_8x_emc.c 2011-06-02 *//** -* @file lpc177x_8x_emc.c -* @brief Contains all functions support for EMC firmware library -* on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_emc.c +* @brief Contains all functions support for EMC firmware library +* on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -30,23 +30,23 @@ /*********************************************************************//** - * @brief EMC initialize - * @param[in] None - * @return None + * @brief EMC initialize + * @param[in] None + * @return None **********************************************************************/ void EMC_Init(void) { - uint8_t i; + uint8_t i; - /* Enable clock for EMC */ -// CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE); -// LPC_EMC->Control = 0x00000001; -// LPC_EMC->Config = 0x00000000; + /* Enable clock for EMC */ +// CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE); +// LPC_EMC->Control = 0x00000001; +// LPC_EMC->Config = 0x00000000; - LPC_SC->PCONP |= 0x00000800; - LPC_SC->EMCDLYCTL = 0x00001010; - LPC_EMC->Control = 0x00000001; - LPC_EMC->Config = 0x00000000; + LPC_SC->PCONP |= 0x00000800; + LPC_SC->EMCDLYCTL = 0x00001010; + LPC_EMC->Control = 0x00000001; + LPC_EMC->Config = 0x00000000; /* Pin configuration: * P2.14 - /EMC_CS2 @@ -81,40 +81,40 @@ void EMC_Init(void) * P4.30 - /EMC_CS0 * P4.31 - /EMC_CS1 */ - PINSEL_ConfigPin(2,14,1); - PINSEL_ConfigPin(2,15,1); - PINSEL_ConfigPin(2,16,1); - PINSEL_ConfigPin(2,17,1); - PINSEL_ConfigPin(2,18,1); - PINSEL_ConfigPin(2,19,1); - PINSEL_ConfigPin(2,20,1); - PINSEL_ConfigPin(2,21,1); - PINSEL_ConfigPin(2,22,1); - PINSEL_ConfigPin(2,23,1); - PINSEL_ConfigPin(2,24,1); - PINSEL_ConfigPin(2,25,1); - PINSEL_ConfigPin(2,26,1); - PINSEL_ConfigPin(2,27,1); - PINSEL_ConfigPin(2,28,1); - PINSEL_ConfigPin(2,29,1); - PINSEL_ConfigPin(2,30,1); - PINSEL_ConfigPin(2,31,1); + PINSEL_ConfigPin(2,14,1); + PINSEL_ConfigPin(2,15,1); + PINSEL_ConfigPin(2,16,1); + PINSEL_ConfigPin(2,17,1); + PINSEL_ConfigPin(2,18,1); + PINSEL_ConfigPin(2,19,1); + PINSEL_ConfigPin(2,20,1); + PINSEL_ConfigPin(2,21,1); + PINSEL_ConfigPin(2,22,1); + PINSEL_ConfigPin(2,23,1); + PINSEL_ConfigPin(2,24,1); + PINSEL_ConfigPin(2,25,1); + PINSEL_ConfigPin(2,26,1); + PINSEL_ConfigPin(2,27,1); + PINSEL_ConfigPin(2,28,1); + PINSEL_ConfigPin(2,29,1); + PINSEL_ConfigPin(2,30,1); + PINSEL_ConfigPin(2,31,1); - PINSEL_ConfigPin(5,0,1); - PINSEL_ConfigPin(5,1,1); + PINSEL_ConfigPin(5,0,1); + PINSEL_ConfigPin(5,1,1); - for(i = 0; i < 32; i++) - { - PINSEL_ConfigPin(3,i,1); - PINSEL_ConfigPin(4,i,1); - } + for(i = 0; i < 32; i++) + { + PINSEL_ConfigPin(3,i,1); + PINSEL_ConfigPin(4,i,1); + } } /*********************************************************************//** - * @brief Configure Little Endian/Big Endian mode for EMC - * @param[in] endia_mode Endian mode, should be: - * - EMC_LITTLE_ENDIAN_MODE: Little-endian mode - * - EMC_BIG_ENDIAN_MODE : Big-endian mode - * @return None + * @brief Configure Little Endian/Big Endian mode for EMC + * @param[in] endia_mode Endian mode, should be: + * - EMC_LITTLE_ENDIAN_MODE: Little-endian mode + * - EMC_BIG_ENDIAN_MODE : Big-endian mode + * @return None **********************************************************************/ void EMC_ConfigEndianMode(uint32_t endian_mode) { @@ -123,12 +123,12 @@ void EMC_ConfigEndianMode(uint32_t endian_mode) /****************** Group of Dynamic control functions************************/ /*********************************************************************//** - * @brief Set the value for dynamic clock enable bit - * @param[in] clock_enable clock enable mode, should be: - * - 0: Clock enable of idle devices are deasserted to - * save power - * - 1: All clock enables are driven HIGH continuously - * @return None + * @brief Set the value for dynamic clock enable bit + * @param[in] clock_enable clock enable mode, should be: + * - 0: Clock enable of idle devices are deasserted to + * save power + * - 1: All clock enables are driven HIGH continuously + * @return None **********************************************************************/ void EMC_DynCtrlClockEnable(uint32_t clock_enable) { @@ -136,13 +136,13 @@ void EMC_DynCtrlClockEnable(uint32_t clock_enable) } /*********************************************************************//** - * @brief Set the value for dynamic memory clock control: - * stops or runs continuously - * @param[in] clock_control clock control mode, should be: - * - 0: CLKOUT stops when all SDRAMs are idle and - * during self-refresh mode - * - 1: CLKOUT runs continuously - * @return None + * @brief Set the value for dynamic memory clock control: + * stops or runs continuously + * @param[in] clock_control clock control mode, should be: + * - 0: CLKOUT stops when all SDRAMs are idle and + * during self-refresh mode + * - 1: CLKOUT runs continuously + * @return None **********************************************************************/ void EMC_DynCtrlClockControl(int32_t clock_control) { @@ -151,11 +151,11 @@ void EMC_DynCtrlClockControl(int32_t clock_control) } /*********************************************************************//** - * @brief Switch the Self-refresh mode between normal and self-refresh mode - * @param[in] self_refresh_mode self refresh mode, should be: - * - 0: Normal mode - * - 1: Enter self-refresh mode - * @return None + * @brief Switch the Self-refresh mode between normal and self-refresh mode + * @param[in] self_refresh_mode self refresh mode, should be: + * - 0: Normal mode + * - 1: Enter self-refresh mode + * @return None **********************************************************************/ void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode) { @@ -164,11 +164,11 @@ void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode) } /*********************************************************************//** - * @brief Enable/disable CLKOUT - * @param[in] MMC_val Memory clock control mode, should be: - * - 0: CLKOUT enabled - * - 1: CLKOUT disabled - * @return None + * @brief Enable/disable CLKOUT + * @param[in] MMC_val Memory clock control mode, should be: + * - 0: CLKOUT enabled + * - 1: CLKOUT disabled + * @return None **********************************************************************/ void EMC_DynCtrlMMC(uint32_t MMC_val) { @@ -177,13 +177,13 @@ void EMC_DynCtrlMMC(uint32_t MMC_val) } /*********************************************************************//** - * @brief Issue SDRAM command - * @param[in] SDRAM_command Command mode, should be: - * - 0x00: Issue SDRAM NORMAL operation command - * - 0x01: Issue SDRAM MODE command - * - 0x02: Issue SDRAM PALL (precharge all) command - * - 0x03: Issue SRAM NOP (no operation) command - * @return None + * @brief Issue SDRAM command + * @param[in] SDRAM_command Command mode, should be: + * - 0x00: Issue SDRAM NORMAL operation command + * - 0x01: Issue SDRAM MODE command + * - 0x02: Issue SDRAM PALL (precharge all) command + * - 0x03: Issue SRAM NOP (no operation) command + * @return None **********************************************************************/ void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command) { @@ -192,11 +192,11 @@ void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command) } /*********************************************************************//** - * @brief Switch between Normal operation and deep sleep power mode - * @param[in] Power_command Low-power SDRAM deep-sleep mode, should be: - * - 0: Normal operation - * - 1: Enter deep-sleep mode - * @return None + * @brief Switch between Normal operation and deep sleep power mode + * @param[in] Power_command Low-power SDRAM deep-sleep mode, should be: + * - 0: Normal operation + * - 1: Enter deep-sleep mode + * @return None **********************************************************************/ void EMC_DynCtrlPowerDownMode(uint32_t Power_command) { @@ -205,22 +205,22 @@ void EMC_DynCtrlPowerDownMode(uint32_t Power_command) } /*********************************************************************//** - * @brief Set the value of EMC dynamic memory registers - * @param[in] par EMC register that will set value, should be: - * - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register - * - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register - * - EMC_DYN_MEM_TRP: Dynamic RP register - * - EMC_DYN_MEM_TRAS: Dynamic RAS register - * - EMC_DYN_MEM_TSREX: Dynamic SREX register - * - EMC_DYN_MEM_TAPR: Dynamic APR register - * - EMC_DYN_MEM_TDAL: Dynamic DAL register - * - EMC_DYN_MEM_TWR: Dynamic WR register - * - EMC_DYN_MEM_TRC: Dynamic RC register - * - EMC_DYN_MEM_TRFC: Dynamic RFC register - * - EMC_DYN_MEM_TXSR: Dynamic XSR register - * - EMC_DYN_MEM_TRRD: Dynamic RRD register - * - EMC_DYN_MEM_TMRD: Dynamic MRD register - * @return None + * @brief Set the value of EMC dynamic memory registers + * @param[in] par EMC register that will set value, should be: + * - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register + * - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register + * - EMC_DYN_MEM_TRP: Dynamic RP register + * - EMC_DYN_MEM_TRAS: Dynamic RAS register + * - EMC_DYN_MEM_TSREX: Dynamic SREX register + * - EMC_DYN_MEM_TAPR: Dynamic APR register + * - EMC_DYN_MEM_TDAL: Dynamic DAL register + * - EMC_DYN_MEM_TWR: Dynamic WR register + * - EMC_DYN_MEM_TRC: Dynamic RC register + * - EMC_DYN_MEM_TRFC: Dynamic RFC register + * - EMC_DYN_MEM_TXSR: Dynamic XSR register + * - EMC_DYN_MEM_TRRD: Dynamic RRD register + * - EMC_DYN_MEM_TMRD: Dynamic MRD register + * @return None **********************************************************************/ void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val) { @@ -269,9 +269,9 @@ void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val) } /*********************************************************************//** - * @brief Set extended wait time out for accessing static memory - * @param[in] Extended_wait_time_out timeout value that will be set - * @return None + * @brief Set extended wait time out for accessing static memory + * @param[in] Extended_wait_time_out timeout value that will be set + * @return None **********************************************************************/ void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out) { @@ -279,13 +279,13 @@ void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out) } /*********************************************************************//** - * @brief Configure the memory device - * @param[in] index index number, should be from 0 to 3 - * @param[in] mem_dev Memory device, should be: - * - 0x00: SDRAM - * - 0x01: Low-power SDRAM - * - 0x02: Micron Syncflash - * @return None + * @brief Configure the memory device + * @param[in] index index number, should be from 0 to 3 + * @param[in] mem_dev Memory device, should be: + * - 0x00: SDRAM + * - 0x01: Low-power SDRAM + * - 0x02: Micron Syncflash + * @return None **********************************************************************/ void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev) { @@ -294,24 +294,24 @@ void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev) { case 0: LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev; - break; + break; case 1: LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev; - break; + break; case 2: LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev; - break; + break; case 3: LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev; - break; + break; } } /*********************************************************************//** - * @brief Map the address for the memory device - * @param[in] index index number, should be from 0 to 3 - * @param[in] add_mapped address where the memory will be mapped - * @return None + * @brief Map the address for the memory device + * @param[in] index index number, should be from 0 to 3 + * @param[in] add_mapped address where the memory will be mapped + * @return None **********************************************************************/ void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped) { @@ -321,26 +321,26 @@ void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped) { case 0: LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask) | add_mapped; - break; + break; case 1: LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | add_mapped; - break; + break; case 2: LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask) | add_mapped; - break; + break; case 3: LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | add_mapped; - break; + break; } } /*********************************************************************//** - * @brief Enable/disable the buffer - * @param[in] index index number, should be from 0 to 3 - * @param[in] buff_control buffer control mode, should be: - * - ENABLE - * - DISABLE - * @return None + * @brief Enable/disable the buffer + * @param[in] index index number, should be from 0 to 3 + * @param[in] buff_control buffer control mode, should be: + * - ENABLE + * - DISABLE + * @return None **********************************************************************/ void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control) { @@ -349,27 +349,27 @@ void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control) { case 0: LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | buff_control; - break; + break; case 1: LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask) | buff_control; - break; + break; case 2: LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask)| buff_control; - break; + break; case 3: LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | buff_control; - break; + break; } } /*********************************************************************//** - * @brief Configure write permission: protect or not - * @param[in] index index number, should be from 0 to 3 - * @param[in] permission permission mode, should be: - * - ENABLE: protect - * - DISABLE: not protect - * @return None + * @brief Configure write permission: protect or not + * @param[in] index index number, should be from 0 to 3 + * @param[in] permission permission mode, should be: + * - ENABLE: protect + * - DISABLE: not protect + * @return None **********************************************************************/ void EMC_DynMemConfigP(uint32_t index , uint32_t permission) { @@ -378,24 +378,24 @@ void EMC_DynMemConfigP(uint32_t index , uint32_t permission) { case 0: LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | permission; - break; + break; case 1: LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | permission; - break; + break; case 2: LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask) | permission; - break; + break; case 3: LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | permission; - break; + break; } } /*********************************************************************//** - * @brief Set value for RAS latency - * @param[in] index index number, should be from 0 to 3 - * @param[in] ras_val RAS value should be in range: 0..3 - * @return None + * @brief Set value for RAS latency + * @param[in] index index number, should be from 0 to 3 + * @param[in] ras_val RAS value should be in range: 0..3 + * @return None **********************************************************************/ void EMC_DynMemRAS(uint32_t index , uint32_t ras_val) { @@ -405,24 +405,24 @@ void EMC_DynMemRAS(uint32_t index , uint32_t ras_val) { case 0: LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | ras_val; - break; + break; case 1: LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | ras_val; - break; + break; case 2: LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask) | ras_val; - break; + break; case 3: LPC_EMC->DynamicRasCas3 = (LPC_EMC->DynamicRasCas3 & mask) | ras_val; - break; + break; } } /*********************************************************************//** - * @brief Set value for CAS latency - * @param[in] index index number, should be from 0 to 3 - * @param[in] ras_val CAS value should be in range: 0..3 - * @return None + * @brief Set value for CAS latency + * @param[in] index index number, should be from 0 to 3 + * @param[in] ras_val CAS value should be in range: 0..3 + * @return None **********************************************************************/ void EMC_DynMemCAS(uint32_t index , uint32_t cas_val) { @@ -431,26 +431,26 @@ void EMC_DynMemCAS(uint32_t index , uint32_t cas_val) { case 0: LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val; - break; + break; case 1: LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val; - break; + break; case 2: LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val; - break; + break; case 3: LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val; - break; + break; } } /*********************************************************************//** - * @brief Configure the memory width - * @param[in] index index number, should be from 0 to 3 - * @param[in] mem_width memory width, should be: - * - 0x00: 8-bits - * - 0x01: 16-bits - * - 0x02: 32-bits - * @return None + * @brief Configure the memory width + * @param[in] index index number, should be from 0 to 3 + * @param[in] mem_width memory width, should be: + * - 0x00: 8-bits + * - 0x01: 16-bits + * - 0x02: 32-bits + * @return None **********************************************************************/ void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width) { @@ -459,25 +459,25 @@ void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | mem_width; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | mem_width; - break; + break; case 2: LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| mem_width; - break; + break; case 3: LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | mem_width; - break; + break; } } /*********************************************************************//** - * @brief Configure the page mode - * @param[in] index index number, should be from 0 to 3 - * @param[in] page_mode page mode, should be: - * - 0: disable - * - 1: asynchronous page mode enable - * @return None + * @brief Configure the page mode + * @param[in] index index number, should be from 0 to 3 + * @param[in] page_mode page mode, should be: + * - 0: disable + * - 1: asynchronous page mode enable + * @return None **********************************************************************/ void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode) { @@ -486,25 +486,25 @@ void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | page_mode; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | page_mode; - break; + break; case 2: LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| page_mode; - break; + break; case 3: LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| page_mode; - break; + break; } } /*********************************************************************//** - * @brief Configure the chip select polarity - * @param[in] index index number, should be from 0 to 3 - * @param[in] pagepol_val_mode page mode, should be: - * - 0: Active LOW ship select - * - 1: Active HIGH chip select - * @return None + * @brief Configure the chip select polarity + * @param[in] index index number, should be from 0 to 3 + * @param[in] pagepol_val_mode page mode, should be: + * - 0: Active LOW ship select + * - 1: Active HIGH chip select + * @return None **********************************************************************/ void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val) { @@ -513,26 +513,26 @@ void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | pol_val; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pol_val; - break; + break; case 2: LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | pol_val; - break; + break; case 3: LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | pol_val; - break; + break; } } /*********************************************************************//** - * @brief Configure the byte lane state - * @param[in] index index number, should be from 0 to 3 - * @param[in] pb_val Byte lane state, should be: - * - 0: For reads all bits in BLSn[3:0] are HIGH. - * - 1: For reads all bits in BLSn[3:0] are LOW. - * @return None + * @brief Configure the byte lane state + * @param[in] index index number, should be from 0 to 3 + * @param[in] pb_val Byte lane state, should be: + * - 0: For reads all bits in BLSn[3:0] are HIGH. + * - 1: For reads all bits in BLSn[3:0] are LOW. + * @return None **********************************************************************/ void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val) { @@ -541,26 +541,26 @@ void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask)| pb_val; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pb_val; - break; + break; case 2: LPC_EMC->StaticConfig2 =( LPC_EMC->StaticConfig2 & mask)| pb_val; - break; + break; case 3: LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| pb_val; - break; + break; } } /*********************************************************************//** - * @brief Configure the extended wait value - * @param[in] index index number, should be from 0 to 3 - * @param[in] ex_wait Extended wait mode, should be: - * - 0: Extended wait disabled. - * - 1: Extended wait enabled. - * @return None + * @brief Configure the extended wait value + * @param[in] index index number, should be from 0 to 3 + * @param[in] ex_wait Extended wait mode, should be: + * - 0: Extended wait disabled. + * - 1: Extended wait enabled. + * @return None **********************************************************************/ void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait) { @@ -569,26 +569,26 @@ void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | ex_wait; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | ex_wait; - break; + break; case 2: LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | ex_wait; - break; + break; case 3: LPC_EMC->StaticConfig3 =( LPC_EMC->StaticConfig3 & mask) | ex_wait; - break; + break; } } /*********************************************************************//** - * @brief Configure the buffer enable value - * @param[in] index index number, should be from 0 to 3 - * @param[in] buf_val Buffer mode, should be: - * - 0: Buffer disabled. - * - 1: Buffer enabled. - * @return None + * @brief Configure the buffer enable value + * @param[in] index index number, should be from 0 to 3 + * @param[in] buf_val Buffer mode, should be: + * - 0: Buffer disabled. + * - 1: Buffer enabled. + * @return None **********************************************************************/ void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val) { @@ -597,26 +597,26 @@ void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | buf_val; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | buf_val; - break; + break; case 2: LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | buf_val; - break; + break; case 3: LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | buf_val; - break; + break; } } /*********************************************************************//** - * @brief Configure the write permission - * @param[in] index index number, should be from 0 to 3 - * @param[in] per_val Permission mode, should be: - * - 0: Write not protected. - * - 1: Write protected. - * @return None + * @brief Configure the write permission + * @param[in] index index number, should be from 0 to 3 + * @param[in] per_val Permission mode, should be: + * - 0: Write not protected. + * - 1: Write protected. + * @return None **********************************************************************/ void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val) { @@ -625,36 +625,36 @@ void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val) { case 0: LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | per_val; - break; + break; case 1: LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | per_val; - break; + break; case 2: LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | per_val; - break; + break; case 3: LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | per_val; - break; + break; } } /*********************************************************************//** - * @brief Set the value of LPC_EMC static memory registers - * @param[in] index index number, should be from 0 to 3 - * @param[in] EMC_STA_MEM_PAR Static register, should be: - * - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register - * - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register - * - EMC_STA_MEM_WAITRD: StaticWaitRd0 register - * - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register - * - EMC_STA_MEM_WAITWR: StaticWaitWr0 register - * - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register - * @return None + * @brief Set the value of LPC_EMC static memory registers + * @param[in] index index number, should be from 0 to 3 + * @param[in] EMC_STA_MEM_PAR Static register, should be: + * - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register + * - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register + * - EMC_STA_MEM_WAITRD: StaticWaitRd0 register + * - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register + * - EMC_STA_MEM_WAITWR: StaticWaitWr0 register + * - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register + * @return None **********************************************************************/ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val) { switch (index) { - case 0: + case 0: switch ( par) { case EMC_STA_MEM_WAITWEN: @@ -676,8 +676,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val LPC_EMC->StaticWaitTurn0 = val; break; } - break; - case 1: + break; + case 1: switch ( par) { case EMC_STA_MEM_WAITWEN: @@ -699,8 +699,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val LPC_EMC->StaticWaitTurn1 = val; break; } - break; - case 2: + break; + case 2: switch ( par) { case EMC_STA_MEM_WAITWEN: @@ -722,8 +722,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val LPC_EMC->StaticWaitTurn2 = val; break; } - break; - case 3: + break; + case 3: switch ( par) { case EMC_STA_MEM_WAITWEN: @@ -745,7 +745,7 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val LPC_EMC->StaticWaitTurn3 = val; break; } - break; + break; } } diff --git a/bsp/lpc178x/drivers/lpc177x_8x_emc.h b/bsp/lpc178x/drivers/lpc177x_8x_emc.h index 41d9cbfcc1..497521edb8 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_emc.h +++ b/bsp/lpc178x/drivers/lpc177x_8x_emc.h @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_emc.h 2011-06-02 +* $Id$ lpc177x_8x_emc.h 2011-06-02 *//** -* @file lpc177x_8x_emc.h -* @brief Contains all macro definitions and function prototypes -* support for EMC firmware library on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_emc.h +* @brief Contains all macro definitions and function prototypes +* support for EMC firmware library on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -25,7 +25,7 @@ **********************************************************************/ /* Peripheral group ----------------------------------------------------------- */ -/** @defgroup EMC EMC (External Memory Controller) +/** @defgroup EMC EMC (External Memory Controller) * @ingroup LPC177x_8xCMSIS_FwLib_Drivers * @{ */ @@ -45,233 +45,233 @@ * EMC Control Register (EMCControl) **********************************************************************/ /* Control register mask */ -#define EMC_Control_MASK ((uint32_t )0x07) +#define EMC_Control_MASK ((uint32_t )0x07) /* Control register EMC: Enable control. */ -#define EMC_Control_E ((uint32_t )(1<<0)) +#define EMC_Control_E ((uint32_t )(1<<0)) /* Control register EMC: Address mirror control. */ -#define EMC_Control_M ((uint32_t )(1<<1)) +#define EMC_Control_M ((uint32_t )(1<<1)) /* Control register EMC: Low-power mode control. */ -#define EMC_Control_L ((uint32_t )(1<<2)) +#define EMC_Control_L ((uint32_t )(1<<2)) /*********************************************************************** * EMC Status Register (EMCStatus) **********************************************************************/ /* Status register mask */ -#define EMC_Status_MASK ((uint32_t )0x07) +#define EMC_Status_MASK ((uint32_t )0x07) /* Status register EMC: Busy. */ -#define EMC_Status_B ((uint32_t )(1<<0)) +#define EMC_Status_B ((uint32_t )(1<<0)) /* Status register EMC: Write buffer status. */ -#define EMC_Status_S ((uint32_t )(1<<1)) +#define EMC_Status_S ((uint32_t )(1<<1)) /* Status register EMC: Self-refresh acknowledge.. */ -#define EMC_Status_SA ((uint32_t )(1<<2)) +#define EMC_Status_SA ((uint32_t )(1<<2)) /*********************************************************************** * EMC Configuration register (EMCConfig) **********************************************************************/ /* EMC Configuration register : Enable control. */ -#define EMC_Config_Endian_Mode ((uint32_t )(1<<0)) +#define EMC_Config_Endian_Mode ((uint32_t )(1<<0)) /* EMC Configuration register: CCLK. */ -#define EMC_Config_CCLK ((uinr32_t)(1<<8)) +#define EMC_Config_CCLK ((uinr32_t)(1<<8)) /* EMC Configuration register mask */ -#define EMC_Config_MASK ((uint32_t)(0x101)) +#define EMC_Config_MASK ((uint32_t)(0x101)) /*********************************************************************** * Dynamic Memory Control register (EMCDynamicControl) **********************************************************************/ /* Dynamic Memory Control register EMC: Dynamic memory clock enable. */ -#define EMC_DynamicControl_CE ((uint32_t )(1<<0)) +#define EMC_DynamicControl_CE ((uint32_t )(1<<0)) /* Dynamic Memory Control register EMC: Dynamic memory clock control */ -#define EMC_DynamicControl_CS ((uint32_t )(1<<1)) +#define EMC_DynamicControl_CS ((uint32_t )(1<<1)) /* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/ -#define EMC_DynamicControl_SR ((uint32_t )(1<<2)) +#define EMC_DynamicControl_SR ((uint32_t )(1<<2)) /* Dynamic Memory Control register EMC: Memory clock control (MMC)*/ -#define EMC_DynamicControl_MMC ((uint32_t )(1<<5)) +#define EMC_DynamicControl_MMC ((uint32_t )(1<<5)) /* Dynamic Memory Control register EMC: SDRAM initialization*/ -#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7)) +#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7)) /* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/ -#define EMC_DynamicControl_DP ((uint32_t ) (1<<13)) +#define EMC_DynamicControl_DP ((uint32_t ) (1<<13)) /*********************************************************************** * Dynamic Memory Refresh Timer register (EMCDynamicRefresh) **********************************************************************/ /* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */ -#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff)) +#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff)) /*********************************************************************** * Dynamic Memory Read Configuration register (EMCDynamicReadConfig) **********************************************************************/ /* EMCDynamicReadConfig register EMC:Read data strategy (RD) */ -#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03)) +#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03)) /*********************************************************************** * Dynamic Memory Percentage Command Period register (EMCDynamictRP) **********************************************************************/ /* EMCDynamictRP register EMC: Precharge command period (tRP). */ -#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f)) +#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS) **********************************************************************/ /* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */ -#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f)) +#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR) **********************************************************************/ /* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */ -#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f)) +#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL) **********************************************************************/ /* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/ -#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f)) +#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Dynamic Memory Write Recovery Time register (EMCDynamictWR) **********************************************************************/ /* EMCDynamictWR register EMC: Write recovery time (tWR)*/ -#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f) +#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f) /*********************************************************************** * Dynamic Memory Active to Active Command Period register (EMCDynamictRC) **********************************************************************/ /* EMCDynamictRC register EMC: Active to active command period (tRC)*/ -#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f) +#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f) /*********************************************************************** * Dynamic Memory Auto-refresh Period register (EMCDynamictRFC) **********************************************************************/ /* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/ -#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f)) +#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f)) /*********************************************************************** * Dynamic Memory Exit Self-refresh register (EMCDynamictXSR) **********************************************************************/ /* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/ -#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f)) +#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f)) /*********************************************************************** * Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD) **********************************************************************/ /* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/ -#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f)) +#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD) **********************************************************************/ /* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/ -#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f)) +#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f)) /*********************************************************************** * Static Memory Extended Wait Register (EMCStaticExtendedWait) **********************************************************************/ /* StaticExtendedWait register EMC: External wait time out. */ -#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff)) +#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff)) /*********************************************************************** * Dynamic Memory Configuration registers (EMCDynamicConfig0-3) **********************************************************************/ /* DynamicConfig register EMC: Memory device (MD). */ -#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3)) +#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3)) /* DynamicConfig register EMC: Address mapping (AM) */ -#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7)) +#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7)) /* DynamicConfig register EMC: Address mapping (AM) */ -#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14)) +#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14)) /* DynamicConfig register EMC: Buffer enable */ -#define EMC_DynamicConfig_B ((uint32_t )(1 << 19)) +#define EMC_DynamicConfig_B ((uint32_t )(1 << 19)) /* DynamicConfig register EMC: Write protect (P) */ -#define EMC_DynamicConfig_P ((uint32_t )(1 << 20)) +#define EMC_DynamicConfig_P ((uint32_t )(1 << 20)) /*********************************************************************** * Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3) **********************************************************************/ /* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */ -#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03)) +#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03)) /* DynamicRASCAS register EMC: CAS latency (CAS)*/ -#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8)) +#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8)) /*********************************************************************** * Static Memory Configuration registers (EMCStaticConfig0-3) **********************************************************************/ /* StaticConfig register EMC: Memory width (MW). */ -#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03)) +#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03)) /* StaticConfig register EMC: Memory width 8bit . */ -#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0)) +#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0)) /* StaticConfig register EMC: Memory width 16bit . */ -#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1)) +#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1)) /* StaticConfig register EMC: Memory width 32bit . */ -#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2)) +#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2)) /* StaticConfig register EMC: Page mode (PM) */ -#define EMC_StaticConfig_PM ((uint32_t )(1 << 3)) +#define EMC_StaticConfig_PM ((uint32_t )(1 << 3)) /* StaticConfig register EMC: Chip select polarity (PC) */ -#define EMC_StaticConfig_PC ((uint32_t )(1 << 6)) +#define EMC_StaticConfig_PC ((uint32_t )(1 << 6)) /* StaticConfig register EMC: Byte lane state (PB) */ -#define EMC_StaticConfig_PB ((uint32_t )(1 << 7)) +#define EMC_StaticConfig_PB ((uint32_t )(1 << 7)) /* StaticConfig register EMC: Extended wait (EW) */ -#define EMC_StaticConfig_EW ((uint32_t )(1 << 8)) +#define EMC_StaticConfig_EW ((uint32_t )(1 << 8)) /* StaticConfig register EMC: Buffer enable (B) */ -#define EMC_StaticConfig_B ((uint32_t )(1 << 19)) +#define EMC_StaticConfig_B ((uint32_t )(1 << 19)) /* StaticConfig register EMC: Write protect (P) */ -#define EMC_StaticConfig_P ((uint32_t )(1 << 20)) +#define EMC_StaticConfig_P ((uint32_t )(1 << 20)) /*********************************************************************** * Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3) **********************************************************************/ /* StaticWaitWen register EMC: Wait write enable (WAITWEN). */ -#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f)) +#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3) **********************************************************************/ /* StaticWaitOen register EMC: Wait output enable (WAITOEN). */ -#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f)) +#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Static Memory Read Delay registers (EMCStaticWaitRd0-3) **********************************************************************/ /* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode read first access wait state (WAITRD) */ -#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f)) +#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f)) /*********************************************************************** * Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3) **********************************************************************/ /* StaticwaitPage register EMC: Asynchronous page mode read after the first read wait states (WAITPAGE). */ -#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f)) +#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f)) /*********************************************************************** * Static Memory Write Delay registers (EMCStaticWaitwr0-3) **********************************************************************/ /* StaticWaitwr register EMC: Write wait states (WAITWR). */ -#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f)) +#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f)) /*********************************************************************** * Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3) **********************************************************************/ /* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */ -#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f)) +#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f)) /*********************************************************************** * Delay Control register (EMCDLYCTL) **********************************************************************/ -#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F)) -#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8)) -#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16)) -#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24)) +#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F)) +#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8)) +#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16)) +#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24)) /*********************************************************************** * EMC Calibration register (EMCCAL) **********************************************************************/ -#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF)) -#define EMC_CAL_START ((uint32_t)(1<<14)) -#define EMC_CAL_DONE ((uint32_t)(1<<15)) +#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF)) +#define EMC_CAL_START ((uint32_t)(1<<14)) +#define EMC_CAL_DONE ((uint32_t)(1<<15)) -#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0)) -#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1)) +#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0)) +#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1)) /** * @} diff --git a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c index d767af1180..062224decf 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c +++ b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_pinsel.c 2011-06-02 +* $Id$ lpc177x_8x_pinsel.c 2011-06-02 *//** -* @file lpc177x_8x_pinsel.c -* @brief Contains all functions support for Pin-connection block -* firmware library on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_pinsel.c +* @brief Contains all functions support for Pin-connection block +* firmware library on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -32,39 +32,39 @@ /* Includes ------------------------------------------------------------------- */ #include "lpc177x_8x_pinsel.h" -#define PINSEL_I2C_MODE_POS (8) -#define PINSEL_I2C_MODE_NUMBITS (2) -#define PINSEL_I2C_MODE_BITMASK (0x03) +#define PINSEL_I2C_MODE_POS (8) +#define PINSEL_I2C_MODE_NUMBITS (2) +#define PINSEL_I2C_MODE_BITMASK (0x03) -#define PINSEL_BASIC_MODE_POS (3) -#define PINSEL_BASIC_MODE_NUMBITS (2) -#define PINSEL_BASIC_MODE_BITMASK (0x03) +#define PINSEL_BASIC_MODE_POS (3) +#define PINSEL_BASIC_MODE_NUMBITS (2) +#define PINSEL_BASIC_MODE_BITMASK (0x03) -#define PINSEL_DACEN_POS (16) -#define PINSEL_DACEN_BITMASK (0x01) -#define PINSEL_DACEN_NUMBITS (1) +#define PINSEL_DACEN_POS (16) +#define PINSEL_DACEN_BITMASK (0x01) +#define PINSEL_DACEN_NUMBITS (1) -#define PINSEL_GLITCH_FILTER_POS (8) -#define PINSEL_GLITCH_FILTER_BITMASK (0x01) -#define PINSEL_GLITCH_FILTER_NUMBITS (1) +#define PINSEL_GLITCH_FILTER_POS (8) +#define PINSEL_GLITCH_FILTER_BITMASK (0x01) +#define PINSEL_GLITCH_FILTER_NUMBITS (1) -#define PINSEL_ADMODE_POS (7) -#define PINSEL_ADMODE_BITMASK (0x01) -#define PINSEL_ADMODE_NUMBITS (1) +#define PINSEL_ADMODE_POS (7) +#define PINSEL_ADMODE_BITMASK (0x01) +#define PINSEL_ADMODE_NUMBITS (1) /* Private Functions ---------------------------------------------------------- */ /*********************************************************************//** - * @brief Get pointer to GPIO peripheral due to GPIO port - * @param[in] portnum Port Number value, should be in range from 0..3. - * @param[in] pinnum Pin number value, should be in range from 0..31 - * @return Pointer to GPIO peripheral + * @brief Get pointer to GPIO peripheral due to GPIO port + * @param[in] portnum Port Number value, should be in range from 0..3. + * @param[in] pinnum Pin number value, should be in range from 0..31 + * @return Pointer to GPIO peripheral **********************************************************************/ static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum) { - uint32_t *pPIN = NULL; - pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t))); - return pPIN; + uint32_t *pPIN = NULL; + pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t))); + return pPIN; } /* Public Functions ----------------------------------------------------------- */ @@ -73,268 +73,268 @@ static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum) */ /*********************************************************************//** - * @brief Setup the pin selection function - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] funcnum Function number, should be range: 0..7 - * - 0: Select GPIO (Default) - * - 1: Selects the 1st alternate function - * - 2: Selects the 2nd alternate function - * ... - * - 7: Selects the 7th alternate function - * @return None + * @brief Setup the pin selection function + * @param[in] portnum PORT number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] funcnum Function number, should be range: 0..7 + * - 0: Select GPIO (Default) + * - 1: Selects the 1st alternate function + * - 2: Selects the 2nd alternate function + * ... + * - 7: Selects the 7th alternate function + * @return None **********************************************************************/ void PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); - *pPIN &= 0x00000007;//Clear function bits - *pPIN |= funcnum; + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); + *pPIN &= 0x00000007;//Clear function bits + *pPIN |= funcnum; } /*********************************************************************//** - * @brief Setup resistor mode for each pin - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] modenum: Mode number, should be in range: 0..3 - - IOCON_MODE_PLAIN: Plain output - - IOCON_MODE_PULLDOWN: Pull-down enable - - IOCON_MODE_PULLUP: Pull-up enable - - IOCON_MODE_REPEATER: Repeater mode - * @return None + * @brief Setup resistor mode for each pin + * @param[in] portnum PORT number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] modenum: Mode number, should be in range: 0..3 + - IOCON_MODE_PLAIN: Plain output + - IOCON_MODE_PULLDOWN: Pull-down enable + - IOCON_MODE_PULLUP: Pull-up enable + - IOCON_MODE_REPEATER: Repeater mode + * @return None **********************************************************************/ void PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); - *(uint32_t *)pPIN &= ~(3<<3);//Clear function bits - *(uint32_t *)pPIN |= modenum; + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); + *(uint32_t *)pPIN &= ~(3<<3);//Clear function bits + *(uint32_t *)pPIN |= modenum; } /*********************************************************************//** - * @brief Setup hysteresis for each pin - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Hysteresis mode, should be: - * - ENABLE: Hysteresis enable - * - DISABLE: Hysteresis disable - * @return None + * @brief Setup hysteresis for each pin + * @param[in] portnum Port number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] NewState new state of Hysteresis mode, should be: + * - ENABLE: Hysteresis enable + * - DISABLE: Hysteresis disable + * @return None **********************************************************************/ void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits - } - else - *(uint32_t *)pPIN |= IOCON_HYS; + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); + if(NewState == DISABLE) + { + *(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits + } + else + *(uint32_t *)pPIN |= IOCON_HYS; } /*********************************************************************//** - * @brief Setup Slew rate for each pin - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Slew rate control, should be: - * - ENABLE: Output slew rate control is enable - * - DISABLE: Output slew rate control is disable - * @return None + * @brief Setup Slew rate for each pin + * @param[in] portnum Port number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] NewState new state of Slew rate control, should be: + * - ENABLE: Output slew rate control is enable + * - DISABLE: Output slew rate control is disable + * @return None **********************************************************************/ void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits - } - else - *(uint32_t *)pPIN |= IOCON_SLEW; + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); + if(NewState == DISABLE) + { + *(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits + } + else + *(uint32_t *)pPIN |= IOCON_SLEW; } /*********************************************************************//** - * @brief Setup Input Buffer for each pin - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Input buffer mode, should be: - * - ENABLE: The input buffer is enable - * - DISABLE: The input buffer is disable - * @return None + * @brief Setup Input Buffer for each pin + * @param[in] portnum Port number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] NewState new state of Input buffer mode, should be: + * - ENABLE: The input buffer is enable + * - DISABLE: The input buffer is disable + * @return None **********************************************************************/ void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits - } - else - *(uint32_t *)pPIN |= IOCON_INBUF; + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); + if(NewState == DISABLE) + { + *(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits + } + else + *(uint32_t *)pPIN |= IOCON_INBUF; } /*********************************************************************//** - * @brief Setup I2CMode for only pins that provide special I2C functionality - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] I2CMode I2C mode, should be: - * - IOCON_I2CMODE_FAST: Fast mode and standard I2C mode - * - IOCON_I2CMODE_OPENDRAIN: Open drain I/O - * - IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O - * - IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O - * @return None + * @brief Setup I2CMode for only pins that provide special I2C functionality + * @param[in] portnum Port number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] I2CMode I2C mode, should be: + * - IOCON_I2CMODE_FAST: Fast mode and standard I2C mode + * - IOCON_I2CMODE_OPENDRAIN: Open drain I/O + * - IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O + * - IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O + * @return None **********************************************************************/ void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); - *(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS); - *(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS); + *(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS); + *(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS); } /*********************************************************************//** - * @brief Setup Open-drain mode in each pin - * @param[in] portnum Port number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] NewState new state of Open-drain mode: - * - DISABLE: Normal pin I/O mode - * - ENABLE: Open-drain enable - * @return None + * @brief Setup Open-drain mode in each pin + * @param[in] portnum Port number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] NewState new state of Open-drain mode: + * - DISABLE: Normal pin I/O mode + * - ENABLE: Open-drain enable + * @return None **********************************************************************/ void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState) { - uint32_t *pPIN = NULL; - pPIN = PIN_GetPointer(portnum, pinnum); - if(NewState == DISABLE) - { - *(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits - } - else - { - *(uint32_t *)pPIN |= IOCON_ODMODE; - } + uint32_t *pPIN = NULL; + pPIN = PIN_GetPointer(portnum, pinnum); + if(NewState == DISABLE) + { + *(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits + } + else + { + *(uint32_t *)pPIN |= IOCON_ODMODE; + } } /*********************************************************************//** - * @brief Enable the Analog mode for each pin (default is as Digital pins) - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: Enable the DAC mode of the pin - - DISABLE: Disable the DAC mode - * @return None + * @brief Enable the Analog mode for each pin (default is as Digital pins) + * @param[in] portnum PORT number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] enable: the state of the pin that is expected to run + - ENABLE: Enable the DAC mode of the pin + - DISABLE: Disable the DAC mode + * @return None **********************************************************************/ void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable) { - uint32_t *pPIN = NULL; + uint32_t *pPIN = NULL; - uint8_t condition = 0; + uint8_t condition = 0; - condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13)) - | ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23)) - | ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31)); + condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13)) + | ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23)) + | ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31)); - if(!condition) - { - return; - } + if(!condition) + { + return; + } - pPIN = PIN_GetPointer(portnum, pinnum); + pPIN = PIN_GetPointer(portnum, pinnum); - //Clear this bit to set the pin to Analog mode - *(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS); + //Clear this bit to set the pin to Analog mode + *(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS); - if(enable) - { + if(enable) + { - } - else - { - *(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one - } + } + else + { + *(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one + } - return; + return; } /*********************************************************************//** - * @brief Choose the DAC mode for each pin - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: Enable the DAC mode of the pin - - DISABLE: Disable the DAC mode - * @return None + * @brief Choose the DAC mode for each pin + * @param[in] portnum PORT number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] enable: the state of the pin that is expected to run + - ENABLE: Enable the DAC mode of the pin + - DISABLE: Disable the DAC mode + * @return None **********************************************************************/ void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable) { - uint32_t *pPIN = NULL; + uint32_t *pPIN = NULL; - // This setting is only for DAC pin (output pin) - if(!((portnum == 0) && (pinnum == 26))) - { - return; - } + // This setting is only for DAC pin (output pin) + if(!((portnum == 0) && (pinnum == 26))) + { + return; + } - pPIN = PIN_GetPointer(portnum, pinnum); + pPIN = PIN_GetPointer(portnum, pinnum); - //Clear DAC Enable function bits - *(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS); + //Clear DAC Enable function bits + *(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS); - if(enable) - { - *(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one - } - else - { + if(enable) + { + *(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one + } + else + { - } + } - return; + return; } /*********************************************************************//** - * @brief Control the glitch filter for each pin - * @param[in] portnum PORT number, should be in range: 0..3 - * @param[in] pinnum Pin number, should be in range: 0..31 - * @param[in] enable: the state of the pin that is expected to run - - ENABLE: The noise pulses below approximately 10ns are filtered out - - DISABLE: No input filtering is done. - * @return None + * @brief Control the glitch filter for each pin + * @param[in] portnum PORT number, should be in range: 0..3 + * @param[in] pinnum Pin number, should be in range: 0..31 + * @param[in] enable: the state of the pin that is expected to run + - ENABLE: The noise pulses below approximately 10ns are filtered out + - DISABLE: No input filtering is done. + * @return None **********************************************************************/ void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable) { - uint32_t *pPIN = NULL; + uint32_t *pPIN = NULL; - // This setting is only for DAC pin (output pin) - if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9)))) - { - return; - } + // This setting is only for DAC pin (output pin) + if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9)))) + { + return; + } - pPIN = PIN_GetPointer(portnum, pinnum); + pPIN = PIN_GetPointer(portnum, pinnum); - *(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0 + *(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0 - //Clear Filter bits - *(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS); + //Clear Filter bits + *(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS); - if(!enable) - { - *(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one - } - else - { + if(!enable) + { + *(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one + } + else + { - } + } - *pPIN = *pPIN; + *pPIN = *pPIN; - return; + return; } /** diff --git a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h index ca83c91fc5..d7a291cff7 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h +++ b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_pinsel.h 2011-06-02 +* $Id$ lpc177x_8x_pinsel.h 2011-06-02 *//** -* @file lpc177x_8x_pinsel.h -* @brief Contains all macro definitions and function prototypes -* support for Pin-connection block firmware library on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_pinsel.h +* @brief Contains all macro definitions and function prototypes +* support for Pin-connection block firmware library on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -25,7 +25,7 @@ **********************************************************************/ /* Peripheral group ----------------------------------------------------------- */ -/** @defgroup PINSEL Pin Selection +/** @defgroup PINSEL Pin Selection * @ingroup LPC177x_8xCMSIS_FwLib_Drivers * @{ */ @@ -44,160 +44,160 @@ */ /* Macros define IOCON bits */ -#define IOCON_MODE_PLAIN ((0<<3)) -#define IOCON_MODE_PULLDOWN ((1<<3)) -#define IOCON_MODE_PULLUP ((2<<3)) -#define IOCON_MODE_REPEATER ((3<<3)) -#define IOCON_HYS ((1<<5)) -#define IOCON_SLEW ((1<<6)) -#define IOCON_INBUF ((1<<7)) -#define IOCON_I2CMODE_FAST ((0<<8)) -#define IOCON_I2CMODE_OPENDRAIN ((1<<8)) -#define IOCON_I2CMODE_FASTPLUS ((2<<8)) -#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8)) -#define IOCON_ODMODE ((1<<10)) +#define IOCON_MODE_PLAIN ((0<<3)) +#define IOCON_MODE_PULLDOWN ((1<<3)) +#define IOCON_MODE_PULLUP ((2<<3)) +#define IOCON_MODE_REPEATER ((3<<3)) +#define IOCON_HYS ((1<<5)) +#define IOCON_SLEW ((1<<6)) +#define IOCON_INBUF ((1<<7)) +#define IOCON_I2CMODE_FAST ((0<<8)) +#define IOCON_I2CMODE_OPENDRAIN ((1<<8)) +#define IOCON_I2CMODE_FASTPLUS ((2<<8)) +#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8)) +#define IOCON_ODMODE ((1<<10)) /* Macros define for LOC registers */ -#define LOC_CAN_RD_1_P0_0 ((0)) /**< Input for CAN_RD_1 comes from P0.0 */ -#define LOC_CAN_RD_1_P0_21 ((1)) /**< Input for CAN_RD_1 comes from P0.21 */ -#define LOC_CAN_RD_2_P2_7 ((0)) /**< Input for CAN_RD_2 comes from P2.7 */ -#define LOC_CAN_RD_2_P0_4 ((1)) /**< Input for CAN_RD_2 comes from P0.4 */ -#define LOC_ENET_MDIO_P2_9 ((0)) /**< Input for ENET_MDIO comes from P2.9 */ -#define LOC_ENET_MDIO_P1_17 ((1)) /**< Input for ENET_MDIO comes from P1.17 */ -#define LOC_EINT_0_P0_29 ((0)) /**< Input for EINT_0 comes from P0.29 */ -#define LOC_EINT_0_P2_10 ((1)) /**< Input for EINT_0 comes from P2.10 */ -#define LOC_EINT_1_P0_30 ((0)) /**< Input for EINT_1 comes from P0.30 */ -#define LOC_EINT_1_P2_11 ((1)) /**< Input for EINT_1 comes from P2.11 */ -#define LOC_I2C0_SCL_P1_31 ((0)) /**< Input for I2C0_SCL comes from P1.31 */ -#define LOC_I2C0_SCL_P0_28 ((1)) /**< Input for I2C0_SCL comes from P0.28 */ -#define LOC_I2C0_SCL_P5_3 ((2)) /**< Input for I2C0_SCL comes from P5.3 */ -#define LOC_I2C0_SDA_P1_30 ((0)) /**< Input for I2C0_SDA comes from P1.30 */ -#define LOC_I2C0_SDA_P0_27 ((1)) /**< Input for I2C0_SDA comes from P0.27 */ -#define LOC_I2C0_SDA_P5_2 ((2)) /**< Input for I2C0_SDA comes from P5.2 */ -#define LOC_I2C1_SCL_P0_1 ((0)) /**< Input for I2C1_SCL comes from P0.1 */ -#define LOC_I2C1_SCL_P2_15 ((1)) /**< Input for I2C1_SCL comes from P2.15 */ -#define LOC_I2C1_SCL_P0_20 ((2)) /**< Input for I2C1_SCL comes from P0.20 */ -#define LOC_I2C1_SDA_P2_14 ((0)) /**< Input for I2C1_SDA comes from P2.14 */ -#define LOC_I2C1_SDA_P0_0 ((1)) /**< Input for I2C1_SDA comes from P0.0 */ -#define LOC_I2C1_SDA_P0_19 ((2)) /**< Input for I2C1_SDA comes from P0.19 */ -#define LOC_I2C2_SCL_P2_31 ((0)) /**< Input for I2C2_SCL comes from P2.31 */ -#define LOC_I2C2_SCL_P0_11 ((1)) /**< Input for I2C2_SCL comes from P0.11 */ -#define LOC_I2C2_SCL_P4_21 ((2)) /**< Input for I2C2_SCL comes from P4.21 */ -#define LOC_I2C2_SCL_P4_29 ((3)) /**< Input for I2C2_SCL comes from P4.29 */ -#define LOC_I2C2_SDA_P2_30 ((0)) /**< Input for I2C2_SDA comes from P2.30 */ -#define LOC_I2C2_SDA_P0_10 ((1)) /**< Input for I2C2_SDA comes from P0.10 */ -#define LOC_I2C2_SDA_P4_20 ((2)) /**< Input for I2C2_SDA comes from P4.20 */ -#define LOC_I2C2_SDA_P1_15 ((3)) /**< Input for I2C2_SDA comes from P1.15 */ -#define LOC_I2S_RX_SCK_P0_23 ((0)) /**< Input for I2S_RX_SCK comes from P0.23 */ -#define LOC_I2S_RX_SCK_P0_4 ((1)) /**< Input for I2S_RX_SCK comes from P0.4 */ -#define LOC_I2S_RX_SDA_P0_25 ((0)) /**< Input for I2S_RX_SDA comes from P0.25 */ -#define LOC_I2S_RX_SDA_P0_6 ((1)) /**< Input for I2S_RX_SDA comes from P0.6 */ -#define LOC_I2S_RX_WS_P0_24 ((0)) /**< Input for I2S_RX_WS comes from P0.24 */ -#define LOC_I2S_RX_WS_P0_5 ((1)) /**< Input for I2S_RX_WS comes from P0.5 */ -#define LOC_I2S_TX_SCK_P2_11 ((0)) /**< Input for I2S_TX_SCK comes from P2.11 */ -#define LOC_I2S_TX_SCK_P0_7 ((1)) /**< Input for I2S_TX_SCK comes from P0.7 */ -#define LOC_I2S_TX_WS_P2_12 ((0)) /**< Input for I2S_TX_WS comes from P2.12 */ -#define LOC_I2S_TX_WS_P0_8 ((1)) /**< Input for I2S_TX_WS comes from P0.8 */ -#define LOC_PWM0_CAP_0_P1_12 ((0)) /**< Input for PWM0_CAP_0 comes from P1.12 */ -#define LOC_PWM0_CAP_0_P3_22 ((1)) /**< Input for PWM0_CAP_0 comes from P3.22 */ -#define LOC_PWM1_CAP_0_P3_23 ((0)) /**< Input for PWM1_CAP_0 comes from P3.23 */ -#define LOC_PWM1_CAP_0_P1_28 ((1)) /**< Input for PWM1_CAP_0 comes from P1.28 */ -#define LOC_PWM1_CAP_0_P2_6 ((2)) /**< Input for PWM1_CAP_0 comes from P2.6 */ -#define LOC_SD_CMD_P0_20 ((0)) /**< Input for SD_CMD comes from P0.20 */ -#define LOC_SD_CMD_P1_3 ((1)) /**< Input for SD_CMD comes from P1.3 */ -#define LOC_SD_DAT_0_P0_22 ((0)) /**< Input for SD_DAT_0 comes from P0.22 */ -#define LOC_SD_DAT_0_P1_6 ((1)) /**< Input for SD_DAT_0 comes from P1.6 */ -#define LOC_SD_DAT_1_P2_11 ((0)) /**< Input for SD_DAT_1 comes from P2.11 */ -#define LOC_SD_DAT_1_P1_7 ((1)) /**< Input for SD_DAT_1 comes from P1.7 */ -#define LOC_SD_DAT_2_P2_12 ((0)) /**< Input for SD_DAT_2 comes from P2.12 */ -#define LOC_SD_DAT_2_P1_11 ((1)) /**< Input for SD_DAT_2 comes from P1.11 */ -#define LOC_SD_DAT_3_P2_13 ((0)) /**< Input for SD_DAT_3 comes from P2.13 */ -#define LOC_SD_DAT_3_P1_12 ((1)) /**< Input for SD_DAT_3 comes from P1.12 */ -#define LOC_SSP0_MISO_P2_26 ((0)) /**< Input for SSP0_MISO comes from P2.26 */ -#define LOC_SSP0_MISO_P1_23 ((1)) /**< Input for SSP0_MISO comes from P1_23 */ -#define LOC_SSP0_MISO_P0_17 ((2)) /**< Input for SSP0_MISO comes from P0_17 */ -#define LOC_SSP0_MOSI_P2_27 ((0)) /**< Input for SSP0_MOSI comes from P2.27 */ -#define LOC_SSP0_MOSI_P1_24 ((1)) /**< Input for SSP0_MOSI comes from P1.24 */ -#define LOC_SSP0_MOSI_P0_18 ((2)) /**< Input for SSP0_MOSI comes from P0.18 */ -#define LOC_SSP0_SCK_P1_20 ((0)) /**< Input for SSP0_SCK comes from P1.20 */ -#define LOC_SSP0_SCK_P2_22 ((1)) /**< Input for SSP0_SCK comes from P2.22 */ -#define LOC_SSP0_SCK_P0_15 ((2)) /**< Input for SSP0_SCK comes from P0_15 */ -#define LOC_SSP0_SSEL_P2_23 ((0)) /**< Input for SSP0_SSEL comes from P2.23 */ -#define LOC_SSP0_SSEL_P1_21 ((1)) /**< Input for SSP0_SSEL comes from P1.21 */ -#define LOC_SSP0_SSEL_P1_28 ((2)) /**< Input for SSP0_SSEL comes from P1.28 */ -#define LOC_SSP0_SSEL_P0_16 ((3)) /**< Input for SSP0_SSEL comes from P0.16 */ -#define LOC_SSP1_MISO_P0_12 ((0)) /**< Input for SSP1_MISO comes from P0.12 */ -#define LOC_SSP1_MISO_P1_18 ((1)) /**< Input for SSP1_MISO comes from P1.18 */ -#define LOC_SSP1_MISO_P4_22 ((2)) /**< Input for SSP1_MISO comes from P4_22 */ -#define LOC_SSP1_MISO_P0_8 ((3)) /**< Input for SSP1_MISO comes from P0.8 */ -#define LOC_SSP1_MOSI_P0_13 ((0)) /**< Input for SSP1_MOSI comes from P0.13 */ -#define LOC_SSP1_MOSI_P1_22 ((1)) /**< Input for SSP1_MOSI comes from P1.22 */ -#define LOC_SSP1_MOSI_P4_23 ((2)) /**< Input for SSP1_MOSI comes from P4.23 */ -#define LOC_SSP1_MOSI_P0_9 ((3)) /**< Input for SSP1_MOSI comes from P0.9 */ -#define LOC_SSP1_SCK_P1_31 ((0)) /**< Input for SSP1_SCK comes from P1.31 */ -#define LOC_SSP1_SCK_P1_19 ((1)) /**< Input for SSP1_SCK comes from P1.19 */ -#define LOC_SSP1_SCK_P4_20 ((2)) /**< Input for SSP1_SCK comes from P4_20 */ -#define LOC_SSP1_SCK_P0_7 ((3)) /**< Input for SSP1_SCK comes from P0_7 */ -#define LOC_SSP1_SSEL_P0_14 ((0)) /**< Input for SSP1_SSEL comes from P0.14 */ -#define LOC_SSP1_SSEL_P1_26 ((1)) /**< Input for SSP1_SSEL comes from P1.26 */ -#define LOC_SSP1_SSEL_P4_21 ((2)) /**< Input for SSP1_SSEL comes from P4.21 */ -#define LOC_SSP1_SSEL_P0_6 ((3)) /**< Input for SSP1_SSEL comes from P0.6 */ -#define LOC_SSP2_MISO_P1_4 ((1)) /**< Input for SSP2_MISO comes from P1.4 */ -#define LOC_SSP2_MOSI_P1_1 ((1)) /**< Input for SSP2_MOSI comes from P1.1 */ -#define LOC_SSP2_SCK_P1_0 ((1)) /**< Input for SSP2_SCK comes from P1.0 */ -#define LOC_SSP2_SSEL_P1_8 ((1)) /**< Input for SSP2_SSEL comes from P1.8 */ -#define LOC_T0_CAP_0_P3_23 ((0)) /**< Input for T0_CAP_0 comes from P3.23 */ -#define LOC_T0_CAP_0_P1_26 ((1)) /**< Input for T0_CAP_0 comes from P1.26 */ -#define LOC_T0_CAP_1_P3_24 ((0)) /**< Input for T0_CAP_1 comes from P3.24 */ -#define LOC_T0_CAP_1_P1_27 ((1)) /**< Input for T0_CAP_1 comes from P1.27 */ -#define LOC_T1_CAP_0_P1_18 ((0)) /**< Input for T1_CAP_0 comes from P1.18 */ -#define LOC_T1_CAP_0_P3_27 ((1)) /**< Input for T1_CAP_0 comes from P3.27 */ -#define LOC_T1_CAP_1_P3_28 ((0)) /**< Input for T1_CAP_1 comes from P3.28 */ -#define LOC_T1_CAP_1_P1_19 ((1)) /**< Input for T1_CAP_1 comes from P1.19 */ -#define LOC_T2_CAP_0_P2_14 ((0)) /**< Input for T2_CAP_0 comes from P2.14 */ -#define LOC_T2_CAP_0_P2_6 ((1)) /**< Input for T2_CAP_0 comes from P2.6 */ -#define LOC_T2_CAP_0_P0_4 ((2)) /**< Input for T2_CAP_0 comes from P0.4 */ -#define LOC_T2_CAP_0_P1_14 ((3)) /**< Input for T2_CAP_0 comes from P1.14 */ -#define LOC_T2_CAP_1_P2_15 ((0)) /**< Input for T2_CAP_1 comes from P2.15 */ -#define LOC_T2_CAP_1_P0_5 ((1)) /**< Input for T2_CAP_1 comes from P0.5 */ -#define LOC_T3_CAP_0_P0_23 ((0)) /**< Input for T3_CAP_0 comes from P0.23 */ -#define LOC_T3_CAP_0_P2_22 ((1)) /**< Input for T3_CAP_0 comes from P2.22 */ -#define LOC_T3_CAP_0_P1_10 ((2)) /**< Input for T3_CAP_0 comes from P1.10 */ -#define LOC_T3_CAP_1_P0_24 ((0)) /**< Input for T3_CAP_1 comes from P0.24 */ -#define LOC_T3_CAP_1_P2_23 ((1)) /**< Input for T3_CAP_1 comes from P2.23 */ -#define LOC_T3_CAP_1_P1_0 ((2)) /**< Input for T3_CAP_1 comes from P1.0 */ -#define LOC_U0_RXD_P0_1 ((0)) /**< Input for U0_RXD comes from P0.1 */ -#define LOC_U0_RXD_P0_3 ((1)) /**< Input for U0_RXD comes from P0.3 */ -#define LOC_U1_CTS_P0_17 ((0)) /**< Input for U1_CTS comes from P0.17 */ -#define LOC_U1_CTS_P2_8 ((1)) /**< Input for U1_CTS comes from P2.8 */ -#define LOC_U1_CTS_P2_2 ((2)) /**< Input for U1_CTS comes from P2.2 */ -#define LOC_U1_CTS_P3_18 ((3)) /**< Input for U1_CTS comes from P3.18 */ -#define LOC_U1_DCD_P0_18 ((0)) /**< Input for U1_DCD comes from P0.18 */ -#define LOC_U1_DCD_P2_3 ((1)) /**< Input for U1_DCD comes from P2.3 */ -#define LOC_U1_DCD_P3_19 ((2)) /**< Input for U1_DCD comes from P3_19 */ -#define LOC_U1_DSR_P0_19 ((0)) /**< Input for U1_DSR comes from P0.19 */ -#define LOC_U1_DSR_P2_4 ((1)) /**< Input for U1_DSR comes from P2.4 */ -#define LOC_U1_DSR_P3_20 ((2)) /**< Input for U1_DSR comes from P0.19 */ -#define LOC_U1_RI_P0_21 ((0)) /**< Input for U1_RI comes from P0.21 */ -#define LOC_U1_RI_P2_6 ((1)) /**< Input for U1_RI comes from P2.6 */ -#define LOC_U1_RI_P3_22 ((2)) /**< Input for U1_RI comes from P3.22 */ -#define LOC_U1_RXD_P0_16 ((0)) /**< Input for U1_RXD comes from P0.16 */ -#define LOC_U1_RXD_P3_17 ((1)) /**< Input for U1_RXD comes from P3.17 */ -#define LOC_U1_RXD_P2_1 ((2)) /**< Input for U1_RXD comes from P2.1 */ -#define LOC_U2_RXD_P0_11 ((0)) /**< Input for U2_RXD comes from P0.11 */ -#define LOC_U2_RXD_P4_23 ((1)) /**< Input for U2_RXD comes from P4.23 */ -#define LOC_U2_RXD_P2_9 ((2)) /**< Input for U2_RXD comes from P2.9 */ -#define LOC_U3_RXD_P0_26 ((0)) /**< Input for U3_RXD comes from P0.26 */ -#define LOC_U3_RXD_P0_1 ((1)) /**< Input for U3_RXD comes from P0.1 */ -#define LOC_U3_RXD_P4_29 ((2)) /**< Input for U3_RXD comes from P4.29 */ -#define LOC_U3_RXD_P0_3 ((3)) /**< Input for U3_RXD comes from P0.3 */ -#define LOC_U4_RXD_P2_9 ((0)) /**< Input for U4_RXD comes from P2.9 */ -#define LOC_U4_RXD_P5_3 ((1)) /**< Input for U4_RXD comes from P5.3 */ -#define LOC_USB_SCL_P0_28 ((0)) /**< Input for USB_SCL comes from P0.28 */ -#define LOC_USB_SCL_P1_28 ((1)) /**< Input for USB_SCL comes from P1.28 */ -#define LOC_USB_SDA_P0_27 ((0)) /**< Input for USB_SDA comes from P0.27 */ -#define LOC_USB_SDA_P1_29 ((1)) /**< Input for USB_SDA comes from P1.29 */ +#define LOC_CAN_RD_1_P0_0 ((0)) /**< Input for CAN_RD_1 comes from P0.0 */ +#define LOC_CAN_RD_1_P0_21 ((1)) /**< Input for CAN_RD_1 comes from P0.21 */ +#define LOC_CAN_RD_2_P2_7 ((0)) /**< Input for CAN_RD_2 comes from P2.7 */ +#define LOC_CAN_RD_2_P0_4 ((1)) /**< Input for CAN_RD_2 comes from P0.4 */ +#define LOC_ENET_MDIO_P2_9 ((0)) /**< Input for ENET_MDIO comes from P2.9 */ +#define LOC_ENET_MDIO_P1_17 ((1)) /**< Input for ENET_MDIO comes from P1.17 */ +#define LOC_EINT_0_P0_29 ((0)) /**< Input for EINT_0 comes from P0.29 */ +#define LOC_EINT_0_P2_10 ((1)) /**< Input for EINT_0 comes from P2.10 */ +#define LOC_EINT_1_P0_30 ((0)) /**< Input for EINT_1 comes from P0.30 */ +#define LOC_EINT_1_P2_11 ((1)) /**< Input for EINT_1 comes from P2.11 */ +#define LOC_I2C0_SCL_P1_31 ((0)) /**< Input for I2C0_SCL comes from P1.31 */ +#define LOC_I2C0_SCL_P0_28 ((1)) /**< Input for I2C0_SCL comes from P0.28 */ +#define LOC_I2C0_SCL_P5_3 ((2)) /**< Input for I2C0_SCL comes from P5.3 */ +#define LOC_I2C0_SDA_P1_30 ((0)) /**< Input for I2C0_SDA comes from P1.30 */ +#define LOC_I2C0_SDA_P0_27 ((1)) /**< Input for I2C0_SDA comes from P0.27 */ +#define LOC_I2C0_SDA_P5_2 ((2)) /**< Input for I2C0_SDA comes from P5.2 */ +#define LOC_I2C1_SCL_P0_1 ((0)) /**< Input for I2C1_SCL comes from P0.1 */ +#define LOC_I2C1_SCL_P2_15 ((1)) /**< Input for I2C1_SCL comes from P2.15 */ +#define LOC_I2C1_SCL_P0_20 ((2)) /**< Input for I2C1_SCL comes from P0.20 */ +#define LOC_I2C1_SDA_P2_14 ((0)) /**< Input for I2C1_SDA comes from P2.14 */ +#define LOC_I2C1_SDA_P0_0 ((1)) /**< Input for I2C1_SDA comes from P0.0 */ +#define LOC_I2C1_SDA_P0_19 ((2)) /**< Input for I2C1_SDA comes from P0.19 */ +#define LOC_I2C2_SCL_P2_31 ((0)) /**< Input for I2C2_SCL comes from P2.31 */ +#define LOC_I2C2_SCL_P0_11 ((1)) /**< Input for I2C2_SCL comes from P0.11 */ +#define LOC_I2C2_SCL_P4_21 ((2)) /**< Input for I2C2_SCL comes from P4.21 */ +#define LOC_I2C2_SCL_P4_29 ((3)) /**< Input for I2C2_SCL comes from P4.29 */ +#define LOC_I2C2_SDA_P2_30 ((0)) /**< Input for I2C2_SDA comes from P2.30 */ +#define LOC_I2C2_SDA_P0_10 ((1)) /**< Input for I2C2_SDA comes from P0.10 */ +#define LOC_I2C2_SDA_P4_20 ((2)) /**< Input for I2C2_SDA comes from P4.20 */ +#define LOC_I2C2_SDA_P1_15 ((3)) /**< Input for I2C2_SDA comes from P1.15 */ +#define LOC_I2S_RX_SCK_P0_23 ((0)) /**< Input for I2S_RX_SCK comes from P0.23 */ +#define LOC_I2S_RX_SCK_P0_4 ((1)) /**< Input for I2S_RX_SCK comes from P0.4 */ +#define LOC_I2S_RX_SDA_P0_25 ((0)) /**< Input for I2S_RX_SDA comes from P0.25 */ +#define LOC_I2S_RX_SDA_P0_6 ((1)) /**< Input for I2S_RX_SDA comes from P0.6 */ +#define LOC_I2S_RX_WS_P0_24 ((0)) /**< Input for I2S_RX_WS comes from P0.24 */ +#define LOC_I2S_RX_WS_P0_5 ((1)) /**< Input for I2S_RX_WS comes from P0.5 */ +#define LOC_I2S_TX_SCK_P2_11 ((0)) /**< Input for I2S_TX_SCK comes from P2.11 */ +#define LOC_I2S_TX_SCK_P0_7 ((1)) /**< Input for I2S_TX_SCK comes from P0.7 */ +#define LOC_I2S_TX_WS_P2_12 ((0)) /**< Input for I2S_TX_WS comes from P2.12 */ +#define LOC_I2S_TX_WS_P0_8 ((1)) /**< Input for I2S_TX_WS comes from P0.8 */ +#define LOC_PWM0_CAP_0_P1_12 ((0)) /**< Input for PWM0_CAP_0 comes from P1.12 */ +#define LOC_PWM0_CAP_0_P3_22 ((1)) /**< Input for PWM0_CAP_0 comes from P3.22 */ +#define LOC_PWM1_CAP_0_P3_23 ((0)) /**< Input for PWM1_CAP_0 comes from P3.23 */ +#define LOC_PWM1_CAP_0_P1_28 ((1)) /**< Input for PWM1_CAP_0 comes from P1.28 */ +#define LOC_PWM1_CAP_0_P2_6 ((2)) /**< Input for PWM1_CAP_0 comes from P2.6 */ +#define LOC_SD_CMD_P0_20 ((0)) /**< Input for SD_CMD comes from P0.20 */ +#define LOC_SD_CMD_P1_3 ((1)) /**< Input for SD_CMD comes from P1.3 */ +#define LOC_SD_DAT_0_P0_22 ((0)) /**< Input for SD_DAT_0 comes from P0.22 */ +#define LOC_SD_DAT_0_P1_6 ((1)) /**< Input for SD_DAT_0 comes from P1.6 */ +#define LOC_SD_DAT_1_P2_11 ((0)) /**< Input for SD_DAT_1 comes from P2.11 */ +#define LOC_SD_DAT_1_P1_7 ((1)) /**< Input for SD_DAT_1 comes from P1.7 */ +#define LOC_SD_DAT_2_P2_12 ((0)) /**< Input for SD_DAT_2 comes from P2.12 */ +#define LOC_SD_DAT_2_P1_11 ((1)) /**< Input for SD_DAT_2 comes from P1.11 */ +#define LOC_SD_DAT_3_P2_13 ((0)) /**< Input for SD_DAT_3 comes from P2.13 */ +#define LOC_SD_DAT_3_P1_12 ((1)) /**< Input for SD_DAT_3 comes from P1.12 */ +#define LOC_SSP0_MISO_P2_26 ((0)) /**< Input for SSP0_MISO comes from P2.26 */ +#define LOC_SSP0_MISO_P1_23 ((1)) /**< Input for SSP0_MISO comes from P1_23 */ +#define LOC_SSP0_MISO_P0_17 ((2)) /**< Input for SSP0_MISO comes from P0_17 */ +#define LOC_SSP0_MOSI_P2_27 ((0)) /**< Input for SSP0_MOSI comes from P2.27 */ +#define LOC_SSP0_MOSI_P1_24 ((1)) /**< Input for SSP0_MOSI comes from P1.24 */ +#define LOC_SSP0_MOSI_P0_18 ((2)) /**< Input for SSP0_MOSI comes from P0.18 */ +#define LOC_SSP0_SCK_P1_20 ((0)) /**< Input for SSP0_SCK comes from P1.20 */ +#define LOC_SSP0_SCK_P2_22 ((1)) /**< Input for SSP0_SCK comes from P2.22 */ +#define LOC_SSP0_SCK_P0_15 ((2)) /**< Input for SSP0_SCK comes from P0_15 */ +#define LOC_SSP0_SSEL_P2_23 ((0)) /**< Input for SSP0_SSEL comes from P2.23 */ +#define LOC_SSP0_SSEL_P1_21 ((1)) /**< Input for SSP0_SSEL comes from P1.21 */ +#define LOC_SSP0_SSEL_P1_28 ((2)) /**< Input for SSP0_SSEL comes from P1.28 */ +#define LOC_SSP0_SSEL_P0_16 ((3)) /**< Input for SSP0_SSEL comes from P0.16 */ +#define LOC_SSP1_MISO_P0_12 ((0)) /**< Input for SSP1_MISO comes from P0.12 */ +#define LOC_SSP1_MISO_P1_18 ((1)) /**< Input for SSP1_MISO comes from P1.18 */ +#define LOC_SSP1_MISO_P4_22 ((2)) /**< Input for SSP1_MISO comes from P4_22 */ +#define LOC_SSP1_MISO_P0_8 ((3)) /**< Input for SSP1_MISO comes from P0.8 */ +#define LOC_SSP1_MOSI_P0_13 ((0)) /**< Input for SSP1_MOSI comes from P0.13 */ +#define LOC_SSP1_MOSI_P1_22 ((1)) /**< Input for SSP1_MOSI comes from P1.22 */ +#define LOC_SSP1_MOSI_P4_23 ((2)) /**< Input for SSP1_MOSI comes from P4.23 */ +#define LOC_SSP1_MOSI_P0_9 ((3)) /**< Input for SSP1_MOSI comes from P0.9 */ +#define LOC_SSP1_SCK_P1_31 ((0)) /**< Input for SSP1_SCK comes from P1.31 */ +#define LOC_SSP1_SCK_P1_19 ((1)) /**< Input for SSP1_SCK comes from P1.19 */ +#define LOC_SSP1_SCK_P4_20 ((2)) /**< Input for SSP1_SCK comes from P4_20 */ +#define LOC_SSP1_SCK_P0_7 ((3)) /**< Input for SSP1_SCK comes from P0_7 */ +#define LOC_SSP1_SSEL_P0_14 ((0)) /**< Input for SSP1_SSEL comes from P0.14 */ +#define LOC_SSP1_SSEL_P1_26 ((1)) /**< Input for SSP1_SSEL comes from P1.26 */ +#define LOC_SSP1_SSEL_P4_21 ((2)) /**< Input for SSP1_SSEL comes from P4.21 */ +#define LOC_SSP1_SSEL_P0_6 ((3)) /**< Input for SSP1_SSEL comes from P0.6 */ +#define LOC_SSP2_MISO_P1_4 ((1)) /**< Input for SSP2_MISO comes from P1.4 */ +#define LOC_SSP2_MOSI_P1_1 ((1)) /**< Input for SSP2_MOSI comes from P1.1 */ +#define LOC_SSP2_SCK_P1_0 ((1)) /**< Input for SSP2_SCK comes from P1.0 */ +#define LOC_SSP2_SSEL_P1_8 ((1)) /**< Input for SSP2_SSEL comes from P1.8 */ +#define LOC_T0_CAP_0_P3_23 ((0)) /**< Input for T0_CAP_0 comes from P3.23 */ +#define LOC_T0_CAP_0_P1_26 ((1)) /**< Input for T0_CAP_0 comes from P1.26 */ +#define LOC_T0_CAP_1_P3_24 ((0)) /**< Input for T0_CAP_1 comes from P3.24 */ +#define LOC_T0_CAP_1_P1_27 ((1)) /**< Input for T0_CAP_1 comes from P1.27 */ +#define LOC_T1_CAP_0_P1_18 ((0)) /**< Input for T1_CAP_0 comes from P1.18 */ +#define LOC_T1_CAP_0_P3_27 ((1)) /**< Input for T1_CAP_0 comes from P3.27 */ +#define LOC_T1_CAP_1_P3_28 ((0)) /**< Input for T1_CAP_1 comes from P3.28 */ +#define LOC_T1_CAP_1_P1_19 ((1)) /**< Input for T1_CAP_1 comes from P1.19 */ +#define LOC_T2_CAP_0_P2_14 ((0)) /**< Input for T2_CAP_0 comes from P2.14 */ +#define LOC_T2_CAP_0_P2_6 ((1)) /**< Input for T2_CAP_0 comes from P2.6 */ +#define LOC_T2_CAP_0_P0_4 ((2)) /**< Input for T2_CAP_0 comes from P0.4 */ +#define LOC_T2_CAP_0_P1_14 ((3)) /**< Input for T2_CAP_0 comes from P1.14 */ +#define LOC_T2_CAP_1_P2_15 ((0)) /**< Input for T2_CAP_1 comes from P2.15 */ +#define LOC_T2_CAP_1_P0_5 ((1)) /**< Input for T2_CAP_1 comes from P0.5 */ +#define LOC_T3_CAP_0_P0_23 ((0)) /**< Input for T3_CAP_0 comes from P0.23 */ +#define LOC_T3_CAP_0_P2_22 ((1)) /**< Input for T3_CAP_0 comes from P2.22 */ +#define LOC_T3_CAP_0_P1_10 ((2)) /**< Input for T3_CAP_0 comes from P1.10 */ +#define LOC_T3_CAP_1_P0_24 ((0)) /**< Input for T3_CAP_1 comes from P0.24 */ +#define LOC_T3_CAP_1_P2_23 ((1)) /**< Input for T3_CAP_1 comes from P2.23 */ +#define LOC_T3_CAP_1_P1_0 ((2)) /**< Input for T3_CAP_1 comes from P1.0 */ +#define LOC_U0_RXD_P0_1 ((0)) /**< Input for U0_RXD comes from P0.1 */ +#define LOC_U0_RXD_P0_3 ((1)) /**< Input for U0_RXD comes from P0.3 */ +#define LOC_U1_CTS_P0_17 ((0)) /**< Input for U1_CTS comes from P0.17 */ +#define LOC_U1_CTS_P2_8 ((1)) /**< Input for U1_CTS comes from P2.8 */ +#define LOC_U1_CTS_P2_2 ((2)) /**< Input for U1_CTS comes from P2.2 */ +#define LOC_U1_CTS_P3_18 ((3)) /**< Input for U1_CTS comes from P3.18 */ +#define LOC_U1_DCD_P0_18 ((0)) /**< Input for U1_DCD comes from P0.18 */ +#define LOC_U1_DCD_P2_3 ((1)) /**< Input for U1_DCD comes from P2.3 */ +#define LOC_U1_DCD_P3_19 ((2)) /**< Input for U1_DCD comes from P3_19 */ +#define LOC_U1_DSR_P0_19 ((0)) /**< Input for U1_DSR comes from P0.19 */ +#define LOC_U1_DSR_P2_4 ((1)) /**< Input for U1_DSR comes from P2.4 */ +#define LOC_U1_DSR_P3_20 ((2)) /**< Input for U1_DSR comes from P0.19 */ +#define LOC_U1_RI_P0_21 ((0)) /**< Input for U1_RI comes from P0.21 */ +#define LOC_U1_RI_P2_6 ((1)) /**< Input for U1_RI comes from P2.6 */ +#define LOC_U1_RI_P3_22 ((2)) /**< Input for U1_RI comes from P3.22 */ +#define LOC_U1_RXD_P0_16 ((0)) /**< Input for U1_RXD comes from P0.16 */ +#define LOC_U1_RXD_P3_17 ((1)) /**< Input for U1_RXD comes from P3.17 */ +#define LOC_U1_RXD_P2_1 ((2)) /**< Input for U1_RXD comes from P2.1 */ +#define LOC_U2_RXD_P0_11 ((0)) /**< Input for U2_RXD comes from P0.11 */ +#define LOC_U2_RXD_P4_23 ((1)) /**< Input for U2_RXD comes from P4.23 */ +#define LOC_U2_RXD_P2_9 ((2)) /**< Input for U2_RXD comes from P2.9 */ +#define LOC_U3_RXD_P0_26 ((0)) /**< Input for U3_RXD comes from P0.26 */ +#define LOC_U3_RXD_P0_1 ((1)) /**< Input for U3_RXD comes from P0.1 */ +#define LOC_U3_RXD_P4_29 ((2)) /**< Input for U3_RXD comes from P4.29 */ +#define LOC_U3_RXD_P0_3 ((3)) /**< Input for U3_RXD comes from P0.3 */ +#define LOC_U4_RXD_P2_9 ((0)) /**< Input for U4_RXD comes from P2.9 */ +#define LOC_U4_RXD_P5_3 ((1)) /**< Input for U4_RXD comes from P5.3 */ +#define LOC_USB_SCL_P0_28 ((0)) /**< Input for USB_SCL comes from P0.28 */ +#define LOC_USB_SCL_P1_28 ((1)) /**< Input for USB_SCL comes from P1.28 */ +#define LOC_USB_SDA_P0_27 ((0)) /**< Input for USB_SDA comes from P0.27 */ +#define LOC_USB_SDA_P1_29 ((1)) /**< Input for USB_SDA comes from P1.29 */ /** * @} @@ -206,32 +206,32 @@ /** @defgroup PINSEL_Public_Types PINSEL Public Types * @{ */ - + typedef enum { - PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */ - PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */ - PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */ - PINSEL_BASICMODE_REPEATER /**< Repeater mode */ + PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */ + PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */ + PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */ + PINSEL_BASICMODE_REPEATER /**< Repeater mode */ }PinSel_BasicMode; typedef enum { - /** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */ - PINSEL_I2CMODE_FAST_STANDARD = 0, - /** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */ - PINSEL_I2CMODE_OPENDRAINIO, - /** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */ - PINSEL_I2CMODE_FASTMODEPLUS, - /** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */ - PINSEL_I2CMODE_HIDRIVE_OPENDRAIN + /** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */ + PINSEL_I2CMODE_FAST_STANDARD = 0, + /** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */ + PINSEL_I2CMODE_OPENDRAINIO, + /** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */ + PINSEL_I2CMODE_FASTMODEPLUS, + /** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */ + PINSEL_I2CMODE_HIDRIVE_OPENDRAIN }PinSel_I2cMode; /** * @} */ - + /* Public Functions ----------------------------------------------------------- */ /** @defgroup PINSEL_Public_Functions diff --git a/bsp/lpc178x/drivers/lpc177x_8x_uart.c b/bsp/lpc178x/drivers/lpc177x_8x_uart.c index 4e0f4e1d7c..7661a32b13 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_uart.c +++ b/bsp/lpc178x/drivers/lpc177x_8x_uart.c @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_uart.c 2011-06-02 +* $Id$ lpc177x_8x_uart.c 2011-06-02 *//** -* @file lpc177x_8x_uart.c -* @brief Contains all functions support for UART firmware library -* on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_uart.c +* @brief Contains all functions support for UART firmware library +* on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -39,127 +39,127 @@ static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate); /*********************************************************************//** - * @brief Determines best dividers to get a target clock rate - * @param[in] UARTx Pointer to selected UART peripheral, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] baudrate Desired UART baud rate. - * @return Error status, could be: - * - SUCCESS - * - ERROR + * @brief Determines best dividers to get a target clock rate + * @param[in] UARTx Pointer to selected UART peripheral, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] baudrate Desired UART baud rate. + * @return Error status, could be: + * - SUCCESS + * - ERROR **********************************************************************/ static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate) { - Status errorStatus = ERROR; + Status errorStatus = ERROR; - uint32_t uClk; - uint32_t d, m, bestd, bestm, tmp; - uint64_t best_divisor, divisor; - uint32_t current_error, best_error; - uint32_t recalcbaud; + uint32_t uClk; + uint32_t d, m, bestd, bestm, tmp; + uint64_t best_divisor, divisor; + uint32_t current_error, best_error; + uint32_t recalcbaud; - /* get UART block clock */ - uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); + /* get UART block clock */ + uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER); - /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers - * The formula is : - * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) - * It involves floating point calculations. That's the reason the formulae are adjusted with - * Multiply and divide method.*/ - - /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: - * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ - best_error = 0xFFFFFFFF; /* Worst case */ - bestd = 0; - bestm = 0; - best_divisor = 0; - - for (m = 1 ; m <= 15 ;m++) - { - for (d = 0 ; d < m ; d++) - { - divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d)); - current_error = divisor & 0xFFFFFFFF; + /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers + * The formula is : + * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) + * It involves floating point calculations. That's the reason the formulae are adjusted with + * Multiply and divide method.*/ - tmp = divisor>>32; + /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: + * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ + best_error = 0xFFFFFFFF; /* Worst case */ + bestd = 0; + bestm = 0; + best_divisor = 0; - /* Adjust error */ - if(current_error > ((uint32_t)1<<31)) - { - current_error = -current_error; - tmp++; - } + for (m = 1 ; m <= 15 ;m++) + { + for (d = 0 ; d < m ; d++) + { + divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d)); + current_error = divisor & 0xFFFFFFFF; - /* Out of range */ - if(tmp < 1 || tmp > 65536) - continue; + tmp = divisor>>32; - if( current_error < best_error) - { - best_error = current_error; - best_divisor = tmp; - bestd = d; - bestm = m; - - if(best_error == 0) - break; - } - } /* end of inner for loop */ + /* Adjust error */ + if(current_error > ((uint32_t)1<<31)) + { + current_error = -current_error; + tmp++; + } - if (best_error == 0) - break; - } /* end of outer for loop */ + /* Out of range */ + if(tmp < 1 || tmp > 65536) + continue; - /* can not find best match */ - if(best_divisor == 0) - return ERROR; + if( current_error < best_error) + { + best_error = current_error; + best_divisor = tmp; + bestd = d; + bestm = m; - recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd)); + if(best_error == 0) + break; + } + } /* end of inner for loop */ - /* reuse best_error to evaluate baud error*/ - if(baudrate > recalcbaud) - best_error = baudrate - recalcbaud; - else - best_error = recalcbaud -baudrate; + if (best_error == 0) + break; + } /* end of outer for loop */ - best_error = best_error * 100 / baudrate; + /* can not find best match */ + if(best_divisor == 0) + return ERROR; - if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) - { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; - - ((LPC_UART1_TypeDef *)UARTx)->DLM = UART_LOAD_DLM(best_divisor); - - ((LPC_UART1_TypeDef *)UARTx)->DLL = UART_LOAD_DLL(best_divisor); - - /* Then reset DLAB bit */ - ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - - ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm) - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - else - { - UARTx->LCR |= UART_LCR_DLAB_EN; - - UARTx->DLM = UART_LOAD_DLM(best_divisor); - - UARTx->DLL = UART_LOAD_DLL(best_divisor); - - /* Then reset DLAB bit */ - UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; - - UARTx->FDR = (UART_FDR_MULVAL(bestm) \ - | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; - } - errorStatus = SUCCESS; - } + recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd)); - return errorStatus; + /* reuse best_error to evaluate baud error*/ + if(baudrate > recalcbaud) + best_error = baudrate - recalcbaud; + else + best_error = recalcbaud -baudrate; + + best_error = best_error * 100 / baudrate; + + if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) + { + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; + + ((LPC_UART1_TypeDef *)UARTx)->DLM = UART_LOAD_DLM(best_divisor); + + ((LPC_UART1_TypeDef *)UARTx)->DLL = UART_LOAD_DLL(best_divisor); + + /* Then reset DLAB bit */ + ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; + + ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm) + | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; + } + else + { + UARTx->LCR |= UART_LCR_DLAB_EN; + + UARTx->DLM = UART_LOAD_DLM(best_divisor); + + UARTx->DLL = UART_LOAD_DLL(best_divisor); + + /* Then reset DLAB bit */ + UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; + + UARTx->FDR = (UART_FDR_MULVAL(bestm) \ + | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; + } + errorStatus = SUCCESS; + } + + return errorStatus; } /* End of Private Functions ---------------------------------------------------- */ @@ -171,1192 +171,1192 @@ static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate) */ /* UART Init/DeInit functions -------------------------------------------------*/ /********************************************************************//** - * @brief Initializes the UARTx peripheral according to the specified + * @brief Initializes the UARTx peripheral according to the specified * parameters in the UART_ConfigStruct. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * - LPC_UART4: UART4 peripheral - * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * - LPC_UART4: UART4 peripheral + * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure * that contains the configuration information for the * specified UART peripheral. - * @return None + * @return None *********************************************************************/ void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct) { - uint32_t tmp; + uint32_t tmp; - if(UARTx == LPC_UART0) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE); - } - if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE); - } - if(UARTx == LPC_UART2) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE); - } - if(UARTx == LPC_UART3) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE); - } + if(UARTx == LPC_UART0) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE); + } + if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE); + } + if(UARTx == LPC_UART2) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE); + } + if(UARTx == LPC_UART3) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE); + } - /* FIFOs are empty */ - UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); + /* FIFOs are empty */ + UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); - // Disable FIFO - UARTx->FCR = 0; + // Disable FIFO + UARTx->FCR = 0; - // Dummy reading - while (UARTx->LSR & UART_LSR_RDR) - { - tmp = UARTx->RBR; - } + // Dummy reading + while (UARTx->LSR & UART_LSR_RDR) + { + tmp = UARTx->RBR; + } - UARTx->TER = UART_TER_TXEN; + UARTx->TER = UART_TER_TXEN; - // Wait for current transmit complete - while (!(UARTx->LSR & UART_LSR_THRE)); + // Wait for current transmit complete + while (!(UARTx->LSR & UART_LSR_THRE)); - // Disable Tx - UARTx->TER = 0; + // Disable Tx + UARTx->TER = 0; - // Disable interrupt - UARTx->IER = 0; + // Disable interrupt + UARTx->IER = 0; - // Set LCR to default state - UARTx->LCR = 0; + // Set LCR to default state + UARTx->LCR = 0; - // Set ACR to default state - UARTx->ACR = 0; + // Set ACR to default state + UARTx->ACR = 0; - // Set RS485 control to default state - UARTx->RS485CTRL = 0; + // Set RS485 control to default state + UARTx->RS485CTRL = 0; - // Set RS485 delay timer to default state - UARTx->RS485DLY = 0; + // Set RS485 delay timer to default state + UARTx->RS485DLY = 0; - // Set RS485 addr match to default state - UARTx->ADRMATCH = 0; + // Set RS485 addr match to default state + UARTx->ADRMATCH = 0; - // Dummy reading - tmp = UARTx->LSR; + // Dummy reading + tmp = UARTx->LSR; - if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - // Set Modem Control to default state - ((LPC_UART1_TypeDef *)UARTx)->MCR = 0; + if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + // Set Modem Control to default state + ((LPC_UART1_TypeDef *)UARTx)->MCR = 0; - //Dummy Reading to Clear Status - tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR; - } - else - { - // Set IrDA to default state for all UART other than UART1 - UARTx->ICR = 0; - } + //Dummy Reading to Clear Status + tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR; + } + else + { + // Set IrDA to default state for all UART other than UART1 + UARTx->ICR = 0; + } - // Set Line Control register ---------------------------- + // Set Line Control register ---------------------------- - uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate)); + uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate)); - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ - & UART_LCR_BITMASK; - } - else - { - tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; - } + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \ + & UART_LCR_BITMASK; + } + else + { + tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; + } - switch (UART_ConfigStruct->Databits) - { - case UART_DATABIT_5: - tmp |= UART_LCR_WLEN5; - break; + switch (UART_ConfigStruct->Databits) + { + case UART_DATABIT_5: + tmp |= UART_LCR_WLEN5; + break; - case UART_DATABIT_6: - tmp |= UART_LCR_WLEN6; - break; + case UART_DATABIT_6: + tmp |= UART_LCR_WLEN6; + break; - case UART_DATABIT_7: - tmp |= UART_LCR_WLEN7; - break; + case UART_DATABIT_7: + tmp |= UART_LCR_WLEN7; + break; - case UART_DATABIT_8: + case UART_DATABIT_8: - default: - tmp |= UART_LCR_WLEN8; - break; - } + default: + tmp |= UART_LCR_WLEN8; + break; + } - if (UART_ConfigStruct->Parity == UART_PARITY_NONE) - { - // Do nothing... - } - else - { - tmp |= UART_LCR_PARITY_EN; - switch (UART_ConfigStruct->Parity) - { - case UART_PARITY_ODD: - tmp |= UART_LCR_PARITY_ODD; - break; + if (UART_ConfigStruct->Parity == UART_PARITY_NONE) + { + // Do nothing... + } + else + { + tmp |= UART_LCR_PARITY_EN; + switch (UART_ConfigStruct->Parity) + { + case UART_PARITY_ODD: + tmp |= UART_LCR_PARITY_ODD; + break; - case UART_PARITY_EVEN: - tmp |= UART_LCR_PARITY_EVEN; - break; + case UART_PARITY_EVEN: + tmp |= UART_LCR_PARITY_EVEN; + break; - case UART_PARITY_SP_1: - tmp |= UART_LCR_PARITY_F_1; - break; + case UART_PARITY_SP_1: + tmp |= UART_LCR_PARITY_F_1; + break; - case UART_PARITY_SP_0: - tmp |= UART_LCR_PARITY_F_0; - break; + case UART_PARITY_SP_0: + tmp |= UART_LCR_PARITY_F_0; + break; - default: - break; - } - } + default: + break; + } + } - switch (UART_ConfigStruct->Stopbits) - { - case UART_STOPBIT_2: - tmp |= UART_LCR_STOPBIT_SEL; - break; + switch (UART_ConfigStruct->Stopbits) + { + case UART_STOPBIT_2: + tmp |= UART_LCR_STOPBIT_SEL; + break; - case UART_STOPBIT_1: + case UART_STOPBIT_1: - default: - // Do no thing - break; - } + default: + // Do no thing + break; + } - // Write back to LCR, configure FIFO and Disable Tx - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } - else - { - UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); - } + // Write back to LCR, configure FIFO and Disable Tx + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); + } + else + { + UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK); + } } /*********************************************************************//** - * @brief De-initializes the UARTx peripheral registers to their + * @brief De-initializes the UARTx peripheral registers to their * default reset values. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @return None + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return None **********************************************************************/ void UART_DeInit(LPC_UART_TypeDef* UARTx) { - UART_TxCmd(UARTx, DISABLE); + UART_TxCmd(UARTx, DISABLE); - if (UARTx == LPC_UART0) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE); - } + if (UARTx == LPC_UART0) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE); + } - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE); - } + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE); + } - if (UARTx == LPC_UART2) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE); - } + if (UARTx == LPC_UART2) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE); + } - if (UARTx == LPC_UART3) - { - /* Set up clock and power for UART module */ - CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE); - } + if (UARTx == LPC_UART3) + { + /* Set up clock and power for UART module */ + CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE); + } } /*****************************************************************************//** -* @brief Fills each UART_InitStruct member with its default value: -* - 9600 bps -* - 8-bit data -* - 1 Stopbit -* - None Parity -* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure +* @brief Fills each UART_InitStruct member with its default value: +* - 9600 bps +* - 8-bit data +* - 1 Stopbit +* - None Parity +* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure * which will be initialized. -* @return None +* @return None *******************************************************************************/ void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct) { - UART_InitStruct->Baud_rate = 9600; + UART_InitStruct->Baud_rate = 9600; - UART_InitStruct->Databits = UART_DATABIT_8; + UART_InitStruct->Databits = UART_DATABIT_8; - UART_InitStruct->Parity = UART_PARITY_NONE; + UART_InitStruct->Parity = UART_PARITY_NONE; - UART_InitStruct->Stopbits = UART_STOPBIT_1; + UART_InitStruct->Stopbits = UART_STOPBIT_1; } /* UART Send/Recieve functions -------------------------------------------------*/ /*********************************************************************//** - * @brief Transmit a single data through UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] Data Data to transmit (must be 8-bit long) - * @return None + * @brief Transmit a single data through UART peripheral + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] Data Data to transmit (must be 8-bit long) + * @return None **********************************************************************/ void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data) { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->THR = Data & UART_THR_MASKBIT; - } - else - { - UARTx->THR = Data & UART_THR_MASKBIT; - } + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->THR = Data & UART_THR_MASKBIT; + } + else + { + UARTx->THR = Data & UART_THR_MASKBIT; + } } /*********************************************************************//** - * @brief Receive a single data from UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @return Data received + * @brief Receive a single data from UART peripheral + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return Data received **********************************************************************/ uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx) { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - return (((LPC_UART1_TypeDef *)UARTx)->RBR & UART_RBR_MASKBIT); - } - else - { - return (UARTx->RBR & UART_RBR_MASKBIT); - } + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + return (((LPC_UART1_TypeDef *)UARTx)->RBR & UART_RBR_MASKBIT); + } + else + { + return (UARTx->RBR & UART_RBR_MASKBIT); + } } /*********************************************************************//** - * @brief Send a block of data via UART peripheral - * @param[in] UARTx Selected UART peripheral used to send data, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] txbuf Pointer to Transmit buffer - * @param[in] buflen Length of Transmit buffer - * @param[in] flag Flag used in UART transfer, should be - * NONE_BLOCKING or BLOCKING - * @return Number of bytes sent. + * @brief Send a block of data via UART peripheral + * @param[in] UARTx Selected UART peripheral used to send data, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] txbuf Pointer to Transmit buffer + * @param[in] buflen Length of Transmit buffer + * @param[in] flag Flag used in UART transfer, should be + * NONE_BLOCKING or BLOCKING + * @return Number of bytes sent. * * Note: when using UART in BLOCKING mode, a time-out condition is used * via defined symbol UART_BLOCKING_TIMEOUT. **********************************************************************/ uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, - uint32_t buflen, TRANSFER_BLOCK_Type flag) + uint32_t buflen, TRANSFER_BLOCK_Type flag) { - uint32_t bToSend, bSent, timeOut, fifo_cnt; - uint8_t *pChar = txbuf; + uint32_t bToSend, bSent, timeOut, fifo_cnt; + uint8_t *pChar = txbuf; - bToSend = buflen; + bToSend = buflen; - // blocking mode - if (flag == BLOCKING) - { - bSent = 0; - while (bToSend) - { - timeOut = UART_BLOCKING_TIMEOUT; + // blocking mode + if (flag == BLOCKING) + { + bSent = 0; + while (bToSend) + { + timeOut = UART_BLOCKING_TIMEOUT; - // Wait for THR empty with timeout - while (!(UARTx->LSR & UART_LSR_THRE)) - { - if (timeOut == 0) - break; + // Wait for THR empty with timeout + while (!(UARTx->LSR & UART_LSR_THRE)) + { + if (timeOut == 0) + break; - timeOut--; - } + timeOut--; + } - // Time out! - if(timeOut == 0) - break; + // Time out! + if(timeOut == 0) + break; - fifo_cnt = UART_TX_FIFO_SIZE; + fifo_cnt = UART_TX_FIFO_SIZE; - while (fifo_cnt && bToSend) - { - UART_SendByte(UARTx, (*pChar++)); + while (fifo_cnt && bToSend) + { + UART_SendByte(UARTx, (*pChar++)); - fifo_cnt--; + fifo_cnt--; - bToSend--; + bToSend--; - bSent++; - } - } - } + bSent++; + } + } + } - // None blocking mode - else - { - bSent = 0; - while (bToSend) - { - if (bToSend == 0) - break; + // None blocking mode + else + { + bSent = 0; + while (bToSend) + { + if (bToSend == 0) + break; - if (!(UARTx->LSR & UART_LSR_THRE)) - { - break; - } + if (!(UARTx->LSR & UART_LSR_THRE)) + { + break; + } - fifo_cnt = UART_TX_FIFO_SIZE; + fifo_cnt = UART_TX_FIFO_SIZE; - while (fifo_cnt && bToSend) - { - UART_SendByte(UARTx, (*pChar++)); + while (fifo_cnt && bToSend) + { + UART_SendByte(UARTx, (*pChar++)); - bToSend--; + bToSend--; - fifo_cnt--; + fifo_cnt--; - bSent++; - } - } - } + bSent++; + } + } + } - return bSent; + return bSent; } /*********************************************************************//** - * @brief Receive a block of data via UART peripheral - * @param[in] UARTx Selected UART peripheral used to send data, - * should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[out] rxbuf Pointer to Received buffer - * @param[in] buflen Length of Received buffer - * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING + * @brief Receive a block of data via UART peripheral + * @param[in] UARTx Selected UART peripheral used to send data, + * should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[out] rxbuf Pointer to Received buffer + * @param[in] buflen Length of Received buffer + * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING - * @return Number of bytes received + * @return Number of bytes received * * Note: when using UART in BLOCKING mode, a time-out condition is used * via defined symbol UART_BLOCKING_TIMEOUT. **********************************************************************/ uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, - uint32_t buflen, TRANSFER_BLOCK_Type flag) + uint32_t buflen, TRANSFER_BLOCK_Type flag) { - uint32_t bToRecv, bRecv, timeOut; - uint8_t *pChar = rxbuf; + uint32_t bToRecv, bRecv, timeOut; + uint8_t *pChar = rxbuf; - bToRecv = buflen; + bToRecv = buflen; - // Blocking mode - if (flag == BLOCKING) - { - bRecv = 0; - while (bToRecv) - { - timeOut = UART_BLOCKING_TIMEOUT; - while (!(UARTx->LSR & UART_LSR_RDR)) - { - if (timeOut == 0) - break; + // Blocking mode + if (flag == BLOCKING) + { + bRecv = 0; + while (bToRecv) + { + timeOut = UART_BLOCKING_TIMEOUT; + while (!(UARTx->LSR & UART_LSR_RDR)) + { + if (timeOut == 0) + break; - timeOut--; - } + timeOut--; + } - // Time out! - if(timeOut == 0) - break; + // Time out! + if(timeOut == 0) + break; - // Get data from the buffer - (*pChar++) = UART_ReceiveByte(UARTx); + // Get data from the buffer + (*pChar++) = UART_ReceiveByte(UARTx); - bToRecv--; + bToRecv--; - bRecv++; - } - } - // None blocking mode - else - { - bRecv = 0; - while (bToRecv) - { - if (!(UARTx->LSR & UART_LSR_RDR)) - { - break; - } - else - { - (*pChar++) = UART_ReceiveByte(UARTx); + bRecv++; + } + } + // None blocking mode + else + { + bRecv = 0; + while (bToRecv) + { + if (!(UARTx->LSR & UART_LSR_RDR)) + { + break; + } + else + { + (*pChar++) = UART_ReceiveByte(UARTx); - bRecv++; + bRecv++; - bToRecv--; - } - } - } + bToRecv--; + } + } + } - return bRecv; + return bRecv; } /*********************************************************************//** - * @brief Force BREAK character on UART line, output pin UARTx TXD is - forced to logic 0. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @return None + * @brief Force BREAK character on UART line, output pin UARTx TXD is + forced to logic 0. + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return None **********************************************************************/ void UART_ForceBreak(LPC_UART_TypeDef* UARTx) { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN; - } - else - { - UARTx->LCR |= UART_LCR_BREAK_EN; - } + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN; + } + else + { + UARTx->LCR |= UART_LCR_BREAK_EN; + } } /********************************************************************//** - * @brief Enable or disable specified UART interrupt. - * @param[in] UARTx UART peripheral selected, should be - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] UARTIntCfg Specifies the interrupt flag, - * should be one of the following: - - UART_INTCFG_RBR : RBR Interrupt enable - - UART_INTCFG_THRE : THR Interrupt enable - - UART_INTCFG_RLS : RX line status interrupt enable - - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) - - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) - - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt - - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt - * @param[in] NewState New state of specified UART interrupt type, - * should be: - * - ENALBE: Enable this UART interrupt type. -* - DISALBE: Disable this UART interrupt type. - * @return None + * @brief Enable or disable specified UART interrupt. + * @param[in] UARTx UART peripheral selected, should be + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] UARTIntCfg Specifies the interrupt flag, + * should be one of the following: + - UART_INTCFG_RBR : RBR Interrupt enable + - UART_INTCFG_THRE : THR Interrupt enable + - UART_INTCFG_RLS : RX line status interrupt enable + - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) + - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) + - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt + - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt + * @param[in] NewState New state of specified UART interrupt type, + * should be: + * - ENALBE: Enable this UART interrupt type. +* - DISALBE: Disable this UART interrupt type. + * @return None *********************************************************************/ void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState) { - uint32_t tmp; + uint32_t tmp; - switch(UARTIntCfg) - { - case UART_INTCFG_RBR: - tmp = UART_IER_RBRINT_EN; - break; + switch(UARTIntCfg) + { + case UART_INTCFG_RBR: + tmp = UART_IER_RBRINT_EN; + break; - case UART_INTCFG_THRE: - tmp = UART_IER_THREINT_EN; - break; + case UART_INTCFG_THRE: + tmp = UART_IER_THREINT_EN; + break; - case UART_INTCFG_RLS: - tmp = UART_IER_RLSINT_EN; - break; + case UART_INTCFG_RLS: + tmp = UART_IER_RLSINT_EN; + break; - case UART1_INTCFG_MS: - tmp = UART1_IER_MSINT_EN; - break; + case UART1_INTCFG_MS: + tmp = UART1_IER_MSINT_EN; + break; - case UART1_INTCFG_CTS: - tmp = UART1_IER_CTSINT_EN; - break; + case UART1_INTCFG_CTS: + tmp = UART1_IER_CTSINT_EN; + break; - case UART_INTCFG_ABEO: - tmp = UART_IER_ABEOINT_EN; - break; + case UART_INTCFG_ABEO: + tmp = UART_IER_ABEOINT_EN; + break; - case UART_INTCFG_ABTO: - tmp = UART_IER_ABTOINT_EN; - break; - } + case UART_INTCFG_ABTO: + tmp = UART_IER_ABTOINT_EN; + break; + } - if (NewState == ENABLE) - { - if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->IER |= tmp; - } - else - { - UARTx->IER |= tmp; - } - } - else - { - if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->IER &= (~tmp) & UART1_IER_BITMASK; - } - else - { - UARTx->IER &= (~tmp) & UART_IER_BITMASK; - } - } + if (NewState == ENABLE) + { + if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->IER |= tmp; + } + else + { + UARTx->IER |= tmp; + } + } + else + { + if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->IER &= (~tmp) & UART1_IER_BITMASK; + } + else + { + UARTx->IER &= (~tmp) & UART_IER_BITMASK; + } + } } /********************************************************************//** - * @brief Get current value of Line Status register in UART peripheral. - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @return Current value of Line Status register in UART peripheral. - * Note: The return value of this function must be ANDed with each member in - * UART_LS_Type enumeration to determine current flag status - * corresponding to each Line status type. Because some flags in - * Line Status register will be cleared after reading, the next reading - * Line Status register could not be correct. So this function used to - * read Line status register in one time only, then the return value - * used to check all flags. + * @brief Get current value of Line Status register in UART peripheral. + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return Current value of Line Status register in UART peripheral. + * Note: The return value of this function must be ANDed with each member in + * UART_LS_Type enumeration to determine current flag status + * corresponding to each Line status type. Because some flags in + * Line Status register will be cleared after reading, the next reading + * Line Status register could not be correct. So this function used to + * read Line status register in one time only, then the return value + * used to check all flags. *********************************************************************/ uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx) { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK); - } - else - { - return ((UARTx->LSR) & UART_LSR_BITMASK); - } + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK); + } + else + { + return ((UARTx->LSR) & UART_LSR_BITMASK); + } } /********************************************************************//** - * @brief Get Interrupt Identification value - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @return Current value of UART UIIR register in UART peripheral. + * @brief Get Interrupt Identification value + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return Current value of UART UIIR register in UART peripheral. *********************************************************************/ uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx) { - return (UARTx->IIR & 0x03CF); + return (UARTx->IIR & 0x03CF); } /*********************************************************************//** - * @brief Check whether if UART is busy or not - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @return RESET if UART is not busy, otherwise return SET. + * @brief Check whether if UART is busy or not + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @return RESET if UART is not busy, otherwise return SET. **********************************************************************/ FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx) { - if (UARTx->LSR & UART_LSR_TEMT) - { - return RESET; - } - else - { - return SET; - } + if (UARTx->LSR & UART_LSR_TEMT) + { + return RESET; + } + else + { + return SET; + } } /*********************************************************************//** - * @brief Configure FIFO function on selected UART peripheral - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that - * contains specified information about FIFO configuration - * @return none + * @brief Configure FIFO function on selected UART peripheral + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that + * contains specified information about FIFO configuration + * @return none **********************************************************************/ void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg) { - uint8_t tmp = 0; + uint8_t tmp = 0; - tmp |= UART_FCR_FIFO_EN; + tmp |= UART_FCR_FIFO_EN; - switch (FIFOCfg->FIFO_Level) - { - case UART_FIFO_TRGLEV0: - tmp |= UART_FCR_TRG_LEV0; - break; + switch (FIFOCfg->FIFO_Level) + { + case UART_FIFO_TRGLEV0: + tmp |= UART_FCR_TRG_LEV0; + break; - case UART_FIFO_TRGLEV1: - tmp |= UART_FCR_TRG_LEV1; - break; + case UART_FIFO_TRGLEV1: + tmp |= UART_FCR_TRG_LEV1; + break; - case UART_FIFO_TRGLEV2: - tmp |= UART_FCR_TRG_LEV2; - break; + case UART_FIFO_TRGLEV2: + tmp |= UART_FCR_TRG_LEV2; + break; - case UART_FIFO_TRGLEV3: + case UART_FIFO_TRGLEV3: - default: - tmp |= UART_FCR_TRG_LEV3; - break; - } + default: + tmp |= UART_FCR_TRG_LEV3; + break; + } - if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) - { - tmp |= UART_FCR_TX_RS; - } + if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) + { + tmp |= UART_FCR_TX_RS; + } - if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) - { - tmp |= UART_FCR_RX_RS; - } + if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) + { + tmp |= UART_FCR_RX_RS; + } - if (FIFOCfg->FIFO_DMAMode == ENABLE) - { - tmp |= UART_FCR_DMAMODE_SEL; - } + if (FIFOCfg->FIFO_DMAMode == ENABLE) + { + tmp |= UART_FCR_DMAMODE_SEL; + } - //write to FIFO control register - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK; - } - else - { - UARTx->FCR = tmp & UART_FCR_BITMASK; - } + //write to FIFO control register + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK; + } + else + { + UARTx->FCR = tmp & UART_FCR_BITMASK; + } } /*****************************************************************************//** -* @brief Fills each UART_FIFOInitStruct member with its default value: -* - FIFO_DMAMode = DISABLE -* - FIFO_Level = UART_FIFO_TRGLEV0 -* - FIFO_ResetRxBuf = ENABLE -* - FIFO_ResetTxBuf = ENABLE -* - FIFO_State = ENABLE +* @brief Fills each UART_FIFOInitStruct member with its default value: +* - FIFO_DMAMode = DISABLE +* - FIFO_Level = UART_FIFO_TRGLEV0 +* - FIFO_ResetRxBuf = ENABLE +* - FIFO_ResetTxBuf = ENABLE +* - FIFO_State = ENABLE -* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure +* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure * which will be initialized. -* @return None +* @return None *******************************************************************************/ void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) { - UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; + UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; - UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0; + UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0; - UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; + UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; - UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; + UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; } /*********************************************************************//** - * @brief Start/Stop Auto Baudrate activity - * @param[in] UARTx UART peripheral selected, should be - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that - * contains specified information about UART - * auto baudrate configuration - * @param[in] NewState New State of Auto baudrate activity, should be: - * - ENABLE: Start this activity - * - DISABLE: Stop this activity - * Note: Auto-baudrate mode enable bit will be cleared once this mode - * completed. - * @return none + * @brief Start/Stop Auto Baudrate activity + * @param[in] UARTx UART peripheral selected, should be + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that + * contains specified information about UART + * auto baudrate configuration + * @param[in] NewState New State of Auto baudrate activity, should be: + * - ENABLE: Start this activity + * - DISABLE: Stop this activity + * Note: Auto-baudrate mode enable bit will be cleared once this mode + * completed. + * @return none **********************************************************************/ void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, - FunctionalState NewState) + FunctionalState NewState) { - uint32_t tmp; + uint32_t tmp; - tmp = 0; - if (NewState == ENABLE) - { - if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1) - { - tmp |= UART_ACR_MODE; - } - if (ABConfigStruct->AutoRestart == ENABLE) - { - tmp |= UART_ACR_AUTO_RESTART; - } - } + tmp = 0; + if (NewState == ENABLE) + { + if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1) + { + tmp |= UART_ACR_MODE; + } + if (ABConfigStruct->AutoRestart == ENABLE) + { + tmp |= UART_ACR_AUTO_RESTART; + } + } - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - if (NewState == ENABLE) - { - // Clear DLL and DLM value - ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + if (NewState == ENABLE) + { + // Clear DLL and DLM value + ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN; - ((LPC_UART1_TypeDef *)UARTx)->DLL = 0; + ((LPC_UART1_TypeDef *)UARTx)->DLL = 0; - ((LPC_UART1_TypeDef *)UARTx)->DLM = 0; + ((LPC_UART1_TypeDef *)UARTx)->DLM = 0; - ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN; + ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN; - // FDR value must be reset to default value - ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10; + // FDR value must be reset to default value + ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10; - ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp; - } - else - { - ((LPC_UART1_TypeDef *)UARTx)->ACR = 0; - } - } - else - { - if (NewState == ENABLE) - { - // Clear DLL and DLM value - UARTx->LCR |= UART_LCR_DLAB_EN; + ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp; + } + else + { + ((LPC_UART1_TypeDef *)UARTx)->ACR = 0; + } + } + else + { + if (NewState == ENABLE) + { + // Clear DLL and DLM value + UARTx->LCR |= UART_LCR_DLAB_EN; - UARTx->DLL = 0; + UARTx->DLL = 0; - UARTx->DLM = 0; + UARTx->DLM = 0; - UARTx->LCR &= ~UART_LCR_DLAB_EN; + UARTx->LCR &= ~UART_LCR_DLAB_EN; - // FDR value must be reset to default value - UARTx->FDR = 0x10; + // FDR value must be reset to default value + UARTx->FDR = 0x10; - UARTx->ACR = UART_ACR_START | tmp; - } - else - { - UARTx->ACR = 0; - } - } + UARTx->ACR = UART_ACR_START | tmp; + } + else + { + UARTx->ACR = 0; + } + } } /*********************************************************************//** - * @brief Clear Autobaud Interrupt Pending - * @param[in] UARTx UART peripheral selected, should be - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] ABIntType type of auto-baud interrupt, should be: - * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt - * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt - * @return none + * @brief Clear Autobaud Interrupt Pending + * @param[in] UARTx UART peripheral selected, should be + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] ABIntType type of auto-baud interrupt, should be: + * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt + * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt + * @return none **********************************************************************/ void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType) { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - UARTx->ACR |= ABIntType; - } - else - UARTx->ACR |= ABIntType; + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + UARTx->ACR |= ABIntType; + } + else + UARTx->ACR |= ABIntType; } /*********************************************************************//** - * @brief Enable/Disable transmission on UART TxD pin - * @param[in] UARTx UART peripheral selected, should be: - * - LPC_UART0: UART0 peripheral - * - LPC_UART1: UART1 peripheral - * - LPC_UART2: UART2 peripheral - * - LPC_UART3: UART3 peripheral - * @param[in] NewState New State of Tx transmission function, should be: - * - ENABLE: Enable this function - - DISABLE: Disable this function + * @brief Enable/Disable transmission on UART TxD pin + * @param[in] UARTx UART peripheral selected, should be: + * - LPC_UART0: UART0 peripheral + * - LPC_UART1: UART1 peripheral + * - LPC_UART2: UART2 peripheral + * - LPC_UART3: UART3 peripheral + * @param[in] NewState New State of Tx transmission function, should be: + * - ENABLE: Enable this function + - DISABLE: Disable this function * @return none **********************************************************************/ void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState) { - if (NewState == ENABLE) - { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN; - } - else - { - UARTx->TER |= UART_TER_TXEN; - } - } - else - { - if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) - { - ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; - } - else - { - UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; - } - } + if (NewState == ENABLE) + { + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN; + } + else + { + UARTx->TER |= UART_TER_TXEN; + } + } + else + { + if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1) + { + ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; + } + else + { + UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK; + } + } } /* UART IrDA functions ---------------------------------------------------*/ /*********************************************************************//** - * @brief Enable or disable inverting serial input function of IrDA - * on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) - * @param[in] NewState New state of inverting serial input, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. + * @brief Enable or disable inverting serial input function of IrDA + * on UART peripheral. + * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) + * @param[in] NewState New state of inverting serial input, should be: + * - ENABLE: Enable this function. + * - DISABLE: Disable this function. * @return none **********************************************************************/ void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState) { - if (NewState == ENABLE) - { - UARTx->ICR |= UART_ICR_IRDAINV; - } - else if (NewState == DISABLE) - { - UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK; - } + if (NewState == ENABLE) + { + UARTx->ICR |= UART_ICR_IRDAINV; + } + else if (NewState == DISABLE) + { + UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK; + } } /*********************************************************************//** - * @brief Enable or disable IrDA function on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) - * @param[in] NewState New state of IrDA function, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. + * @brief Enable or disable IrDA function on UART peripheral. + * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) + * @param[in] NewState New state of IrDA function, should be: + * - ENABLE: Enable this function. + * - DISABLE: Disable this function. * @return none **********************************************************************/ void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState) { - if (NewState == ENABLE) - { - UARTx->ICR |= UART_ICR_IRDAEN; - } - else - { - UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK; - } + if (NewState == ENABLE) + { + UARTx->ICR |= UART_ICR_IRDAEN; + } + else + { + UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK; + } } /*********************************************************************//** - * @brief Configure Pulse divider for IrDA function on UART peripheral. - * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) - * @param[in] PulseDiv Pulse Divider value from Peripheral clock, - * should be one of the following: - - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk - - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk - - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk - - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk - - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk - - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk - - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk - - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk + * @brief Configure Pulse divider for IrDA function on UART peripheral. + * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only) + * @param[in] PulseDiv Pulse Divider value from Peripheral clock, + * should be one of the following: + - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk + - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk + - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk + - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk + - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk + - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk + - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk + - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk * @return none **********************************************************************/ void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv) { - uint32_t tmp, tmp1; + uint32_t tmp, tmp1; - tmp1 = UART_ICR_PULSEDIV(PulseDiv); + tmp1 = UART_ICR_PULSEDIV(PulseDiv); - tmp = UARTx->ICR & (~ UART_ICR_PULSEDIV(7)); + tmp = UARTx->ICR & (~ UART_ICR_PULSEDIV(7)); - tmp |= tmp1 | UART_ICR_FIXPULSE_EN; + tmp |= tmp1 | UART_ICR_FIXPULSE_EN; - UARTx->ICR = tmp & UART_ICR_BITMASK; + UARTx->ICR = tmp & UART_ICR_BITMASK; } /* UART1 FullModem function ---------------------------------------------*/ /*********************************************************************//** - * @brief Force pin DTR/RTS corresponding to given state (Full modem mode) - * @param[in] UARTx LPC_UART1 (only) - * @param[in] Pin Pin that NewState will be applied to, should be: - * - UART1_MODEM_PIN_DTR: DTR pin. - * - UART1_MODEM_PIN_RTS: RTS pin. - * @param[in] NewState New State of DTR/RTS pin, should be: - * - INACTIVE: Force the pin to inactive signal. - - ACTIVE: Force the pin to active signal. + * @brief Force pin DTR/RTS corresponding to given state (Full modem mode) + * @param[in] UARTx LPC_UART1 (only) + * @param[in] Pin Pin that NewState will be applied to, should be: + * - UART1_MODEM_PIN_DTR: DTR pin. + * - UART1_MODEM_PIN_RTS: RTS pin. + * @param[in] NewState New State of DTR/RTS pin, should be: + * - INACTIVE: Force the pin to inactive signal. + - ACTIVE: Force the pin to active signal. * @return none **********************************************************************/ void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, - UART_MODEM_PIN_Type Pin, - UART1_SignalState NewState) + UART_MODEM_PIN_Type Pin, + UART1_SignalState NewState) { - uint8_t tmp = 0; + uint8_t tmp = 0; - switch (Pin) - { - case UART1_MODEM_PIN_DTR: - tmp = UART1_MCR_DTR_CTRL; - break; + switch (Pin) + { + case UART1_MODEM_PIN_DTR: + tmp = UART1_MCR_DTR_CTRL; + break; - case UART1_MODEM_PIN_RTS: - tmp = UART1_MCR_RTS_CTRL; - break; + case UART1_MODEM_PIN_RTS: + tmp = UART1_MCR_RTS_CTRL; + break; - default: - break; - } + default: + break; + } - if (NewState == ACTIVE) - { - UARTx->MCR |= tmp; - } - else - { - UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; - } + if (NewState == ACTIVE) + { + UARTx->MCR |= tmp; + } + else + { + UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; + } } /*********************************************************************//** - * @brief Configure Full Modem mode for UART peripheral - * @param[in] UARTx LPC_UART1 (only) - * @param[in] Mode Full Modem mode, should be: - * - UART1_MODEM_MODE_LOOPBACK: Loop back mode. - * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode. - * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode. - * @param[in] NewState New State of this mode, should be: - * - ENABLE: Enable this mode. - - DISABLE: Disable this mode. + * @brief Configure Full Modem mode for UART peripheral + * @param[in] UARTx LPC_UART1 (only) + * @param[in] Mode Full Modem mode, should be: + * - UART1_MODEM_MODE_LOOPBACK: Loop back mode. + * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode. + * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode. + * @param[in] NewState New State of this mode, should be: + * - ENABLE: Enable this mode. + - DISABLE: Disable this mode. * @return none **********************************************************************/ void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, - FunctionalState NewState) + FunctionalState NewState) { - uint8_t tmp; + uint8_t tmp; - switch(Mode) - { - case UART1_MODEM_MODE_LOOPBACK: - tmp = UART1_MCR_LOOPB_EN; - break; + switch(Mode) + { + case UART1_MODEM_MODE_LOOPBACK: + tmp = UART1_MCR_LOOPB_EN; + break; - case UART1_MODEM_MODE_AUTO_RTS: - tmp = UART1_MCR_AUTO_RTS_EN; - break; + case UART1_MODEM_MODE_AUTO_RTS: + tmp = UART1_MCR_AUTO_RTS_EN; + break; - case UART1_MODEM_MODE_AUTO_CTS: - tmp = UART1_MCR_AUTO_CTS_EN; - break; + case UART1_MODEM_MODE_AUTO_CTS: + tmp = UART1_MCR_AUTO_CTS_EN; + break; - default: - break; - } + default: + break; + } - if (NewState == ENABLE) - { - UARTx->MCR |= tmp; - } - else - { - UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; - } + if (NewState == ENABLE) + { + UARTx->MCR |= tmp; + } + else + { + UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK; + } } /*********************************************************************//** - * @brief Get current status of modem status register - * @param[in] UARTx LPC_UART1 (only) - * @return Current value of modem status register - * Note: The return value of this function must be ANDed with each member - * UART_MODEM_STAT_type enumeration to determine current flag status - * corresponding to each modem flag status. Because some flags in - * modem status register will be cleared after reading, the next reading - * modem register could not be correct. So this function used to - * read modem status register in one time only, then the return value - * used to check all flags. + * @brief Get current status of modem status register + * @param[in] UARTx LPC_UART1 (only) + * @return Current value of modem status register + * Note: The return value of this function must be ANDed with each member + * UART_MODEM_STAT_type enumeration to determine current flag status + * corresponding to each modem flag status. Because some flags in + * modem status register will be cleared after reading, the next reading + * modem register could not be correct. So this function used to + * read modem status register in one time only, then the return value + * used to check all flags. **********************************************************************/ uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx) { - return ((UARTx->MSR) & UART1_MSR_BITMASK); + return ((UARTx->MSR) & UART1_MSR_BITMASK); } /* UART RS485 functions --------------------------------------------------------------*/ /*********************************************************************//** - * @brief Configure UART peripheral in RS485 mode according to the specified + * @brief Configure UART peripheral in RS485 mode according to the specified * parameters in the RS485ConfigStruct. - * @param[in] UARTx LPC_UART1 (only) - * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure + * @param[in] UARTx LPC_UART1 (only) + * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure * that contains the configuration information for specified UART * in RS485 mode. - * @return None + * @return None **********************************************************************/ void UART_RS485Config(LPC_UART_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct) { - uint32_t tmp; + uint32_t tmp; - tmp = 0; + tmp = 0; - // If Auto Direction Control is enabled - This function is used in Master mode - if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE) - { - tmp |= UART1_RS485CTRL_DCTRL_EN; + // If Auto Direction Control is enabled - This function is used in Master mode + if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE) + { + tmp |= UART1_RS485CTRL_DCTRL_EN; - // Set polar - if (RS485ConfigStruct->DirCtrlPol_Level == SET) - { - tmp |= UART1_RS485CTRL_OINV_1; - } + // Set polar + if (RS485ConfigStruct->DirCtrlPol_Level == SET) + { + tmp |= UART1_RS485CTRL_OINV_1; + } - // Set pin according to. This condition is only with UART1. The others are used - // OE pin as default for control the direction of RS485 buffer IC - if ((RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR) - && ((LPC_UART1_TypeDef *)UARTx == LPC_UART1)) - { - tmp |= UART1_RS485CTRL_SEL_DTR; - } + // Set pin according to. This condition is only with UART1. The others are used + // OE pin as default for control the direction of RS485 buffer IC + if ((RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR) + && ((LPC_UART1_TypeDef *)UARTx == LPC_UART1)) + { + tmp |= UART1_RS485CTRL_SEL_DTR; + } - // Fill delay time - UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK; - } + // Fill delay time + UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK; + } - // MultiDrop mode is enable - if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE) - { - tmp |= UART1_RS485CTRL_NMM_EN; - } + // MultiDrop mode is enable + if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE) + { + tmp |= UART1_RS485CTRL_NMM_EN; + } - // Auto Address Detect function - if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE) - { - tmp |= UART1_RS485CTRL_AADEN; + // Auto Address Detect function + if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE) + { + tmp |= UART1_RS485CTRL_AADEN; - // Fill Match Address - UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK; - } + // Fill Match Address + UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK; + } - // Receiver is disable - if (RS485ConfigStruct->Rx_State == DISABLE) - { - tmp |= UART1_RS485CTRL_RX_DIS; - } + // Receiver is disable + if (RS485ConfigStruct->Rx_State == DISABLE) + { + tmp |= UART1_RS485CTRL_RX_DIS; + } - // write back to RS485 control register - UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK; + // write back to RS485 control register + UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK; - // Enable Parity function and leave parity in stick '0' parity as default - UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); + // Enable Parity function and leave parity in stick '0' parity as default + UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN); } /*********************************************************************//** - * @brief Enable/Disable receiver in RS485 module in UART1 - * @param[in] UARTx LPC_UART1 (only) - * @param[in] NewState New State of command, should be: - * - ENABLE: Enable this function. - * - DISABLE: Disable this function. - * @return None + * @brief Enable/Disable receiver in RS485 module in UART1 + * @param[in] UARTx LPC_UART1 (only) + * @param[in] NewState New State of command, should be: + * - ENABLE: Enable this function. + * - DISABLE: Disable this function. + * @return None **********************************************************************/ void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState) { - if (NewState == ENABLE) - { - UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS; - } - else - { - UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS; - } + if (NewState == ENABLE) + { + UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS; + } + else + { + UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS; + } } /*********************************************************************//** - * @brief Send data on RS485 bus with specified parity stick value (9-bit mode). - * @param[in] UARTx LPC_UART1 (only) - * @param[in] pDatFrm Pointer to data frame. - * @param[in] size Size of data. - * @param[in] ParityStick Parity Stick value, should be 0 or 1. - * @return None + * @brief Send data on RS485 bus with specified parity stick value (9-bit mode). + * @param[in] UARTx LPC_UART1 (only) + * @param[in] pDatFrm Pointer to data frame. + * @param[in] size Size of data. + * @param[in] ParityStick Parity Stick value, should be 0 or 1. + * @return None **********************************************************************/ uint32_t UART_RS485Send(LPC_UART_TypeDef *UARTx, uint8_t *pDatFrm, - uint32_t size, uint8_t ParityStick) + uint32_t size, uint8_t ParityStick) { - uint8_t tmp, save; - uint32_t cnt; + uint8_t tmp, save; + uint32_t cnt; - if (ParityStick) - { - save = tmp = UARTx->LCR & UART_LCR_BITMASK; + if (ParityStick) + { + save = tmp = UARTx->LCR & UART_LCR_BITMASK; - tmp &= ~(UART_LCR_PARITY_EVEN); + tmp &= ~(UART_LCR_PARITY_EVEN); - UARTx->LCR = tmp; + UARTx->LCR = tmp; - cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); + cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); - while (!(UARTx->LSR & UART_LSR_TEMT)); + while (!(UARTx->LSR & UART_LSR_TEMT)); - UARTx->LCR = save; - } - else - { - cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); + UARTx->LCR = save; + } + else + { + cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING); - while (!(UARTx->LSR & UART_LSR_TEMT)); - } + while (!(UARTx->LSR & UART_LSR_TEMT)); + } - return cnt; + return cnt; } /*********************************************************************//** - * @brief Send Slave address frames on RS485 bus. - * @param[in] UARTx LPC_UART1 (only) - * @param[in] SlvAddr Slave Address. - * @return None + * @brief Send Slave address frames on RS485 bus. + * @param[in] UARTx LPC_UART1 (only) + * @param[in] SlvAddr Slave Address. + * @return None **********************************************************************/ void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr) { - UART_RS485Send(UARTx, &SlvAddr, 1, 1); + UART_RS485Send(UARTx, &SlvAddr, 1, 1); } /*********************************************************************//** - * @brief Send Data frames on RS485 bus. - * @param[in] UARTx LPC_UART1 (only) - * @param[in] pData Pointer to data to be sent. - * @param[in] size Size of data frame to be sent. - * @return None + * @brief Send Data frames on RS485 bus. + * @param[in] UARTx LPC_UART1 (only) + * @param[in] pData Pointer to data to be sent. + * @param[in] size Size of data frame to be sent. + * @return None **********************************************************************/ uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size) { - return (UART_RS485Send(UARTx, pData, size, 0)); + return (UART_RS485Send(UARTx, pData, size, 0)); } /** diff --git a/bsp/lpc178x/drivers/lpc177x_8x_uart.h b/bsp/lpc178x/drivers/lpc177x_8x_uart.h index 2b8a6f85cb..35c756d0c7 100644 --- a/bsp/lpc178x/drivers/lpc177x_8x_uart.h +++ b/bsp/lpc178x/drivers/lpc177x_8x_uart.h @@ -1,13 +1,13 @@ /********************************************************************** -* $Id$ lpc177x_8x_uart.h 2011-06-02 +* $Id$ lpc177x_8x_uart.h 2011-06-02 *//** -* @file lpc177x_8x_uart.h -* @brief Contains all macro definitions and function prototypes -* support for UART firmware library on LPC177x_8x -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc177x_8x_uart.h +* @brief Contains all macro definitions and function prototypes +* support for UART firmware library on LPC177x_8x +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -25,7 +25,7 @@ **********************************************************************/ /* Peripheral group ----------------------------------------------------------- */ -/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter) +/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter) * @ingroup LPC177x_8xCMSIS_FwLib_Drivers * @{ */ @@ -51,7 +51,7 @@ extern "C" /** UART time-out definitions in case of using Read() and Write function * with Blocking Flag mode */ -#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) +#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) /** * @} @@ -63,7 +63,7 @@ extern "C" */ /* Accepted Error baud rate value (in percent unit) */ -#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ +#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ /* --------------------- BIT DEFINITIONS -------------------------------------- */ @@ -71,27 +71,27 @@ extern "C" * Macro defines for Macro defines for UARTn Receiver Buffer Register **********************************************************************/ /** UART Received Buffer mask bit (8 bits) */ -#define UART_RBR_MASKBIT ((uint8_t)0xFF) +#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*********************************************************************//** * Macro defines for Macro defines for UARTn Transmit Holding Register **********************************************************************/ /** UART Transmit Holding mask bit (8 bits) */ -#define UART_THR_MASKBIT ((uint8_t)0xFF) +#define UART_THR_MASKBIT ((uint8_t)0xFF) /*********************************************************************//** * Macro defines for Macro defines for UARTn Divisor Latch LSB register **********************************************************************/ /** Macro for loading least significant halfs of divisors */ -#define UART_LOAD_DLL(div) ((div) & 0xFF) +#define UART_LOAD_DLL(div) ((div) & 0xFF) /** Divisor latch LSB bit mask */ -#define UART_DLL_MASKBIT ((uint8_t)0xFF) +#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*********************************************************************//** * Macro defines for Macro defines for UARTn Divisor Latch MSB register **********************************************************************/ /** Divisor latch MSB bit mask */ -#define UART_DLM_MASKBIT ((uint8_t)0xFF) +#define UART_DLM_MASKBIT ((uint8_t)0xFF) /** Macro for loading most significant halfs of divisors */ #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) @@ -99,258 +99,258 @@ extern "C" * Macro defines for Macro defines for UART interrupt enable register **********************************************************************/ /** RBR Interrupt enable*/ -#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) +#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /** THR Interrupt enable*/ -#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) +#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /** RX line status interrupt enable*/ -#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) +#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /** Modem status interrupt enable */ -#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) +#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /** CTS1 signal transition interrupt enable */ -#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) +#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /** Enables the end of auto-baud interrupt */ -#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) +#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /** Enables the auto-baud time-out interrupt */ -#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) +#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /** UART interrupt enable register bit mask */ -#define UART_IER_BITMASK ((uint32_t)(0x307)) +#define UART_IER_BITMASK ((uint32_t)(0x307)) /** UART1 interrupt enable register bit mask */ -#define UART1_IER_BITMASK ((uint32_t)(0x38F)) +#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*********************************************************************//** * Macro defines for Macro defines for UART interrupt identification register **********************************************************************/ /** Interrupt Status - Active low */ -#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) +#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /** Interrupt identification: Receive line status*/ -#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) +#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /** Interrupt identification: Receive data available*/ -#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) +#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /** Interrupt identification: Character time-out indicator*/ -#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) +#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /** Interrupt identification: THRE interrupt*/ -#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) +#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /** Interrupt identification: Modem interrupt*/ -#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) +#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /** Interrupt identification: Interrupt ID mask */ -#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) +#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /** These bits are equivalent to UnFCR[0] */ -#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) +#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /** End of auto-baud interrupt */ -#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) +#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /** Auto-baud time-out interrupt */ -#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) +#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /** UART interrupt identification register bit mask */ -#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) +#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*********************************************************************//** * Macro defines for Macro defines for UART FIFO control register **********************************************************************/ /** UART FIFO enable */ -#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) +#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /** UART FIFO RX reset */ -#define UART_FCR_RX_RS ((uint8_t)(1<<1)) +#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /** UART FIFO TX reset */ -#define UART_FCR_TX_RS ((uint8_t)(1<<2)) +#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /** UART DMA mode selection */ -#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) +#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /** UART FIFO trigger level 0: 1 character */ -#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) +#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /** UART FIFO trigger level 1: 4 character */ -#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) +#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /** UART FIFO trigger level 2: 8 character */ -#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) +#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /** UART FIFO trigger level 3: 14 character */ -#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) +#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /** UART FIFO control bit mask */ -#define UART_FCR_BITMASK ((uint8_t)(0xCF)) +#define UART_FCR_BITMASK ((uint8_t)(0xCF)) -#define UART_TX_FIFO_SIZE (16) +#define UART_TX_FIFO_SIZE (16) /*********************************************************************//** * Macro defines for Macro defines for UART line control register **********************************************************************/ /** UART 5 bit data mode */ -#define UART_LCR_WLEN5 ((uint8_t)(0)) +#define UART_LCR_WLEN5 ((uint8_t)(0)) /** UART 6 bit data mode */ -#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) +#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /** UART 7 bit data mode */ -#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) +#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /** UART 8 bit data mode */ -#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) +#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /** UART Two Stop Bits Select */ -#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) +#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /** UART Parity Enable */ -#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) +#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /** UART Odd Parity Select */ -#define UART_LCR_PARITY_ODD ((uint8_t)(0)) +#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /** UART Even Parity Select */ -#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) +#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /** UART force 1 stick parity */ -#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) +#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /** UART force 0 stick parity */ -#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) +#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /** UART Transmission Break enable */ -#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) +#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /** UART Divisor Latches Access bit enable */ -#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) +#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /** UART line control bit mask */ -#define UART_LCR_BITMASK ((uint8_t)(0xFF)) +#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*********************************************************************//** * Macro defines for Macro defines for UART1 Modem Control Register **********************************************************************/ /** Source for modem output pin DTR */ -#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) +#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /** Source for modem output pin RTS */ -#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) +#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /** Loop back mode select */ -#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) +#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /** Enable Auto RTS flow-control */ -#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) +#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /** Enable Auto CTS flow-control */ -#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) +#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /** UART1 bit mask value */ -#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) +#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*********************************************************************//** * Macro defines for Macro defines for UART line status register **********************************************************************/ /** Line status register: Receive data ready*/ -#define UART_LSR_RDR ((uint8_t)(1<<0)) +#define UART_LSR_RDR ((uint8_t)(1<<0)) /** Line status register: Overrun error*/ -#define UART_LSR_OE ((uint8_t)(1<<1)) +#define UART_LSR_OE ((uint8_t)(1<<1)) /** Line status register: Parity error*/ -#define UART_LSR_PE ((uint8_t)(1<<2)) +#define UART_LSR_PE ((uint8_t)(1<<2)) /** Line status register: Framing error*/ -#define UART_LSR_FE ((uint8_t)(1<<3)) +#define UART_LSR_FE ((uint8_t)(1<<3)) /** Line status register: Break interrupt*/ -#define UART_LSR_BI ((uint8_t)(1<<4)) +#define UART_LSR_BI ((uint8_t)(1<<4)) /** Line status register: Transmit holding register empty*/ -#define UART_LSR_THRE ((uint8_t)(1<<5)) +#define UART_LSR_THRE ((uint8_t)(1<<5)) /** Line status register: Transmitter empty*/ -#define UART_LSR_TEMT ((uint8_t)(1<<6)) +#define UART_LSR_TEMT ((uint8_t)(1<<6)) /** Error in RX FIFO*/ -#define UART_LSR_RXFE ((uint8_t)(1<<7)) +#define UART_LSR_RXFE ((uint8_t)(1<<7)) /** UART Line status bit mask */ -#define UART_LSR_BITMASK ((uint8_t)(0xFF)) +#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*********************************************************************//** * Macro defines for Macro defines for UART Modem (UART1 only) status register **********************************************************************/ /** Set upon state change of input CTS */ -#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) +#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /** Set upon state change of input DSR */ -#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) +#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /** Set upon low to high transition of input RI */ -#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) +#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /** Set upon state change of input DCD */ -#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) +#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /** Clear To Send State */ -#define UART1_MSR_CTS ((uint8_t)(1<<4)) +#define UART1_MSR_CTS ((uint8_t)(1<<4)) /** Data Set Ready State */ -#define UART1_MSR_DSR ((uint8_t)(1<<5)) +#define UART1_MSR_DSR ((uint8_t)(1<<5)) /** Ring Indicator State */ -#define UART1_MSR_RI ((uint8_t)(1<<6)) +#define UART1_MSR_RI ((uint8_t)(1<<6)) /** Data Carrier Detect State */ -#define UART1_MSR_DCD ((uint8_t)(1<<7)) +#define UART1_MSR_DCD ((uint8_t)(1<<7)) /** MSR register bit-mask value */ -#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) +#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*********************************************************************//** * Macro defines for Macro defines for UART Scratch Pad Register **********************************************************************/ /** UART Scratch Pad bit mask */ -#define UART_SCR_BIMASK ((uint8_t)(0xFF)) +#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*********************************************************************//** * Macro defines for Macro defines for UART Auto baudrate control register **********************************************************************/ /** UART Auto-baud start */ -#define UART_ACR_START ((uint32_t)(1<<0)) +#define UART_ACR_START ((uint32_t)(1<<0)) /** UART Auto baudrate Mode 1 */ -#define UART_ACR_MODE ((uint32_t)(1<<1)) +#define UART_ACR_MODE ((uint32_t)(1<<1)) /** UART Auto baudrate restart */ -#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) +#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /** UART End of auto-baud interrupt clear */ -#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) +#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /** UART Auto-baud time-out interrupt clear */ -#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) +#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /** UART Auto Baudrate register bit mask */ -#define UART_ACR_BITMASK ((uint32_t)(0x307)) +#define UART_ACR_BITMASK ((uint32_t)(0x307)) /*********************************************************************//** * Macro defines for Macro defines for UART IrDA control register **********************************************************************/ /** IrDA mode enable */ -#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) +#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /** IrDA serial input inverted */ -#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) +#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /** IrDA fixed pulse width mode */ -#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) +#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /** PulseDiv - Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) +#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /** UART IRDA bit mask */ -#define UART_ICR_BITMASK ((uint32_t)(0x3F)) +#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*********************************************************************//** * Macro defines for Macro defines for UART Fractional divider register **********************************************************************/ /** Baud-rate generation pre-scaler divisor */ -#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) +#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /** Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) +#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /** UART Fractional Divider register bit mask */ -#define UART_FDR_BITMASK ((uint32_t)(0xFF)) +#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /*********************************************************************//** * Macro defines for Macro defines for UART Tx Enable register **********************************************************************/ /** Transmit enable bit */ -#define UART_TER_TXEN ((uint8_t)(1<<7)) +#define UART_TER_TXEN ((uint8_t)(1<<7)) /** UART Transmit Enable Register bit mask */ -#define UART_TER_BITMASK ((uint8_t)(0x80)) +#define UART_TER_BITMASK ((uint8_t)(0x80)) /*********************************************************************//** * Macro defines for Macro defines for UART1 RS485 Control register **********************************************************************/ /** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */ -#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) +#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /** The receiver is disabled */ -#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) +#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /** Auto Address Detect (AAD) is enabled */ -#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) +#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */ -#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) +#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /** Enable Auto Direction Control */ -#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) -/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. +#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) +/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. The direction control pin will be driven to logic "1" when the transmitter has data to be sent */ -#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) +#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /** RS485 control bit-mask value */ -#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) +#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /*********************************************************************//** * Macro defines for Macro defines for UART1 RS-485 Address Match register **********************************************************************/ -#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ +#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ /*********************************************************************//** * Macro defines for Macro defines for UART1 RS-485 Delay value register **********************************************************************/ /* Macro defines for UART1 RS-485 Delay value register */ -#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ +#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ /*********************************************************************//** * Macro defines for Macro defines for UART FIFO Level register **********************************************************************/ /** Reflects the current level of the UART receiver FIFO */ -#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) +#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /** Reflects the current level of the UART transmitter FIFO */ -#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) +#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /** UART FIFO Level Register bit mask */ -#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) +#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /** @@ -367,199 +367,199 @@ The direction control pin will be driven to logic "1" when the transmitter has d * @brief UART Databit type definitions */ typedef enum { - UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ - UART_DATABIT_6, /*!< UART 6 bit data mode */ - UART_DATABIT_7, /*!< UART 7 bit data mode */ - UART_DATABIT_8 /*!< UART 8 bit data mode */ + UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ + UART_DATABIT_6, /*!< UART 6 bit data mode */ + UART_DATABIT_7, /*!< UART 7 bit data mode */ + UART_DATABIT_8 /*!< UART 8 bit data mode */ } UART_DATABIT_Type; /** * @brief UART Stop bit type definitions */ typedef enum { - UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ - UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ + UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ + UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ } UART_STOPBIT_Type; /** * @brief UART Parity type definitions */ typedef enum { - UART_PARITY_NONE = 0, /*!< No parity */ - UART_PARITY_ODD, /*!< Odd parity */ - UART_PARITY_EVEN, /*!< Even parity */ - UART_PARITY_SP_1, /*!< Forced "1" stick parity */ - UART_PARITY_SP_0 /*!< Forced "0" stick parity */ + UART_PARITY_NONE = 0, /*!< No parity */ + UART_PARITY_ODD, /*!< Odd parity */ + UART_PARITY_EVEN, /*!< Even parity */ + UART_PARITY_SP_1, /*!< Forced "1" stick parity */ + UART_PARITY_SP_0 /*!< Forced "0" stick parity */ } UART_PARITY_Type; /** * @brief FIFO Level type definitions */ typedef enum { - UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ - UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ - UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ - UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ + UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ + UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ + UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ + UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ } UART_FITO_LEVEL_Type; /********************************************************************//** * @brief UART Interrupt Type definitions **********************************************************************/ typedef enum { - UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ - UART_INTCFG_THRE, /*!< THR Interrupt enable*/ - UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ - UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ - UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ - UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ - UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ + UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ + UART_INTCFG_THRE, /*!< THR Interrupt enable*/ + UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ + UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ + UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ + UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ + UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ } UART_INT_Type; /** * @brief UART Line Status Type definition */ typedef enum { - UART_LINESTAT_RDR = UART_LSR_RDR, /*!DIR |= 1<<4; - LPC_GPIO5->CLR = 1<<4; - LPC_GPIO5->SET = 1<<4; + LPC_GPIO5->DIR |= 1<<4; + LPC_GPIO5->CLR = 1<<4; + LPC_GPIO5->SET = 1<<4; - /*Disable LCD controller*/ - GLCD_Ctrl (FALSE); - /*Init LCD and copy picture in video RAM*/ - GLCD_Init (_lcd_info.framebuffer); - /*Enable LCD*/ - GLCD_Ctrl (TRUE); + /*Disable LCD controller*/ + GLCD_Ctrl (FALSE); + /*Init LCD and copy picture in video RAM*/ + GLCD_Init (_lcd_info.framebuffer); + /*Enable LCD*/ + GLCD_Ctrl (TRUE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; - } + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; + } - return RT_EOK; + return RT_EOK; } @@ -63,27 +63,27 @@ void rt_hw_lcd_init(void) { rt_uint16_t * _rt_framebuffer = RT_NULL; - // _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8); - // if (_rt_framebuffer == RT_NULL) return; /* no memory yet */ + // _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8); + // if (_rt_framebuffer == RT_NULL) return; /* no memory yet */ - _rt_framebuffer = (rt_uint16_t *)0xA0000000; + _rt_framebuffer = (rt_uint16_t *)0xA0000000; - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = (void*)_rt_framebuffer; - _lcd_info.width = RT_HW_LCD_WIDTH; - _lcd_info.height = RT_HW_LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + _lcd_info.framebuffer = (void*)_rt_framebuffer; + _lcd_info.width = RT_HW_LCD_WIDTH; + _lcd_info.height = RT_HW_LCD_HEIGHT; - /* init device structure */ - lcd.type = RT_Device_Class_Graphic; - lcd.init = rt_lcd_init; - lcd.open = RT_NULL; - lcd.close = RT_NULL; - lcd.control = rt_lcd_control; - lcd.user_data = (void*)&_lcd_info; + /* init device structure */ + lcd.type = RT_Device_Class_Graphic; + lcd.init = rt_lcd_init; + lcd.open = RT_NULL; + lcd.close = RT_NULL; + lcd.control = rt_lcd_control; + lcd.user_data = (void*)&_lcd_info; - /* register lcd device to RT-Thread */ - rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); + /* register lcd device to RT-Thread */ + rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); } void lcd_fill(uint8_t * start, uint8_t * end, uint8_t pixel) diff --git a/bsp/lpc178x/drivers/lpc_types.h b/bsp/lpc178x/drivers/lpc_types.h index 9cc511a135..a36624baf4 100644 --- a/bsp/lpc178x/drivers/lpc_types.h +++ b/bsp/lpc178x/drivers/lpc_types.h @@ -1,15 +1,15 @@ /********************************************************************** -* $Id$ lpc_types.h 2011-06-02 +* $Id$ lpc_types.h 2011-06-02 *//** -* @file lpc_types.h -* @brief Contains the NXP ABL typedefs for C standard types. -* It is intended to be used in ISO C conforming development -* environments and checks for this insofar as it is possible -* to do so. -* @version 1.0 -* @date 02. June. 2011 -* @author NXP MCU SW Application Team -* +* @file lpc_types.h +* @brief Contains the NXP ABL typedefs for C standard types. +* It is intended to be used in ISO C conforming development +* environments and checks for this insofar as it is possible +* to do so. +* @version 1.0 +* @date 02. June. 2011 +* @author NXP MCU SW Application Team +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -37,7 +37,7 @@ * @ingroup LPC177x_8xCMSIS_FwLib_Drivers * @{ */ - + /* Public Types --------------------------------------------------------------- */ /** @defgroup LPC_Types_Public_Types Basic Public Data Types * @{ @@ -71,8 +71,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; */ typedef enum { - NONE_BLOCKING = 0, /**< None Blocking type */ - BLOCKING, /**< Blocking type */ + NONE_BLOCKING = 0, /**< None Blocking type */ + BLOCKING, /**< Blocking type */ } TRANSFER_BLOCK_Type; @@ -98,7 +98,7 @@ typedef int32_t(*PFI)(); */ #undef _BIT /** Set bit macro */ -#define _BIT(n) (1<TCR = 0x02; /* reset timer */ -// LPC_TIM0->PR = 0x00; /* set prescaler to zero */ -// LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1); -// LPC_TIM0->IR = 0xff; /* reset all interrrupts */ -// LPC_TIM0->MCR = 0x04; /* stop timer on match */ -// LPC_TIM0->TCR = 0x01; /* start timer */ +// LPC_TIM0->TCR = 0x02; /* reset timer */ +// LPC_TIM0->PR = 0x00; /* set prescaler to zero */ +// LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1); +// LPC_TIM0->IR = 0xff; /* reset all interrrupts */ +// LPC_TIM0->MCR = 0x04; /* stop timer on match */ +// LPC_TIM0->TCR = 0x01; /* start timer */ // -// /* wait until delay time has elapsed */ -// while (LPC_TIM0->TCR & 0x01); +// /* wait until delay time has elapsed */ +// while (LPC_TIM0->TCR & 0x01); // } // else if ( timer_num == 1 ) // { -// LPC_TIM1->TCR = 0x02; /* reset timer */ -// LPC_TIM1->PR = 0x00; /* set prescaler to zero */ -// LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1); -// LPC_TIM1->IR = 0xff; /* reset all interrrupts */ -// LPC_TIM1->MCR = 0x04; /* stop timer on match */ -// LPC_TIM1->TCR = 0x01; /* start timer */ +// LPC_TIM1->TCR = 0x02; /* reset timer */ +// LPC_TIM1->PR = 0x00; /* set prescaler to zero */ +// LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1); +// LPC_TIM1->IR = 0xff; /* reset all interrrupts */ +// LPC_TIM1->MCR = 0x04; /* stop timer on match */ +// LPC_TIM1->TCR = 0x01; /* start timer */ // -// /* wait until delay time has elapsed */ -// while (LPC_TIM1->TCR & 0x01); +// /* wait until delay time has elapsed */ +// while (LPC_TIM1->TCR & 0x01); // } // else if ( timer_num == 2 ) // { -// LPC_TIM2->TCR = 0x02; /* reset timer */ -// LPC_TIM2->PR = 0x00; /* set prescaler to zero */ -// LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1); -// LPC_TIM2->IR = 0xff; /* reset all interrrupts */ -// LPC_TIM2->MCR = 0x04; /* stop timer on match */ -// LPC_TIM2->TCR = 0x01; /* start timer */ +// LPC_TIM2->TCR = 0x02; /* reset timer */ +// LPC_TIM2->PR = 0x00; /* set prescaler to zero */ +// LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1); +// LPC_TIM2->IR = 0xff; /* reset all interrrupts */ +// LPC_TIM2->MCR = 0x04; /* stop timer on match */ +// LPC_TIM2->TCR = 0x01; /* start timer */ // -// /* wait until delay time has elapsed */ -// while (LPC_TIM2->TCR & 0x01); +// /* wait until delay time has elapsed */ +// while (LPC_TIM2->TCR & 0x01); // } // else if ( timer_num == 3 ) // { -// LPC_TIM3->TCR = 0x02; /* reset timer */ -// LPC_TIM3->PR = 0x00; /* set prescaler to zero */ -// LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1); -// LPC_TIM3->IR = 0xff; /* reset all interrrupts */ -// LPC_TIM3->MCR = 0x04; /* stop timer on match */ -// LPC_TIM3->TCR = 0x01; /* start timer */ +// LPC_TIM3->TCR = 0x02; /* reset timer */ +// LPC_TIM3->PR = 0x00; /* set prescaler to zero */ +// LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1); +// LPC_TIM3->IR = 0xff; /* reset all interrrupts */ +// LPC_TIM3->MCR = 0x04; /* stop timer on match */ +// LPC_TIM3->TCR = 0x01; /* start timer */ // -// /* wait until delay time has elapsed */ -// while (LPC_TIM3->TCR & 0x01); +// /* wait until delay time has elapsed */ +// while (LPC_TIM3->TCR & 0x01); // } // return; //} @@ -204,7 +204,7 @@ void SDRAM_Init (void) { uint32_t i, dwtemp = dwtemp; uint16_t wtemp = wtemp; - uint32_t mhz, nsPerClk; + uint32_t mhz, nsPerClk; /* Enable External Memory Controller power/clock */ LPC_SC->PCONP |= 0x00000800; LPC_SC->EMCDLYCTL = 0x00001010; @@ -213,10 +213,10 @@ void SDRAM_Init (void) EMC_GPIO_Init(); - mhz = SystemCoreClock / 1000000; - if (LPC_SC->EMCCLKSEL) - mhz >>= 1; - nsPerClk = 1000 / mhz; + mhz = SystemCoreClock / 1000000; + if (LPC_SC->EMCCLKSEL) + mhz >>= 1; + nsPerClk = 1000 / mhz; LPC_EMC->DynamicRP = EMC_NS2CLK(20, nsPerClk); /* 20ns, */ LPC_EMC->DynamicRAS = /*EMC_NS2CLK(42, nsPerClk);*/ 15; /* 42ns to 100K ns, */ LPC_EMC->DynamicSREX = 1 - 1; /* tSRE, 1clk, */ @@ -225,7 +225,7 @@ void SDRAM_Init (void) LPC_EMC->DynamicWR = 2 - 1; /* 2CLK, */ LPC_EMC->DynamicRC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRC=63ns(min)*/ LPC_EMC->DynamicRFC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRFC=tRC */ - LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, ²»ÖªµÀ£¬ÉèΪ×î¾Ã */ + LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, ä¸çŸ¥é“，设为最久 */ LPC_EMC->DynamicRRD = EMC_NS2CLK(63, nsPerClk); /* 3clk, tRRD=15ns(min) */ LPC_EMC->DynamicMRD = 2 - 1; /* 2clk, tMRD=2clk(min) */ @@ -249,22 +249,22 @@ void SDRAM_Init (void) #ifdef SDRAM_CONFIG_16BIT LPC_EMC->DynamicConfig0 = 0x680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ #elif defined SDRAM_CONFIG_32BIT - LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ + LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */ #endif delayMs(0, 100); LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */ - delayMs(0, 200); /* wait 200ms */ + delayMs(0, 200); /* wait 200ms */ LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */ LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */ - for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */ + for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */ /* 64ms/8192=7.8125us, nx16x8.33ns<7.8125us, n<58.6*/ - wtemp = 64000000 / (1 << 13); - wtemp -= 16; - wtemp >>= 4; - wtemp = wtemp * mhz / 1000; + wtemp = 64000000 / (1 << 13); + wtemp -= 16; + wtemp >>= 4; + wtemp = wtemp * mhz / 1000; LPC_EMC->DynamicRefresh = wtemp; LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */ @@ -273,7 +273,7 @@ void SDRAM_Init (void) wtemp = *((volatile uint16_t *)(SDRAM_BASE | (0x33<<12))); /* 8 burst, 3 CAS latency */ #elif defined SDRAM_CONFIG_32BIT - dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */ + dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */ #endif LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */ diff --git a/bsp/lpc178x/drivers/sdram.h b/bsp/lpc178x/drivers/sdram.h index d89e515ebb..b627bed75e 100644 --- a/bsp/lpc178x/drivers/sdram.h +++ b/bsp/lpc178x/drivers/sdram.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef SDRAM_H_INCLUDED #define SDRAM_H_INCLUDED diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c index 0d92eb1fca..cb8e68d30c 100644 --- a/bsp/lpc178x/drivers/uart.c +++ b/bsp/lpc178x/drivers/uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,14 +25,14 @@ struct rt_uart_lpc { - struct rt_device parent; + struct rt_device parent; - LPC_UART_TypeDef * UART; - IRQn_Type UART_IRQn; + LPC_UART_TypeDef * UART; + IRQn_Type UART_IRQn; - /* buffer for reception */ - rt_uint8_t read_index, save_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART0 @@ -45,96 +45,96 @@ struct rt_uart_lpc uart1_device; #ifdef RT_USING_UART0 void UART0_IRQHandler(void) { - rt_ubase_t level, iir; + rt_ubase_t level, iir; struct rt_uart_lpc* uart = &uart0_device; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); /* read IIR and clear it */ - iir = uart->UART->IIR; + iir = uart->UART->IIR; - if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ - { - /* Receive Data Available */ + if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ + { + /* Receive Data Available */ uart->rx_buffer[uart->save_index] = uart->UART->RBR; level = rt_hw_interrupt_disable(); - uart->save_index ++; + uart->save_index ++; if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) uart->save_index = 0; rt_hw_interrupt_enable(level); - /* invoke callback */ - if(uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; else length = uart->save_index - uart->read_index; uart->parent.rx_indicate(&uart->parent, length); - } - } + } + } - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); - return; + return; } #endif #ifdef RT_USING_UART1 void UART1_IRQHandler(void) { - rt_ubase_t level, iir; + rt_ubase_t level, iir; struct rt_uart_lpc* uart = &uart1_device; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); /* read IIR and clear it */ - iir = uart->UART->IIR; + iir = uart->UART->IIR; - if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ - { - /* Receive Data Available */ + if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */ + { + /* Receive Data Available */ uart->rx_buffer[uart->save_index] = uart->UART->RBR; level = rt_hw_interrupt_disable(); - uart->save_index ++; + uart->save_index ++; if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) uart->save_index = 0; rt_hw_interrupt_enable(level); - /* invoke callback */ - if(uart->parent.rx_indicate != RT_NULL) - { - rt_size_t length; - if (uart->read_index > uart->save_index) + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; else length = uart->save_index - uart->read_index; uart->parent.rx_indicate(&uart->parent, length); - } - } + } + } - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); - return; + return; } #endif static rt_err_t rt_uart_init (rt_device_t dev) { - struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - UART_CFG_Type UART_ConfigStruct; + struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; + UART_CFG_Type UART_ConfigStruct; #ifdef RT_USING_UART0 - if( uart->UART == LPC_UART0 ) + if( uart->UART == LPC_UART0 ) { /* * Initialize UART0 pin connect @@ -184,170 +184,170 @@ static rt_err_t rt_uart_init (rt_device_t dev) #endif #ifdef RT_USING_UART2 - if( uart->UART == LPC_UART2 ) + if( uart->UART == LPC_UART2 ) { } #endif - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) { struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable the UART Interrupt */ - NVIC_EnableIRQ( uart->UART_IRQn ); - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + NVIC_EnableIRQ( uart->UART_IRQn ); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_uart_close(rt_device_t dev) { struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - RT_ASSERT(dev != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Disable the UART Interrupt */ - NVIC_DisableIRQ( uart->UART_IRQn ); - } + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + NVIC_DisableIRQ( uart->UART_IRQn ); + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - RT_ASSERT(uart != RT_NULL); + rt_uint8_t* ptr; + struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; + RT_ASSERT(uart != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (uart->read_index != uart->save_index) - { - *ptr = uart->rx_buffer[uart->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; - uart->read_index ++; - if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) - uart->read_index = 0; - } - else - { - /* no data in rx buffer */ + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; - size --; - } + ptr ++; + size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; - char *ptr; - ptr = (char*)buffer; + struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev; + char *ptr; + ptr = (char*)buffer; - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(uart->UART->LSR & UART_LSR_THRE)); + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(uart->UART->LSR & UART_LSR_THRE)); UART_SendByte( uart->UART,'\r'); - } + } - while (!(uart->UART->LSR & UART_LSR_THRE)); - UART_SendByte( uart->UART,*ptr); - ptr ++; - size --; - } - } - else - { + while (!(uart->UART->LSR & UART_LSR_THRE)); + UART_SendByte( uart->UART,*ptr); + ptr ++; + size --; + } + } + else + { UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING); } - return (rt_size_t) ptr - (rt_size_t) buffer; + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_uart_init(void) { - struct rt_uart_lpc* uart; + struct rt_uart_lpc* uart; #ifdef RT_USING_UART0 - /* get uart device */ - uart = &uart0_device; - uart0_device.UART = LPC_UART0; - uart0_device.UART_IRQn = UART0_IRQn; + /* get uart device */ + uart = &uart0_device; + uart0_device.UART = LPC_UART0; + uart0_device.UART_IRQn = UART0_IRQn; - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; - rt_device_register(&uart->parent, - "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&uart->parent, + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART1 - /* get uart device */ - uart = &uart1_device; - uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1; - uart1_device.UART_IRQn = UART1_IRQn; + /* get uart device */ + uart = &uart1_device; + uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1; + uart1_device.UART_IRQn = UART1_IRQn; - /* device initialization */ - uart->parent.type = RT_Device_Class_Char; - rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); - uart->read_index = uart->save_index = 0; + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; - /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; - uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; - uart->parent.write = rt_uart_write; - uart->parent.control = RT_NULL; - uart->parent.user_data = RT_NULL; + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.user_data = RT_NULL; - rt_device_register(&uart->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&uart->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lpc178x/rtconfig.h b/bsp/lpc178x/rtconfig.h index 25f99888f7..ce51ba355f 100644 --- a/bsp/lpc178x/rtconfig.h +++ b/bsp/lpc178x/rtconfig.h @@ -5,17 +5,17 @@ // // -#define RT_NAME_MAX 6 +#define RT_NAME_MAX 6 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
#define RT_DEBUG #define RT_DEBUG_COLOR @@ -30,11 +30,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -66,13 +66,13 @@ //
#define RT_USING_DEVICE // -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 //
//
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 //
// @@ -84,7 +84,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -99,18 +99,18 @@ // // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -120,7 +120,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -136,31 +136,31 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_PBUF_NUM 4 +#define RT_LWIP_PBUF_NUM 4 // -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_LWIP_TCP_PCB_NUM 3 // -#define RT_LWIP_TCP_SND_BUF 2048 +#define RT_LWIP_TCP_SND_BUF 2048 // -#define RT_LWIP_TCP_WND 2048 +#define RT_LWIP_TCP_WND 2048 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCP_SEG_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 4 // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR0 192 #define RT_LWIP_IPADDR1 168 @@ -181,7 +181,7 @@ //
// #define RT_USING_RTGUI // -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 // #define RTGUI_USING_SMALL_SIZE // @@ -191,7 +191,7 @@ // #define RTGUI_USING_FONTHZ // -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 // // #define RTGUI_USING_DFS_FILERW // diff --git a/bsp/lpc2148/applications/application.c b/bsp/lpc2148/applications/application.c index fd07f22f05..731b30a510 100644 --- a/bsp/lpc2148/applications/application.c +++ b/bsp/lpc2148/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2148/applications/startup.c b/bsp/lpc2148/applications/startup.c index cc16a5c12b..a3229083ac 100644 --- a/bsp/lpc2148/applications/startup.c +++ b/bsp/lpc2148/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2148/drivers/board.c b/bsp/lpc2148/drivers/board.c index 96a4aa62f4..757e1cb8f0 100644 --- a/bsp/lpc2148/drivers/board.c +++ b/bsp/lpc2148/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -25,13 +25,13 @@ */ void rt_hw_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); - /* clear interrupt flag */ - T0IR |= 0x01; + /* clear interrupt flag */ + T0IR |= 0x01; - /* acknowledge Interrupt */ - VICVectAddr = 0; + /* acknowledge Interrupt */ + VICVectAddr = 0; } /** @@ -42,37 +42,37 @@ void rt_hw_timer_handler(int vector, void *param) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - while (!(U0LSR & 0x20)); - U0THR = '\r'; - } + while (*str) + { + if (*str=='\n') + { + while (!(U0LSR & 0x20)); + U0THR = '\r'; + } - while (!(U0LSR & 0x20)); - U0THR = *str; + while (!(U0LSR & 0x20)); + U0THR = *str; - str ++; - } + str ++; + } } -#define BAUD_RATE 115200 -#define U0PINS 0x05 +#define BAUD_RATE 115200 +#define U0PINS 0x05 void rt_hw_console_init() { - /* Enable RxD and TxD pins */ - PINSEL0 = U0PINS; + /* Enable RxD and TxD pins */ + PINSEL0 = U0PINS; - /* 8 bits, no Parity, 1 Stop bit */ - U0LCR = 0x83; + /* 8 bits, no Parity, 1 Stop bit */ + U0LCR = 0x83; - /* Setup Baudrate */ - U0DLL = (PCLK/16/BAUD_RATE) & 0xFF; - U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF; + /* Setup Baudrate */ + U0DLL = (PCLK/16/BAUD_RATE) & 0xFF; + U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF; - /* DLAB = 0 */ - U0LCR = 0x03; + /* DLAB = 0 */ + U0LCR = 0x03; } /** @@ -80,23 +80,23 @@ void rt_hw_console_init() */ void rt_hw_board_init(void) { - /* console init */ - rt_hw_console_init(); + /* console init */ + rt_hw_console_init(); - /* prescaler = 0*/ - T0PR = 0; - T0PC = 0; + /* prescaler = 0*/ + T0PR = 0; + T0PC = 0; - /* reset and enable MR0 interrupt */ - T0MCR = 0x3; - T0MR0 = PCLK / RT_TICK_PER_SECOND; + /* reset and enable MR0 interrupt */ + T0MCR = 0x3; + T0MR0 = PCLK / RT_TICK_PER_SECOND; - /* enable timer 0 */ - T0TCR = 1; + /* enable timer 0 */ + T0TCR = 1; - /* install timer handler */ - rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0"); - rt_hw_interrupt_umask(TIMER0_INT); + /* install timer handler */ + rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0"); + rt_hw_interrupt_umask(TIMER0_INT); } /*@}*/ diff --git a/bsp/lpc2148/drivers/board.h b/bsp/lpc2148/drivers/board.h index 346f10182f..957f360652 100644 --- a/bsp/lpc2148/drivers/board.h +++ b/bsp/lpc2148/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,13 +12,13 @@ #define __BOARD_H__ #include -#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ -#define PCLK 15000000 /* CCLK/4, use default */ +#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ +#define PCLK 15000000 /* CCLK/4, use default */ /* RT_USING_UART */ #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 void rt_hw_board_init(void); diff --git a/bsp/lpc2148/drivers/dm9000.c b/bsp/lpc2148/drivers/dm9000.c index 169be59f12..9bc8d445f9 100644 --- a/bsp/lpc2148/drivers/dm9000.c +++ b/bsp/lpc2148/drivers/dm9000.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ #define MAX_ADDR_LEN 6 struct rt_dm9000_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct rt_dm9000_eth dm9000_device; @@ -52,67 +52,67 @@ static rt_err_t rt_dm9000_init(rt_device_t dev) static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_dm9000_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_dm9000_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, dm9000_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, dm9000_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /* ethernet device interface */ /* transmit packet. */ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p) { - struct pbuf* q; - rt_uint32_t len; - rt_uint8_t* ptr; + struct pbuf* q; + rt_uint32_t len; + rt_uint8_t* ptr; - for (q = p; q != NULL; q = q->next) - { - len = q->len; - ptr = q->payload; + for (q = p; q != NULL; q = q->next) + { + len = q->len; + ptr = q->payload; - /* write data to device */ - } + /* write data to device */ + } - return RT_EOK; + return RT_EOK; } /* reception packet. */ struct pbuf *rt_dm9000_rx(rt_device_t dev) { struct pbuf* p; - rt_uint32_t len; + rt_uint32_t len; /* init p pointer */ p = RT_NULL; @@ -149,17 +149,17 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev) void rt_hw_dm9000_init() { - dm9000_device.parent.parent.init = rt_dm9000_init; - dm9000_device.parent.parent.open = rt_dm9000_open; - dm9000_device.parent.parent.close = rt_dm9000_close; - dm9000_device.parent.parent.read = rt_dm9000_read; - dm9000_device.parent.parent.write = rt_dm9000_write; - dm9000_device.parent.parent.control = rt_dm9000_control; - dm9000_device.parent.parent.user_data = RT_NULL; + dm9000_device.parent.parent.init = rt_dm9000_init; + dm9000_device.parent.parent.open = rt_dm9000_open; + dm9000_device.parent.parent.close = rt_dm9000_close; + dm9000_device.parent.parent.read = rt_dm9000_read; + dm9000_device.parent.parent.write = rt_dm9000_write; + dm9000_device.parent.parent.control = rt_dm9000_control; + dm9000_device.parent.parent.user_data = RT_NULL; - dm9000_device.parent.eth_rx = rt_dm9000_rx; - dm9000_device.parent.eth_tx = rt_dm9000_tx; + dm9000_device.parent.eth_rx = rt_dm9000_rx; + dm9000_device.parent.eth_tx = rt_dm9000_tx; - rt_device_register((rt_device_t)&dm9000_device, - "E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX); + rt_device_register((rt_device_t)&dm9000_device, + "E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX); } diff --git a/bsp/lpc2148/drivers/sd.c b/bsp/lpc2148/drivers/sd.c index d7b6769621..144c9f2ff5 100644 --- a/bsp/lpc2148/drivers/sd.c +++ b/bsp/lpc2148/drivers/sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,12 +22,12 @@ static rt_err_t rt_sdcard_init(rt_device_t dev) static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_sdcard_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) @@ -48,54 +48,54 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } void rt_hw_sdcard_init() { rt_size_t length; - rt_uint8_t* sector; + rt_uint8_t* sector; /* sdcard hardware init */ - sd.type = RT_Device_Class_Block; - sd.init = rt_sdcard_init; - sd.open = rt_sdcard_open; - sd.close = rt_sdcard_close; - sd.read = rt_sdcard_read; - sd.write = rt_sdcard_write; - sd.control = rt_sdcard_control; - sd.user_data = RT_NULL; + sd.type = RT_Device_Class_Block; + sd.init = rt_sdcard_init; + sd.open = rt_sdcard_open; + sd.close = rt_sdcard_close; + sd.read = rt_sdcard_read; + sd.write = rt_sdcard_write; + sd.control = rt_sdcard_control; + sd.user_data = RT_NULL; - /* get the first sector to read partition table */ - sector = (rt_uint8_t*) rt_malloc (512); - if (sector == RT_NULL) - { - rt_kprintf("allocate partition sector buffer failed\n"); - return; - } + /* get the first sector to read partition table */ + sector = (rt_uint8_t*) rt_malloc (512); + if (sector == RT_NULL) + { + rt_kprintf("allocate partition sector buffer failed\n"); + return; + } - length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512); - if (length == 512) - { - rt_err_t status; + length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512); + if (length == 512) + { + rt_err_t status; - /* get the first partition */ - status = dfs_filesystem_get_partition(&part, sector, 0); - if (status != RT_EOK) - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } - } - else - { - /* there is no partition table */ - part.offset = 0; - part.size = 0; - } + /* get the first partition */ + status = dfs_filesystem_get_partition(&part, sector, 0); + if (status != RT_EOK) + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } - rt_device_register(&sd, - "sd", RT_DEVICE_FLAG_RDWR); + rt_device_register(&sd, + "sd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/lpc2148/drivers/serial.c b/bsp/lpc2148/drivers/serial.c index 0c78ecc026..36bbcbd608 100644 --- a/bsp/lpc2148/drivers/serial.c +++ b/bsp/lpc2148/drivers/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,8 +15,8 @@ #include "board.h" /* serial hardware register */ -#define REG8(d) (*((volatile unsigned char *)(d))) -#define REG32(d) (*((volatile unsigned long *)(d))) +#define REG8(d) (*((volatile unsigned char *)(d))) +#define REG32(d) (*((volatile unsigned long *)(d))) #define UART_RBR(base) REG8(base + 0x00) #define UART_THR(base) REG8(base + 0x00) @@ -37,16 +37,16 @@ /* LPC serial device */ struct rt_lpcserial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -58,70 +58,70 @@ struct rt_lpcserial serial2; void rt_hw_serial_init(void); -#define U0PINS 0x00000005 +#define U0PINS 0x00000005 void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial) { - RT_UNUSED rt_uint32_t iir; + RT_UNUSED rt_uint32_t iir; - RT_ASSERT(lpc_serial != RT_NULL) + RT_ASSERT(lpc_serial != RT_NULL) - if (UART_LSR(lpc_serial->hw_base) & 0x01) - { - rt_base_t level; + if (UART_LSR(lpc_serial->hw_base) & 0x01) + { + rt_base_t level; - while (UART_LSR(lpc_serial->hw_base) & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + while (UART_LSR(lpc_serial->hw_base) & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* read character */ - lpc_serial->rx_buffer[lpc_serial->save_index] = - UART_RBR(lpc_serial->hw_base); - lpc_serial->save_index ++; - if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->save_index = 0; + /* read character */ + lpc_serial->rx_buffer[lpc_serial->save_index] = + UART_RBR(lpc_serial->hw_base); + lpc_serial->save_index ++; + if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (lpc_serial->save_index == lpc_serial->read_index) - { - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (lpc_serial->save_index == lpc_serial->read_index) + { + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } - /* invoke callback */ - if(lpc_serial->parent.rx_indicate != RT_NULL) - { - lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); - } - } + /* invoke callback */ + if(lpc_serial->parent.rx_indicate != RT_NULL) + { + lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); + } + } - /* clear interrupt source */ - iir = UART_IIR(lpc_serial->hw_base); + /* clear interrupt source */ + iir = UART_IIR(lpc_serial->hw_base); - /* acknowledge Interrupt */ - VICVectAddr = 0; + /* acknowledge Interrupt */ + VICVectAddr = 0; } #ifdef RT_USING_UART1 void rt_hw_uart_isr_1(int irqno, void *param) { - /* get lpc serial device */ - rt_hw_uart_isr(&serial1); -} + /* get lpc serial device */ + rt_hw_uart_isr(&serial1); +} #endif #ifdef RT_USING_UART2 void rt_hw_uart_isr_2(int irqno, void *param) { - /* get lpc serial device */ - rt_hw_uart_isr(&serial2); -} + /* get lpc serial device */ + rt_hw_uart_isr(&serial2); +} #endif /** @@ -131,256 +131,256 @@ void rt_hw_uart_isr_2(int irqno, void *param) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; - - RT_ASSERT(lpc_serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* init UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x01; + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; - /* install ISR */ - if (lpc_serial->irqno == UART0_INT) - { + RT_ASSERT(lpc_serial != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* init UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x01; + + /* install ISR */ + if (lpc_serial->irqno == UART0_INT) + { #ifdef RT_USING_UART1 - rt_hw_interrupt_install(lpc_serial->irqno, + rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_1, &serial1, "UART1"); #endif - } - else - { + } + else + { #ifdef RT_USING_UART2 - rt_hw_interrupt_install(lpc_serial->irqno, + rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_2, &serial2, "UART2"); #endif - } + } - rt_hw_interrupt_umask(lpc_serial->irqno); - } + rt_hw_interrupt_umask(lpc_serial->irqno); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; - RT_ASSERT(lpc_serial != RT_NULL); + RT_ASSERT(lpc_serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x00; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x00; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; - RT_ASSERT(lpc_serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; + RT_ASSERT(lpc_serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (lpc_serial->read_index != lpc_serial->save_index) - { - *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (lpc_serial->read_index != lpc_serial->save_index) + { + *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } - /* polling mode */ - while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) - { - /* Read Character */ - *ptr = UART_RBR(lpc_serial->hw_base); + /* polling mode */ + while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) + { + /* Read Character */ + *ptr = UART_RBR(lpc_serial->hw_base); - ptr ++; - size --; - } + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lpcserial* lpc_serial; - char *ptr; + struct rt_lpcserial* lpc_serial; + char *ptr; - lpc_serial = (struct rt_lpcserial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } + lpc_serial = (struct rt_lpcserial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } - /* polling write */ - ptr = (char *)buffer; + /* polling write */ + ptr = (char *)buffer; - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = '\r'; - } + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = '\r'; + } - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; - ptr ++; - size --; - } - } - else - { - while (size) - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; + ptr ++; + size --; + } + } + else + { + while (size) + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; - ptr ++; - size --; - } - } + ptr ++; + size --; + } + } - return (rt_size_t) ptr - (rt_size_t) buffer; + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lpcserial* lpc_serial; + struct rt_lpcserial* lpc_serial; #ifdef RT_USING_UART1 - lpc_serial = &serial1; + lpc_serial = &serial1; - lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->hw_base = 0xE000C000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART0_INT; + lpc_serial->hw_base = 0xE000C000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART0_INT; - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; - /* Enable UART0 RxD and TxD pins */ + /* Enable UART0 RxD and TxD pins */ PINSEL0 |= 0x05; - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; - rt_device_register(&lpc_serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&lpc_serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - lpc_serial = &serial2; + lpc_serial = &serial2; - lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->hw_base = 0xE0010000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART1_INT; + lpc_serial->hw_base = 0xE0010000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART1_INT; - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; - /* Enable UART1 RxD and TxD pins */ - PINSEL0 |= 0x05 << 16; + /* Enable UART1 RxD and TxD pins */ + PINSEL0 |= 0x05 << 16; - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; - rt_device_register(&lpc_serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + rt_device_register(&lpc_serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lpc2148/rtconfig.h b/bsp/lpc2148/rtconfig.h index 60887daac1..220742ce41 100644 --- a/bsp/lpc2148/rtconfig.h +++ b/bsp/lpc2148/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -62,12 +62,12 @@ #define RT_USING_DEVICE #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -87,11 +87,11 @@ /* SECTION: DFS options */ /* #define RT_USING_DFS */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 8 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 8 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* Using lighweight TCP/IP protocol stack*/ @@ -119,21 +119,21 @@ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 0 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 0 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 #endif diff --git a/bsp/lpc2478/applications/application.c b/bsp/lpc2478/applications/application.c index 64dbf3c807..fa10f80d56 100644 --- a/bsp/lpc2478/applications/application.c +++ b/bsp/lpc2478/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2478/applications/startup.c b/bsp/lpc2478/applications/startup.c index 0b961e4f94..05dee0ef8e 100644 --- a/bsp/lpc2478/applications/startup.c +++ b/bsp/lpc2478/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc2478/drivers/board.c b/bsp/lpc2478/drivers/board.c index 65ff918711..956ec5c03f 100644 --- a/bsp/lpc2478/drivers/board.c +++ b/bsp/lpc2478/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ #include #include "board.h" -#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */ +#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */ extern void rt_hw_serial_init(void); @@ -25,9 +25,9 @@ extern void rt_hw_serial_init(void); void rt_timer_handler(int vector, void* param) { - T0IR |= 0x01; /* clear interrupt flag */ - rt_tick_increase(); - VICVectAddr = 0; /* Acknowledge Interrupt */ + T0IR |= 0x01; /* clear interrupt flag */ + rt_tick_increase(); + VICVectAddr = 0; /* Acknowledge Interrupt */ } /** @@ -36,19 +36,19 @@ void rt_timer_handler(int vector, void* param) void rt_hw_board_init(void) { #if defined(RT_USING_DEVICE) && defined(RT_USING_UART1) - rt_hw_serial_init(); - rt_console_set_device("uart1"); + rt_hw_serial_init(); + rt_console_set_device("uart1"); #endif - T0IR = 0xff; - T0TC = 0; - T0MCR = 0x03; - T0MR0 = (DATA_COUNT); + T0IR = 0xff; + T0TC = 0; + T0MCR = 0x03; + T0MR0 = (DATA_COUNT); - rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(TIMER0_INT); + rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(TIMER0_INT); - T0TCR = 0x01; //enable timer0 counter + T0TCR = 0x01; //enable timer0 counter } /*@}*/ diff --git a/bsp/lpc2478/drivers/board.h b/bsp/lpc2478/drivers/board.h index 6386c19ba8..075fe354b8 100644 --- a/bsp/lpc2478/drivers/board.h +++ b/bsp/lpc2478/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ /* RT_USING_UART */ #define RT_USING_UART1 #define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 void rt_hw_board_init(void); void rt_hw_led_set(rt_uint32_t led); void rt_hw_led_flash(void); @@ -23,93 +23,93 @@ void rt_hw_led_flash(void); void rt_hw_finsh_init(void); #endif -#define USE_USB 0 +#define USE_USB 0 -#if USE_USB /* 1 is USB, 0 is non-USB related */ -#define PLL_MValue 11 -#define PLL_NValue 0 -#define CCLKDivValue 4 -#define USBCLKDivValue 5 +#if USE_USB /* 1 is USB, 0 is non-USB related */ +#define PLL_MValue 11 +#define PLL_NValue 0 +#define CCLKDivValue 4 +#define USBCLKDivValue 5 -#define Fosc 12000000 -#define Fcclk 57600000 -#define Fcco 288000000 +#define Fosc 12000000 +#define Fcclk 57600000 +#define Fcco 288000000 #else -#define PLL_MValue 12 -#define PLL_NValue 1 -#define CCLKDivValue 5 +#define PLL_MValue 12 +#define PLL_NValue 1 +#define CCLKDivValue 5 -#define Fosc 12000000 -#define Fcclk 72000000 -#define Fcco 360000000 +#define Fosc 12000000 +#define Fcclk 72000000 +#define Fcco 360000000 #endif #if USE_USB -#define Fpclk (Fcclk / 2) +#define Fpclk (Fcclk / 2) #else -#define Fpclk (Fcclk / 4) +#define Fpclk (Fcclk / 4) #endif /* IRQ define */ -#define SYS32Mode 0x1F -#define IRQ32Mode 0x12 -#define FIQ32Mode 0x11 +#define SYS32Mode 0x1F +#define IRQ32Mode 0x12 +#define FIQ32Mode 0x11 -#define HIGHEST_PRIORITY 0x01 -#define LOWEST_PRIORITY 0x0F +#define HIGHEST_PRIORITY 0x01 +#define LOWEST_PRIORITY 0x0F -#define WDT_INT 0 -#define SWI_INT 1 -#define ARM_CORE0_INT 2 -#define ARM_CORE1_INT 3 -#define TIMER0_INT 4 -#define TIMER1_INT 5 -#define UART0_INT 6 -#define UART1_INT 7 -#define PWM0_1_INT 8 -#define I2C0_INT 9 -#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ -#define SSP0_INT 10 -#define SSP1_INT 11 -#define PLL_INT 12 -#define RTC_INT 13 -#define EINT0_INT 14 -#define EINT1_INT 15 -#define EINT2_INT 16 -#define EINT3_INT 17 -#define ADC0_INT 18 -#define I2C1_INT 19 -#define BOD_INT 20 -#define EMAC_INT 21 -#define USB_INT 22 -#define CAN_INT 23 -#define MCI_INT 24 -#define GPDMA_INT 25 -#define TIMER2_INT 26 -#define TIMER3_INT 27 -#define UART2_INT 28 -#define UART3_INT 29 -#define I2C2_INT 30 -#define I2S_INT 31 +#define WDT_INT 0 +#define SWI_INT 1 +#define ARM_CORE0_INT 2 +#define ARM_CORE1_INT 3 +#define TIMER0_INT 4 +#define TIMER1_INT 5 +#define UART0_INT 6 +#define UART1_INT 7 +#define PWM0_1_INT 8 +#define I2C0_INT 9 +#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ +#define SSP0_INT 10 +#define SSP1_INT 11 +#define PLL_INT 12 +#define RTC_INT 13 +#define EINT0_INT 14 +#define EINT1_INT 15 +#define EINT2_INT 16 +#define EINT3_INT 17 +#define ADC0_INT 18 +#define I2C1_INT 19 +#define BOD_INT 20 +#define EMAC_INT 21 +#define USB_INT 22 +#define CAN_INT 23 +#define MCI_INT 24 +#define GPDMA_INT 25 +#define TIMER2_INT 26 +#define TIMER3_INT 27 +#define UART2_INT 28 +#define UART3_INT 29 +#define I2C2_INT 30 +#define I2S_INT 31 -#define VIC_SIZE 32 +#define VIC_SIZE 32 -#define VECT_ADDR_INDEX 0x100 +#define VECT_ADDR_INDEX 0x100 #define VECT_CNTL_INDEX 0x200 -#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ -#define PCLK 15000000 /* CCLK/4, use default */ +#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */ +#define PCLK 15000000 /* CCLK/4, use default */ /****************************************************************************** -** Function name: TargetInit +** Function name: TargetInit ** -** Descriptions: Initialize the target board; it is called in a -** necessary place, change it as needed +** Descriptions: Initialize the target board; it is called in a +** necessary place, change it as needed ** -** parameters: None -** Returned value: None +** parameters: None +** Returned value: None ** ******************************************************************************/ extern void TargetInit(void); diff --git a/bsp/lpc2478/drivers/serial.c b/bsp/lpc2478/drivers/serial.c index dff575c7cc..8e1fe1f91f 100644 --- a/bsp/lpc2478/drivers/serial.c +++ b/bsp/lpc2478/drivers/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,8 +15,8 @@ #include "board.h" /* serial hardware register */ -#define REG8(d) (*((volatile unsigned char *)(d))) -#define REG32(d) (*((volatile unsigned long *)(d))) +#define REG8(d) (*((volatile unsigned char *)(d))) +#define REG32(d) (*((volatile unsigned long *)(d))) #define UART_RBR(base) REG8(base + 0x00) #define UART_THR(base) REG8(base + 0x00) @@ -37,16 +37,16 @@ /* LPC serial device */ struct rt_lpcserial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 @@ -58,55 +58,55 @@ struct rt_lpcserial serial2; void rt_hw_serial_init(void); -#define U0PINS 0x00000005 +#define U0PINS 0x00000005 void rt_hw_uart_isr(int irqno, void *param) { - RT_UNUSED rt_uint32_t iir; - struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param; + RT_UNUSED rt_uint32_t iir; + struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param; - RT_ASSERT(lpc_serial != RT_NULL) - - if (UART_LSR(lpc_serial->hw_base) & 0x01) - { - rt_base_t level; + RT_ASSERT(lpc_serial != RT_NULL) - while (UART_LSR(lpc_serial->hw_base) & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + if (UART_LSR(lpc_serial->hw_base) & 0x01) + { + rt_base_t level; - /* read character */ - lpc_serial->rx_buffer[lpc_serial->save_index] = - UART_RBR(lpc_serial->hw_base); - lpc_serial->save_index ++; - if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (lpc_serial->save_index == lpc_serial->read_index) - { - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } + while (UART_LSR(lpc_serial->hw_base) & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + /* read character */ + lpc_serial->rx_buffer[lpc_serial->save_index] = + UART_RBR(lpc_serial->hw_base); + lpc_serial->save_index ++; + if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->save_index = 0; - /* invoke callback */ - if(lpc_serial->parent.rx_indicate != RT_NULL) - { - lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); - } - } + /* if the next position is read index, discard this 'read char' */ + if (lpc_serial->save_index == lpc_serial->read_index) + { + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } - /* clear interrupt source */ - iir = UART_IIR(lpc_serial->hw_base); + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } - /* acknowledge Interrupt */ - VICVectAddr = 0; + /* invoke callback */ + if(lpc_serial->parent.rx_indicate != RT_NULL) + { + lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1); + } + } + + /* clear interrupt source */ + iir = UART_IIR(lpc_serial->hw_base); + + /* acknowledge Interrupt */ + VICVectAddr = 0; } @@ -117,243 +117,243 @@ void rt_hw_uart_isr(int irqno, void *param) static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; - - RT_ASSERT(lpc_serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* init UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x01; + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; - /* install ISR */ - rt_hw_interrupt_install(lpc_serial->irqno, + RT_ASSERT(lpc_serial != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* init UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x01; + + /* install ISR */ + rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr, lpc_serial, RT_NULL); - rt_hw_interrupt_umask(lpc_serial->irqno); - } + rt_hw_interrupt_umask(lpc_serial->irqno); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_lpcserial* lpc_serial; - lpc_serial = (struct rt_lpcserial*) dev; - - RT_ASSERT(lpc_serial != RT_NULL); + struct rt_lpcserial* lpc_serial; + lpc_serial = (struct rt_lpcserial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable UART rx interrupt */ - UART_IER(lpc_serial->hw_base) = 0x00; - } + RT_ASSERT(lpc_serial != RT_NULL); - return RT_EOK; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable UART rx interrupt */ + UART_IER(lpc_serial->hw_base) = 0x00; + } + + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; - RT_ASSERT(lpc_serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev; + RT_ASSERT(lpc_serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (lpc_serial->read_index != lpc_serial->save_index) - { - *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (lpc_serial->read_index != lpc_serial->save_index) + { + *ptr = lpc_serial->rx_buffer[lpc_serial->read_index]; - lpc_serial->read_index ++; - if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) - lpc_serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + lpc_serial->read_index ++; + if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE) + lpc_serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } - /* polling mode */ - while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) - { - /* Read Character */ - *ptr = UART_RBR(lpc_serial->hw_base); - - ptr ++; - size --; - } + /* polling mode */ + while (size && (UART_LSR(lpc_serial->hw_base) & 0x01)) + { + /* Read Character */ + *ptr = UART_RBR(lpc_serial->hw_base); - return (rt_size_t)ptr - (rt_size_t)buffer; + ptr ++; + size --; + } + + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - struct rt_lpcserial* lpc_serial; - char *ptr; + struct rt_lpcserial* lpc_serial; + char *ptr; - lpc_serial = (struct rt_lpcserial*) dev; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } + lpc_serial = (struct rt_lpcserial*) dev; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = '\r'; - } + /* polling write */ + ptr = (char *)buffer; - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; - - ptr ++; - size --; - } - } - else - { - while (size) - { - while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); - UART_THR(lpc_serial->hw_base) = *ptr; - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = '\r'; + } + + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; + + ptr ++; + size --; + } + } + else + { + while (size) + { + while (!(UART_LSR(lpc_serial->hw_base) & 0x20)); + UART_THR(lpc_serial->hw_base) = *ptr; + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_hw_serial_init(void) { - struct rt_lpcserial* lpc_serial; - + struct rt_lpcserial* lpc_serial; + #ifdef RT_USING_UART1 - lpc_serial = &serial1; - - lpc_serial->parent.type = RT_Device_Class_Char; - - lpc_serial->hw_base = 0xE000C000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART0_INT; - - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; + lpc_serial = &serial1; - /* Enable UART0 RxD and TxD pins */ - PINSEL0 |= 0x50; + lpc_serial->parent.type = RT_Device_Class_Char; - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; - - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + lpc_serial->hw_base = 0xE000C000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART0_INT; - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; + /* Enable UART0 RxD and TxD pins */ + PINSEL0 |= 0x50; - rt_device_register(&lpc_serial->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; + + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; + + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; + + rt_device_register(&lpc_serial->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); #endif #ifdef RT_USING_UART2 - lpc_serial = &serial2; - - lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial = &serial2; - lpc_serial->hw_base = 0xE0010000; - lpc_serial->baudrate = 115200; - lpc_serial->irqno = UART1_INT; + lpc_serial->parent.type = RT_Device_Class_Char; - rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); - lpc_serial->read_index = lpc_serial->save_index = 0; + lpc_serial->hw_base = 0xE0010000; + lpc_serial->baudrate = 115200; + lpc_serial->irqno = UART1_INT; - /* Enable UART1 RxD and TxD pins */ - PINSEL0 |= 0x05 << 16; + rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer)); + lpc_serial->read_index = lpc_serial->save_index = 0; - /* 8 bits, no Parity, 1 Stop bit */ - UART_LCR(lpc_serial->hw_base) = 0x83; - - /* Setup Baudrate */ - UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; - UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; + /* Enable UART1 RxD and TxD pins */ + PINSEL0 |= 0x05 << 16; - /* DLAB = 0 */ - UART_LCR(lpc_serial->hw_base) = 0x03; + /* 8 bits, no Parity, 1 Stop bit */ + UART_LCR(lpc_serial->hw_base) = 0x83; - lpc_serial->parent.type = RT_Device_Class_Char; - lpc_serial->parent.init = rt_serial_init; - lpc_serial->parent.open = rt_serial_open; - lpc_serial->parent.close = rt_serial_close; - lpc_serial->parent.read = rt_serial_read; - lpc_serial->parent.write = rt_serial_write; - lpc_serial->parent.control = rt_serial_control; - lpc_serial->parent.user_data = RT_NULL; + /* Setup Baudrate */ + UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF; + UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF; - rt_device_register(&lpc_serial->parent, - "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* DLAB = 0 */ + UART_LCR(lpc_serial->hw_base) = 0x03; + + lpc_serial->parent.type = RT_Device_Class_Char; + lpc_serial->parent.init = rt_serial_init; + lpc_serial->parent.open = rt_serial_open; + lpc_serial->parent.close = rt_serial_close; + lpc_serial->parent.read = rt_serial_read; + lpc_serial->parent.write = rt_serial_write; + lpc_serial->parent.control = rt_serial_control; + lpc_serial->parent.user_data = RT_NULL; + + rt_device_register(&lpc_serial->parent, + "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif } diff --git a/bsp/lpc2478/rtconfig.h b/bsp/lpc2478/rtconfig.h index c35691aa80..d0c419d9ff 100644 --- a/bsp/lpc2478/rtconfig.h +++ b/bsp/lpc2478/rtconfig.h @@ -3,22 +3,22 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 #define RT_TIMER_THREAD_PRIO 1 /* Rate at which timer management task runs (Hz) */ -#define RT_TIMER_EX_TICKS_PER_SEC 10 +#define RT_TIMER_EX_TICKS_PER_SEC 10 /* SECTION: RT_DEBUG */ @@ -67,7 +67,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -102,21 +102,21 @@ /* #define RT_LWIP_DHCP */ /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 0 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 0 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 0 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 0 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 #endif diff --git a/bsp/lpc408x/applications/main.c b/bsp/lpc408x/applications/main.c index 7874a25073..93495ce8c0 100644 --- a/bsp/lpc408x/applications/main.c +++ b/bsp/lpc408x/applications/main.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-10 armink first version + * 2018-12-10 armink first version */ #include @@ -14,6 +14,6 @@ int main(void) { rt_kprintf("Hello RT-Thread!\n"); - + return RT_EOK; -} +} diff --git a/bsp/lpc408x/drivers/board.c b/bsp/lpc408x/drivers/board.c index 8db9473876..23e0ec07ac 100644 --- a/bsp/lpc408x/drivers/board.c +++ b/bsp/lpc408x/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/board.h b/bsp/lpc408x/drivers/board.h index 1cc74d0fd6..0b4946ced7 100644 --- a/bsp/lpc408x/drivers/board.h +++ b/bsp/lpc408x/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_emac.c b/bsp/lpc408x/drivers/drv_emac.c index 7ea47d52ed..0bae0f1456 100644 --- a/bsp/lpc408x/drivers/drv_emac.c +++ b/bsp/lpc408x/drivers/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_emac.h b/bsp/lpc408x/drivers/drv_emac.h index 7d67eae178..ce5ca7d9e3 100644 --- a/bsp/lpc408x/drivers/drv_emac.h +++ b/bsp/lpc408x/drivers/drv_emac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_hwtimer.c b/bsp/lpc408x/drivers/drv_hwtimer.c index fa09f87d76..0357c2c1f9 100644 --- a/bsp/lpc408x/drivers/drv_hwtimer.c +++ b/bsp/lpc408x/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_hwtimer.h b/bsp/lpc408x/drivers/drv_hwtimer.h index 21c5a25eeb..ca34816a77 100644 --- a/bsp/lpc408x/drivers/drv_hwtimer.h +++ b/bsp/lpc408x/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_led.c b/bsp/lpc408x/drivers/drv_led.c index d7df12ba82..29c74af1af 100644 --- a/bsp/lpc408x/drivers/drv_led.c +++ b/bsp/lpc408x/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_led.h b/bsp/lpc408x/drivers/drv_led.h index f3a958c9b5..d006ac7ee6 100644 --- a/bsp/lpc408x/drivers/drv_led.h +++ b/bsp/lpc408x/drivers/drv_led.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_sdram.c b/bsp/lpc408x/drivers/drv_sdram.c index 0bb9ec6eb3..a0473bae01 100644 --- a/bsp/lpc408x/drivers/drv_sdram.c +++ b/bsp/lpc408x/drivers/drv_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_sdram.h b/bsp/lpc408x/drivers/drv_sdram.h index 74ceab2d18..0722e02d9d 100644 --- a/bsp/lpc408x/drivers/drv_sdram.h +++ b/bsp/lpc408x/drivers/drv_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_uart.c b/bsp/lpc408x/drivers/drv_uart.c index 09a518f4ab..3b11a851db 100644 --- a/bsp/lpc408x/drivers/drv_uart.c +++ b/bsp/lpc408x/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc408x/drivers/drv_uart.h b/bsp/lpc408x/drivers/drv_uart.h index 6fbe0535a5..3d8988e3ac 100644 --- a/bsp/lpc408x/drivers/drv_uart.h +++ b/bsp/lpc408x/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/application.c b/bsp/lpc43xx/M0/applications/application.c index 2a9cec5103..1b14f82cd7 100644 --- a/bsp/lpc43xx/M0/applications/application.c +++ b/bsp/lpc43xx/M0/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/board.c b/bsp/lpc43xx/M0/applications/board.c index cd1cf62df0..26d9cd404c 100644 --- a/bsp/lpc43xx/M0/applications/board.c +++ b/bsp/lpc43xx/M0/applications/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/board.h b/bsp/lpc43xx/M0/applications/board.h index 24dfee67d4..8462dad0f6 100644 --- a/bsp/lpc43xx/M0/applications/board.h +++ b/bsp/lpc43xx/M0/applications/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/startup.c b/bsp/lpc43xx/M0/applications/startup.c index df9cb7a211..65d430d64a 100644 --- a/bsp/lpc43xx/M0/applications/startup.c +++ b/bsp/lpc43xx/M0/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M0/applications/vbus_drv.c b/bsp/lpc43xx/M0/applications/vbus_drv.c index 696535247f..8d90d72bfb 100644 --- a/bsp/lpc43xx/M0/applications/vbus_drv.c +++ b/bsp/lpc43xx/M0/applications/vbus_drv.c @@ -1,6 +1,6 @@ /* - * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M0/applications/vbus_hw.h b/bsp/lpc43xx/M0/applications/vbus_hw.h index 850466cc45..d269a7c907 100644 --- a/bsp/lpc43xx/M0/applications/vbus_hw.h +++ b/bsp/lpc43xx/M0/applications/vbus_hw.h @@ -1,6 +1,6 @@ /* - * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/application.c b/bsp/lpc43xx/M4/applications/application.c index 8fb1a4ae83..03e56fa955 100644 --- a/bsp/lpc43xx/M4/applications/application.c +++ b/bsp/lpc43xx/M4/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -32,10 +32,10 @@ static void _boot_M0(void) LPC_CREG->M0APPMEMMAP = (uint32_t)&_M0_CODE[0]; - // Release Slave from reset, first read status + // Release Slave from reset, first read status u32REG = LPC_RGU->RESET_ACTIVE_STATUS1; - // If the M0 is being held in reset, release it... + // If the M0 is being held in reset, release it... // 1 = no reset, 0 = reset while(!(u32REG & (1u << 24))) { diff --git a/bsp/lpc43xx/M4/applications/board.c b/bsp/lpc43xx/M4/applications/board.c index c6bfa10574..2f815060d5 100644 --- a/bsp/lpc43xx/M4/applications/board.c +++ b/bsp/lpc43xx/M4/applications/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M4/applications/board.h b/bsp/lpc43xx/M4/applications/board.h index 0450724e53..faf2930854 100644 --- a/bsp/lpc43xx/M4/applications/board.h +++ b/bsp/lpc43xx/M4/applications/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M4/applications/startup.c b/bsp/lpc43xx/M4/applications/startup.c index df9cb7a211..65d430d64a 100644 --- a/bsp/lpc43xx/M4/applications/startup.c +++ b/bsp/lpc43xx/M4/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/M4/applications/vbus_drv.c b/bsp/lpc43xx/M4/applications/vbus_drv.c index 09fd2373c4..4a3ee9dda6 100644 --- a/bsp/lpc43xx/M4/applications/vbus_drv.c +++ b/bsp/lpc43xx/M4/applications/vbus_drv.c @@ -1,6 +1,6 @@ /* - * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/M4/applications/vbus_hw.h b/bsp/lpc43xx/M4/applications/vbus_hw.h index 850466cc45..d269a7c907 100644 --- a/bsp/lpc43xx/M4/applications/vbus_hw.h +++ b/bsp/lpc43xx/M4/applications/vbus_hw.h @@ -1,6 +1,6 @@ /* - * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * Change Logs: * Date Author Notes diff --git a/bsp/lpc43xx/drivers/drv_emac.c b/bsp/lpc43xx/drivers/drv_emac.c index b8875c340c..a2df5dfd4d 100644 --- a/bsp/lpc43xx/drivers/drv_emac.c +++ b/bsp/lpc43xx/drivers/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/drivers/drv_emac.h b/bsp/lpc43xx/drivers/drv_emac.h index efaa0ac8e3..cde6d2742e 100644 --- a/bsp/lpc43xx/drivers/drv_emac.h +++ b/bsp/lpc43xx/drivers/drv_emac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/drivers/drv_led.c b/bsp/lpc43xx/drivers/drv_led.c index 73128c243c..464ddb4f9f 100644 --- a/bsp/lpc43xx/drivers/drv_led.c +++ b/bsp/lpc43xx/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc43xx/drivers/drv_uart.c b/bsp/lpc43xx/drivers/drv_uart.c index e1b203a359..f15f6fb760 100644 --- a/bsp/lpc43xx/drivers/drv_uart.c +++ b/bsp/lpc43xx/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -179,7 +179,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial0.ops = &lpc_uart_ops; serial0.config = config; @@ -230,7 +230,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial2.ops = &lpc_uart_ops; serial2.config = config; @@ -282,7 +282,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; serial3.ops = &lpc_uart_ops; serial3.config = config; diff --git a/bsp/lpc5410x/applications/application.c b/bsp/lpc5410x/applications/application.c index bad0922693..b99155b09d 100644 --- a/bsp/lpc5410x/applications/application.c +++ b/bsp/lpc5410x/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/applications/board.c b/bsp/lpc5410x/applications/board.c index 0fb09e6574..ff451b2f1c 100644 --- a/bsp/lpc5410x/applications/board.c +++ b/bsp/lpc5410x/applications/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -46,7 +46,7 @@ void rt_hw_board_init() SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); #endif SystemCoreClockUpdate(); - /* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/ + /* init systick 1 systick = 1/(100M / 100) 100个systick = 1s*/ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); /* set pend exception priority */ NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); diff --git a/bsp/lpc5410x/applications/board.h b/bsp/lpc5410x/applications/board.h index 5bbf8bc235..03f6a284e7 100644 --- a/bsp/lpc5410x/applications/board.h +++ b/bsp/lpc5410x/applications/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/applications/demo_thread.c b/bsp/lpc5410x/applications/demo_thread.c index 6acb8ae0ef..0d7ce2d2b8 100644 --- a/bsp/lpc5410x/applications/demo_thread.c +++ b/bsp/lpc5410x/applications/demo_thread.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,47 +10,47 @@ #include "drv_led.h" #include "drv_uart.h" -static void thread1_entry(void* parameter) +static void thread1_entry(void* parameter) { while(1) { - Led_Control(0,1); - rt_thread_delay(RT_TICK_PER_SECOND); - Led_Control(0,0); - rt_thread_delay(RT_TICK_PER_SECOND); + Led_Control(0,1); + rt_thread_delay(RT_TICK_PER_SECOND); + Led_Control(0,0); + rt_thread_delay(RT_TICK_PER_SECOND); } } -static void thread2_entry(void* parameter) +static void thread2_entry(void* parameter) { while(1) { - Led_Control(1,1); - rt_thread_delay(RT_TICK_PER_SECOND); - Led_Control(1,0); - rt_thread_delay(RT_TICK_PER_SECOND); - } + Led_Control(1,1); + rt_thread_delay(RT_TICK_PER_SECOND); + Led_Control(1,0); + rt_thread_delay(RT_TICK_PER_SECOND); + } } int demo_init(void) { - rt_thread_t thread1 = RT_NULL; - rt_thread_t thread2 = RT_NULL; - - - rt_led_hw_init(); - - - thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5); - if (thread1 != RT_NULL) - rt_thread_startup(thread1); + rt_thread_t thread1 = RT_NULL; + rt_thread_t thread2 = RT_NULL; - thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5); - if (thread2 != RT_NULL) - rt_thread_startup(thread2); - - return 0; - + rt_led_hw_init(); + + + thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5); + if (thread1 != RT_NULL) + rt_thread_startup(thread1); + + thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5); + if (thread2 != RT_NULL) + rt_thread_startup(thread2); + + + return 0; + } diff --git a/bsp/lpc5410x/applications/startup.c b/bsp/lpc5410x/applications/startup.c index 6f4ab94e82..0f50596ab1 100644 --- a/bsp/lpc5410x/applications/startup.c +++ b/bsp/lpc5410x/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/drivers/drv_led.c b/bsp/lpc5410x/drivers/drv_led.c index 8923e3fda4..108707aee1 100644 --- a/bsp/lpc5410x/drivers/drv_led.c +++ b/bsp/lpc5410x/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/drivers/drv_led.h b/bsp/lpc5410x/drivers/drv_led.h index 9ce2fea7be..87208c0e99 100644 --- a/bsp/lpc5410x/drivers/drv_led.h +++ b/bsp/lpc5410x/drivers/drv_led.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef __DRV_LED_H__ #define __DRV_LED_H__ diff --git a/bsp/lpc5410x/drivers/drv_uart.c b/bsp/lpc5410x/drivers/drv_uart.c index d348921740..826e659eb4 100644 --- a/bsp/lpc5410x/drivers/drv_uart.c +++ b/bsp/lpc5410x/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc5410x/drivers/drv_uart.h b/bsp/lpc5410x/drivers/drv_uart.h index 4ff948e746..6fa6e193d8 100644 --- a/bsp/lpc5410x/drivers/drv_uart.h +++ b/bsp/lpc5410x/drivers/drv_uart.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef __DRV_UART_H_ #define __DRV_UART_H_ diff --git a/bsp/lpc5410x/rtconfig.h b/bsp/lpc5410x/rtconfig.h index 387f1e75e6..c45f7094f6 100644 --- a/bsp/lpc5410x/rtconfig.h +++ b/bsp/lpc5410x/rtconfig.h @@ -5,17 +5,17 @@ // // -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 //
#define RT_DEBUG #define RT_DEBUG_COLOR @@ -30,11 +30,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_TICK_PER_SECOND 10 //
//
@@ -75,7 +75,7 @@ //
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 //
// @@ -87,7 +87,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -102,18 +102,18 @@ // // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 4 +#define DFS_FD_MAX 4 // #define RT_USING_DFS_ELMFAT // // 1 // 2 // -#define RT_DFS_ELM_USE_LFN 1 +#define RT_DFS_ELM_USE_LFN 1 // -#define RT_DFS_ELM_MAX_LFN 64 +#define RT_DFS_ELM_MAX_LFN 64 // // #define RT_USING_DFS_YAFFS2 // @@ -123,7 +123,7 @@ // // #define RT_USING_DFS_NFS // -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" //
//
@@ -139,29 +139,29 @@ // #define RT_LWIP_DNS // -#define RT_LWIP_PBUF_NUM 4 +#define RT_LWIP_PBUF_NUM 4 // -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_LWIP_TCP_PCB_NUM 3 // -#define RT_LWIP_TCP_SND_BUF 2048 +#define RT_LWIP_TCP_SND_BUF 2048 // -#define RT_LWIP_TCP_WND 2048 +#define RT_LWIP_TCP_WND 2048 // // #define RT_LWIP_SNMP // // #define RT_LWIP_DHCP // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // #define RT_LWIP_IPADDR0 192 #define RT_LWIP_IPADDR1 168 @@ -182,7 +182,7 @@ //
// #define RT_USING_RTGUI // -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 // #define RTGUI_USING_SMALL_SIZE // @@ -192,7 +192,7 @@ // #define RTGUI_USING_FONTHZ // -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 // // #define RTGUI_USING_DFS_FILERW // diff --git a/bsp/lpc54114-lite/applications/main.c b/bsp/lpc54114-lite/applications/main.c index 5c13ff5166..f3490dd40b 100644 --- a/bsp/lpc54114-lite/applications/main.c +++ b/bsp/lpc54114-lite/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,9 +14,9 @@ int main(void) { - /* user app entry */ + /* user app entry */ rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); - + while (1) { rt_pin_write(LED4_PIN, !rt_pin_read(LED4_PIN)); diff --git a/bsp/lpc54114-lite/applications/mnt.c b/bsp/lpc54114-lite/applications/mnt.c index 7942e159ed..49852b2025 100644 --- a/bsp/lpc54114-lite/applications/mnt.c +++ b/bsp/lpc54114-lite/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,15 +24,15 @@ int mnt_init(void) { rt_kprintf("spi flash mount '%s' failed.\n", BSP_FLASH_MOUNT_PATH); } -#endif - +#endif + #if defined(BSP_USING_SDCARD) if(dfs_mount("sd0", BSP_SDCARD_MOUNT_PATH, "elm", 0, 0) != 0) { rt_kprintf("sdcard mount '%s' failed.\n", BSP_SDCARD_MOUNT_PATH); } -#endif +#endif return 0; } -INIT_APP_EXPORT(mnt_init); +INIT_APP_EXPORT(mnt_init); diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.c b/bsp/lpc54114-lite/drivers/audio/drv_mic.c index d8219b504d..37bab8e125 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_mic.c +++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -160,4 +160,4 @@ int rt_hw_mic_init(void) return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_mic_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_mic_init); diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.h b/bsp/lpc54114-lite/drivers/audio/drv_mic.h index 1ce777d87d..7364999df5 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_mic.h +++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.c b/bsp/lpc54114-lite/drivers/audio/drv_sound.c index b6cf0ca2f0..409403facb 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_sound.c +++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -358,4 +358,4 @@ int rt_hw_sound_init(void) rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_sound_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_sound_init); diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.h b/bsp/lpc54114-lite/drivers/audio/drv_sound.h index aa997983ae..b50fe66593 100644 --- a/bsp/lpc54114-lite/drivers/audio/drv_sound.h +++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54114-lite/drivers/board.c b/bsp/lpc54114-lite/drivers/board.c index 61652d1c78..f8dc23a34b 100644 --- a/bsp/lpc54114-lite/drivers/board.c +++ b/bsp/lpc54114-lite/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,15 +57,15 @@ void rt_hw_board_init() SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); /* set pend exception priority */ NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); - + #ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif #ifdef RT_USING_COMPONENTS_INIT /* initialization board with RT-Thread Components */ rt_components_board_init(); -#endif -#ifdef RT_USING_CONSOLE +#endif +#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif } diff --git a/bsp/lpc54114-lite/drivers/board.h b/bsp/lpc54114-lite/drivers/board.h index 78c6d7c8c3..4e07415919 100644 --- a/bsp/lpc54114-lite/drivers/board.h +++ b/bsp/lpc54114-lite/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.c b/bsp/lpc54114-lite/drivers/drv_gpio.c index 978fa2898e..9b8b4d5da4 100644 --- a/bsp/lpc54114-lite/drivers/drv_gpio.c +++ b/bsp/lpc54114-lite/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, }; static rt_base_t lpc_pin_get(const char *name) @@ -85,46 +85,46 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { int portx, piny, dir; uint32_t pin_cfg; - + if(pin > PIN_MAX_VAL) return; - + portx = get_port(pin); - piny = get_pin(pin); - + piny = get_pin(pin); + switch(mode) { - case PIN_MODE_OUTPUT: + case PIN_MODE_OUTPUT: dir = kGPIO_DigitalOutput; pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN; break; case PIN_MODE_OUTPUT_OD: - dir = kGPIO_DigitalOutput; - pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN; + dir = kGPIO_DigitalOutput; + pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN; break; - - case PIN_MODE_INPUT: + + case PIN_MODE_INPUT: dir = kGPIO_DigitalInput; pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN; - break; + break; case PIN_MODE_INPUT_PULLUP: - dir = kGPIO_DigitalInput; + dir = kGPIO_DigitalInput; pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP; break; - case PIN_MODE_INPUT_PULLDOWN: + case PIN_MODE_INPUT_PULLDOWN: dir = kGPIO_DigitalInput; - pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN; break; default: break; - } - - CLOCK_EnableClock(kCLOCK_Iocon); - - IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); - GPIO_PortInit(GPIO, portx); - + } + + CLOCK_EnableClock(kCLOCK_Iocon); + + IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); + GPIO_PortInit(GPIO, portx); + gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0}; - GPIO_PinInit(GPIO, portx, piny, &pin_config); + GPIO_PinInit(GPIO, portx, piny, &pin_config); CLOCK_DisableClock(kCLOCK_Iocon); } @@ -133,27 +133,27 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { int portx, piny; portx = get_port(pin); - piny = get_pin(pin); + piny = get_pin(pin); if(pin > PIN_MAX_VAL) return; - GPIO_PinWrite(GPIO, portx, piny, value); + GPIO_PinWrite(GPIO, portx, piny, value); } static int lpc_pin_read(rt_device_t dev, rt_base_t pin) { - int portx, piny, value; - + int portx, piny, value; + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + portx = get_port(pin); - piny = get_pin(pin); - + piny = get_pin(pin); + value = (int)(GPIO_PinRead(GPIO, portx, piny)); - - return value; + + return value; } static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) @@ -166,10 +166,10 @@ static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) break; } } - + if(irqno >= IRQ_MAX_VAL) return; - + if (pin_irq_hdr_tab[irqno].hdr) { pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); @@ -184,14 +184,14 @@ void callback(pint_pin_int_t pintr, uint32_t pmatch_status) static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { - int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i; - + int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i; + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + portx = get_port(pin); - piny = get_pin(pin); - + piny = get_pin(pin); + switch (mode) { case PIN_IRQ_MODE_RISING: @@ -210,10 +210,10 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, trigger_mode = kPINT_PinIntEnableLowLevel; break; } - - /* Get inputmux_connection_t */ + + /* Get inputmux_connection_t */ pintsel = (pin + (0xC0U << 20)); - + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == -1) @@ -226,40 +226,40 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, break; } } - + if(i >= IRQ_MAX_VAL) return RT_ERROR; - + /* open clk */ CLOCK_EnableClock(kCLOCK_InputMux); CLOCK_EnableClock(kCLOCK_Iocon); - - /* AttachSignal */ + + /* AttachSignal */ INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel); pin_cfg = ((IOCON->PIO[portx][piny] & (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */ | IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */ | IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */ | IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */ - - IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); - + + IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); + /* PINT_PinInterruptConfig */ - PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); - + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); + CLOCK_DisableClock(kCLOCK_InputMux); CLOCK_DisableClock(kCLOCK_Iocon); - + return RT_EOK; } static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { - int i; - + int i; + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == pin) @@ -270,18 +270,18 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) pin_irq_hdr_tab[i].args = RT_NULL; break; } - } + } return RT_EOK; } static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) -{ +{ int irqn_type, i; - + if(pin > PIN_MAX_VAL) - return RT_ERROR; - + return RT_ERROR; + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == pin) @@ -315,8 +315,8 @@ static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, } break; } - } - + } + if(i >= IRQ_MAX_VAL) return RT_ERROR; diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.h b/bsp/lpc54114-lite/drivers/drv_gpio.h index 0c98e82298..41e4c45724 100644 --- a/bsp/lpc54114-lite/drivers/drv_gpio.h +++ b/bsp/lpc54114-lite/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,4 +13,4 @@ extern int rt_hw_pin_init(void); -#endif +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.c b/bsp/lpc54114-lite/drivers/drv_i2c.c index 81be945067..cba87c8aec 100644 --- a/bsp/lpc54114-lite/drivers/drv_i2c.c +++ b/bsp/lpc54114-lite/drivers/drv_i2c.c @@ -1,21 +1,21 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#include "drv_i2c.h" -#include "fsl_common.h" +#include "drv_i2c.h" + +#include "fsl_common.h" #include "fsl_iocon.h" #include "fsl_i2c.h" struct lpc_i2c { - struct rt_i2c_bus_device bus; - + struct rt_i2c_bus_device bus; + I2C_Type *base; - + char *device_name; }; @@ -28,9 +28,9 @@ static uint32_t get_i2c_freq(I2C_Type *base) { freq = CLOCK_GetFreq(kCLOCK_Flexcomm4); } -#endif +#endif - return freq; + return freq; } static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) @@ -43,7 +43,7 @@ static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg ms i2c_direction_t direction; status_t result = kStatus_Success; - RT_ASSERT(bus != RT_NULL); + RT_ASSERT(bus != RT_NULL); lpc_i2c = (struct lpc_i2c *)bus; @@ -94,13 +94,13 @@ static rt_err_t i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd, static const struct rt_i2c_bus_device_ops ops = { - master_xfer, + master_xfer, slave_xfer, i2c_bus_control, -}; +}; #if defined(BSP_USING_I2C4) -static struct lpc_i2c i2c4 = {0}; +static struct lpc_i2c i2c4 = {0}; #endif int rt_hw_i2c_init(void) @@ -110,11 +110,11 @@ int rt_hw_i2c_init(void) #if defined(BSP_USING_I2C4) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn); - + i2c4.base = I2C4; - i2c4.device_name = "i2c4"; - i2c4.bus.ops = &ops; - + i2c4.device_name = "i2c4"; + i2c4.bus.ops = &ops; + IOCON_PinMuxSet(IOCON, 1, 1, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); IOCON_PinMuxSet(IOCON, 1, 2, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); @@ -122,12 +122,12 @@ int rt_hw_i2c_init(void) I2C_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate_Bps = 100*1000U; - + I2C_MasterInit(I2C4, &masterConfig, get_i2c_freq(I2C4)); rt_i2c_bus_device_register(&i2c4.bus, i2c4.device_name); #endif - return RT_EOK; + return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_i2c_init); +INIT_BOARD_EXPORT(rt_hw_i2c_init); diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.h b/bsp/lpc54114-lite/drivers/drv_i2c.h index 468ac3c0dc..c5073237a8 100644 --- a/bsp/lpc54114-lite/drivers/drv_i2c.h +++ b/bsp/lpc54114-lite/drivers/drv_i2c.h @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_I2C_H__ -#define __DRV_I2C_H__ -#include -#include +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include int rt_hw_i2c_init(void); diff --git a/bsp/lpc54114-lite/drivers/drv_romfs.c b/bsp/lpc54114-lite/drivers/drv_romfs.c index 7c444af03f..d488b163fc 100644 --- a/bsp/lpc54114-lite/drivers/drv_romfs.c +++ b/bsp/lpc54114-lite/drivers/drv_romfs.c @@ -2,49 +2,49 @@ #include #include -static const rt_uint8_t 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{ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_flash__keep, sizeof(_romfs_root_mnt_flash__keep) / sizeof(_romfs_root_mnt_flash__keep[0])} }; -static const rt_uint8_t _romfs_root_mnt_sd__keep[] = +static const rt_uint8_t _romfs_root_mnt_sd__keep[] = { 0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a }; -static const struct romfs_dirent _romfs_root_mnt_sd[] = +static const struct romfs_dirent _romfs_root_mnt_sd[] = { {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_sd__keep, sizeof(_romfs_root_mnt_sd__keep) / sizeof(_romfs_root_mnt_sd__keep[0])} }; -static const rt_uint8_t _romfs_root_mnt_tmp__keep[] = +static const rt_uint8_t _romfs_root_mnt_tmp__keep[] = { 0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a }; -static const struct romfs_dirent _romfs_root_mnt_tmp[] = +static const struct romfs_dirent _romfs_root_mnt_tmp[] = { {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_tmp__keep, sizeof(_romfs_root_mnt_tmp__keep) / sizeof(_romfs_root_mnt_tmp__keep[0])} }; -static const struct romfs_dirent _romfs_root_mnt[] = +static const struct romfs_dirent _romfs_root_mnt[] = { {ROMFS_DIRENT_DIR, "flash", (rt_uint8_t *)_romfs_root_mnt_flash, sizeof(_romfs_root_mnt_flash) / sizeof(_romfs_root_mnt_flash[0])}, {ROMFS_DIRENT_DIR, "sd", (rt_uint8_t *)_romfs_root_mnt_sd, sizeof(_romfs_root_mnt_sd) / sizeof(_romfs_root_mnt_sd[0])}, {ROMFS_DIRENT_DIR, "tmp", (rt_uint8_t *)_romfs_root_mnt_tmp, sizeof(_romfs_root_mnt_tmp) / sizeof(_romfs_root_mnt_tmp[0])} }; -static const struct romfs_dirent _romfs_root[] = +static const struct romfs_dirent _romfs_root[] = { {ROMFS_DIRENT_FILE, "license", (rt_uint8_t *)_romfs_root_license, sizeof(_romfs_root_license) / sizeof(_romfs_root_license[0])}, {ROMFS_DIRENT_DIR, "mnt", (rt_uint8_t *)_romfs_root_mnt, sizeof(_romfs_root_mnt) / sizeof(_romfs_root_mnt[0])} diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.c b/bsp/lpc54114-lite/drivers/drv_sdcard.c index 3ef5081aa7..7ca47a1932 100644 --- a/bsp/lpc54114-lite/drivers/drv_sdcard.c +++ b/bsp/lpc54114-lite/drivers/drv_sdcard.c @@ -1,27 +1,27 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - + #include "drv_sdcard.h" -#include "drv_spi.h" +#include "drv_spi.h" #include "spi_msd.h" #define RT_SDCARD_CS_PIN (3) int rt_hw_sdcard_init(void) { - rt_err_t ret; - - ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN); - if(ret != RT_EOK) + rt_err_t ret; + + ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN); + if(ret != RT_EOK) { - return ret; + return ret; } - + ret = msd_init("sd0", "spi21"); - return ret; + return ret; } -INIT_DEVICE_EXPORT(rt_hw_sdcard_init); +INIT_DEVICE_EXPORT(rt_hw_sdcard_init); diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.h b/bsp/lpc54114-lite/drivers/drv_sdcard.h index 1ba77cf2b2..a225433b15 100644 --- a/bsp/lpc54114-lite/drivers/drv_sdcard.h +++ b/bsp/lpc54114-lite/drivers/drv_sdcard.h @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_SDCARD_H__ -#define __DRV_SDCARD_H__ -#include -#include +#ifndef __DRV_SDCARD_H__ +#define __DRV_SDCARD_H__ + +#include +#include int rt_hw_sdcard_init(void); diff --git a/bsp/lpc54114-lite/drivers/drv_spi.c b/bsp/lpc54114-lite/drivers/drv_spi.c index 0843e0baab..c83aaf03ee 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi.c +++ b/bsp/lpc54114-lite/drivers/drv_spi.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ #include "drv_spi.h" -#include "fsl_common.h" +#include "fsl_common.h" #include "fsl_iocon.h" #include "fsl_spi.h" @@ -25,23 +25,23 @@ static uint32_t get_spi_freq(SPI_Type *base) { freq = CLOCK_GetFreq(kCLOCK_Flexcomm2); } -#endif +#endif - return freq; + return freq; } static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) { spi_master_config_t masterConfig = {0}; - RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(cfg != RT_NULL); if(cfg->data_width != 8 && cfg->data_width != 16) { - return (-RT_EINVAL); + return (-RT_EINVAL); } - SPI_MasterGetDefaultConfig(&masterConfig); + SPI_MasterGetDefaultConfig(&masterConfig); if(cfg->max_hz > 12*1000*1000) { @@ -51,124 +51,124 @@ static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) if(cfg->data_width == 8) { - masterConfig.dataWidth = kSPI_Data8Bits; + masterConfig.dataWidth = kSPI_Data8Bits; } else if(cfg->data_width == 16) { - masterConfig.dataWidth = kSPI_Data16Bits; + masterConfig.dataWidth = kSPI_Data16Bits; } if(cfg->mode & RT_SPI_MSB) { - masterConfig.direction = kSPI_MsbFirst; + masterConfig.direction = kSPI_MsbFirst; } else { - masterConfig.direction = kSPI_LsbFirst; + masterConfig.direction = kSPI_LsbFirst; } if(cfg->mode & RT_SPI_CPHA) { - masterConfig.phase = kSPI_ClockPhaseSecondEdge; + masterConfig.phase = kSPI_ClockPhaseSecondEdge; } else { - masterConfig.phase = kSPI_ClockPhaseFirstEdge; + masterConfig.phase = kSPI_ClockPhaseFirstEdge; } if(cfg->mode & RT_SPI_CPOL) { - masterConfig.polarity = kSPI_ClockPolarityActiveLow; + masterConfig.polarity = kSPI_ClockPolarityActiveLow; } else { - masterConfig.polarity = kSPI_ClockPolarityActiveHigh; + masterConfig.polarity = kSPI_ClockPolarityActiveHigh; } - masterConfig.txWatermark = kSPI_TxFifo0, - masterConfig.rxWatermark = kSPI_RxFifo1, - - // masterConfig.sselNum = kSPI_Ssel3; - SPI_MasterInit(base, &masterConfig, get_spi_freq(base)); + masterConfig.txWatermark = kSPI_TxFifo0, + masterConfig.rxWatermark = kSPI_RxFifo1, - return RT_EOK; + // masterConfig.sselNum = kSPI_Ssel3; + SPI_MasterInit(base, &masterConfig, get_spi_freq(base)); + + return RT_EOK; } rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) { - rt_err_t ret = RT_EOK; - - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - - struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); - + cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, PIN_HIGH); - - ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); - - return ret; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; } static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { - rt_err_t ret = RT_EOK; - struct lpc_spi *spi = RT_NULL; - + rt_err_t ret = RT_EOK; + struct lpc_spi *spi = RT_NULL; + RT_ASSERT(cfg != RT_NULL); RT_ASSERT(device != RT_NULL); - - spi = (struct lpc_spi *)(device->bus->parent.user_data); - spi->cfg = cfg; - ret = spi_init(spi->base, cfg); - + + spi = (struct lpc_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = spi_init(spi->base, cfg); + return ret; } static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { - spi_transfer_t transfer = {0}; - + spi_transfer_t transfer = {0}; + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - - struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); - struct lpc_sw_spi_cs *cs = device->parent.user_data; - + + struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); + struct lpc_sw_spi_cs *cs = device->parent.user_data; + if(message->cs_take) { rt_pin_write(cs->pin, PIN_LOW); } - - transfer.dataSize = message->length; - transfer.rxData = (uint8_t *)(message->recv_buf); - transfer.txData = (uint8_t *)(message->send_buf); + + transfer.dataSize = message->length; + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); transfer.configFlags |= kSPI_FrameAssert; - - SPI_MasterTransferBlocking(spi->base, &transfer); - + + SPI_MasterTransferBlocking(spi->base, &transfer); + if(message->cs_release) { rt_pin_write(cs->pin, PIN_HIGH); } - - return message->length; + + return message->length; } #if defined(BSP_USING_SPI2) -static struct lpc_spi spi2 = {0}; -static struct rt_spi_bus spi2_bus = {0}; +static struct lpc_spi spi2 = {0}; +static struct rt_spi_bus spi2_bus = {0}; #endif -static struct rt_spi_ops lpc_spi_ops = +static struct rt_spi_ops lpc_spi_ops = { - configure, + configure, spixfer -}; +}; int rt_hw_spi_init(void) { @@ -178,17 +178,17 @@ int rt_hw_spi_init(void) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); - spi2.base = SPI2; - spi2.cfg = RT_NULL; - spi2_bus.parent.user_data = &spi2; - + spi2.base = SPI2; + spi2.cfg = RT_NULL; + spi2_bus.parent.user_data = &spi2; + IOCON_PinMuxSet(IOCON, 0, 8, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MOSI */ IOCON_PinMuxSet(IOCON, 0, 9, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MISO */ IOCON_PinMuxSet(IOCON, 0, 10, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_SCK */ - rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); + rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); #endif - return RT_EOK; + return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_spi_init); +INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/lpc54114-lite/drivers/drv_spi.h b/bsp/lpc54114-lite/drivers/drv_spi.h index c269cb9892..2938716aa4 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi.h +++ b/bsp/lpc54114-lite/drivers/drv_spi.h @@ -1,21 +1,21 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_SPI_H__ -#define __DRV_SPI_H__ -#include -#include +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include struct lpc_sw_spi_cs { rt_uint32_t pin; -}; +}; int rt_hw_spi_init(void); -rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); #endif diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.c b/bsp/lpc54114-lite/drivers/drv_spi_flash.c index 65433ce30c..11098636f9 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi_flash.c +++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#include "drv_spi.h" + +#include "drv_spi.h" #include "drv_spi_flash.h" -#include "rtthread.h" -#include "rtdevice.h" +#include "rtthread.h" +#include "rtdevice.h" #include "spi_flash.h" #include "spi_flash_sfud.h" @@ -16,19 +16,19 @@ int rt_hw_flash_init(void) { - rt_err_t result; - - result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN); - if(result != RT_EOK) + rt_err_t result; + + result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN); + if(result != RT_EOK) { - return result; + return result; } - - if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL) + + if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL) { return RT_ERROR; } - return RT_EOK; + return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_flash_init); +INIT_DEVICE_EXPORT(rt_hw_flash_init); diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.h b/bsp/lpc54114-lite/drivers/drv_spi_flash.h index f3c71e06c2..50b941449e 100644 --- a/bsp/lpc54114-lite/drivers/drv_spi_flash.h +++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,6 @@ #ifndef __DRV_SPI_FLASH_H_ #define __DRV_SPI_FLASH_H_ -int rt_hw_w25qxx_init(void); +int rt_hw_w25qxx_init(void); #endif diff --git a/bsp/lpc54114-lite/drivers/drv_uart.c b/bsp/lpc54114-lite/drivers/drv_uart.c index fc0999d4a4..0ccce7632c 100644 --- a/bsp/lpc54114-lite/drivers/drv_uart.c +++ b/bsp/lpc54114-lite/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -42,14 +42,14 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con * config.enableRx = false; */ USART_GetDefaultConfig(&u0_config); - - u0_config.baudRate_Bps = cfg->baud_rate; + + u0_config.baudRate_Bps = cfg->baud_rate; u0_config.parityMode = kUSART_ParityDisabled, u0_config.stopBitCount = kUSART_OneStopBit, u0_config.bitCountPerChar = kUSART_8BitsPerChar, u0_config.loopback = false, u0_config.txWatermark = kUSART_TxFifo0, - u0_config.rxWatermark = kUSART_RxFifo1, + u0_config.rxWatermark = kUSART_RxFifo1, u0_config.enableTx = true; u0_config.enableRx = true; @@ -143,7 +143,7 @@ int rt_hw_uart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef BSP_USING_UART0 - + uart = &uart0; serial0.ops = &lpc_uart_ops; @@ -152,40 +152,40 @@ int rt_hw_uart_init(void) /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); - + /* reset FLEXCOMM for USART */ RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); - + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ CLOCK_EnableClock(kCLOCK_Iocon); - + const uint32_t port0_pin0_config = ((IOCON->PIO[PORT0_IDX][PIN0_IDX] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(1) /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */ - | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ - - IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN0_IDX, port0_pin0_config); /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */ - - const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(1) /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(1) /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */ | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ - + + IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN0_IDX, port0_pin0_config); /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */ + + const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(1) /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */ + | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ + IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN1_IDX, port0_pin1_config); /* PORT0 PIN1 (coords: 32) is configured as FC0_TXD_SCL_MISO */ - + /* Enable RX interrupt. */ USART_EnableInterrupts(uart->UART, kUSART_RxLevelInterruptEnable | kUSART_RxErrorInterruptEnable); EnableIRQ(uart->UART_IRQn); - - CLOCK_DisableClock(kCLOCK_Iocon); - + + CLOCK_DisableClock(kCLOCK_Iocon); + /* register UART0 device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); -#endif - +#endif + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/lpc54114-lite/drivers/drv_uart.h b/bsp/lpc54114-lite/drivers/drv_uart.h index e066448d24..1bef2e50a6 100644 --- a/bsp/lpc54114-lite/drivers/drv_uart.h +++ b/bsp/lpc54114-lite/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,4 +13,4 @@ extern int rt_hw_uart_init(void); -#endif +#endif diff --git a/bsp/lpc54608-LPCXpresso/applications/application.c b/bsp/lpc54608-LPCXpresso/applications/application.c index b85de95df6..bfb039472d 100644 --- a/bsp/lpc54608-LPCXpresso/applications/application.c +++ b/bsp/lpc54608-LPCXpresso/applications/application.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -47,10 +47,10 @@ void link_dump(void) extern unsigned int _sbss; extern unsigned int _ebss; - + #define DUMP_VAR(__VAR) \ rt_kprintf("%-20s %p\n", #__VAR, &__VAR) - + DUMP_VAR(_sdata); DUMP_VAR(_edata); DUMP_VAR(_sidata); @@ -62,10 +62,10 @@ void link_dump(void) int rt_application_init(void) { rt_thread_t tid; - + build_dump(); link_dump(); - + tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048, RT_THREAD_PRIORITY_MAX / 3, 20); diff --git a/bsp/lpc54608-LPCXpresso/applications/mnt.c b/bsp/lpc54608-LPCXpresso/applications/mnt.c index dd1f862ea5..4a865340d9 100644 --- a/bsp/lpc54608-LPCXpresso/applications/mnt.c +++ b/bsp/lpc54608-LPCXpresso/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ int mnt_init(void) dfs_romfs_init(); /* mount rom file system */ - if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0) + if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0) { rt_kprintf("ROM file system initializated!\n"); } @@ -44,14 +44,14 @@ int mnt_init(void) mci_hw_init("sd0"); #endif -#ifdef RT_DFS_ELM_REENTRANT +#ifdef RT_DFS_ELM_REENTRANT /* mount sd card fat partition 1 as root directory */ if (dfs_mount("sd0", SD_ROOT, "elm", 0, 0) == 0) rt_kprintf("File System initialized!\n"); else rt_kprintf("File System init failed!\n"); #endif - + return 0; } INIT_ENV_EXPORT(mnt_init); diff --git a/bsp/lpc54608-LPCXpresso/applications/startup.c b/bsp/lpc54608-LPCXpresso/applications/startup.c index 687cc0f864..fcd836cdac 100644 --- a/bsp/lpc54608-LPCXpresso/applications/startup.c +++ b/bsp/lpc54608-LPCXpresso/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -39,10 +39,10 @@ void rtthread_startup(void) /* initialize scheduler system */ rt_system_scheduler_init(); - + /* initialize system timer*/ rt_system_timer_init(); - + /* initialize application */ rt_application_init(); diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.c b/bsp/lpc54608-LPCXpresso/drivers/board.c index 51c72ec3f5..decd9adfa3 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/board.c +++ b/bsp/lpc54608-LPCXpresso/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ void rt_hw_board_init() { /* Hardware Initialization */ CLOCK_EnableClock(kCLOCK_InputMux); - CLOCK_EnableClock(kCLOCK_Iocon); + CLOCK_EnableClock(kCLOCK_Iocon); /* NVIC Configuration */ #define NVIC_VTOR_MASK 0x3FFFFF80 @@ -54,15 +54,15 @@ void rt_hw_board_init() #endif BOARD_BootClockFROHF48M(); - /* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/ + /* init systick 1 systick = 1/(100M / 100) 100个systick = 1s*/ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); /* set pend exception priority */ NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /*init uart device*/ rt_hw_uart_init(); - -#ifdef RT_USING_CONSOLE + +#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.h b/bsp/lpc54608-LPCXpresso/drivers/board.h index 679f33682f..db2ac831c5 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/board.h +++ b/bsp/lpc54608-LPCXpresso/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c index c6c5d114e4..7e220327cb 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,9 +26,9 @@ int rt_hw_mpu_init(void) { uint32_t rbar; uint32_t rasr; - + MPU_PRINT("\nnumber of regions: %d\n", (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos); - + /* Disable MPU */ ARM_MPU_Disable(); diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h index ff34c225e7..782f6fce08 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c index b432aea70e..394ad22cca 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -73,14 +73,14 @@ struct lpc_emac /* inherit from ethernet device */ struct eth_device parent; struct rt_semaphore tx_wait; - + ENET_Type *base; enet_handle_t handle; - + /* interface address info. */ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ uint32_t phyAddr; - + uint8_t RxBuffDescrip[ENET_RXBD_NUM * sizeof(enet_rx_bd_struct_t) + ENET_BUFF_ALIGNMENT]; uint8_t TxBuffDescrip[ENET_TXBD_NUM * sizeof(enet_tx_bd_struct_t) + ENET_BUFF_ALIGNMENT]; uint8_t RxDataBuff[ENET_RXBD_NUM * ENET_ALIGN(ENET_RXBUFF_SIZE) + ENET_BUFF_ALIGNMENT]; @@ -273,7 +273,7 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex) { bool link = false; int32_t status; - + RT_ASSERT(speed != NULL); RT_ASSERT(duplex != NULL); @@ -284,9 +284,9 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex) *duplex = kPHY_HalfDuplex; /* 10M speed. */ *speed = kPHY_Speed10M; - + eth_device_linkchange(&lpc_emac_device.parent, RT_FALSE); - + ETH_PRINTF("PHY_Init failed!\n"); return RT_ERROR; } @@ -305,7 +305,7 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex) } PHY_GetLinkSpeedDuplex(lpc_emac_device.base, lpc_emac_device.phyAddr, speed, duplex); - + eth_device_linkchange(&lpc_emac_device.parent, RT_TRUE); return RT_EOK; @@ -338,19 +338,19 @@ static rt_err_t lpc_emac_init(rt_device_t dev) buffCfg.rxDescTailAddrAlign = get_rx_desc(ENET_RXBD_NUM); buffCfg.rxBufferStartAddr = rxBufferStartAddr; buffCfg.rxBuffSizeAlign = ENET_ALIGN(ENET_RXBUFF_SIZE); - + /* Get default configuration 100M RMII. */ ENET_GetDefaultConfig(&config); /* Use the actual speed and duplex when phy success to finish the autonegotiation. */ config.miiSpeed = (enet_mii_speed_t)speed; config.miiDuplex = (enet_mii_duplex_t)duplex; - + ETH_PRINTF("Auto negotiation, Speed: "); if (config.miiSpeed == kENET_MiiSpeed100M) ETH_PRINTF("100M"); else ETH_PRINTF("10M"); - + ETH_PRINTF(", Duplex: "); if (config.miiSpeed == kENET_MiiSpeed100M) ETH_PRINTF("Full\n"); @@ -363,10 +363,10 @@ static rt_err_t lpc_emac_init(rt_device_t dev) /* Enable the tx/rx interrupt. */ ENET_EnableInterrupts(lpc_emac_device.base, (kENET_DmaTx | kENET_DmaRx)); ENET_CreateHandler(lpc_emac_device.base, &lpc_emac_device.handle, &config, &buffCfg, ethernet_callback, NULL); - + /* Initialize Descriptor. */ ENET_DescriptorInit(lpc_emac_device.base, &config, &buffCfg); - + /* Active TX/RX. */ ENET_StartRxTx(lpc_emac_device.base, 1, 1); @@ -416,23 +416,23 @@ static rt_err_t lpc_emac_control(rt_device_t dev, int cmd, void *args) /* transmit packet. */ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p) { - rt_err_t result = RT_EOK; - enet_handle_t * enet_handle = &lpc_emac_device.handle; + rt_err_t result = RT_EOK; + enet_handle_t * enet_handle = &lpc_emac_device.handle; ENET_Type *enet_base = lpc_emac_device.base; uint8_t * data; - - uint16_t len; - RT_ASSERT(p != NULL); + uint16_t len; + + RT_ASSERT(p != NULL); RT_ASSERT(enet_handle != RT_NULL); if (p->tot_len > ENET_TXBUFF_SIZE) { return RT_ERROR; } - + packet_dump("TX dump", p); - + /* get free tx buffer */ { rt_err_t result; @@ -442,18 +442,18 @@ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p) return RT_ERROR; } } - - // fix RxDataBuff -> TxDataBuff, ENET_RXBUFF_SIZE -> ENET_TXBUFF_SIZE + + // fix RxDataBuff -> TxDataBuff, ENET_RXBUFF_SIZE -> ENET_TXBUFF_SIZE data = (uint8_t *)ENET_ALIGN(&lpc_emac_device.TxDataBuff[lpc_emac_device.txIdx * ENET_ALIGN(ENET_TXBUFF_SIZE)]); len = pbuf_copy_partial(p, data, p->tot_len, 0); lpc_emac_device.txIdx = (lpc_emac_device.txIdx + 1) / ENET_TXBD_NUM; - - // fix 'p->len' to 'len', avoid send wrong partial packet. + + // fix 'p->len' to 'len', avoid send wrong partial packet. result = ENET_SendFrame(enet_base, enet_handle, data, len); - + if ((result == kStatus_ENET_TxFrameFail) || (result == kStatus_ENET_TxFrameOverLen) || (result == kStatus_ENET_TxFrameBusy)) { - return RT_ERROR; + return RT_ERROR; } return RT_EOK; @@ -462,22 +462,22 @@ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p) /* reception packet. */ struct pbuf *lpc_emac_rx(rt_device_t dev) { - uint32_t length = 0; - status_t status; - - struct pbuf* p = RT_NULL; - enet_handle_t * enet_handle = &lpc_emac_device.handle; - ENET_Type *enet_base = lpc_emac_device.base; - - /* Get the Frame size */ - status = ENET_GetRxFrameSize(enet_base, enet_handle, &length, 0); + uint32_t length = 0; + status_t status; + + struct pbuf* p = RT_NULL; + enet_handle_t * enet_handle = &lpc_emac_device.handle; + ENET_Type *enet_base = lpc_emac_device.base; + + /* Get the Frame size */ + status = ENET_GetRxFrameSize(enet_base, enet_handle, &length, 0); + + /* Call ENET_ReadFrame when there is a received frame. */ + if (length != 0) + { + /* Received valid frame. Deliver the rx buffer with the size equal to length. */ + p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); - /* Call ENET_ReadFrame when there is a received frame. */ - if (length != 0) - { - /* Received valid frame. Deliver the rx buffer with the size equal to length. */ - p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); - if (p != NULL) { status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length, 0); @@ -496,12 +496,12 @@ struct pbuf *lpc_emac_rx(rt_device_t dev) { ETH_PRINTF(" pbuf_alloc faild\n"); } - } - else if (status == kStatus_ENET_RxFrameError) - { - ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); - ENET_ReadFrame(enet_base, enet_handle, NULL, 0, 0); - } + } + else if (status == kStatus_ENET_RxFrameError) + { + ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); + ENET_ReadFrame(enet_base, enet_handle, NULL, 0, 0); + } return NULL; } @@ -510,11 +510,11 @@ int lpc_emac_hw_init(void) { /* init tx semaphore */ rt_sem_init(&lpc_emac_device.tx_wait, "tx_wait", ENET_TXBD_NUM, RT_IPC_FLAG_FIFO); - + lpc_emac_device.phyAddr = 0; lpc_emac_device.txIdx = 0; lpc_emac_device.base = ENET; - + // OUI 00-60-37 NXP Semiconductors lpc_emac_device.dev_addr[0] = 0x00; lpc_emac_device.dev_addr[1] = 0x60; @@ -536,7 +536,7 @@ int lpc_emac_hw_init(void) lpc_emac_device.parent.eth_tx = lpc_emac_tx; eth_device_init(&(lpc_emac_device.parent), "e0"); - + return 0; } INIT_DEVICE_EXPORT(lpc_emac_hw_init); @@ -546,7 +546,7 @@ int emac_stat(void) { rt_kprintf("enter rx isr coutner : %d\n", isr_rx_counter); rt_kprintf("enter tx isr coutner : %d\n", isr_tx_counter); - + return 0; } #endif @@ -556,14 +556,14 @@ void phy_dump(void) status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); int i; - + for (i = 0; i < 31; i++) { status_t result = kStatus_Success; uint32_t reg; - + result = PHY_Read(lpc_emac_device.base, lpc_emac_device.phyAddr, i, ®); - + if (result == kStatus_Success) { rt_kprintf("%02d: %08d\n", i, reg); @@ -630,7 +630,7 @@ void emac_dump(void) DUMP_REG(DMA_SYSBUS_MODE); DUMP_REG(DMA_INTR_STAT); DUMP_REG(DMA_DBG_STAT); - + DUMP_REG(MTL_QUEUE[0].MTL_TXQX_OP_MODE); DUMP_REG(MTL_QUEUE[0].MTL_TXQX_UNDRFLW); DUMP_REG(MTL_QUEUE[0].MTL_TXQX_DBG); @@ -660,7 +660,7 @@ void emac_dump(void) DUMP_REG(MTL_QUEUE[1].MTL_RXQX_MISSPKT_OVRFLW_CNT); DUMP_REG(MTL_QUEUE[1].MTL_RXQX_DBG); DUMP_REG(MTL_QUEUE[1].MTL_RXQX_CTRL); - + DUMP_REG(DMA_CH[0].DMA_CHX_CTRL); DUMP_REG(DMA_CH[0].DMA_CHX_TX_CTRL); DUMP_REG(DMA_CH[0].DMA_CHX_RX_CTRL); @@ -678,7 +678,7 @@ void emac_dump(void) DUMP_REG(DMA_CH[0].DMA_CHX_CUR_HST_TXBUF); DUMP_REG(DMA_CH[0].DMA_CHX_CUR_HST_RXBUF); DUMP_REG(DMA_CH[0].DMA_CHX_STAT); - + DUMP_REG(DMA_CH[1].DMA_CHX_CTRL); DUMP_REG(DMA_CH[1].DMA_CHX_TX_CTRL); DUMP_REG(DMA_CH[1].DMA_CHX_RX_CTRL); @@ -701,23 +701,23 @@ void emac_dump(void) void emac_bd_dump(void) { int i; - + rt_kprintf("rx bd dump: \n"); for (i = 0; i < ENET_RXBD_NUM; i++) { enet_rx_bd_struct_t * rx_bd = get_rx_desc(i); - rt_kprintf("buf1: %p, buf2: %p, ctrl: %08x\n", - rx_bd->buff1Addr, + rt_kprintf("buf1: %p, buf2: %p, ctrl: %08x\n", + rx_bd->buff1Addr, rx_bd->buff2Addr, rx_bd->control); } - + rt_kprintf("tx bd dump: \n"); for (i = 0; i < ENET_TXBD_NUM; i++) { enet_tx_bd_struct_t * tx_bd = get_tx_desc(i); - rt_kprintf("buf1: %p, buf2: %p, len: %08x, ctrl: %08x\n", - tx_bd->buff1Addr, + rt_kprintf("buf1: %p, buf2: %p, len: %08x, ctrl: %08x\n", + tx_bd->buff1Addr, tx_bd->buff2Addr, tx_bd->buffLen, tx_bd->controlStat); diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h index efaa0ac8e3..cde6d2742e 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c index fd46a199c0..c87d2039f3 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-08 Yang the first version */ - + #include #include #include diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c index 39e08af2d3..1a6b5ff3b8 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-08 Yang the first version */ - + #include #include #include "board.h" diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c index c1a6660819..260fb09f0e 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-08 Yang the first version */ - + #include #include #include @@ -427,7 +427,7 @@ void rt_hw_lcd_init(void) _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH, 32); if (_rt_framebuffer == RT_NULL) return; /* no memory yet */ _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; // RTGRAPHIC_PIXEL_FORMAT_ARGB888 + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; // RTGRAPHIC_PIXEL_FORMAT_ARGB888 _lcd_info.framebuffer = (void *)_rt_framebuffer; _lcd_info.width = RT_HW_LCD_WIDTH; _lcd_info.height = RT_HW_LCD_HEIGHT; diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c index e1239b7899..f5efc2a9d7 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -394,22 +394,22 @@ rt_err_t mci_hw_init(const char *device_name) rt_kprintf("SD_Init failed!\n"); return -RT_ERROR; } - - /* - follow the page: https://community.nxp.com/thread/454769 - - The issue concerns sdmmc library bug (I finally solved) in SD_Init() in the file sdmmc/src/fsl_sd.c:SD_SelectBusTiming() - calls SD_SwitchFunction() which sets block size to 64bytes (512bits).Therefore SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE) - should be called again before SD_Init() exits. - */ - - if (kStatus_Success != SDMMC_SetBlockSize(_mci_device->card.host.base, _mci_device->card.host.transfer, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) - { + + /* + follow the page: https://community.nxp.com/thread/454769 + + The issue concerns sdmmc library bug (I finally solved) in SD_Init() in the file sdmmc/src/fsl_sd.c:SD_SelectBusTiming() + calls SD_SwitchFunction() which sets block size to 64bytes (512bits).Therefore SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE) + should be called again before SD_Init() exits. + */ + + if (kStatus_Success != SDMMC_SetBlockSize(_mci_device->card.host.base, _mci_device->card.host.transfer, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) + { SD_Deinit(&_mci_device->card); memset(&_mci_device->card, 0U, sizeof(_mci_device->card)); rt_kprintf("SD_Init failed!\n"); - return -RT_ERROR; - } + return -RT_ERROR; + } /* initialize mutex lock */ rt_mutex_init(&_mci_device->lock, device_name, RT_IPC_FLAG_FIFO); diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h index d36134eaa4..1fc53a7459 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -50,7 +50,7 @@ struct mci_device { struct rt_device parent; /**< RT-Thread device struct */ struct rt_device_blk_geometry geometry; /**< sector size, sector count */ - sd_card_t card; /**< Card descriptor */ + sd_card_t card; /**< Card descriptor */ rt_event_t finish_event; /**< data send finish event*/ rt_bool_t data_error; /**< data send error*/ struct rt_mutex lock; diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c index 9b6438c4d2..2270e7ed72 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2017-08-02 Yang the first version */ - + #include "drv_sdram.h" #include @@ -15,10 +15,10 @@ /******************************************************************************************* -* @º¯ÊýÃû£ºsdram_gpio_config() -* @²ÎÊý £ºvoid -* @·µ»ØÖµ£ºvoid -* @ÃèÊö £ºSDRAM¹Ü½ÅÅäÖú¯Êý£¬ÄÚ²¿µ÷Óà +* @函数å：sdram_gpio_config() +* @å‚æ•° ：void +* @返回值：void +* @æè¿° ：SDRAM管脚é…置函数，内部调用 *********************************************************************************************/ static void sdram_gpio_config(void) { diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h index 4de79410b0..1d9a9db4aa 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c index 81f4ba6e9c..4b27d23fa1 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h index 14c87054ff..7abc19420f 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c index 7c9bd9fc7f..ce9e48fdad 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c +++ b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -146,7 +146,7 @@ void rt_hw_uart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef RT_USING_UART0 - + uart = &uart0; serial0.ops = &lpc_uart_ops; @@ -188,5 +188,5 @@ void rt_hw_uart_init(void) rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, uart); -#endif +#endif } diff --git a/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c b/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c index 70fa7b3dc8..6a522d7ad7 100644 --- a/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c +++ b/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c @@ -87,7 +87,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) while ((idReg != PHY_CONTROL_ID1) && (delay != 0)) { PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); - delay --; + delay --; } if (!delay) @@ -224,7 +224,7 @@ status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) else { *status = false; - } + } } return result; } @@ -260,7 +260,7 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t * else { /* 10M speed. */ *speed = kPHY_Speed10M; - } + } } return result; } diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_adc.c b/bsp/lpc55sxx/Libraries/drivers/drv_adc.c index e1f79c2429..d7d29f0728 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_adc.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -34,7 +34,7 @@ static rt_err_t lpc_lpadc_convert(struct rt_adc_device *device, rt_uint32_t chan lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; lpadc_conv_command_config_t mLpadcCommandConfigStruct; lpadc_conv_result_t mLpadcResultConfigStruct; - + ADC_Type *base; base = (ADC_Type *)(device->parent.user_data); @@ -42,13 +42,13 @@ static rt_err_t lpc_lpadc_convert(struct rt_adc_device *device, rt_uint32_t chan LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); mLpadcCommandConfigStruct.channelNumber = channel; LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); - + /* Set trigger configuration. */ LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); mLpadcTriggerConfigStruct.targetCommandId = 1U; mLpadcTriggerConfigStruct.enableHardwareTrigger = false; LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U)); @@ -74,12 +74,12 @@ int rt_hw_adc_init(void) #if defined(BSP_USING_ADC0_CH0) lpadc_config_t mLpadcConfigStruct; - + CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true); CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); /* Disable LDOGPADC power down */ POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC); - + LPADC_GetDefaultConfig(&mLpadcConfigStruct); mLpadcConfigStruct.enableAnalogPreliminary = true; mLpadcConfigStruct.referenceVoltageSource = kLPADC_ReferenceVoltageAlt2; @@ -91,7 +91,7 @@ int rt_hw_adc_init(void) LPADC_SetOffsetValue(ADC0, 10U, 10U); /* Request gain calibration. */ LPADC_DoAutoCalibration(ADC0); - + result = rt_hw_adc_register(&adc0_device, "adc0", &lpc_adc_ops, ADC0); if (result != RT_EOK) diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_adc.h b/bsp/lpc55sxx/Libraries/drivers/drv_adc.h index 0113b54f3e..412b5f3cd2 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_adc.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c index bbaf2d6704..6014317b63 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,15 +31,15 @@ static void NVIC_Configuration(void) #ifdef BSP_USING_CTIMER1 EnableIRQ(CTIMER1_IRQn); #endif - + #ifdef BSP_USING_CTIMER2 EnableIRQ(CTIMER2_IRQn); #endif - + #ifdef BSP_USING_CTIMER3 EnableIRQ(CTIMER3_IRQn); #endif - + #ifdef BSP_USING_CTIMER4 EnableIRQ(CTIMER4_IRQn); #endif @@ -64,9 +64,9 @@ static rt_err_t lpc_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *a if(hwtimer_dev == CTIMER2) clk = CLOCK_GetFreq(kCLOCK_CTimer2); if(hwtimer_dev == CTIMER3) clk = CLOCK_GetFreq(kCLOCK_CTimer3); if(hwtimer_dev == CTIMER4) clk = CLOCK_GetFreq(kCLOCK_CTimer4); - + pre = clk / *((uint32_t *)args) - 1; - + hwtimer_dev->PR = pre; } break; @@ -97,16 +97,16 @@ static void lpc_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state) hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - + /* Use Main clock for some of the Ctimers */ if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0); if(hwtimer_dev == CTIMER1) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER1); if(hwtimer_dev == CTIMER2) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER2); if(hwtimer_dev == CTIMER3) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER3); if(hwtimer_dev == CTIMER4) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER4); - + CTIMER_Deinit(hwtimer_dev); - + if (state == 1) { NVIC_Configuration(); @@ -121,7 +121,7 @@ static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtime hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; /* Match Configuration for Channel 0 */ ctimer_match_config_t matchCfg; - + RT_ASSERT(timer != RT_NULL); /* Configuration*/ @@ -131,13 +131,13 @@ static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtime matchCfg.outControl = kCTIMER_Output_NoAction; matchCfg.outPinInitState = false; matchCfg.enableInterrupt = true; - + CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg); - + NVIC_Configuration(); CTIMER_StartTimer(hwtimer_dev); - + return RT_EOK; } @@ -213,7 +213,7 @@ int rt_hw_hwtimer_init(void) LOG_E("CTIMER1 register failed\n"); } #endif - + #ifdef BSP_USING_CTIMER2 CTimer2.info = &lpc_hwtimer_info; CTimer2.ops = &lpc_hwtimer_ops; @@ -224,7 +224,7 @@ int rt_hw_hwtimer_init(void) LOG_E("CTIMER2 register failed\n"); } #endif - + #ifdef BSP_USING_CTIMER3 CTimer3.info = &lpc_hwtimer_info; CTimer3.ops = &lpc_hwtimer_ops; @@ -235,7 +235,7 @@ int rt_hw_hwtimer_init(void) LOG_E("CTIMER3 register failed\n"); } #endif - + #ifdef BSP_USING_CTIMER4 CTimer4.info = &lpc_hwtimer_info; CTimer4.ops = &lpc_hwtimer_ops; @@ -246,7 +246,7 @@ int rt_hw_hwtimer_init(void) LOG_E("CTIMER4 register failed\n"); } #endif - + return ret; } diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h index 441665c6e8..04d64d79e4 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c index 45273f1552..53361bdd40 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-07-15 Magicoe The first version for LPC55S6x */ - + #include #include #include "board.h" @@ -86,7 +86,7 @@ out: } static const struct rt_i2c_bus_device_ops i2c_ops = -{ +{ lpc_i2c_xfer, RT_NULL, @@ -115,7 +115,7 @@ int rt_hw_i2c_init(void) lpc_i2c1.device_name = "LPC Flexcomm1 as I2C"; rt_i2c_bus_device_register(&lpc_i2c1.parent, "i2c1"); #endif /* BSP_USING_I2C1 */ - + #ifdef BSP_USING_I2C4 static struct lpc_i2c_bus lpc_i2c4; /* attach 12 MHz clock to FLEXCOMM2 (I2C master for touch controller) */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h index ac303c7367..87b576f30d 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,12 +8,12 @@ * 2018-03-15 Liuguang the first version. * 2019-07-19 Magicoe The first version for LPC55S6x */ - + #ifndef __DRV_RTC_H__ #define __DRV_RTC_H__ -#include -#include +#include +#include extern int rt_hw_i2c_init(void); diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_key.c b/bsp/lpc55sxx/Libraries/drivers/drv_key.c index 3f8188febe..930c2c706b 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_key.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_key.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -47,11 +47,11 @@ int my_button_register(struct my_button *button) { rt_pin_mode(button->pin, PIN_MODE_INPUT_PULLDOWN); } - + button->cnt = 0; button->event = BUTTON_EVENT_NONE; button_manage.button_list[button_manage.num++] = button; - + return 0; } @@ -100,7 +100,7 @@ static void my_button_scan(void *param) else if (cnt_old >= MY_BUTTON_HOLD_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_HOLD_UP */ { LOG_D("BUTTON_HOLD_UP"); - button_manage.button_list[i]->event = BUTTON_EVENT_HOLD_UP; + button_manage.button_list[i]->event = BUTTON_EVENT_HOLD_UP; MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i])); } } @@ -117,7 +117,7 @@ int my_button_start(void) my_button_scan, /* Timeout callback func */ RT_NULL, /* Timeout func entry */ RT_TICK_PER_SECOND * MY_BUTTON_SCAN_SPACE_MS / 1000, - RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); /* Start Timer */ if (button_manage.timer != RT_NULL) rt_timer_start(button_manage.timer); @@ -159,7 +159,7 @@ void key_test(rt_uint32_t led_num, rt_uint32_t value) key.pin = KEY_PIN; my_button_register(&key); - + my_button_start(); } MSH_CMD_EXPORT(key_test, key_test); diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_key.h b/bsp/lpc55sxx/Libraries/drivers/drv_key.h index b0fb9d4095..f8a65370f0 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_key.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_key.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,12 +7,12 @@ * Date Author Notes * 2019-07-19 Magicoe The first version for LPC55S6x, refered github.com/Guozhanxin/RTT-BeepPlayer-pkg */ - + #ifndef __DRV_KEY_H__ #define __DRV_KEY_H__ -#include -#include +#include +#include #define MY_BUTTON_DOWN_MS 50 #define MY_BUTTON_HOLD_MS 700 diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_led.c b/bsp/lpc55sxx/Libraries/drivers/drv_led.c index d7c5a32ef7..922982f654 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_led.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_led.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_led.h b/bsp/lpc55sxx/Libraries/drivers/drv_led.h index de45db9063..65f55668b6 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_led.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_led.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,12 +7,12 @@ * Date Author Notes * 2019-07-19 Magicoe The first version for LPC55S6x */ - + #ifndef __DRV_LED_H__ #define __DRV_LED_H__ -#include -#include +#include +#include int rt_hw_led_init(void); diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_log.h b/bsp/lpc55sxx/Libraries/drivers/drv_log.h index 7e0bfee5b4..3fe511789b 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_log.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c index e009c86842..80b3b2671b 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ rt_err_t mma8562_read_reg(rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf) struct rt_i2c_msg msgs[2]; msgs[0].addr = kMMA8562_ADDR; - msgs[0].flags = RT_I2C_WR; + msgs[0].flags = RT_I2C_WR; msgs[0].buf = ® msgs[0].len = 1; @@ -60,7 +60,7 @@ rt_err_t mma8562_write_reg(rt_uint8_t reg, rt_uint8_t data) buf[0] = reg; buf[1] = data; - + if (rt_i2c_master_send(mma8562_i2c_bus, kMMA8562_ADDR, 0, buf ,2) == 2) { return RT_EOK; @@ -78,15 +78,15 @@ rt_err_t mma8562_write_reg(rt_uint8_t reg, rt_uint8_t data) void get_mma8562(uint8_t data) { volatile acceleration_t accel; - + uint8_t ucVal1 = 0; uint8_t ucVal2 = 0; uint8_t ucStatus = 0; - + do { mma8562_read_reg(kMMA8562_STATUS, 1, &ucStatus); } while (!(ucStatus & 0x08)); - + mma8562_read_reg(kMMA8562_OUT_X_MSB, 1, &ucVal1); mma8562_read_reg(kMMA8562_OUT_X_LSB, 1, &ucVal2); @@ -150,7 +150,7 @@ int mma8562_hw_init(void) /* databyte = 0x0D; */ val = 0x0D; mma8562_write_reg(kMMA8562_CTRL_REG1, val); - + return 0; } diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pin.c b/bsp/lpc55sxx/Libraries/drivers/drv_pin.c index 48d26a5825..d38a7ead9a 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_pin.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pin.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -83,8 +83,8 @@ static struct lpc_pin lpc_pin_map[] = __LPC55S69_PIN(30, GPIO, 0, 29), /* PIO0_29 */ __LPC55S69_PIN(31, GPIO, 0, 30), /* PIO0_30 */ __LPC55S69_PIN(32, GPIO, 0, 31), /* PIO0_31 */ - - + + /* PIO1 / GPIO, 1 */ __LPC55S69_PIN(33, GPIO, 1, 0), /* PIO1_00 */ __LPC55S69_PIN(34, GPIO, 1, 1), /* PIO1_01 */ @@ -129,7 +129,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, }; static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) @@ -179,15 +179,15 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) } break; } - + /* Enable IOCON Clock */ CLOCK_EnableClock(kCLOCK_Iocon); - IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] = pin_cfg; + IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] = pin_cfg; /* Disable IOCON Clock -- To Save Power */ CLOCK_DisableClock(kCLOCK_Iocon); - + gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 1}; - GPIO_PinInit(GPIO, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, &pin_config); + GPIO_PinInit(GPIO, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, &pin_config); } @@ -197,20 +197,20 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { return; } - + GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value); } static int lpc_pin_read(rt_device_t dev, rt_base_t pin) { - int value; + int value; if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) { return RT_ERROR; } value = GPIO_PinRead(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin); - + return value; } @@ -225,10 +225,10 @@ static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) break; } } - + if(irqno >= IRQ_MAX_VAL) return; - + if (pin_irq_hdr_tab[irqno].hdr) { pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); @@ -250,7 +250,7 @@ void PIN_INT0_IRQHandler(void) pmstatus = PINT_PatternMatchResetDetectLogic(PINT); pin_irq_hdr(kPINT_PinInt0, pmstatus); - + if ((PINT->ISEL & 0x1U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ @@ -264,8 +264,8 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, void (*hdr)(void *args), void *args) { - int trigger_mode, pin_initx, pintsel, pin_cfg, i; - + int trigger_mode, pin_initx, pintsel, pin_cfg, i; + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) { return RT_ERROR; @@ -289,10 +289,10 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, trigger_mode = kPINT_PinIntEnableLowLevel; break; } - - /* Get inputmux_connection_t */ + + /* Get inputmux_connection_t */ pintsel = (pin - 1 + (0xC0U << 20)); - + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == -1) @@ -308,43 +308,43 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, if(i >= IRQ_MAX_VAL) return RT_ERROR; - + /* Initialize PINT */ PINT_Init(PINT); - + /* Enable Input and IOCon clk */ - /* AttachSignal */ + /* AttachSignal */ /* Connect trigger sources to PINT */ INPUTMUX_Init(INPUTMUX); INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel); /* Turnoff clock to inputmux to save power. Clock is only needed to make changes */ INPUTMUX_Deinit(INPUTMUX); - + pin_cfg = ((IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] & (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */ | IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */ | IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */ | IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */ - - IOCON_PinMuxSet(IOCON, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, pin_cfg); - + + IOCON_PinMuxSet(IOCON, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, pin_cfg); + /* PINT_PinInterruptConfig */ - PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); /* Enable callbacks for PINTx by Index */ PINT_EnableCallbackByIndex(PINT, (pint_pin_int_t)pin_initx); - + return RT_EOK; } static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { - int i; + int i; if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) { return RT_ERROR; } - + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == pin) @@ -355,19 +355,19 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) pin_irq_hdr_tab[i].args = RT_NULL; break; } - } + } return RT_EOK; } static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { int irqn_type, i; - + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) { return RT_ERROR; } - + for(i = 0; i < IRQ_MAX_VAL; i++) { if(pin_irq_hdr_tab[i].pin == pin) @@ -401,8 +401,8 @@ static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u } break; } - } - + } + if(i >= IRQ_MAX_VAL) return RT_ERROR; diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pin.h b/bsp/lpc55sxx/Libraries/drivers/drv_pin.h index 0c69698e67..21ebf56051 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_pin.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pin.h @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-03-13 Liuguang the first version. + * 2018-03-13 Liuguang the first version. * 2018-03-19 Liuguang add GPIO interrupt mode support. * 2019-07-15 Magicoe The first version for LPC55S6x */ - + #ifndef __DRV_PIN_H__ #define __DRV_PIN_H__ -#include +#include #include #define GET_PINS(PORTx, PINx) (32 * PORTx + PINx + 1) /* PORTx:0,1, PINx:0,1...31 */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c index 64d6cfd00a..e2fa7f05b6 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ static struct rt_pwm_ops lpc_drv_ops = static rt_err_t lpc_drv_pwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) { CTIMER_Type *base; - + base = (CTIMER_Type *)device->parent.user_data; if (!enable) @@ -63,14 +63,14 @@ static rt_err_t lpc_drv_pwm_get(struct rt_device_pwm *device, struct rt_pwm_conf uint32_t get_frequence; uint32_t pwmClock = 0; CTIMER_Type *base; - + base = (CTIMER_Type *)device->parent.user_data; - + #ifdef BSP_USING_CTIMER2 /* get frequence */ pwmClock = CLOCK_GetFreq(kCLOCK_CTimer2) ; #endif - + get_frequence = pwmClock / (base->MR[kCTIMER_Match_3] + 1); if(configuration->channel == 1) @@ -85,7 +85,7 @@ static rt_err_t lpc_drv_pwm_get(struct rt_device_pwm *device, struct rt_pwm_conf configuration->pulse = get_duty * configuration->period / 100; rt_kprintf("*** PWM period %d, pulse %d\r\n", configuration->period, configuration->pulse); - + return RT_EOK; } @@ -97,7 +97,7 @@ static rt_err_t lpc_drv_pwm_set(struct rt_device_pwm *device, struct rt_pwm_conf ctimer_config_t config; CTIMER_Type *base; base = (CTIMER_Type *)device->parent.user_data; - + uint32_t pwmPeriod, pulsePeriod; /* Run as a timer */ config.mode = kCTIMER_TimerMode; @@ -105,7 +105,7 @@ static rt_err_t lpc_drv_pwm_set(struct rt_device_pwm *device, struct rt_pwm_conf config.input = kCTIMER_Capture_0; /* Timer counter is incremented on every APB bus clock */ config.prescale = 0; - + if(configuration->channel == 1) { /* Get the PWM period match value and pulse width match value of DEFAULT_FREQ PWM signal with DEFAULT_DUTY dutycycle */ @@ -159,17 +159,17 @@ int rt_hw_pwm_init(void) static struct rt_device_pwm pwm1_device; ctimer_config_t config; uint32_t pwmPeriod, pulsePeriod; - + /* Use 12 MHz clock for some of the Ctimers */ CLOCK_AttachClk(kMAIN_CLK_to_CTIMER2); - + /* Run as a timer */ config.mode = kCTIMER_TimerMode; /* This field is ignored when mode is timer */ config.input = kCTIMER_Capture_0; /* Timer counter is incremented on every APB bus clock */ config.prescale = 0; - + CTIMER_Init(CTIMER2, &config); #ifdef BSP_USING_CTIMER2_MAT1 @@ -243,7 +243,7 @@ static int pwm_get(int argc, char **argv) result = -RT_EIO; goto _exit; } - + result = rt_pwm_get(device, atoi(argv[2])); _exit: diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h index 7260c0c587..47e50a435b 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c index c277d82079..fc49389566 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,12 +8,12 @@ * 2018-03-15 Liuguang the first version. * 2019-07-19 Magicoe The first version for LPC55S6x */ - + #include #include #include -#include "drv_rtc.h" -#include "fsl_common.h" +#include "drv_rtc.h" +#include "fsl_common.h" #include "fsl_rtc.h" #ifdef RT_USING_RTC @@ -22,21 +22,21 @@ #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif -static time_t get_timestamp(void) +static time_t get_timestamp(void) { - struct tm tm_new = {0}; - rtc_datetime_t rtcDate; - + struct tm tm_new = {0}; + rtc_datetime_t rtcDate; + /* Get date time */ RTC_GetDatetime(RTC, &rtcDate); - - tm_new.tm_sec = rtcDate.second; - tm_new.tm_min = rtcDate.minute; + + tm_new.tm_sec = rtcDate.second; + tm_new.tm_min = rtcDate.minute; tm_new.tm_hour = rtcDate.hour; - - tm_new.tm_mday = rtcDate.day; - tm_new.tm_mon = rtcDate.month - 1; - tm_new.tm_year = rtcDate.year - 1900; + + tm_new.tm_mday = rtcDate.day; + tm_new.tm_mon = rtcDate.month - 1; + tm_new.tm_year = rtcDate.year - 1900; return timegm(&tm_new); } @@ -44,27 +44,27 @@ static time_t get_timestamp(void) static int set_timestamp(time_t timestamp) { struct tm *p_tm; - rtc_datetime_t rtcDate; - - p_tm = gmtime(×tamp); - - rtcDate.second = p_tm->tm_sec ; - rtcDate.minute = p_tm->tm_min ; - rtcDate.hour = p_tm->tm_hour; + rtc_datetime_t rtcDate; + + p_tm = gmtime(×tamp); + + rtcDate.second = p_tm->tm_sec ; + rtcDate.minute = p_tm->tm_min ; + rtcDate.hour = p_tm->tm_hour; + + rtcDate.day = p_tm->tm_mday; + rtcDate.month = p_tm->tm_mon + 1; + rtcDate.year = p_tm->tm_year + 1900; - rtcDate.day = p_tm->tm_mday; - rtcDate.month = p_tm->tm_mon + 1; - rtcDate.year = p_tm->tm_year + 1900; - /* RTC time counter has to be stopped before setting the date & time in the TSR register */ RTC_StopTimer(RTC); - + /* Set RTC time to default */ RTC_SetDatetime(RTC, &rtcDate); /* Start the RTC time counter */ RTC_StartTimer(RTC); - + return RT_EOK; } @@ -72,83 +72,83 @@ static rt_err_t lpc_rtc_init(rt_device_t dev) { /* Init RTC */ RTC_Init(RTC); - + /* Start the RTC time counter */ RTC_StartTimer(RTC); - - return RT_EOK; + + return RT_EOK; } static rt_err_t lpc_rtc_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } -static rt_err_t lpc_rtc_close(rt_device_t dev) +static rt_err_t lpc_rtc_close(rt_device_t dev) { - return RT_EOK; -} + return RT_EOK; +} static rt_size_t lpc_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - return 0; + return 0; } static rt_size_t lpc_rtc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - return 0; + return 0; } static rt_err_t lpc_rtc_control(rt_device_t dev, int cmd, void *args) { RT_ASSERT(dev != RT_NULL); - + switch(cmd) { - case RT_DEVICE_CTRL_RTC_GET_TIME: + case RT_DEVICE_CTRL_RTC_GET_TIME: { - *(uint32_t *)args = get_timestamp(); + *(uint32_t *)args = get_timestamp(); } break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: + + case RT_DEVICE_CTRL_RTC_SET_TIME: { - set_timestamp(*(time_t *)args); + set_timestamp(*(time_t *)args); } break; - + default: - return RT_EINVAL; + return RT_EINVAL; } - - return RT_EOK; + + return RT_EOK; } -static struct rt_device device = +static struct rt_device device = { - .type = RT_Device_Class_RTC, - .init = lpc_rtc_init, - .open = lpc_rtc_open, - .close = lpc_rtc_close, + .type = RT_Device_Class_RTC, + .init = lpc_rtc_init, + .open = lpc_rtc_open, + .close = lpc_rtc_close, .read = lpc_rtc_read, .write = lpc_rtc_write, - .control = lpc_rtc_control, + .control = lpc_rtc_control, }; int rt_hw_rtc_init(void) { rt_err_t ret = RT_EOK; - - ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); + + ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); if(ret != RT_EOK) { - return ret; + return ret; } - - rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); - - return RT_EOK; + + rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); + + return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_rtc_init); +INIT_DEVICE_EXPORT(rt_hw_rtc_init); #endif /*RT_USING_RTC */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h index a0623308ad..a905b177ae 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,12 +8,12 @@ * 2018-03-15 Liuguang the first version. * 2019-07-19 Magicoe The first version for LPC55S6x */ - + #ifndef __DRV_RTC_H__ #define __DRV_RTC_H__ -#include -#include +#include +#include int rt_hw_rtc_init(void); diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_sd.c b/bsp/lpc55sxx/Libraries/drivers/drv_sd.c index 66385a7056..597e49aa7b 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_sd.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_sd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include #include -#include "fsl_common.h" +#include "fsl_common.h" #include "fsl_iocon.h" #include "fsl_sdif.h" @@ -177,14 +177,14 @@ int rt_hw_mci_init(void) return -RT_ERROR; } rt_memset(_mci_device, 0, sizeof(struct mci_device)); - + /* attach main clock to SDIF */ CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK); /* need call this function to clear the halt bit in clock divider register */ CLOCK_SetClkDiv(kCLOCK_DivSdioClk, (uint32_t)(SystemCoreClock / FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK + 1U), true); _mci_device->card = g_sd; - + /* Save host information. */ _mci_device->card.host.base = SDIF; _mci_device->card.host.sourceClock_Hz = CLOCK_GetFreq(kCLOCK_SDio); @@ -202,14 +202,14 @@ int rt_hw_mci_init(void) /* power off card */ SD_PowerOffCard(_mci_device->card.host.base, _mci_device->card.usrParam.pwr); - + /* check SD card insert */ if(BOARD_SDIF_CD_STATUS() == true) { rt_kprintf("\r\nCard detect fail.\r\n"); return kStatus_Fail; } - + /* wait card insert */ if (SD_WaitCardDetectStatus(_mci_device->card.host.base, &s_sdCardDetect, true) == kStatus_Success) { @@ -223,7 +223,7 @@ int rt_hw_mci_init(void) rt_kprintf("\r\nCard detect fail.\r\n"); return kStatus_Fail; } - + /* Init card. */ if (SD_CardInit(&_mci_device->card)) { diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_sd.h b/bsp/lpc55sxx/Libraries/drivers/drv_sd.h index 125f2b9a47..e604787c16 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_sd.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_sd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,7 +18,7 @@ struct mci_device { struct rt_device parent; /**< RT-Thread device struct */ struct rt_device_blk_geometry geometry; /**< sector size, sector count */ - sd_card_t card; /**< Card descriptor */ + sd_card_t card; /**< Card descriptor */ rt_event_t finish_event; /**< data send finish event*/ rt_bool_t data_error; /**< data send error*/ struct rt_mutex lock; diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_spi.c b/bsp/lpc55sxx/Libraries/drivers/drv_spi.c index 53c4c3730f..332b20ac5e 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_spi.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,7 +9,7 @@ */ #include "drv_spi.h" -#include "fsl_common.h" +#include "fsl_common.h" #include "fsl_iocon.h" #include "fsl_spi.h" @@ -23,7 +23,7 @@ defined(BSP_USING_SPIBUS6) || \ defined(BSP_USING_SPIBUS7) || \ defined(BSP_USING_SPIBUS8) - + #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #endif @@ -44,14 +44,14 @@ struct lpc_sw_spi_cs static uint32_t lpc_get_spi_freq(SPI_Type *base) { uint32_t freq = 0; - + #if defined(BSP_USING_SPIBUS0) if(base == SPI0) { freq = CLOCK_GetFreq(kCLOCK_Flexcomm0); } -#endif - +#endif + #if defined(BSP_USING_SPIBUS1) if(base == SPI1) { @@ -72,7 +72,7 @@ static uint32_t lpc_get_spi_freq(SPI_Type *base) freq = CLOCK_GetFreq(kCLOCK_Flexcomm3); } #endif - + #if defined(BSP_USING_SPIBUS4) if(base == SPI4) { @@ -116,15 +116,15 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) { spi_master_config_t masterConfig = {0}; - RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(cfg != RT_NULL); if(cfg->data_width != 8 && cfg->data_width != 16) { - return (-RT_EINVAL); + return (-RT_EINVAL); } - - SPI_MasterGetDefaultConfig(&masterConfig); + + SPI_MasterGetDefaultConfig(&masterConfig); #if defined(BSP_USING_SPIBUS8) if(base == SPI8) @@ -140,81 +140,81 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) cfg->max_hz = 12*1000*1000; } #endif - + masterConfig.baudRate_Bps = cfg->max_hz; if(cfg->data_width == 8) { - masterConfig.dataWidth = kSPI_Data8Bits; + masterConfig.dataWidth = kSPI_Data8Bits; } else if(cfg->data_width == 16) { - masterConfig.dataWidth = kSPI_Data16Bits; + masterConfig.dataWidth = kSPI_Data16Bits; } if(cfg->mode & RT_SPI_MSB) { - masterConfig.direction = kSPI_MsbFirst; + masterConfig.direction = kSPI_MsbFirst; } else { - masterConfig.direction = kSPI_LsbFirst; + masterConfig.direction = kSPI_LsbFirst; } if(cfg->mode & RT_SPI_CPHA) { - masterConfig.phase = kSPI_ClockPhaseSecondEdge; + masterConfig.phase = kSPI_ClockPhaseSecondEdge; } else { - masterConfig.phase = kSPI_ClockPhaseFirstEdge; + masterConfig.phase = kSPI_ClockPhaseFirstEdge; } if(cfg->mode & RT_SPI_CPOL) { - masterConfig.polarity = kSPI_ClockPolarityActiveLow; + masterConfig.polarity = kSPI_ClockPolarityActiveLow; } else { - masterConfig.polarity = kSPI_ClockPolarityActiveHigh; + masterConfig.polarity = kSPI_ClockPolarityActiveHigh; } - SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base)); + SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base)); - return RT_EOK; + return RT_EOK; } rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) { - rt_err_t ret = RT_EOK; - - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - - struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); - + cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, PIN_HIGH); - - ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); - - return ret; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; } static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { - rt_err_t ret = RT_EOK; - struct lpc_spi *spi = RT_NULL; - + rt_err_t ret = RT_EOK; + struct lpc_spi *spi = RT_NULL; + RT_ASSERT(cfg != RT_NULL); RT_ASSERT(device != RT_NULL); - - spi = (struct lpc_spi *)(device->bus->parent.user_data); - spi->cfg = cfg; - ret = lpc_spi_init(spi->base, cfg); - + + spi = (struct lpc_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = lpc_spi_init(spi->base, cfg); + return ret; } @@ -222,23 +222,23 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { uint32_t length; - + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); - - struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); - struct lpc_sw_spi_cs *cs = device->parent.user_data; - + + struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); + struct lpc_sw_spi_cs *cs = device->parent.user_data; + if(message->cs_take) { rt_pin_write(cs->pin, PIN_LOW); } - + length = message->length; - const rt_uint8_t *txData = (uint8_t *)(message->send_buf); - rt_uint8_t *rxData = (uint8_t *)(message->recv_buf); - + const rt_uint8_t *txData = (uint8_t *)(message->send_buf); + rt_uint8_t *rxData = (uint8_t *)(message->recv_buf); + rt_kprintf("*** spi send %d\r\n", length); while (length) @@ -257,181 +257,181 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * } txData += SPISTEP(spi->cfg->data_width);; length--; - } - + } + if(message->cs_release) { rt_pin_write(cs->pin, PIN_HIGH); } - - return (message->length - length); + + return (message->length - length); } #if defined(BSP_USING_SPIBUS0) -static struct lpc_spi spi0 = +static struct lpc_spi spi0 = { .base = SPI0 -}; -static struct rt_spi_bus spi0_bus = +}; +static struct rt_spi_bus spi0_bus = { .parent.user_data = &spi0 -}; +}; #endif #if defined(BSP_USING_SPIBUS1) -static struct lpc_spi spi1 = +static struct lpc_spi spi1 = { .base = SPI1 -}; -static struct rt_spi_bus spi1_bus = +}; +static struct rt_spi_bus spi1_bus = { .parent.user_data = &spi1 -}; +}; #endif #if defined(BSP_USING_SPIBUS2) -static struct lpc_spi spi2 = +static struct lpc_spi spi2 = { .base = SPI2 -}; -static struct rt_spi_bus spi2_bus = +}; +static struct rt_spi_bus spi2_bus = { .parent.user_data = &spi2 -}; +}; #endif #if defined(BSP_USING_SPIBUS3) -static struct lpc_spi spi3 = +static struct lpc_spi spi3 = { .base = SPI3 -}; -static struct rt_spi_bus spi3_bus = +}; +static struct rt_spi_bus spi3_bus = { .parent.user_data = &spi3 -}; +}; #endif #if defined(BSP_USING_SPIBUS4) -static struct lpc_spi spi4 = +static struct lpc_spi spi4 = { .base = SPI4 -}; -static struct rt_spi_bus spi4_bus = +}; +static struct rt_spi_bus spi4_bus = { .parent.user_data = &spi4 -}; +}; #endif #if defined(BSP_USING_SPIBUS5) -static struct lpc_spi spi5 = +static struct lpc_spi spi5 = { .base = SPI5 -}; -static struct rt_spi_bus spi5_bus = +}; +static struct rt_spi_bus spi5_bus = { .parent.user_data = &spi5 -}; +}; #endif #if defined(BSP_USING_SPIBUS6) -static struct lpc_spi spi6 = +static struct lpc_spi spi6 = { .base = SPI6 -}; -static struct rt_spi_bus spi6_bus = +}; +static struct rt_spi_bus spi6_bus = { .parent.user_data = &spi6 -}; +}; #endif #if defined(BSP_USING_SPIBUS7) -static struct lpc_spi spi7 = +static struct lpc_spi spi7 = { .base = SPI7 -}; -static struct rt_spi_bus spi7_bus = +}; +static struct rt_spi_bus spi7_bus = { .parent.user_data = &spi7 -}; +}; #endif #if defined(BSP_USING_SPIBUS8) -static struct lpc_spi spi8 = +static struct lpc_spi spi8 = { .base = SPI8 -}; -static struct rt_spi_bus spi8_bus = +}; +static struct rt_spi_bus spi8_bus = { .parent.user_data = &spi8 -}; +}; #endif -static struct rt_spi_ops lpc_spi_ops = +static struct rt_spi_ops lpc_spi_ops = { - .configure = spi_configure, + .configure = spi_configure, .xfer = spixfer -}; +}; int rt_hw_spi_init(void) { #if defined(BSP_USING_SPIBUS0) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); - spi0.cfg = RT_NULL; - rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops); + spi0.cfg = RT_NULL; + rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops); #endif #if defined(BSP_USING_SPIBUS1) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn); - spi1.cfg = RT_NULL; - rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops); + spi1.cfg = RT_NULL; + rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops); #endif #if defined(BSP_USING_SPIBUS2) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); - spi2.cfg = RT_NULL; - rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); + spi2.cfg = RT_NULL; + rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); #endif #if defined(BSP_USING_SPIBUS3) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3); RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn); - spi3.cfg = RT_NULL; - rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops); + spi3.cfg = RT_NULL; + rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops); #endif #if defined(BSP_USING_SPIBUS4) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn); - spi4.cfg = RT_NULL; - rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops); + spi4.cfg = RT_NULL; + rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops); #endif - + #if defined(BSP_USING_SPIBUS5) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5); RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn); - spi5.cfg = RT_NULL; - rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops); + spi5.cfg = RT_NULL; + rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops); #endif #if defined(BSP_USING_SPIBUS6) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6); RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn); - spi6.cfg = RT_NULL; - rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops); + spi6.cfg = RT_NULL; + rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops); #endif #if defined(BSP_USING_SPIBUS7) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7); RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn); - spi7.cfg = RT_NULL; - rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops); + spi7.cfg = RT_NULL; + rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops); #endif - + #if defined(BSP_USING_SPIBUS8) CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI); RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn); @@ -440,7 +440,7 @@ int rt_hw_spi_init(void) rt_spi_bus_register(&spi8_bus, "spi8", &lpc_spi_ops); #endif - return RT_EOK; + return RT_EOK; } INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_spi.h b/bsp/lpc55sxx/Libraries/drivers/drv_spi.h index 6aeb91256e..d361637c60 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_spi.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_spi.h @@ -1,16 +1,16 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 */ - -#ifndef __DRV_SPI_H__ -#define __DRV_SPI_H__ -#include -#include +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include int rt_hw_spi_init(void); -rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); #endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c index d9c325971f..c9bf72eb8d 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ struct lpc_uart USART_Type *uart_base; IRQn_Type irqn; clock_name_t clock_src; - + struct rt_serial_device *serial; char *device_name; }; @@ -133,7 +133,7 @@ static const struct lpc_uart uarts[] = USART0, FLEXCOMM0_IRQn, kCLOCK_Flexcomm0, - + &serial0, "uart", }, @@ -143,7 +143,7 @@ static const struct lpc_uart uarts[] = USART1, FLEXCOMM1_IRQn, kCLOCK_Flexcomm1, - + &serial1, "uart1", }, @@ -153,7 +153,7 @@ static const struct lpc_uart uarts[] = USART2, FLEXCOMM2_IRQn, kCLOCK_Flexcomm2, - + &serial2, "uart2", }, @@ -163,7 +163,7 @@ static const struct lpc_uart uarts[] = USART3, FLEXCOMM3_IRQn, kCLOCK_Flexcomm3, - + &serial3, "uart3", }, @@ -173,7 +173,7 @@ static const struct lpc_uart uarts[] = USART4, FLEXCOMM4_IRQn, kCLOCK_Flexcomm4, - + &serial4, "uart4", }, @@ -183,7 +183,7 @@ static const struct lpc_uart uarts[] = USART5, FLEXCOMM5_IRQn, kCLOCK_Flexcomm5, - + &serial5, "uart5", }, @@ -193,7 +193,7 @@ static const struct lpc_uart uarts[] = USART6, FLEXCOMM6_IRQn, kCLOCK_Flexcomm6, - + &serial6, "uart6", }, @@ -203,7 +203,7 @@ static const struct lpc_uart uarts[] = USART7, FLEXCOMM7_IRQn, kCLOCK_Flexcomm7, - + &serial7, "uart7", }, @@ -270,11 +270,11 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - + uart = (struct lpc_uart *)serial->parent.user_data; lpc_uart_gpio_init(uart); - + /* * config.baudRate_Bps = 115200U; * config.parityMode = kUSART_ParityDisabled; @@ -285,7 +285,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con */ USART_GetDefaultConfig(&config); config.baudRate_Bps = cfg->baud_rate; - + switch (cfg->data_bits) { case DATA_BITS_7: @@ -296,7 +296,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con config.bitCountPerChar = kUSART_8BitsPerChar; break; } - + switch (cfg->stop_bits) { case STOP_BITS_2: @@ -306,7 +306,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con config.stopBitCount = kUSART_OneStopBit; break; } - + switch (cfg->parity) { case PARITY_ODD: @@ -319,7 +319,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con config.parityMode = kUSART_ParityDisabled; break; } - + config.enableTx = true; config.enableRx = true; @@ -399,7 +399,7 @@ static void uart_isr(struct rt_serial_device *serial) /* UART in mode Receiver -------------------------------------------------*/ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -416,7 +416,7 @@ int rt_hw_uart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; int i; - + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { uarts[i].serial->ops = &lpc_uart_ops; diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.h b/bsp/lpc55sxx/Libraries/drivers/drv_uart.h index 603e2a248b..b0dffa8e70 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_uart.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c index 65150a42fb..095c3f0665 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ static wwdt_config_t WWDT1_config = /* No warning is provided */ .warningValue = 0, /* Set clock frequency. */ - .clockFreq_Hz = 0U, + .clockFreq_Hz = 0U, }; void WDT_BOD_IRQHandler(void) @@ -109,9 +109,9 @@ static rt_err_t lpc_wwdt_init(rt_watchdog_t *wdt) SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK; /* Set clock divider for WWDT clock source. */ CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, true); - + WWDT_GetDefaultConfig(&WWDT1_config); - + /* * Set watchdog feed time constant to approximately 4s * Set watchdog warning time to 512 ticks after feed time constant @@ -125,7 +125,7 @@ static rt_err_t lpc_wwdt_init(rt_watchdog_t *wdt) WWDT1_config.enableWatchdogReset = true; /* Setup watchdog clock frequency(Hz). */ WWDT1_config.clockFreq_Hz = CLOCK_GetFreq(kCLOCK_WdtClk); - + WWDT_Init(base, &WWDT1_config); lpc_wwdt_close(wdt); @@ -175,11 +175,11 @@ static rt_err_t lpc_wwdt_control(rt_watchdog_t *wdt, int cmd, void *args) case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: { RT_ASSERT(*(uint16_t *)args != 0); - + WWDT1_config.timeoutValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * (*(uint16_t *)args) * 2; WWDT1_config.warningValue = 512; WWDT1_config.windowValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * (*(uint16_t *)args) * 2 / 4; - + base->TC = WWDT_TC_COUNT(WWDT1_config.timeoutValue); base->WINDOW = WWDT_WINDOW_WINDOW(WWDT1_config.windowValue); base->WARNINT = WWDT_WARNINT_WARNINT(WWDT1_config.warningValue); diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h index 2517fb81d9..1b34934cf2 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h +++ b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c index e03a8c6336..ef4393ba39 100644 --- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ int main(void) #elif defined(__GNUC__) rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); #endif - + rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT); /* Set GPIO as Output */ while (1) { diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c index 4a7fb3f885..42a08bcb34 100644 --- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -41,15 +41,15 @@ void rt_hw_board_init() { /* Hardware Initialization */ BOARD_InitPins(); - + CLOCK_EnableClock(kCLOCK_InputMux); - + CLOCK_EnableClock(kCLOCK_Gpio0); CLOCK_EnableClock(kCLOCK_Gpio1); - + GPIO_PortInit(GPIO, 0); GPIO_PortInit(GPIO, 1); - + /* NVIC Configuration */ #define NVIC_VTOR_MASK 0x3FFFFF80 #ifdef VECT_TAB_RAM @@ -62,16 +62,16 @@ void rt_hw_board_init() BOARD_BootClockPLL150M(); //BOARD_BootClockFROHF96M(); - - /* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/ + + /* init systick 1 systick = 1/(100M / 100) 100个systick = 1s*/ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); /* set pend exception priority */ NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /*init uart device*/ rt_hw_uart_init(); - -#ifdef RT_USING_CONSOLE + +#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h index f2fce5c093..1899798c13 100644 --- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c index e0a2e3171f..64689741de 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c index b81bc8e616..0b71b508e7 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -43,15 +43,15 @@ void rt_hw_board_init() { /* Hardware Initialization */ BOARD_InitPins(); - + CLOCK_EnableClock(kCLOCK_InputMux); - + CLOCK_EnableClock(kCLOCK_Gpio0); CLOCK_EnableClock(kCLOCK_Gpio1); - + GPIO_PortInit(GPIO, 0); GPIO_PortInit(GPIO, 1); - + /* NVIC Configuration */ #define NVIC_VTOR_MASK 0x3FFFFF80 #ifdef VECT_TAB_RAM @@ -73,16 +73,16 @@ void rt_hw_board_init() BOARD_BootClockPLL150M(); #endif //BOARD_BootClockFROHF96M(); - - /* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/ + + /* init systick 1 systick = 1/(100M / 100) 100个systick = 1s*/ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); /* set pend exception priority */ NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /*init uart device*/ rt_hw_uart_init(); - -#ifdef RT_USING_CONSOLE + +#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h index 32afed7da3..d2deccda88 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc824/applications/application.c b/bsp/lpc824/applications/application.c index f8ef7f40e3..ed7972b4d2 100644 --- a/bsp/lpc824/applications/application.c +++ b/bsp/lpc824/applications/application.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-01-05 Bernard the first version - * 2014-04-27 Bernard make code cleanup. + * 2014-04-27 Bernard make code cleanup. */ #include @@ -29,26 +29,26 @@ static struct rt_thread led_thread; #endif void rt_init_thread_entry(void* parameter) -{ +{ /* initialization RT-Thread Components */ #ifdef RT_USING_COMPONENTS_INIT rt_components_init(); #endif - + } void rt_led_thread_entry(void *parameter) { /* Initialize GPIO */ - Chip_GPIO_Init(LPC_GPIO_PORT); + Chip_GPIO_Init(LPC_GPIO_PORT); Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, 7, 1); Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, true); - + while (1) { Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, true); rt_thread_delay(RT_TICK_PER_SECOND / 2); - + Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, false); rt_thread_delay(RT_TICK_PER_SECOND / 2); } @@ -64,7 +64,7 @@ int rt_application_init() INIT_STACK_SIZE, RT_THREAD_PRIORITY_MAX/3, 20); #else { - + rt_err_t result; tid = &init_thread; @@ -75,14 +75,14 @@ int rt_application_init() #endif if (tid != RT_NULL) rt_thread_startup(tid); - + #ifdef RT_USING_HEAP tid = rt_thread_create("led", rt_led_thread_entry, RT_NULL, LED_STACK_SIZE, RT_THREAD_PRIORITY_MAX/3, 20); #else { - + rt_err_t result; tid = &led_thread; diff --git a/bsp/lpc824/applications/startup.c b/bsp/lpc824/applications/startup.c index e165242f86..d25c76e723 100644 --- a/bsp/lpc824/applications/startup.c +++ b/bsp/lpc824/applications/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -58,7 +58,7 @@ void rtthread_startup(void) #ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif - + /* init scheduler system */ rt_system_scheduler_init(); diff --git a/bsp/lpc824/drivers/board.c b/bsp/lpc824/drivers/board.c index 51656718b8..0817a3b7e8 100644 --- a/bsp/lpc824/drivers/board.c +++ b/bsp/lpc824/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -62,7 +62,7 @@ void rt_hw_board_init() #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - + #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif diff --git a/bsp/lpc824/drivers/board.h b/bsp/lpc824/drivers/board.h index c8d21d94b5..d86369ce31 100644 --- a/bsp/lpc824/drivers/board.h +++ b/bsp/lpc824/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc824/drivers/usart.c b/bsp/lpc824/drivers/usart.c index 5109164a9a..54a56501c9 100644 --- a/bsp/lpc824/drivers/usart.c +++ b/bsp/lpc824/drivers/usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ struct lpc8xx_uart LPC_USART_T * uart_base; IRQn_Type uart_irq; rt_uint8_t rx_buffer[UART_RX_BUFSZ]; - + }; #ifdef RT_USING_UART0 struct lpc8xx_uart uart0_device; @@ -45,10 +45,10 @@ struct lpc8xx_uart uart2_device; void uart_irq_handler(struct lpc8xx_uart* uart) { uint32_t status; - + /* enter interrupt */ rt_interrupt_enter(); - + status = Chip_UART_GetStatus(uart->uart_base); if(status & UART_STAT_RXRDY) // RXIRQ { @@ -57,9 +57,9 @@ void uart_irq_handler(struct lpc8xx_uart* uart) if(uart->parent.rx_indicate != RT_NULL) { uart->parent.rx_indicate(&uart->parent, rt_ringbuffer_data_len(&uart->rx_rb)); - } + } } - + /* leave interrupt */ rt_interrupt_leave(); } @@ -88,15 +88,15 @@ void UART2_IRQHandler(void) static void uart1_io_init(LPC_USART_T * uart_base) { /* Enable the clock to the Switch Matrix */ - Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); - + Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); + Chip_Clock_SetUARTClockDiv(1); - + #ifdef RT_USING_UART0 if (uart_base == LPC_USART0) { - Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0); + Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4); + Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0); } else #endif @@ -104,8 +104,8 @@ static void uart1_io_init(LPC_USART_T * uart_base) #ifdef RT_USING_UART1 if (uart_base == LPC_USART1) { - Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0); + Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4); + Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0); } else #endif @@ -113,32 +113,32 @@ static void uart1_io_init(LPC_USART_T * uart_base) #ifdef RT_USING_UART2 if (uart_base == LPC_USART2) { - Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4); - Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0); + Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4); + Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0); } else #endif { RT_ASSERT((uart_base == USART0) || (uart_base == USART2) || (uart_base == USART2)); } - - /* Disable the clock to the Switch Matrix to save power */ - Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); + + /* Disable the clock to the Switch Matrix to save power */ + Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); } static void uart_ll_init(LPC_USART_T * uart) { Chip_UART_Init(uart); Chip_UART_ConfigData(uart, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1); - Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true); - Chip_UART_SetBaud(uart, 115200); - Chip_UART_Enable(uart); - Chip_UART_TXEnable(uart); - - // we must NOT enable TX ready/idle IRQ before we want to write data - // otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC - Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE); - Chip_UART_IntEnable(uart, UART_INTEN_RXRDY); + Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true); + Chip_UART_SetBaud(uart, 115200); + Chip_UART_Enable(uart); + Chip_UART_TXEnable(uart); + + // we must NOT enable TX ready/idle IRQ before we want to write data + // otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC + Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE); + Chip_UART_IntEnable(uart, UART_INTEN_RXRDY); } static rt_err_t rt_uart_init (rt_device_t dev) @@ -146,7 +146,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) struct lpc8xx_uart* uart; RT_ASSERT(dev != RT_NULL); uart = (struct lpc8xx_uart *)dev; - + uart1_io_init(uart->uart_base); uart_ll_init(uart->uart_base); @@ -220,11 +220,11 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer if (*ptr == '\n') { while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY)); - Chip_UART_SendByte(uart->uart_base, '\r'); + Chip_UART_SendByte(uart->uart_base, '\r'); } while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY)); - Chip_UART_SendByte(uart->uart_base, *ptr); + Chip_UART_SendByte(uart->uart_base, *ptr); ptr ++; size --; @@ -235,7 +235,7 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer while (size) { while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY)); - Chip_UART_SendByte(uart->uart_base, *ptr); + Chip_UART_SendByte(uart->uart_base, *ptr); ptr++; size--; @@ -258,14 +258,14 @@ int rt_hw_usart_init(void) uart->parent.type = RT_Device_Class_Char; uart->uart_base = LPC_USART0; uart->uart_irq = UART0_IRQn; - + rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; @@ -273,7 +273,7 @@ int rt_hw_usart_init(void) rt_device_register(&uart->parent, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); } #endif - + #ifdef RT_USING_UART1 { struct lpc8xx_uart* uart; @@ -285,14 +285,14 @@ int rt_hw_usart_init(void) uart->parent.type = RT_Device_Class_Char; uart->uart_base = LPC_USART1; uart->uart_irq = UART1_IRQn; - + rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; @@ -315,10 +315,10 @@ int rt_hw_usart_init(void) rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer)); /* device interface */ - uart->parent.init = rt_uart_init; - uart->parent.open = rt_uart_open; + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; uart->parent.close = rt_uart_close; - uart->parent.read = rt_uart_read; + uart->parent.read = rt_uart_read; uart->parent.write = rt_uart_write; uart->parent.control = RT_NULL; uart->parent.user_data = RT_NULL; diff --git a/bsp/lpc824/drivers/usart.h b/bsp/lpc824/drivers/usart.h index 1db28e9385..7298cdab8b 100644 --- a/bsp/lpc824/drivers/usart.h +++ b/bsp/lpc824/drivers/usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/lpc824/rtconfig.h b/bsp/lpc824/rtconfig.h index e8a551c2a3..d7c9608e28 100644 --- a/bsp/lpc824/rtconfig.h +++ b/bsp/lpc824/rtconfig.h @@ -6,17 +6,17 @@ // <<< Use Configuration Wizard in Context Menu >>> // Basic Configuration // Maximal level of thread priority <8-256> -// Default: 32 +// Default: 32 #define RT_THREAD_PRIORITY_MAX 8 // OS tick per second // Default: 1000 (1ms) -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 // Alignment size for CPU architecture data access -// Default: 4 +// Default: 4 #define RT_ALIGN_SIZE 4 // the max length of object name<2-16> -// Default: 8 -#define RT_NAME_MAX 8 +// Default: 8 +#define RT_NAME_MAX 8 // Using RT-Thread components initialization // Using RT-Thread components initialization #define RT_USING_COMPONENTS_INIT @@ -26,7 +26,7 @@ //#define RT_USING_USER_MAIN // // the size of main thread<1-4086> -// Default: 512 +// Default: 512 #define RT_MAIN_THREAD_STACK_SIZE 256 // @@ -64,13 +64,13 @@ #endif // The priority level of timer thread <0-31> // Default: 4 -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // The stack size of timer thread <0-8192> // Default: 512 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // The soft-timer tick per second <0-1000> // Default: 100 -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_TICK_PER_SECOND 100 // // IPC(Inter-process communication) Configuration @@ -164,7 +164,7 @@ // the history lines of finsh thread <1-32> // the history lines of finsh thread // Default: 5 -#define FINSH_HISTORY_LINES 1 +#define FINSH_HISTORY_LINES 1 // Using symbol table in finsh shell // Using symbol table in finsh shell #define FINSH_USING_SYMTAB diff --git a/bsp/mb9bf500r/adc.c b/bsp/mb9bf500r/adc.c index 85b4dc36ea..2e431e90c9 100644 --- a/bsp/mb9bf500r/adc.c +++ b/bsp/mb9bf500r/adc.c @@ -1,17 +1,13 @@ /* - * File : adc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2011-03-03 lgnq + * 2011-03-03 lgnq First version */ - + #include #include #include "mb9bf506r.h" @@ -33,45 +29,45 @@ static rt_err_t rt_adc_init(rt_device_t dev) if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) { - /* I/O setting AN08 - P18 */ + /* I/O setting AN08 - P18 */ FM3_GPIO->ADE |= 0x100; - FM3_GPIO->PFR1 = 0x100; - - /* A/DC setting */ - FM3_ADC0->SCIS1 = 0x01; - FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ - FM3_ADC0->ADST1 = 0x43; - FM3_ADC0->ADCT = 0x02; - FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ - FM3_ADC0->CMPCR = 0x00; /* disable comparator */ - - /* starting A/DC */ - FM3_ADC0->SCCR |= 0x01; /* A/DC start */ - + FM3_GPIO->PFR1 = 0x100; + + /* A/DC setting */ + FM3_ADC0->SCIS1 = 0x01; + FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ + FM3_ADC0->ADST1 = 0x43; + FM3_ADC0->ADCT = 0x02; + FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ + FM3_ADC0->CMPCR = 0x00; /* disable comparator */ + + /* starting A/DC */ + FM3_ADC0->SCCR |= 0x01; /* A/DC start */ + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - return RT_EOK; + } + return RT_EOK; } static rt_err_t rt_adc_control(rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_ADC_START: + switch (cmd) + { + case RT_DEVICE_CTRL_ADC_START: FM3_ADC0->SCCR |= 0x1; - break; - - case RT_DEVICE_CTRL_ADC_RESULT: + break; + + case RT_DEVICE_CTRL_ADC_RESULT: while(FM3_ADC0->ADSR & 0x1) ; *((rt_uint16_t*)args) = FM3_ADC0->SCFD; *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6; *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024; - break; - } - return RT_EOK; + break; + } + return RT_EOK; } extern struct rt_messagequeue mq; @@ -80,29 +76,29 @@ rt_uint16_t adc_value; static void adc_thread_entry(void *parameter) { rt_device_t device; - + #ifdef RT_USING_RTGUI struct rtgui_event_command ecmd; - + RTGUI_EVENT_COMMAND_INIT(&ecmd); ecmd.type = RTGUI_CMD_USER_INT; ecmd.command_id = ADC_UPDATE; #else struct lcd_msg msg; -#endif +#endif device = rt_device_find("adc"); while(1) { - rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); + rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value); pwm_update(adc_value/3); #ifdef RT_USING_RTGUI rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); #else msg.type = ADC_MSG; - msg.adc_value = adc_value; + msg.adc_value = adc_value; rt_mq_send(&mq, &msg, sizeof(msg)); #endif rt_thread_delay(20); @@ -112,22 +108,22 @@ static void adc_thread_entry(void *parameter) static rt_thread_t adc_thread; void rt_hw_adc_init(void) { - adc.type = RT_Device_Class_Char; - adc.rx_indicate = RT_NULL; - adc.tx_complete = RT_NULL; - adc.init = rt_adc_init; - adc.open = RT_NULL; - adc.close = RT_NULL; - adc.read = RT_NULL; - adc.write = RT_NULL; - adc.control = rt_adc_control; - adc.user_data = RT_NULL; + adc.type = RT_Device_Class_Char; + adc.rx_indicate = RT_NULL; + adc.tx_complete = RT_NULL; + adc.init = rt_adc_init; + adc.open = RT_NULL; + adc.close = RT_NULL; + adc.read = RT_NULL; + adc.write = RT_NULL; + adc.control = rt_adc_control; + adc.user_data = RT_NULL; adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5); - if(adc_thread != RT_NULL) + if(adc_thread != RT_NULL) rt_thread_startup(adc_thread); - - /* register a character device */ - rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); + + /* register a character device */ + rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mb9bf500r/adc.h b/bsp/mb9bf500r/adc.h index edbafcf831..c8846b0beb 100644 --- a/bsp/mb9bf500r/adc.h +++ b/bsp/mb9bf500r/adc.h @@ -1,28 +1,24 @@ /* - * File : adc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __ADC_H__ #define __ADC_H__ /* Exported constants ---------------------------------------------------------*/ /* Exported macro -------------------------------------------------------------*/ -#define ADC_MODE_SINGLE 0x00UL -#define ADC_MODE_SCAN 0x01UL -#define ADC_MODE_TAILGATE 0x02UL +#define ADC_MODE_SINGLE 0x00UL +#define ADC_MODE_SCAN 0x01UL +#define ADC_MODE_TAILGATE 0x02UL #define RT_DEVICE_CTRL_ADC_START 0xF1 /* start ADC conversion */ -#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ +#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ #define ADC_UPDATE 0 diff --git a/bsp/mb9bf500r/application.c b/bsp/mb9bf500r/application.c index ff22c008b1..1cbd0c2d83 100644 --- a/bsp/mb9bf500r/application.c +++ b/bsp/mb9bf500r/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -15,7 +11,7 @@ /** * @addtogroup FM3 */ - + /*@{*/ #include @@ -37,96 +33,96 @@ static char msg_pool[2048]; void rt_init_thread_entry(void *parameter) { - rt_device_t lcd; - + rt_device_t lcd; + rt_hw_led_init(); - rt_hw_key_init(); - rt_hw_adc_init(); - rt_hw_lcd_init(); - rt_hw_cpu_init(); + rt_hw_key_init(); + rt_hw_adc_init(); + rt_hw_lcd_init(); + rt_hw_cpu_init(); #ifdef RT_USING_RTGUI - extern void rtgui_system_server_init(void); + extern void rtgui_system_server_init(void); - /* find lcd device */ - lcd = rt_device_find("lcd"); - - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); + /* find lcd device */ + lcd = rt_device_find("lcd"); - /* init rtgui system server */ - rtgui_system_server_init(); - - /* startup rtgui */ - rtgui_startup(); + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); + + /* init rtgui system server */ + rtgui_system_server_init(); + + /* startup rtgui */ + rtgui_startup(); #else - { - char buf[20] = {'\0'}; + { + char buf[20] = {'\0'}; struct lcd_msg msg; - rt_device_t device; + rt_device_t device; device = rt_device_find("lcd"); - rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); - x = 1; - y = 1; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); - x = 1; - y = 20; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); - x = 1; - y = 40; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); - + rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); + x = 1; + y = 1; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); + x = 1; + y = 20; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); + x = 1; + y = 40; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); + while(1) { if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK) { - switch(msg.type) - { - case ADC_MSG: - x = 40; - y = 1; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%04d", msg.adc_value); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case CPU_MSG: - x = 40; - y = 20; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case KEY_MSG: - x = 40; - y = 40; - rt_memset(buf, 0, sizeof(buf)); + switch(msg.type) + { + case ADC_MSG: + x = 40; + y = 1; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%04d", msg.adc_value); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case CPU_MSG: + x = 40; + y = 20; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case KEY_MSG: + x = 40; + y = 40; + rt_memset(buf, 0, sizeof(buf)); switch(msg.key) - { - case KEY_DOWN: - rt_sprintf(buf, "DOWN KEY "); - break; - case KEY_UP: - rt_sprintf(buf, "UP KEY "); - break; - case KEY_RIGHT: - rt_sprintf(buf, "RIGHT KEY"); - break; - case KEY_LEFT: - rt_sprintf(buf, "LEFT KEY "); - break; - case KEY_ENTER: - rt_sprintf(buf, "ENTER KEY"); - break; - default: - rt_sprintf(buf, "NO KEY "); - break; - } - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - } + { + case KEY_DOWN: + rt_sprintf(buf, "DOWN KEY "); + break; + case KEY_UP: + rt_sprintf(buf, "UP KEY "); + break; + case KEY_RIGHT: + rt_sprintf(buf, "RIGHT KEY"); + break; + case KEY_LEFT: + rt_sprintf(buf, "LEFT KEY "); + break; + case KEY_ENTER: + rt_sprintf(buf, "ENTER KEY"); + break; + default: + rt_sprintf(buf, "NO KEY "); + break; + } + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + } } } - } + } #endif } @@ -134,12 +130,12 @@ int rt_application_init(void) { rt_thread_t init_thread; - rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); - + rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); + init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20); if(init_thread != RT_NULL) rt_thread_startup(init_thread); - + return 0; } diff --git a/bsp/mb9bf500r/board.c b/bsp/mb9bf500r/board.c index f9f83d99ed..f52a5fa3a8 100644 --- a/bsp/mb9bf500r/board.c +++ b/bsp/mb9bf500r/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,13 +29,13 @@ extern const uint32_t SystemFrequency; */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** diff --git a/bsp/mb9bf500r/board.h b/bsp/mb9bf500r/board.h index ac5823cec1..2b419c759e 100644 --- a/bsp/mb9bf500r/board.h +++ b/bsp/mb9bf500r/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf500r/cpuusage.c b/bsp/mb9bf500r/cpuusage.c index 78e65bced6..df8ba2c240 100644 --- a/bsp/mb9bf500r/cpuusage.c +++ b/bsp/mb9bf500r/cpuusage.c @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include #include #include "cpuusage.h" @@ -9,73 +18,73 @@ #include #endif -#define CPU_USAGE_CALC_TICK 10 -#define CPU_USAGE_LOOP 100 +#define CPU_USAGE_CALC_TICK 10 +#define CPU_USAGE_LOOP 100 static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0; static rt_uint32_t total_count = 0; static void cpu_usage_idle_hook() { - rt_tick_t tick; - rt_uint32_t count; - volatile rt_uint32_t loop; + rt_tick_t tick; + rt_uint32_t count; + volatile rt_uint32_t loop; - if (total_count == 0) - { - loop = 0; + if (total_count == 0) + { + loop = 0; - /* get total count */ - rt_enter_critical(); - tick = rt_tick_get(); - while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK) - { - total_count ++; - while (loop < CPU_USAGE_LOOP) loop ++; - } - rt_exit_critical(); - } + /* get total count */ + rt_enter_critical(); + tick = rt_tick_get(); + while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK) + { + total_count ++; + while (loop < CPU_USAGE_LOOP) loop ++; + } + rt_exit_critical(); + } - count = 0; - loop = 0; - /* get CPU usage */ - tick = rt_tick_get(); - while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK) - { - count ++; - while (loop < CPU_USAGE_LOOP) loop ++; - } + count = 0; + loop = 0; + /* get CPU usage */ + tick = rt_tick_get(); + while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK) + { + count ++; + while (loop < CPU_USAGE_LOOP) loop ++; + } - /* calculate major and minor */ - if (count < total_count) - { - count = total_count - count; - cpu_usage_major = (count * 100) / total_count; - cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count; - } - else - { - total_count = count; + /* calculate major and minor */ + if (count < total_count) + { + count = total_count - count; + cpu_usage_major = (count * 100) / total_count; + cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count; + } + else + { + total_count = count; - /* no CPU usage */ - cpu_usage_major = 0; - cpu_usage_minor = 0; - } + /* no CPU usage */ + cpu_usage_major = 0; + cpu_usage_minor = 0; + } } void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor) { - RT_ASSERT(major != RT_NULL); - RT_ASSERT(minor != RT_NULL); + RT_ASSERT(major != RT_NULL); + RT_ASSERT(minor != RT_NULL); - *major = cpu_usage_major; - *minor = cpu_usage_minor; + *major = cpu_usage_major; + *minor = cpu_usage_minor; } void cpu_usage_init() { - /* set idle thread hook */ - rt_thread_idle_sethook(cpu_usage_idle_hook); + /* set idle thread hook */ + rt_thread_idle_sethook(cpu_usage_idle_hook); } extern struct rt_messagequeue mq; extern rt_thread_t info_tid; @@ -83,12 +92,12 @@ static void cpu_thread_entry(void *parameter) { #ifdef RT_USING_RTGUI struct rtgui_event_command ecmd; - + RTGUI_EVENT_COMMAND_INIT(&ecmd); ecmd.type = RTGUI_CMD_USER_INT; ecmd.command_id = CPU_UPDATE; #else - struct lcd_msg msg; + struct lcd_msg msg; #endif while (1) @@ -96,10 +105,10 @@ static void cpu_thread_entry(void *parameter) #ifdef RT_USING_RTGUI rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); #else - msg.type = CPU_MSG; - msg.major = cpu_usage_major; - msg.minor = cpu_usage_minor; - rt_mq_send(&mq, &msg, sizeof(msg)); + msg.type = CPU_MSG; + msg.major = cpu_usage_major; + msg.minor = cpu_usage_minor; + rt_mq_send(&mq, &msg, sizeof(msg)); #endif rt_thread_delay(20); } @@ -110,6 +119,6 @@ void rt_hw_cpu_init(void) { cpu_usage_init(); cpu_thread = rt_thread_create("cpu", cpu_thread_entry, RT_NULL, 384, 27, 5); - if(cpu_thread != RT_NULL) + if(cpu_thread != RT_NULL) rt_thread_startup(cpu_thread); } diff --git a/bsp/mb9bf500r/cpuusage.h b/bsp/mb9bf500r/cpuusage.h index c7dd70c944..6a53481f3f 100644 --- a/bsp/mb9bf500r/cpuusage.h +++ b/bsp/mb9bf500r/cpuusage.h @@ -1,17 +1,13 @@ /* - * File : cpuusage.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __CPUUSAGE_H__ #define __CPUUSAGE_H__ diff --git a/bsp/mb9bf500r/font.h b/bsp/mb9bf500r/font.h index bc56c0bb34..92253c59c3 100644 --- a/bsp/mb9bf500r/font.h +++ b/bsp/mb9bf500r/font.h @@ -1,263 +1,272 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef __FONT_H #define __FONT_H /* Font definition */ -#define ________ 0x00 -#define _______X 0x01 -#define ______X_ 0x02 -#define ______XX 0x03 -#define _____X__ 0x04 -#define _____X_X 0x05 -#define _____XX_ 0x06 -#define _____XXX 0x07 -#define ____X___ 0x08 -#define ____X__X 0x09 -#define ____X_X_ 0x0a -#define ____X_XX 0x0b -#define ____XX__ 0x0c -#define ____XX_X 0x0d -#define ____XXX_ 0x0e -#define ____XXXX 0x0f -#define ___X____ 0x10 -#define ___X___X 0x11 -#define ___X__X_ 0x12 -#define ___X__XX 0x13 -#define ___X_X__ 0x14 -#define ___X_X_X 0x15 -#define ___X_XX_ 0x16 -#define ___X_XXX 0x17 -#define ___XX___ 0x18 -#define ___XX__X 0x19 -#define ___XX_X_ 0x1a -#define ___XX_XX 0x1b -#define ___XXX__ 0x1c -#define ___XXX_X 0x1d -#define ___XXXX_ 0x1e -#define ___XXXXX 0x1f -#define __X_____ 0x20 -#define __X____X 0x21 -#define __X___X_ 0x22 -#define __X___XX 0x23 -#define __X__X__ 0x24 -#define __X__X_X 0x25 -#define __X__XX_ 0x26 -#define __X__XXX 0x27 -#define __X_X___ 0x28 -#define __X_X__X 0x29 -#define __X_X_X_ 0x2a -#define __X_X_XX 0x2b -#define __X_XX__ 0x2c -#define __X_XX_X 0x2d -#define __X_XXX_ 0x2e -#define __X_XXXX 0x2f -#define __XX____ 0x30 -#define __XX___X 0x31 -#define __XX__X_ 0x32 -#define __XX__XX 0x33 -#define __XX_X__ 0x34 -#define __XX_X_X 0x35 -#define __XX_XX_ 0x36 -#define __XX_XXX 0x37 -#define __XXX___ 0x38 -#define __XXX__X 0x39 -#define __XXX_X_ 0x3a -#define __XXX_XX 0x3b -#define __XXXX__ 0x3c -#define __XXXX_X 0x3d -#define __XXXXX_ 0x3e -#define __XXXXXX 0x3f -#define _X______ 0x40 -#define _X_____X 0x41 -#define _X____X_ 0x42 -#define _X____XX 0x43 -#define _X___X__ 0x44 -#define _X___X_X 0x45 -#define _X___XX_ 0x46 -#define _X___XXX 0x47 -#define _X__X___ 0x48 -#define _X__X__X 0x49 -#define _X__X_X_ 0x4a -#define _X__X_XX 0x4b -#define _X__XX__ 0x4c -#define _X__XX_X 0x4d -#define _X__XXX_ 0x4e -#define _X__XXXX 0x4f -#define _X_X____ 0x50 -#define _X_X___X 0x51 -#define _X_X__X_ 0x52 -#define _X_X__XX 0x53 -#define _X_X_X__ 0x54 -#define _X_X_X_X 0x55 -#define _X_X_XX_ 0x56 -#define _X_X_XXX 0x57 -#define _X_XX___ 0x58 -#define _X_XX__X 0x59 -#define _X_XX_X_ 0x5a -#define _X_XX_XX 0x5b -#define _X_XXX__ 0x5c -#define _X_XXX_X 0x5d -#define _X_XXXX_ 0x5e -#define _X_XXXXX 0x5f -#define _XX_____ 0x60 -#define _XX____X 0x61 -#define _XX___X_ 0x62 -#define _XX___XX 0x63 -#define _XX__X__ 0x64 -#define _XX__X_X 0x65 -#define _XX__XX_ 0x66 -#define _XX__XXX 0x67 -#define _XX_X___ 0x68 -#define _XX_X__X 0x69 -#define _XX_X_X_ 0x6a -#define _XX_X_XX 0x6b -#define _XX_XX__ 0x6c -#define _XX_XX_X 0x6d -#define _XX_XXX_ 0x6e -#define _XX_XXXX 0x6f -#define _XXX____ 0x70 -#define _XXX___X 0x71 -#define _XXX__X_ 0x72 -#define _XXX__XX 0x73 -#define _XXX_X__ 0x74 -#define _XXX_X_X 0x75 -#define _XXX_XX_ 0x76 -#define _XXX_XXX 0x77 -#define _XXXX___ 0x78 -#define _XXXX__X 0x79 -#define _XXXX_X_ 0x7a -#define _XXXX_XX 0x7b -#define _XXXXX__ 0x7c -#define _XXXXX_X 0x7d -#define _XXXXXX_ 0x7e -#define _XXXXXXX 0x7f -#define X_______ 0x80 -#define X______X 0x81 -#define X_____X_ 0x82 -#define X_____XX 0x83 -#define X____X__ 0x84 -#define X____X_X 0x85 -#define X____XX_ 0x86 -#define X____XXX 0x87 -#define X___X___ 0x88 -#define X___X__X 0x89 -#define X___X_X_ 0x8a -#define X___X_XX 0x8b -#define X___XX__ 0x8c -#define X___XX_X 0x8d -#define X___XXX_ 0x8e -#define X___XXXX 0x8f -#define X__X____ 0x90 -#define X__X___X 0x91 -#define X__X__X_ 0x92 -#define X__X__XX 0x93 -#define X__X_X__ 0x94 -#define X__X_X_X 0x95 -#define X__X_XX_ 0x96 -#define X__X_XXX 0x97 -#define X__XX___ 0x98 -#define X__XX__X 0x99 -#define X__XX_X_ 0x9a -#define X__XX_XX 0x9b -#define X__XXX__ 0x9c -#define X__XXX_X 0x9d -#define X__XXXX_ 0x9e -#define X__XXXXX 0x9f -#define X_X_____ 0xa0 -#define X_X____X 0xa1 -#define X_X___X_ 0xa2 -#define X_X___XX 0xa3 -#define X_X__X__ 0xa4 -#define X_X__X_X 0xa5 -#define X_X__XX_ 0xa6 -#define X_X__XXX 0xa7 -#define X_X_X___ 0xa8 -#define X_X_X__X 0xa9 -#define X_X_X_X_ 0xaa -#define X_X_X_XX 0xab -#define X_X_XX__ 0xac -#define X_X_XX_X 0xad -#define X_X_XXX_ 0xae -#define X_X_XXXX 0xaf -#define X_XX____ 0xb0 -#define X_XX___X 0xb1 -#define X_XX__X_ 0xb2 -#define X_XX__XX 0xb3 -#define X_XX_X__ 0xb4 -#define X_XX_X_X 0xb5 -#define X_XX_XX_ 0xb6 -#define X_XX_XXX 0xb7 -#define X_XXX___ 0xb8 -#define X_XXX__X 0xb9 -#define X_XXX_X_ 0xba -#define X_XXX_XX 0xbb -#define X_XXXX__ 0xbc -#define X_XXXX_X 0xbd -#define X_XXXXX_ 0xbe -#define X_XXXXXX 0xbf -#define XX______ 0xc0 -#define XX_____X 0xc1 -#define XX____X_ 0xc2 -#define XX____XX 0xc3 -#define XX___X__ 0xc4 -#define XX___X_X 0xc5 -#define XX___XX_ 0xc6 -#define XX___XXX 0xc7 -#define XX__X___ 0xc8 -#define XX__X__X 0xc9 -#define XX__X_X_ 0xca -#define XX__X_XX 0xcb -#define XX__XX__ 0xcc -#define XX__XX_X 0xcd -#define XX__XXX_ 0xce -#define XX__XXXX 0xcf -#define XX_X____ 0xd0 -#define XX_X___X 0xd1 -#define XX_X__X_ 0xd2 -#define XX_X__XX 0xd3 -#define XX_X_X__ 0xd4 -#define XX_X_X_X 0xd5 -#define XX_X_XX_ 0xd6 -#define XX_X_XXX 0xd7 -#define XX_XX___ 0xd8 -#define XX_XX__X 0xd9 -#define XX_XX_X_ 0xda -#define XX_XX_XX 0xdb -#define XX_XXX__ 0xdc -#define XX_XXX_X 0xdd -#define XX_XXXX_ 0xde -#define XX_XXXXX 0xdf -#define XXX_____ 0xe0 -#define XXX____X 0xe1 -#define XXX___X_ 0xe2 -#define XXX___XX 0xe3 -#define XXX__X__ 0xe4 -#define XXX__X_X 0xe5 -#define XXX__XX_ 0xe6 -#define XXX__XXX 0xe7 -#define XXX_X___ 0xe8 -#define XXX_X__X 0xe9 -#define XXX_X_X_ 0xea -#define XXX_X_XX 0xeb -#define XXX_XX__ 0xec -#define XXX_XX_X 0xed -#define XXX_XXX_ 0xee -#define XXX_XXXX 0xef -#define XXXX____ 0xf0 -#define XXXX___X 0xf1 -#define XXXX__X_ 0xf2 -#define XXXX__XX 0xf3 -#define XXXX_X__ 0xf4 -#define XXXX_X_X 0xf5 -#define XXXX_XX_ 0xf6 -#define XXXX_XXX 0xf7 -#define XXXXX___ 0xf8 -#define XXXXX__X 0xf9 -#define XXXXX_X_ 0xfa -#define XXXXX_XX 0xfb -#define XXXXXX__ 0xfc -#define XXXXXX_X 0xfd -#define XXXXXXX_ 0xfe -#define XXXXXXXX 0xff +#define ________ 0x00 +#define _______X 0x01 +#define ______X_ 0x02 +#define ______XX 0x03 +#define _____X__ 0x04 +#define _____X_X 0x05 +#define _____XX_ 0x06 +#define _____XXX 0x07 +#define ____X___ 0x08 +#define ____X__X 0x09 +#define ____X_X_ 0x0a +#define ____X_XX 0x0b +#define ____XX__ 0x0c +#define ____XX_X 0x0d +#define ____XXX_ 0x0e +#define ____XXXX 0x0f +#define ___X____ 0x10 +#define ___X___X 0x11 +#define ___X__X_ 0x12 +#define ___X__XX 0x13 +#define ___X_X__ 0x14 +#define ___X_X_X 0x15 +#define ___X_XX_ 0x16 +#define ___X_XXX 0x17 +#define ___XX___ 0x18 +#define ___XX__X 0x19 +#define ___XX_X_ 0x1a +#define ___XX_XX 0x1b +#define ___XXX__ 0x1c +#define ___XXX_X 0x1d +#define ___XXXX_ 0x1e +#define ___XXXXX 0x1f +#define __X_____ 0x20 +#define __X____X 0x21 +#define __X___X_ 0x22 +#define __X___XX 0x23 +#define __X__X__ 0x24 +#define __X__X_X 0x25 +#define __X__XX_ 0x26 +#define __X__XXX 0x27 +#define __X_X___ 0x28 +#define __X_X__X 0x29 +#define __X_X_X_ 0x2a +#define __X_X_XX 0x2b +#define __X_XX__ 0x2c +#define __X_XX_X 0x2d +#define __X_XXX_ 0x2e +#define __X_XXXX 0x2f +#define __XX____ 0x30 +#define __XX___X 0x31 +#define __XX__X_ 0x32 +#define __XX__XX 0x33 +#define __XX_X__ 0x34 +#define __XX_X_X 0x35 +#define __XX_XX_ 0x36 +#define __XX_XXX 0x37 +#define __XXX___ 0x38 +#define __XXX__X 0x39 +#define __XXX_X_ 0x3a +#define __XXX_XX 0x3b +#define __XXXX__ 0x3c +#define __XXXX_X 0x3d +#define __XXXXX_ 0x3e +#define __XXXXXX 0x3f +#define _X______ 0x40 +#define _X_____X 0x41 +#define _X____X_ 0x42 +#define _X____XX 0x43 +#define _X___X__ 0x44 +#define _X___X_X 0x45 +#define _X___XX_ 0x46 +#define _X___XXX 0x47 +#define _X__X___ 0x48 +#define _X__X__X 0x49 +#define _X__X_X_ 0x4a +#define _X__X_XX 0x4b +#define _X__XX__ 0x4c +#define _X__XX_X 0x4d +#define _X__XXX_ 0x4e +#define _X__XXXX 0x4f +#define _X_X____ 0x50 +#define _X_X___X 0x51 +#define _X_X__X_ 0x52 +#define _X_X__XX 0x53 +#define _X_X_X__ 0x54 +#define _X_X_X_X 0x55 +#define _X_X_XX_ 0x56 +#define _X_X_XXX 0x57 +#define _X_XX___ 0x58 +#define _X_XX__X 0x59 +#define _X_XX_X_ 0x5a +#define _X_XX_XX 0x5b +#define _X_XXX__ 0x5c +#define _X_XXX_X 0x5d +#define _X_XXXX_ 0x5e +#define _X_XXXXX 0x5f +#define _XX_____ 0x60 +#define _XX____X 0x61 +#define _XX___X_ 0x62 +#define _XX___XX 0x63 +#define _XX__X__ 0x64 +#define _XX__X_X 0x65 +#define _XX__XX_ 0x66 +#define _XX__XXX 0x67 +#define _XX_X___ 0x68 +#define _XX_X__X 0x69 +#define _XX_X_X_ 0x6a +#define _XX_X_XX 0x6b +#define _XX_XX__ 0x6c +#define _XX_XX_X 0x6d +#define _XX_XXX_ 0x6e +#define _XX_XXXX 0x6f +#define _XXX____ 0x70 +#define _XXX___X 0x71 +#define _XXX__X_ 0x72 +#define _XXX__XX 0x73 +#define _XXX_X__ 0x74 +#define _XXX_X_X 0x75 +#define _XXX_XX_ 0x76 +#define _XXX_XXX 0x77 +#define _XXXX___ 0x78 +#define _XXXX__X 0x79 +#define _XXXX_X_ 0x7a +#define _XXXX_XX 0x7b +#define _XXXXX__ 0x7c +#define _XXXXX_X 0x7d +#define _XXXXXX_ 0x7e +#define _XXXXXXX 0x7f +#define X_______ 0x80 +#define X______X 0x81 +#define X_____X_ 0x82 +#define X_____XX 0x83 +#define X____X__ 0x84 +#define X____X_X 0x85 +#define X____XX_ 0x86 +#define X____XXX 0x87 +#define X___X___ 0x88 +#define X___X__X 0x89 +#define X___X_X_ 0x8a +#define X___X_XX 0x8b +#define X___XX__ 0x8c +#define X___XX_X 0x8d +#define X___XXX_ 0x8e +#define X___XXXX 0x8f +#define X__X____ 0x90 +#define X__X___X 0x91 +#define X__X__X_ 0x92 +#define X__X__XX 0x93 +#define X__X_X__ 0x94 +#define X__X_X_X 0x95 +#define X__X_XX_ 0x96 +#define X__X_XXX 0x97 +#define X__XX___ 0x98 +#define X__XX__X 0x99 +#define X__XX_X_ 0x9a +#define X__XX_XX 0x9b +#define X__XXX__ 0x9c +#define X__XXX_X 0x9d +#define X__XXXX_ 0x9e +#define X__XXXXX 0x9f +#define X_X_____ 0xa0 +#define X_X____X 0xa1 +#define X_X___X_ 0xa2 +#define X_X___XX 0xa3 +#define X_X__X__ 0xa4 +#define X_X__X_X 0xa5 +#define X_X__XX_ 0xa6 +#define X_X__XXX 0xa7 +#define X_X_X___ 0xa8 +#define X_X_X__X 0xa9 +#define X_X_X_X_ 0xaa +#define X_X_X_XX 0xab +#define X_X_XX__ 0xac +#define X_X_XX_X 0xad +#define X_X_XXX_ 0xae +#define X_X_XXXX 0xaf +#define X_XX____ 0xb0 +#define X_XX___X 0xb1 +#define X_XX__X_ 0xb2 +#define X_XX__XX 0xb3 +#define X_XX_X__ 0xb4 +#define X_XX_X_X 0xb5 +#define X_XX_XX_ 0xb6 +#define X_XX_XXX 0xb7 +#define X_XXX___ 0xb8 +#define X_XXX__X 0xb9 +#define X_XXX_X_ 0xba +#define X_XXX_XX 0xbb +#define X_XXXX__ 0xbc +#define X_XXXX_X 0xbd +#define X_XXXXX_ 0xbe +#define X_XXXXXX 0xbf +#define XX______ 0xc0 +#define XX_____X 0xc1 +#define XX____X_ 0xc2 +#define XX____XX 0xc3 +#define XX___X__ 0xc4 +#define XX___X_X 0xc5 +#define XX___XX_ 0xc6 +#define XX___XXX 0xc7 +#define XX__X___ 0xc8 +#define XX__X__X 0xc9 +#define XX__X_X_ 0xca +#define XX__X_XX 0xcb +#define XX__XX__ 0xcc +#define XX__XX_X 0xcd +#define XX__XXX_ 0xce +#define XX__XXXX 0xcf +#define XX_X____ 0xd0 +#define XX_X___X 0xd1 +#define XX_X__X_ 0xd2 +#define XX_X__XX 0xd3 +#define XX_X_X__ 0xd4 +#define XX_X_X_X 0xd5 +#define XX_X_XX_ 0xd6 +#define XX_X_XXX 0xd7 +#define XX_XX___ 0xd8 +#define XX_XX__X 0xd9 +#define XX_XX_X_ 0xda +#define XX_XX_XX 0xdb +#define XX_XXX__ 0xdc +#define XX_XXX_X 0xdd +#define XX_XXXX_ 0xde +#define XX_XXXXX 0xdf +#define XXX_____ 0xe0 +#define XXX____X 0xe1 +#define XXX___X_ 0xe2 +#define XXX___XX 0xe3 +#define XXX__X__ 0xe4 +#define XXX__X_X 0xe5 +#define XXX__XX_ 0xe6 +#define XXX__XXX 0xe7 +#define XXX_X___ 0xe8 +#define XXX_X__X 0xe9 +#define XXX_X_X_ 0xea +#define XXX_X_XX 0xeb +#define XXX_XX__ 0xec +#define XXX_XX_X 0xed +#define XXX_XXX_ 0xee +#define XXX_XXXX 0xef +#define XXXX____ 0xf0 +#define XXXX___X 0xf1 +#define XXXX__X_ 0xf2 +#define XXXX__XX 0xf3 +#define XXXX_X__ 0xf4 +#define XXXX_X_X 0xf5 +#define XXXX_XX_ 0xf6 +#define XXXX_XXX 0xf7 +#define XXXXX___ 0xf8 +#define XXXXX__X 0xf9 +#define XXXXX_X_ 0xfa +#define XXXXX_XX 0xfb +#define XXXXXX__ 0xfc +#define XXXXXX_X 0xfd +#define XXXXXXX_ 0xfe +#define XXXXXXXX 0xff @@ -272,8 +281,8 @@ const unsigned char FONTTYPE8_8[][8] = { ________, ________, ________, - ________} - + ________} + /* 0 */ ,{ __XXX___, @@ -283,7 +292,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, _XX_XX__, __XXX___, - ________} + ________} /* 1 */ ,{ @@ -294,7 +303,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, ___XX___, _XXXXXX_, - ________} + ________} /* 2 */ ,{ @@ -305,7 +314,7 @@ const unsigned char FONTTYPE8_8[][8] = { __XX____, _XX__XX_, XXXXXXX_, - ________} + ________} /* 3 */ ,{ @@ -316,7 +325,7 @@ const unsigned char FONTTYPE8_8[][8] = { _____XX_, XX___XX_, _XXXXX__, - ________} + ________} /* 4 */ ,{ @@ -327,7 +336,7 @@ const unsigned char FONTTYPE8_8[][8] = { XXXXXXX_, ____XX__, ___XXXX_, - ________} + ________} /* 5 */ ,{ @@ -338,7 +347,7 @@ const unsigned char FONTTYPE8_8[][8] = { _____XX_, XX___XX_, _XXXXX__, - ________} + ________} /* 6 */ ,{ @@ -349,7 +358,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, _XXXXX__, - ________} + ________} /* 7 */ ,{ @@ -360,7 +369,7 @@ const unsigned char FONTTYPE8_8[][8] = { __XX____, __XX____, __XX____, - ________} + ________} /* 8 */ ,{ @@ -371,7 +380,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, _XXXXX__, - ________} + ________} /* 9 */ ,{ @@ -382,7 +391,7 @@ const unsigned char FONTTYPE8_8[][8] = { _____XX_, ____XX__, _XXXX___, - ________} + ________} /* A */ ,{ @@ -393,7 +402,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, XX___XX_, - ________} + ________} /* B */ ,{ @@ -404,7 +413,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX__XX_, _XX__XX_, XXXXXX__, - ________} + ________} /* C */ ,{ @@ -415,7 +424,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX______, _XX__XX_, __XXXX__, - ________} + ________} /* D */ ,{ @@ -426,7 +435,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX__XX_, _XX_XX__, XXXXX___, - ________} + ________} /* E */ ,{ @@ -437,7 +446,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_X___, _XX___X_, XXXXXXX_, - ________} + ________} /* F */ ,{ @@ -448,7 +457,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_X___, _XX_____, XXXX____, - ________} + ________} /* G */ ,{ @@ -459,7 +468,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XXX_, _XX__XX_, __XXX_X_, - ________} + ________} /* H */ ,{ @@ -470,7 +479,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, XX___XX_, - ________} + ________} /* I */ ,{ @@ -481,7 +490,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, ___XX___, __XXXX__, - ________} + ________} /* J */ ,{ @@ -492,7 +501,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XX__, XX__XX__, _XXXX___, - ________} + ________} /* K */ ,{ @@ -503,7 +512,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_XX__, _XX__XX_, XXX__XX_, - ________} + ________} /* L */ ,{ @@ -514,7 +523,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX___X_, _XX__XX_, XXXXXXX_, - ________} + ________} /* M */ ,{ @@ -525,7 +534,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX_X_XX_, XX___XX_, XX___XX_, - ________} + ________} /* N */ ,{ @@ -536,7 +545,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XXX_, XX___XX_, XX___XX_, - ________} + ________} /* O */ ,{ @@ -547,7 +556,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, _XXXXX__, - ________} + ________} /* P */ ,{ @@ -558,7 +567,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_____, _XX_____, XXXX____, - ________} + ________} /* Q */ ,{ @@ -569,7 +578,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX__XXX_, _XXXXX__, - ____XXX_} + ____XXX_} /* R */ ,{ @@ -580,7 +589,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_XX__, _XX__XX_, XXX__XX_, - ________} + ________} /* S */ ,{ @@ -591,7 +600,7 @@ const unsigned char FONTTYPE8_8[][8] = { ____XX__, _XX__XX_, __XXXX__, - ________} + ________} /* T */ ,{ @@ -602,7 +611,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, ___XX___, __XXXX__, - ________} + ________} /* U */ ,{ @@ -613,7 +622,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, _XXXXX__, - ________} + ________} /* V */ ,{ @@ -624,7 +633,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, _XX_XX__, __XXX___, - ________} + ________} /* W */ ,{ @@ -635,7 +644,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX_X_XX_, XXXXXXX_, _XX_XX__, - ________} + ________} /* X */ ,{ @@ -646,7 +655,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_XX__, XX___XX_, XX___XX_, - ________} + ________} /* Y */ ,{ @@ -657,7 +666,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, ___XX___, __XXXX__, - ________} + ________} /* Z */ ,{ @@ -668,7 +677,7 @@ const unsigned char FONTTYPE8_8[][8] = { __XX__X_, _XX__XX_, XXXXXXX_, - ________} + ________} /* a */ ,{ @@ -679,7 +688,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XXXXX__, XX__XX__, _XXX_XX_, - ________} + ________} /* b */ ,{ @@ -690,7 +699,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX__XX_, _XX__XX_, XX_XXX__, - ________} + ________} /* c */ ,{ @@ -701,7 +710,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX______, XX___XX_, _XXXXX__, - ________} + ________} /* d */ ,{ @@ -712,7 +721,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XX__, XX__XX__, _XXX_XX_, - ________} + ________} /* e */ ,{ @@ -723,7 +732,7 @@ const unsigned char FONTTYPE8_8[][8] = { XXXXXXX_, XX______, _XXXXX__, - ________} + ________} /* f */ ,{ @@ -734,7 +743,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_____, _XX_____, XXXX____, - ________} + ________} /* g */ ,{ @@ -745,7 +754,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XX__, _XXXXX__, ____XX__, - XXXXX___} + XXXXX___} /* h */ ,{ @@ -756,7 +765,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX__XX_, _XX__XX_, XXX__XX_, - ________} + ________} /* i */ ,{ @@ -767,7 +776,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, ___XX___, __XXXX__, - ________} + ________} /* j */ ,{ @@ -778,7 +787,7 @@ const unsigned char FONTTYPE8_8[][8] = { _____XX_, _XX__XX_, _XX__XX_, - __XXXX__} + __XXXX__} /* k */ ,{ @@ -789,7 +798,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XXXX___, _XX_XX__, XXX__XX_, - ________} + ________} /* l */ ,{ @@ -800,7 +809,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, ___XX___, __XXXX__, - ________} + ________} /* m */ ,{ @@ -811,7 +820,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX_X_XX_, XX_X_XX_, XX_X_XX_, - ________} + ________} /* n */ ,{ @@ -822,7 +831,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX__XX_, _XX__XX_, _XX__XX_, - ________} + ________} /* o */ ,{ @@ -833,7 +842,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, XX___XX_, _XXXXX__, - ________} + ________} /* p */ ,{ @@ -844,7 +853,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX__XX_, _XXXXX__, _XX_____, - XXXX____} + XXXX____} /* q */ ,{ @@ -855,7 +864,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XX__, _XXXXX__, ____XX__, - ___XXXX_} + ___XXXX_} /* r */ ,{ @@ -866,7 +875,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XX_____, _XX_____, XXXX____, - ________} + ________} /* s */ ,{ @@ -877,7 +886,7 @@ const unsigned char FONTTYPE8_8[][8] = { _XXXXX__, _____XX_, XXXXXX__, - ________} + ________} /* t */ ,{ @@ -888,7 +897,7 @@ const unsigned char FONTTYPE8_8[][8] = { __XX____, __XX_XX_, ___XXX__, - ________} + ________} /* u */ ,{ @@ -899,7 +908,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX__XX__, XX__XX__, _XXX_XX_, - ________} + ________} /* v */ ,{ @@ -910,7 +919,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, _XX_XX__, __XXX___, - ________} + ________} /* w */ ,{ @@ -921,7 +930,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX_X_XX_, XXXXXXX_, _XX_XX__, - ________} + ________} /* x */ ,{ @@ -932,7 +941,7 @@ const unsigned char FONTTYPE8_8[][8] = { __XXX___, _XX_XX__, XX___XX_, - ________} + ________} /* y */ ,{ @@ -943,7 +952,7 @@ const unsigned char FONTTYPE8_8[][8] = { XX___XX_, _XXXXXX_, _____XX_, - XXXXXX__} + XXXXXX__} /* z */ ,{ @@ -954,7 +963,7 @@ const unsigned char FONTTYPE8_8[][8] = { ___XX___, __XX__X_, _XXXXXX_, - ________} + ________} }; diff --git a/bsp/mb9bf500r/info.c b/bsp/mb9bf500r/info.c index 6e76c95e59..fcf514f1b0 100644 --- a/bsp/mb9bf500r/info.c +++ b/bsp/mb9bf500r/info.c @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include #ifdef RT_USING_RTGUI @@ -15,37 +24,37 @@ extern rt_uint16_t adc_value; static rt_uint8_t index = 0 ; static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) { - if (event->type == RTGUI_EVENT_PAINT) - { - struct rtgui_dc* dc; - struct rtgui_rect rect; + if (event->type == RTGUI_EVENT_PAINT) + { + struct rtgui_dc* dc; + struct rtgui_rect rect; - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) return RT_FALSE; - rtgui_widget_get_rect(widget, &rect); - - rtgui_dc_fill_rect(dc, &rect); - rect.x2 -= 1; rect.y2 -= 1; - rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1); - rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2); - - rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2); - rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1); - - /* shrink border */ - rtgui_rect_inflate(&rect, -1); - - /* draw text */ rtgui_widget_get_rect(widget, &rect); - rect.y1 += 25; + + rtgui_dc_fill_rect(dc, &rect); + rect.x2 -= 1; rect.y2 -= 1; + rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1); + rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2); + + rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2); + rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1); + + /* shrink border */ + rtgui_rect_inflate(&rect, -1); + + /* draw text */ + rtgui_widget_get_rect(widget, &rect); + rect.y1 += 25; rtgui_dc_draw_text(dc, " FM3 Easy Kit Demo", &rect); rect.y1 += 10; rtgui_dc_draw_text(dc, " rt-thread / RTGUI", &rect); - rtgui_dc_end_drawing(dc, RT_TRUE); + rtgui_dc_end_drawing(dc, RT_TRUE); - return RT_FALSE; - } + return RT_FALSE; + } else if (event->type == RTGUI_EVENT_KBD) { struct rtgui_dc* dc; @@ -67,18 +76,18 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev break; case RTGUIK_UP: rt_sprintf(key_str, "%s", "U"); - break; + break; default: rt_sprintf(key_str, "%s", "S"); break; } dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) + if (dc == RT_NULL) return RT_FALSE; rect.x1 = 118; - rect.y1 = 1; + rect.y1 = 1; rect.x2 = 127; - rect.y2 = 10; + rect.y2 = 10; rtgui_dc_fill_rect(dc, &rect); rtgui_dc_draw_text(dc, key_str, &rect); rtgui_dc_end_drawing(dc, RT_TRUE); @@ -86,12 +95,12 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev else if (ekbd->type == RTGUI_KEYUP) { dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) + if (dc == RT_NULL) return RT_FALSE; rect.x1 = 118; - rect.y1 = 1; + rect.y1 = 1; rect.x2 = 127; - rect.y2 = 10; + rect.y2 = 10; rtgui_dc_fill_rect(dc, &rect); //rtgui_dc_draw_text(dc, key_str, &rect); rtgui_dc_end_drawing(dc, RT_TRUE); @@ -105,38 +114,38 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev struct rtgui_event_command* ecmd; rt_uint8_t major,minor; dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) + if (dc == RT_NULL) return RT_FALSE; - + ecmd = (struct rtgui_event_command*)event; switch (ecmd->command_id) - { + { case ADC_UPDATE: rect.x1 = 1; - rect.y1 = 1; + rect.y1 = 1; rect.x2 = 117; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(str, "ADC = %d mv", adc_value); - rtgui_dc_draw_text(dc, str, &rect); + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(str, "ADC = %d mv", adc_value); + rtgui_dc_draw_text(dc, str, &rect); break; case CPU_UPDATE: cpu_usage_get(&major, &minor); rect.x1 = 1; - rect.y1 = 12; + rect.y1 = 12; rect.x2 = 127; - rect.y2 = 22; - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(str, "CPU : %d.%d%", major, minor); - rtgui_dc_draw_text(dc, str, &rect); + rect.y2 = 22; + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(str, "CPU : %d.%d%", major, minor); + rtgui_dc_draw_text(dc, str, &rect); - rect.y1 = 23; - rect.y2 = 63; + rect.y1 = 23; + rect.y2 = 63; index++; if (index == 127) - { + { index = 1; - rtgui_dc_fill_rect(dc, &rect); + rtgui_dc_fill_rect(dc, &rect); } if (major>40) rtgui_dc_draw_vline(dc, index, rect.y1, rect.y2); @@ -144,42 +153,42 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev rtgui_dc_draw_vline(dc, index, rect.y2-major, rect.y2); break; } - rtgui_dc_end_drawing(dc, RT_TRUE); + rtgui_dc_end_drawing(dc, RT_TRUE); } - return rtgui_view_event_handler(widget, event); + return rtgui_view_event_handler(widget, event); } static void info_entry(void* parameter) { - rt_mq_t mq; - struct rtgui_view* view; - struct rtgui_workbench* workbench; + rt_mq_t mq; + struct rtgui_view* view; + struct rtgui_workbench* workbench; - mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO); - rtgui_thread_register(rt_thread_self(), mq); + mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO); + rtgui_thread_register(rt_thread_self(), mq); - workbench = rtgui_workbench_create("info", "workbench"); - if(workbench == RT_NULL) + workbench = rtgui_workbench_create("info", "workbench"); + if(workbench == RT_NULL) return; - view = rtgui_view_create("view"); - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white; + view = rtgui_view_create("view"); + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white; RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(view)) = black; - rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler); + rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler); - rtgui_workbench_add_view(workbench, view); + rtgui_workbench_add_view(workbench, view); /* this view can be focused */ RTGUI_WIDGET(view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; /* set widget focus */ - rtgui_widget_focus(RTGUI_WIDGET(view)); + rtgui_widget_focus(RTGUI_WIDGET(view)); - rtgui_view_show(view, RT_FALSE); + rtgui_view_show(view, RT_FALSE); - rtgui_workbench_event_loop(workbench); + rtgui_workbench_event_loop(workbench); - rtgui_thread_deregister(rt_thread_self()); - rt_mq_delete(mq); + rtgui_thread_deregister(rt_thread_self()); + rt_mq_delete(mq); } rt_thread_t info_tid; @@ -195,10 +204,9 @@ void info_init() void rtgui_startup() { rtgui_rect_t rect; - - /* GUIϵͳ³õʼ»¯ */ + rtgui_system_server_init(); - + /* register dock panel */ rect.x1 = 0; rect.y1 = 0; @@ -206,9 +214,9 @@ void rtgui_startup() rect.y2 = 64; rtgui_panel_register("info", &rect); rtgui_panel_set_default_focused("info"); - - /* Æô¶¯info workbench */ - info_init(); + + /*init info workbench */ + info_init(); } #endif diff --git a/bsp/mb9bf500r/key.c b/bsp/mb9bf500r/key.c index 6a574a1251..1886e72974 100644 --- a/bsp/mb9bf500r/key.c +++ b/bsp/mb9bf500r/key.c @@ -1,15 +1,11 @@ /* - * File : key.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2011-03-03 lgnq + * 2011-03-03 lgnq */ #include @@ -25,7 +21,7 @@ static void key_io_init(void) { /*Select CPIO function*/ KEY_PFR &= ~KEY_MASK; - /*Set CPIO Pull-Up function*/ + /*Set CPIO Pull-Up function*/ KEY_PCR |= KEY_MASK; /*Make button pins inputs*/ KEY_DDR &= ~KEY_MASK; @@ -38,7 +34,7 @@ static void key_thread_entry(void *parameter) rt_uint8_t i; struct rtgui_event_kbd kbd_event; - + key_io_init(); /* init keyboard event */ @@ -109,49 +105,49 @@ static void key_thread_entry(void *parameter) rt_thread_delay(next_delay); } #else - extern struct rt_messagequeue mq; - rt_time_t next_delay; - struct lcd_msg msg; - msg.type = KEY_MSG; - - key_io_init(); - - while (1) - { - msg.key = NO_KEY; - - next_delay = RT_TICK_PER_SECOND/10; - - if (KEY_ENTER_GETVALUE() == 0 ) - { - msg.key = KEY_ENTER; - } - - if (KEY_DOWN_GETVALUE() == 0) - { - msg.key = KEY_DOWN; - } - - if (KEY_UP_GETVALUE() == 0) - { - msg.key = KEY_UP; - } - - if (KEY_RIGHT_GETVALUE() == 0) - { - msg.key = KEY_RIGHT; - } - - if (KEY_LEFT_GETVALUE() == 0) - { - msg.key = KEY_LEFT; - } - - rt_mq_send(&mq, &msg, sizeof(msg)); - - /* wait next key press */ - rt_thread_delay(next_delay); - } + extern struct rt_messagequeue mq; + rt_time_t next_delay; + struct lcd_msg msg; + msg.type = KEY_MSG; + + key_io_init(); + + while (1) + { + msg.key = NO_KEY; + + next_delay = RT_TICK_PER_SECOND/10; + + if (KEY_ENTER_GETVALUE() == 0 ) + { + msg.key = KEY_ENTER; + } + + if (KEY_DOWN_GETVALUE() == 0) + { + msg.key = KEY_DOWN; + } + + if (KEY_UP_GETVALUE() == 0) + { + msg.key = KEY_UP; + } + + if (KEY_RIGHT_GETVALUE() == 0) + { + msg.key = KEY_RIGHT; + } + + if (KEY_LEFT_GETVALUE() == 0) + { + msg.key = KEY_LEFT; + } + + rt_mq_send(&mq, &msg, sizeof(msg)); + + /* wait next key press */ + rt_thread_delay(next_delay); + } #endif } @@ -159,6 +155,6 @@ static rt_thread_t key_thread; void rt_hw_key_init(void) { key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5); - if (key_thread != RT_NULL) + if (key_thread != RT_NULL) rt_thread_startup(key_thread); } diff --git a/bsp/mb9bf500r/key.h b/bsp/mb9bf500r/key.h index edabf1dffb..45c044c7c0 100644 --- a/bsp/mb9bf500r/key.h +++ b/bsp/mb9bf500r/key.h @@ -1,11 +1,7 @@ /* - * File : key.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf500r/lcd.c b/bsp/mb9bf500r/lcd.c index db2f272a8a..8b61abf2e0 100644 --- a/bsp/mb9bf500r/lcd.c +++ b/bsp/mb9bf500r/lcd.c @@ -1,11 +1,7 @@ /* - * File : lcd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -59,7 +55,7 @@ void lcd_write_cmd(unsigned char command) LCD_DATA_HIGH(); else LCD_DATA_LOW(); - + LCD_CLK_LOW(); delay(); LCD_CLK_HIGH(); @@ -81,7 +77,7 @@ void lcd_write_data(unsigned char data) LCD_DATA_HIGH(); else LCD_DATA_LOW(); - + LCD_CLK_LOW(); delay(); LCD_CLK_HIGH(); @@ -97,12 +93,12 @@ void lcd_write_data(unsigned char data) static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info) { rt_uint8_t i,j = GUI_LCM_XMAX; - rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; - + rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; + for (i=0; i> 4; - - lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. - lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr + + lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. + lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr lcd_write_cmd(SET_COLL_ADDR_0 | coll); lcd_write_data(gui_disp_buf[page][x]); } /**************************************************************************** * Function Name : LCD_PutChar -* Description : output a char to screen +* Description : output a char to screen (the char only can be ' ','0'~'9','A'~'Z','a'~'z') * Input : x X-coordinate y Y-coordinate @@ -363,13 +359,13 @@ void LCD_UpdatePoint(unsigned int x, unsigned int y) 0 Fail ****************************************************************************/ unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) -{ +{ unsigned char data; unsigned char i, j; if( x >=(GUI_LCM_XMAX-8) ) return(0); if( y >=(GUI_LCM_YMAX-8) ) return(0); - + if(ch == 0x20) ch -= 0x20; else if((ch >= 0x30)&&(ch <= 0x39)) @@ -380,30 +376,30 @@ unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) ch -= 0x3C; else return(0); - + for(i = 0; i < 8; i++) - { + { data = FONTTYPE8_8[ch][i]; - + for(j = 0; j < 8; j++) - { + { if( (data&BIT_MASK[j]) == 0) gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8))); - else + else gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8)); LCD_UpdatePoint(x, y); x ++; } - x -= 8; - y++; + x -= 8; + y++; } - + return(1); } /**************************************************************************** * Function Name : LCD_PutString -* Description : output string to screen +* Description : output string to screen * Input : x X-coordinate y Y-coordinate str pointer to string @@ -411,32 +407,32 @@ unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) * Return : None ****************************************************************************/ void LCD_PutString(unsigned long x, unsigned long y, char *str) -{ +{ while(1) - { + { if( (*str)=='\0' ) break; if( LCD_PutChar(x, y, *str++) == 0 ) break; - x += 6; + x += 6; } } static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) { - switch (cmd) - { -#ifdef RT_USING_RTGUI - case RTGRAPHIC_CTRL_RECT_UPDATE: - rt_hw_lcd_update(args); - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; + switch (cmd) + { +#ifdef RT_USING_RTGUI + case RTGRAPHIC_CTRL_RECT_UPDATE: + rt_hw_lcd_update(args); + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; #else case RT_DEVICE_CTRL_LCD_DISPLAY_ON: lcd_write_cmd(DISPLAY_ON); @@ -450,32 +446,32 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_LCD_CLEAR_SCR: LCD_ClearSCR(); break; -#endif - } +#endif + } - return RT_EOK; + return RT_EOK; } void rt_hw_lcd_init(void) { - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = RT_NULL; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + _lcd_info.framebuffer = RT_NULL; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; #ifdef RT_USING_RTGUI - lcd->user_data = (void*)&_lcd_ops; -#endif - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); + lcd->user_data = (void*)&_lcd_ops; +#endif + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); } diff --git a/bsp/mb9bf500r/lcd.h b/bsp/mb9bf500r/lcd.h index 8c0462d6e3..e0fa9efdc3 100644 --- a/bsp/mb9bf500r/lcd.h +++ b/bsp/mb9bf500r/lcd.h @@ -1,11 +1,7 @@ /* - * File : lcd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -19,166 +15,166 @@ #include "mb9bf506r.h" /********* LCD Hardward Interface ************* -LCD_CS PORT1.7 -LCD_CD PORT1.6 -LCD_WR PORT1.5 -LCD_RD PORT1.4 -LCD_SCK PORT1.3 -LCD_MOSI PORT1.2 -LCD_C86 PORT1.1 -LCD_PS PORT1.0 -LCD_DATA[0..7] PORT5.[0..7] +LCD_CS PORT1.7 +LCD_CD PORT1.6 +LCD_WR PORT1.5 +LCD_RD PORT1.4 +LCD_SCK PORT1.3 +LCD_MOSI PORT1.2 +LCD_C86 PORT1.1 +LCD_PS PORT1.0 +LCD_DATA[0..7] PORT5.[0..7] ***********************************************/ -#define LCD_CS (1UL << 7) -#define LCD_CS_DDR (FM3_GPIO->DDR1) -#define LCD_CS_PFR (FM3_GPIO->PFR1) -#define LCD_CS_PDOR (FM3_GPIO->PDOR1) +#define LCD_CS (1UL << 7) +#define LCD_CS_DDR (FM3_GPIO->DDR1) +#define LCD_CS_PFR (FM3_GPIO->PFR1) +#define LCD_CS_PDOR (FM3_GPIO->PDOR1) -#define LCD_CD (1UL << 6) -#define LCD_CD_DDR (FM3_GPIO->DDR1) -#define LCD_CD_PFR (FM3_GPIO->PFR1) -#define LCD_CD_PDOR (FM3_GPIO->PDOR1) +#define LCD_CD (1UL << 6) +#define LCD_CD_DDR (FM3_GPIO->DDR1) +#define LCD_CD_PFR (FM3_GPIO->PFR1) +#define LCD_CD_PDOR (FM3_GPIO->PDOR1) -#define LCD_PS (1UL << 0) -#define LCD_PS_DDR (FM3_GPIO->DDR1) -#define LCD_PS_PFR (FM3_GPIO->PFR1) -#define LCD_PS_PDOR (FM3_GPIO->PDOR1) +#define LCD_PS (1UL << 0) +#define LCD_PS_DDR (FM3_GPIO->DDR1) +#define LCD_PS_PFR (FM3_GPIO->PFR1) +#define LCD_PS_PDOR (FM3_GPIO->PDOR1) -#define LCD_CLK (1UL << 6) -#define LCD_CLK_DDR (FM3_GPIO->DDR5) -#define LCD_CLK_PFR (FM3_GPIO->PFR5) -#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) +#define LCD_CLK (1UL << 6) +#define LCD_CLK_DDR (FM3_GPIO->DDR5) +#define LCD_CLK_PFR (FM3_GPIO->PFR5) +#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) -#define LCD_DATA (1UL << 7) -#define LCD_DATA_DDR (FM3_GPIO->DDR5) -#define LCD_DATA_PFR (FM3_GPIO->PFR5) -#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) +#define LCD_DATA (1UL << 7) +#define LCD_DATA_DDR (FM3_GPIO->DDR5) +#define LCD_DATA_PFR (FM3_GPIO->PFR5) +#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) /* LCD driver for ZYMG12864C3 */ -#define LCD_WIDTH 128 -#define LCD_HEIGHT 64 +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 // Driver the LCD with Parallel or serial interface and the command/data control pin is gpio -#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS -#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS +#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS +#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS -#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD -#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD +#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD +#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD -#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS -#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS +#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS +#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS -#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK -#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK +#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK +#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK -#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA -#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA +#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA +#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA // define the arrtibute of ZYMG12864(LCM) -#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 -#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 -#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) +#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 +#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 +#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) /* set LCD command */ -#define DISPLAY_ON 0xAF // A0,RD,WR:010 -#define DISPLAY_OFF 0xAE // A0,RD,WR:010 +#define DISPLAY_ON 0xAF // A0,RD,WR:010 +#define DISPLAY_OFF 0xAE // A0,RD,WR:010 -#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 -#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 -#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; -#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 +#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 +#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 +#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; +#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 -#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 -#define STATUS_BUSY 0x80 -#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n -#define STATUS_DISPLAY_OFF 0x20 -#define STATUS_RESET 0x80 +#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 +#define STATUS_BUSY 0x80 +#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n +#define STATUS_DISPLAY_OFF 0x20 +#define STATUS_RESET 0x80 -#define WRITE_DATA 0x-- // A0,RD,WR:110 -#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable +#define WRITE_DATA 0x-- // A0,RD,WR:110 +#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable -#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 -#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 -#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 -#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color -#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 -#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 +#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 +#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 +#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 +#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color +#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 +#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 /************************************************************* -* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* ---------------|----------|----------|----------|--------- * -* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * -* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * +* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* ---------------|----------|----------|----------|--------- * +* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * +* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * **************************************************************/ -#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 -#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 +#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 +#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 -#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating -#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. -#define RESET_LCD 0xE2 // A0,RD,WR:010 +#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating +#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. +#define RESET_LCD 0xE2 // A0,RD,WR:010 /************************************************************************************** -* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* --------------|-------------|-------------|-------------|------------------------ * -* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * -* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * +* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* --------------|-------------|-------------|-------------|------------------------ * +* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * +* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * ***************************************************************************************/ -#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 -#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 +#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 +#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 // 0 0 1 0 1 | Booster On | Regulator On | Follower On -#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 -#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 -#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 +#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 +#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 +#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 -#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large +#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large -#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command -#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. +#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command +#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. -#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command -#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command -#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command +#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command +#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command +#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command -#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command -#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command -#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command -#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command +#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command +#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command +#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command +#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command -#define COMMAND_NOP 0xE3 // A0,RD,WR:010 -#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use +#define COMMAND_NOP 0xE3 // A0,RD,WR:010 +#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use -#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 -#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 -#define RT_DEVICE_CTRL_LCD_GET_BPP 2 -#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 -#define RT_DEVICE_CTRL_LCD_POWER_ON 4 -#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 -#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 -#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 -#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 -#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 -#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 -#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 +#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 +#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 +#define RT_DEVICE_CTRL_LCD_GET_BPP 2 +#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 +#define RT_DEVICE_CTRL_LCD_POWER_ON 4 +#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 +#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 +#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 +#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 +#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 +#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 +#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 -enum +enum { - ADC_MSG, - KEY_MSG, - CPU_MSG, - MAX_MSG, + ADC_MSG, + KEY_MSG, + CPU_MSG, + MAX_MSG, }; struct lcd_msg { - rt_uint8_t type; - rt_uint16_t adc_value; - rt_uint8_t key; - rt_uint16_t major; - rt_uint16_t minor; + rt_uint8_t type; + rt_uint16_t adc_value; + rt_uint8_t key; + rt_uint16_t major; + rt_uint16_t minor; }; extern rt_uint32_t x; diff --git a/bsp/mb9bf500r/led.c b/bsp/mb9bf500r/led.c index 72c01b4507..ee28af7035 100644 --- a/bsp/mb9bf500r/led.c +++ b/bsp/mb9bf500r/led.c @@ -1,17 +1,13 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #include #include @@ -20,8 +16,8 @@ void rt_hw_led_on(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -31,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num) LED_PDOR &= ~LED2; break; case 3: - LED_PDOR &= ~LED3; + LED_PDOR &= ~LED3; break; default: break; - } + } } void rt_hw_led_off(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); + RT_ASSERT(num < LEDS_MAX_NUMBER); switch (num) { @@ -51,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num) LED_PDOR |= LED2; break; case 3: - LED_PDOR |= LED3; + LED_PDOR |= LED3; break; default: break; - } + } } void rt_hw_led_toggle(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -80,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num) if (LED_PDOR&LED3) LED_PDOR &= ~LED3; else - LED_PDOR |= LED3; + LED_PDOR |= LED3; break; default: break; - } + } } static rt_err_t led_io_init(void) @@ -95,23 +91,23 @@ static rt_err_t led_io_init(void) LED_PDOR |= LED_MASK; /*Make led pins outputs*/ LED_DDR |= LED_MASK; - + //LED3 is controled by PWM FM3_GPIO->PFR3 = 0x1000; FM3_GPIO->EPFR04 = 0x00080000; FM3_BT2_PWM->TMCR = 0x0018; - FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ + FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ FM3_BT2_PWM->STC = 0x00; - FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ - FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ - - FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ + FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ + FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ + + FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ return RT_EOK; } void pwm_update(rt_uint16_t value) { - FM3_BT2_PWM->PDUT = value; + FM3_BT2_PWM->PDUT = value; } static void led1_thread_entry(void *parameter) @@ -139,11 +135,11 @@ void rt_hw_led_init(void) led_io_init(); led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) + if (led1_thread != RT_NULL) rt_thread_startup(led1_thread); - + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) + if (led2_thread != RT_NULL) rt_thread_startup(led2_thread); } diff --git a/bsp/mb9bf500r/led.h b/bsp/mb9bf500r/led.h index 6dd71c0d95..c4a433cb81 100644 --- a/bsp/mb9bf500r/led.h +++ b/bsp/mb9bf500r/led.h @@ -1,23 +1,19 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __LED_H__ #define __LED_H__ #include "mb9bf506r.h" -#define LEDS_MAX_NUMBER 4 +#define LEDS_MAX_NUMBER 4 /*LEDs*/ #define LED1 (1UL<<10) @@ -29,9 +25,9 @@ #define LED_DDR (FM3_GPIO->DDR3) #define LED_PDOR (FM3_GPIO->PDOR3) -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 void rt_hw_led_init(void); void rt_hw_led_on(rt_uint8_t num); diff --git a/bsp/mb9bf500r/rtconfig.h b/bsp/mb9bf500r/rtconfig.h index cb2c62fccd..ac37ecb464 100644 --- a/bsp/mb9bf500r/rtconfig.h +++ b/bsp/mb9bf500r/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -53,20 +53,20 @@ #define RT_USING_DEVICE /* RT_USING_UART */ #define RT_USING_UART0 -#define RT_UART_RX_BUFFER_SIZE 64 +#define RT_UART_RX_BUFFER_SIZE 64 /* SECTION: Console options */ #define RT_TINY_SIZE #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: RTGUI support */ /* using RTGUI support */ /* #define RT_USING_RTGUI */ /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 +#define RTGUI_NAME_MAX 16 /* support 16 weight font */ //#define RTGUI_USING_FONT16 /* support 12 weight font */ diff --git a/bsp/mb9bf500r/startup.c b/bsp/mb9bf500r/startup.c index a8718750fc..1e7309ae3e 100644 --- a/bsp/mb9bf500r/startup.c +++ b/bsp/mb9bf500r/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -38,57 +34,57 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* init board */ - rt_hw_board_init(); + /* init board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* init timer system */ - rt_system_timer_init(); + /* init timer system */ + rt_system_timer_init(); #ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); - /* init application */ - rt_application_init(); + /* init application */ + rt_application_init(); /* init timer thread */ rt_system_timer_thread_init(); - /* init idle thread */ - rt_thread_idle_init(); + /* init idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* init system setting */ - SystemInit(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* init system setting */ + SystemInit(); - return 0; + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/applications/application.c b/bsp/mb9bf506r/applications/application.c index ce1daa2327..fdc42a9100 100644 --- a/bsp/mb9bf506r/applications/application.c +++ b/bsp/mb9bf506r/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,35 +29,35 @@ void rt_init_thread_entry(void *parameter) { - /* LED Initialization */ - rt_hw_led_init(); + /* LED Initialization */ + rt_hw_led_init(); #ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); + /* initialization RT-Thread Components */ + rt_components_init(); #endif - /* Filesystem Initialization */ + /* Filesystem Initialization */ #ifdef RT_USING_DFS - /* mount nand fat partition 1 as root directory */ - if (dfs_mount("nand", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); + /* mount nand fat partition 1 as root directory */ + if (dfs_mount("nand", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); #endif } int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) - rt_thread_startup(tid); + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) + rt_thread_startup(tid); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c index 9076d572d6..ccb31d40b4 100644 --- a/bsp/mb9bf506r/applications/startup.c +++ b/bsp/mb9bf506r/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -38,60 +34,60 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE #if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS) - rt_hw_nand_init(); + rt_hw_nand_init(); #endif #endif - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); - /* initialize timer thread */ - rt_system_timer_thread_init(); + /* initialize timer thread */ + rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/drivers/board.c b/bsp/mb9bf506r/drivers/board.c index 89d42c6329..d687bea929 100644 --- a/bsp/mb9bf506r/drivers/board.c +++ b/bsp/mb9bf506r/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,13 +28,13 @@ */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** @@ -46,16 +42,16 @@ void SysTick_Handler(void) */ void rt_hw_board_init(void) { - /* init systick */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - - /* initialize nand flash device */ - rt_hw_nand_init(); + /* init systick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + /* initialize nand flash device */ + rt_hw_nand_init(); } /*@}*/ diff --git a/bsp/mb9bf506r/drivers/board.h b/bsp/mb9bf506r/drivers/board.h index 960dac022b..d2f252990c 100644 --- a/bsp/mb9bf506r/drivers/board.h +++ b/bsp/mb9bf506r/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf506r/drivers/fm3_uart.c b/bsp/mb9bf506r/drivers/fm3_uart.c index 2c82afd288..ece042cca4 100644 --- a/bsp/mb9bf506r/drivers/fm3_uart.c +++ b/bsp/mb9bf506r/drivers/fm3_uart.c @@ -1,12 +1,7 @@ /* - * File : fm3_uart.c - * mb9bf506r uart driver - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,19 +17,19 @@ /* UART0 device driver structure */ struct uart03_device uart0 = { - FM3_MFS0_UART, - MFS0RX_IRQn, - MFS0TX_IRQn, + FM3_MFS0_UART, + MFS0RX_IRQn, + MFS0TX_IRQn, }; struct rt_serial_device serial0; void MFS0RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -42,19 +37,19 @@ void MFS0RX_IRQHandler(void) /* UART1 device driver structure */ struct uart03_device uart1 = { - FM3_MFS1_UART, - MFS1RX_IRQn, - MFS1TX_IRQn, + FM3_MFS1_UART, + MFS1RX_IRQn, + MFS1TX_IRQn, }; struct rt_serial_device serial1; void MFS1RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -62,19 +57,19 @@ void MFS1RX_IRQHandler(void) /* UART2 device driver structure */ struct uart03_device uart2 = { - FM3_MFS2_UART, - MFS2RX_IRQn, - MFS2TX_IRQn, + FM3_MFS2_UART, + MFS2RX_IRQn, + MFS2TX_IRQn, }; struct rt_serial_device serial2; void MFS2RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -82,19 +77,19 @@ void MFS2RX_IRQHandler(void) /* UART3 device driver structure */ struct uart03_device uart3 = { - FM3_MFS3_UART, - MFS3RX_IRQn, - MFS3TX_IRQn, + FM3_MFS3_UART, + MFS3RX_IRQn, + MFS3TX_IRQn, }; struct rt_serial_device serial3; void MFS3RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -102,20 +97,20 @@ void MFS3RX_IRQHandler(void) /* UART4 device driver structure */ struct uart47_device uart4 = { - FM3_MFS4_UART, - MFS4RX_IRQn, - MFS4TX_IRQn, - FIFO_SIZE, + FM3_MFS4_UART, + MFS4RX_IRQn, + MFS4TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial4; void MFS4RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -123,20 +118,20 @@ void MFS4RX_IRQHandler(void) /* UART5 device driver structure */ struct uart47_device uart5 = { - FM3_MFS5_UART, - MFS5RX_IRQn, - MFS5TX_IRQn, - FIFO_SIZE, + FM3_MFS5_UART, + MFS5RX_IRQn, + MFS5TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial5; void MFS5RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -144,20 +139,20 @@ void MFS5RX_IRQHandler(void) /* UART6 device driver structure */ struct uart47_device uart6 = { - FM3_MFS6_UART, - MFS6RX_IRQn, - MFS6TX_IRQn, - FIFO_SIZE, + FM3_MFS6_UART, + MFS6RX_IRQn, + MFS6TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial6; void MFS6RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -165,20 +160,20 @@ void MFS6RX_IRQHandler(void) /* UART7 device driver structure */ struct uart47_device uart7 = { - FM3_MFS7_UART, - MFS7RX_IRQn, - MFS7TX_IRQn, - FIFO_SIZE, + FM3_MFS7_UART, + MFS7RX_IRQn, + MFS7TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial7; void MFS7RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -186,749 +181,749 @@ void MFS7RX_IRQHandler(void) void uart_pin_setup(void) { #if defined(RT_USING_UART0_0) - /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ - FM3_GPIO->PFR2_f.P1 = 1; - FM3_GPIO->PFR2_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 1; - FM3_GPIO->EPFR07_f.SIN0S1 = 0; - FM3_GPIO->EPFR07_f.SOT0B0 = 1; - FM3_GPIO->EPFR07_f.SOT0B1 = 0; + /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ + FM3_GPIO->PFR2_f.P1 = 1; + FM3_GPIO->PFR2_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 1; + FM3_GPIO->EPFR07_f.SIN0S1 = 0; + FM3_GPIO->EPFR07_f.SOT0B0 = 1; + FM3_GPIO->EPFR07_f.SOT0B1 = 0; #elif defined(RT_USING_UART0_1) - /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ - FM3_GPIO->PFR1_f.P4 = 1; - FM3_GPIO->PFR1_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 0; - FM3_GPIO->EPFR07_f.SIN0S1 = 1; - FM3_GPIO->EPFR07_f.SOT0B0 = 0; - FM3_GPIO->EPFR07_f.SOT0B1 = 1; + /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ + FM3_GPIO->PFR1_f.P4 = 1; + FM3_GPIO->PFR1_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 0; + FM3_GPIO->EPFR07_f.SIN0S1 = 1; + FM3_GPIO->EPFR07_f.SOT0B0 = 0; + FM3_GPIO->EPFR07_f.SOT0B1 = 1; #endif #if defined(RT_USING_UART1_0) - /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ - FM3_GPIO->PFR5_f.P6 = 1; - FM3_GPIO->PFR5_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 1; - FM3_GPIO->EPFR07_f.SIN1S1 = 0; - FM3_GPIO->EPFR07_f.SOT1B0 = 1; - FM3_GPIO->EPFR07_f.SOT1B1 = 0; + /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ + FM3_GPIO->PFR5_f.P6 = 1; + FM3_GPIO->PFR5_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 1; + FM3_GPIO->EPFR07_f.SIN1S1 = 0; + FM3_GPIO->EPFR07_f.SOT1B0 = 1; + FM3_GPIO->EPFR07_f.SOT1B1 = 0; #elif defined(RT_USING_UART1_1) - /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ - FM3_GPIO->PFR1_f.P1 = 1; - FM3_GPIO->PFR1_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 0; - FM3_GPIO->EPFR07_f.SIN1S1 = 1; - FM3_GPIO->EPFR07_f.SOT1B0 = 0; - FM3_GPIO->EPFR07_f.SOT1B1 = 1; + /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ + FM3_GPIO->PFR1_f.P1 = 1; + FM3_GPIO->PFR1_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 0; + FM3_GPIO->EPFR07_f.SIN1S1 = 1; + FM3_GPIO->EPFR07_f.SOT1B0 = 0; + FM3_GPIO->EPFR07_f.SOT1B1 = 1; #endif #if defined(RT_USING_UART2_0) - /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ - FM3_GPIO->PFR7_f.P2 = 1; - FM3_GPIO->PFR7_f.P3 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 0; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 0; + /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ + FM3_GPIO->PFR7_f.P2 = 1; + FM3_GPIO->PFR7_f.P3 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 0; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 0; #elif defined(RT_USING_UART2_1) - /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ - FM3_GPIO->PFR2_f.P4 = 1; - FM3_GPIO->PFR2_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 0; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 0; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; + /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ + FM3_GPIO->PFR2_f.P4 = 1; + FM3_GPIO->PFR2_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 0; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 0; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; #elif defined(RT_USING_UART2_2) - /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ - FM3_GPIO->PFR1_f.P7 = 1; - FM3_GPIO->PFR1_f.P8 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; + /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ + FM3_GPIO->PFR1_f.P7 = 1; + FM3_GPIO->PFR1_f.P8 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; #endif #if defined(RT_USING_UART3_0) - /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ - FM3_GPIO->PFR6_f.P6 = 1; - FM3_GPIO->PFR6_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 0; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 0; + /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ + FM3_GPIO->PFR6_f.P6 = 1; + FM3_GPIO->PFR6_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 0; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 0; #elif defined(RT_USING_UART3_1) - /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ - FM3_GPIO->PFR5_f.P0 = 1; - FM3_GPIO->PFR5_f.P1 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 0; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 0; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; + /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ + FM3_GPIO->PFR5_f.P0 = 1; + FM3_GPIO->PFR5_f.P1 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 0; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 0; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; #elif defined(RT_USING_UART3_2) - /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ - FM3_GPIO->PFR4_f.P8 = 1; - FM3_GPIO->PFR4_f.P9 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; + /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ + FM3_GPIO->PFR4_f.P8 = 1; + FM3_GPIO->PFR4_f.P9 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; #endif #if defined(RT_USING_UART4_0) - /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ - FM3_GPIO->PFR0_f.PA = 1; - FM3_GPIO->PFR0_f.PB = 1; - FM3_GPIO->PFR0_f.PD = 1; - FM3_GPIO->PFR0_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 0; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 0; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 0; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 0; + /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ + FM3_GPIO->PFR0_f.PA = 1; + FM3_GPIO->PFR0_f.PB = 1; + FM3_GPIO->PFR0_f.PD = 1; + FM3_GPIO->PFR0_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 0; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 0; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 0; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 0; #elif defined(RT_USING_UART4_1) - /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ - FM3_GPIO->PFR1_f.PA = 1; - FM3_GPIO->PFR1_f.PB = 1; - FM3_GPIO->PFR1_f.PD = 1; - FM3_GPIO->PFR1_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 0; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 0; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 0; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 0; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; + /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ + FM3_GPIO->PFR1_f.PA = 1; + FM3_GPIO->PFR1_f.PB = 1; + FM3_GPIO->PFR1_f.PD = 1; + FM3_GPIO->PFR1_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 0; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 0; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 0; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 0; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; #elif defined(RT_USING_UART4_2) - /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ - FM3_GPIO->PFR0_f.P5 = 1; - FM3_GPIO->PFR0_f.P6 = 1; - FM3_GPIO->PFR0_f.P8 = 1; - FM3_GPIO->PFR0_f.P9 = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; + /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ + FM3_GPIO->PFR0_f.P5 = 1; + FM3_GPIO->PFR0_f.P6 = 1; + FM3_GPIO->PFR0_f.P8 = 1; + FM3_GPIO->PFR0_f.P9 = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; #endif #if defined(RT_USING_UART5_0) - /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ - FM3_GPIO->PFR6_f.P0 = 1; - FM3_GPIO->PFR6_f.P1 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 0; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 0; + /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ + FM3_GPIO->PFR6_f.P0 = 1; + FM3_GPIO->PFR6_f.P1 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 0; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 0; #elif defined(RT_USING_UART5_1) - /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ - FM3_GPIO->PFR6_f.P3 = 1; - FM3_GPIO->PFR6_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 0; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 0; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; + /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ + FM3_GPIO->PFR6_f.P3 = 1; + FM3_GPIO->PFR6_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 0; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 0; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; #elif defined(RT_USING_UART5_2) - /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ - FM3_GPIO->PFR3_f.P6 = 1; - FM3_GPIO->PFR3_f.P7 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; + /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ + FM3_GPIO->PFR3_f.P6 = 1; + FM3_GPIO->PFR3_f.P7 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; #endif #if defined(RT_USING_UART6_0) - /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ - FM3_GPIO->PFR5_f.P3 = 1; - FM3_GPIO->PFR5_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 1; - FM3_GPIO->EPFR08_f.SIN6S1 = 0; - FM3_GPIO->EPFR08_f.SOT6B0 = 1; - FM3_GPIO->EPFR08_f.SOT6B1 = 0; + /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ + FM3_GPIO->PFR5_f.P3 = 1; + FM3_GPIO->PFR5_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 1; + FM3_GPIO->EPFR08_f.SIN6S1 = 0; + FM3_GPIO->EPFR08_f.SOT6B0 = 1; + FM3_GPIO->EPFR08_f.SOT6B1 = 0; #elif defined(RT_USING_UART6_1) - /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ - FM3_GPIO->PFR3_f.P2 = 1; - FM3_GPIO->PFR3_f.P3 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 0; - FM3_GPIO->EPFR08_f.SIN6S1 = 1; - FM3_GPIO->EPFR08_f.SOT6B0 = 0; - FM3_GPIO->EPFR08_f.SOT6B1 = 1; + /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ + FM3_GPIO->PFR3_f.P2 = 1; + FM3_GPIO->PFR3_f.P3 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 0; + FM3_GPIO->EPFR08_f.SIN6S1 = 1; + FM3_GPIO->EPFR08_f.SOT6B0 = 0; + FM3_GPIO->EPFR08_f.SOT6B1 = 1; #endif #if defined(RT_USING_UART7_0) - /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ - FM3_GPIO->PFR5_f.P9 = 1; - FM3_GPIO->PFR5_f.PA = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 1; - FM3_GPIO->EPFR08_f.SIN7S1 = 0; - FM3_GPIO->EPFR08_f.SOT7B0 = 1; - FM3_GPIO->EPFR08_f.SOT7B1 = 0; + /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ + FM3_GPIO->PFR5_f.P9 = 1; + FM3_GPIO->PFR5_f.PA = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 1; + FM3_GPIO->EPFR08_f.SIN7S1 = 0; + FM3_GPIO->EPFR08_f.SOT7B0 = 1; + FM3_GPIO->EPFR08_f.SOT7B1 = 0; #elif defined(RT_USING_UART7_1) - /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ - FM3_GPIO->PFR4_f.PD = 1; - FM3_GPIO->PFR4_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 0; - FM3_GPIO->EPFR08_f.SIN7S1 = 1; - FM3_GPIO->EPFR08_f.SOT7B0 = 0; - FM3_GPIO->EPFR08_f.SOT7B1 = 1; + /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ + FM3_GPIO->PFR4_f.PD = 1; + FM3_GPIO->PFR4_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 0; + FM3_GPIO->EPFR08_f.SIN7S1 = 1; + FM3_GPIO->EPFR08_f.SOT7B0 = 0; + FM3_GPIO->EPFR08_f.SOT7B1 = 1; #endif } static rt_err_t uart03_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct uart03_device *uart; + struct uart03_device *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - uart = (struct uart03_device *)serial->parent.user_data; + uart = (struct uart03_device *)serial->parent.user_data; - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } - return RT_EOK; + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; } - + static rt_err_t uart03_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct uart03_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } + struct uart03_device *uart; - return (RT_EOK); + RT_ASSERT(serial != RT_NULL); + uart = (struct uart03_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); } - + static int uart03_putc(struct rt_serial_device *serial, char c) { - struct uart03_device *uart; + struct uart03_device *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* while send buffer is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to send buffer */ - uart->uart_regs->TDR = c; + RT_ASSERT(serial != RT_NULL); - return (1); + uart = (struct uart03_device *)serial->parent.user_data; + /* while send buffer is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to send buffer */ + uart->uart_regs->TDR = c; + + return (1); } static int uart03_getc(struct rt_serial_device *serial) -{ - struct uart03_device *uart; - int ch; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* receive buffer is full */ - if (uart->uart_regs->SSR & SSR_RDRF) - { - ch = uart->uart_regs->RDR & 0xff; - return (ch); - } - else - return (-1); +{ + struct uart03_device *uart; + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + /* receive buffer is full */ + if (uart->uart_regs->SSR & SSR_RDRF) + { + ch = uart->uart_regs->RDR & 0xff; + return (ch); + } + else + return (-1); } static struct rt_uart_ops uart03_ops = { - uart03_configure, - uart03_control, - uart03_putc, - uart03_getc, + uart03_configure, + uart03_control, + uart03_putc, + uart03_getc, }; static rt_err_t uart47_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct uart47_device *uart; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - uart = (struct uart47_device *)serial->parent.user_data; + uart = (struct uart47_device *)serial->parent.user_data; - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - /* configure fifo */ - /* Disable the Data Lost detection */ - uart->uart_regs->FCR1_f.FLSTE = 0; - /* Enable the received FIFO idle detection */ - uart->uart_regs->FCR1_f.FRIE = 1; - /* Requests for the transmit FIFO data */ - uart->uart_regs->FCR1_f.FDRQ = 1; - /* Disable the transmit FIFO interrupt */ - uart->uart_regs->FCR1_f.FTIE = 0; - /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ - uart->uart_regs->FCR1_f.FSEL = 0; + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } - /* Transfer data count */ - uart->uart_regs->FBYTE1 = 0; - /* Set the data count to generate a received interrupt */ - uart->uart_regs->FBYTE2 = uart->fifo_size; + /* configure fifo */ + /* Disable the Data Lost detection */ + uart->uart_regs->FCR1_f.FLSTE = 0; + /* Enable the received FIFO idle detection */ + uart->uart_regs->FCR1_f.FRIE = 1; + /* Requests for the transmit FIFO data */ + uart->uart_regs->FCR1_f.FDRQ = 1; + /* Disable the transmit FIFO interrupt */ + uart->uart_regs->FCR1_f.FTIE = 0; + /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ + uart->uart_regs->FCR1_f.FSEL = 0; - /* FIFO pointer Not reloaded */ - uart->uart_regs->FCR0_f.FLD = 0; - /* FIFO pointer Not saved */ - uart->uart_regs->FCR0_f.FSET = 0; - /* FIFO2 is reset */ - uart->uart_regs->FCR0_f.FCL2 = 1; - /* FIFO1 is reset */ - uart->uart_regs->FCR0_f.FCL1 = 1; - /* Enables the FIFO2 operation */ - uart->uart_regs->FCR0_f.FE2 = 1; - /* Enables the FIFO1 operation */ - uart->uart_regs->FCR0_f.FE1 = 1; - - /* enable receive and send */ - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + /* Transfer data count */ + uart->uart_regs->FBYTE1 = 0; + /* Set the data count to generate a received interrupt */ + uart->uart_regs->FBYTE2 = uart->fifo_size; - return RT_EOK; + /* FIFO pointer Not reloaded */ + uart->uart_regs->FCR0_f.FLD = 0; + /* FIFO pointer Not saved */ + uart->uart_regs->FCR0_f.FSET = 0; + /* FIFO2 is reset */ + uart->uart_regs->FCR0_f.FCL2 = 1; + /* FIFO1 is reset */ + uart->uart_regs->FCR0_f.FCL1 = 1; + /* Enables the FIFO2 operation */ + uart->uart_regs->FCR0_f.FE2 = 1; + /* Enables the FIFO1 operation */ + uart->uart_regs->FCR0_f.FE1 = 1; + + /* enable receive and send */ + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; } static rt_err_t uart47_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct uart47_device *uart; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct uart47_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } + RT_ASSERT(serial != RT_NULL); + uart = (struct uart47_device *)serial->parent.user_data; - return (RT_EOK); + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); } static int uart47_putc(struct rt_serial_device *serial, char c) { - struct uart47_device *uart; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; + RT_ASSERT(serial != RT_NULL); - /* while send fifo is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to fifo */ - uart->uart_regs->TDR = c; + uart = (struct uart47_device *)serial->parent.user_data; - return (1); + /* while send fifo is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to fifo */ + uart->uart_regs->TDR = c; + + return (1); } static int uart47_getc(struct rt_serial_device *serial) -{ - int ch; - struct uart47_device *uart; +{ + int ch; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - /* receive is disabled */ - if (!(uart->uart_regs->SCR & SCR_RXE)) - return (-1); + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + /* receive is disabled */ + if (!(uart->uart_regs->SCR & SCR_RXE)) + return (-1); /* receive fifo is not full */ - if ((uart->uart_regs->SSR & SSR_RDRF) == 0) - return (-1); - /* read char */ - ch = uart->uart_regs->RDR & 0xff; - - return (ch); + if ((uart->uart_regs->SSR & SSR_RDRF) == 0) + return (-1); + /* read char */ + ch = uart->uart_regs->RDR & 0xff; + + return (ch); } static struct rt_uart_ops uart47_ops = { - uart47_configure, - uart47_control, - uart47_putc, - uart47_getc, + uart47_configure, + uart47_control, + uart47_putc, + uart47_getc, }; void rt_hw_serial_init(void) { - struct serial_configure config; + struct serial_configure config; - uart_pin_setup(); + uart_pin_setup(); #if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial0.ops = &uart03_ops; - serial0.config = config; + serial0.ops = &uart03_ops; + serial0.config = config; - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); #endif #if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial1.ops = &uart03_ops; - serial1.config = config; + serial1.ops = &uart03_ops; + serial1.config = config; - /* register UART1 device */ - rt_hw_serial_register(&serial1, - "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart1); + /* register UART1 device */ + rt_hw_serial_register(&serial1, + "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); #endif #if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial2.ops = &uart03_ops; - serial2.config = config; + serial2.ops = &uart03_ops; + serial2.config = config; - /* register UART2 device */ - rt_hw_serial_register(&serial2, - "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); + /* register UART2 device */ + rt_hw_serial_register(&serial2, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); #endif #if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial3.ops = &uart03_ops; - serial3.config = config; + serial3.ops = &uart03_ops; + serial3.config = config; - /* register UART3 device */ - rt_hw_serial_register(&serial3, - "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart3); + /* register UART3 device */ + rt_hw_serial_register(&serial3, + "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart3); #endif #if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial4.ops = &uart47_ops; - serial4.config = config; + serial4.ops = &uart47_ops; + serial4.config = config; - /* register UART4 device */ - rt_hw_serial_register(&serial4, - "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart4); + /* register UART4 device */ + rt_hw_serial_register(&serial4, + "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart4); #endif #if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial5.ops = &uart47_ops; - serial5.config = config; + serial5.ops = &uart47_ops; + serial5.config = config; - /* register UART5 device */ - rt_hw_serial_register(&serial5, - "uart5", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart5); + /* register UART5 device */ + rt_hw_serial_register(&serial5, + "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart5); #endif #if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial6.ops = &uart47_ops; - serial6.config = config; + serial6.ops = &uart47_ops; + serial6.config = config; - /* register UART6 device */ - rt_hw_serial_register(&serial6, - "uart6", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart6); + /* register UART6 device */ + rt_hw_serial_register(&serial6, + "uart6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart6); #endif #if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial7.ops = &uart47_ops; - serial7.config = config; + serial7.ops = &uart47_ops; + serial7.config = config; - /* register UART7 device */ - rt_hw_serial_register(&serial7, - "uart7", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart7); + /* register UART7 device */ + rt_hw_serial_register(&serial7, + "uart7", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart7); #endif } diff --git a/bsp/mb9bf506r/drivers/fm3_uart.h b/bsp/mb9bf506r/drivers/fm3_uart.h index f8698dbe17..824592c850 100644 --- a/bsp/mb9bf506r/drivers/fm3_uart.h +++ b/bsp/mb9bf506r/drivers/fm3_uart.h @@ -1,11 +1,7 @@ /* - * File : fm3_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -55,7 +51,7 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define FIFO_SIZE 16 +#define FIFO_SIZE 16 /* * Enable/DISABLE Interrupt Controller @@ -66,19 +62,19 @@ struct uart03_device { - FM3_MFS03_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; + FM3_MFS03_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; }; struct uart47_device { - FM3_MFS47_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; - rt_uint8_t fifo_size; + FM3_MFS47_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + rt_uint8_t fifo_size; }; void rt_hw_serial_init(void); diff --git a/bsp/mb9bf506r/drivers/led.c b/bsp/mb9bf506r/drivers/led.c index a1ab6a0592..3f6a11fcfe 100644 --- a/bsp/mb9bf506r/drivers/led.c +++ b/bsp/mb9bf506r/drivers/led.c @@ -1,17 +1,13 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #include #include @@ -20,8 +16,8 @@ void rt_hw_led_on(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -31,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num) USER_LED_PDOR &= ~USER_LED2; break; case 3: - USER_LED_PDOR &= ~USER_LED3; + USER_LED_PDOR &= ~USER_LED3; break; default: break; - } + } } void rt_hw_led_off(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); + RT_ASSERT(num < LEDS_MAX_NUMBER); switch (num) { @@ -51,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num) USER_LED_PDOR |= USER_LED2; break; case 3: - USER_LED_PDOR |= USER_LED3; + USER_LED_PDOR |= USER_LED3; break; default: break; - } + } } void rt_hw_led_toggle(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -80,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num) if (USER_LED_PDOR&USER_LED3) USER_LED_PDOR &= ~USER_LED3; else - USER_LED_PDOR |= USER_LED3; + USER_LED_PDOR |= USER_LED3; break; default: break; - } + } } void led_init(void) @@ -102,7 +98,7 @@ void led_init(void) void pwm_update(rt_uint16_t value) { - FM3_BT2_PWM->PDUT = value; + FM3_BT2_PWM->PDUT = value; } static void led1_thread_entry(void *parameter) @@ -130,11 +126,11 @@ void rt_hw_led_init(void) led_init(); led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) + if (led1_thread != RT_NULL) rt_thread_startup(led1_thread); - + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) + if (led2_thread != RT_NULL) rt_thread_startup(led2_thread); } diff --git a/bsp/mb9bf506r/drivers/led.h b/bsp/mb9bf506r/drivers/led.h index 5db0980520..bcbfaf9b62 100644 --- a/bsp/mb9bf506r/drivers/led.h +++ b/bsp/mb9bf506r/drivers/led.h @@ -1,38 +1,34 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __LED_H__ #define __LED_H__ #include "mb9bf506r.h" -#define LEDS_MAX_NUMBER 4 +#define LEDS_MAX_NUMBER 4 /* LED */ #define USER_LED1 (1UL<<0x9) #define USER_LED2 (1UL<<0xa) #define USER_LED3 (1UL<<0xb) -#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) -#define USER_LED_PFR FM3_GPIO->PFR1 -#define USER_LED_PCR FM3_GPIO->PCR1 -#define USER_LED_PDOR FM3_GPIO->PDOR1 -#define USER_LED_DDR FM3_GPIO->DDR1 +#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) +#define USER_LED_PFR FM3_GPIO->PFR1 +#define USER_LED_PCR FM3_GPIO->PCR1 +#define USER_LED_PDOR FM3_GPIO->PDOR1 +#define USER_LED_DDR FM3_GPIO->DDR1 -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 void rt_hw_led_init(void); void rt_hw_led_on(rt_uint8_t num); diff --git a/bsp/mb9bf506r/drivers/nand.c b/bsp/mb9bf506r/drivers/nand.c index 22427a3d5f..fcd8cf42d4 100644 --- a/bsp/mb9bf506r/drivers/nand.c +++ b/bsp/mb9bf506r/drivers/nand.c @@ -1,11 +1,7 @@ /* - * File : nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,17 +12,17 @@ #include "mb9bf506r.h" /* - * NandFlash driver for SamSung K9F5608 + * NandFlash driver for SamSung K9F5608 * 32M x 8bit */ -#define PAGE_SIZE 512 -#define PAGE_PER_BLOCK 32 -#define BLOCK_NUM 2048 +#define PAGE_SIZE 512 +#define PAGE_PER_BLOCK 32 +#define BLOCK_NUM 2048 /* device driver debug trace */ /* #define NAND_DEBUG */ #ifdef NAND_DEBUG -#define trace_log rt_kprintf +#define trace_log rt_kprintf #else #define trace_log(...) #endif @@ -38,14 +34,14 @@ */ struct rt_device_nand { - struct rt_device parent; /* which is inherited from rt_device */ + struct rt_device parent; /* which is inherited from rt_device */ - rt_uint16_t block_num; /* total block number in device */ - rt_uint16_t page_per_block; /* pages in one block */ - rt_uint16_t page_size; /* page size */ + rt_uint16_t block_num; /* total block number in device */ + rt_uint16_t page_per_block; /* pages in one block */ + rt_uint16_t page_size; /* page size */ - /* this buffer which used as to save data before erase block */ - rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; + /* this buffer which used as to save data before erase block */ + rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; }; static struct rt_device_nand _nand; @@ -60,8 +56,8 @@ static struct rt_device_nand _nand; #define NF_OE_H() {IO_NF_PDOR |= NF_EN;} #define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} -#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} -#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} +#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} +#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} static unsigned char NF_ReadStatus(void); static void Wait(unsigned int cnt); @@ -107,11 +103,11 @@ static unsigned char NF_ReadStatus(void) */ static void NF_Init(void) { - FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ - FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ - |1<<6 /* ALE, CLE, WEX, REX enable */ - |1<<0); /* D0-D7 enable */ + FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ + FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ + |1<<6 /* ALE, CLE, WEX, REX enable */ + |1<<0); /* D0-D7 enable */ FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ @@ -125,9 +121,9 @@ static void NF_Init(void) static void NF_UnInit(void) { - FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ - FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ + FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ + FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ |1<<6 /* disable ALE, CLE, WEX, REX enable */ |1<<0); /* disable D0-D7 enable */ FM3_EXBUS->MODE7 &= ~(1<<4); @@ -144,52 +140,52 @@ static void NF_UnInit(void) * Return: 0: Flash Operation OK * 1: Flash Operation NG */ -int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, +int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, unsigned char *oob) { unsigned int blockPage,i; NF_Init(); - blockPage=(block<<5)+page; /* 1 block=32 page */ + blockPage=(block<<5)+page; /* 1 block=32 page */ NF_OE_L(); NF_DATA_OUT(); - if (buffer != RT_NULL) - { - volatile unsigned char ch; + if (buffer != RT_NULL) + { + volatile unsigned char ch; - NF_CMD(NAND_CMD_READ0); /* send read data */ + NF_CMD(NAND_CMD_READ0); /* send read data */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); - Wait(500); + Wait(500); - for(i=0;i<512;i++) /* read 512 bytes data */ - buffer[i] = NF_RDDATA(); - for(i=0;i<16;i++) /* read 16 bytes oob */ - if (oob != RT_NULL) - oob[i] = NF_RDDATA(); - else - ch = NF_RDDATA(); - } - else - { - NF_CMD(NAND_CMD_READOOB); /* send read data */ + for(i=0;i<512;i++) /* read 512 bytes data */ + buffer[i] = NF_RDDATA(); + for(i=0;i<16;i++) /* read 16 bytes oob */ + if (oob != RT_NULL) + oob[i] = NF_RDDATA(); + else + ch = NF_RDDATA(); + } + else + { + NF_CMD(NAND_CMD_READOOB); /* send read data */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); - Wait(500); + Wait(500); - for (i=0; i<16; i++) /* read 16 bytes oob */ - oob[i] = NF_RDDATA(); - } + for (i=0; i<16; i++) /* read 16 bytes oob */ + oob[i] = NF_RDDATA(); + } NF_OE_H(); NF_UnInit(); @@ -206,7 +202,7 @@ int NF_EraseBlock(unsigned int block) { rt_uint32_t blockPage; - trace_log("Erase block %d: ", block); + trace_log("Erase block %d: ", block); NF_Init(); blockPage = (block << 5); @@ -219,19 +215,19 @@ int NF_EraseBlock(unsigned int block) if(NF_ReadStatus()) { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - trace_log("Failed\n"); - rt_kprintf("erase block failed\n"); + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + trace_log("Failed\n"); + rt_kprintf("erase block failed\n"); - return FLASH_NG; + return FLASH_NG; } NF_OE_H(); NF_UnInit(); - trace_log("OK\n"); + trace_log("OK\n"); return FLASH_OK; } @@ -261,24 +257,24 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) NF_ADDR((blockPage>>8) & 0xff); NF_CLR_ALE(); - for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ - for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ + for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ + for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ - NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ + NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ if(NF_ReadStatus()) { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - - trace_log("write failed\n"); - return FLASH_NG; + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + + trace_log("write failed\n"); + return FLASH_NG; } /* verify the write data */ NF_DATA_OUT(); - NF_CMD(NAND_CMD_READ0); /* send read command */ + NF_CMD(NAND_CMD_READ0); /* send read command */ NF_ADDR(0); NF_ADDR(blockPage & 0xff); NF_ADDR((blockPage>>8) & 0xff); @@ -288,11 +284,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) Wait(500); for(i=0; i<512; i++) { - data=NF_RDDATA(); /* verify 1-512 byte */ + data=NF_RDDATA(); /* verify 1-512 byte */ if(data != buffer[i]) { - trace_log("block %d, page %d\n", block , page); - trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); + trace_log("block %d, page %d\n", block , page); + trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); NF_Reset(); NF_OE_H(); @@ -303,11 +299,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) for(i=0; i<16; i++) { - data=NF_RDDATA(); /* verify 16 byte dummy data */ + data=NF_RDDATA(); /* verify 16 byte dummy data */ if(data != se[i]) { - trace_log("block %d, page %d\n", block , page); - trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); + trace_log("block %d, page %d\n", block , page); + trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); NF_Reset(); NF_OE_H(); NF_UnInit(); @@ -327,7 +323,7 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) */ void NF_ReadID(unsigned char *id) { - unsigned char maker_code; + unsigned char maker_code; NF_Init(); NF_OE_L(); NF_DATA_OUT(); @@ -337,7 +333,7 @@ void NF_ReadID(unsigned char *id) Wait(10); NF_DATA_IN(); maker_code = NF_RDDATA(); - maker_code = maker_code; + maker_code = maker_code; *id = NF_RDDATA(); NF_OE_H(); NF_UnInit(); @@ -345,58 +341,58 @@ void NF_ReadID(unsigned char *id) static rt_err_t rt_nand_init (rt_device_t dev) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } static rt_err_t rt_nand_close(rt_device_t dev) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } /* nand device read */ -static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, +static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_ubase_t block; /* block of position */ - rt_ubase_t page, index; /* page in block of position */ - rt_uint8_t *page_ptr, oob[16]; - struct rt_device_nand *nand; + rt_ubase_t block; /* block of position */ + rt_ubase_t page, index; /* page in block of position */ + rt_uint8_t *page_ptr, oob[16]; + struct rt_device_nand *nand; - /* get nand device */ - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); + /* get nand device */ + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; - trace_log("nand read: position %d, block %d, page %d, size %d\n", - pos, block, page, size); + trace_log("nand read: position %d, block %d, page %d, size %d\n", + pos, block, page, size); - /* set page buffer pointer */ - page_ptr = (rt_uint8_t*) buffer; - for (index = 0; index < size; index ++) - { - NF_ReadPage(block, page + index, page_ptr, oob); - page_ptr += nand->page_size; - - if (page + index > nand->page_per_block) - { - block += 1; - page = 0; - } - } + /* set page buffer pointer */ + page_ptr = (rt_uint8_t*) buffer; + for (index = 0; index < size; index ++) + { + NF_ReadPage(block, page + index, page_ptr, oob); + page_ptr += nand->page_size; - /* return read size (count of block) */ - return size; + if (page + index > nand->page_per_block) + { + block += 1; + page = 0; + } + } + + /* return read size (count of block) */ + return size; } /* @@ -407,190 +403,190 @@ static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, * @param buffer the data buffer to be written * @param pages the number of pages to be written */ -static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, - rt_ubase_t block, rt_ubase_t page, - const rt_uint8_t *buffer, rt_ubase_t pages) +static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, + rt_ubase_t block, rt_ubase_t page, + const rt_uint8_t *buffer, rt_ubase_t pages) { - rt_ubase_t index; - rt_uint32_t page_status; - rt_uint8_t *page_ptr, oob[16]; + rt_ubase_t index; + rt_uint32_t page_status; + rt_uint8_t *page_ptr, oob[16]; - /* set page status */ - page_status = 0; + /* set page status */ + page_status = 0; - /* read each page in block */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - NF_ReadPage(block, index, page_ptr, oob); - if (!oob[0]) - page_status |= (1 << index); - page_ptr += nand->page_size; - } + /* read each page in block */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + NF_ReadPage(block, index, page_ptr, oob); + if (!oob[0]) + page_status |= (1 << index); + page_ptr += nand->page_size; + } - /* erase block */ - NF_EraseBlock(block); + /* erase block */ + NF_EraseBlock(block); - page_ptr = &(nand->block_buffer[page * nand->page_size]); - /* merge buffer to page buffer */ - for (index = 0; index < pages; index ++) - { - rt_memcpy(page_ptr, buffer, nand->page_size); + page_ptr = &(nand->block_buffer[page * nand->page_size]); + /* merge buffer to page buffer */ + for (index = 0; index < pages; index ++) + { + rt_memcpy(page_ptr, buffer, nand->page_size); - /* set page status */ - page_status |= (1 << (page + index)); + /* set page status */ + page_status |= (1 << (page + index)); - /* move to next page */ - page_ptr += nand->page_size; - buffer += nand->page_size; - } + /* move to next page */ + page_ptr += nand->page_size; + buffer += nand->page_size; + } - /* write to flash */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - if (page_status & (1 << index)) - NF_WritePage(block, index, page_ptr); + /* write to flash */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + if (page_status & (1 << index)) + NF_WritePage(block, index, page_ptr); - /* move to next page */ - page_ptr += nand->page_size; - } + /* move to next page */ + page_ptr += nand->page_size; + } - return 0; + return 0; } /* nand device write */ -static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, +static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_ubase_t block, page; - rt_uint8_t oob[16]; - struct rt_device_nand *nand; + rt_ubase_t block, page; + rt_uint8_t oob[16]; + struct rt_device_nand *nand; - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; - trace_log("nand write: position %d, block %d, page %d, size %d\n", - pos, block, page, size); + trace_log("nand write: position %d, block %d, page %d, size %d\n", + pos, block, page, size); - if (size == 1) - { - /* write one page */ + if (size == 1) + { + /* write one page */ - /* read oob to get page status */ - NF_ReadPage(block, page, RT_NULL, oob); - if (oob[0]) - NF_WritePage(block, page, buffer); - else - /* erase block and then write page */ - rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); - } - else if (size > 1) - { - rt_ubase_t index; - rt_ubase_t need_erase_block; - const rt_uint8_t *page_ptr; - rt_ubase_t chunk_pages, pages; + /* read oob to get page status */ + NF_ReadPage(block, page, RT_NULL, oob); + if (oob[0]) + NF_WritePage(block, page, buffer); + else + /* erase block and then write page */ + rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); + } + else if (size > 1) + { + rt_ubase_t index; + rt_ubase_t need_erase_block; + const rt_uint8_t *page_ptr; + rt_ubase_t chunk_pages, pages; - pages = size; - page_ptr = (const rt_uint8_t*) buffer; - do - { - need_erase_block = 0; - /* calculate pages in current chunk */ - if (pages > nand->page_per_block - page) - chunk_pages = nand->page_per_block - page; - else - chunk_pages = pages; + pages = size; + page_ptr = (const rt_uint8_t*) buffer; + do + { + need_erase_block = 0; + /* calculate pages in current chunk */ + if (pages > nand->page_per_block - page) + chunk_pages = nand->page_per_block - page; + else + chunk_pages = pages; - /* get page status in current block */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_ReadPage(block, index, RT_NULL, oob); - if (!oob[0]) - { - /* this page has data, need erase this block firstly */ - need_erase_block = 1; - break; - } - } + /* get page status in current block */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_ReadPage(block, index, RT_NULL, oob); + if (!oob[0]) + { + /* this page has data, need erase this block firstly */ + need_erase_block = 1; + break; + } + } - if (need_erase_block) - { - /* erase block and then write it */ - rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); - page_ptr += chunk_pages * nand->page_size; - } - else - { - /* write pages directly */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_WritePage(block, index, page_ptr); - page_ptr += nand->page_size; - } - } + if (need_erase_block) + { + /* erase block and then write it */ + rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); + page_ptr += chunk_pages * nand->page_size; + } + else + { + /* write pages directly */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_WritePage(block, index, page_ptr); + page_ptr += nand->page_size; + } + } - pages -= chunk_pages; - page = 0; block ++; /* move to next block */ - } - while (pages); - } + pages -= chunk_pages; + page = 0; block ++; /* move to next block */ + } + while (pages); + } - return size; + return size; } static rt_err_t rt_nand_control (rt_device_t dev, int cmd, void *args) { - struct rt_device_nand *nand; + struct rt_device_nand *nand; - nand = (struct rt_device_nand*) dev; + nand = (struct rt_device_nand*) dev; RT_ASSERT(dev != RT_NULL); switch (cmd) - { - case RT_DEVICE_CTRL_BLK_GETGEOME: - { - struct rt_device_blk_geometry *geometry; + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + { + struct rt_device_blk_geometry *geometry; - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; - geometry->bytes_per_sector = nand->page_size; - geometry->block_size = nand->page_size * nand->page_per_block; - geometry->sector_count = nand->block_num * nand->page_per_block; - } - break; - } + geometry->bytes_per_sector = nand->page_size; + geometry->block_size = nand->page_size * nand->page_per_block; + geometry->sector_count = nand->block_num * nand->page_per_block; + } + break; + } - return RT_EOK; + return RT_EOK; } void rt_hw_nand_init(void) { - /* initialize nand flash structure */ - _nand.block_num = BLOCK_NUM; - _nand.page_per_block = PAGE_PER_BLOCK; - _nand.page_size = PAGE_SIZE; + /* initialize nand flash structure */ + _nand.block_num = BLOCK_NUM; + _nand.page_per_block = PAGE_PER_BLOCK; + _nand.page_size = PAGE_SIZE; - rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); + rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); - _nand.parent.type = RT_Device_Class_MTD; - _nand.parent.rx_indicate = RT_NULL; - _nand.parent.tx_complete = RT_NULL; - _nand.parent.init = rt_nand_init; - _nand.parent.open = rt_nand_open; - _nand.parent.close = rt_nand_close; - _nand.parent.read = rt_nand_read; - _nand.parent.write = rt_nand_write; - _nand.parent.control = rt_nand_control; + _nand.parent.type = RT_Device_Class_MTD; + _nand.parent.rx_indicate = RT_NULL; + _nand.parent.tx_complete = RT_NULL; + _nand.parent.init = rt_nand_init; + _nand.parent.open = rt_nand_open; + _nand.parent.close = rt_nand_close; + _nand.parent.read = rt_nand_read; + _nand.parent.write = rt_nand_write; + _nand.parent.control = rt_nand_control; - /* register a MTD device */ - rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); + /* register a MTD device */ + rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); } #ifdef NAND_DEBUG @@ -600,68 +596,68 @@ unsigned char nand_oob[16]; void dump_mem(unsigned char* buffer, int length) { - int i; + int i; - if (length > 64) length = 64; - for (i = 0; i < length; i ++) - { - rt_kprintf("%02x ", *buffer++); - if (((i+1) % 16) == 0) - rt_kprintf("\n"); - } - rt_kprintf("\n"); + if (length > 64) length = 64; + for (i = 0; i < length; i ++) + { + rt_kprintf("%02x ", *buffer++); + if (((i+1) % 16) == 0) + rt_kprintf("\n"); + } + rt_kprintf("\n"); } void nand_read(int block, int page) { - rt_kprintf("read block %d, page %d\n", block, page); + rt_kprintf("read block %d, page %d\n", block, page); - NF_ReadPage(block, page, nand_buffer, nand_oob); - rt_kprintf("page data:\n"); - dump_mem(nand_buffer, 512); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); + NF_ReadPage(block, page, nand_buffer, nand_oob); + rt_kprintf("page data:\n"); + dump_mem(nand_buffer, 512); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); } FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); void nand_write(int block, int page) { - int i; - for (i = 0; i < 512; i ++) - nand_buffer[i] = i; + int i; + for (i = 0; i < 512; i ++) + nand_buffer[i] = i; - NF_WritePage(block, page, nand_buffer); + NF_WritePage(block, page, nand_buffer); } FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); void nand_erase(int block) { - NF_EraseBlock(block); + NF_EraseBlock(block); } FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); void nand_readoob(int block, int page) { - rt_kprintf("read oob on block %d, page %d\n", block, page); + rt_kprintf("read oob on block %d, page %d\n", block, page); - NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); + NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); } FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); void nand_erase_chip() { - int i; - unsigned char id; - - NF_ReadID(&id); - rt_kprintf("id: %02x\n", id); + int i; + unsigned char id; - for (i = 0; i < 2048; i ++) - { - NF_EraseBlock(i); - } + NF_ReadID(&id); + rt_kprintf("id: %02x\n", id); + + for (i = 0; i < 2048; i ++) + { + NF_EraseBlock(i); + } } FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); #endif diff --git a/bsp/mb9bf506r/drivers/nand.h b/bsp/mb9bf506r/drivers/nand.h index ffb4bae2c3..d00909ddce 100644 --- a/bsp/mb9bf506r/drivers/nand.h +++ b/bsp/mb9bf506r/drivers/nand.h @@ -1,11 +1,7 @@ /* - * File : nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,7 +29,7 @@ #define NF_ALE_OFFSET 0x00003000 #define NF_ADDR_OFFSET 0x00002000 #define NF_CMD_OFFSET 0x00001000 -#define NF_DATA_OFFSET 0x00000000 +#define NF_DATA_OFFSET 0x00000000 /* NAND command */ #define NAND_CMD_READ0 0x00 @@ -47,7 +43,7 @@ #define NAND_CMD_READID1 0x91 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff - + #define FLASH_OK 0 #define FLASH_NG 1 diff --git a/bsp/mb9bf568r/applications/application.c b/bsp/mb9bf568r/applications/application.c index 462207672e..e5d2b55950 100644 --- a/bsp/mb9bf568r/applications/application.c +++ b/bsp/mb9bf568r/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,7 +24,7 @@ void rt_init_thread_entry(void *parameter) #endif - //finsh_system_init(); + //finsh_system_init(); finsh_set_device(RT_CONSOLE_DEVICE_NAME); @@ -36,10 +32,6 @@ void rt_init_thread_entry(void *parameter) { extern void rt_led_hw_init(void); rt_led_hw_init(); - } - { - extern int demo_init(void); - demo_init(); } } diff --git a/bsp/mb9bf568r/applications/demo.c b/bsp/mb9bf568r/applications/demo.c deleted file mode 100644 index d43ce2f5a4..0000000000 --- a/bsp/mb9bf568r/applications/demo.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - ´ËdemoÓÃÓÚÑÝʾ¶¯Ì¬Ï̴߳´½¨ - */ -#include -#include "board.h" - -#ifdef RT_USING_FINSH -#include -#include -#endif - - -static rt_thread_t tid1 = RT_NULL; -static rt_thread_t tid2 = RT_NULL; - - -static void thread1_entry(void* parameter) -{ - rt_uint32_t count = 0; - - rt_kprintf("thread1 dynamicly created ok\n"); - while (1) - { - rt_kprintf("thread1 count: %d\n",count++); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void thread2_entry(void* parameter) -{ - rt_uint32_t count = 0; - rt_kprintf("thread2 dynamicly created ok\n"); - - while(1) - { - if(count == 3) - break; - rt_kprintf("thread2 count: %d\n",count++); - rt_thread_delay(RT_TICK_PER_SECOND); - - } - rt_thread_delay(RT_TICK_PER_SECOND * 4); - - rt_thread_delete(tid1); - rt_kprintf("thread1 deleted ok\n"); -} - - -int demo_init(void) -{ - - tid1 = rt_thread_create("thread1", - thread1_entry, - RT_NULL, - 512, 6, 10); - - if (tid1 != RT_NULL) - rt_thread_startup(tid1); - - tid2 = rt_thread_create("thread2", - thread2_entry, - RT_NULL, - 512, 6, 10); - - if (tid2 != RT_NULL) - rt_thread_startup(tid2); - - return 0; -} diff --git a/bsp/mb9bf568r/applications/startup.c b/bsp/mb9bf568r/applications/startup.c index 1ad95dbce8..263bd20a28 100644 --- a/bsp/mb9bf568r/applications/startup.c +++ b/bsp/mb9bf568r/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -43,7 +39,7 @@ void rtthread_startup(void) /* show version */ rt_show_version(); - + /* init timer system */ rt_system_timer_init(); diff --git a/bsp/mb9bf568r/drivers/board.c b/bsp/mb9bf568r/drivers/board.c index 2dbc219f28..bd44ad80b1 100644 --- a/bsp/mb9bf568r/drivers/board.c +++ b/bsp/mb9bf568r/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -64,7 +60,7 @@ rt_uint32_t rt_hw_tick_get_microsecond(void) rt_tick_t tick; rt_uint32_t value; -#define TICK_US (1000000/RT_TICK_PER_SECOND) +#define TICK_US (1000000/RT_TICK_PER_SECOND) tick = rt_tick_get(); value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; diff --git a/bsp/mb9bf568r/drivers/board.h b/bsp/mb9bf568r/drivers/board.h index 1b784810bf..ed258f82a0 100644 --- a/bsp/mb9bf568r/drivers/board.h +++ b/bsp/mb9bf568r/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf568r/drivers/led.c b/bsp/mb9bf568r/drivers/led.c index 20e015cdc9..db80b56fd0 100644 --- a/bsp/mb9bf568r/drivers/led.c +++ b/bsp/mb9bf568r/drivers/led.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "board.h" @@ -28,9 +36,9 @@ static rt_err_t rt_led_init (rt_device_t dev) /* led0-1-2 : P27-P38-PE0 */ FM4_GPIO->PFR2 &= ~((1<<7) ); /* set P27 fuction is GPIO. */ FM4_GPIO->DDR2 |= (1<<7) ; /* set P27 output. */ - FM4_GPIO->PFR3 &= ~((1<<8) ); /* set P38 fuction is GPIO. */ + FM4_GPIO->PFR3 &= ~((1<<8) ); /* set P38 fuction is GPIO. */ FM4_GPIO->DDR3 |= (1<<8) ; /* set P38 output. */ - FM4_GPIO->PFRE &= ~((1<<0) ); /* set PE0 fuction is GPIO. */ + FM4_GPIO->PFRE &= ~((1<<0) ); /* set PE0 fuction is GPIO. */ FM4_GPIO->DDRE |= (1<<0) ; /* set PE0 output. */ /* LED0 */ @@ -127,16 +135,16 @@ static rt_err_t rt_led_control (rt_device_t dev, int cmd, void *args) void rt_led_hw_init(void) { - fm4_led.parent.type = RT_Device_Class_Char; + fm4_led.parent.type = RT_Device_Class_Char; fm4_led.parent.rx_indicate = RT_NULL; fm4_led.parent.tx_complete = RT_NULL; - fm4_led.parent.init = rt_led_init; - fm4_led.parent.open = rt_led_open; - fm4_led.parent.close = rt_led_close; + fm4_led.parent.init = rt_led_init; + fm4_led.parent.open = rt_led_open; + fm4_led.parent.close = rt_led_close; fm4_led.parent.read = rt_led_read; - fm4_led.parent.write = rt_led_write; - fm4_led.parent.control = rt_led_control; - fm4_led.parent.user_data = RT_NULL; + fm4_led.parent.write = rt_led_write; + fm4_led.parent.control = rt_led_control; + fm4_led.parent.user_data = RT_NULL; /* register a character device */ rt_device_register(&fm4_led.parent, "led", RT_DEVICE_FLAG_RDWR); diff --git a/bsp/mb9bf568r/drivers/mcu.h b/bsp/mb9bf568r/drivers/mcu.h index 6ee4e1fe7e..5717ff37cc 100644 --- a/bsp/mb9bf568r/drivers/mcu.h +++ b/bsp/mb9bf568r/drivers/mcu.h @@ -41,8 +41,8 @@ ** ******************************************************************************/ -#define PDL_INT_TYPE_C 1 -#define PDL_INT_TYPE_A 2 +#define PDL_INT_TYPE_C 1 +#define PDL_INT_TYPE_A 2 #define PDL_MCU_INT_TYPE PDL_INT_TYPE_A @@ -50,7 +50,7 @@ ****************************************************************************** ** \brief MCU header file include ** - ******************************************************************************/ + ******************************************************************************/ #ifndef _MB9B560R_H_ #include "mb9b560r.h" #endif @@ -59,7 +59,7 @@ ****************************************************************************** ** \brief MCU system start-up header file include ** - ******************************************************************************/ + ******************************************************************************/ #ifndef _SYSTEM_MB9ABXXX_H_ #include "system_mb9bf56xr.h" #endif diff --git a/bsp/mb9bf568r/drivers/serial.c b/bsp/mb9bf568r/drivers/serial.c index b4d42d510b..6c3a132216 100644 --- a/bsp/mb9bf568r/drivers/serial.c +++ b/bsp/mb9bf568r/drivers/serial.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -258,16 +254,16 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, { RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; + device->type = RT_Device_Class_Char; device->rx_indicate = RT_NULL; device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; /* register a character device */ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); @@ -303,7 +299,7 @@ void rt_hw_serial_isr(rt_device_t device) #ifdef RT_USING_UART0 /* UART0 device driver structure */ -#define UART0 FM4_MFS0 +#define UART0 FM4_MFS0 struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { @@ -316,8 +312,8 @@ struct serial_device uart0 = struct rt_device uart0_device; void MFS0_RX_IRQHandler(void) -{ - /* enter interrupt */ +{ + /* enter interrupt */ rt_interrupt_enter(); rt_hw_serial_isr(&uart0_device); /* leave interrupt */ @@ -330,28 +326,28 @@ void MFS0_RX_IRQHandler(void) void rt_hw_serial_init(void) { - uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); - + uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03)); + #ifdef RT_USING_UART0 // Initialize ports for MFS0 - FM4_GPIO->PFR2 = 0x06u; // P21>SIN0_0, P22>SOT0_0 - FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful; - FM4_GPIO->EPFR07 |= 0x00000040ul; - - // Initialize MFS to UART asynchronous mode - - uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + FM4_GPIO->PFR2 = 0x06u; // P21>SIN0_0, P22>SOT0_0 + FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful; + FM4_GPIO->EPFR07 |= 0x00000040ul; + + // Initialize MFS to UART asynchronous mode + + uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;; uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */ uart0.uart_device->ESCR = ESCR_DATABITS_8; uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - + /* register UART0 device */ rt_hw_serial_register(&uart0_device, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart0); - - + + #endif /**< #ifdef RT_USING_UART0 */ } diff --git a/bsp/mb9bf568r/drivers/serial.h b/bsp/mb9bf568r/drivers/serial.h index b057a811dd..776b2a3877 100644 --- a/bsp/mb9bf568r/drivers/serial.h +++ b/bsp/mb9bf568r/drivers/serial.h @@ -1,16 +1,12 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. + * 2011-05-15 lgnq modified according bernard's implementaion. */ #ifndef __RT_HW_SERIAL_H__ @@ -57,21 +53,21 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 128 -#define UART_TX_BUFFER_SIZE 128 +#define UART_RX_BUFFER_SIZE 128 +#define UART_TX_BUFFER_SIZE 128 struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; /* @@ -83,15 +79,15 @@ struct serial_int_tx struct serial_device { - FM4_MFS_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; + FM4_MFS_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; }; void rt_hw_serial_isr(rt_device_t device); diff --git a/bsp/mb9bf568r/rtconfig.h b/bsp/mb9bf568r/rtconfig.h index 1982028ce7..8191fc8e65 100644 --- a/bsp/mb9bf568r/rtconfig.h +++ b/bsp/mb9bf568r/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 64 +#define RT_THREAD_PRIORITY_MAX 64 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -60,9 +60,9 @@ /* #define RT_TINY_SIZE */ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ diff --git a/bsp/mb9bf618s/applications/application.c b/bsp/mb9bf618s/applications/application.c index 56187b68c2..5e7c265450 100644 --- a/bsp/mb9bf618s/applications/application.c +++ b/bsp/mb9bf618s/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf618s/applications/startup.c b/bsp/mb9bf618s/applications/startup.c index ad46ce7e39..22d38bcf95 100644 --- a/bsp/mb9bf618s/applications/startup.c +++ b/bsp/mb9bf618s/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -43,7 +39,7 @@ void rtthread_startup(void) /* show version */ rt_show_version(); - + /* init timer system */ rt_system_timer_init(); diff --git a/bsp/mb9bf618s/drivers/board.c b/bsp/mb9bf618s/drivers/board.c index 12345bbea5..8490e7a060 100644 --- a/bsp/mb9bf618s/drivers/board.c +++ b/bsp/mb9bf618s/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -64,7 +60,7 @@ rt_uint32_t rt_hw_tick_get_microsecond(void) rt_tick_t tick; rt_uint32_t value; -#define TICK_US (1000000/RT_TICK_PER_SECOND) +#define TICK_US (1000000/RT_TICK_PER_SECOND) tick = rt_tick_get(); value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD; diff --git a/bsp/mb9bf618s/drivers/board.h b/bsp/mb9bf618s/drivers/board.h index 3e5887b8f1..c082b0b54c 100644 --- a/bsp/mb9bf618s/drivers/board.h +++ b/bsp/mb9bf618s/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf618s/drivers/led.c b/bsp/mb9bf618s/drivers/led.c index e36e70ca46..bfad9947e7 100644 --- a/bsp/mb9bf618s/drivers/led.c +++ b/bsp/mb9bf618s/drivers/led.c @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #include #include "board.h" @@ -129,16 +138,16 @@ static rt_err_t rt_led_control (rt_device_t dev, int cmd, void *args) void rt_led_hw_init(void) { - fm3_led.parent.type = RT_Device_Class_Char; + fm3_led.parent.type = RT_Device_Class_Char; fm3_led.parent.rx_indicate = RT_NULL; fm3_led.parent.tx_complete = RT_NULL; - fm3_led.parent.init = rt_led_init; - fm3_led.parent.open = rt_led_open; - fm3_led.parent.close = rt_led_close; + fm3_led.parent.init = rt_led_init; + fm3_led.parent.open = rt_led_open; + fm3_led.parent.close = rt_led_close; fm3_led.parent.read = rt_led_read; - fm3_led.parent.write = rt_led_write; - fm3_led.parent.control = rt_led_control; - fm3_led.parent.user_data = RT_NULL; + fm3_led.parent.write = rt_led_write; + fm3_led.parent.control = rt_led_control; + fm3_led.parent.user_data = RT_NULL; /* register a character device */ rt_device_register(&fm3_led.parent, "led", RT_DEVICE_FLAG_RDWR); diff --git a/bsp/mb9bf618s/drivers/serial.c b/bsp/mb9bf618s/drivers/serial.c index 50e3d37829..79279e79e5 100644 --- a/bsp/mb9bf618s/drivers/serial.c +++ b/bsp/mb9bf618s/drivers/serial.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -258,16 +254,16 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, { RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; + device->type = RT_Device_Class_Char; device->rx_indicate = RT_NULL; device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; /* register a character device */ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); @@ -303,7 +299,7 @@ void rt_hw_serial_isr(rt_device_t device) #ifdef RT_USING_UART0 /* UART0 device driver structure */ -#define UART0 FM3_MFS0_UART +#define UART0 FM3_MFS0_UART struct serial_int_rx uart0_int_rx; struct serial_device uart0 = { @@ -327,7 +323,7 @@ void MFS0RX_IRQHandler(void) #ifdef RT_USING_UART2 /* UART2 device driver structure */ -#define UART2 FM3_MFS2_UART +#define UART2 FM3_MFS2_UART struct serial_int_rx uart2_int_rx; struct serial_device uart2 = { @@ -351,7 +347,7 @@ void MFS2RX_IRQHandler(void) #ifdef RT_USING_UART4 /* UART4 device driver structure */ -#define UART4 FM3_MFS4_UART +#define UART4 FM3_MFS4_UART struct serial_int_rx uart4_int_rx; struct serial_device uart4 = { diff --git a/bsp/mb9bf618s/drivers/serial.h b/bsp/mb9bf618s/drivers/serial.h index 9a47cba38f..388f9eef86 100644 --- a/bsp/mb9bf618s/drivers/serial.h +++ b/bsp/mb9bf618s/drivers/serial.h @@ -1,16 +1,12 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. + * 2011-05-15 lgnq modified according bernard's implementaion. */ #ifndef __RT_HW_SERIAL_H__ @@ -57,21 +53,21 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; /* @@ -83,14 +79,14 @@ struct serial_int_tx struct serial_device { - FM3_MFS03_UART_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq, tx_irq; + FM3_MFS03_UART_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq, tx_irq; - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; }; void rt_hw_serial_isr(rt_device_t device); diff --git a/bsp/mb9bf618s/rtconfig.h b/bsp/mb9bf618s/rtconfig.h index 1b647a7a30..d887692233 100644 --- a/bsp/mb9bf618s/rtconfig.h +++ b/bsp/mb9bf618s/rtconfig.h @@ -3,16 +3,16 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -60,9 +60,9 @@ /* #define RT_TINY_SIZE */ #define RT_USING_CONSOLE /* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_CONSOLE_DEVICE_NAME "uart0" /* SECTION: finsh, a C-Express shell */ /* Using FinSH as Shell*/ diff --git a/bsp/nios_ii/application.c b/bsp/nios_ii/application.c index 22037c8f9a..eedd990a18 100644 --- a/bsp/nios_ii/application.c +++ b/bsp/nios_ii/application.c @@ -1,7 +1,7 @@ /* * File : application.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsp/nios_ii/board.c b/bsp/nios_ii/board.c index 2614a25095..d9609c1cec 100644 --- a/bsp/nios_ii/board.c +++ b/bsp/nios_ii/board.c @@ -1,7 +1,7 @@ /* * File : board.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsp/nios_ii/board.h b/bsp/nios_ii/board.h index d7c6d3540f..218dfd372a 100644 --- a/bsp/nios_ii/board.h +++ b/bsp/nios_ii/board.h @@ -1,7 +1,7 @@ /* * File : board.h * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsp/nios_ii/rtconfig.h b/bsp/nios_ii/rtconfig.h index fcd3799846..6a7d9c7d33 100644 --- a/bsp/nios_ii/rtconfig.h +++ b/bsp/nios_ii/rtconfig.h @@ -6,17 +6,17 @@ #define __RTTHREAD_CFG_H__ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second */ /* TIMER_TICKS_PER_SEC define in system.h */ -#define RT_TICK_PER_SECOND TIMER_TICKS_PER_SEC +#define RT_TICK_PER_SECOND TIMER_TICKS_PER_SEC /* SECTION: RT_DEBUG */ /* Thread Debug */ @@ -35,9 +35,9 @@ /* Using Software Timer */ /* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 /* SECTION: IPC */ /* Using Semaphore*/ @@ -73,7 +73,7 @@ /* SECTION: Console options */ #define RT_USING_CONSOLE /* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_USING_NEWLIB @@ -92,11 +92,11 @@ #define RT_USING_DFS_ELMFAT /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 4 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: lwip, a lighwight TCP/IP protocol stack */ //#define RT_USING_LWIP @@ -110,37 +110,37 @@ #define RT_LWIP_DNS /* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +#define RT_LWIP_TCP_PCB_NUM 5 /* Using DHCP */ //#define RT_LWIP_DHCP /* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 /* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 /* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 /* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 /* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #endif diff --git a/bsp/nios_ii/startup.c b/bsp/nios_ii/startup.c index e2bbaaa996..76983e346d 100644 --- a/bsp/nios_ii/startup.c +++ b/bsp/nios_ii/startup.c @@ -1,7 +1,7 @@ /* * File : startup.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsp/nios_ii/uart.c b/bsp/nios_ii/uart.c index 65a22db34c..79c2dcc586 100644 --- a/bsp/nios_ii/uart.c +++ b/bsp/nios_ii/uart.c @@ -32,7 +32,7 @@ static rt_err_t rt_uart_init (rt_device_t dev) { set_baudrate(115200); - IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//½ÓÊÕÖжÏʹÄÜ + IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//接收中断使能 IOWR_ALTERA_AVALON_UART_STATUS(RS232_BASE, 0x0); // clean status rx_put_index = 0; @@ -99,17 +99,17 @@ void rt_hw_uart_init(void) { // init uart set_baudrate(115200); - IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//½ÓÊÕÖжÏʹÄÜ + IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//接收中断使能 IOWR_ALTERA_AVALON_UART_STATUS(RS232_BASE, 0x0); // clean status alt_irq_register(RS232_IRQ, NULL, uart_isr); // register device uart_device.type = RT_Device_Class_Char; /* device interface */ - uart_device.init = rt_uart_init; - uart_device.open = rt_uart_open; + uart_device.init = rt_uart_init; + uart_device.open = rt_uart_open; uart_device.close = rt_uart_close; - uart_device.read = rt_uart_read; + uart_device.read = rt_uart_read; uart_device.write = rt_uart_write; uart_device.control = rt_uart_control; diff --git a/bsp/raspberry-pi/raspi2/driver/bcm283x.h b/bsp/raspberry-pi/raspi2/driver/bcm283x.h index 85422e2a22..8339133652 100644 --- a/bsp/raspberry-pi/raspi2/driver/bcm283x.h +++ b/bsp/raspberry-pi/raspi2/driver/bcm283x.h @@ -3,8 +3,8 @@ #include -#define PER_BASE (0x3F000000) -#define PER_BASE_40000000 (0x40000000) +#define PER_BASE (0x3F000000) +#define PER_BASE_40000000 (0x40000000) /* * GPIO @@ -50,17 +50,17 @@ /* * ARM Timer */ -#define ARM_TIMER_BASE (PER_BASE + 0xB000) +#define ARM_TIMER_BASE (PER_BASE + 0xB000) -#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) -#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) -#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) -#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) -#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) -#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) -#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) -#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) -#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) +#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) +#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) +#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) +#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) +#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) +#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) +#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) +#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) +#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) /* * Core Timer diff --git a/bsp/raspberry-pi/raspi3-32/applications/main.c b/bsp/raspberry-pi/raspi3-32/applications/main.c index cda0e0d711..de0fe56137 100644 --- a/bsp/raspberry-pi/raspi3-32/applications/main.c +++ b/bsp/raspberry-pi/raspi3-32/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/applications/mnt.c b/bsp/raspberry-pi/raspi3-32/applications/mnt.c index 88b714022c..44450fe9b6 100644 --- a/bsp/raspberry-pi/raspi3-32/applications/mnt.c +++ b/bsp/raspberry-pi/raspi3-32/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/applications/test_device.c b/bsp/raspberry-pi/raspi3-32/applications/test_device.c index 7efb1cfb64..ec7e480212 100644 --- a/bsp/raspberry-pi/raspi3-32/applications/test_device.c +++ b/bsp/raspberry-pi/raspi3-32/applications/test_device.c @@ -1,6 +1,6 @@ /* * File : test_driver.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -50,7 +50,7 @@ void test_hdmi() int i=0; for (; i < 20; i++) colors[i] = COLOR_RED; rt_graphix_ops(hdmi) -> blit_line((char *)colors, 20, 20, 20); - + #endif } @@ -73,8 +73,8 @@ void test_cpusmp(void) { rt_kprintf("Hello Test SMP!\n"); #ifdef RT_USING_SMP - int i; - char test_name[RT_NAME_MAX]; + int i; + char test_name[RT_NAME_MAX]; for (i = 0; i < _CPUS_NR; i++) { rt_sprintf(test_name, "smp%d", i); @@ -162,17 +162,17 @@ void test_i2c(void) rt_kprintf("can't find %s device!\n", name); else { - read_regs(i2c_bus, 7, buf); - buf[0] = buf[0]&0x7F; //sec - buf[1] = buf[1]&0x7F; //min - buf[2] = buf[2]&0x3F; //hour - buf[3] = buf[3]&0x07; //week - buf[4] = buf[4]&0x3F; //day - buf[5] = buf[5]&0x1F; //mouth - //year/month/day - rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]); - //hour:minute/second - rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]); + read_regs(i2c_bus, 7, buf); + buf[0] = buf[0]&0x7F; //sec + buf[1] = buf[1]&0x7F; //min + buf[2] = buf[2]&0x3F; //hour + buf[3] = buf[3]&0x07; //week + buf[4] = buf[4]&0x3F; //day + buf[5] = buf[5]&0x1F; //mouth + //year/month/day + rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]); + //hour:minute/second + rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]); } #endif } diff --git a/bsp/raspberry-pi/raspi3-32/cpu/armv7.h b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h index 859b0371b7..a992fdebd0 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/armv7.h +++ b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cp15.h b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h index 14b85b7e64..d8075c84df 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/cp15.h +++ b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector) static inline void setup_bootstrap_addr(int cpu, int addr) { - CORE_MAILBOX3_SET(cpu) = addr; + CORE_MAILBOX3_SET(cpu) = addr; } static inline void enable_cpu_ipi_intr(int cpu) @@ -67,7 +67,7 @@ static inline void enable_cpu_ipi_intr(int cpu) static inline void enable_cpu_timer_intr(int cpu) { - CORETIMER_INTCTL(cpu) = 0x8; + CORETIMER_INTCTL(cpu) = 0x8; } static inline void enable_cntv(void) diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cpu.c b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c index 4d02ca35e1..b43b804597 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/cpu.c +++ b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -52,7 +52,7 @@ void rt_hw_spin_lock(rt_hw_spinlock_t *lock) : "r" (&lock->slock), "I" (1 << 16) : "cc"); - while (lockval.tickets.next != lockval.tickets.owner) + while (lockval.tickets.next != lockval.tickets.owner) { __WFE(); lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); diff --git a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c index c9e7c17f8f..11cfdb3d25 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c +++ b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018/5/3 Bernard first version * 2019-07-28 zdzn add smp support - * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi */ @@ -163,15 +163,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) } if (cpu_mask & 0x2) { - send_ipi_msg(1, ipi_vector); + send_ipi_msg(1, ipi_vector); } if (cpu_mask & 0x4) { - send_ipi_msg(2, ipi_vector); + send_ipi_msg(2, ipi_vector); } if (cpu_mask & 0x8) { - send_ipi_msg(3, ipi_vector); + send_ipi_msg(3, ipi_vector); } __DSB(); } diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.c b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c index b3541d2ad4..f642dc235c 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/mmu.c +++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.h b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h index 6b0c25e990..6b994cac77 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/mmu.h +++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h @@ -43,7 +43,7 @@ /* normal memory mapping type */ #define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) #define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC) -#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, rt_uint32_t size, diff --git a/bsp/raspberry-pi/raspi3-32/cpu/stack.c b/bsp/raspberry-pi/raspi3-32/cpu/stack.c index c2c60fbf49..4d20ad7879 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/stack.c +++ b/bsp/raspberry-pi/raspi3-32/cpu/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/cpu/trap.c b/bsp/raspberry-pi/raspi3-32/cpu/trap.c index f83f183695..b9fa6bb1c5 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/trap.c +++ b/bsp/raspberry-pi/raspi3-32/cpu/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2013-07-20 Bernard first version * 2019-07-28 zdzn add smp support - * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi */ @@ -164,7 +164,7 @@ void rt_hw_trap_irq(void) if (mailbox_data & 0x1) { /* clear mailbox */ - IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; + IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; isr_func = isr_table[IRQ_ARM_MAILBOX].handler; #ifdef RT_USING_INTERRUPT_INFO isr_table[IRQ_ARM_MAILBOX].counter++; @@ -175,7 +175,7 @@ void rt_hw_trap_irq(void) isr_func(IRQ_ARM_MAILBOX, param); } } - else + else CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; } #endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.c b/bsp/raspberry-pi/raspi3-32/driver/board.c index 9cd929662e..920d284c07 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/board.c +++ b/bsp/raspberry-pi/raspi3-32/driver/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.h b/bsp/raspberry-pi/raspi3-32/driver/board.h index 8736027c06..bc5be3f9c8 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/board.h +++ b/bsp/raspberry-pi/raspi3-32/driver/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c index cc915351af..f004edad8c 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -306,7 +306,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) return RT_EOK; } -const static struct rt_device_ops hdmi_fb_ops = +const static struct rt_device_ops hdmi_fb_ops = { RT_NULL, hdmi_fb_open, @@ -368,7 +368,7 @@ static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size) } } -static struct rt_device_graphic_ops hdmi_ops = +static struct rt_device_graphic_ops hdmi_ops = { hdmi_set_pixel, hdmi_get_pixel, diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h index 4926fa3ab1..1d447aeab1 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,15 +14,15 @@ #define COLOR_BLACK RGB(0, 0, 0) -#define COLOR_GREEN RGB(0, 255, 0) - -#define COLOR_CYAN RGB(0, 255, 255) +#define COLOR_GREEN RGB(0, 255, 0) -#define COLOR_RED RGB(255, 0, 0) +#define COLOR_CYAN RGB(0, 255, 255) -#define COLOR_YELLOW RGB(255, 255, 0) +#define COLOR_RED RGB(255, 0, 0) -#define COLOR_WHITE RGB(255, 255, 255) +#define COLOR_YELLOW RGB(255, 255, 0) + +#define COLOR_WHITE RGB(255, 255, 255) #define CONSOLE_WHITE COLOR_WHITE #define CONSOLE_BLACK COLOR_BLACK diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c index 205d7f10aa..721643f515 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h index ce0be096e8..18f95fecfd 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c index 35ab7c36d7..5d1080eadb 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h index ff9e8ca724..2412631852 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c index 147504bd16..3d7b97e8ac 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h index d850defa68..1fd8453e6f 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c index 46df0372e9..4ab2e4c25b 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c @@ -1,6 +1,6 @@ /* * File : drv_sdio.c - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -125,7 +125,7 @@ rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask) else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) { return -RT_ERROR; - } + } return RT_EOK; } diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h index 5c052de90a..917c002daf 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h @@ -1,6 +1,6 @@ /* * File : drv_sdio.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c index eab7a08b39..c42d1cf013 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h index 9e4623b327..58ede93ef4 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c index 36a4fd2baf..117026e91c 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,24 +27,24 @@ static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_ if (mode == HWTIMER_MODE_PERIOD) timer->cnt = cnt; else - timer->cnt = 0; + timer->cnt = 0; __sync_synchronize(); if (timer_id == 1) { rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1); STIMER_C1 = STIMER_CLO + cnt; - } + } else if (timer_id == 3) { rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3); STIMER_C3 = STIMER_CLO + cnt; } - else + else result = -RT_ERROR; __sync_synchronize(); - + return result; } @@ -56,7 +56,7 @@ static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1); else if (timer_id == 3) rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3); - + } static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) @@ -75,7 +75,7 @@ static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void * void rt_device_systimer_isr(int vector, void *param) { - + rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param; rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; RT_ASSERT(timer != RT_NULL); @@ -86,18 +86,18 @@ void rt_device_systimer_isr(int vector, void *param) if (timer_id == 1) { STIMER_CS = 0x2; - STIMER_C1 = STIMER_CLO + timer->cnt; - } + STIMER_C1 = STIMER_CLO + timer->cnt; + } else if (timer_id == 3) { STIMER_CS = 0x8; - STIMER_C3 = STIMER_CLO + timer->cnt; + STIMER_C3 = STIMER_CLO + timer->cnt; } __sync_synchronize(); rt_device_hwtimer_isr(hwtimer); } - + static struct rt_hwtimer_device _hwtimer1; static struct rt_hwtimer_device _hwtimer3; diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h index c85d4c9d1f..7fca63f6b7 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c index 18501b7849..293570e7ab 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -125,7 +125,7 @@ static const struct rt_uart_ops _uart_ops = static void rt_hw_uart_isr(int irqno, void *param) { - struct rt_serial_device *serial = (struct rt_serial_device*)param; + struct rt_serial_device *serial = (struct rt_serial_device*)param; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h index 5211c19989..4f0a31bf52 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c index ad511913cb..b748a7b472 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -129,9 +129,9 @@ int reboot(void) PM_RSTS = PM_PASSWORD | r; // boot from partition 0 PM_WDOG = PM_PASSWORD | 10; PM_RSTC = PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; - + while (1); - + return 0; } MSH_CMD_EXPORT(reboot,reboot system...); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h index 0b59ab79f3..ffb07ff5da 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.c b/bsp/raspberry-pi/raspi3-32/driver/mbox.c index bbd5183aa8..041017e471 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/mbox.c +++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.c @@ -1,6 +1,6 @@ /* * File : mbox.c - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ int mbox_call(unsigned char ch, int mmu_enable) do { asm volatile("nop"); - } + } while (*MBOX_STATUS & MBOX_EMPTY); /* is it a response to our message? */ if (r == *MBOX_READ) diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.h b/bsp/raspberry-pi/raspi3-32/driver/mbox.h index 5c59fd608c..3190603e8f 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/mbox.h +++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.h @@ -1,6 +1,6 @@ /* * File : mbox.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-32/driver/raspi.h b/bsp/raspberry-pi/raspi3-32/driver/raspi.h index 19daa3541d..fedf4bcff8 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/raspi.h +++ b/bsp/raspberry-pi/raspi3-32/driver/raspi.h @@ -1,6 +1,6 @@ /* * File : rsapi.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/applications/main.c b/bsp/raspberry-pi/raspi3-64/applications/main.c index 397f40126b..bd7c917e64 100644 --- a/bsp/raspberry-pi/raspi3-64/applications/main.c +++ b/bsp/raspberry-pi/raspi3-64/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,10 +16,10 @@ void set_led(int state) //set state LED nyala atau mati { if (state==1) //LED nyala - { + { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = 0x00038041; // get serial number command mbox[3] = 8; // buffer size mbox[4] = 0; @@ -29,10 +29,10 @@ void set_led(int state) //set state LED nyala atau mati mbox_call(8, MMU_DISABLE); } else if (state==0) //LED mati - { + { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = 0x00038041; // get serial number command mbox[3] = 8; // buffer size mbox[4] = 0; diff --git a/bsp/raspberry-pi/raspi3-64/applications/mnt.c b/bsp/raspberry-pi/raspi3-64/applications/mnt.c index 33b466434c..01e97b325b 100644 --- a/bsp/raspberry-pi/raspi3-64/applications/mnt.c +++ b/bsp/raspberry-pi/raspi3-64/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c index 5d15dda987..531a0a0dfa 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/board.c +++ b/bsp/raspberry-pi/raspi3-64/driver/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -62,7 +62,7 @@ void rt_hw_timer_init(void) timerStep = rt_hw_get_gtimer_frq(); __DSB(); timerStep /= RT_TICK_PER_SECOND; - + rt_hw_gtimer_enable(); rt_hw_set_gtimer_val(timerStep); core0_timer_enable_interrupt_controller(); @@ -90,7 +90,7 @@ void idle_wfi(void) } /** - * Initialize the Hardware related stuffs. Called from rtthread_startup() + * Initialize the Hardware related stuffs. Called from rtthread_startup() * after interrupt disabled. */ void rt_hw_board_init(void) @@ -105,7 +105,7 @@ void rt_hw_board_init(void) armv8_map(0x3f804000, 0x3f804000, 0x1000, MEM_ATTR_IO);//i2c0 armv8_map(0x3f205000, 0x3f205000, 0x1000, MEM_ATTR_IO);//i2c1 mmu_enable(); - + /* initialize hardware interrupt */ rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors); diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.h b/bsp/raspberry-pi/raspi3-64/driver/board.h index b44c245a17..6b51f0408e 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/board.h +++ b/bsp/raspberry-pi/raspi3-64/driver/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c index cabaded5fd..204fa0c868 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -116,7 +116,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) return RT_EOK; } -const static struct rt_device_ops hdmi_fb_ops = +const static struct rt_device_ops hdmi_fb_ops = { RT_NULL, hdmi_fb_open, @@ -157,7 +157,7 @@ rt_uint32_t bcm283x_mbox_fb_get_gpiovirt(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT; mbox[3] = 4; // buffer size mbox[4] = 0; // len @@ -174,7 +174,7 @@ rt_uint32_t bcm283x_mbox_fb_get_pitch(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_GET_PITCH; mbox[3] = 4; // buffer size mbox[4] = 0; // len @@ -191,7 +191,7 @@ void bcm283x_mbox_fb_set_porder(int rgb) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER; mbox[3] = 4; // buffer size mbox[4] = 4; // len @@ -207,7 +207,7 @@ void bcm283x_mbox_fb_setoffset(int xoffset, int yoffset) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -225,7 +225,7 @@ void bcm283x_mbox_fb_setalpha(int alpha) mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE; mbox[3] = 4; // buffer size mbox[4] = 4; // len diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h index 9fdac754cd..1074dc79c7 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c index 0cd6abb84e..04b5cdf162 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h index f51817b035..009f4e3edc 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c index ce0fd7ae74..b7c6067ae4 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -130,7 +130,7 @@ static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus, volatile rt_base_t base = (volatile rt_base_t)(bus->parent.user_data); if (bus->addr == 0) - base = BCM283X_BSC0_BASE; + base = BCM283X_BSC0_BASE; else base = BCM283X_BSC1_BASE; diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h index 9b652b746f..2412631852 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c index 18fd6474a2..5d43c39073 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h index 82306068ca..4af28efa17 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c index 785f335ebb..a46115804a 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c @@ -1,6 +1,6 @@ /* * File : drv_sdio.c - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -128,7 +128,7 @@ rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask) else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) { return -RT_ERROR; - } + } return RT_EOK; } diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h index 5c052de90a..917c002daf 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h @@ -1,6 +1,6 @@ /* * File : drv_sdio.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c index 0b0c8881a8..4c63fe9aae 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h index 9e4623b327..58ede93ef4 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c index 00b31897d8..a8cb5149d4 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,24 +29,24 @@ static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_ if (mode == HWTIMER_MODE_PERIOD) timer->cnt = cnt; else - timer->cnt = 0; + timer->cnt = 0; __sync_synchronize(); if (timer_id == 1) { rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1); STIMER_C1 = STIMER_CLO + cnt; - } + } else if (timer_id == 3) { rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3); STIMER_C3 = STIMER_CLO + cnt; } - else + else result = -RT_ERROR; __sync_synchronize(); - + return result; } @@ -58,7 +58,7 @@ static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1); else if (timer_id == 3) rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3); - + } static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) @@ -77,7 +77,7 @@ static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void * void rt_device_systimer_isr(int vector, void *param) { - + rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param; rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; RT_ASSERT(timer != RT_NULL); @@ -88,12 +88,12 @@ void rt_device_systimer_isr(int vector, void *param) if (timer_id == 1) { STIMER_CS = 0x2; - STIMER_C1 = STIMER_CLO + timer->cnt; - } + STIMER_C1 = STIMER_CLO + timer->cnt; + } else if (timer_id == 3) { STIMER_CS = 0x8; - STIMER_C3 = STIMER_CLO + timer->cnt; + STIMER_C3 = STIMER_CLO + timer->cnt; } __sync_synchronize(); diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h index c18e3d893c..ebe5536fa5 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c index 62fcb966b4..6eb7a46f10 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -124,7 +124,7 @@ static const struct rt_uart_ops _uart_ops = static void rt_hw_uart_isr(int irqno, void *param) { - struct rt_serial_device *serial = (struct rt_serial_device*)param; + struct rt_serial_device *serial = (struct rt_serial_device*)param; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h index 894c6098db..76072f938e 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c index 245f4df197..f90a251ad0 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -130,9 +130,9 @@ int reboot(void) PM_RSTS = PM_PASSWORD | r; // boot from partition 0 PM_WDOG = PM_PASSWORD | 10; PM_RSTC = PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; - + while (1); - + return 0; } MSH_CMD_EXPORT(reboot,reboot system...); diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h index 0b59ab79f3..ffb07ff5da 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.c b/bsp/raspberry-pi/raspi3-64/driver/mbox.c index dc09ecab4b..fbfc456b4d 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/mbox.c +++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.c @@ -1,6 +1,6 @@ /* * File : mbox.c - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ int mbox_call(unsigned char ch, int mmu_enable) /* is it a response to our message? */ if (r == *MBOX_READ){ /* is it a valid successful response? */ - // rt_kprintf("mbox: %x, %x, %x, %x, %x, %x, %x, %x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4], mbox[5], mbox[6], mbox[7]); + // rt_kprintf("mbox: %x, %x, %x, %x, %x, %x, %x, %x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4], mbox[5], mbox[6], mbox[7]); return mbox[1] == MBOX_RESPONSE; } } @@ -52,12 +52,12 @@ int bcm283x_mbox_hardware_get_model(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL; mbox[3] = 4; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -70,12 +70,12 @@ int bcm283x_mbox_hardware_get_revison(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_REV; + + mbox[2] = MBOX_TAG_HARDWARE_GET_REV; mbox[3] = 4; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -88,12 +88,12 @@ int bcm283x_mbox_hardware_get_mac_address(uint8_t * mac) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS; + + mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS; mbox[3] = 6; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -114,12 +114,12 @@ int bcm283x_mbox_hardware_get_serial(rt_uint64_t* sn) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL; + + mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL; mbox[3] = 8; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -134,12 +134,12 @@ int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY; + + mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY; mbox[3] = 8; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -147,7 +147,7 @@ int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size) *base = mbox[5]; *size = mbox[6]; - + return 0; } @@ -156,12 +156,12 @@ int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY; mbox[3] = 8; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -169,7 +169,7 @@ int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size) *base = mbox[5]; *size = mbox[6]; - + return 0; } @@ -177,8 +177,8 @@ int bcm283x_mbox_clock_get_turbo(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; + + mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -200,8 +200,8 @@ int bcm283x_mbox_clock_set_turbo(int level) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_SET_TURBO; + + mbox[2] = MBOX_TAG_CLOCK_SET_TURBO; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -223,7 +223,7 @@ int bcm283x_mbox_clock_get_state(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_GET_STATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -246,7 +246,7 @@ int bcm283x_mbox_clock_set_state(int id, int state) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_SET_STATE; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -269,8 +269,8 @@ int bcm283x_mbox_clock_get_rate(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_GET_RATE; + + mbox[2] = MBOX_TAG_CLOCK_GET_RATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -292,7 +292,7 @@ int bcm283x_mbox_clock_set_rate(int id, int rate) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -315,7 +315,7 @@ int bcm283x_mbox_clock_get_max_rate(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -338,8 +338,8 @@ int bcm283x_mbox_clock_get_min_rate(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; + + mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -361,7 +361,7 @@ int bcm283x_mbox_power_get_state(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_POWER_GET_STATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -384,7 +384,7 @@ int bcm283x_mbox_power_set_state(int id, int state) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_POWER_SET_STATE; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -407,7 +407,7 @@ int bcm283x_mbox_temp_get(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_TEMP_GET; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -430,7 +430,7 @@ int bcm283x_mbox_temp_get_max(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_TEMP_GET_MAX; mbox[3] = 8; // buffer size mbox[4] = 4; // len diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.h b/bsp/raspberry-pi/raspi3-64/driver/mbox.h index f235691d7b..b7aa2e95c9 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/mbox.h +++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.h @@ -1,6 +1,6 @@ /* * File : mbox.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ extern volatile unsigned int* mbox; /* tags */ #define MBOX_TAG_SETPOWER 0x28001 #define MBOX_TAG_SETCLKRATE 0x38002 -#define MBOX_GET_MAC_ADDRESS 0x10003 +#define MBOX_GET_MAC_ADDRESS 0x10003 #define MBOX_TAG_LAST 0 #define MMIO_BASE 0x3F000000 @@ -47,12 +47,12 @@ extern volatile unsigned int* mbox; #define MBOX_FULL 0x80000000 #define MBOX_EMPTY 0x40000000 -#define DEVICE_ID_SD_CARD 0 -#define DEVICE_ID_USB_HCD 3 -#define POWER_STATE_OFF (0 << 0) -#define POWER_STATE_ON (1 << 0) -#define POWER_STATE_WAIT (1 << 1) -#define POWER_STATE_NO_DEVICE (1 << 1) // in response +#define DEVICE_ID_SD_CARD 0 +#define DEVICE_ID_USB_HCD 3 +#define POWER_STATE_OFF (0 << 0) +#define POWER_STATE_ON (1 << 0) +#define POWER_STATE_WAIT (1 << 1) +#define POWER_STATE_NO_DEVICE (1 << 1) // in response #define MMU_ENABLE 1 #define MMU_DISABLE 0 diff --git a/bsp/raspberry-pi/raspi3-64/driver/raspi.h b/bsp/raspberry-pi/raspi3-64/driver/raspi.h index 9a5de2af02..a24640d07d 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/raspi.h +++ b/bsp/raspberry-pi/raspi3-64/driver/raspi.h @@ -1,6 +1,6 @@ /* * File : rsapi.h - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/applications/main.c b/bsp/raspberry-pi/raspi4-32/applications/main.c index 15dc74dc58..f2248e1660 100644 --- a/bsp/raspberry-pi/raspi4-32/applications/main.c +++ b/bsp/raspberry-pi/raspi4-32/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ int main(int argc, char** argv) { rt_kprintf("Hi, this is RT-Thread!!\n"); - + rt_pin_mode(ACTLED, PIN_MODE_OUTPUT); while(1) diff --git a/bsp/raspberry-pi/raspi4-32/applications/mnt.c b/bsp/raspberry-pi/raspi4-32/applications/mnt.c index ae224e8e89..ea67a4a46a 100644 --- a/bsp/raspberry-pi/raspi4-32/applications/mnt.c +++ b/bsp/raspberry-pi/raspi4-32/applications/mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c index 455bd28ee2..c9571316d1 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.c +++ b/bsp/raspberry-pi/raspi4-32/driver/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ struct mem_desc platform_mem_desc[] = { {0x0, 0x6400000, 0x0, NORMAL_MEM}, {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM}, //mbox msg {0x0E000000, 0x0EE00000, 0x0E000000, DEVICE_MEM}, //framebuffer - {0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch + {0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac {0xFE000000, 0xFF000000, 0xFE000000, DEVICE_MEM}, //peripheral {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic @@ -65,7 +65,7 @@ void idle_wfi(void) } /** - * Initialize the Hardware related stuffs. Called from rtthread_startup() + * Initialize the Hardware related stuffs. Called from rtthread_startup() * after interrupt disabled. */ void rt_hw_board_init(void) diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.h b/bsp/raspberry-pi/raspi4-32/driver/board.h index d675cc658e..29019514b9 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.h +++ b/bsp/raspberry-pi/raspi4-32/driver/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c index 6b839f5e23..cdf809cc77 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h index 9de47bf191..0e7453ca3d 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c index 4ec94896c1..a258dd41e4 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h index 1b79eb1c95..83fbcbdd0e 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c index a2f78ffd61..58683b422d 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -670,7 +670,7 @@ struct pbuf *rt_eth_rx(rt_device_t device) int rt_hw_eth_init(void) { rt_uint8_t mac_addr[6]; - + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h index f7916ee5e1..39bfc87913 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c index b2d2ed79c4..7a3d2604a1 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -102,7 +102,7 @@ static void gpio_set_pud(GPIO_PIN pin, GPIO_PUPD_FUNC mode) case 3: reg_value = GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE); GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE) = (reg_value | (mode << (fselrest*2))); - break; + break; default: break; } @@ -194,7 +194,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin) else { pin_level = 0; - } + } } else @@ -422,7 +422,7 @@ int rt_hw_gpio_init(void) GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; - + rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); rt_hw_interrupt_umask(IRQ_GPIO0); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h index 7594759f97..78c1709965 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c index f596eccc89..3a7503a04d 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ /* * (3.3v) -1 2- * (SDA1/SDA3) -3 4- -* (SCL1/SCL3) -5 6- +* (SCL1/SCL3) -5 6- * (SDA3) -7 8- * -9 10- * -11 12- @@ -268,7 +268,7 @@ static struct raspi_i2c_hw_config hw_device4 = .scl_pin = GPIO_PIN_7, #else .sda_pin = GPIO_PIN_8, - .scl_pin = GPIO_PIN_9, + .scl_pin = GPIO_PIN_9, #endif .sda_mode = ALT5, .scl_mode = ALT5, diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h index e02c8887f0..bfb724ad93 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c index 4d88668eee..d0f63cfce0 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -128,7 +128,7 @@ rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask) else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) { return -RT_ERROR; - } + } return RT_EOK; } @@ -450,7 +450,7 @@ static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock) sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT; int cdiv = sd_get_clock_divider(sdHostVer, mmc_base_clock, clock); temp = read32((pdat->virt + EMMC_CONTROL1)); - temp |= 1; + temp |= 1; temp |= cdiv; temp |= (7 << 16); @@ -639,7 +639,7 @@ int raspi_sdmmc_init(void) #endif mmcsd_change(host); #endif - return RT_EOK; + return RT_EOK; err: if (host) rt_free(host); if (sdhci) rt_free(sdhci); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h index 5919bd64d3..0481a82e6d 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -85,7 +85,7 @@ struct sdhci_t rt_uint32_t width; rt_uint32_t clock; rt_err_t removeable; - void * sdcard; + void * sdcard; rt_err_t (*detect)(struct sdhci_t * sdhci); rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c index f0c6351d7f..9c188a8fa9 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -98,11 +98,11 @@ static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_ if(cfg->mode & RT_SPI_CS_HIGH) { - SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH; + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH; } else { - SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CSPOL_HIGH; + SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CSPOL_HIGH; } return RT_EOK; } @@ -157,7 +157,7 @@ static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_me if (config.mode & RT_SPI_MSB) { flag = 1; - } + } else { flag = 0; @@ -172,7 +172,7 @@ static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_me { SPI_REG_CLK(hwcfg->hw_base) = (RPI_CORE_CLK_HZ / (config.max_hz)); } - + //cs_pin spi0.0 if(cs_pin == GPIO_PIN_8) { diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h index 9cd8e031e4..8fa8baabe0 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -70,7 +70,7 @@ struct raspi_spi_hw_config GPIO_FUNC ce2_mode; #endif rt_ubase_t hw_base; - + }; struct raspi_spi_device diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c index 34b9e1d945..1a3100c745 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -211,7 +211,7 @@ static const struct rt_uart_ops _uart_ops = #ifdef RT_USING_UART1 static void rt_hw_aux_uart_isr(int irqno, void *param) { - struct rt_serial_device *serial = (struct rt_serial_device*)param; + struct rt_serial_device *serial = (struct rt_serial_device*)param; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } #endif @@ -220,7 +220,7 @@ static void rt_hw_uart_isr(int irqno, void *param) { #ifdef RT_USING_UART0 if((PACTL_CS & IRQ_UART0) == IRQ_UART0) - { + { PACTL_CS &= ~(IRQ_UART0); rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND); PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h index d57f4e52f4..b2a4552872 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c index 3c091354bb..a9b2e8fc0c 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -128,7 +128,7 @@ void reboot(void) PM_RSTS |= (PM_PASSWORD | r); // boot from partition 0 PM_WDOG |= (PM_PASSWORD | 0x0A); PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET); - + while (1); } MSH_CMD_EXPORT(reboot,reboot system...); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h index 4c9454ed91..6998792e0d 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c index 955e55bcf5..175c6cd907 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c +++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -123,7 +123,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops hdmi_fb_ops = +const static struct rt_device_ops hdmi_fb_ops = { RT_NULL, hdmi_fb_open, @@ -165,7 +165,7 @@ rt_uint32_t bcm271x_mbox_fb_get_gpiovirt(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT; mbox[3] = 4; // buffer size mbox[4] = 0; // len @@ -182,7 +182,7 @@ rt_uint32_t bcm271x_mbox_fb_get_pitch(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_GET_PITCH; mbox[3] = 4; // buffer size mbox[4] = 0; // len @@ -199,7 +199,7 @@ void bcm271x_mbox_fb_set_porder(int rgb) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER; mbox[3] = 4; // buffer size mbox[4] = 4; // len @@ -215,7 +215,7 @@ void bcm271x_mbox_fb_setoffset(int xoffset, int yoffset) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -233,7 +233,7 @@ void bcm271x_mbox_fb_setalpha(int alpha) mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE; mbox[3] = 4; // buffer size mbox[4] = 4; // len diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h index c9a06358d0..b9901e204b 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h +++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c index c2317bd112..7db4940c97 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c +++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ void lcd_write_data(rt_uint8_t data) } /*Ser rotation of the screen - changes x0 and y0*/ -static inline void lcd_set_rotation(uint8_t rotation) +static inline void lcd_set_rotation(uint8_t rotation) { writeCommand(lcd_dev, 0x36); rt_thread_mdelay(100); @@ -134,7 +134,7 @@ static inline void lcd_set_rotation(uint8_t rotation) lcd_write_data(0x01); lcd_write_data(0xE0); } - + if((rotation == SCREEN_HORIZONTAL_1) || (rotation == SCREEN_HORIZONTAL_2)) { lcd_write_commmand(0x2B); @@ -177,7 +177,7 @@ static inline void fast_send_data(void) rt_sem_release(&lcd_spi_lock); } -static inline void lcd_show(void) +static inline void lcd_show(void) { lcd_write_commmand(0x2C); // Memory write? @@ -188,11 +188,11 @@ static inline void lcd_show(void) fast_send_data(); #else int i, j; - for (i = 0 ; i < 30 ; i ++) + for (i = 0 ; i < 30 ; i ++) { uint16_t *tx_data = (uint16_t*)&send_buffer[5120* i]; int32_t data_sz = 5120; - for( j=0; jdepth >= 3) { - uint32_t *addr_32bit = (uint32_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width; + uint32_t *addr_32bit = (uint32_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width; for (i = 0; i < (CHAR_H * fb->width); i++) { @@ -64,7 +64,7 @@ static void newline(fb_t* fb) } else { - uint16_t *addr_16bit = (uint16_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width; + uint16_t *addr_16bit = (uint16_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width; for (i = 0; i < (CHAR_H * fb->width); i++) { @@ -107,7 +107,7 @@ static void fb_draw_char(fb_t *fb, char s) { *((unsigned short*) (addr + line)) = ((int) *(glyph + ((i)/8)) * 1) & mask ? fb->fore : fb->back; } - + mask >>= 1; if(mask == 0) { @@ -170,12 +170,12 @@ void fb_print(char *s) { rt_device_control(console_dev,RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); } -#endif +#endif } #ifndef LCD_CONSOLE_FLUSH_NOW void lcd_console_task_entry(void *param) -{ +{ fb_t *fb = (fb_t *)param; while (1) { @@ -186,7 +186,7 @@ void lcd_console_task_entry(void *param) } rt_thread_mdelay(LCD_CONSOLE_DELAY); } - + } #endif @@ -199,7 +199,7 @@ int lcd_console_init(void) rt_kprintf("no console dev!\n"); return 0; } - + if(console_dev->ref_count >= 1) { rt_kprintf("lcd console has open!\n"); @@ -209,7 +209,7 @@ int lcd_console_init(void) rt_device_open(console_dev,RT_DEVICE_OFLAG_RDWR); rt_device_control(console_dev, RTGRAPHIC_CTRL_GET_INFO, &info); - + virt_buffer = (rt_uint8_t* )rt_malloc(info.width * info.height * (info.bits_per_pixel/8)); rt_memset(virt_buffer, 0 , info.width * info.height * (info.bits_per_pixel/8)); console_fb.width = info.width; @@ -246,7 +246,7 @@ int lcd_console_init(void) * #ifdef USING_LCD_CONSOLE * fb_print((char*)rt_log_buf); * #endif - * + * * remove rt_console_set_device(CONSOLE_NAME); */ rt_console_set_device(CONSOLE_NAME); diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h index ebe6afa068..2bc7a1ceb1 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h +++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,10 +15,10 @@ #define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b))) #define COLOR_BLACK RGB(0, 0, 0) -#define COLOR_GREEN RGB(0, 255, 0) -#define COLOR_CYAN RGB(0, 255, 255) -#define COLOR_RED RGB(255, 0, 0) -#define COLOR_YELLOW RGB(255, 255, 0) +#define COLOR_GREEN RGB(0, 255, 0) +#define COLOR_CYAN RGB(0, 255, 255) +#define COLOR_RED RGB(255, 0, 0) +#define COLOR_YELLOW RGB(255, 255, 0) #define COLOR_WHITE RGB(255, 255, 255) #define CONSOLE_WHITE_32 COLOR_WHITE diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h index 7ef56d7e3c..55610713d9 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h +++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.c b/bsp/raspberry-pi/raspi4-32/driver/mbox.c index 0f993f945a..ecb357c82d 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.c +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.c @@ -1,6 +1,6 @@ /* * File : mbox.c - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #include "mmu.h" //volatile unsigned int __attribute__((aligned(16))) mbox[36]; volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR; -#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) /** * Make a mailbox call. Returns 0 on failure, non-zero on success @@ -53,8 +53,8 @@ int bcm271x_mbox_get_touch(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_GET_TOUCHBUF; + + mbox[2] = MBOX_TAG_GET_TOUCHBUF; mbox[3] = 4; // buffer size mbox[4] = 0; // len @@ -76,7 +76,7 @@ int bcm271x_notify_reboot(void) mbox[4] = 0x00000000; // size of the data mbox[5] = 0x00000000; // request - mbox[6] = MBOX_TAG_LAST; + mbox[6] = MBOX_TAG_LAST; mbox_call(8, MMU_DISABLE); return 0; } @@ -89,7 +89,7 @@ int bcm271x_notify_xhci_reset(void) mbox[3] = 0x00000004; // length + 4 mbox[4] = 0x00000004; // size of the data mbox[5] = 0x00100000; // request - mbox[6] = MBOX_TAG_LAST; + mbox[6] = MBOX_TAG_LAST; mbox_call(8, MMU_DISABLE); return 0; } @@ -98,7 +98,7 @@ int bcm271x_gpu_enable(void) { mbox[0] = 12*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; mbox[3] = 0x00000008; // (the tag id) mbox[4] = 0x00000008; // (the tag id) @@ -117,12 +117,12 @@ int bcm271x_mbox_hardware_get_model(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL; mbox[3] = 4; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -135,12 +135,12 @@ int bcm271x_mbox_hardware_get_revison(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_REV; + + mbox[2] = MBOX_TAG_HARDWARE_GET_REV; mbox[3] = 4; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -153,12 +153,12 @@ int bcm271x_mbox_hardware_get_mac_address(uint8_t * mac) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS; + + mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS; mbox[3] = 6; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -179,12 +179,12 @@ int bcm271x_mbox_hardware_get_serial(rt_uint64_t* sn) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL; + + mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL; mbox[3] = 8; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -199,12 +199,12 @@ int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY; + + mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY; mbox[3] = 8; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -212,7 +212,7 @@ int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size) *base = mbox[5]; *size = mbox[6]; - + return 0; } @@ -221,12 +221,12 @@ int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY; mbox[3] = 8; // buffer size mbox[4] = 0; // len - mbox[5] = 0; + mbox[5] = 0; mbox[6] = 0; mbox[7] = MBOX_TAG_LAST; @@ -234,7 +234,7 @@ int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size) *base = mbox[5]; *size = mbox[6]; - + return 0; } @@ -242,8 +242,8 @@ int bcm271x_mbox_clock_get_turbo(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; + + mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -265,8 +265,8 @@ int bcm271x_mbox_clock_set_turbo(int level) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_SET_TURBO; + + mbox[2] = MBOX_TAG_CLOCK_SET_TURBO; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -288,7 +288,7 @@ int bcm271x_mbox_clock_get_state(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_GET_STATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -311,7 +311,7 @@ int bcm271x_mbox_clock_set_state(int id, int state) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_SET_STATE; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -334,8 +334,8 @@ int bcm271x_mbox_clock_get_rate(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_GET_RATE; + + mbox[2] = MBOX_TAG_CLOCK_GET_RATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -357,7 +357,7 @@ int bcm271x_mbox_clock_set_rate(int id, int rate) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -380,7 +380,7 @@ int bcm271x_mbox_clock_get_max_rate(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -403,8 +403,8 @@ int bcm271x_mbox_clock_get_min_rate(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - - mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; + + mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -426,7 +426,7 @@ int bcm271x_mbox_power_get_state(int id) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_POWER_GET_STATE; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -449,7 +449,7 @@ int bcm271x_mbox_power_set_state(int id, int state) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_POWER_SET_STATE; mbox[3] = 8; // buffer size mbox[4] = 8; // len @@ -472,7 +472,7 @@ int bcm271x_mbox_temp_get(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_TEMP_GET; mbox[3] = 8; // buffer size mbox[4] = 4; // len @@ -495,7 +495,7 @@ int bcm271x_mbox_temp_get_max(void) { mbox[0] = 8*4; // length of the message mbox[1] = MBOX_REQUEST; // this is a request message - + mbox[2] = MBOX_TAG_TEMP_GET_MAX; mbox[3] = 8; // buffer size mbox[4] = 4; // len diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.h b/bsp/raspberry-pi/raspi4-32/driver/mbox.h index 7a05597de4..2c69bcf55a 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.h +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index 72e212ff85..bba81ea311 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -149,8 +149,8 @@ typedef enum { } while (0) \ //External Mass Media Controller (SD Card) -#define MMC0_BASE_ADDR (PER_BASE+0x300000) -#define MMC2_BASE_ADDR (PER_BASE+0x340000) +#define MMC0_BASE_ADDR (PER_BASE+0x300000) +#define MMC2_BASE_ADDR (PER_BASE+0x340000) #define ETH_IRQ (160+29) @@ -162,7 +162,7 @@ typedef enum { #define BSC5_BASE_OFFSET (0x205A80) #define BSC6_BASE_OFFSET (0x205C00) -//BSC2 and BSC7 masters are dedicated for use by the +//BSC2 and BSC7 masters are dedicated for use by the //HDMI interfaces and should not be accessed byuser programs. #define BSC0_BASE (PER_BASE + BSC0_BASE_OFFSET) #define BSC1_BASE (PER_BASE + BSC1_BASE_OFFSET) diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c index 894ef1f25c..3f9dbb83ad 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c +++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -58,7 +58,7 @@ static void dsi_touch_thread_entry(void *param) rt_kprintf("init dsi touch err!\n"); return; } - + while (1) { struct touch_regs *regs = (struct touch_regs *)touchbuf; @@ -73,7 +73,7 @@ static void dsi_touch_thread_entry(void *param) { touch_state = 0; } - rt_thread_mdelay(50); + rt_thread_mdelay(50); } } diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h index 6d6439f199..ea70191dde 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h +++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c index 489701f079..5911b5b6e3 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c +++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -104,7 +104,7 @@ no pressed:(0x800,0xfff) ------------------------------------ */ #define XMIN 0x800 -#define YMAX 0xfff +#define YMAX 0xfff void read_tp(void *dev, rt_uint16_t *x, rt_uint16_t *y) { struct rt_spi_device *touch_dev = (struct rt_spi_device *)dev; diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h index 5b28c0a7dd..0a88546250 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h +++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-64/applications/main.c b/bsp/raspberry-pi/raspi4-64/applications/main.c index 9664e67d01..9400e2a598 100644 --- a/bsp/raspberry-pi/raspi4-64/applications/main.c +++ b/bsp/raspberry-pi/raspi4-64/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.c b/bsp/raspberry-pi/raspi4-64/driver/board.c index 79a24d184f..0fbd4921f8 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/board.c +++ b/bsp/raspberry-pi/raspi4-64/driver/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -44,7 +44,7 @@ void rt_hw_timer_init(void) timerStep = rt_hw_get_gtimer_frq(); __DSB(); timerStep /= RT_TICK_PER_SECOND; - + rt_hw_gtimer_enable(); rt_hw_set_gtimer_val(timerStep); core0_timer_enable_interrupt_controller(); @@ -56,7 +56,7 @@ void idle_wfi(void) } /** - * Initialize the Hardware related stuffs. Called from rtthread_startup() + * Initialize the Hardware related stuffs. Called from rtthread_startup() * after interrupt disabled. */ void rt_hw_board_init(void) diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.h b/bsp/raspberry-pi/raspi4-64/driver/board.h index d675cc658e..29019514b9 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/board.h +++ b/bsp/raspberry-pi/raspi4-64/driver/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c index bba20a86a4..f526ff99e6 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -71,7 +71,7 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t valu { GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); } - + } } diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h index c4658fcebb..3627b51593 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c index 6a70cdfb3a..597682df34 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c +++ b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -117,7 +117,7 @@ static const struct rt_uart_ops _uart_ops = static void rt_hw_uart_isr(int irqno, void *param) { - struct rt_serial_device *serial = (struct rt_serial_device*)param; + struct rt_serial_device *serial = (struct rt_serial_device*)param; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; } diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h index 714043efd3..1dfb9b7e04 100644 --- a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h +++ b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config.h index 1bbb838481..24c81ec14b 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_config.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config.h @@ -194,7 +194,7 @@ typedef unsigned int uintptr_t; #define SDL_VIDEO_RENDER_D3D 1 #endif #ifndef SDL_VIDEO_RENDER_D3D11 -#define SDL_VIDEO_RENDER_D3D11 0 +#define SDL_VIDEO_RENDER_D3D11 0 #endif /* Enable OpenGL support */ diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h index 361bad8b77..27cfd9540c 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h @@ -108,7 +108,7 @@ #define HAVE_SETJMP 1 #define HAVE_NANOSLEEP 1 #define HAVE_SYSCONF 1 -#define HAVE_CLOCK_GETTIME 1 +#define HAVE_CLOCK_GETTIME 1 #define SIZEOF_VOIDP 4 diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h index 2456c843fe..2a5724a4c9 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h @@ -185,7 +185,7 @@ typedef unsigned int uintptr_t; #define SDL_VIDEO_RENDER_D3D 1 #endif #ifndef SDL_VIDEO_RENDER_D3D11 -#define SDL_VIDEO_RENDER_D3D11 0 +#define SDL_VIDEO_RENDER_D3D11 0 #endif /* Enable OpenGL support */ diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h index 24f9e17f20..621c8116b6 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h @@ -44,7 +44,7 @@ #if !defined(_STDINT_H_) && (!defined(HAVE_STDINT_H) || !_HAVE_STDINT_H) #if defined(__GNUC__) || defined(__DMC__) || defined(__WATCOMC__) -#define HAVE_STDINT_H 1 +#define HAVE_STDINT_H 1 #elif defined(_MSC_VER) typedef signed __int8 int8_t; typedef unsigned __int8 uint8_t; @@ -121,13 +121,13 @@ typedef unsigned int uintptr_t; #define HAVE_STRLEN 1 #define HAVE__STRREV 1 #define HAVE__STRUPR 1 -//#define HAVE__STRLWR 1 // TODO, WinRT: consider using _strlwr_s instead +//#define HAVE__STRLWR 1 // TODO, WinRT: consider using _strlwr_s instead #define HAVE_STRCHR 1 #define HAVE_STRRCHR 1 #define HAVE_STRSTR 1 //#define HAVE_ITOA 1 // TODO, WinRT: consider using _itoa_s instead -//#define HAVE__LTOA 1 // TODO, WinRT: consider using _ltoa_s instead -//#define HAVE__ULTOA 1 // TODO, WinRT: consider using _ultoa_s instead +//#define HAVE__LTOA 1 // TODO, WinRT: consider using _ltoa_s instead +//#define HAVE__ULTOA 1 // TODO, WinRT: consider using _ultoa_s instead #define HAVE_STRTOL 1 #define HAVE_STRTOUL 1 //#define HAVE_STRTOLL 1 @@ -139,7 +139,7 @@ typedef unsigned int uintptr_t; #define HAVE__STRICMP 1 #define HAVE__STRNICMP 1 #define HAVE_VSNPRINTF 1 -//#define HAVE_SSCANF 1 // TODO, WinRT: consider using sscanf_s instead +//#define HAVE_SSCANF 1 // TODO, WinRT: consider using sscanf_s instead #define HAVE_M_PI 1 #define HAVE_ATAN 1 #define HAVE_ATAN2 1 @@ -162,21 +162,21 @@ typedef unsigned int uintptr_t; #define HAVE__FSEEKI64 1 /* Enable various audio drivers */ -#define SDL_AUDIO_DRIVER_XAUDIO2 1 -#define SDL_AUDIO_DRIVER_DISK 1 -#define SDL_AUDIO_DRIVER_DUMMY 1 +#define SDL_AUDIO_DRIVER_XAUDIO2 1 +#define SDL_AUDIO_DRIVER_DISK 1 +#define SDL_AUDIO_DRIVER_DUMMY 1 /* Enable various input drivers */ #if WINAPI_FAMILY == WINAPI_FAMILY_PHONE_APP #define SDL_JOYSTICK_DISABLED 1 -#define SDL_HAPTIC_DISABLED 1 +#define SDL_HAPTIC_DISABLED 1 #else #define SDL_JOYSTICK_XINPUT 1 #define SDL_HAPTIC_XINPUT 1 #endif /* Enable various shared object loading systems */ -#define SDL_LOADSO_WINDOWS 1 +#define SDL_LOADSO_WINDOWS 1 /* Enable various threading systems */ #if (NTDDI_VERSION >= NTDDI_WINBLUE) @@ -187,10 +187,10 @@ typedef unsigned int uintptr_t; #endif /* Enable various timer systems */ -#define SDL_TIMER_WINDOWS 1 +#define SDL_TIMER_WINDOWS 1 /* Enable various video drivers */ -#define SDL_VIDEO_DRIVER_WINRT 1 +#define SDL_VIDEO_DRIVER_WINRT 1 #define SDL_VIDEO_DRIVER_DUMMY 1 /* Enable OpenGL ES 2.0 (via a modified ANGLE library) */ @@ -209,7 +209,7 @@ typedef unsigned int uintptr_t; /* Enable assembly routines (Win64 doesn't have inline asm) */ #ifndef _WIN64 -#define SDL_ASSEMBLY_ROUTINES 1 +#define SDL_ASSEMBLY_ROUTINES 1 #endif #endif /* SDL_config_winrt_h_ */ diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h b/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h index c9215132ef..406e77e91e 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h @@ -116,7 +116,7 @@ typedef struct SDL_GameControllerButtonBind * A community sourced database of controllers is available at https://raw.github.com/gabomdq/SDL_GameControllerDB/master/gamecontrollerdb.txt * * If \c freerw is non-zero, the stream will be closed after being read. - * + * * \return number of mappings added, -1 on error */ extern DECLSPEC int SDLCALL SDL_GameControllerAddMappingsFromRW(SDL_RWops * rw, int freerw); diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h b/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h index 007a4bee05..7d43814b6b 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h @@ -153,7 +153,7 @@ extern "C" { #define SDL_HINT_RENDER_VSYNC "SDL_RENDER_VSYNC" /** - * \brief A variable controlling whether the screensaver is enabled. + * \brief A variable controlling whether the screensaver is enabled. * * This variable can be set to the following values: * "0" - Disable screensaver @@ -211,7 +211,7 @@ extern "C" { #define SDL_HINT_VIDEO_X11_NET_WM_PING "SDL_VIDEO_X11_NET_WM_PING" /** - * \brief A variable controlling whether the window frame and title bar are interactive when the cursor is hidden + * \brief A variable controlling whether the window frame and title bar are interactive when the cursor is hidden * * This variable can be set to the following values: * "0" - The window frame is not interactive when the cursor is hidden (no move, resize, etc) @@ -222,13 +222,13 @@ extern "C" { #define SDL_HINT_WINDOW_FRAME_USABLE_WHILE_CURSOR_HIDDEN "SDL_WINDOW_FRAME_USABLE_WHILE_CURSOR_HIDDEN" /** - * \brief A variable to specify custom icon resource id from RC file on Windows platform + * \brief A variable to specify custom icon resource id from RC file on Windows platform */ #define SDL_HINT_WINDOWS_INTRESOURCE_ICON "SDL_WINDOWS_INTRESOURCE_ICON" #define SDL_HINT_WINDOWS_INTRESOURCE_ICON_SMALL "SDL_WINDOWS_INTRESOURCE_ICON_SMALL" /** - * \brief A variable controlling whether the windows message loop is processed by SDL + * \brief A variable controlling whether the windows message loop is processed by SDL * * This variable can be set to the following values: * "0" - The window message loop is not run @@ -528,9 +528,9 @@ extern "C" { /** * \brief A variable that is the address of another SDL_Window* (as a hex string formatted with "%p"). -* +* * If this hint is set before SDL_CreateWindowFrom() and the SDL_Window* it is set to has -* SDL_WINDOW_OPENGL set (and running on WGL only, currently), then two things will occur on the newly +* SDL_WINDOW_OPENGL set (and running on WGL only, currently), then two things will occur on the newly * created SDL_Window: * * 1. Its pixel format will be set to the same pixel format as this SDL_Window. This is @@ -682,7 +682,7 @@ extern "C" { * By default this hint is not set and the APK expansion files are not searched. */ #define SDL_HINT_ANDROID_APK_EXPANSION_MAIN_FILE_VERSION "SDL_ANDROID_APK_EXPANSION_MAIN_FILE_VERSION" - + /** * \brief Android APK expansion patch file version. Should be a string number like "1", "2" etc. * @@ -700,9 +700,9 @@ extern "C" { * * The variable can be set to the following values: * "0" - SDL_TEXTEDITING events are sent, and it is the application's - * responsibility to render the text from these events and + * responsibility to render the text from these events and * differentiate it somehow from committed text. (default) - * "1" - If supported by the IME then SDL_TEXTEDITING events are not sent, + * "1" - If supported by the IME then SDL_TEXTEDITING events are not sent, * and text that is being composed will be rendered in its own UI. */ #define SDL_HINT_IME_INTERNAL_EDITING "SDL_IME_INTERNAL_EDITING" @@ -752,7 +752,7 @@ extern "C" { * "0" - SDL will generate a window-close event when it sees Alt+F4. * "1" - SDL will only do normal key handling for Alt+F4. */ -#define SDL_HINT_WINDOWS_NO_CLOSE_ON_ALT_F4 "SDL_WINDOWS_NO_CLOSE_ON_ALT_F4" +#define SDL_HINT_WINDOWS_NO_CLOSE_ON_ALT_F4 "SDL_WINDOWS_NO_CLOSE_ON_ALT_F4" /** * \brief Prevent SDL from using version 4 of the bitmap header when saving BMPs. diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_main.h b/bsp/simulator/SDL2-2.0.7/include/SDL_main.h index 2af32360f7..719f6726a0 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_main.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_main.h @@ -69,9 +69,9 @@ #elif defined(__NACL__) /* On NACL we use ppapi_simple to set up the application helper code, - then wait for the first PSE_INSTANCE_DIDCHANGEVIEW event before + then wait for the first PSE_INSTANCE_DIDCHANGEVIEW event before starting the user main function. - All user code is run in a separate thread by ppapi_simple, thus + All user code is run in a separate thread by ppapi_simple, thus allowing for blocking io to take place via nacl_io */ #define SDL_MAIN_NEEDED diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h b/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h index 314dd57eda..8c60791b32 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h @@ -90,7 +90,7 @@ # define GLAPI extern # endif /* _STATIC_MESA support */ # if defined(__MINGW32__) && defined(GL_NO_STDCALL) || defined(UNDER_CE) /* The generated DLLs by MingW with STDCALL are not compatible with the ones done by Microsoft's compilers */ -# define GLAPIENTRY +# define GLAPIENTRY # else # define GLAPIENTRY __stdcall # endif @@ -173,21 +173,21 @@ extern "C" { /* * Datatypes */ -typedef unsigned int GLenum; -typedef unsigned char GLboolean; -typedef unsigned int GLbitfield; -typedef void GLvoid; -typedef signed char GLbyte; /* 1-byte signed */ -typedef short GLshort; /* 2-byte signed */ -typedef int GLint; /* 4-byte signed */ -typedef unsigned char GLubyte; /* 1-byte unsigned */ -typedef unsigned short GLushort; /* 2-byte unsigned */ -typedef unsigned int GLuint; /* 4-byte unsigned */ -typedef int GLsizei; /* 4-byte signed */ -typedef float GLfloat; /* single precision float */ -typedef float GLclampf; /* single precision float in [0,1] */ -typedef double GLdouble; /* double precision float */ -typedef double GLclampd; /* double precision float in [0,1] */ +typedef unsigned int GLenum; +typedef unsigned char GLboolean; +typedef unsigned int GLbitfield; +typedef void GLvoid; +typedef signed char GLbyte; /* 1-byte signed */ +typedef short GLshort; /* 2-byte signed */ +typedef int GLint; /* 4-byte signed */ +typedef unsigned char GLubyte; /* 1-byte unsigned */ +typedef unsigned short GLushort; /* 2-byte unsigned */ +typedef unsigned int GLuint; /* 4-byte unsigned */ +typedef int GLsizei; /* 4-byte signed */ +typedef float GLfloat; /* single precision float */ +typedef float GLclampf; /* single precision float in [0,1] */ +typedef double GLdouble; /* double precision float */ +typedef double GLclampd; /* double precision float in [0,1] */ @@ -196,603 +196,603 @@ typedef double GLclampd; /* double precision float in [0,1] */ */ /* Boolean values */ -#define GL_FALSE 0 -#define GL_TRUE 1 +#define GL_FALSE 0 +#define GL_TRUE 1 /* Data types */ -#define GL_BYTE 0x1400 -#define GL_UNSIGNED_BYTE 0x1401 -#define GL_SHORT 0x1402 -#define GL_UNSIGNED_SHORT 0x1403 -#define GL_INT 0x1404 -#define GL_UNSIGNED_INT 0x1405 -#define GL_FLOAT 0x1406 -#define GL_2_BYTES 0x1407 -#define GL_3_BYTES 0x1408 -#define GL_4_BYTES 0x1409 -#define GL_DOUBLE 0x140A +#define GL_BYTE 0x1400 +#define GL_UNSIGNED_BYTE 0x1401 +#define GL_SHORT 0x1402 +#define GL_UNSIGNED_SHORT 0x1403 +#define GL_INT 0x1404 +#define GL_UNSIGNED_INT 0x1405 +#define GL_FLOAT 0x1406 +#define GL_2_BYTES 0x1407 +#define GL_3_BYTES 0x1408 +#define GL_4_BYTES 0x1409 +#define GL_DOUBLE 0x140A /* Primitives */ -#define GL_POINTS 0x0000 -#define GL_LINES 0x0001 -#define GL_LINE_LOOP 0x0002 -#define GL_LINE_STRIP 0x0003 -#define GL_TRIANGLES 0x0004 -#define GL_TRIANGLE_STRIP 0x0005 -#define GL_TRIANGLE_FAN 0x0006 -#define GL_QUADS 0x0007 -#define GL_QUAD_STRIP 0x0008 -#define GL_POLYGON 0x0009 +#define GL_POINTS 0x0000 +#define GL_LINES 0x0001 +#define GL_LINE_LOOP 0x0002 +#define GL_LINE_STRIP 0x0003 +#define GL_TRIANGLES 0x0004 +#define GL_TRIANGLE_STRIP 0x0005 +#define GL_TRIANGLE_FAN 0x0006 +#define GL_QUADS 0x0007 +#define GL_QUAD_STRIP 0x0008 +#define GL_POLYGON 0x0009 /* Vertex Arrays */ -#define GL_VERTEX_ARRAY 0x8074 -#define GL_NORMAL_ARRAY 0x8075 -#define GL_COLOR_ARRAY 0x8076 -#define GL_INDEX_ARRAY 0x8077 -#define GL_TEXTURE_COORD_ARRAY 0x8078 -#define GL_EDGE_FLAG_ARRAY 0x8079 -#define GL_VERTEX_ARRAY_SIZE 0x807A -#define GL_VERTEX_ARRAY_TYPE 0x807B -#define GL_VERTEX_ARRAY_STRIDE 0x807C -#define GL_NORMAL_ARRAY_TYPE 0x807E -#define GL_NORMAL_ARRAY_STRIDE 0x807F -#define GL_COLOR_ARRAY_SIZE 0x8081 -#define GL_COLOR_ARRAY_TYPE 0x8082 -#define GL_COLOR_ARRAY_STRIDE 0x8083 -#define GL_INDEX_ARRAY_TYPE 0x8085 -#define GL_INDEX_ARRAY_STRIDE 0x8086 -#define GL_TEXTURE_COORD_ARRAY_SIZE 0x8088 -#define GL_TEXTURE_COORD_ARRAY_TYPE 0x8089 -#define GL_TEXTURE_COORD_ARRAY_STRIDE 0x808A -#define GL_EDGE_FLAG_ARRAY_STRIDE 0x808C -#define GL_VERTEX_ARRAY_POINTER 0x808E -#define GL_NORMAL_ARRAY_POINTER 0x808F -#define GL_COLOR_ARRAY_POINTER 0x8090 -#define GL_INDEX_ARRAY_POINTER 0x8091 -#define GL_TEXTURE_COORD_ARRAY_POINTER 0x8092 -#define GL_EDGE_FLAG_ARRAY_POINTER 0x8093 -#define GL_V2F 0x2A20 -#define GL_V3F 0x2A21 -#define GL_C4UB_V2F 0x2A22 -#define GL_C4UB_V3F 0x2A23 -#define GL_C3F_V3F 0x2A24 -#define GL_N3F_V3F 0x2A25 -#define GL_C4F_N3F_V3F 0x2A26 -#define GL_T2F_V3F 0x2A27 -#define GL_T4F_V4F 0x2A28 -#define GL_T2F_C4UB_V3F 0x2A29 -#define GL_T2F_C3F_V3F 0x2A2A -#define GL_T2F_N3F_V3F 0x2A2B -#define GL_T2F_C4F_N3F_V3F 0x2A2C -#define GL_T4F_C4F_N3F_V4F 0x2A2D +#define GL_VERTEX_ARRAY 0x8074 +#define GL_NORMAL_ARRAY 0x8075 +#define GL_COLOR_ARRAY 0x8076 +#define GL_INDEX_ARRAY 0x8077 +#define GL_TEXTURE_COORD_ARRAY 0x8078 +#define GL_EDGE_FLAG_ARRAY 0x8079 +#define GL_VERTEX_ARRAY_SIZE 0x807A +#define GL_VERTEX_ARRAY_TYPE 0x807B +#define GL_VERTEX_ARRAY_STRIDE 0x807C +#define GL_NORMAL_ARRAY_TYPE 0x807E +#define GL_NORMAL_ARRAY_STRIDE 0x807F +#define GL_COLOR_ARRAY_SIZE 0x8081 +#define GL_COLOR_ARRAY_TYPE 0x8082 +#define GL_COLOR_ARRAY_STRIDE 0x8083 +#define GL_INDEX_ARRAY_TYPE 0x8085 +#define GL_INDEX_ARRAY_STRIDE 0x8086 +#define GL_TEXTURE_COORD_ARRAY_SIZE 0x8088 +#define GL_TEXTURE_COORD_ARRAY_TYPE 0x8089 +#define GL_TEXTURE_COORD_ARRAY_STRIDE 0x808A +#define GL_EDGE_FLAG_ARRAY_STRIDE 0x808C +#define GL_VERTEX_ARRAY_POINTER 0x808E +#define GL_NORMAL_ARRAY_POINTER 0x808F +#define GL_COLOR_ARRAY_POINTER 0x8090 +#define GL_INDEX_ARRAY_POINTER 0x8091 +#define GL_TEXTURE_COORD_ARRAY_POINTER 0x8092 +#define GL_EDGE_FLAG_ARRAY_POINTER 0x8093 +#define GL_V2F 0x2A20 +#define GL_V3F 0x2A21 +#define GL_C4UB_V2F 0x2A22 +#define GL_C4UB_V3F 0x2A23 +#define GL_C3F_V3F 0x2A24 +#define GL_N3F_V3F 0x2A25 +#define GL_C4F_N3F_V3F 0x2A26 +#define GL_T2F_V3F 0x2A27 +#define GL_T4F_V4F 0x2A28 +#define GL_T2F_C4UB_V3F 0x2A29 +#define GL_T2F_C3F_V3F 0x2A2A +#define GL_T2F_N3F_V3F 0x2A2B +#define GL_T2F_C4F_N3F_V3F 0x2A2C +#define GL_T4F_C4F_N3F_V4F 0x2A2D /* Matrix Mode */ -#define GL_MATRIX_MODE 0x0BA0 -#define GL_MODELVIEW 0x1700 -#define GL_PROJECTION 0x1701 -#define GL_TEXTURE 0x1702 +#define GL_MATRIX_MODE 0x0BA0 +#define GL_MODELVIEW 0x1700 +#define GL_PROJECTION 0x1701 +#define GL_TEXTURE 0x1702 /* Points */ -#define GL_POINT_SMOOTH 0x0B10 -#define GL_POINT_SIZE 0x0B11 -#define GL_POINT_SIZE_GRANULARITY 0x0B13 -#define GL_POINT_SIZE_RANGE 0x0B12 +#define GL_POINT_SMOOTH 0x0B10 +#define GL_POINT_SIZE 0x0B11 +#define GL_POINT_SIZE_GRANULARITY 0x0B13 +#define GL_POINT_SIZE_RANGE 0x0B12 /* Lines */ -#define GL_LINE_SMOOTH 0x0B20 -#define GL_LINE_STIPPLE 0x0B24 -#define GL_LINE_STIPPLE_PATTERN 0x0B25 -#define GL_LINE_STIPPLE_REPEAT 0x0B26 -#define GL_LINE_WIDTH 0x0B21 -#define GL_LINE_WIDTH_GRANULARITY 0x0B23 -#define GL_LINE_WIDTH_RANGE 0x0B22 +#define GL_LINE_SMOOTH 0x0B20 +#define GL_LINE_STIPPLE 0x0B24 +#define GL_LINE_STIPPLE_PATTERN 0x0B25 +#define GL_LINE_STIPPLE_REPEAT 0x0B26 +#define GL_LINE_WIDTH 0x0B21 +#define GL_LINE_WIDTH_GRANULARITY 0x0B23 +#define GL_LINE_WIDTH_RANGE 0x0B22 /* Polygons */ -#define GL_POINT 0x1B00 -#define GL_LINE 0x1B01 -#define GL_FILL 0x1B02 -#define GL_CW 0x0900 -#define GL_CCW 0x0901 -#define GL_FRONT 0x0404 -#define GL_BACK 0x0405 -#define GL_POLYGON_MODE 0x0B40 -#define GL_POLYGON_SMOOTH 0x0B41 -#define GL_POLYGON_STIPPLE 0x0B42 -#define GL_EDGE_FLAG 0x0B43 -#define GL_CULL_FACE 0x0B44 -#define GL_CULL_FACE_MODE 0x0B45 -#define GL_FRONT_FACE 0x0B46 -#define GL_POLYGON_OFFSET_FACTOR 0x8038 -#define GL_POLYGON_OFFSET_UNITS 0x2A00 -#define GL_POLYGON_OFFSET_POINT 0x2A01 -#define GL_POLYGON_OFFSET_LINE 0x2A02 -#define GL_POLYGON_OFFSET_FILL 0x8037 +#define GL_POINT 0x1B00 +#define GL_LINE 0x1B01 +#define GL_FILL 0x1B02 +#define GL_CW 0x0900 +#define GL_CCW 0x0901 +#define GL_FRONT 0x0404 +#define GL_BACK 0x0405 +#define GL_POLYGON_MODE 0x0B40 +#define GL_POLYGON_SMOOTH 0x0B41 +#define GL_POLYGON_STIPPLE 0x0B42 +#define GL_EDGE_FLAG 0x0B43 +#define GL_CULL_FACE 0x0B44 +#define GL_CULL_FACE_MODE 0x0B45 +#define GL_FRONT_FACE 0x0B46 +#define GL_POLYGON_OFFSET_FACTOR 0x8038 +#define GL_POLYGON_OFFSET_UNITS 0x2A00 +#define GL_POLYGON_OFFSET_POINT 0x2A01 +#define GL_POLYGON_OFFSET_LINE 0x2A02 +#define GL_POLYGON_OFFSET_FILL 0x8037 /* Display Lists */ -#define GL_COMPILE 0x1300 -#define GL_COMPILE_AND_EXECUTE 0x1301 -#define GL_LIST_BASE 0x0B32 -#define GL_LIST_INDEX 0x0B33 -#define GL_LIST_MODE 0x0B30 +#define GL_COMPILE 0x1300 +#define GL_COMPILE_AND_EXECUTE 0x1301 +#define GL_LIST_BASE 0x0B32 +#define GL_LIST_INDEX 0x0B33 +#define GL_LIST_MODE 0x0B30 /* Depth buffer */ -#define GL_NEVER 0x0200 -#define GL_LESS 0x0201 -#define GL_EQUAL 0x0202 -#define GL_LEQUAL 0x0203 -#define GL_GREATER 0x0204 -#define GL_NOTEQUAL 0x0205 -#define GL_GEQUAL 0x0206 -#define GL_ALWAYS 0x0207 -#define GL_DEPTH_TEST 0x0B71 -#define GL_DEPTH_BITS 0x0D56 -#define GL_DEPTH_CLEAR_VALUE 0x0B73 -#define GL_DEPTH_FUNC 0x0B74 -#define GL_DEPTH_RANGE 0x0B70 -#define GL_DEPTH_WRITEMASK 0x0B72 -#define GL_DEPTH_COMPONENT 0x1902 +#define GL_NEVER 0x0200 +#define GL_LESS 0x0201 +#define GL_EQUAL 0x0202 +#define GL_LEQUAL 0x0203 +#define GL_GREATER 0x0204 +#define GL_NOTEQUAL 0x0205 +#define GL_GEQUAL 0x0206 +#define GL_ALWAYS 0x0207 +#define GL_DEPTH_TEST 0x0B71 +#define GL_DEPTH_BITS 0x0D56 +#define GL_DEPTH_CLEAR_VALUE 0x0B73 +#define GL_DEPTH_FUNC 0x0B74 +#define GL_DEPTH_RANGE 0x0B70 +#define GL_DEPTH_WRITEMASK 0x0B72 +#define GL_DEPTH_COMPONENT 0x1902 /* Lighting */ -#define GL_LIGHTING 0x0B50 -#define GL_LIGHT0 0x4000 -#define GL_LIGHT1 0x4001 -#define GL_LIGHT2 0x4002 -#define GL_LIGHT3 0x4003 -#define GL_LIGHT4 0x4004 -#define GL_LIGHT5 0x4005 -#define GL_LIGHT6 0x4006 -#define GL_LIGHT7 0x4007 -#define GL_SPOT_EXPONENT 0x1205 -#define GL_SPOT_CUTOFF 0x1206 -#define GL_CONSTANT_ATTENUATION 0x1207 -#define GL_LINEAR_ATTENUATION 0x1208 -#define GL_QUADRATIC_ATTENUATION 0x1209 -#define GL_AMBIENT 0x1200 -#define GL_DIFFUSE 0x1201 -#define GL_SPECULAR 0x1202 -#define GL_SHININESS 0x1601 -#define GL_EMISSION 0x1600 -#define GL_POSITION 0x1203 -#define GL_SPOT_DIRECTION 0x1204 -#define GL_AMBIENT_AND_DIFFUSE 0x1602 -#define GL_COLOR_INDEXES 0x1603 -#define GL_LIGHT_MODEL_TWO_SIDE 0x0B52 -#define GL_LIGHT_MODEL_LOCAL_VIEWER 0x0B51 -#define GL_LIGHT_MODEL_AMBIENT 0x0B53 -#define GL_FRONT_AND_BACK 0x0408 -#define GL_SHADE_MODEL 0x0B54 -#define GL_FLAT 0x1D00 -#define GL_SMOOTH 0x1D01 -#define GL_COLOR_MATERIAL 0x0B57 -#define GL_COLOR_MATERIAL_FACE 0x0B55 -#define GL_COLOR_MATERIAL_PARAMETER 0x0B56 -#define GL_NORMALIZE 0x0BA1 +#define GL_LIGHTING 0x0B50 +#define GL_LIGHT0 0x4000 +#define GL_LIGHT1 0x4001 +#define GL_LIGHT2 0x4002 +#define GL_LIGHT3 0x4003 +#define GL_LIGHT4 0x4004 +#define GL_LIGHT5 0x4005 +#define GL_LIGHT6 0x4006 +#define GL_LIGHT7 0x4007 +#define GL_SPOT_EXPONENT 0x1205 +#define GL_SPOT_CUTOFF 0x1206 +#define GL_CONSTANT_ATTENUATION 0x1207 +#define GL_LINEAR_ATTENUATION 0x1208 +#define GL_QUADRATIC_ATTENUATION 0x1209 +#define GL_AMBIENT 0x1200 +#define GL_DIFFUSE 0x1201 +#define GL_SPECULAR 0x1202 +#define GL_SHININESS 0x1601 +#define GL_EMISSION 0x1600 +#define GL_POSITION 0x1203 +#define GL_SPOT_DIRECTION 0x1204 +#define GL_AMBIENT_AND_DIFFUSE 0x1602 +#define GL_COLOR_INDEXES 0x1603 +#define GL_LIGHT_MODEL_TWO_SIDE 0x0B52 +#define GL_LIGHT_MODEL_LOCAL_VIEWER 0x0B51 +#define GL_LIGHT_MODEL_AMBIENT 0x0B53 +#define GL_FRONT_AND_BACK 0x0408 +#define GL_SHADE_MODEL 0x0B54 +#define GL_FLAT 0x1D00 +#define GL_SMOOTH 0x1D01 +#define GL_COLOR_MATERIAL 0x0B57 +#define GL_COLOR_MATERIAL_FACE 0x0B55 +#define GL_COLOR_MATERIAL_PARAMETER 0x0B56 +#define GL_NORMALIZE 0x0BA1 /* User clipping planes */ -#define GL_CLIP_PLANE0 0x3000 -#define GL_CLIP_PLANE1 0x3001 -#define GL_CLIP_PLANE2 0x3002 -#define GL_CLIP_PLANE3 0x3003 -#define GL_CLIP_PLANE4 0x3004 -#define GL_CLIP_PLANE5 0x3005 +#define GL_CLIP_PLANE0 0x3000 +#define GL_CLIP_PLANE1 0x3001 +#define GL_CLIP_PLANE2 0x3002 +#define GL_CLIP_PLANE3 0x3003 +#define GL_CLIP_PLANE4 0x3004 +#define GL_CLIP_PLANE5 0x3005 /* Accumulation buffer */ -#define GL_ACCUM_RED_BITS 0x0D58 -#define GL_ACCUM_GREEN_BITS 0x0D59 -#define GL_ACCUM_BLUE_BITS 0x0D5A -#define GL_ACCUM_ALPHA_BITS 0x0D5B -#define GL_ACCUM_CLEAR_VALUE 0x0B80 -#define GL_ACCUM 0x0100 -#define GL_ADD 0x0104 -#define GL_LOAD 0x0101 -#define GL_MULT 0x0103 -#define GL_RETURN 0x0102 +#define GL_ACCUM_RED_BITS 0x0D58 +#define GL_ACCUM_GREEN_BITS 0x0D59 +#define GL_ACCUM_BLUE_BITS 0x0D5A +#define GL_ACCUM_ALPHA_BITS 0x0D5B +#define GL_ACCUM_CLEAR_VALUE 0x0B80 +#define GL_ACCUM 0x0100 +#define GL_ADD 0x0104 +#define GL_LOAD 0x0101 +#define GL_MULT 0x0103 +#define GL_RETURN 0x0102 /* Alpha testing */ -#define GL_ALPHA_TEST 0x0BC0 -#define GL_ALPHA_TEST_REF 0x0BC2 -#define GL_ALPHA_TEST_FUNC 0x0BC1 +#define GL_ALPHA_TEST 0x0BC0 +#define GL_ALPHA_TEST_REF 0x0BC2 +#define GL_ALPHA_TEST_FUNC 0x0BC1 /* Blending */ -#define GL_BLEND 0x0BE2 -#define GL_BLEND_SRC 0x0BE1 -#define GL_BLEND_DST 0x0BE0 -#define GL_ZERO 0 -#define GL_ONE 1 -#define GL_SRC_COLOR 0x0300 -#define GL_ONE_MINUS_SRC_COLOR 0x0301 -#define GL_SRC_ALPHA 0x0302 -#define GL_ONE_MINUS_SRC_ALPHA 0x0303 -#define GL_DST_ALPHA 0x0304 -#define GL_ONE_MINUS_DST_ALPHA 0x0305 -#define GL_DST_COLOR 0x0306 -#define GL_ONE_MINUS_DST_COLOR 0x0307 -#define GL_SRC_ALPHA_SATURATE 0x0308 +#define GL_BLEND 0x0BE2 +#define GL_BLEND_SRC 0x0BE1 +#define GL_BLEND_DST 0x0BE0 +#define GL_ZERO 0 +#define GL_ONE 1 +#define GL_SRC_COLOR 0x0300 +#define GL_ONE_MINUS_SRC_COLOR 0x0301 +#define GL_SRC_ALPHA 0x0302 +#define GL_ONE_MINUS_SRC_ALPHA 0x0303 +#define GL_DST_ALPHA 0x0304 +#define GL_ONE_MINUS_DST_ALPHA 0x0305 +#define GL_DST_COLOR 0x0306 +#define GL_ONE_MINUS_DST_COLOR 0x0307 +#define GL_SRC_ALPHA_SATURATE 0x0308 /* Render Mode */ -#define GL_FEEDBACK 0x1C01 -#define GL_RENDER 0x1C00 -#define GL_SELECT 0x1C02 +#define GL_FEEDBACK 0x1C01 +#define GL_RENDER 0x1C00 +#define GL_SELECT 0x1C02 /* Feedback */ -#define GL_2D 0x0600 -#define GL_3D 0x0601 -#define GL_3D_COLOR 0x0602 -#define GL_3D_COLOR_TEXTURE 0x0603 -#define GL_4D_COLOR_TEXTURE 0x0604 -#define GL_POINT_TOKEN 0x0701 -#define GL_LINE_TOKEN 0x0702 -#define GL_LINE_RESET_TOKEN 0x0707 -#define GL_POLYGON_TOKEN 0x0703 -#define GL_BITMAP_TOKEN 0x0704 -#define GL_DRAW_PIXEL_TOKEN 0x0705 -#define GL_COPY_PIXEL_TOKEN 0x0706 -#define GL_PASS_THROUGH_TOKEN 0x0700 -#define GL_FEEDBACK_BUFFER_POINTER 0x0DF0 -#define GL_FEEDBACK_BUFFER_SIZE 0x0DF1 -#define GL_FEEDBACK_BUFFER_TYPE 0x0DF2 +#define GL_2D 0x0600 +#define GL_3D 0x0601 +#define GL_3D_COLOR 0x0602 +#define GL_3D_COLOR_TEXTURE 0x0603 +#define GL_4D_COLOR_TEXTURE 0x0604 +#define GL_POINT_TOKEN 0x0701 +#define GL_LINE_TOKEN 0x0702 +#define GL_LINE_RESET_TOKEN 0x0707 +#define GL_POLYGON_TOKEN 0x0703 +#define GL_BITMAP_TOKEN 0x0704 +#define GL_DRAW_PIXEL_TOKEN 0x0705 +#define GL_COPY_PIXEL_TOKEN 0x0706 +#define GL_PASS_THROUGH_TOKEN 0x0700 +#define GL_FEEDBACK_BUFFER_POINTER 0x0DF0 +#define GL_FEEDBACK_BUFFER_SIZE 0x0DF1 +#define GL_FEEDBACK_BUFFER_TYPE 0x0DF2 /* Selection */ -#define GL_SELECTION_BUFFER_POINTER 0x0DF3 -#define GL_SELECTION_BUFFER_SIZE 0x0DF4 +#define GL_SELECTION_BUFFER_POINTER 0x0DF3 +#define GL_SELECTION_BUFFER_SIZE 0x0DF4 /* Fog */ -#define GL_FOG 0x0B60 -#define GL_FOG_MODE 0x0B65 -#define GL_FOG_DENSITY 0x0B62 -#define GL_FOG_COLOR 0x0B66 -#define GL_FOG_INDEX 0x0B61 -#define GL_FOG_START 0x0B63 -#define GL_FOG_END 0x0B64 -#define GL_LINEAR 0x2601 -#define GL_EXP 0x0800 -#define GL_EXP2 0x0801 +#define GL_FOG 0x0B60 +#define GL_FOG_MODE 0x0B65 +#define GL_FOG_DENSITY 0x0B62 +#define GL_FOG_COLOR 0x0B66 +#define GL_FOG_INDEX 0x0B61 +#define GL_FOG_START 0x0B63 +#define GL_FOG_END 0x0B64 +#define GL_LINEAR 0x2601 +#define GL_EXP 0x0800 +#define GL_EXP2 0x0801 /* Logic Ops */ -#define GL_LOGIC_OP 0x0BF1 -#define GL_INDEX_LOGIC_OP 0x0BF1 -#define GL_COLOR_LOGIC_OP 0x0BF2 -#define GL_LOGIC_OP_MODE 0x0BF0 -#define GL_CLEAR 0x1500 -#define GL_SET 0x150F -#define GL_COPY 0x1503 -#define GL_COPY_INVERTED 0x150C -#define GL_NOOP 0x1505 -#define GL_INVERT 0x150A -#define GL_AND 0x1501 -#define GL_NAND 0x150E -#define GL_OR 0x1507 -#define GL_NOR 0x1508 -#define GL_XOR 0x1506 -#define GL_EQUIV 0x1509 -#define GL_AND_REVERSE 0x1502 -#define GL_AND_INVERTED 0x1504 -#define GL_OR_REVERSE 0x150B -#define GL_OR_INVERTED 0x150D +#define GL_LOGIC_OP 0x0BF1 +#define GL_INDEX_LOGIC_OP 0x0BF1 +#define GL_COLOR_LOGIC_OP 0x0BF2 +#define GL_LOGIC_OP_MODE 0x0BF0 +#define GL_CLEAR 0x1500 +#define GL_SET 0x150F +#define GL_COPY 0x1503 +#define GL_COPY_INVERTED 0x150C +#define GL_NOOP 0x1505 +#define GL_INVERT 0x150A +#define GL_AND 0x1501 +#define GL_NAND 0x150E +#define GL_OR 0x1507 +#define GL_NOR 0x1508 +#define GL_XOR 0x1506 +#define GL_EQUIV 0x1509 +#define GL_AND_REVERSE 0x1502 +#define GL_AND_INVERTED 0x1504 +#define GL_OR_REVERSE 0x150B +#define GL_OR_INVERTED 0x150D /* Stencil */ -#define GL_STENCIL_BITS 0x0D57 -#define GL_STENCIL_TEST 0x0B90 -#define GL_STENCIL_CLEAR_VALUE 0x0B91 -#define GL_STENCIL_FUNC 0x0B92 -#define GL_STENCIL_VALUE_MASK 0x0B93 -#define GL_STENCIL_FAIL 0x0B94 -#define GL_STENCIL_PASS_DEPTH_FAIL 0x0B95 -#define GL_STENCIL_PASS_DEPTH_PASS 0x0B96 -#define GL_STENCIL_REF 0x0B97 -#define GL_STENCIL_WRITEMASK 0x0B98 -#define GL_STENCIL_INDEX 0x1901 -#define GL_KEEP 0x1E00 -#define GL_REPLACE 0x1E01 -#define GL_INCR 0x1E02 -#define GL_DECR 0x1E03 +#define GL_STENCIL_BITS 0x0D57 +#define GL_STENCIL_TEST 0x0B90 +#define GL_STENCIL_CLEAR_VALUE 0x0B91 +#define GL_STENCIL_FUNC 0x0B92 +#define GL_STENCIL_VALUE_MASK 0x0B93 +#define GL_STENCIL_FAIL 0x0B94 +#define GL_STENCIL_PASS_DEPTH_FAIL 0x0B95 +#define GL_STENCIL_PASS_DEPTH_PASS 0x0B96 +#define GL_STENCIL_REF 0x0B97 +#define GL_STENCIL_WRITEMASK 0x0B98 +#define GL_STENCIL_INDEX 0x1901 +#define GL_KEEP 0x1E00 +#define GL_REPLACE 0x1E01 +#define GL_INCR 0x1E02 +#define GL_DECR 0x1E03 /* Buffers, Pixel Drawing/Reading */ -#define GL_NONE 0 -#define GL_LEFT 0x0406 -#define GL_RIGHT 0x0407 -/*GL_FRONT 0x0404 */ -/*GL_BACK 0x0405 */ -/*GL_FRONT_AND_BACK 0x0408 */ -#define GL_FRONT_LEFT 0x0400 -#define GL_FRONT_RIGHT 0x0401 -#define GL_BACK_LEFT 0x0402 -#define GL_BACK_RIGHT 0x0403 -#define GL_AUX0 0x0409 -#define GL_AUX1 0x040A -#define GL_AUX2 0x040B -#define GL_AUX3 0x040C -#define GL_COLOR_INDEX 0x1900 -#define GL_RED 0x1903 -#define GL_GREEN 0x1904 -#define GL_BLUE 0x1905 -#define GL_ALPHA 0x1906 -#define GL_LUMINANCE 0x1909 -#define GL_LUMINANCE_ALPHA 0x190A -#define GL_ALPHA_BITS 0x0D55 -#define GL_RED_BITS 0x0D52 -#define GL_GREEN_BITS 0x0D53 -#define GL_BLUE_BITS 0x0D54 -#define GL_INDEX_BITS 0x0D51 -#define GL_SUBPIXEL_BITS 0x0D50 -#define GL_AUX_BUFFERS 0x0C00 -#define GL_READ_BUFFER 0x0C02 -#define GL_DRAW_BUFFER 0x0C01 -#define GL_DOUBLEBUFFER 0x0C32 -#define GL_STEREO 0x0C33 -#define GL_BITMAP 0x1A00 -#define GL_COLOR 0x1800 -#define GL_DEPTH 0x1801 -#define GL_STENCIL 0x1802 -#define GL_DITHER 0x0BD0 -#define GL_RGB 0x1907 -#define GL_RGBA 0x1908 +#define GL_NONE 0 +#define GL_LEFT 0x0406 +#define GL_RIGHT 0x0407 +/*GL_FRONT 0x0404 */ +/*GL_BACK 0x0405 */ +/*GL_FRONT_AND_BACK 0x0408 */ +#define GL_FRONT_LEFT 0x0400 +#define GL_FRONT_RIGHT 0x0401 +#define GL_BACK_LEFT 0x0402 +#define GL_BACK_RIGHT 0x0403 +#define GL_AUX0 0x0409 +#define GL_AUX1 0x040A +#define GL_AUX2 0x040B +#define GL_AUX3 0x040C +#define GL_COLOR_INDEX 0x1900 +#define GL_RED 0x1903 +#define GL_GREEN 0x1904 +#define GL_BLUE 0x1905 +#define GL_ALPHA 0x1906 +#define GL_LUMINANCE 0x1909 +#define GL_LUMINANCE_ALPHA 0x190A +#define GL_ALPHA_BITS 0x0D55 +#define GL_RED_BITS 0x0D52 +#define GL_GREEN_BITS 0x0D53 +#define GL_BLUE_BITS 0x0D54 +#define GL_INDEX_BITS 0x0D51 +#define GL_SUBPIXEL_BITS 0x0D50 +#define GL_AUX_BUFFERS 0x0C00 +#define GL_READ_BUFFER 0x0C02 +#define GL_DRAW_BUFFER 0x0C01 +#define GL_DOUBLEBUFFER 0x0C32 +#define GL_STEREO 0x0C33 +#define GL_BITMAP 0x1A00 +#define GL_COLOR 0x1800 +#define GL_DEPTH 0x1801 +#define GL_STENCIL 0x1802 +#define GL_DITHER 0x0BD0 +#define GL_RGB 0x1907 +#define GL_RGBA 0x1908 /* Implementation limits */ -#define GL_MAX_LIST_NESTING 0x0B31 -#define GL_MAX_EVAL_ORDER 0x0D30 -#define GL_MAX_LIGHTS 0x0D31 -#define GL_MAX_CLIP_PLANES 0x0D32 -#define GL_MAX_TEXTURE_SIZE 0x0D33 -#define GL_MAX_PIXEL_MAP_TABLE 0x0D34 -#define GL_MAX_ATTRIB_STACK_DEPTH 0x0D35 -#define GL_MAX_MODELVIEW_STACK_DEPTH 0x0D36 -#define GL_MAX_NAME_STACK_DEPTH 0x0D37 -#define GL_MAX_PROJECTION_STACK_DEPTH 0x0D38 -#define GL_MAX_TEXTURE_STACK_DEPTH 0x0D39 -#define GL_MAX_VIEWPORT_DIMS 0x0D3A -#define GL_MAX_CLIENT_ATTRIB_STACK_DEPTH 0x0D3B +#define GL_MAX_LIST_NESTING 0x0B31 +#define GL_MAX_EVAL_ORDER 0x0D30 +#define GL_MAX_LIGHTS 0x0D31 +#define GL_MAX_CLIP_PLANES 0x0D32 +#define GL_MAX_TEXTURE_SIZE 0x0D33 +#define GL_MAX_PIXEL_MAP_TABLE 0x0D34 +#define GL_MAX_ATTRIB_STACK_DEPTH 0x0D35 +#define GL_MAX_MODELVIEW_STACK_DEPTH 0x0D36 +#define GL_MAX_NAME_STACK_DEPTH 0x0D37 +#define GL_MAX_PROJECTION_STACK_DEPTH 0x0D38 +#define GL_MAX_TEXTURE_STACK_DEPTH 0x0D39 +#define GL_MAX_VIEWPORT_DIMS 0x0D3A +#define GL_MAX_CLIENT_ATTRIB_STACK_DEPTH 0x0D3B /* Gets */ -#define GL_ATTRIB_STACK_DEPTH 0x0BB0 -#define GL_CLIENT_ATTRIB_STACK_DEPTH 0x0BB1 -#define GL_COLOR_CLEAR_VALUE 0x0C22 -#define GL_COLOR_WRITEMASK 0x0C23 -#define GL_CURRENT_INDEX 0x0B01 -#define GL_CURRENT_COLOR 0x0B00 -#define GL_CURRENT_NORMAL 0x0B02 -#define GL_CURRENT_RASTER_COLOR 0x0B04 -#define GL_CURRENT_RASTER_DISTANCE 0x0B09 -#define GL_CURRENT_RASTER_INDEX 0x0B05 -#define GL_CURRENT_RASTER_POSITION 0x0B07 -#define GL_CURRENT_RASTER_TEXTURE_COORDS 0x0B06 -#define GL_CURRENT_RASTER_POSITION_VALID 0x0B08 -#define GL_CURRENT_TEXTURE_COORDS 0x0B03 -#define GL_INDEX_CLEAR_VALUE 0x0C20 -#define GL_INDEX_MODE 0x0C30 -#define GL_INDEX_WRITEMASK 0x0C21 -#define GL_MODELVIEW_MATRIX 0x0BA6 -#define GL_MODELVIEW_STACK_DEPTH 0x0BA3 -#define GL_NAME_STACK_DEPTH 0x0D70 -#define GL_PROJECTION_MATRIX 0x0BA7 -#define GL_PROJECTION_STACK_DEPTH 0x0BA4 -#define GL_RENDER_MODE 0x0C40 -#define GL_RGBA_MODE 0x0C31 -#define GL_TEXTURE_MATRIX 0x0BA8 -#define GL_TEXTURE_STACK_DEPTH 0x0BA5 -#define GL_VIEWPORT 0x0BA2 +#define GL_ATTRIB_STACK_DEPTH 0x0BB0 +#define GL_CLIENT_ATTRIB_STACK_DEPTH 0x0BB1 +#define GL_COLOR_CLEAR_VALUE 0x0C22 +#define GL_COLOR_WRITEMASK 0x0C23 +#define GL_CURRENT_INDEX 0x0B01 +#define GL_CURRENT_COLOR 0x0B00 +#define GL_CURRENT_NORMAL 0x0B02 +#define GL_CURRENT_RASTER_COLOR 0x0B04 +#define GL_CURRENT_RASTER_DISTANCE 0x0B09 +#define GL_CURRENT_RASTER_INDEX 0x0B05 +#define GL_CURRENT_RASTER_POSITION 0x0B07 +#define GL_CURRENT_RASTER_TEXTURE_COORDS 0x0B06 +#define GL_CURRENT_RASTER_POSITION_VALID 0x0B08 +#define GL_CURRENT_TEXTURE_COORDS 0x0B03 +#define GL_INDEX_CLEAR_VALUE 0x0C20 +#define GL_INDEX_MODE 0x0C30 +#define GL_INDEX_WRITEMASK 0x0C21 +#define GL_MODELVIEW_MATRIX 0x0BA6 +#define GL_MODELVIEW_STACK_DEPTH 0x0BA3 +#define GL_NAME_STACK_DEPTH 0x0D70 +#define GL_PROJECTION_MATRIX 0x0BA7 +#define GL_PROJECTION_STACK_DEPTH 0x0BA4 +#define GL_RENDER_MODE 0x0C40 +#define GL_RGBA_MODE 0x0C31 +#define GL_TEXTURE_MATRIX 0x0BA8 +#define GL_TEXTURE_STACK_DEPTH 0x0BA5 +#define GL_VIEWPORT 0x0BA2 /* Evaluators */ -#define GL_AUTO_NORMAL 0x0D80 -#define GL_MAP1_COLOR_4 0x0D90 -#define GL_MAP1_INDEX 0x0D91 -#define GL_MAP1_NORMAL 0x0D92 -#define GL_MAP1_TEXTURE_COORD_1 0x0D93 -#define GL_MAP1_TEXTURE_COORD_2 0x0D94 -#define GL_MAP1_TEXTURE_COORD_3 0x0D95 -#define GL_MAP1_TEXTURE_COORD_4 0x0D96 -#define GL_MAP1_VERTEX_3 0x0D97 -#define GL_MAP1_VERTEX_4 0x0D98 -#define GL_MAP2_COLOR_4 0x0DB0 -#define GL_MAP2_INDEX 0x0DB1 -#define GL_MAP2_NORMAL 0x0DB2 -#define GL_MAP2_TEXTURE_COORD_1 0x0DB3 -#define GL_MAP2_TEXTURE_COORD_2 0x0DB4 -#define GL_MAP2_TEXTURE_COORD_3 0x0DB5 -#define GL_MAP2_TEXTURE_COORD_4 0x0DB6 -#define GL_MAP2_VERTEX_3 0x0DB7 -#define GL_MAP2_VERTEX_4 0x0DB8 -#define GL_MAP1_GRID_DOMAIN 0x0DD0 -#define GL_MAP1_GRID_SEGMENTS 0x0DD1 -#define GL_MAP2_GRID_DOMAIN 0x0DD2 -#define GL_MAP2_GRID_SEGMENTS 0x0DD3 -#define GL_COEFF 0x0A00 -#define GL_ORDER 0x0A01 -#define GL_DOMAIN 0x0A02 +#define GL_AUTO_NORMAL 0x0D80 +#define GL_MAP1_COLOR_4 0x0D90 +#define GL_MAP1_INDEX 0x0D91 +#define GL_MAP1_NORMAL 0x0D92 +#define GL_MAP1_TEXTURE_COORD_1 0x0D93 +#define GL_MAP1_TEXTURE_COORD_2 0x0D94 +#define GL_MAP1_TEXTURE_COORD_3 0x0D95 +#define GL_MAP1_TEXTURE_COORD_4 0x0D96 +#define GL_MAP1_VERTEX_3 0x0D97 +#define GL_MAP1_VERTEX_4 0x0D98 +#define GL_MAP2_COLOR_4 0x0DB0 +#define GL_MAP2_INDEX 0x0DB1 +#define GL_MAP2_NORMAL 0x0DB2 +#define GL_MAP2_TEXTURE_COORD_1 0x0DB3 +#define GL_MAP2_TEXTURE_COORD_2 0x0DB4 +#define GL_MAP2_TEXTURE_COORD_3 0x0DB5 +#define GL_MAP2_TEXTURE_COORD_4 0x0DB6 +#define GL_MAP2_VERTEX_3 0x0DB7 +#define GL_MAP2_VERTEX_4 0x0DB8 +#define GL_MAP1_GRID_DOMAIN 0x0DD0 +#define GL_MAP1_GRID_SEGMENTS 0x0DD1 +#define GL_MAP2_GRID_DOMAIN 0x0DD2 +#define GL_MAP2_GRID_SEGMENTS 0x0DD3 +#define GL_COEFF 0x0A00 +#define GL_ORDER 0x0A01 +#define GL_DOMAIN 0x0A02 /* Hints */ -#define GL_PERSPECTIVE_CORRECTION_HINT 0x0C50 -#define GL_POINT_SMOOTH_HINT 0x0C51 -#define GL_LINE_SMOOTH_HINT 0x0C52 -#define GL_POLYGON_SMOOTH_HINT 0x0C53 -#define GL_FOG_HINT 0x0C54 -#define GL_DONT_CARE 0x1100 -#define GL_FASTEST 0x1101 -#define GL_NICEST 0x1102 +#define GL_PERSPECTIVE_CORRECTION_HINT 0x0C50 +#define GL_POINT_SMOOTH_HINT 0x0C51 +#define GL_LINE_SMOOTH_HINT 0x0C52 +#define GL_POLYGON_SMOOTH_HINT 0x0C53 +#define GL_FOG_HINT 0x0C54 +#define GL_DONT_CARE 0x1100 +#define GL_FASTEST 0x1101 +#define GL_NICEST 0x1102 /* Scissor box */ -#define GL_SCISSOR_BOX 0x0C10 -#define GL_SCISSOR_TEST 0x0C11 +#define GL_SCISSOR_BOX 0x0C10 +#define GL_SCISSOR_TEST 0x0C11 /* Pixel Mode / Transfer */ -#define GL_MAP_COLOR 0x0D10 -#define GL_MAP_STENCIL 0x0D11 -#define GL_INDEX_SHIFT 0x0D12 -#define GL_INDEX_OFFSET 0x0D13 -#define GL_RED_SCALE 0x0D14 -#define GL_RED_BIAS 0x0D15 -#define GL_GREEN_SCALE 0x0D18 -#define GL_GREEN_BIAS 0x0D19 -#define GL_BLUE_SCALE 0x0D1A -#define GL_BLUE_BIAS 0x0D1B -#define GL_ALPHA_SCALE 0x0D1C -#define GL_ALPHA_BIAS 0x0D1D -#define GL_DEPTH_SCALE 0x0D1E -#define GL_DEPTH_BIAS 0x0D1F -#define GL_PIXEL_MAP_S_TO_S_SIZE 0x0CB1 -#define GL_PIXEL_MAP_I_TO_I_SIZE 0x0CB0 -#define GL_PIXEL_MAP_I_TO_R_SIZE 0x0CB2 -#define GL_PIXEL_MAP_I_TO_G_SIZE 0x0CB3 -#define GL_PIXEL_MAP_I_TO_B_SIZE 0x0CB4 -#define GL_PIXEL_MAP_I_TO_A_SIZE 0x0CB5 -#define GL_PIXEL_MAP_R_TO_R_SIZE 0x0CB6 -#define GL_PIXEL_MAP_G_TO_G_SIZE 0x0CB7 -#define GL_PIXEL_MAP_B_TO_B_SIZE 0x0CB8 -#define GL_PIXEL_MAP_A_TO_A_SIZE 0x0CB9 -#define GL_PIXEL_MAP_S_TO_S 0x0C71 -#define GL_PIXEL_MAP_I_TO_I 0x0C70 -#define GL_PIXEL_MAP_I_TO_R 0x0C72 -#define GL_PIXEL_MAP_I_TO_G 0x0C73 -#define GL_PIXEL_MAP_I_TO_B 0x0C74 -#define GL_PIXEL_MAP_I_TO_A 0x0C75 -#define GL_PIXEL_MAP_R_TO_R 0x0C76 -#define GL_PIXEL_MAP_G_TO_G 0x0C77 -#define GL_PIXEL_MAP_B_TO_B 0x0C78 -#define GL_PIXEL_MAP_A_TO_A 0x0C79 -#define GL_PACK_ALIGNMENT 0x0D05 -#define GL_PACK_LSB_FIRST 0x0D01 -#define GL_PACK_ROW_LENGTH 0x0D02 -#define GL_PACK_SKIP_PIXELS 0x0D04 -#define GL_PACK_SKIP_ROWS 0x0D03 -#define GL_PACK_SWAP_BYTES 0x0D00 -#define GL_UNPACK_ALIGNMENT 0x0CF5 -#define GL_UNPACK_LSB_FIRST 0x0CF1 -#define GL_UNPACK_ROW_LENGTH 0x0CF2 -#define GL_UNPACK_SKIP_PIXELS 0x0CF4 -#define GL_UNPACK_SKIP_ROWS 0x0CF3 -#define GL_UNPACK_SWAP_BYTES 0x0CF0 -#define GL_ZOOM_X 0x0D16 -#define GL_ZOOM_Y 0x0D17 +#define GL_MAP_COLOR 0x0D10 +#define GL_MAP_STENCIL 0x0D11 +#define GL_INDEX_SHIFT 0x0D12 +#define GL_INDEX_OFFSET 0x0D13 +#define GL_RED_SCALE 0x0D14 +#define GL_RED_BIAS 0x0D15 +#define GL_GREEN_SCALE 0x0D18 +#define GL_GREEN_BIAS 0x0D19 +#define GL_BLUE_SCALE 0x0D1A +#define GL_BLUE_BIAS 0x0D1B +#define GL_ALPHA_SCALE 0x0D1C +#define GL_ALPHA_BIAS 0x0D1D +#define GL_DEPTH_SCALE 0x0D1E +#define GL_DEPTH_BIAS 0x0D1F +#define GL_PIXEL_MAP_S_TO_S_SIZE 0x0CB1 +#define GL_PIXEL_MAP_I_TO_I_SIZE 0x0CB0 +#define GL_PIXEL_MAP_I_TO_R_SIZE 0x0CB2 +#define GL_PIXEL_MAP_I_TO_G_SIZE 0x0CB3 +#define GL_PIXEL_MAP_I_TO_B_SIZE 0x0CB4 +#define GL_PIXEL_MAP_I_TO_A_SIZE 0x0CB5 +#define GL_PIXEL_MAP_R_TO_R_SIZE 0x0CB6 +#define GL_PIXEL_MAP_G_TO_G_SIZE 0x0CB7 +#define GL_PIXEL_MAP_B_TO_B_SIZE 0x0CB8 +#define GL_PIXEL_MAP_A_TO_A_SIZE 0x0CB9 +#define GL_PIXEL_MAP_S_TO_S 0x0C71 +#define GL_PIXEL_MAP_I_TO_I 0x0C70 +#define GL_PIXEL_MAP_I_TO_R 0x0C72 +#define GL_PIXEL_MAP_I_TO_G 0x0C73 +#define GL_PIXEL_MAP_I_TO_B 0x0C74 +#define GL_PIXEL_MAP_I_TO_A 0x0C75 +#define GL_PIXEL_MAP_R_TO_R 0x0C76 +#define GL_PIXEL_MAP_G_TO_G 0x0C77 +#define GL_PIXEL_MAP_B_TO_B 0x0C78 +#define GL_PIXEL_MAP_A_TO_A 0x0C79 +#define GL_PACK_ALIGNMENT 0x0D05 +#define GL_PACK_LSB_FIRST 0x0D01 +#define GL_PACK_ROW_LENGTH 0x0D02 +#define GL_PACK_SKIP_PIXELS 0x0D04 +#define GL_PACK_SKIP_ROWS 0x0D03 +#define GL_PACK_SWAP_BYTES 0x0D00 +#define GL_UNPACK_ALIGNMENT 0x0CF5 +#define GL_UNPACK_LSB_FIRST 0x0CF1 +#define GL_UNPACK_ROW_LENGTH 0x0CF2 +#define GL_UNPACK_SKIP_PIXELS 0x0CF4 +#define GL_UNPACK_SKIP_ROWS 0x0CF3 +#define GL_UNPACK_SWAP_BYTES 0x0CF0 +#define GL_ZOOM_X 0x0D16 +#define GL_ZOOM_Y 0x0D17 /* Texture mapping */ -#define GL_TEXTURE_ENV 0x2300 -#define GL_TEXTURE_ENV_MODE 0x2200 -#define GL_TEXTURE_1D 0x0DE0 -#define GL_TEXTURE_2D 0x0DE1 -#define GL_TEXTURE_WRAP_S 0x2802 -#define GL_TEXTURE_WRAP_T 0x2803 -#define GL_TEXTURE_MAG_FILTER 0x2800 -#define GL_TEXTURE_MIN_FILTER 0x2801 -#define GL_TEXTURE_ENV_COLOR 0x2201 -#define GL_TEXTURE_GEN_S 0x0C60 -#define GL_TEXTURE_GEN_T 0x0C61 -#define GL_TEXTURE_GEN_R 0x0C62 -#define GL_TEXTURE_GEN_Q 0x0C63 -#define GL_TEXTURE_GEN_MODE 0x2500 -#define GL_TEXTURE_BORDER_COLOR 0x1004 -#define GL_TEXTURE_WIDTH 0x1000 -#define GL_TEXTURE_HEIGHT 0x1001 -#define GL_TEXTURE_BORDER 0x1005 -#define GL_TEXTURE_COMPONENTS 0x1003 -#define GL_TEXTURE_RED_SIZE 0x805C -#define GL_TEXTURE_GREEN_SIZE 0x805D -#define GL_TEXTURE_BLUE_SIZE 0x805E -#define GL_TEXTURE_ALPHA_SIZE 0x805F -#define GL_TEXTURE_LUMINANCE_SIZE 0x8060 -#define GL_TEXTURE_INTENSITY_SIZE 0x8061 -#define GL_NEAREST_MIPMAP_NEAREST 0x2700 -#define GL_NEAREST_MIPMAP_LINEAR 0x2702 -#define GL_LINEAR_MIPMAP_NEAREST 0x2701 -#define GL_LINEAR_MIPMAP_LINEAR 0x2703 -#define GL_OBJECT_LINEAR 0x2401 -#define GL_OBJECT_PLANE 0x2501 -#define GL_EYE_LINEAR 0x2400 -#define GL_EYE_PLANE 0x2502 -#define GL_SPHERE_MAP 0x2402 -#define GL_DECAL 0x2101 -#define GL_MODULATE 0x2100 -#define GL_NEAREST 0x2600 -#define GL_REPEAT 0x2901 -#define GL_CLAMP 0x2900 -#define GL_S 0x2000 -#define GL_T 0x2001 -#define GL_R 0x2002 -#define GL_Q 0x2003 +#define GL_TEXTURE_ENV 0x2300 +#define GL_TEXTURE_ENV_MODE 0x2200 +#define GL_TEXTURE_1D 0x0DE0 +#define GL_TEXTURE_2D 0x0DE1 +#define GL_TEXTURE_WRAP_S 0x2802 +#define GL_TEXTURE_WRAP_T 0x2803 +#define GL_TEXTURE_MAG_FILTER 0x2800 +#define GL_TEXTURE_MIN_FILTER 0x2801 +#define GL_TEXTURE_ENV_COLOR 0x2201 +#define GL_TEXTURE_GEN_S 0x0C60 +#define GL_TEXTURE_GEN_T 0x0C61 +#define GL_TEXTURE_GEN_R 0x0C62 +#define GL_TEXTURE_GEN_Q 0x0C63 +#define GL_TEXTURE_GEN_MODE 0x2500 +#define GL_TEXTURE_BORDER_COLOR 0x1004 +#define GL_TEXTURE_WIDTH 0x1000 +#define GL_TEXTURE_HEIGHT 0x1001 +#define GL_TEXTURE_BORDER 0x1005 +#define GL_TEXTURE_COMPONENTS 0x1003 +#define GL_TEXTURE_RED_SIZE 0x805C +#define GL_TEXTURE_GREEN_SIZE 0x805D +#define GL_TEXTURE_BLUE_SIZE 0x805E +#define GL_TEXTURE_ALPHA_SIZE 0x805F +#define GL_TEXTURE_LUMINANCE_SIZE 0x8060 +#define GL_TEXTURE_INTENSITY_SIZE 0x8061 +#define GL_NEAREST_MIPMAP_NEAREST 0x2700 +#define GL_NEAREST_MIPMAP_LINEAR 0x2702 +#define GL_LINEAR_MIPMAP_NEAREST 0x2701 +#define GL_LINEAR_MIPMAP_LINEAR 0x2703 +#define GL_OBJECT_LINEAR 0x2401 +#define GL_OBJECT_PLANE 0x2501 +#define GL_EYE_LINEAR 0x2400 +#define GL_EYE_PLANE 0x2502 +#define GL_SPHERE_MAP 0x2402 +#define GL_DECAL 0x2101 +#define GL_MODULATE 0x2100 +#define GL_NEAREST 0x2600 +#define GL_REPEAT 0x2901 +#define GL_CLAMP 0x2900 +#define GL_S 0x2000 +#define GL_T 0x2001 +#define GL_R 0x2002 +#define GL_Q 0x2003 /* Utility */ -#define GL_VENDOR 0x1F00 -#define GL_RENDERER 0x1F01 -#define GL_VERSION 0x1F02 -#define GL_EXTENSIONS 0x1F03 +#define GL_VENDOR 0x1F00 +#define GL_RENDERER 0x1F01 +#define GL_VERSION 0x1F02 +#define GL_EXTENSIONS 0x1F03 /* Errors */ -#define GL_NO_ERROR 0 -#define GL_INVALID_ENUM 0x0500 -#define GL_INVALID_VALUE 0x0501 -#define GL_INVALID_OPERATION 0x0502 -#define GL_STACK_OVERFLOW 0x0503 -#define GL_STACK_UNDERFLOW 0x0504 -#define GL_OUT_OF_MEMORY 0x0505 +#define GL_NO_ERROR 0 +#define GL_INVALID_ENUM 0x0500 +#define GL_INVALID_VALUE 0x0501 +#define GL_INVALID_OPERATION 0x0502 +#define GL_STACK_OVERFLOW 0x0503 +#define GL_STACK_UNDERFLOW 0x0504 +#define GL_OUT_OF_MEMORY 0x0505 /* glPush/PopAttrib bits */ -#define GL_CURRENT_BIT 0x00000001 -#define GL_POINT_BIT 0x00000002 -#define GL_LINE_BIT 0x00000004 -#define GL_POLYGON_BIT 0x00000008 -#define GL_POLYGON_STIPPLE_BIT 0x00000010 -#define GL_PIXEL_MODE_BIT 0x00000020 -#define GL_LIGHTING_BIT 0x00000040 -#define GL_FOG_BIT 0x00000080 -#define GL_DEPTH_BUFFER_BIT 0x00000100 -#define GL_ACCUM_BUFFER_BIT 0x00000200 -#define GL_STENCIL_BUFFER_BIT 0x00000400 -#define GL_VIEWPORT_BIT 0x00000800 -#define GL_TRANSFORM_BIT 0x00001000 -#define GL_ENABLE_BIT 0x00002000 -#define GL_COLOR_BUFFER_BIT 0x00004000 -#define GL_HINT_BIT 0x00008000 -#define GL_EVAL_BIT 0x00010000 -#define GL_LIST_BIT 0x00020000 -#define GL_TEXTURE_BIT 0x00040000 -#define GL_SCISSOR_BIT 0x00080000 -#define GL_ALL_ATTRIB_BITS 0x000FFFFF +#define GL_CURRENT_BIT 0x00000001 +#define GL_POINT_BIT 0x00000002 +#define GL_LINE_BIT 0x00000004 +#define GL_POLYGON_BIT 0x00000008 +#define GL_POLYGON_STIPPLE_BIT 0x00000010 +#define GL_PIXEL_MODE_BIT 0x00000020 +#define GL_LIGHTING_BIT 0x00000040 +#define GL_FOG_BIT 0x00000080 +#define GL_DEPTH_BUFFER_BIT 0x00000100 +#define GL_ACCUM_BUFFER_BIT 0x00000200 +#define GL_STENCIL_BUFFER_BIT 0x00000400 +#define GL_VIEWPORT_BIT 0x00000800 +#define GL_TRANSFORM_BIT 0x00001000 +#define GL_ENABLE_BIT 0x00002000 +#define GL_COLOR_BUFFER_BIT 0x00004000 +#define GL_HINT_BIT 0x00008000 +#define GL_EVAL_BIT 0x00010000 +#define GL_LIST_BIT 0x00020000 +#define GL_TEXTURE_BIT 0x00040000 +#define GL_SCISSOR_BIT 0x00080000 +#define GL_ALL_ATTRIB_BITS 0x000FFFFF /* OpenGL 1.1 */ -#define GL_PROXY_TEXTURE_1D 0x8063 -#define GL_PROXY_TEXTURE_2D 0x8064 -#define GL_TEXTURE_PRIORITY 0x8066 -#define GL_TEXTURE_RESIDENT 0x8067 -#define GL_TEXTURE_BINDING_1D 0x8068 -#define GL_TEXTURE_BINDING_2D 0x8069 -#define GL_TEXTURE_INTERNAL_FORMAT 0x1003 -#define GL_ALPHA4 0x803B -#define GL_ALPHA8 0x803C -#define GL_ALPHA12 0x803D -#define GL_ALPHA16 0x803E -#define GL_LUMINANCE4 0x803F -#define GL_LUMINANCE8 0x8040 -#define GL_LUMINANCE12 0x8041 -#define GL_LUMINANCE16 0x8042 -#define GL_LUMINANCE4_ALPHA4 0x8043 -#define GL_LUMINANCE6_ALPHA2 0x8044 -#define GL_LUMINANCE8_ALPHA8 0x8045 -#define GL_LUMINANCE12_ALPHA4 0x8046 -#define GL_LUMINANCE12_ALPHA12 0x8047 -#define GL_LUMINANCE16_ALPHA16 0x8048 -#define GL_INTENSITY 0x8049 -#define GL_INTENSITY4 0x804A -#define GL_INTENSITY8 0x804B -#define GL_INTENSITY12 0x804C -#define GL_INTENSITY16 0x804D -#define GL_R3_G3_B2 0x2A10 -#define GL_RGB4 0x804F -#define GL_RGB5 0x8050 -#define GL_RGB8 0x8051 -#define GL_RGB10 0x8052 -#define GL_RGB12 0x8053 -#define GL_RGB16 0x8054 -#define GL_RGBA2 0x8055 -#define GL_RGBA4 0x8056 -#define GL_RGB5_A1 0x8057 -#define GL_RGBA8 0x8058 -#define GL_RGB10_A2 0x8059 -#define GL_RGBA12 0x805A -#define GL_RGBA16 0x805B -#define GL_CLIENT_PIXEL_STORE_BIT 0x00000001 -#define GL_CLIENT_VERTEX_ARRAY_BIT 0x00000002 -#define GL_ALL_CLIENT_ATTRIB_BITS 0xFFFFFFFF -#define GL_CLIENT_ALL_ATTRIB_BITS 0xFFFFFFFF +#define GL_PROXY_TEXTURE_1D 0x8063 +#define GL_PROXY_TEXTURE_2D 0x8064 +#define GL_TEXTURE_PRIORITY 0x8066 +#define GL_TEXTURE_RESIDENT 0x8067 +#define GL_TEXTURE_BINDING_1D 0x8068 +#define GL_TEXTURE_BINDING_2D 0x8069 +#define GL_TEXTURE_INTERNAL_FORMAT 0x1003 +#define GL_ALPHA4 0x803B +#define GL_ALPHA8 0x803C +#define GL_ALPHA12 0x803D +#define GL_ALPHA16 0x803E +#define GL_LUMINANCE4 0x803F +#define GL_LUMINANCE8 0x8040 +#define GL_LUMINANCE12 0x8041 +#define GL_LUMINANCE16 0x8042 +#define GL_LUMINANCE4_ALPHA4 0x8043 +#define GL_LUMINANCE6_ALPHA2 0x8044 +#define GL_LUMINANCE8_ALPHA8 0x8045 +#define GL_LUMINANCE12_ALPHA4 0x8046 +#define GL_LUMINANCE12_ALPHA12 0x8047 +#define GL_LUMINANCE16_ALPHA16 0x8048 +#define GL_INTENSITY 0x8049 +#define GL_INTENSITY4 0x804A +#define GL_INTENSITY8 0x804B +#define GL_INTENSITY12 0x804C +#define GL_INTENSITY16 0x804D +#define GL_R3_G3_B2 0x2A10 +#define GL_RGB4 0x804F +#define GL_RGB5 0x8050 +#define GL_RGB8 0x8051 +#define GL_RGB10 0x8052 +#define GL_RGB12 0x8053 +#define GL_RGB16 0x8054 +#define GL_RGBA2 0x8055 +#define GL_RGBA4 0x8056 +#define GL_RGB5_A1 0x8057 +#define GL_RGBA8 0x8058 +#define GL_RGB10_A2 0x8059 +#define GL_RGBA12 0x805A +#define GL_RGBA16 0x805B +#define GL_CLIENT_PIXEL_STORE_BIT 0x00000001 +#define GL_CLIENT_VERTEX_ARRAY_BIT 0x00000002 +#define GL_ALL_CLIENT_ATTRIB_BITS 0xFFFFFFFF +#define GL_CLIENT_ALL_ATTRIB_BITS 0xFFFFFFFF @@ -1425,13 +1425,13 @@ GLAPI void GLAPIENTRY glMap1f( GLenum target, GLfloat u1, GLfloat u2, GLint order, const GLfloat *points ); GLAPI void GLAPIENTRY glMap2d( GLenum target, - GLdouble u1, GLdouble u2, GLint ustride, GLint uorder, - GLdouble v1, GLdouble v2, GLint vstride, GLint vorder, - const GLdouble *points ); + GLdouble u1, GLdouble u2, GLint ustride, GLint uorder, + GLdouble v1, GLdouble v2, GLint vstride, GLint vorder, + const GLdouble *points ); GLAPI void GLAPIENTRY glMap2f( GLenum target, - GLfloat u1, GLfloat u2, GLint ustride, GLint uorder, - GLfloat v1, GLfloat v2, GLint vstride, GLint vorder, - const GLfloat *points ); + GLfloat u1, GLfloat u2, GLint ustride, GLint uorder, + GLfloat v1, GLfloat v2, GLint vstride, GLint vorder, + const GLfloat *points ); GLAPI void GLAPIENTRY glGetMapdv( GLenum target, GLenum query, GLdouble *v ); GLAPI void GLAPIENTRY glGetMapfv( GLenum target, GLenum query, GLfloat *v ); @@ -1503,50 +1503,50 @@ GLAPI void GLAPIENTRY glPopName( void ); * OpenGL 1.2 */ -#define GL_RESCALE_NORMAL 0x803A -#define GL_CLAMP_TO_EDGE 0x812F -#define GL_MAX_ELEMENTS_VERTICES 0x80E8 -#define GL_MAX_ELEMENTS_INDICES 0x80E9 -#define GL_BGR 0x80E0 -#define GL_BGRA 0x80E1 -#define GL_UNSIGNED_BYTE_3_3_2 0x8032 -#define GL_UNSIGNED_BYTE_2_3_3_REV 0x8362 -#define GL_UNSIGNED_SHORT_5_6_5 0x8363 -#define GL_UNSIGNED_SHORT_5_6_5_REV 0x8364 -#define GL_UNSIGNED_SHORT_4_4_4_4 0x8033 -#define GL_UNSIGNED_SHORT_4_4_4_4_REV 0x8365 -#define GL_UNSIGNED_SHORT_5_5_5_1 0x8034 -#define GL_UNSIGNED_SHORT_1_5_5_5_REV 0x8366 -#define GL_UNSIGNED_INT_8_8_8_8 0x8035 -#define GL_UNSIGNED_INT_8_8_8_8_REV 0x8367 -#define GL_UNSIGNED_INT_10_10_10_2 0x8036 -#define GL_UNSIGNED_INT_2_10_10_10_REV 0x8368 -#define GL_LIGHT_MODEL_COLOR_CONTROL 0x81F8 -#define GL_SINGLE_COLOR 0x81F9 -#define GL_SEPARATE_SPECULAR_COLOR 0x81FA -#define GL_TEXTURE_MIN_LOD 0x813A -#define GL_TEXTURE_MAX_LOD 0x813B -#define GL_TEXTURE_BASE_LEVEL 0x813C -#define GL_TEXTURE_MAX_LEVEL 0x813D -#define GL_SMOOTH_POINT_SIZE_RANGE 0x0B12 -#define GL_SMOOTH_POINT_SIZE_GRANULARITY 0x0B13 -#define GL_SMOOTH_LINE_WIDTH_RANGE 0x0B22 -#define GL_SMOOTH_LINE_WIDTH_GRANULARITY 0x0B23 -#define GL_ALIASED_POINT_SIZE_RANGE 0x846D -#define GL_ALIASED_LINE_WIDTH_RANGE 0x846E -#define GL_PACK_SKIP_IMAGES 0x806B -#define GL_PACK_IMAGE_HEIGHT 0x806C -#define GL_UNPACK_SKIP_IMAGES 0x806D -#define GL_UNPACK_IMAGE_HEIGHT 0x806E -#define GL_TEXTURE_3D 0x806F -#define GL_PROXY_TEXTURE_3D 0x8070 -#define GL_TEXTURE_DEPTH 0x8071 -#define GL_TEXTURE_WRAP_R 0x8072 -#define GL_MAX_3D_TEXTURE_SIZE 0x8073 -#define GL_TEXTURE_BINDING_3D 0x806A +#define GL_RESCALE_NORMAL 0x803A +#define GL_CLAMP_TO_EDGE 0x812F +#define GL_MAX_ELEMENTS_VERTICES 0x80E8 +#define GL_MAX_ELEMENTS_INDICES 0x80E9 +#define GL_BGR 0x80E0 +#define GL_BGRA 0x80E1 +#define GL_UNSIGNED_BYTE_3_3_2 0x8032 +#define GL_UNSIGNED_BYTE_2_3_3_REV 0x8362 +#define GL_UNSIGNED_SHORT_5_6_5 0x8363 +#define GL_UNSIGNED_SHORT_5_6_5_REV 0x8364 +#define GL_UNSIGNED_SHORT_4_4_4_4 0x8033 +#define GL_UNSIGNED_SHORT_4_4_4_4_REV 0x8365 +#define GL_UNSIGNED_SHORT_5_5_5_1 0x8034 +#define GL_UNSIGNED_SHORT_1_5_5_5_REV 0x8366 +#define GL_UNSIGNED_INT_8_8_8_8 0x8035 +#define GL_UNSIGNED_INT_8_8_8_8_REV 0x8367 +#define GL_UNSIGNED_INT_10_10_10_2 0x8036 +#define GL_UNSIGNED_INT_2_10_10_10_REV 0x8368 +#define GL_LIGHT_MODEL_COLOR_CONTROL 0x81F8 +#define GL_SINGLE_COLOR 0x81F9 +#define GL_SEPARATE_SPECULAR_COLOR 0x81FA +#define GL_TEXTURE_MIN_LOD 0x813A +#define GL_TEXTURE_MAX_LOD 0x813B +#define GL_TEXTURE_BASE_LEVEL 0x813C +#define GL_TEXTURE_MAX_LEVEL 0x813D +#define GL_SMOOTH_POINT_SIZE_RANGE 0x0B12 +#define GL_SMOOTH_POINT_SIZE_GRANULARITY 0x0B13 +#define GL_SMOOTH_LINE_WIDTH_RANGE 0x0B22 +#define GL_SMOOTH_LINE_WIDTH_GRANULARITY 0x0B23 +#define GL_ALIASED_POINT_SIZE_RANGE 0x846D +#define GL_ALIASED_LINE_WIDTH_RANGE 0x846E +#define GL_PACK_SKIP_IMAGES 0x806B +#define GL_PACK_IMAGE_HEIGHT 0x806C +#define GL_UNPACK_SKIP_IMAGES 0x806D +#define GL_UNPACK_IMAGE_HEIGHT 0x806E +#define GL_TEXTURE_3D 0x806F +#define GL_PROXY_TEXTURE_3D 0x8070 +#define GL_TEXTURE_DEPTH 0x8071 +#define GL_TEXTURE_WRAP_R 0x8072 +#define GL_MAX_3D_TEXTURE_SIZE 0x8073 +#define GL_TEXTURE_BINDING_3D 0x806A GLAPI void GLAPIENTRY glDrawRangeElements( GLenum mode, GLuint start, - GLuint end, GLsizei count, GLenum type, const GLvoid *indices ); + GLuint end, GLsizei count, GLenum type, const GLvoid *indices ); GLAPI void GLAPIENTRY glTexImage3D( GLenum target, GLint level, GLint internalFormat, @@ -1578,81 +1578,81 @@ typedef void (APIENTRYP PFNGLCOPYTEXSUBIMAGE3DPROC) (GLenum target, GLint level, * GL_ARB_imaging */ -#define GL_CONSTANT_COLOR 0x8001 -#define GL_ONE_MINUS_CONSTANT_COLOR 0x8002 -#define GL_CONSTANT_ALPHA 0x8003 -#define GL_ONE_MINUS_CONSTANT_ALPHA 0x8004 -#define GL_COLOR_TABLE 0x80D0 -#define GL_POST_CONVOLUTION_COLOR_TABLE 0x80D1 -#define GL_POST_COLOR_MATRIX_COLOR_TABLE 0x80D2 -#define GL_PROXY_COLOR_TABLE 0x80D3 -#define GL_PROXY_POST_CONVOLUTION_COLOR_TABLE 0x80D4 -#define GL_PROXY_POST_COLOR_MATRIX_COLOR_TABLE 0x80D5 -#define GL_COLOR_TABLE_SCALE 0x80D6 -#define GL_COLOR_TABLE_BIAS 0x80D7 -#define GL_COLOR_TABLE_FORMAT 0x80D8 -#define GL_COLOR_TABLE_WIDTH 0x80D9 -#define GL_COLOR_TABLE_RED_SIZE 0x80DA -#define GL_COLOR_TABLE_GREEN_SIZE 0x80DB -#define GL_COLOR_TABLE_BLUE_SIZE 0x80DC -#define GL_COLOR_TABLE_ALPHA_SIZE 0x80DD -#define GL_COLOR_TABLE_LUMINANCE_SIZE 0x80DE -#define GL_COLOR_TABLE_INTENSITY_SIZE 0x80DF -#define GL_CONVOLUTION_1D 0x8010 -#define GL_CONVOLUTION_2D 0x8011 -#define GL_SEPARABLE_2D 0x8012 -#define GL_CONVOLUTION_BORDER_MODE 0x8013 -#define GL_CONVOLUTION_FILTER_SCALE 0x8014 -#define GL_CONVOLUTION_FILTER_BIAS 0x8015 -#define GL_REDUCE 0x8016 -#define GL_CONVOLUTION_FORMAT 0x8017 -#define GL_CONVOLUTION_WIDTH 0x8018 -#define GL_CONVOLUTION_HEIGHT 0x8019 -#define GL_MAX_CONVOLUTION_WIDTH 0x801A -#define GL_MAX_CONVOLUTION_HEIGHT 0x801B -#define GL_POST_CONVOLUTION_RED_SCALE 0x801C -#define GL_POST_CONVOLUTION_GREEN_SCALE 0x801D -#define GL_POST_CONVOLUTION_BLUE_SCALE 0x801E -#define GL_POST_CONVOLUTION_ALPHA_SCALE 0x801F -#define GL_POST_CONVOLUTION_RED_BIAS 0x8020 -#define GL_POST_CONVOLUTION_GREEN_BIAS 0x8021 -#define GL_POST_CONVOLUTION_BLUE_BIAS 0x8022 -#define GL_POST_CONVOLUTION_ALPHA_BIAS 0x8023 -#define GL_CONSTANT_BORDER 0x8151 -#define GL_REPLICATE_BORDER 0x8153 -#define GL_CONVOLUTION_BORDER_COLOR 0x8154 -#define GL_COLOR_MATRIX 0x80B1 -#define GL_COLOR_MATRIX_STACK_DEPTH 0x80B2 -#define GL_MAX_COLOR_MATRIX_STACK_DEPTH 0x80B3 -#define GL_POST_COLOR_MATRIX_RED_SCALE 0x80B4 -#define GL_POST_COLOR_MATRIX_GREEN_SCALE 0x80B5 -#define GL_POST_COLOR_MATRIX_BLUE_SCALE 0x80B6 -#define GL_POST_COLOR_MATRIX_ALPHA_SCALE 0x80B7 -#define GL_POST_COLOR_MATRIX_RED_BIAS 0x80B8 -#define GL_POST_COLOR_MATRIX_GREEN_BIAS 0x80B9 -#define GL_POST_COLOR_MATRIX_BLUE_BIAS 0x80BA -#define GL_POST_COLOR_MATRIX_ALPHA_BIAS 0x80BB -#define GL_HISTOGRAM 0x8024 -#define GL_PROXY_HISTOGRAM 0x8025 -#define GL_HISTOGRAM_WIDTH 0x8026 -#define GL_HISTOGRAM_FORMAT 0x8027 -#define GL_HISTOGRAM_RED_SIZE 0x8028 -#define GL_HISTOGRAM_GREEN_SIZE 0x8029 -#define GL_HISTOGRAM_BLUE_SIZE 0x802A -#define GL_HISTOGRAM_ALPHA_SIZE 0x802B -#define GL_HISTOGRAM_LUMINANCE_SIZE 0x802C -#define GL_HISTOGRAM_SINK 0x802D -#define GL_MINMAX 0x802E -#define GL_MINMAX_FORMAT 0x802F -#define GL_MINMAX_SINK 0x8030 -#define GL_TABLE_TOO_LARGE 0x8031 -#define GL_BLEND_EQUATION 0x8009 -#define GL_MIN 0x8007 -#define GL_MAX 0x8008 -#define GL_FUNC_ADD 0x8006 -#define GL_FUNC_SUBTRACT 0x800A -#define GL_FUNC_REVERSE_SUBTRACT 0x800B -#define GL_BLEND_COLOR 0x8005 +#define GL_CONSTANT_COLOR 0x8001 +#define GL_ONE_MINUS_CONSTANT_COLOR 0x8002 +#define GL_CONSTANT_ALPHA 0x8003 +#define GL_ONE_MINUS_CONSTANT_ALPHA 0x8004 +#define GL_COLOR_TABLE 0x80D0 +#define GL_POST_CONVOLUTION_COLOR_TABLE 0x80D1 +#define GL_POST_COLOR_MATRIX_COLOR_TABLE 0x80D2 +#define GL_PROXY_COLOR_TABLE 0x80D3 +#define GL_PROXY_POST_CONVOLUTION_COLOR_TABLE 0x80D4 +#define GL_PROXY_POST_COLOR_MATRIX_COLOR_TABLE 0x80D5 +#define GL_COLOR_TABLE_SCALE 0x80D6 +#define GL_COLOR_TABLE_BIAS 0x80D7 +#define GL_COLOR_TABLE_FORMAT 0x80D8 +#define GL_COLOR_TABLE_WIDTH 0x80D9 +#define GL_COLOR_TABLE_RED_SIZE 0x80DA +#define GL_COLOR_TABLE_GREEN_SIZE 0x80DB +#define GL_COLOR_TABLE_BLUE_SIZE 0x80DC +#define GL_COLOR_TABLE_ALPHA_SIZE 0x80DD +#define GL_COLOR_TABLE_LUMINANCE_SIZE 0x80DE +#define GL_COLOR_TABLE_INTENSITY_SIZE 0x80DF +#define GL_CONVOLUTION_1D 0x8010 +#define GL_CONVOLUTION_2D 0x8011 +#define GL_SEPARABLE_2D 0x8012 +#define GL_CONVOLUTION_BORDER_MODE 0x8013 +#define GL_CONVOLUTION_FILTER_SCALE 0x8014 +#define GL_CONVOLUTION_FILTER_BIAS 0x8015 +#define GL_REDUCE 0x8016 +#define GL_CONVOLUTION_FORMAT 0x8017 +#define GL_CONVOLUTION_WIDTH 0x8018 +#define GL_CONVOLUTION_HEIGHT 0x8019 +#define GL_MAX_CONVOLUTION_WIDTH 0x801A +#define GL_MAX_CONVOLUTION_HEIGHT 0x801B +#define GL_POST_CONVOLUTION_RED_SCALE 0x801C +#define GL_POST_CONVOLUTION_GREEN_SCALE 0x801D +#define GL_POST_CONVOLUTION_BLUE_SCALE 0x801E +#define GL_POST_CONVOLUTION_ALPHA_SCALE 0x801F +#define GL_POST_CONVOLUTION_RED_BIAS 0x8020 +#define GL_POST_CONVOLUTION_GREEN_BIAS 0x8021 +#define GL_POST_CONVOLUTION_BLUE_BIAS 0x8022 +#define GL_POST_CONVOLUTION_ALPHA_BIAS 0x8023 +#define GL_CONSTANT_BORDER 0x8151 +#define GL_REPLICATE_BORDER 0x8153 +#define GL_CONVOLUTION_BORDER_COLOR 0x8154 +#define GL_COLOR_MATRIX 0x80B1 +#define GL_COLOR_MATRIX_STACK_DEPTH 0x80B2 +#define GL_MAX_COLOR_MATRIX_STACK_DEPTH 0x80B3 +#define GL_POST_COLOR_MATRIX_RED_SCALE 0x80B4 +#define GL_POST_COLOR_MATRIX_GREEN_SCALE 0x80B5 +#define GL_POST_COLOR_MATRIX_BLUE_SCALE 0x80B6 +#define GL_POST_COLOR_MATRIX_ALPHA_SCALE 0x80B7 +#define GL_POST_COLOR_MATRIX_RED_BIAS 0x80B8 +#define GL_POST_COLOR_MATRIX_GREEN_BIAS 0x80B9 +#define GL_POST_COLOR_MATRIX_BLUE_BIAS 0x80BA +#define GL_POST_COLOR_MATRIX_ALPHA_BIAS 0x80BB +#define GL_HISTOGRAM 0x8024 +#define GL_PROXY_HISTOGRAM 0x8025 +#define GL_HISTOGRAM_WIDTH 0x8026 +#define GL_HISTOGRAM_FORMAT 0x8027 +#define GL_HISTOGRAM_RED_SIZE 0x8028 +#define GL_HISTOGRAM_GREEN_SIZE 0x8029 +#define GL_HISTOGRAM_BLUE_SIZE 0x802A +#define GL_HISTOGRAM_ALPHA_SIZE 0x802B +#define GL_HISTOGRAM_LUMINANCE_SIZE 0x802C +#define GL_HISTOGRAM_SINK 0x802D +#define GL_MINMAX 0x802E +#define GL_MINMAX_FORMAT 0x802F +#define GL_MINMAX_SINK 0x8030 +#define GL_TABLE_TOO_LARGE 0x8031 +#define GL_BLEND_EQUATION 0x8009 +#define GL_MIN 0x8007 +#define GL_MAX 0x8008 +#define GL_FUNC_ADD 0x8006 +#define GL_FUNC_SUBTRACT 0x800A +#define GL_FUNC_REVERSE_SUBTRACT 0x800B +#define GL_BLEND_COLOR 0x8005 GLAPI void GLAPIENTRY glColorTable( GLenum target, GLenum internalformat, @@ -1691,22 +1691,22 @@ GLAPI void GLAPIENTRY glBlendColor( GLclampf red, GLclampf green, GLclampf blue, GLclampf alpha ); GLAPI void GLAPIENTRY glHistogram( GLenum target, GLsizei width, - GLenum internalformat, GLboolean sink ); + GLenum internalformat, GLboolean sink ); GLAPI void GLAPIENTRY glResetHistogram( GLenum target ); GLAPI void GLAPIENTRY glGetHistogram( GLenum target, GLboolean reset, - GLenum format, GLenum type, - GLvoid *values ); + GLenum format, GLenum type, + GLvoid *values ); GLAPI void GLAPIENTRY glGetHistogramParameterfv( GLenum target, GLenum pname, - GLfloat *params ); + GLfloat *params ); GLAPI void GLAPIENTRY glGetHistogramParameteriv( GLenum target, GLenum pname, - GLint *params ); + GLint *params ); GLAPI void GLAPIENTRY glMinmax( GLenum target, GLenum internalformat, - GLboolean sink ); + GLboolean sink ); GLAPI void GLAPIENTRY glResetMinmax( GLenum target ); @@ -1715,53 +1715,53 @@ GLAPI void GLAPIENTRY glGetMinmax( GLenum target, GLboolean reset, GLvoid *values ); GLAPI void GLAPIENTRY glGetMinmaxParameterfv( GLenum target, GLenum pname, - GLfloat *params ); + GLfloat *params ); GLAPI void GLAPIENTRY glGetMinmaxParameteriv( GLenum target, GLenum pname, - GLint *params ); + GLint *params ); GLAPI void GLAPIENTRY glConvolutionFilter1D( GLenum target, - GLenum internalformat, GLsizei width, GLenum format, GLenum type, - const GLvoid *image ); + GLenum internalformat, GLsizei width, GLenum format, GLenum type, + const GLvoid *image ); GLAPI void GLAPIENTRY glConvolutionFilter2D( GLenum target, - GLenum internalformat, GLsizei width, GLsizei height, GLenum format, - GLenum type, const GLvoid *image ); + GLenum internalformat, GLsizei width, GLsizei height, GLenum format, + GLenum type, const GLvoid *image ); GLAPI void GLAPIENTRY glConvolutionParameterf( GLenum target, GLenum pname, - GLfloat params ); + GLfloat params ); GLAPI void GLAPIENTRY glConvolutionParameterfv( GLenum target, GLenum pname, - const GLfloat *params ); + const GLfloat *params ); GLAPI void GLAPIENTRY glConvolutionParameteri( GLenum target, GLenum pname, - GLint params ); + GLint params ); GLAPI void GLAPIENTRY glConvolutionParameteriv( GLenum target, GLenum pname, - const GLint *params ); + const GLint *params ); GLAPI void GLAPIENTRY glCopyConvolutionFilter1D( GLenum target, - GLenum internalformat, GLint x, GLint y, GLsizei width ); + GLenum internalformat, GLint x, GLint y, GLsizei width ); GLAPI void GLAPIENTRY glCopyConvolutionFilter2D( GLenum target, - GLenum internalformat, GLint x, GLint y, GLsizei width, - GLsizei height); + GLenum internalformat, GLint x, GLint y, GLsizei width, + GLsizei height); GLAPI void GLAPIENTRY glGetConvolutionFilter( GLenum target, GLenum format, - GLenum type, GLvoid *image ); + GLenum type, GLvoid *image ); GLAPI void GLAPIENTRY glGetConvolutionParameterfv( GLenum target, GLenum pname, - GLfloat *params ); + GLfloat *params ); GLAPI void GLAPIENTRY glGetConvolutionParameteriv( GLenum target, GLenum pname, - GLint *params ); + GLint *params ); GLAPI void GLAPIENTRY glSeparableFilter2D( GLenum target, - GLenum internalformat, GLsizei width, GLsizei height, GLenum format, - GLenum type, const GLvoid *row, const GLvoid *column ); + GLenum internalformat, GLsizei width, GLsizei height, GLenum format, + GLenum type, const GLvoid *row, const GLvoid *column ); GLAPI void GLAPIENTRY glGetSeparableFilter( GLenum target, GLenum format, - GLenum type, GLvoid *row, GLvoid *column, GLvoid *span ); + GLenum type, GLvoid *row, GLvoid *column, GLvoid *span ); @@ -1771,109 +1771,109 @@ GLAPI void GLAPIENTRY glGetSeparableFilter( GLenum target, GLenum format, */ /* multitexture */ -#define GL_TEXTURE0 0x84C0 -#define GL_TEXTURE1 0x84C1 -#define GL_TEXTURE2 0x84C2 -#define GL_TEXTURE3 0x84C3 -#define GL_TEXTURE4 0x84C4 -#define GL_TEXTURE5 0x84C5 -#define GL_TEXTURE6 0x84C6 -#define GL_TEXTURE7 0x84C7 -#define GL_TEXTURE8 0x84C8 -#define GL_TEXTURE9 0x84C9 -#define GL_TEXTURE10 0x84CA -#define GL_TEXTURE11 0x84CB -#define GL_TEXTURE12 0x84CC -#define GL_TEXTURE13 0x84CD -#define GL_TEXTURE14 0x84CE -#define GL_TEXTURE15 0x84CF -#define GL_TEXTURE16 0x84D0 -#define GL_TEXTURE17 0x84D1 -#define GL_TEXTURE18 0x84D2 -#define GL_TEXTURE19 0x84D3 -#define GL_TEXTURE20 0x84D4 -#define GL_TEXTURE21 0x84D5 -#define GL_TEXTURE22 0x84D6 -#define GL_TEXTURE23 0x84D7 -#define GL_TEXTURE24 0x84D8 -#define GL_TEXTURE25 0x84D9 -#define GL_TEXTURE26 0x84DA -#define GL_TEXTURE27 0x84DB -#define GL_TEXTURE28 0x84DC -#define GL_TEXTURE29 0x84DD -#define GL_TEXTURE30 0x84DE -#define GL_TEXTURE31 0x84DF -#define GL_ACTIVE_TEXTURE 0x84E0 -#define GL_CLIENT_ACTIVE_TEXTURE 0x84E1 -#define GL_MAX_TEXTURE_UNITS 0x84E2 +#define GL_TEXTURE0 0x84C0 +#define GL_TEXTURE1 0x84C1 +#define GL_TEXTURE2 0x84C2 +#define GL_TEXTURE3 0x84C3 +#define GL_TEXTURE4 0x84C4 +#define GL_TEXTURE5 0x84C5 +#define GL_TEXTURE6 0x84C6 +#define GL_TEXTURE7 0x84C7 +#define GL_TEXTURE8 0x84C8 +#define GL_TEXTURE9 0x84C9 +#define GL_TEXTURE10 0x84CA +#define GL_TEXTURE11 0x84CB +#define GL_TEXTURE12 0x84CC +#define GL_TEXTURE13 0x84CD +#define GL_TEXTURE14 0x84CE +#define GL_TEXTURE15 0x84CF +#define GL_TEXTURE16 0x84D0 +#define GL_TEXTURE17 0x84D1 +#define GL_TEXTURE18 0x84D2 +#define GL_TEXTURE19 0x84D3 +#define GL_TEXTURE20 0x84D4 +#define GL_TEXTURE21 0x84D5 +#define GL_TEXTURE22 0x84D6 +#define GL_TEXTURE23 0x84D7 +#define GL_TEXTURE24 0x84D8 +#define GL_TEXTURE25 0x84D9 +#define GL_TEXTURE26 0x84DA +#define GL_TEXTURE27 0x84DB +#define GL_TEXTURE28 0x84DC +#define GL_TEXTURE29 0x84DD +#define GL_TEXTURE30 0x84DE +#define GL_TEXTURE31 0x84DF +#define GL_ACTIVE_TEXTURE 0x84E0 +#define GL_CLIENT_ACTIVE_TEXTURE 0x84E1 +#define GL_MAX_TEXTURE_UNITS 0x84E2 /* texture_cube_map */ -#define GL_NORMAL_MAP 0x8511 -#define GL_REFLECTION_MAP 0x8512 -#define GL_TEXTURE_CUBE_MAP 0x8513 -#define GL_TEXTURE_BINDING_CUBE_MAP 0x8514 -#define GL_TEXTURE_CUBE_MAP_POSITIVE_X 0x8515 -#define GL_TEXTURE_CUBE_MAP_NEGATIVE_X 0x8516 -#define GL_TEXTURE_CUBE_MAP_POSITIVE_Y 0x8517 -#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Y 0x8518 -#define GL_TEXTURE_CUBE_MAP_POSITIVE_Z 0x8519 -#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Z 0x851A -#define GL_PROXY_TEXTURE_CUBE_MAP 0x851B -#define GL_MAX_CUBE_MAP_TEXTURE_SIZE 0x851C +#define GL_NORMAL_MAP 0x8511 +#define GL_REFLECTION_MAP 0x8512 +#define GL_TEXTURE_CUBE_MAP 0x8513 +#define GL_TEXTURE_BINDING_CUBE_MAP 0x8514 +#define GL_TEXTURE_CUBE_MAP_POSITIVE_X 0x8515 +#define GL_TEXTURE_CUBE_MAP_NEGATIVE_X 0x8516 +#define GL_TEXTURE_CUBE_MAP_POSITIVE_Y 0x8517 +#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Y 0x8518 +#define GL_TEXTURE_CUBE_MAP_POSITIVE_Z 0x8519 +#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Z 0x851A +#define GL_PROXY_TEXTURE_CUBE_MAP 0x851B +#define GL_MAX_CUBE_MAP_TEXTURE_SIZE 0x851C /* texture_compression */ -#define GL_COMPRESSED_ALPHA 0x84E9 -#define GL_COMPRESSED_LUMINANCE 0x84EA -#define GL_COMPRESSED_LUMINANCE_ALPHA 0x84EB -#define GL_COMPRESSED_INTENSITY 0x84EC -#define GL_COMPRESSED_RGB 0x84ED -#define GL_COMPRESSED_RGBA 0x84EE -#define GL_TEXTURE_COMPRESSION_HINT 0x84EF -#define GL_TEXTURE_COMPRESSED_IMAGE_SIZE 0x86A0 -#define GL_TEXTURE_COMPRESSED 0x86A1 -#define GL_NUM_COMPRESSED_TEXTURE_FORMATS 0x86A2 -#define GL_COMPRESSED_TEXTURE_FORMATS 0x86A3 +#define GL_COMPRESSED_ALPHA 0x84E9 +#define GL_COMPRESSED_LUMINANCE 0x84EA +#define GL_COMPRESSED_LUMINANCE_ALPHA 0x84EB +#define GL_COMPRESSED_INTENSITY 0x84EC +#define GL_COMPRESSED_RGB 0x84ED +#define GL_COMPRESSED_RGBA 0x84EE +#define GL_TEXTURE_COMPRESSION_HINT 0x84EF +#define GL_TEXTURE_COMPRESSED_IMAGE_SIZE 0x86A0 +#define GL_TEXTURE_COMPRESSED 0x86A1 +#define GL_NUM_COMPRESSED_TEXTURE_FORMATS 0x86A2 +#define GL_COMPRESSED_TEXTURE_FORMATS 0x86A3 /* multisample */ -#define GL_MULTISAMPLE 0x809D -#define GL_SAMPLE_ALPHA_TO_COVERAGE 0x809E -#define GL_SAMPLE_ALPHA_TO_ONE 0x809F -#define GL_SAMPLE_COVERAGE 0x80A0 -#define GL_SAMPLE_BUFFERS 0x80A8 -#define GL_SAMPLES 0x80A9 -#define GL_SAMPLE_COVERAGE_VALUE 0x80AA -#define GL_SAMPLE_COVERAGE_INVERT 0x80AB -#define GL_MULTISAMPLE_BIT 0x20000000 +#define GL_MULTISAMPLE 0x809D +#define GL_SAMPLE_ALPHA_TO_COVERAGE 0x809E +#define GL_SAMPLE_ALPHA_TO_ONE 0x809F +#define GL_SAMPLE_COVERAGE 0x80A0 +#define GL_SAMPLE_BUFFERS 0x80A8 +#define GL_SAMPLES 0x80A9 +#define GL_SAMPLE_COVERAGE_VALUE 0x80AA +#define GL_SAMPLE_COVERAGE_INVERT 0x80AB +#define GL_MULTISAMPLE_BIT 0x20000000 /* transpose_matrix */ -#define GL_TRANSPOSE_MODELVIEW_MATRIX 0x84E3 -#define GL_TRANSPOSE_PROJECTION_MATRIX 0x84E4 -#define GL_TRANSPOSE_TEXTURE_MATRIX 0x84E5 -#define GL_TRANSPOSE_COLOR_MATRIX 0x84E6 +#define GL_TRANSPOSE_MODELVIEW_MATRIX 0x84E3 +#define GL_TRANSPOSE_PROJECTION_MATRIX 0x84E4 +#define GL_TRANSPOSE_TEXTURE_MATRIX 0x84E5 +#define GL_TRANSPOSE_COLOR_MATRIX 0x84E6 /* texture_env_combine */ -#define GL_COMBINE 0x8570 -#define GL_COMBINE_RGB 0x8571 -#define GL_COMBINE_ALPHA 0x8572 -#define GL_SOURCE0_RGB 0x8580 -#define GL_SOURCE1_RGB 0x8581 -#define GL_SOURCE2_RGB 0x8582 -#define GL_SOURCE0_ALPHA 0x8588 -#define GL_SOURCE1_ALPHA 0x8589 -#define GL_SOURCE2_ALPHA 0x858A -#define GL_OPERAND0_RGB 0x8590 -#define GL_OPERAND1_RGB 0x8591 -#define GL_OPERAND2_RGB 0x8592 -#define GL_OPERAND0_ALPHA 0x8598 -#define GL_OPERAND1_ALPHA 0x8599 -#define GL_OPERAND2_ALPHA 0x859A -#define GL_RGB_SCALE 0x8573 -#define GL_ADD_SIGNED 0x8574 -#define GL_INTERPOLATE 0x8575 -#define GL_SUBTRACT 0x84E7 -#define GL_CONSTANT 0x8576 -#define GL_PRIMARY_COLOR 0x8577 -#define GL_PREVIOUS 0x8578 +#define GL_COMBINE 0x8570 +#define GL_COMBINE_RGB 0x8571 +#define GL_COMBINE_ALPHA 0x8572 +#define GL_SOURCE0_RGB 0x8580 +#define GL_SOURCE1_RGB 0x8581 +#define GL_SOURCE2_RGB 0x8582 +#define GL_SOURCE0_ALPHA 0x8588 +#define GL_SOURCE1_ALPHA 0x8589 +#define GL_SOURCE2_ALPHA 0x858A +#define GL_OPERAND0_RGB 0x8590 +#define GL_OPERAND1_RGB 0x8591 +#define GL_OPERAND2_RGB 0x8592 +#define GL_OPERAND0_ALPHA 0x8598 +#define GL_OPERAND1_ALPHA 0x8599 +#define GL_OPERAND2_ALPHA 0x859A +#define GL_RGB_SCALE 0x8573 +#define GL_ADD_SIGNED 0x8574 +#define GL_INTERPOLATE 0x8575 +#define GL_SUBTRACT 0x84E7 +#define GL_CONSTANT 0x8576 +#define GL_PRIMARY_COLOR 0x8577 +#define GL_PREVIOUS 0x8578 /* texture_env_dot3 */ -#define GL_DOT3_RGB 0x86AE -#define GL_DOT3_RGBA 0x86AF +#define GL_DOT3_RGB 0x86AE +#define GL_DOT3_RGBA 0x86AF /* texture_border_clamp */ -#define GL_CLAMP_TO_BORDER 0x812D +#define GL_CLAMP_TO_BORDER 0x812D GLAPI void GLAPIENTRY glActiveTexture( GLenum texture ); @@ -1987,41 +1987,41 @@ typedef void (APIENTRYP PFNGLGETCOMPRESSEDTEXIMAGEPROC) (GLenum target, GLint le #ifndef GL_ARB_multitexture #define GL_ARB_multitexture 1 -#define GL_TEXTURE0_ARB 0x84C0 -#define GL_TEXTURE1_ARB 0x84C1 -#define GL_TEXTURE2_ARB 0x84C2 -#define GL_TEXTURE3_ARB 0x84C3 -#define GL_TEXTURE4_ARB 0x84C4 -#define GL_TEXTURE5_ARB 0x84C5 -#define GL_TEXTURE6_ARB 0x84C6 -#define GL_TEXTURE7_ARB 0x84C7 -#define GL_TEXTURE8_ARB 0x84C8 -#define GL_TEXTURE9_ARB 0x84C9 -#define GL_TEXTURE10_ARB 0x84CA -#define GL_TEXTURE11_ARB 0x84CB -#define GL_TEXTURE12_ARB 0x84CC -#define GL_TEXTURE13_ARB 0x84CD -#define GL_TEXTURE14_ARB 0x84CE -#define GL_TEXTURE15_ARB 0x84CF -#define GL_TEXTURE16_ARB 0x84D0 -#define GL_TEXTURE17_ARB 0x84D1 -#define GL_TEXTURE18_ARB 0x84D2 -#define GL_TEXTURE19_ARB 0x84D3 -#define GL_TEXTURE20_ARB 0x84D4 -#define GL_TEXTURE21_ARB 0x84D5 -#define GL_TEXTURE22_ARB 0x84D6 -#define GL_TEXTURE23_ARB 0x84D7 -#define GL_TEXTURE24_ARB 0x84D8 -#define GL_TEXTURE25_ARB 0x84D9 -#define GL_TEXTURE26_ARB 0x84DA -#define GL_TEXTURE27_ARB 0x84DB -#define GL_TEXTURE28_ARB 0x84DC -#define GL_TEXTURE29_ARB 0x84DD -#define GL_TEXTURE30_ARB 0x84DE -#define GL_TEXTURE31_ARB 0x84DF -#define GL_ACTIVE_TEXTURE_ARB 0x84E0 -#define GL_CLIENT_ACTIVE_TEXTURE_ARB 0x84E1 -#define GL_MAX_TEXTURE_UNITS_ARB 0x84E2 +#define GL_TEXTURE0_ARB 0x84C0 +#define GL_TEXTURE1_ARB 0x84C1 +#define GL_TEXTURE2_ARB 0x84C2 +#define GL_TEXTURE3_ARB 0x84C3 +#define GL_TEXTURE4_ARB 0x84C4 +#define GL_TEXTURE5_ARB 0x84C5 +#define GL_TEXTURE6_ARB 0x84C6 +#define GL_TEXTURE7_ARB 0x84C7 +#define GL_TEXTURE8_ARB 0x84C8 +#define GL_TEXTURE9_ARB 0x84C9 +#define GL_TEXTURE10_ARB 0x84CA +#define GL_TEXTURE11_ARB 0x84CB +#define GL_TEXTURE12_ARB 0x84CC +#define GL_TEXTURE13_ARB 0x84CD +#define GL_TEXTURE14_ARB 0x84CE +#define GL_TEXTURE15_ARB 0x84CF +#define GL_TEXTURE16_ARB 0x84D0 +#define GL_TEXTURE17_ARB 0x84D1 +#define GL_TEXTURE18_ARB 0x84D2 +#define GL_TEXTURE19_ARB 0x84D3 +#define GL_TEXTURE20_ARB 0x84D4 +#define GL_TEXTURE21_ARB 0x84D5 +#define GL_TEXTURE22_ARB 0x84D6 +#define GL_TEXTURE23_ARB 0x84D7 +#define GL_TEXTURE24_ARB 0x84D8 +#define GL_TEXTURE25_ARB 0x84D9 +#define GL_TEXTURE26_ARB 0x84DA +#define GL_TEXTURE27_ARB 0x84DB +#define GL_TEXTURE28_ARB 0x84DC +#define GL_TEXTURE29_ARB 0x84DD +#define GL_TEXTURE30_ARB 0x84DE +#define GL_TEXTURE31_ARB 0x84DF +#define GL_ACTIVE_TEXTURE_ARB 0x84E0 +#define GL_CLIENT_ACTIVE_TEXTURE_ARB 0x84E1 +#define GL_MAX_TEXTURE_UNITS_ARB 0x84E2 GLAPI void GLAPIENTRY glActiveTextureARB(GLenum texture); GLAPI void GLAPIENTRY glClientActiveTextureARB(GLenum texture); @@ -2114,11 +2114,11 @@ typedef void (APIENTRYP PFNGLMULTITEXCOORD4SVARBPROC) (GLenum target, const GLsh #ifndef GL_MESA_packed_depth_stencil #define GL_MESA_packed_depth_stencil 1 -#define GL_DEPTH_STENCIL_MESA 0x8750 -#define GL_UNSIGNED_INT_24_8_MESA 0x8751 -#define GL_UNSIGNED_INT_8_24_REV_MESA 0x8752 -#define GL_UNSIGNED_SHORT_15_1_MESA 0x8753 -#define GL_UNSIGNED_SHORT_1_15_REV_MESA 0x8754 +#define GL_DEPTH_STENCIL_MESA 0x8750 +#define GL_UNSIGNED_INT_24_8_MESA 0x8751 +#define GL_UNSIGNED_INT_8_24_REV_MESA 0x8752 +#define GL_UNSIGNED_SHORT_15_1_MESA 0x8753 +#define GL_UNSIGNED_SHORT_1_15_REV_MESA 0x8754 #endif /* GL_MESA_packed_depth_stencil */ @@ -2126,7 +2126,7 @@ typedef void (APIENTRYP PFNGLMULTITEXCOORD4SVARBPROC) (GLenum target, const GLsh #ifndef GL_ATI_blend_equation_separate #define GL_ATI_blend_equation_separate 1 -#define GL_ALPHA_BLEND_EQUATION_ATI 0x883D +#define GL_ALPHA_BLEND_EQUATION_ATI 0x883D GLAPI void GLAPIENTRY glBlendEquationSeparateATI( GLenum modeRGB, GLenum modeA ); typedef void (APIENTRYP PFNGLBLENDEQUATIONSEPARATEATIPROC) (GLenum modeRGB, GLenum modeA); diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h index e8ca8b13f1..7ed16f5300 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h @@ -1535,7 +1535,7 @@ typedef void (GL_APIENTRYP PFNGLFLUSHMAPPEDBUFFERRANGEEXTPROC) (GLenum target, G #ifndef GL_EXT_multisampled_render_to_texture #define GL_EXT_multisampled_render_to_texture 1 #ifdef GL_GLEXT_PROTOTYPES -GL_APICALL void GL_APIENTRY glRenderbufferStorageMultisampleEXT (GLenum target, GLsizei samples, GLenum internalformat, GLsizei width, GLsizei height); +GL_APICALL void GL_APIENTRY glRenderbufferStorageMultisampleEXT (GLenum target, GLsizei samples, GLenum internalformat, GLsizei width, GLsizei height); GL_APICALL void GL_APIENTRY glFramebufferTexture2DMultisampleEXT (GLenum target, GLenum attachment, GLenum textarget, GLuint texture, GLint level, GLsizei samples); #endif typedef void (GL_APIENTRYP PFNGLRENDERBUFFERSTORAGEMULTISAMPLEEXTPROC) (GLenum target, GLsizei samples, GLenum internalformat, GLsizei width, GLsizei height); diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h index c9e6f17d34..43aac97a73 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h @@ -223,7 +223,7 @@ typedef signed short int khronos_int16_t; typedef unsigned short int khronos_uint16_t; /* - * Types that differ between LLP64 and LP64 architectures - in LLP64, + * Types that differ between LLP64 and LP64 architectures - in LLP64, * pointers are 64 bits, but 'long' is still 32 bits. Win64 appears * to be the only LLP64 architecture in current use. */ diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_system.h b/bsp/simulator/SDL2-2.0.7/include/SDL_system.h index eb069b33d8..53075c2c78 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_system.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_system.h @@ -42,7 +42,7 @@ extern "C" { /* Platform specific functions for Windows */ #ifdef __WIN32__ - + /** \brief Set a function that is called for every windows message, before TranslateMessage() */ diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h b/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h index 43b67f521b..424d7eea7a 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h @@ -39,7 +39,7 @@ extern "C" { /** * \brief Start tracking SDL memory allocations - * + * * \note This should be called before any other SDL functions for complete tracking coverage */ int SDLTest_TrackAllocations(); diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h b/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h index d0f6575cd5..204cfe12aa 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h @@ -246,7 +246,7 @@ extern DECLSPEC void SDLCALL SDL_DetachThread(SDL_Thread * thread); * \code * static SDL_SpinLock tls_lock; * static SDL_TLSID thread_local_storage; - * + * * void SetMyThreadData(void *value) * { * if (!thread_local_storage) { @@ -258,7 +258,7 @@ extern DECLSPEC void SDLCALL SDL_DetachThread(SDL_Thread * thread); * } * SDL_TLSSet(thread_local_storage, value, 0); * } - * + * * void *GetMyThreadData(void) * { * return SDL_TLSGet(thread_local_storage); diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h b/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h index 803b5feef3..52d781135b 100644 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h +++ b/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h @@ -187,9 +187,9 @@ extern DECLSPEC void SDLCALL SDL_Vulkan_UnloadLibrary(void); * \sa SDL_Vulkan_CreateSurface() */ extern DECLSPEC SDL_bool SDLCALL SDL_Vulkan_GetInstanceExtensions( - SDL_Window *window, - unsigned int *pCount, - const char **pNames); + SDL_Window *window, + unsigned int *pCount, + const char **pNames); /** * \brief Create a Vulkan rendering surface for a window. @@ -221,9 +221,9 @@ extern DECLSPEC SDL_bool SDLCALL SDL_Vulkan_GetInstanceExtensions( * \sa SDL_Vulkan_GetInstanceExtensions() */ extern DECLSPEC SDL_bool SDLCALL SDL_Vulkan_CreateSurface( - SDL_Window *window, - VkInstance instance, - VkSurfaceKHR* surface); + SDL_Window *window, + VkInstance instance, + VkSurfaceKHR* surface); /** * \brief Get the size of a window's underlying drawable in pixels (for use diff --git a/bsp/simulator/applications/application.c b/bsp/simulator/applications/application.c index 656da63f61..dcbca14dee 100755 --- a/bsp/simulator/applications/application.c +++ b/bsp/simulator/applications/application.c @@ -1,27 +1,12 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-01-05 Bernard the first version */ - #include #include #include @@ -37,7 +22,7 @@ void rt_init_thread_entry(void *parameter) platform_init(); mnt_init(); - platform_post_init(); + platform_post_init(); #if defined(PKG_USING_GUIENGINE) && defined(GUIENGINE_USING_DEMO) { diff --git a/bsp/simulator/applications/mnt.c b/bsp/simulator/applications/mnt.c index 1a531ed2eb..39879d5817 100644 --- a/bsp/simulator/applications/mnt.c +++ b/bsp/simulator/applications/mnt.c @@ -1,12 +1,12 @@ /* - * File : mnt.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2017Äê4ÔÂ3ÈÕ Urey the first version + * 2017-04-03 Urey the first version */ - #include #include @@ -20,7 +20,7 @@ int mnt_init(void) #ifdef RT_USING_DFS_WINSHAREDIR extern int dfs_win32_init(void); extern rt_err_t rt_win_sharedir_init(const char *name); - + dfs_win32_init(); rt_win_sharedir_init("wshare"); diff --git a/bsp/simulator/applications/platform.c b/bsp/simulator/applications/platform.c index f4b0db41eb..a6bd636e4f 100644 --- a/bsp/simulator/applications/platform.c +++ b/bsp/simulator/applications/platform.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include "board.h" diff --git a/bsp/simulator/applications/startup.c b/bsp/simulator/applications/startup.c index 900d774844..7ae5374c77 100644 --- a/bsp/simulator/applications/startup.c +++ b/bsp/simulator/applications/startup.c @@ -1,27 +1,12 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2012-09-03 prife first implementation */ - #include #include diff --git a/bsp/simulator/drivers/board.c b/bsp/simulator/drivers/board.c index 2bf10263f2..b5037d6575 100755 --- a/bsp/simulator/drivers/board.c +++ b/bsp/simulator/drivers/board.c @@ -1,17 +1,12 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-01-05 Bernard first implementation */ - #include #include diff --git a/bsp/simulator/drivers/board.h b/bsp/simulator/drivers/board.h index 7edb856505..1643b0de5a 100644 --- a/bsp/simulator/drivers/board.h +++ b/bsp/simulator/drivers/board.h @@ -1,17 +1,12 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2009-09-22 Bernard add board.h to this bsp */ - #ifndef __BOARD_H__ #define __BOARD_H__ void rt_hw_board_init(void); diff --git a/bsp/simulator/drivers/dfs_win32.c b/bsp/simulator/drivers/dfs_win32.c index b275751efb..b910c2bf83 100644 --- a/bsp/simulator/drivers/dfs_win32.c +++ b/bsp/simulator/drivers/dfs_win32.c @@ -1,11 +1,7 @@ /* - * File : rtthread.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/simulator/drivers/module_win32.c b/bsp/simulator/drivers/module_win32.c index 8fcf3ef2fe..81a98eca87 100644 --- a/bsp/simulator/drivers/module_win32.c +++ b/bsp/simulator/drivers/module_win32.c @@ -1,11 +1,7 @@ /* - * File : module.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -130,7 +126,7 @@ void rt_module_unload_sethook(void (*hook)(rt_module_t module)) */ int rt_system_module_init(void) { - return 0; + return 0; } /** @@ -240,9 +236,9 @@ rt_module_t rt_module_open(const char *path) struct dfs_filesystem *fs; appentry_t fptr; HINSTANCE hinstlib; - rt_module_t module; + rt_module_t module; - char * winpath = RT_NULL; + char * winpath = RT_NULL; char * name = RT_NULL; RT_DEBUG_NOT_IN_INTERRUPT; @@ -353,60 +349,60 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_module_open, exec, exec module from a file); #define RT_MODULE_ARG_MAX 8 static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[]) { - int argc = 0; - char *ptr = cmd; + int argc = 0; + char *ptr = cmd; - while ((ptr - cmd) < length) - { - /* strip bank and tab */ - while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length) - *ptr++ = '\0'; - /* check whether it's the end of line */ - if ((ptr - cmd)>= length) break; + while ((ptr - cmd) < length) + { + /* strip bank and tab */ + while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length) + *ptr++ = '\0'; + /* check whether it's the end of line */ + if ((ptr - cmd)>= length) break; - /* handle string with quote */ - if (*ptr == '"') - { - argv[argc++] = ++ptr; + /* handle string with quote */ + if (*ptr == '"') + { + argv[argc++] = ++ptr; - /* skip this string */ - while (*ptr != '"' && (ptr-cmd) < length) - if (*ptr ++ == '\\') ptr ++; - if ((ptr - cmd) >= length) break; + /* skip this string */ + while (*ptr != '"' && (ptr-cmd) < length) + if (*ptr ++ == '\\') ptr ++; + if ((ptr - cmd) >= length) break; - /* skip '"' */ - *ptr ++ = '\0'; - } - else - { - argv[argc++] = ptr; - while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length) - ptr ++; - } + /* skip '"' */ + *ptr ++ = '\0'; + } + else + { + argv[argc++] = ptr; + while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length) + ptr ++; + } - if (argc >= RT_MODULE_ARG_MAX) break; - } + if (argc >= RT_MODULE_ARG_MAX) break; + } - return argc; + return argc; } /* module main thread entry */ static void module_main_entry(void* parameter) { - int argc; - char *argv[RT_MODULE_ARG_MAX]; - typedef int (*main_func_t)(int argc, char** argv); + int argc; + char *argv[RT_MODULE_ARG_MAX]; + typedef int (*main_func_t)(int argc, char** argv); - rt_module_t module = (rt_module_t) parameter; - if (module == RT_NULL || module->module_cmd_line == RT_NULL) return; + rt_module_t module = (rt_module_t) parameter; + if (module == RT_NULL || module->module_cmd_line == RT_NULL) return; - rt_memset(argv, 0x00, sizeof(argv)); - argc = _rt_module_split_arg((char*)module->module_cmd_line, module->module_cmd_size, argv); - if (argc == 0) return ; + rt_memset(argv, 0x00, sizeof(argv)); + argc = _rt_module_split_arg((char*)module->module_cmd_line, module->module_cmd_size, argv); + if (argc == 0) return ; - /* do the main function */ - ((main_func_t)module->module_entry)(argc, argv); - return; + /* do the main function */ + ((main_func_t)module->module_entry)(argc, argv); + return; } /** @@ -423,25 +419,25 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ struct dfs_filesystem *fs; appentry_t fptr; HINSTANCE hinstlib; - rt_module_t module; + rt_module_t module; - char * winpath = RT_NULL; + char * winpath = RT_NULL; char * name = RT_NULL; - char *full_path = RT_NULL; + char *full_path = RT_NULL; RT_DEBUG_NOT_IN_INTERRUPT; /* check parameters */ RT_ASSERT(path != RT_NULL); - if (*path != '/') - { - full_path = dfs_normalize_path(RT_NULL, path); - } - else - { - full_path = (const char*)path; - } + if (*path != '/') + { + full_path = dfs_normalize_path(RT_NULL, path); + } + else + { + full_path = (const char*)path; + } /* app module should only in DFS_WIN32 */ fs = dfs_filesystem_lookup(full_path); @@ -456,14 +452,14 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ if ((winpath = dfs_win32_dirdup((char *)full_path)) == RT_NULL) { rt_kprintf("out of memory, exit", path); - goto __exit; + goto __exit; } hinstlib = LoadLibrary(winpath); if (hinstlib == NULL) { rt_kprintf("error: unable to open %s\n", winpath); - goto __exit; + goto __exit; } fptr = (appentry_t)GetProcAddress(hinstlib, "main"); @@ -471,21 +467,21 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ { rt_kprintf("error: unable to find function in %s\n", winpath); FreeLibrary(hinstlib); - goto __exit; + goto __exit; } - /* release winpath */ - rt_free(winpath); + /* release winpath */ + rt_free(winpath); /* get the name of the module */ name = _module_name(path); /* allocate module */ module = (struct rt_module *)rt_object_allocate(RT_Object_Class_Module, name); - if (!module) - { - goto __exit; - } + if (!module) + { + goto __exit; + } module->nref = 0; module->module_entry = fptr; @@ -498,11 +494,11 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ if (module->module_entry != 0) { - /* set module argument */ - module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1); - rt_memcpy(module->module_cmd_line, cmd_line, line_size); - module->module_cmd_line[line_size] = '\0'; - module->module_cmd_size = line_size; + /* set module argument */ + module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1); + rt_memcpy(module->module_cmd_line, cmd_line, line_size); + module->module_cmd_line[line_size] = '\0'; + module->module_cmd_size = line_size; #ifdef RT_USING_SLAB /* init module memory allocator */ @@ -514,10 +510,10 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ module->page_cnt = 0; #endif - /* create module thread */ - module->module_thread = rt_thread_create(name, - module_main_entry, module, - 2048, RT_THREAD_PRIORITY_MAX - 2, 10); + /* create module thread */ + module->module_thread = rt_thread_create(name, + module_main_entry, module, + 2048, RT_THREAD_PRIORITY_MAX - 2, 10); /* set module id */ module->module_thread->module_id = (void *)module; @@ -543,11 +539,11 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_ return module; __exit: - if (full_path != path) rt_free(full_path); - if (name != RT_NULL) rt_free(full_path); - if (winpath != RT_NULL)rt_free(winpath); + if (full_path != path) rt_free(full_path); + if (name != RT_NULL) rt_free(full_path); + if (winpath != RT_NULL)rt_free(winpath); - return RT_NULL; + return RT_NULL; /* FreeLibrary(hinstlib); */ } diff --git a/bsp/simulator/drivers/nanddrv_file.c b/bsp/simulator/drivers/nanddrv_file.c index 075ed7f5d8..c47ffdbbe4 100644 --- a/bsp/simulator/drivers/nanddrv_file.c +++ b/bsp/simulator/drivers/nanddrv_file.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include #include diff --git a/bsp/simulator/drivers/sd_sim.c b/bsp/simulator/drivers/sd_sim.c index b317e5428d..41c495403a 100755 --- a/bsp/simulator/drivers/sd_sim.c +++ b/bsp/simulator/drivers/sd_sim.c @@ -1,3 +1,11 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include #include #include diff --git a/bsp/simulator/drivers/sdl_fb.c b/bsp/simulator/drivers/sdl_fb.c index 98da565a2a..986c3139de 100755 --- a/bsp/simulator/drivers/sdl_fb.c +++ b/bsp/simulator/drivers/sdl_fb.c @@ -1,7 +1,13 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ #include - #include - #ifdef _WIN32 #include #else @@ -190,7 +196,7 @@ static void sdlfb_hw_init(void) SDL_PixelFormatEnumToMasks(SDL_SCREEN_FORMAT, &bpp, &Rmask, &Gmask, &Bmask, &Amask); - _device.surface = SDL_CreateRGBSurface(0, SDL_SCREEN_WIDTH, SDL_SCREEN_HEIGHT, + _device.surface = SDL_CreateRGBSurface(0, SDL_SCREEN_WIDTH, SDL_SCREEN_HEIGHT, bpp, Rmask, Gmask, Bmask, Amask); } @@ -255,7 +261,7 @@ static void *sdl_loop(void *lpParam) int motion_tick = 50; int mouse_id = 1; - + #ifndef _WIN32 sigset_t sigmask, oldmask; /* set the getchar without buffer */ @@ -455,7 +461,7 @@ static void *sdl_loop(void *lpParam) exit(1); break; } - + } rt_hw_exit(); return 0; diff --git a/bsp/simulator/drivers/sst25vfxx_mtd.h b/bsp/simulator/drivers/sst25vfxx_mtd.h index cb0bb84129..202c6884a3 100644 --- a/bsp/simulator/drivers/sst25vfxx_mtd.h +++ b/bsp/simulator/drivers/sst25vfxx_mtd.h @@ -1,11 +1,7 @@ /* - * File : sst25vfxx_mtd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/simulator/drivers/sst25vfxx_mtd_sim.c b/bsp/simulator/drivers/sst25vfxx_mtd_sim.c index cd8894f612..4460e1da3b 100644 --- a/bsp/simulator/drivers/sst25vfxx_mtd_sim.c +++ b/bsp/simulator/drivers/sst25vfxx_mtd_sim.c @@ -1,11 +1,7 @@ /* - * File : rtdef.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -20,7 +16,7 @@ #ifdef RT_USING_MTD_NOR #define NOR_SIM "nor.bin" -/* JEDEC Manufacturer¡¯s ID */ +/* JEDEC Manufacturer’s ID */ #define MF_ID (0xBF) /* JEDEC Device ID : Memory Type */ #define MT_ID (0x25) diff --git a/bsp/simulator/drivers/tap_netif.c b/bsp/simulator/drivers/tap_netif.c index a8cd865c5e..8bac666cc0 100644 --- a/bsp/simulator/drivers/tap_netif.c +++ b/bsp/simulator/drivers/tap_netif.c @@ -33,7 +33,7 @@ #include #define MAX_ADDR_LEN 6 -#define TAP_IFNAME "RT-net" +#define TAP_IFNAME "RT-net" //============= // TAP IOCTLs @@ -112,13 +112,13 @@ static tap_win32_overlapped_t tap_overlapped; /************************************************************************/ struct tap_netif { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - tap_win32_overlapped_t *handle; + tap_win32_overlapped_t *handle; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; #define NETIF_DEVICE(netif) ((struct tap_netif*)(netif)) #define NETIF_TAP(netif) (NETIF_DEVICE(netif)->handle) @@ -505,12 +505,12 @@ static void tap_win32_thread_entry(void* param) unsigned long read_size; BOOL result; DWORD dwError; - tun_buffer_t* buffer; - struct eth_device* eth; + tun_buffer_t* buffer; + struct eth_device* eth; - eth = (struct eth_device*) &tap_netif_device; - overlapped = NETIF_TAP(&tap_netif_device); - buffer = get_buffer_from_free_list(overlapped); + eth = (struct eth_device*) &tap_netif_device; + overlapped = NETIF_TAP(&tap_netif_device); + buffer = get_buffer_from_free_list(overlapped); for (;;) { result = ReadFile(overlapped->handle, @@ -548,15 +548,15 @@ static void tap_win32_thread_entry(void* param) } if(read_size > 0) { - // rt_kprintf("rx packet, length=%d\n", read_size); + // rt_kprintf("rx packet, length=%d\n", read_size); - buffer->read_size = read_size; + buffer->read_size = read_size; put_buffer_on_output_queue(overlapped, buffer); - /* notify eth rx thread to receive packet */ - eth_device_ready(eth); + /* notify eth rx thread to receive packet */ + eth_device_ready(eth); - buffer = get_buffer_from_free_list(overlapped); + buffer = get_buffer_from_free_list(overlapped); } } } @@ -649,143 +649,143 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle, static rt_err_t tap_netif_init(rt_device_t dev) { - rt_thread_t tid; - tap_win32_overlapped_t *handle; + rt_thread_t tid; + tap_win32_overlapped_t *handle; - if (tap_win32_open(&handle, TAP_IFNAME) < 0) { - printf("tap: Could not open '%s'\n", TAP_IFNAME); - return -RT_ERROR; - } + if (tap_win32_open(&handle, TAP_IFNAME) < 0) { + printf("tap: Could not open '%s'\n", TAP_IFNAME); + return -RT_ERROR; + } - tap_netif_device.handle = handle; + tap_netif_device.handle = handle; - /* create recv thread */ - tid = rt_thread_create("tap", tap_win32_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX - 1, 10); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - } + /* create recv thread */ + tid = rt_thread_create("tap", tap_win32_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX - 1, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } - rt_thread_sleep(RT_TICK_PER_SECOND); + rt_thread_sleep(RT_TICK_PER_SECOND); - return RT_EOK; + return RT_EOK; } static rt_err_t tap_netif_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t tap_netif_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t tap_netif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t tap_netif_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t tap_netif_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, tap_netif_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, tap_netif_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } rt_err_t tap_netif_tx( rt_device_t dev, struct pbuf* p) { - struct pbuf *q; - char buffer[2048]; - int length; - tap_win32_overlapped_t *handle; - unsigned char* ptr; + struct pbuf *q; + char buffer[2048]; + int length; + tap_win32_overlapped_t *handle; + unsigned char* ptr; - handle = NETIF_TAP(dev); + handle = NETIF_TAP(dev); - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)buffer; - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } - length = p->tot_len; + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)buffer; + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } + length = p->tot_len; - tap_win32_write(handle, buffer, length); + tap_win32_write(handle, buffer, length); - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* unlock EMAC device */ + rt_sem_release(&sem_lock); - return RT_EOK; + return RT_EOK; } struct pbuf *tap_netif_rx(rt_device_t dev) { - struct pbuf* p = RT_NULL; - tap_win32_overlapped_t *handle; - rt_uint8_t *buf; - int max_size = 4096; - int size; + struct pbuf* p = RT_NULL; + tap_win32_overlapped_t *handle; + rt_uint8_t *buf; + int max_size = 4096; + int size; - handle = NETIF_TAP(dev); + handle = NETIF_TAP(dev); - size = tap_win32_read(handle, &buf, max_size); - if (size > 0) { - p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); - pbuf_take(p, buf, size); + size = tap_win32_read(handle, &buf, max_size); + if (size > 0) { + p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM); + pbuf_take(p, buf, size); - tap_win32_free_buffer(handle, buf); - } + tap_win32_free_buffer(handle, buf); + } - return p; + return p; } void tap_netif_hw_init(void) { - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - tap_netif_device.dev_addr[0] = 0x00; - tap_netif_device.dev_addr[1] = 0x60; - tap_netif_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - tap_netif_device.dev_addr[3] = 0x12; - tap_netif_device.dev_addr[4] = 0x34; - tap_netif_device.dev_addr[5] = 0x56; + tap_netif_device.dev_addr[0] = 0x00; + tap_netif_device.dev_addr[1] = 0x60; + tap_netif_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + tap_netif_device.dev_addr[3] = 0x12; + tap_netif_device.dev_addr[4] = 0x34; + tap_netif_device.dev_addr[5] = 0x56; - tap_netif_device.parent.parent.init = tap_netif_init; - tap_netif_device.parent.parent.open = tap_netif_open; - tap_netif_device.parent.parent.close = tap_netif_close; - tap_netif_device.parent.parent.read = tap_netif_read; - tap_netif_device.parent.parent.write = tap_netif_write; - tap_netif_device.parent.parent.control = tap_netif_control; - tap_netif_device.parent.parent.user_data= RT_NULL; + tap_netif_device.parent.parent.init = tap_netif_init; + tap_netif_device.parent.parent.open = tap_netif_open; + tap_netif_device.parent.parent.close = tap_netif_close; + tap_netif_device.parent.parent.read = tap_netif_read; + tap_netif_device.parent.parent.write = tap_netif_write; + tap_netif_device.parent.parent.control = tap_netif_control; + tap_netif_device.parent.parent.user_data= RT_NULL; - tap_netif_device.parent.eth_rx = tap_netif_rx; - tap_netif_device.parent.eth_tx = tap_netif_tx; + tap_netif_device.parent.eth_rx = tap_netif_rx; + tap_netif_device.parent.eth_tx = tap_netif_tx; - eth_device_init(&(tap_netif_device.parent), "e0"); + eth_device_init(&(tap_netif_device.parent), "e0"); } diff --git a/bsp/simulator/drivers/uart_console.c b/bsp/simulator/drivers/uart_console.c index 913daf2311..8fd799b297 100644 --- a/bsp/simulator/drivers/uart_console.c +++ b/bsp/simulator/drivers/uart_console.c @@ -1,5 +1,13 @@ -#include +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include #include #include #include @@ -88,11 +96,11 @@ static struct termios oldt, newt; /*simulate windows' getch(), it works!!*/ static void set_stty(void) { - /* get terminal input's attribute */ + /* get terminal input's attribute */ tcgetattr(STDIN_FILENO, &oldt); newt = oldt; - /* set termios' local mode */ + /* set termios' local mode */ newt.c_lflag &= ~(ECHO|ICANON); tcsetattr(STDIN_FILENO, TCSANOW, &newt); } @@ -117,10 +125,10 @@ static void * ThreadforKeyGet(void * lpParam) #ifndef _WIN32 sigset_t sigmask, oldmask; - /* set the getchar without buffer */ - sigfillset(&sigmask); - pthread_sigmask(SIG_BLOCK, &sigmask, &oldmask); - set_stty(); + /* set the getchar without buffer */ + sigfillset(&sigmask); + pthread_sigmask(SIG_BLOCK, &sigmask, &oldmask); + set_stty(); #endif (void)lpParam; //prevent compiler warnings @@ -217,7 +225,7 @@ static int console_putc(struct rt_serial_device *serial, char c) level = rt_hw_interrupt_disable(); fwrite(&c, 1, 1, stdout); - fflush(stdout); + fflush(stdout); rt_hw_interrupt_enable(level); return 1; } diff --git a/bsp/simulator/drivers/uart_console.h b/bsp/simulator/drivers/uart_console.h index 149a7a21f8..8ea20cc2f4 100644 --- a/bsp/simulator/drivers/uart_console.h +++ b/bsp/simulator/drivers/uart_console.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef UART_CONSOLE_H__ #define UART_CONSOLE_H__ diff --git a/bsp/simulator/dummy.c b/bsp/simulator/dummy.c index 67a38866cb..38584eb5fd 100644 --- a/bsp/simulator/dummy.c +++ b/bsp/simulator/dummy.c @@ -1,4 +1,13 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + int dummy_main() { - return 0; + return 0; } diff --git a/bsp/simulator/pcap/Include/Packet32.h b/bsp/simulator/pcap/Include/Packet32.h index 64be055d96..4dcafc1492 100644 --- a/bsp/simulator/pcap/Include/Packet32.h +++ b/bsp/simulator/pcap/Include/Packet32.h @@ -12,9 +12,9 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino, CACE Technologies - * nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written + * 3. Neither the name of the Politecnico di Torino, CACE Technologies + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS @@ -32,7 +32,7 @@ */ /** @ingroup packetapi - * @{ + * @{ */ /** @defgroup packet32h Packet.dll definitions and data structures @@ -70,19 +70,19 @@ typedef struct _AirpcapHandle *PAirpcapHandle; /// Alignment macro. Defines the alignment size. #define Packet_ALIGNMENT sizeof(int) -/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. +/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. #define Packet_WORDALIGN(x) (((x)+(Packet_ALIGNMENT-1))&~(Packet_ALIGNMENT-1)) -#define NdisMediumNull -1 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumCHDLC -2 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumPPPSerial -3 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumBare80211 -4 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumRadio80211 -5 ///< Custom linktype: NDIS doesn't provide an equivalent -#define NdisMediumPpi -6 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumNull -1 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumCHDLC -2 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumPPPSerial -3 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumBare80211 -4 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumRadio80211 -5 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumPpi -6 ///< Custom linktype: NDIS doesn't provide an equivalent // Loopback behaviour definitions -#define NPF_DISABLE_LOOPBACK 1 ///< Drop the packets sent by the NPF driver -#define NPF_ENABLE_LOOPBACK 2 ///< Capture the packets sent by the NPF driver +#define NPF_DISABLE_LOOPBACK 1 ///< Drop the packets sent by the NPF driver +#define NPF_ENABLE_LOOPBACK 2 ///< Capture the packets sent by the NPF driver /*! \brief Network type structure. @@ -91,8 +91,8 @@ typedef struct _AirpcapHandle *PAirpcapHandle; */ typedef struct NetType { - UINT LinkType; ///< The MAC of the current network adapter (see function PacketGetNetType() for more information) - ULONGLONG LinkSpeed; ///< The speed of the network in bits per second + UINT LinkType; ///< The MAC of the current network adapter (see function PacketGetNetType() for more information) + ULONGLONG LinkSpeed; ///< The speed of the network in bits per second }NetType; @@ -103,12 +103,12 @@ typedef struct NetType /*! \brief A BPF pseudo-assembly program. - The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. + The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. */ -struct bpf_program +struct bpf_program { - UINT bf_len; ///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow. - struct bpf_insn *bf_insns; ///< A pointer to the first instruction of the program. + UINT bf_len; ///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow. + struct bpf_insn *bf_insns; ///< A pointer to the first instruction of the program. }; /*! @@ -116,12 +116,12 @@ struct bpf_program bpf_insn contains a single instruction for the BPF register-machine. It is used to send a filter program to the driver. */ -struct bpf_insn +struct bpf_insn { - USHORT code; ///< Instruction type and addressing mode. - UCHAR jt; ///< Jump if true - UCHAR jf; ///< Jump if false - int k; ///< Generic field used for various purposes. + USHORT code; ///< Instruction type and addressing mode. + UCHAR jt; ///< Jump if true + UCHAR jf; ///< Jump if false + int k; ///< Generic field used for various purposes. }; /*! @@ -129,17 +129,17 @@ struct bpf_insn It is used by packet.dll to return statistics about a capture session. */ -struct bpf_stat +struct bpf_stat { - UINT bs_recv; ///< Number of packets that the driver received from the network adapter - ///< from the beginning of the current capture. This value includes the packets - ///< lost by the driver. - UINT bs_drop; ///< number of packets that the driver lost from the beginning of a capture. - ///< Basically, a packet is lost when the the buffer of the driver is full. - ///< In this situation the packet cannot be stored and the driver rejects it. - UINT ps_ifdrop; ///< drops by interface. XXX not yet supported - UINT bs_capt; ///< number of packets that pass the filter, find place in the kernel buffer and - ///< thus reach the application. + UINT bs_recv; ///< Number of packets that the driver received from the network adapter + ///< from the beginning of the current capture. This value includes the packets + ///< lost by the driver. + UINT bs_drop; ///< number of packets that the driver lost from the beginning of a capture. + ///< Basically, a packet is lost when the the buffer of the driver is full. + ///< In this situation the packet cannot be stored and the driver rejects it. + UINT ps_ifdrop; ///< drops by interface. XXX not yet supported + UINT bs_capt; ///< number of packets that pass the filter, find place in the kernel buffer and + ///< thus reach the application. }; /*! @@ -147,18 +147,18 @@ struct bpf_stat This structure defines the header associated with every packet delivered to the application. */ -struct bpf_hdr +struct bpf_hdr { - struct timeval bh_tstamp; ///< The timestamp associated with the captured packet. - ///< It is stored in a TimeVal structure. - UINT bh_caplen; ///< Length of captured portion. The captured portion can be different - ///< from the original packet, because it is possible (with a proper filter) - ///< to instruct the driver to capture only a portion of the packets. - UINT bh_datalen; ///< Original length of packet - USHORT bh_hdrlen; ///< Length of bpf header (this struct plus alignment padding). In some cases, - ///< a padding could be added between the end of this structure and the packet - ///< data for performance reasons. This filed can be used to retrieve the actual data - ///< of the packet. + struct timeval bh_tstamp; ///< The timestamp associated with the captured packet. + ///< It is stored in a TimeVal structure. + UINT bh_caplen; ///< Length of captured portion. The captured portion can be different + ///< from the original packet, because it is possible (with a proper filter) + ///< to instruct the driver to capture only a portion of the packets. + UINT bh_datalen; ///< Original length of packet + USHORT bh_hdrlen; ///< Length of bpf header (this struct plus alignment padding). In some cases, + ///< a padding could be added between the end of this structure and the packet + ///< data for performance reasons. This filed can be used to retrieve the actual data + ///< of the packet. }; /*! @@ -169,11 +169,11 @@ struct bpf_hdr packet in a dump file. This makes straightforward sending WinPcap dump files to the network. */ struct dump_bpf_hdr{ - struct timeval ts; ///< Time stamp of the packet - UINT caplen; ///< Length of captured portion. The captured portion can smaller than the - ///< the original packet, because it is possible (with a proper filter) to - ///< instruct the driver to capture only a portion of the packets. - UINT len; ///< Length of the original packet (off wire). + struct timeval ts; ///< Time stamp of the packet + UINT caplen; ///< Length of captured portion. The captured portion can smaller than the + ///< the original packet, because it is possible (with a proper filter) to + ///< instruct the driver to capture only a portion of the packets. + UINT len; ///< Length of the original packet (off wire). }; @@ -181,39 +181,39 @@ struct dump_bpf_hdr{ struct bpf_stat; -#define DOSNAMEPREFIX TEXT("Packet_") ///< Prefix added to the adapters device names to create the WinPcap devices -#define MAX_LINK_NAME_LENGTH 64 //< Maximum length of the devices symbolic links +#define DOSNAMEPREFIX TEXT("Packet_") ///< Prefix added to the adapters device names to create the WinPcap devices +#define MAX_LINK_NAME_LENGTH 64 //< Maximum length of the devices symbolic links #define NMAX_PACKET 65535 /*! \brief Addresses of a network adapter. - This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with + This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with an adapter. */ typedef struct npf_if_addr { - struct sockaddr_storage IPAddress; ///< IP address. - struct sockaddr_storage SubnetMask; ///< Netmask for that address. - struct sockaddr_storage Broadcast; ///< Broadcast address. + struct sockaddr_storage IPAddress; ///< IP address. + struct sockaddr_storage SubnetMask; ///< Netmask for that address. + struct sockaddr_storage Broadcast; ///< Broadcast address. }npf_if_addr; -#define ADAPTER_NAME_LENGTH 256 + 12 ///< Maximum length for the name of an adapter. The value is the same used by the IP Helper API. -#define ADAPTER_DESC_LENGTH 128 ///< Maximum length for the description of an adapter. The value is the same used by the IP Helper API. -#define MAX_MAC_ADDR_LENGTH 8 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. -#define MAX_NETWORK_ADDRESSES 16 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. +#define ADAPTER_NAME_LENGTH 256 + 12 ///< Maximum length for the name of an adapter. The value is the same used by the IP Helper API. +#define ADAPTER_DESC_LENGTH 128 ///< Maximum length for the description of an adapter. The value is the same used by the IP Helper API. +#define MAX_MAC_ADDR_LENGTH 8 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. +#define MAX_NETWORK_ADDRESSES 16 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. typedef struct WAN_ADAPTER_INT WAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API -#define INFO_FLAG_NDIS_ADAPTER 0 ///< Flag for ADAPTER_INFO: this is a traditional ndis adapter -#define INFO_FLAG_NDISWAN_ADAPTER 1 ///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET -#define INFO_FLAG_DAG_CARD 2 ///< Flag for ADAPTER_INFO: this is a DAG card -#define INFO_FLAG_DAG_FILE 6 ///< Flag for ADAPTER_INFO: this is a DAG file -#define INFO_FLAG_DONT_EXPORT 8 ///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones. -#define INFO_FLAG_AIRPCAP_CARD 16 ///< Flag for ADAPTER_INFO: this is an airpcap card -#define INFO_FLAG_NPFIM_DEVICE 32 +#define INFO_FLAG_NDIS_ADAPTER 0 ///< Flag for ADAPTER_INFO: this is a traditional ndis adapter +#define INFO_FLAG_NDISWAN_ADAPTER 1 ///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET +#define INFO_FLAG_DAG_CARD 2 ///< Flag for ADAPTER_INFO: this is a DAG card +#define INFO_FLAG_DAG_FILE 6 ///< Flag for ADAPTER_INFO: this is a DAG file +#define INFO_FLAG_DONT_EXPORT 8 ///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones. +#define INFO_FLAG_AIRPCAP_CARD 16 ///< Flag for ADAPTER_INFO: this is an airpcap card +#define INFO_FLAG_NPFIM_DEVICE 32 /*! \brief Describes an opened network adapter. @@ -221,39 +221,39 @@ typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) This structure is the most important for the functioning of packet.dll, but the great part of its fields should be ignored by the user, since the library offers functions that avoid to cope with low-level parameters */ -typedef struct _ADAPTER { - HANDLE hFile; ///< \internal Handle to an open instance of the NPF driver. - CHAR SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened. - int NumWrites; ///< \internal Number of times a packets written on this adapter will be repeated - ///< on the wire. - HANDLE ReadEvent; ///< A notification event associated with the read calls on the adapter. - ///< It can be passed to standard Win32 functions (like WaitForSingleObject - ///< or WaitForMultipleObjects) to wait until the driver's buffer contains some - ///< data. It is particularly useful in GUI applications that need to wait - ///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy() - ///< function can be used to define the minimum amount of data in the kernel buffer - ///< that will cause the event to be signalled. - - UINT ReadTimeOut; ///< \internal The amount of time after which a read on the driver will be released and - ///< ReadEvent will be signaled, also if no packets were captured - CHAR Name[ADAPTER_NAME_LENGTH]; - PWAN_ADAPTER pWanAdapter; - UINT Flags; ///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API. +typedef struct _ADAPTER { + HANDLE hFile; ///< \internal Handle to an open instance of the NPF driver. + CHAR SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened. + int NumWrites; ///< \internal Number of times a packets written on this adapter will be repeated + ///< on the wire. + HANDLE ReadEvent; ///< A notification event associated with the read calls on the adapter. + ///< It can be passed to standard Win32 functions (like WaitForSingleObject + ///< or WaitForMultipleObjects) to wait until the driver's buffer contains some + ///< data. It is particularly useful in GUI applications that need to wait + ///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy() + ///< function can be used to define the minimum amount of data in the kernel buffer + ///< that will cause the event to be signalled. + + UINT ReadTimeOut; ///< \internal The amount of time after which a read on the driver will be released and + ///< ReadEvent will be signaled, also if no packets were captured + CHAR Name[ADAPTER_NAME_LENGTH]; + PWAN_ADAPTER pWanAdapter; + UINT Flags; ///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API. #ifdef HAVE_AIRPCAP_API - PAirpcapHandle AirpcapAd; + PAirpcapHandle AirpcapAd; #endif // HAVE_AIRPCAP_API #ifdef HAVE_NPFIM_API - void* NpfImHandle; + void* NpfImHandle; #endif // HAVE_NPFIM_API #ifdef HAVE_DAG_API - dagc_t *pDagCard; ///< Pointer to the dagc API adapter descriptor for this adapter - PCHAR DagBuffer; ///< Pointer to the buffer with the packets that is received from the DAG card - struct timeval DagReadTimeout; ///< Read timeout. The dagc API requires a timeval structure - unsigned DagFcsLen; ///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry - DWORD DagFastProcess; ///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps). + dagc_t *pDagCard; ///< Pointer to the dagc API adapter descriptor for this adapter + PCHAR DagBuffer; ///< Pointer to the buffer with the packets that is received from the DAG card + struct timeval DagReadTimeout; ///< Read timeout. The dagc API requires a timeval structure + unsigned DagFcsLen; ///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry + DWORD DagFastProcess; ///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps). #endif // HAVE_DAG_API } ADAPTER, *LPADAPTER; @@ -262,31 +262,31 @@ typedef struct _ADAPTER { This structure defines the header associated with every packet delivered to the application. */ -typedef struct _PACKET { - HANDLE hEvent; ///< \deprecated Still present for compatibility with old applications. - OVERLAPPED OverLapped; ///< \deprecated Still present for compatibility with old applications. - PVOID Buffer; ///< Buffer with containing the packets. See the PacketReceivePacket() for - ///< details about the organization of the data in this buffer - UINT Length; ///< Length of the buffer - DWORD ulBytesReceived; ///< Number of valid bytes present in the buffer, i.e. amount of data - ///< received by the last call to PacketReceivePacket() - BOOLEAN bIoComplete; ///< \deprecated Still present for compatibility with old applications. +typedef struct _PACKET { + HANDLE hEvent; ///< \deprecated Still present for compatibility with old applications. + OVERLAPPED OverLapped; ///< \deprecated Still present for compatibility with old applications. + PVOID Buffer; ///< Buffer with containing the packets. See the PacketReceivePacket() for + ///< details about the organization of the data in this buffer + UINT Length; ///< Length of the buffer + DWORD ulBytesReceived; ///< Number of valid bytes present in the buffer, i.e. amount of data + ///< received by the last call to PacketReceivePacket() + BOOLEAN bIoComplete; ///< \deprecated Still present for compatibility with old applications. } PACKET, *LPPACKET; /*! \brief Structure containing an OID request. - It is used by the PacketRequest() function to send an OID to the interface card driver. - It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, + It is used by the PacketRequest() function to send an OID to the interface card driver. + It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, the list of the multicast groups defined on it, and so on. */ struct _PACKET_OID_DATA { - ULONG Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h - ///< for a complete list of valid codes. - ULONG Length; ///< Length of the data field - UCHAR Data[1]; ///< variable-lenght field that contains the information passed to or received - ///< from the adapter. -}; + ULONG Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h + ///< for a complete list of valid codes. + ULONG Length; ///< Length of the data field + UCHAR Data[1]; ///< variable-lenght field that contains the information passed to or received + ///< from the adapter. +}; typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA; #ifdef __cplusplus @@ -299,16 +299,16 @@ extern "C" { /* BOOLEAN QueryWinPcapRegistryStringA(CHAR *SubKeyName, - CHAR *Value, - UINT *pValueLen, - CHAR *DefaultVal); + CHAR *Value, + UINT *pValueLen, + CHAR *DefaultVal); BOOLEAN QueryWinPcapRegistryStringW(WCHAR *SubKeyName, - WCHAR *Value, - UINT *pValueLen, - WCHAR *DefaultVal); + WCHAR *Value, + UINT *pValueLen, + WCHAR *DefaultVal); */ - + //--------------------------------------------------------------------------- // EXPORTED FUNCTIONS //--------------------------------------------------------------------------- @@ -350,10 +350,10 @@ PAirpcapHandle PacketGetAirPcapHandle(LPADAPTER AdapterObject); // // Used by PacketStartOemEx // -#define PACKET_START_OEM_NO_NETMON 0x00000001 +#define PACKET_START_OEM_NO_NETMON 0x00000001 #ifdef __cplusplus } -#endif +#endif #endif //__PACKET32 diff --git a/bsp/simulator/pcap/Include/Win32-Extensions.h b/bsp/simulator/pcap/Include/Win32-Extensions.h index ad3be25cfa..42120290a9 100644 --- a/bsp/simulator/pcap/Include/Win32-Extensions.h +++ b/bsp/simulator/pcap/Include/Win32-Extensions.h @@ -12,9 +12,9 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino, CACE Technologies - * nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written + * 3. Neither the name of the Politecnico di Torino, CACE Technologies + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS @@ -45,9 +45,9 @@ extern "C" { */ struct pcap_send_queue { - u_int maxlen; ///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field. - u_int len; ///< Current size of the queue, in bytes. - char *buffer; ///< Buffer containing the packets to be sent. + u_int maxlen; ///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field. + u_int len; ///< Current size of the queue, in bytes. + char *buffer; ///< Buffer containing the packets to be sent. }; typedef struct pcap_send_queue pcap_send_queue; @@ -60,26 +60,26 @@ typedef struct pcap_send_queue pcap_send_queue; typedef struct _AirpcapHandle *PAirpcapHandle; #endif -#define BPF_MEM_EX_IMM 0xc0 -#define BPF_MEM_EX_IND 0xe0 +#define BPF_MEM_EX_IMM 0xc0 +#define BPF_MEM_EX_IND 0xe0 /*used for ST*/ -#define BPF_MEM_EX 0xc0 -#define BPF_TME 0x08 +#define BPF_MEM_EX 0xc0 +#define BPF_TME 0x08 -#define BPF_LOOKUP 0x90 -#define BPF_EXECUTE 0xa0 -#define BPF_INIT 0xb0 -#define BPF_VALIDATE 0xc0 -#define BPF_SET_ACTIVE 0xd0 -#define BPF_RESET 0xe0 -#define BPF_SET_MEMORY 0x80 -#define BPF_GET_REGISTER_VALUE 0x70 -#define BPF_SET_REGISTER_VALUE 0x60 -#define BPF_SET_WORKING 0x50 -#define BPF_SET_ACTIVE_READ 0x40 -#define BPF_SET_AUTODELETION 0x30 -#define BPF_SEPARATION 0xff +#define BPF_LOOKUP 0x90 +#define BPF_EXECUTE 0xa0 +#define BPF_INIT 0xb0 +#define BPF_VALIDATE 0xc0 +#define BPF_SET_ACTIVE 0xd0 +#define BPF_RESET 0xe0 +#define BPF_SET_MEMORY 0x80 +#define BPF_GET_REGISTER_VALUE 0x70 +#define BPF_SET_REGISTER_VALUE 0x60 +#define BPF_SET_WORKING 0x50 +#define BPF_SET_ACTIVE_READ 0x40 +#define BPF_SET_AUTODELETION 0x30 +#define BPF_SEPARATION 0xff /* Prototypes */ pcap_send_queue* pcap_sendqueue_alloc(u_int memsize); diff --git a/bsp/simulator/pcap/Include/bittypes.h b/bsp/simulator/pcap/Include/bittypes.h index 558a0b5c0d..e098671b58 100644 --- a/bsp/simulator/pcap/Include/bittypes.h +++ b/bsp/simulator/pcap/Include/bittypes.h @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 WIDE Project. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -13,7 +13,7 @@ * 3. Neither the name of the project nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ typedef signed int int8_t; #endif /* HAVE_U_INT8_T */ -#ifndef HAVE_U_INT16_T +#ifndef HAVE_U_INT16_T #if SIZEOF_SHORT == 2 typedef unsigned short u_int16_t; @@ -104,33 +104,33 @@ typedef unsigned short u_int64_t; #ifndef PRId64 #ifdef _MSC_EXTENSIONS -#define PRId64 "I64d" +#define PRId64 "I64d" #else /* _MSC_EXTENSIONS */ -#define PRId64 "lld" +#define PRId64 "lld" #endif /* _MSC_EXTENSIONS */ #endif /* PRId64 */ #ifndef PRIo64 #ifdef _MSC_EXTENSIONS -#define PRIo64 "I64o" +#define PRIo64 "I64o" #else /* _MSC_EXTENSIONS */ -#define PRIo64 "llo" +#define PRIo64 "llo" #endif /* _MSC_EXTENSIONS */ #endif /* PRIo64 */ #ifndef PRIx64 #ifdef _MSC_EXTENSIONS -#define PRIx64 "I64x" +#define PRIx64 "I64x" #else /* _MSC_EXTENSIONS */ -#define PRIx64 "llx" +#define PRIx64 "llx" #endif /* _MSC_EXTENSIONS */ #endif /* PRIx64 */ #ifndef PRIu64 #ifdef _MSC_EXTENSIONS -#define PRIu64 "I64u" +#define PRIu64 "I64u" #else /* _MSC_EXTENSIONS */ -#define PRIu64 "llu" +#define PRIu64 "llu" #endif /* _MSC_EXTENSIONS */ #endif /* PRIu64 */ diff --git a/bsp/simulator/pcap/Include/ip6_misc.h b/bsp/simulator/pcap/Include/ip6_misc.h index 562fa6184e..a55e8340d0 100644 --- a/bsp/simulator/pcap/Include/ip6_misc.h +++ b/bsp/simulator/pcap/Include/ip6_misc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 1993, 1994, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that: (1) source code distributions @@ -30,12 +30,12 @@ #include #ifndef __MINGW32__ -#define IN_MULTICAST(a) IN_CLASSD(a) +#define IN_MULTICAST(a) IN_CLASSD(a) #endif -#define IN_EXPERIMENTAL(a) ((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000) +#define IN_EXPERIMENTAL(a) ((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000) -#define IN_LOOPBACKNET 127 +#define IN_LOOPBACKNET 127 #if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) /* IPv6 address */ @@ -43,14 +43,14 @@ struct in6_addr { union { - u_int8_t u6_addr8[16]; - u_int16_t u6_addr16[8]; - u_int32_t u6_addr32[4]; + u_int8_t u6_addr8[16]; + u_int16_t u6_addr16[8]; + u_int32_t u6_addr32[4]; } in6_u; -#define s6_addr in6_u.u6_addr8 -#define s6_addr16 in6_u.u6_addr16 -#define s6_addr32 in6_u.u6_addr32 -#define s6_addr64 in6_u.u6_addr64 +#define s6_addr in6_u.u6_addr8 +#define s6_addr16 in6_u.u6_addr16 +#define s6_addr32 in6_u.u6_addr32 +#define s6_addr64 in6_u.u6_addr64 }; #define IN6ADDR_ANY_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } @@ -59,36 +59,36 @@ struct in6_addr #if (defined _MSC_VER) || (defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)) -typedef unsigned short sa_family_t; +typedef unsigned short sa_family_t; #endif #if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) -#define __SOCKADDR_COMMON(sa_prefix) \ +#define __SOCKADDR_COMMON(sa_prefix) \ sa_family_t sa_prefix##family /* Ditto, for IPv6. */ struct sockaddr_in6 { __SOCKADDR_COMMON (sin6_); - u_int16_t sin6_port; /* Transport layer port # */ - u_int32_t sin6_flowinfo; /* IPv6 flow information */ - struct in6_addr sin6_addr; /* IPv6 address */ + u_int16_t sin6_port; /* Transport layer port # */ + u_int32_t sin6_flowinfo; /* IPv6 flow information */ + struct in6_addr sin6_addr; /* IPv6 address */ }; #define IN6_IS_ADDR_V4MAPPED(a) \ - ((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \ - (((u_int32_t *) (a))[2] == htonl (0xffff))) + ((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \ + (((u_int32_t *) (a))[2] == htonl (0xffff))) #define IN6_IS_ADDR_MULTICAST(a) (((u_int8_t *) (a))[0] == 0xff) #define IN6_IS_ADDR_LINKLOCAL(a) \ - ((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000)) + ((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000)) #define IN6_IS_ADDR_LOOPBACK(a) \ - (((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \ - ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1)) + (((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \ + ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1)) #endif /* __MINGW32__ */ #define ip6_vfc ip6_ctlun.ip6_un2_vfc @@ -104,60 +104,60 @@ struct sockaddr_in6 #define nd_rd_reserved nd_rd_hdr.icmp6_data32[0] /* - * IPV6 extension headers + * IPV6 extension headers */ -#define IPPROTO_HOPOPTS 0 /* IPv6 hop-by-hop options */ -#define IPPROTO_IPV6 41 /* IPv6 header. */ -#define IPPROTO_ROUTING 43 /* IPv6 routing header */ -#define IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */ -#define IPPROTO_ESP 50 /* encapsulating security payload */ -#define IPPROTO_AH 51 /* authentication header */ -#define IPPROTO_ICMPV6 58 /* ICMPv6 */ -#define IPPROTO_NONE 59 /* IPv6 no next header */ -#define IPPROTO_DSTOPTS 60 /* IPv6 destination options */ -#define IPPROTO_PIM 103 /* Protocol Independent Multicast. */ +#define IPPROTO_HOPOPTS 0 /* IPv6 hop-by-hop options */ +#define IPPROTO_IPV6 41 /* IPv6 header. */ +#define IPPROTO_ROUTING 43 /* IPv6 routing header */ +#define IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */ +#define IPPROTO_ESP 50 /* encapsulating security payload */ +#define IPPROTO_AH 51 /* authentication header */ +#define IPPROTO_ICMPV6 58 /* ICMPv6 */ +#define IPPROTO_NONE 59 /* IPv6 no next header */ +#define IPPROTO_DSTOPTS 60 /* IPv6 destination options */ +#define IPPROTO_PIM 103 /* Protocol Independent Multicast. */ -#define IPV6_RTHDR_TYPE_0 0 +#define IPV6_RTHDR_TYPE_0 0 /* Option types and related macros */ -#define IP6OPT_PAD1 0x00 /* 00 0 00000 */ -#define IP6OPT_PADN 0x01 /* 00 0 00001 */ -#define IP6OPT_JUMBO 0xC2 /* 11 0 00010 = 194 */ -#define IP6OPT_JUMBO_LEN 6 -#define IP6OPT_ROUTER_ALERT 0x05 /* 00 0 00101 */ +#define IP6OPT_PAD1 0x00 /* 00 0 00000 */ +#define IP6OPT_PADN 0x01 /* 00 0 00001 */ +#define IP6OPT_JUMBO 0xC2 /* 11 0 00010 = 194 */ +#define IP6OPT_JUMBO_LEN 6 +#define IP6OPT_ROUTER_ALERT 0x05 /* 00 0 00101 */ -#define IP6OPT_RTALERT_LEN 4 -#define IP6OPT_RTALERT_MLD 0 /* Datagram contains an MLD message */ -#define IP6OPT_RTALERT_RSVP 1 /* Datagram contains an RSVP message */ -#define IP6OPT_RTALERT_ACTNET 2 /* contains an Active Networks msg */ -#define IP6OPT_MINLEN 2 +#define IP6OPT_RTALERT_LEN 4 +#define IP6OPT_RTALERT_MLD 0 /* Datagram contains an MLD message */ +#define IP6OPT_RTALERT_RSVP 1 /* Datagram contains an RSVP message */ +#define IP6OPT_RTALERT_ACTNET 2 /* contains an Active Networks msg */ +#define IP6OPT_MINLEN 2 -#define IP6OPT_BINDING_UPDATE 0xc6 /* 11 0 00110 */ -#define IP6OPT_BINDING_ACK 0x07 /* 00 0 00111 */ -#define IP6OPT_BINDING_REQ 0x08 /* 00 0 01000 */ -#define IP6OPT_HOME_ADDRESS 0xc9 /* 11 0 01001 */ -#define IP6OPT_EID 0x8a /* 10 0 01010 */ +#define IP6OPT_BINDING_UPDATE 0xc6 /* 11 0 00110 */ +#define IP6OPT_BINDING_ACK 0x07 /* 00 0 00111 */ +#define IP6OPT_BINDING_REQ 0x08 /* 00 0 01000 */ +#define IP6OPT_HOME_ADDRESS 0xc9 /* 11 0 01001 */ +#define IP6OPT_EID 0x8a /* 10 0 01010 */ -#define IP6OPT_TYPE(o) ((o) & 0xC0) -#define IP6OPT_TYPE_SKIP 0x00 -#define IP6OPT_TYPE_DISCARD 0x40 -#define IP6OPT_TYPE_FORCEICMP 0x80 -#define IP6OPT_TYPE_ICMP 0xC0 +#define IP6OPT_TYPE(o) ((o) & 0xC0) +#define IP6OPT_TYPE_SKIP 0x00 +#define IP6OPT_TYPE_DISCARD 0x40 +#define IP6OPT_TYPE_FORCEICMP 0x80 +#define IP6OPT_TYPE_ICMP 0xC0 -#define IP6OPT_MUTABLE 0x20 +#define IP6OPT_MUTABLE 0x20 #if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) #ifndef EAI_ADDRFAMILY struct addrinfo { - int ai_flags; /* AI_PASSIVE, AI_CANONNAME */ - int ai_family; /* PF_xxx */ - int ai_socktype; /* SOCK_xxx */ - int ai_protocol; /* 0 or IPPROTO_xxx for IPv4 and IPv6 */ - size_t ai_addrlen; /* length of ai_addr */ - char *ai_canonname; /* canonical name for hostname */ - struct sockaddr *ai_addr; /* binary address */ - struct addrinfo *ai_next; /* next structure in linked list */ + int ai_flags; /* AI_PASSIVE, AI_CANONNAME */ + int ai_family; /* PF_xxx */ + int ai_socktype; /* SOCK_xxx */ + int ai_protocol; /* 0 or IPPROTO_xxx for IPv4 and IPv6 */ + size_t ai_addrlen; /* length of ai_addr */ + char *ai_canonname; /* canonical name for hostname */ + struct sockaddr *ai_addr; /* binary address */ + struct addrinfo *ai_next; /* next structure in linked list */ }; #endif #endif /* __MINGW32__ */ diff --git a/bsp/simulator/pcap/Include/pcap-bpf.h b/bsp/simulator/pcap/Include/pcap-bpf.h index 5fe129dbb4..b272e63002 100644 --- a/bsp/simulator/pcap/Include/pcap-bpf.h +++ b/bsp/simulator/pcap/Include/pcap-bpf.h @@ -1,10 +1,10 @@ /*- * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * This code is derived from the Stanford/CMU enet packet filter, * (net/enet.c) distributed as part of 4.3BSD, and code contributed - * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence * Berkeley Laboratory. * * Redistribution and use in source and binary forms, with or without diff --git a/bsp/simulator/pcap/Include/pcap-namedb.h b/bsp/simulator/pcap/Include/pcap-namedb.h index 80a2f00401..c1e255ca22 100644 --- a/bsp/simulator/pcap/Include/pcap-namedb.h +++ b/bsp/simulator/pcap/Include/pcap-namedb.h @@ -1,6 +1,6 @@ /* * Copyright (c) 1994, 1996 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -12,8 +12,8 @@ * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. * 4. Neither the name of the University nor of the Laboratory may be used * to endorse or promote products derived from this software without * specific prior written permission. diff --git a/bsp/simulator/pcap/Include/pcap-stdinc.h b/bsp/simulator/pcap/Include/pcap-stdinc.h index 417604177b..46100ccca5 100644 --- a/bsp/simulator/pcap/Include/pcap-stdinc.h +++ b/bsp/simulator/pcap/Include/pcap-stdinc.h @@ -39,7 +39,7 @@ #endif /* - * Avoids a compiler warning in case this was already defined + * Avoids a compiler warning in case this was already defined * (someone defined _WINSOCKAPI_ when including 'windows.h', in order * to prevent it from including 'winsock.h') */ @@ -66,7 +66,7 @@ #define strdup _strdup #endif -#define inline __inline +#define inline __inline #ifdef __MINGW32__ #include @@ -88,6 +88,6 @@ typedef __int64 intptr_t; typedef _W64 int intptr_t; #endif #define _INTPTR_T_DEFINED -#endif +#endif #endif /*__MINGW32__*/ diff --git a/bsp/simulator/pcap/Include/pcap.h b/bsp/simulator/pcap/Include/pcap.h index 935f9494c1..8540af309c 100644 --- a/bsp/simulator/pcap/Include/pcap.h +++ b/bsp/simulator/pcap/Include/pcap.h @@ -1,6 +1,6 @@ /* * Copyright (c) 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -12,8 +12,8 @@ * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. * 4. Neither the name of the University nor of the Laboratory may be used * to endorse or promote products derived from this software without * specific prior written permission. diff --git a/bsp/simulator/pcap/Include/pcap/bluetooth.h b/bsp/simulator/pcap/Include/pcap/bluetooth.h index 7bf65df034..097499eab3 100644 --- a/bsp/simulator/pcap/Include/pcap/bluetooth.h +++ b/bsp/simulator/pcap/Include/pcap/bluetooth.h @@ -11,8 +11,8 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior written + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS @@ -32,7 +32,7 @@ * * @(#) $Header: /tcpdump/master/libpcap/pcap/bluetooth.h,v 1.1 2007/09/22 02:10:17 guy Exp $ */ - + #ifndef _PCAP_BLUETOOTH_STRUCTS_H__ #define _PCAP_BLUETOOTH_STRUCTS_H__ @@ -41,7 +41,7 @@ * fields are in network byte order */ typedef struct _pcap_bluetooth_h4_header { - u_int32_t direction; /* if first bit is set direction is incoming */ + u_int32_t direction; /* if first bit is set direction is incoming */ } pcap_bluetooth_h4_header; diff --git a/bsp/simulator/pcap/Include/pcap/bpf.h b/bsp/simulator/pcap/Include/pcap/bpf.h index 9f4ca33e35..fce0a3c130 100644 --- a/bsp/simulator/pcap/Include/pcap/bpf.h +++ b/bsp/simulator/pcap/Include/pcap/bpf.h @@ -1,10 +1,10 @@ /*- * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * This code is derived from the Stanford/CMU enet packet filter, * (net/enet.c) distributed as part of 4.3BSD, and code contributed - * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence * Berkeley Laboratory. * * Redistribution and use in source and binary forms, with or without @@ -64,13 +64,13 @@ extern "C" { typedef long bpf_int32; typedef unsigned long bpf_u_int32; #else -typedef int bpf_int32; -typedef u_int bpf_u_int32; +typedef int bpf_int32; +typedef u_int bpf_u_int32; #endif /* - * Alignment macros. BPF_WORDALIGN rounds up to the next - * even multiple of BPF_ALIGNMENT. + * Alignment macros. BPF_WORDALIGN rounds up to the next + * even multiple of BPF_ALIGNMENT. */ #ifndef __NetBSD__ #define BPF_ALIGNMENT sizeof(bpf_int32) @@ -86,12 +86,12 @@ typedef u_int bpf_u_int32; * Structure for "pcap_compile()", "pcap_setfilter()", etc.. */ struct bpf_program { - u_int bf_len; - struct bpf_insn *bf_insns; + u_int bf_len; + struct bpf_insn *bf_insns; }; - + /* - * Struct return by BIOCVERSION. This represents the version number of + * Struct return by BIOCVERSION. This represents the version number of * the filter language described by the instruction encodings below. * bpf understands a program iff kernel_major == filter_major && * kernel_minor >= filter_minor, that is, if the value returned by the @@ -102,8 +102,8 @@ struct bpf_program { * It has nothing to do with the source code version. */ struct bpf_version { - u_short bv_major; - u_short bv_minor; + u_short bv_major; + u_short bv_minor; }; /* Current version number of filter architecture. */ #define BPF_MAJOR_VERSION 1 @@ -125,17 +125,17 @@ struct bpf_version { * These are the types that are the same on all platforms, and that * have been defined by for ages. */ -#define DLT_NULL 0 /* BSD loopback encapsulation */ -#define DLT_EN10MB 1 /* Ethernet (10Mb) */ -#define DLT_EN3MB 2 /* Experimental Ethernet (3Mb) */ -#define DLT_AX25 3 /* Amateur Radio AX.25 */ -#define DLT_PRONET 4 /* Proteon ProNET Token Ring */ -#define DLT_CHAOS 5 /* Chaos */ -#define DLT_IEEE802 6 /* 802.5 Token Ring */ -#define DLT_ARCNET 7 /* ARCNET, with BSD-style header */ -#define DLT_SLIP 8 /* Serial Line IP */ -#define DLT_PPP 9 /* Point-to-point Protocol */ -#define DLT_FDDI 10 /* FDDI */ +#define DLT_NULL 0 /* BSD loopback encapsulation */ +#define DLT_EN10MB 1 /* Ethernet (10Mb) */ +#define DLT_EN3MB 2 /* Experimental Ethernet (3Mb) */ +#define DLT_AX25 3 /* Amateur Radio AX.25 */ +#define DLT_PRONET 4 /* Proteon ProNET Token Ring */ +#define DLT_CHAOS 5 /* Chaos */ +#define DLT_IEEE802 6 /* 802.5 Token Ring */ +#define DLT_ARCNET 7 /* ARCNET, with BSD-style header */ +#define DLT_SLIP 8 /* Serial Line IP */ +#define DLT_PPP 9 /* Point-to-point Protocol */ +#define DLT_FDDI 10 /* FDDI */ /* * These are types that are different on some platforms, and that @@ -146,12 +146,12 @@ struct bpf_version { * XXX - DLT_ATM_RFC1483 is 13 in BSD/OS, and DLT_RAW is 14 in BSD/OS, * but I don't know what the right #define is for BSD/OS. */ -#define DLT_ATM_RFC1483 11 /* LLC-encapsulated ATM */ +#define DLT_ATM_RFC1483 11 /* LLC-encapsulated ATM */ #ifdef __OpenBSD__ -#define DLT_RAW 14 /* raw IP */ +#define DLT_RAW 14 /* raw IP */ #else -#define DLT_RAW 12 /* raw IP */ +#define DLT_RAW 12 /* raw IP */ #endif /* @@ -162,12 +162,12 @@ struct bpf_version { */ #if defined(__NetBSD__) || defined(__FreeBSD__) #ifndef DLT_SLIP_BSDOS -#define DLT_SLIP_BSDOS 13 /* BSD/OS Serial Line IP */ -#define DLT_PPP_BSDOS 14 /* BSD/OS Point-to-point Protocol */ +#define DLT_SLIP_BSDOS 13 /* BSD/OS Serial Line IP */ +#define DLT_PPP_BSDOS 14 /* BSD/OS Point-to-point Protocol */ #endif #else -#define DLT_SLIP_BSDOS 15 /* BSD/OS Serial Line IP */ -#define DLT_PPP_BSDOS 16 /* BSD/OS Point-to-point Protocol */ +#define DLT_SLIP_BSDOS 15 /* BSD/OS Serial Line IP */ +#define DLT_PPP_BSDOS 16 /* BSD/OS Point-to-point Protocol */ #endif /* @@ -176,21 +176,21 @@ struct bpf_version { * 18 is used for DLT_PFSYNC in OpenBSD; don't use it for anything else. */ -#define DLT_ATM_CLIP 19 /* Linux Classical-IP over ATM */ +#define DLT_ATM_CLIP 19 /* Linux Classical-IP over ATM */ /* * Apparently Redback uses this for its SmartEdge 400/800. I hope * nobody else decided to use it, too. */ -#define DLT_REDBACK_SMARTEDGE 32 +#define DLT_REDBACK_SMARTEDGE 32 /* * These values are defined by NetBSD; other platforms should refrain from * using them for other purposes, so that NetBSD savefiles with link * types of 50 or 51 can be read as this type on all platforms. */ -#define DLT_PPP_SERIAL 50 /* PPP over serial with HDLC encapsulation */ -#define DLT_PPP_ETHER 51 /* PPP over Ethernet */ +#define DLT_PPP_SERIAL 50 /* PPP over serial with HDLC encapsulation */ +#define DLT_PPP_ETHER 51 /* PPP over Ethernet */ /* * The Axent Raptor firewall - now the Symantec Enterprise Firewall - uses @@ -199,7 +199,7 @@ struct bpf_version { * Ethernet type, and 36 bytes that appear to be 0 in at least one capture * I've seen. */ -#define DLT_SYMANTEC_FIREWALL 99 +#define DLT_SYMANTEC_FIREWALL 99 /* * Values between 100 and 103 are used in capture file headers as @@ -221,10 +221,10 @@ struct bpf_version { * libpcap 0.5 defined it as DLT_CHDLC; we define DLT_CHDLC as well, * for source compatibility with programs written for libpcap 0.5. */ -#define DLT_C_HDLC 104 /* Cisco HDLC */ -#define DLT_CHDLC DLT_C_HDLC +#define DLT_C_HDLC 104 /* Cisco HDLC */ +#define DLT_CHDLC DLT_C_HDLC -#define DLT_IEEE802_11 105 /* IEEE 802.11 wireless */ +#define DLT_IEEE802_11 105 /* IEEE 802.11 wireless */ /* * 106 is reserved for Linux Classical IP over ATM; it's like DLT_RAW, @@ -239,7 +239,7 @@ struct bpf_version { * DLT_FR and DLT_FRELAY packets start with the Q.922 Frame Relay header * (DLCI, etc.). */ -#define DLT_FRELAY 107 +#define DLT_FRELAY 107 /* * OpenBSD DLT_LOOP, for loopback devices; it's like DLT_NULL, except @@ -249,9 +249,9 @@ struct bpf_version { * we don't use 12 for it in OSes other than OpenBSD. */ #ifdef __OpenBSD__ -#define DLT_LOOP 12 +#define DLT_LOOP 12 #else -#define DLT_LOOP 108 +#define DLT_LOOP 108 #endif /* @@ -260,9 +260,9 @@ struct bpf_version { * than OpenBSD. */ #ifdef __OpenBSD__ -#define DLT_ENC 13 +#define DLT_ENC 13 #else -#define DLT_ENC 109 +#define DLT_ENC 109 #endif /* @@ -275,22 +275,22 @@ struct bpf_version { /* * This is for Linux cooked sockets. */ -#define DLT_LINUX_SLL 113 +#define DLT_LINUX_SLL 113 /* * Apple LocalTalk hardware. */ -#define DLT_LTALK 114 +#define DLT_LTALK 114 /* * Acorn Econet. */ -#define DLT_ECONET 115 +#define DLT_ECONET 115 /* * Reserved for use with OpenBSD ipfilter. */ -#define DLT_IPFILTER 116 +#define DLT_IPFILTER 116 /* * OpenBSD DLT_PFLOG; DLT_PFLOG is 17 in OpenBSD, but that's DLT_LANE8023 @@ -299,33 +299,33 @@ struct bpf_version { * XXX: is there a conflict with DLT_PFSYNC 18 as well? */ #ifdef __OpenBSD__ -#define DLT_OLD_PFLOG 17 -#define DLT_PFSYNC 18 +#define DLT_OLD_PFLOG 17 +#define DLT_PFSYNC 18 #endif -#define DLT_PFLOG 117 +#define DLT_PFLOG 117 /* * Registered for Cisco-internal use. */ -#define DLT_CISCO_IOS 118 +#define DLT_CISCO_IOS 118 /* * For 802.11 cards using the Prism II chips, with a link-layer * header including Prism monitor mode information plus an 802.11 * header. */ -#define DLT_PRISM_HEADER 119 +#define DLT_PRISM_HEADER 119 /* * Reserved for Aironet 802.11 cards, with an Aironet link-layer header * (see Doug Ambrisko's FreeBSD patches). */ -#define DLT_AIRONET_HEADER 120 +#define DLT_AIRONET_HEADER 120 /* * Reserved for Siemens HiPath HDLC. */ -#define DLT_HHDLC 121 +#define DLT_HHDLC 121 /* * This is for RFC 2625 IP-over-Fibre Channel. @@ -335,7 +335,7 @@ struct bpf_version { * where the link-layer header starts with an RFC 2625 Network_Header * field. */ -#define DLT_IP_OVER_FC 122 +#define DLT_IP_OVER_FC 122 /* * This is for Full Frontal ATM on Solaris with SunATM, with a @@ -351,9 +351,9 @@ struct bpf_version { * and the like don't have to infer the presence or absence of a * pseudo-header and the form of the pseudo-header. */ -#define DLT_SUNATM 123 /* Solaris+SunATM */ +#define DLT_SUNATM 123 /* Solaris+SunATM */ -/* +/* * Reserved as per request from Kent Dahlgren * for private use. */ @@ -366,7 +366,7 @@ struct bpf_version { * including radio information, used by some recent BSD drivers as * well as the madwifi Atheros driver for Linux. */ -#define DLT_IEEE802_11_RADIO 127 /* 802.11 plus radiotap radio header */ +#define DLT_IEEE802_11_RADIO 127 /* 802.11 plus radiotap radio header */ /* * Reserved for the TZSP encapsulation, as per request from @@ -389,7 +389,7 @@ struct bpf_version { * * We therefore have to have separate DLT_ values for them. */ -#define DLT_ARCNET_LINUX 129 /* ARCNET */ +#define DLT_ARCNET_LINUX 129 /* ARCNET */ /* * Juniper-private data link types, as per request from @@ -411,31 +411,31 @@ struct bpf_version { * . The header that's presented is an Ethernet-like * header: * - * #define FIREWIRE_EUI64_LEN 8 - * struct firewire_header { - * u_char firewire_dhost[FIREWIRE_EUI64_LEN]; - * u_char firewire_shost[FIREWIRE_EUI64_LEN]; - * u_short firewire_type; - * }; + * #define FIREWIRE_EUI64_LEN 8 + * struct firewire_header { + * u_char firewire_dhost[FIREWIRE_EUI64_LEN]; + * u_char firewire_shost[FIREWIRE_EUI64_LEN]; + * u_short firewire_type; + * }; * * with "firewire_type" being an Ethernet type value, rather than, * for example, raw GASP frames being handed up. */ -#define DLT_APPLE_IP_OVER_IEEE1394 138 +#define DLT_APPLE_IP_OVER_IEEE1394 138 /* * Various SS7 encapsulations, as per a request from Jeff Morriss * and subsequent discussions. */ -#define DLT_MTP2_WITH_PHDR 139 /* pseudo-header with various info, followed by MTP2 */ -#define DLT_MTP2 140 /* MTP2, without pseudo-header */ -#define DLT_MTP3 141 /* MTP3, without pseudo-header or MTP2 */ -#define DLT_SCCP 142 /* SCCP, without pseudo-header or MTP2 or MTP3 */ +#define DLT_MTP2_WITH_PHDR 139 /* pseudo-header with various info, followed by MTP2 */ +#define DLT_MTP2 140 /* MTP2, without pseudo-header */ +#define DLT_MTP3 141 /* MTP3, without pseudo-header or MTP2 */ +#define DLT_SCCP 142 /* SCCP, without pseudo-header or MTP2 or MTP3 */ /* * DOCSIS MAC frames. */ -#define DLT_DOCSIS 143 +#define DLT_DOCSIS 143 /* * Linux-IrDA packets. Protocol defined at http://www.irda.org. @@ -452,13 +452,13 @@ struct bpf_version { * issue and define a real DLT_IRDA... * Jean II */ -#define DLT_LINUX_IRDA 144 +#define DLT_LINUX_IRDA 144 /* * Reserved for IBM SP switch and IBM Next Federation switch. */ -#define DLT_IBM_SP 145 -#define DLT_IBM_SN 146 +#define DLT_IBM_SP 145 +#define DLT_IBM_SN 146 /* * Reserved for private use. If you have some link-layer header type @@ -485,34 +485,34 @@ struct bpf_version { * Instead, ask "tcpdump-workers@lists.tcpdump.org" for a new DLT_ value, * as per the comment above, and use the type you're given. */ -#define DLT_USER0 147 -#define DLT_USER1 148 -#define DLT_USER2 149 -#define DLT_USER3 150 -#define DLT_USER4 151 -#define DLT_USER5 152 -#define DLT_USER6 153 -#define DLT_USER7 154 -#define DLT_USER8 155 -#define DLT_USER9 156 -#define DLT_USER10 157 -#define DLT_USER11 158 -#define DLT_USER12 159 -#define DLT_USER13 160 -#define DLT_USER14 161 -#define DLT_USER15 162 +#define DLT_USER0 147 +#define DLT_USER1 148 +#define DLT_USER2 149 +#define DLT_USER3 150 +#define DLT_USER4 151 +#define DLT_USER5 152 +#define DLT_USER6 153 +#define DLT_USER7 154 +#define DLT_USER8 155 +#define DLT_USER9 156 +#define DLT_USER10 157 +#define DLT_USER11 158 +#define DLT_USER12 159 +#define DLT_USER13 160 +#define DLT_USER14 161 +#define DLT_USER15 162 /* * For future use with 802.11 captures - defined by AbsoluteValue * Systems to store a number of bits of link-layer information * including radio information: * - * http://www.shaftnet.org/~pizza/software/capturefrm.txt + * http://www.shaftnet.org/~pizza/software/capturefrm.txt * * but it might be used by some non-AVS drivers now or in the * future. */ -#define DLT_IEEE802_11_RADIO_AVS 163 /* 802.11 plus AVS radio header */ +#define DLT_IEEE802_11_RADIO_AVS 163 /* 802.11 plus AVS radio header */ /* * Juniper-private data link type, as per request from @@ -525,7 +525,7 @@ struct bpf_version { /* * Reserved for BACnet MS/TP. */ -#define DLT_BACNET_MS_TP 165 +#define DLT_BACNET_MS_TP 165 /* * Another PPP variant as per request from Karsten Keil . @@ -541,14 +541,14 @@ struct bpf_version { * The first byte of the PPP header (0xff03) is modified to accomodate * the direction - 0x00 = IN, 0x01 = OUT. */ -#define DLT_PPP_PPPD 166 +#define DLT_PPP_PPPD 166 /* * Names for backwards compatibility with older versions of some PPP * software; new software should use DLT_PPP_PPPD. */ -#define DLT_PPP_WITH_DIRECTION DLT_PPP_PPPD -#define DLT_LINUX_PPP_WITHDIRECTION DLT_PPP_PPPD +#define DLT_PPP_WITH_DIRECTION DLT_PPP_PPPD +#define DLT_LINUX_PPP_WITHDIRECTION DLT_PPP_PPPD /* * Juniper-private data link type, as per request from @@ -559,16 +559,16 @@ struct bpf_version { #define DLT_JUNIPER_PPPOE 167 #define DLT_JUNIPER_PPPOE_ATM 168 -#define DLT_GPRS_LLC 169 /* GPRS LLC */ -#define DLT_GPF_T 170 /* GPF-T (ITU-T G.7041/Y.1303) */ -#define DLT_GPF_F 171 /* GPF-F (ITU-T G.7041/Y.1303) */ +#define DLT_GPRS_LLC 169 /* GPRS LLC */ +#define DLT_GPF_T 170 /* GPF-T (ITU-T G.7041/Y.1303) */ +#define DLT_GPF_F 171 /* GPF-F (ITU-T G.7041/Y.1303) */ /* * Requested by Oolan Zimmer for use in Gcom's T1/E1 line * monitoring equipment. */ -#define DLT_GCOM_T1E1 172 -#define DLT_GCOM_SERIAL 173 +#define DLT_GCOM_T1E1 172 +#define DLT_GCOM_SERIAL 173 /* * Juniper-private data link type, as per request from @@ -583,8 +583,8 @@ struct bpf_version { * http://www.endace.com/support/EndaceRecordFormat.pdf) in front of * the link-layer header. */ -#define DLT_ERF_ETH 175 /* Ethernet */ -#define DLT_ERF_POS 176 /* Packet-over-SONET */ +#define DLT_ERF_ETH 175 /* Ethernet */ +#define DLT_ERF_POS 176 /* Packet-over-SONET */ /* * Requested by Daniele Orlandi for raw LAPD @@ -592,11 +592,11 @@ struct bpf_version { * includes additional information before the LAPD header, so it's * not necessarily a generic LAPD header. */ -#define DLT_LINUX_LAPD 177 +#define DLT_LINUX_LAPD 177 /* * Juniper-private data link type, as per request from - * Hannes Gredler . + * Hannes Gredler . * The DLT_ are used for prepending meta-information * like interface index, interface name * before standard Ethernet, PPP, Frelay & C-HDLC Frames @@ -613,7 +613,7 @@ struct bpf_version { /* * Juniper-private data link type, as per request from - * Hannes Gredler . + * Hannes Gredler . * The DLT_ is used for internal communication with a * voice Adapter Card (PIC) */ @@ -639,25 +639,25 @@ struct bpf_version { * USB packets, beginning with a USB setup header; requested by * Paolo Abeni . */ -#define DLT_USB 186 +#define DLT_USB 186 /* * Bluetooth HCI UART transport layer (part H:4); requested by * Paolo Abeni. */ -#define DLT_BLUETOOTH_HCI_H4 187 +#define DLT_BLUETOOTH_HCI_H4 187 /* * IEEE 802.16 MAC Common Part Sublayer; requested by Maria Cruz * . */ -#define DLT_IEEE802_16_MAC_CPS 188 +#define DLT_IEEE802_16_MAC_CPS 188 /* * USB packets, beginning with a Linux USB header; requested by * Paolo Abeni . */ -#define DLT_USB_LINUX 189 +#define DLT_USB_LINUX 189 /* * Controller Area Network (CAN) v. 2.0B packets. @@ -672,23 +672,23 @@ struct bpf_version { * IEEE 802.15.4, with address fields padded, as is done by Linux * drivers; requested by Juergen Schimmer. */ -#define DLT_IEEE802_15_4_LINUX 191 +#define DLT_IEEE802_15_4_LINUX 191 /* * Per Packet Information encapsulated packets. * DLT_ requested by Gianluca Varenni . */ -#define DLT_PPI 192 +#define DLT_PPI 192 /* * Header for 802.16 MAC Common Part Sublayer plus a radiotap radio header; * requested by Charles Clancy. */ -#define DLT_IEEE802_16_MAC_CPS_RADIO 193 +#define DLT_IEEE802_16_MAC_CPS_RADIO 193 /* * Juniper-private data link type, as per request from - * Hannes Gredler . + * Hannes Gredler . * The DLT_ is used for internal communication with a * integrated service module (ISM). */ @@ -698,38 +698,38 @@ struct bpf_version { * IEEE 802.15.4, exactly as it appears in the spec (no padding, no * nothing); requested by Mikko Saarnivala . */ -#define DLT_IEEE802_15_4 195 +#define DLT_IEEE802_15_4 195 /* * Various link-layer types, with a pseudo-header, for SITA * (http://www.sita.aero/); requested by Fulko Hew (fulko.hew@gmail.com). */ -#define DLT_SITA 196 +#define DLT_SITA 196 /* * Various link-layer types, with a pseudo-header, for Endace DAG cards; * encapsulates Endace ERF records. Requested by Stephen Donnelly * . */ -#define DLT_ERF 197 +#define DLT_ERF 197 /* * Special header prepended to Ethernet packets when capturing from a * u10 Networks board. Requested by Phil Mulholland * . */ -#define DLT_RAIF1 198 +#define DLT_RAIF1 198 /* * IPMB packet for IPMI, beginning with the I2C slave address, followed * by the netFn and LUN, etc.. Requested by Chanthy Toeung * . */ -#define DLT_IPMB 199 +#define DLT_IPMB 199 /* * Juniper-private data link type, as per request from - * Hannes Gredler . + * Hannes Gredler . * The DLT_ is used for capturing data on a secure tunnel interface. */ #define DLT_JUNIPER_ST 200 @@ -738,23 +738,23 @@ struct bpf_version { * Bluetooth HCI UART transport layer (part H:4), with pseudo-header * that includes direction information; requested by Paolo Abeni. */ -#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR 201 +#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR 201 /* * AX.25 packet with a 1-byte KISS header; see * - * http://www.ax25.net/kiss.htm + * http://www.ax25.net/kiss.htm * * as per Richard Stearn . */ -#define DLT_AX25_KISS 202 +#define DLT_AX25_KISS 202 /* * LAPD packets from an ISDN channel, starting with the address field, * with no pseudo-header. * Requested by Varuna De Silva . */ -#define DLT_LAPD 203 +#define DLT_LAPD 203 /* * Variants of various link-layer headers, with a one-byte direction @@ -762,10 +762,10 @@ struct bpf_version { * non-zero (any non-zero value) means "sent by this host" - as per * Will Barker . */ -#define DLT_PPP_WITH_DIR 204 /* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */ -#define DLT_C_HDLC_WITH_DIR 205 /* Cisco HDLC */ -#define DLT_FRELAY_WITH_DIR 206 /* Frame Relay */ -#define DLT_LAPB_WITH_DIR 207 /* LAPB */ +#define DLT_PPP_WITH_DIR 204 /* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */ +#define DLT_C_HDLC_WITH_DIR 205 /* Cisco HDLC */ +#define DLT_FRELAY_WITH_DIR 206 /* Frame Relay */ +#define DLT_LAPB_WITH_DIR 207 /* LAPB */ /* * 208 is reserved for an as-yet-unspecified proprietary link-layer @@ -776,39 +776,39 @@ struct bpf_version { * IPMB with a Linux-specific pseudo-header; as requested by Alexey Neyman * . */ -#define DLT_IPMB_LINUX 209 +#define DLT_IPMB_LINUX 209 /* * FlexRay automotive bus - http://www.flexray.com/ - as requested * by Hannes Kaelber . */ -#define DLT_FLEXRAY 210 +#define DLT_FLEXRAY 210 /* * Media Oriented Systems Transport (MOST) bus for multimedia * transport - http://www.mostcooperation.com/ - as requested * by Hannes Kaelber . */ -#define DLT_MOST 211 +#define DLT_MOST 211 /* * Local Interconnect Network (LIN) bus for vehicle networks - * http://www.lin-subbus.org/ - as requested by Hannes Kaelber * . */ -#define DLT_LIN 212 +#define DLT_LIN 212 /* * X2E-private data link type used for serial line capture, * as requested by Hannes Kaelber . */ -#define DLT_X2E_SERIAL 213 +#define DLT_X2E_SERIAL 213 /* * X2E-private data link type used for the Xoraya data logger * family, as requested by Hannes Kaelber . */ -#define DLT_X2E_XORAYA 214 +#define DLT_X2E_XORAYA 214 /* * IEEE 802.15.4, exactly as it appears in the spec (no padding, no @@ -819,7 +819,7 @@ struct bpf_version { * * Requested by Max Filippov . */ -#define DLT_IEEE802_15_4_NONASK_PHY 215 +#define DLT_IEEE802_15_4_NONASK_PHY 215 /* @@ -827,7 +827,7 @@ struct bpf_version { * a member of that class. A class value of 0 indicates a regular * DLT_/LINKTYPE_ value. */ -#define DLT_CLASS(x) ((x) & 0x03ff0000) +#define DLT_CLASS(x) ((x) & 0x03ff0000) /* * NetBSD-specific generic "raw" link type. The class value indicates @@ -836,10 +836,10 @@ struct bpf_version { * do not assume that they correspond to AF_ values for your operating * system. */ -#define DLT_CLASS_NETBSD_RAWAF 0x02240000 -#define DLT_NETBSD_RAWAF(af) (DLT_CLASS_NETBSD_RAWAF | (af)) -#define DLT_NETBSD_RAWAF_AF(x) ((x) & 0x0000ffff) -#define DLT_IS_NETBSD_RAWAF(x) (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF) +#define DLT_CLASS_NETBSD_RAWAF 0x02240000 +#define DLT_NETBSD_RAWAF(af) (DLT_CLASS_NETBSD_RAWAF | (af)) +#define DLT_NETBSD_RAWAF_AF(x) ((x) & 0x0000ffff) +#define DLT_IS_NETBSD_RAWAF(x) (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF) /* @@ -847,65 +847,65 @@ struct bpf_version { */ /* instruction classes */ #define BPF_CLASS(code) ((code) & 0x07) -#define BPF_LD 0x00 -#define BPF_LDX 0x01 -#define BPF_ST 0x02 -#define BPF_STX 0x03 -#define BPF_ALU 0x04 -#define BPF_JMP 0x05 -#define BPF_RET 0x06 -#define BPF_MISC 0x07 +#define BPF_LD 0x00 +#define BPF_LDX 0x01 +#define BPF_ST 0x02 +#define BPF_STX 0x03 +#define BPF_ALU 0x04 +#define BPF_JMP 0x05 +#define BPF_RET 0x06 +#define BPF_MISC 0x07 /* ld/ldx fields */ -#define BPF_SIZE(code) ((code) & 0x18) -#define BPF_W 0x00 -#define BPF_H 0x08 -#define BPF_B 0x10 -#define BPF_MODE(code) ((code) & 0xe0) -#define BPF_IMM 0x00 -#define BPF_ABS 0x20 -#define BPF_IND 0x40 -#define BPF_MEM 0x60 -#define BPF_LEN 0x80 -#define BPF_MSH 0xa0 +#define BPF_SIZE(code) ((code) & 0x18) +#define BPF_W 0x00 +#define BPF_H 0x08 +#define BPF_B 0x10 +#define BPF_MODE(code) ((code) & 0xe0) +#define BPF_IMM 0x00 +#define BPF_ABS 0x20 +#define BPF_IND 0x40 +#define BPF_MEM 0x60 +#define BPF_LEN 0x80 +#define BPF_MSH 0xa0 /* alu/jmp fields */ -#define BPF_OP(code) ((code) & 0xf0) -#define BPF_ADD 0x00 -#define BPF_SUB 0x10 -#define BPF_MUL 0x20 -#define BPF_DIV 0x30 -#define BPF_OR 0x40 -#define BPF_AND 0x50 -#define BPF_LSH 0x60 -#define BPF_RSH 0x70 -#define BPF_NEG 0x80 -#define BPF_JA 0x00 -#define BPF_JEQ 0x10 -#define BPF_JGT 0x20 -#define BPF_JGE 0x30 -#define BPF_JSET 0x40 -#define BPF_SRC(code) ((code) & 0x08) -#define BPF_K 0x00 -#define BPF_X 0x08 +#define BPF_OP(code) ((code) & 0xf0) +#define BPF_ADD 0x00 +#define BPF_SUB 0x10 +#define BPF_MUL 0x20 +#define BPF_DIV 0x30 +#define BPF_OR 0x40 +#define BPF_AND 0x50 +#define BPF_LSH 0x60 +#define BPF_RSH 0x70 +#define BPF_NEG 0x80 +#define BPF_JA 0x00 +#define BPF_JEQ 0x10 +#define BPF_JGT 0x20 +#define BPF_JGE 0x30 +#define BPF_JSET 0x40 +#define BPF_SRC(code) ((code) & 0x08) +#define BPF_K 0x00 +#define BPF_X 0x08 /* ret - BPF_K and BPF_X also apply */ -#define BPF_RVAL(code) ((code) & 0x18) -#define BPF_A 0x10 +#define BPF_RVAL(code) ((code) & 0x18) +#define BPF_A 0x10 /* misc */ #define BPF_MISCOP(code) ((code) & 0xf8) -#define BPF_TAX 0x00 -#define BPF_TXA 0x80 +#define BPF_TAX 0x00 +#define BPF_TXA 0x80 /* * The instruction data structure. */ struct bpf_insn { - u_short code; - u_char jt; - u_char jf; - bpf_u_int32 k; + u_short code; + u_char jt; + u_char jf; + bpf_u_int32 k; }; /* diff --git a/bsp/simulator/pcap/Include/pcap/namedb.h b/bsp/simulator/pcap/Include/pcap/namedb.h index 9002c75093..a74c85a421 100644 --- a/bsp/simulator/pcap/Include/pcap/namedb.h +++ b/bsp/simulator/pcap/Include/pcap/namedb.h @@ -1,6 +1,6 @@ /* * Copyright (c) 1994, 1996 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -12,8 +12,8 @@ * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. * 4. Neither the name of the University nor of the Laboratory may be used * to endorse or promote products derived from this software without * specific prior written permission. @@ -48,13 +48,13 @@ extern "C" { * export these hooks since they'll */ struct pcap_etherent { - u_char addr[6]; - char name[122]; + u_char addr[6]; + char name[122]; }; #ifndef PCAP_ETHERS_FILE #define PCAP_ETHERS_FILE "/etc/ethers" #endif -struct pcap_etherent *pcap_next_etherent(FILE *); +struct pcap_etherent *pcap_next_etherent(FILE *); u_char *pcap_ether_hostton(const char*); u_char *pcap_ether_aton(const char *); @@ -64,23 +64,23 @@ struct addrinfo *pcap_nametoaddrinfo(const char *); #endif bpf_u_int32 pcap_nametonetaddr(const char *); -int pcap_nametoport(const char *, int *, int *); -int pcap_nametoportrange(const char *, int *, int *, int *); -int pcap_nametoproto(const char *); -int pcap_nametoeproto(const char *); -int pcap_nametollc(const char *); +int pcap_nametoport(const char *, int *, int *); +int pcap_nametoportrange(const char *, int *, int *, int *); +int pcap_nametoproto(const char *); +int pcap_nametoeproto(const char *); +int pcap_nametollc(const char *); /* * If a protocol is unknown, PROTO_UNDEF is returned. * Also, pcap_nametoport() returns the protocol along with the port number. * If there are ambiguous entried in /etc/services (i.e. domain * can be either tcp or udp) PROTO_UNDEF is returned. */ -#define PROTO_UNDEF -1 +#define PROTO_UNDEF -1 /* XXX move these to pcap-int.h? */ int __pcap_atodn(const char *, bpf_u_int32 *); int __pcap_atoin(const char *, bpf_u_int32 *); -u_short __pcap_nametodnaddr(const char *); +u_short __pcap_nametodnaddr(const char *); #ifdef __cplusplus } diff --git a/bsp/simulator/pcap/Include/pcap/pcap.h b/bsp/simulator/pcap/Include/pcap/pcap.h index ad8fc40ac1..f01ea49993 100644 --- a/bsp/simulator/pcap/Include/pcap/pcap.h +++ b/bsp/simulator/pcap/Include/pcap/pcap.h @@ -1,7 +1,7 @@ /* -*- Mode: c; tab-width: 8; indent-tabs-mode: 1; c-basic-offset: 8; -*- */ /* * Copyright (c) 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -13,8 +13,8 @@ * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: - * This product includes software developed by the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory. + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. * 4. Neither the name of the University nor of the Laboratory may be used * to endorse or promote products derived from this software without * specific prior written permission. @@ -54,16 +54,16 @@ #include #ifdef HAVE_REMOTE - // We have to define the SOCKET here, although it has been defined in sockutils.h - // This is to avoid the distribution of the 'sockutils.h' file around - // (for example in the WinPcap developer's pack) - #ifndef SOCKET - #ifdef WIN32 - #define SOCKET unsigned int - #else - #define SOCKET int - #endif - #endif + // We have to define the SOCKET here, although it has been defined in sockutils.h + // This is to avoid the distribution of the 'sockutils.h' file around + // (for example in the WinPcap developer's pack) + #ifndef SOCKET + #ifdef WIN32 + #define SOCKET unsigned int + #else + #define SOCKET int + #endif + #endif #endif #ifdef __cplusplus @@ -80,8 +80,8 @@ extern "C" { * predates the bpf typedefs for 64-bit support. */ #if BPF_RELEASE - 0 < 199406 -typedef int bpf_int32; -typedef u_int bpf_u_int32; +typedef int bpf_int32; +typedef u_int bpf_u_int32; #endif typedef struct pcap pcap_t; @@ -105,46 +105,46 @@ typedef struct pcap_addr pcap_addr_t; * * Instead: * - * introduce a new structure for the new format, if the layout - * of the structure changed; + * introduce a new structure for the new format, if the layout + * of the structure changed; * - * send mail to "tcpdump-workers@lists.tcpdump.org", requesting - * a new magic number for your new capture file format, and, when - * you get the new magic number, put it in "savefile.c"; + * send mail to "tcpdump-workers@lists.tcpdump.org", requesting + * a new magic number for your new capture file format, and, when + * you get the new magic number, put it in "savefile.c"; * - * use that magic number for save files with the changed file - * header; + * use that magic number for save files with the changed file + * header; * - * make the code in "savefile.c" capable of reading files with - * the old file header as well as files with the new file header - * (using the magic number to determine the header format). + * make the code in "savefile.c" capable of reading files with + * the old file header as well as files with the new file header + * (using the magic number to determine the header format). * * Then supply the changes as a patch at * - * http://sourceforge.net/projects/libpcap/ + * http://sourceforge.net/projects/libpcap/ * * so that future versions of libpcap and programs that use it (such as * tcpdump) will be able to read your new capture file format. */ struct pcap_file_header { - bpf_u_int32 magic; - u_short version_major; - u_short version_minor; - bpf_int32 thiszone; /* gmt to local correction */ - bpf_u_int32 sigfigs; /* accuracy of timestamps */ - bpf_u_int32 snaplen; /* max length saved portion of each pkt */ - bpf_u_int32 linktype; /* data link type (LINKTYPE_*) */ + bpf_u_int32 magic; + u_short version_major; + u_short version_minor; + bpf_int32 thiszone; /* gmt to local correction */ + bpf_u_int32 sigfigs; /* accuracy of timestamps */ + bpf_u_int32 snaplen; /* max length saved portion of each pkt */ + bpf_u_int32 linktype; /* data link type (LINKTYPE_*) */ }; /* * Macros for the value returned by pcap_datalink_ext(). - * + * * If LT_FCS_LENGTH_PRESENT(x) is true, the LT_FCS_LENGTH(x) macro * gives the FCS length of packets in the capture. */ -#define LT_FCS_LENGTH_PRESENT(x) ((x) & 0x04000000) -#define LT_FCS_LENGTH(x) (((x) & 0xF0000000) >> 28) -#define LT_FCS_DATALINK_EXT(x) ((((x) & 0xF) << 28) | 0x04000000) +#define LT_FCS_LENGTH_PRESENT(x) ((x) & 0x04000000) +#define LT_FCS_LENGTH(x) (((x) & 0xF0000000) >> 28) +#define LT_FCS_DATALINK_EXT(x) ((((x) & 0xF) << 28) | 0x04000000) typedef enum { PCAP_D_INOUT = 0, @@ -165,22 +165,22 @@ typedef enum { * that's not what the underlying packet capture mechanism supplies. */ struct pcap_pkthdr { - struct timeval ts; /* time stamp */ - bpf_u_int32 caplen; /* length of portion present */ - bpf_u_int32 len; /* length this packet (off wire) */ + struct timeval ts; /* time stamp */ + bpf_u_int32 caplen; /* length of portion present */ + bpf_u_int32 len; /* length this packet (off wire) */ }; /* * As returned by the pcap_stats() */ struct pcap_stat { - u_int ps_recv; /* number of packets received */ - u_int ps_drop; /* number of packets dropped */ - u_int ps_ifdrop; /* drops by interface XXX not yet supported */ + u_int ps_recv; /* number of packets received */ + u_int ps_drop; /* number of packets dropped */ + u_int ps_ifdrop; /* drops by interface XXX not yet supported */ #ifdef HAVE_REMOTE - u_int ps_capt; /* number of packets that are received by the application; please get rid off the Win32 ifdef */ - u_int ps_sent; /* number of packets sent by the server on the network */ - u_int ps_netdrop; /* number of packets lost on the network */ + u_int ps_capt; /* number of packets that are received by the application; please get rid off the Win32 ifdef */ + u_int ps_sent; /* number of packets sent by the server on the network */ + u_int ps_netdrop; /* number of packets lost on the network */ #endif /* HAVE_REMOTE */ }; @@ -221,28 +221,28 @@ struct pcap_stat_ex { * Item in a list of interfaces. */ struct pcap_if { - struct pcap_if *next; - char *name; /* name to hand to "pcap_open_live()" */ - char *description; /* textual description of interface, or NULL */ - struct pcap_addr *addresses; - bpf_u_int32 flags; /* PCAP_IF_ interface flags */ + struct pcap_if *next; + char *name; /* name to hand to "pcap_open_live()" */ + char *description; /* textual description of interface, or NULL */ + struct pcap_addr *addresses; + bpf_u_int32 flags; /* PCAP_IF_ interface flags */ }; -#define PCAP_IF_LOOPBACK 0x00000001 /* interface is loopback */ +#define PCAP_IF_LOOPBACK 0x00000001 /* interface is loopback */ /* * Representation of an interface address. */ struct pcap_addr { - struct pcap_addr *next; - struct sockaddr *addr; /* address */ - struct sockaddr *netmask; /* netmask for that address */ - struct sockaddr *broadaddr; /* broadcast address for that address */ - struct sockaddr *dstaddr; /* P2P destination address for that address */ + struct pcap_addr *next; + struct sockaddr *addr; /* address */ + struct sockaddr *netmask; /* netmask for that address */ + struct sockaddr *broadaddr; /* broadcast address for that address */ + struct sockaddr *dstaddr; /* P2P destination address for that address */ }; typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *, - const u_char *); + const u_char *); /* * Error codes for the pcap API. @@ -250,111 +250,111 @@ typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *, * failure of a call that returns these codes by checking for a * negative value. */ -#define PCAP_ERROR -1 /* generic error code */ -#define PCAP_ERROR_BREAK -2 /* loop terminated by pcap_breakloop */ -#define PCAP_ERROR_NOT_ACTIVATED -3 /* the capture needs to be activated */ -#define PCAP_ERROR_ACTIVATED -4 /* the operation can't be performed on already activated captures */ -#define PCAP_ERROR_NO_SUCH_DEVICE -5 /* no such device exists */ -#define PCAP_ERROR_RFMON_NOTSUP -6 /* this device doesn't support rfmon (monitor) mode */ -#define PCAP_ERROR_NOT_RFMON -7 /* operation supported only in monitor mode */ -#define PCAP_ERROR_PERM_DENIED -8 /* no permission to open the device */ -#define PCAP_ERROR_IFACE_NOT_UP -9 /* interface isn't up */ +#define PCAP_ERROR -1 /* generic error code */ +#define PCAP_ERROR_BREAK -2 /* loop terminated by pcap_breakloop */ +#define PCAP_ERROR_NOT_ACTIVATED -3 /* the capture needs to be activated */ +#define PCAP_ERROR_ACTIVATED -4 /* the operation can't be performed on already activated captures */ +#define PCAP_ERROR_NO_SUCH_DEVICE -5 /* no such device exists */ +#define PCAP_ERROR_RFMON_NOTSUP -6 /* this device doesn't support rfmon (monitor) mode */ +#define PCAP_ERROR_NOT_RFMON -7 /* operation supported only in monitor mode */ +#define PCAP_ERROR_PERM_DENIED -8 /* no permission to open the device */ +#define PCAP_ERROR_IFACE_NOT_UP -9 /* interface isn't up */ /* * Warning codes for the pcap API. * These will all be positive and non-zero, so they won't look like * errors. */ -#define PCAP_WARNING 1 /* generic warning code */ -#define PCAP_WARNING_PROMISC_NOTSUP 2 /* this device doesn't support promiscuous mode */ +#define PCAP_WARNING 1 /* generic warning code */ +#define PCAP_WARNING_PROMISC_NOTSUP 2 /* this device doesn't support promiscuous mode */ -char *pcap_lookupdev(char *); -int pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *); +char *pcap_lookupdev(char *); +int pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *); -pcap_t *pcap_create(const char *, char *); -int pcap_set_snaplen(pcap_t *, int); -int pcap_set_promisc(pcap_t *, int); -int pcap_can_set_rfmon(pcap_t *); -int pcap_set_rfmon(pcap_t *, int); -int pcap_set_timeout(pcap_t *, int); -int pcap_set_buffer_size(pcap_t *, int); -int pcap_activate(pcap_t *); +pcap_t *pcap_create(const char *, char *); +int pcap_set_snaplen(pcap_t *, int); +int pcap_set_promisc(pcap_t *, int); +int pcap_can_set_rfmon(pcap_t *); +int pcap_set_rfmon(pcap_t *, int); +int pcap_set_timeout(pcap_t *, int); +int pcap_set_buffer_size(pcap_t *, int); +int pcap_activate(pcap_t *); -pcap_t *pcap_open_live(const char *, int, int, int, char *); -pcap_t *pcap_open_dead(int, int); -pcap_t *pcap_open_offline(const char *, char *); +pcap_t *pcap_open_live(const char *, int, int, int, char *); +pcap_t *pcap_open_dead(int, int); +pcap_t *pcap_open_offline(const char *, char *); #if defined(WIN32) pcap_t *pcap_hopen_offline(intptr_t, char *); #if !defined(LIBPCAP_EXPORTS) #define pcap_fopen_offline(f,b) \ - pcap_hopen_offline(_get_osfhandle(_fileno(f)), b) + pcap_hopen_offline(_get_osfhandle(_fileno(f)), b) #else /*LIBPCAP_EXPORTS*/ static pcap_t *pcap_fopen_offline(FILE *, char *); #endif #else /*WIN32*/ -pcap_t *pcap_fopen_offline(FILE *, char *); +pcap_t *pcap_fopen_offline(FILE *, char *); #endif /*WIN32*/ -void pcap_close(pcap_t *); -int pcap_loop(pcap_t *, int, pcap_handler, u_char *); -int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *); +void pcap_close(pcap_t *); +int pcap_loop(pcap_t *, int, pcap_handler, u_char *); +int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *); const u_char* - pcap_next(pcap_t *, struct pcap_pkthdr *); -int pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **); -void pcap_breakloop(pcap_t *); -int pcap_stats(pcap_t *, struct pcap_stat *); -int pcap_setfilter(pcap_t *, struct bpf_program *); -int pcap_setdirection(pcap_t *, pcap_direction_t); -int pcap_getnonblock(pcap_t *, char *); -int pcap_setnonblock(pcap_t *, int, char *); -int pcap_inject(pcap_t *, const void *, size_t); -int pcap_sendpacket(pcap_t *, const u_char *, int); + pcap_next(pcap_t *, struct pcap_pkthdr *); +int pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **); +void pcap_breakloop(pcap_t *); +int pcap_stats(pcap_t *, struct pcap_stat *); +int pcap_setfilter(pcap_t *, struct bpf_program *); +int pcap_setdirection(pcap_t *, pcap_direction_t); +int pcap_getnonblock(pcap_t *, char *); +int pcap_setnonblock(pcap_t *, int, char *); +int pcap_inject(pcap_t *, const void *, size_t); +int pcap_sendpacket(pcap_t *, const u_char *, int); const char *pcap_statustostr(int); const char *pcap_strerror(int); -char *pcap_geterr(pcap_t *); -void pcap_perror(pcap_t *, char *); -int pcap_compile(pcap_t *, struct bpf_program *, const char *, int, - bpf_u_int32); -int pcap_compile_nopcap(int, int, struct bpf_program *, - const char *, int, bpf_u_int32); -void pcap_freecode(struct bpf_program *); -int pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *, - const u_char *); -int pcap_datalink(pcap_t *); -int pcap_datalink_ext(pcap_t *); -int pcap_list_datalinks(pcap_t *, int **); -int pcap_set_datalink(pcap_t *, int); -void pcap_free_datalinks(int *); -int pcap_datalink_name_to_val(const char *); +char *pcap_geterr(pcap_t *); +void pcap_perror(pcap_t *, char *); +int pcap_compile(pcap_t *, struct bpf_program *, const char *, int, + bpf_u_int32); +int pcap_compile_nopcap(int, int, struct bpf_program *, + const char *, int, bpf_u_int32); +void pcap_freecode(struct bpf_program *); +int pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *, + const u_char *); +int pcap_datalink(pcap_t *); +int pcap_datalink_ext(pcap_t *); +int pcap_list_datalinks(pcap_t *, int **); +int pcap_set_datalink(pcap_t *, int); +void pcap_free_datalinks(int *); +int pcap_datalink_name_to_val(const char *); const char *pcap_datalink_val_to_name(int); const char *pcap_datalink_val_to_description(int); -int pcap_snapshot(pcap_t *); -int pcap_is_swapped(pcap_t *); -int pcap_major_version(pcap_t *); -int pcap_minor_version(pcap_t *); +int pcap_snapshot(pcap_t *); +int pcap_is_swapped(pcap_t *); +int pcap_major_version(pcap_t *); +int pcap_minor_version(pcap_t *); /* XXX */ -FILE *pcap_file(pcap_t *); -int pcap_fileno(pcap_t *); +FILE *pcap_file(pcap_t *); +int pcap_fileno(pcap_t *); pcap_dumper_t *pcap_dump_open(pcap_t *, const char *); pcap_dumper_t *pcap_dump_fopen(pcap_t *, FILE *fp); -FILE *pcap_dump_file(pcap_dumper_t *); -long pcap_dump_ftell(pcap_dumper_t *); -int pcap_dump_flush(pcap_dumper_t *); -void pcap_dump_close(pcap_dumper_t *); -void pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *); +FILE *pcap_dump_file(pcap_dumper_t *); +long pcap_dump_ftell(pcap_dumper_t *); +int pcap_dump_flush(pcap_dumper_t *); +void pcap_dump_close(pcap_dumper_t *); +void pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *); -int pcap_findalldevs(pcap_if_t **, char *); -void pcap_freealldevs(pcap_if_t *); +int pcap_findalldevs(pcap_if_t **, char *); +void pcap_freealldevs(pcap_if_t *); const char *pcap_lib_version(void); /* XXX this guy lives in the bpf tree */ -u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); -int bpf_validate(const struct bpf_insn *f, int len); -char *bpf_image(const struct bpf_insn *, int); -void bpf_dump(const struct bpf_program *, int); +u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); +int bpf_validate(const struct bpf_insn *f, int len); +char *bpf_image(const struct bpf_insn *, int); +void bpf_dump(const struct bpf_program *, int); #if defined(WIN32) @@ -391,14 +391,14 @@ u_long pcap_mac_packets (void); * UN*X definitions */ -int pcap_get_selectable_fd(pcap_t *); +int pcap_get_selectable_fd(pcap_t *); #endif /* WIN32/MSDOS/UN*X */ #ifdef HAVE_REMOTE /* Includes most of the public stuff that is needed for the remote capture */ #include -#endif /* HAVE_REMOTE */ +#endif /* HAVE_REMOTE */ #ifdef __cplusplus } diff --git a/bsp/simulator/pcap/Include/pcap/sll.h b/bsp/simulator/pcap/Include/pcap/sll.h index e9d5452af7..20b816b2f2 100644 --- a/bsp/simulator/pcap/Include/pcap/sll.h +++ b/bsp/simulator/pcap/Include/pcap/sll.h @@ -1,6 +1,6 @@ /*- * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * This code is derived from the Stanford/CMU enet packet filter, * (net/enet.c) distributed as part of 4.3BSD, and code contributed @@ -42,22 +42,22 @@ * For captures on Linux cooked sockets, we construct a fake header * that includes: * - * a 2-byte "packet type" which is one of: + * a 2-byte "packet type" which is one of: * - * LINUX_SLL_HOST packet was sent to us - * LINUX_SLL_BROADCAST packet was broadcast - * LINUX_SLL_MULTICAST packet was multicast - * LINUX_SLL_OTHERHOST packet was sent to somebody else - * LINUX_SLL_OUTGOING packet was sent *by* us; + * LINUX_SLL_HOST packet was sent to us + * LINUX_SLL_BROADCAST packet was broadcast + * LINUX_SLL_MULTICAST packet was multicast + * LINUX_SLL_OTHERHOST packet was sent to somebody else + * LINUX_SLL_OUTGOING packet was sent *by* us; * - * a 2-byte Ethernet protocol field; + * a 2-byte Ethernet protocol field; * - * a 2-byte link-layer type; + * a 2-byte link-layer type; * - * a 2-byte link-layer address length; + * a 2-byte link-layer address length; * - * an 8-byte source link-layer address, whose actual length is - * specified by the previous value. + * an 8-byte source link-layer address, whose actual length is + * specified by the previous value. * * All fields except for the link-layer address are in network byte order. * @@ -79,15 +79,15 @@ /* * A DLT_LINUX_SLL fake link-layer header. */ -#define SLL_HDR_LEN 16 /* total header length */ -#define SLL_ADDRLEN 8 /* length of address field */ +#define SLL_HDR_LEN 16 /* total header length */ +#define SLL_ADDRLEN 8 /* length of address field */ struct sll_header { - u_int16_t sll_pkttype; /* packet type */ - u_int16_t sll_hatype; /* link-layer address type */ - u_int16_t sll_halen; /* link-layer address length */ - u_int8_t sll_addr[SLL_ADDRLEN]; /* link-layer address */ - u_int16_t sll_protocol; /* protocol */ + u_int16_t sll_pkttype; /* packet type */ + u_int16_t sll_hatype; /* link-layer address type */ + u_int16_t sll_halen; /* link-layer address length */ + u_int8_t sll_addr[SLL_ADDRLEN]; /* link-layer address */ + u_int16_t sll_protocol; /* protocol */ }; /* @@ -96,11 +96,11 @@ struct sll_header { * available even on systems other than Linux, and so that they * don't change even if the PACKET_ values change. */ -#define LINUX_SLL_HOST 0 -#define LINUX_SLL_BROADCAST 1 -#define LINUX_SLL_MULTICAST 2 -#define LINUX_SLL_OTHERHOST 3 -#define LINUX_SLL_OUTGOING 4 +#define LINUX_SLL_HOST 0 +#define LINUX_SLL_BROADCAST 1 +#define LINUX_SLL_MULTICAST 2 +#define LINUX_SLL_OTHERHOST 3 +#define LINUX_SLL_OUTGOING 4 /* * The LINUX_SLL_ values for "sll_protocol"; these correspond to the @@ -108,22 +108,22 @@ struct sll_header { * available even on systems other than Linux. We assume, for now, * that the ETH_P_ values won't change in Linux; if they do, then: * - * if we don't translate them in "pcap-linux.c", capture files - * won't necessarily be readable if captured on a system that - * defines ETH_P_ values that don't match these values; + * if we don't translate them in "pcap-linux.c", capture files + * won't necessarily be readable if captured on a system that + * defines ETH_P_ values that don't match these values; * - * if we do translate them in "pcap-linux.c", that makes life - * unpleasant for the BPF code generator, as the values you test - * for in the kernel aren't the values that you test for when - * reading a capture file, so the fixup code run on BPF programs - * handed to the kernel ends up having to do more work. + * if we do translate them in "pcap-linux.c", that makes life + * unpleasant for the BPF code generator, as the values you test + * for in the kernel aren't the values that you test for when + * reading a capture file, so the fixup code run on BPF programs + * handed to the kernel ends up having to do more work. * * Add other values here as necessary, for handling packet types that * might show up on non-Ethernet, non-802.x networks. (Not all the ones * in the Linux "if_ether.h" will, I suspect, actually show up in * captures.) */ -#define LINUX_SLL_P_802_3 0x0001 /* Novell 802.3 frames without 802.2 LLC header */ -#define LINUX_SLL_P_802_2 0x0004 /* 802.2 frames (not D/I/X Ethernet) */ +#define LINUX_SLL_P_802_3 0x0001 /* Novell 802.3 frames without 802.2 LLC header */ +#define LINUX_SLL_P_802_2 0x0004 /* 802.2 frames (not D/I/X Ethernet) */ #endif diff --git a/bsp/simulator/pcap/Include/pcap/usb.h b/bsp/simulator/pcap/Include/pcap/usb.h index adcd19c058..4837fe4ac1 100644 --- a/bsp/simulator/pcap/Include/pcap/usb.h +++ b/bsp/simulator/pcap/Include/pcap/usb.h @@ -11,8 +11,8 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior written + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS @@ -32,11 +32,11 @@ * * @(#) $Header: /tcpdump/master/libpcap/pcap/usb.h,v 1.6 2007/09/22 02:06:08 guy Exp $ */ - + #ifndef _PCAP_USB_STRUCTS_H__ #define _PCAP_USB_STRUCTS_H__ -/* +/* * possible transfer mode */ #define URB_TRANSFER_IN 0x80 @@ -57,11 +57,11 @@ * Appears at the front of each packet in DLT_USB captures. */ typedef struct _usb_setup { - u_int8_t bmRequestType; - u_int8_t bRequest; - u_int16_t wValue; - u_int16_t wIndex; - u_int16_t wLength; + u_int8_t bmRequestType; + u_int8_t bRequest; + u_int16_t wValue; + u_int16_t wIndex; + u_int16_t wLength; } pcap_usb_setup; @@ -70,20 +70,20 @@ typedef struct _usb_setup { * Appears at the front of each packet in DLT_USB_LINUX captures. */ typedef struct _usb_header { - u_int64_t id; - u_int8_t event_type; - u_int8_t transfer_type; - u_int8_t endpoint_number; - u_int8_t device_address; - u_int16_t bus_id; - char setup_flag;/*if !=0 the urb setup header is not present*/ - char data_flag; /*if !=0 no urb data is present*/ - int64_t ts_sec; - int32_t ts_usec; - int32_t status; - u_int32_t urb_len; - u_int32_t data_len; /* amount of urb data really present in this event*/ - pcap_usb_setup setup; + u_int64_t id; + u_int8_t event_type; + u_int8_t transfer_type; + u_int8_t endpoint_number; + u_int8_t device_address; + u_int16_t bus_id; + char setup_flag;/*if !=0 the urb setup header is not present*/ + char data_flag; /*if !=0 no urb data is present*/ + int64_t ts_sec; + int32_t ts_usec; + int32_t status; + u_int32_t urb_len; + u_int32_t data_len; /* amount of urb data really present in this event*/ + pcap_usb_setup setup; } pcap_usb_header; diff --git a/bsp/simulator/pcap/Include/pcap/vlan.h b/bsp/simulator/pcap/Include/pcap/vlan.h index b0cb7949be..b9fa284c35 100644 --- a/bsp/simulator/pcap/Include/pcap/vlan.h +++ b/bsp/simulator/pcap/Include/pcap/vlan.h @@ -1,6 +1,6 @@ /*- * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 - * The Regents of the University of California. All rights reserved. + * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -37,10 +37,10 @@ #define lib_pcap_vlan_h struct vlan_tag { - u_int16_t vlan_tpid; /* ETH_P_8021Q */ - u_int16_t vlan_tci; /* VLAN TCI */ + u_int16_t vlan_tpid; /* ETH_P_8021Q */ + u_int16_t vlan_tci; /* VLAN TCI */ }; -#define VLAN_TAG_LEN 4 +#define VLAN_TAG_LEN 4 #endif diff --git a/bsp/simulator/pcap/Include/remote-ext.h b/bsp/simulator/pcap/Include/remote-ext.h index 35a2fff6c2..34e4efba3a 100644 --- a/bsp/simulator/pcap/Include/remote-ext.h +++ b/bsp/simulator/pcap/Include/remote-ext.h @@ -2,32 +2,32 @@ * Copyright (c) 2002 - 2003 * NetGroup, Politecnico di Torino (Italy) * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions * are met: - * - * 1. Redistributions of source code must retain the above copyright + * + * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Politecnico di Torino nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ @@ -49,135 +49,135 @@ extern "C" { #endif /*! - \file remote-ext.h + \file remote-ext.h - The goal of this file it to include most of the new definitions that should be - placed into the pcap.h file. + The goal of this file it to include most of the new definitions that should be + placed into the pcap.h file. - It includes all new definitions (structures and functions like pcap_open(). - Some of the functions are not really a remote feature, but, right now, - they are placed here. + It includes all new definitions (structures and functions like pcap_open(). + Some of the functions are not really a remote feature, but, right now, + they are placed here. */ // All this stuff is public /*! \addtogroup remote_struct - \{ + \{ */ /*! - \brief Defines the maximum buffer size in which address, port, interface names are kept. + \brief Defines the maximum buffer size in which address, port, interface names are kept. - In case the adapter name or such is larger than this value, it is truncated. - This is not used by the user; however it must be aware that an hostname / interface - name longer than this value will be truncated. + In case the adapter name or such is larger than this value, it is truncated. + This is not used by the user; however it must be aware that an hostname / interface + name longer than this value will be truncated. */ #define PCAP_BUF_SIZE 1024 /*! \addtogroup remote_source_ID - \{ + \{ */ /*! - \brief Internal representation of the type of source in use (file, - remote/local interface). + \brief Internal representation of the type of source in use (file, + remote/local interface). - This indicates a file, i.e. the user want to open a capture from a local file. + This indicates a file, i.e. the user want to open a capture from a local file. */ #define PCAP_SRC_FILE 2 /*! - \brief Internal representation of the type of source in use (file, - remote/local interface). + \brief Internal representation of the type of source in use (file, + remote/local interface). - This indicates a local interface, i.e. the user want to open a capture from - a local interface. This does not involve the RPCAP protocol. + This indicates a local interface, i.e. the user want to open a capture from + a local interface. This does not involve the RPCAP protocol. */ #define PCAP_SRC_IFLOCAL 3 /*! - \brief Internal representation of the type of source in use (file, - remote/local interface). + \brief Internal representation of the type of source in use (file, + remote/local interface). - This indicates a remote interface, i.e. the user want to open a capture from - an interface on a remote host. This does involve the RPCAP protocol. + This indicates a remote interface, i.e. the user want to open a capture from + an interface on a remote host. This does involve the RPCAP protocol. */ #define PCAP_SRC_IFREMOTE 4 /*! - \} + \} */ /*! \addtogroup remote_source_string - The formats allowed by the pcap_open() are the following: - - file://path_and_filename [opens a local file] - - rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol] - - rpcap://host/devicename [opens the selected device available on a remote host] - - rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP] - - adaptername [to open a local adapter; kept for compability, but it is strongly discouraged] - - (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged] + The formats allowed by the pcap_open() are the following: + - file://path_and_filename [opens a local file] + - rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol] + - rpcap://host/devicename [opens the selected device available on a remote host] + - rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP] + - adaptername [to open a local adapter; kept for compability, but it is strongly discouraged] + - (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged] - The formats allowed by the pcap_findalldevs_ex() are the following: - - file://folder/ [lists all the files in the given folder] - - rpcap:// [lists all local adapters] - - rpcap://host:port/ [lists the devices available on a remote host] + The formats allowed by the pcap_findalldevs_ex() are the following: + - file://folder/ [lists all the files in the given folder] + - rpcap:// [lists all local adapters] + - rpcap://host:port/ [lists the devices available on a remote host] - Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since - IPv6 is fully supported, these are the allowed formats: + Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since + IPv6 is fully supported, these are the allowed formats: - - host (literal): e.g. host.foo.bar - - host (numeric IPv4): e.g. 10.11.12.13 - - host (numeric IPv4, IPv6 style): e.g. [10.11.12.13] - - host (numeric IPv6): e.g. [1:2:3::4] - - port: can be either numeric (e.g. '80') or literal (e.g. 'http') + - host (literal): e.g. host.foo.bar + - host (numeric IPv4): e.g. 10.11.12.13 + - host (numeric IPv4, IPv6 style): e.g. [10.11.12.13] + - host (numeric IPv6): e.g. [1:2:3::4] + - port: can be either numeric (e.g. '80') or literal (e.g. 'http') - Here you find some allowed examples: - - rpcap://host.foo.bar/devicename [everything literal, no port number] - - rpcap://host.foo.bar:1234/devicename [everything literal, with port number] - - rpcap://10.11.12.13/devicename [IPv4 numeric, no port number] - - rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number] - - rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number] - - rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number] - - rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number] - - rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number] - - \{ + Here you find some allowed examples: + - rpcap://host.foo.bar/devicename [everything literal, no port number] + - rpcap://host.foo.bar:1234/devicename [everything literal, with port number] + - rpcap://10.11.12.13/devicename [IPv4 numeric, no port number] + - rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number] + - rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number] + - rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number] + - rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number] + - rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number] + + \{ */ /*! - \brief String that will be used to determine the type of source in use (file, - remote/local interface). + \brief String that will be used to determine the type of source in use (file, + remote/local interface). - This string will be prepended to the interface name in order to create a string - that contains all the information required to open the source. + This string will be prepended to the interface name in order to create a string + that contains all the information required to open the source. - This string indicates that the user wants to open a capture from a local file. + This string indicates that the user wants to open a capture from a local file. */ #define PCAP_SRC_FILE_STRING "file://" /*! - \brief String that will be used to determine the type of source in use (file, - remote/local interface). + \brief String that will be used to determine the type of source in use (file, + remote/local interface). - This string will be prepended to the interface name in order to create a string - that contains all the information required to open the source. + This string will be prepended to the interface name in order to create a string + that contains all the information required to open the source. - This string indicates that the user wants to open a capture from a network interface. - This string does not necessarily involve the use of the RPCAP protocol. If the - interface required resides on the local host, the RPCAP protocol is not involved - and the local functions are used. + This string indicates that the user wants to open a capture from a network interface. + This string does not necessarily involve the use of the RPCAP protocol. If the + interface required resides on the local host, the RPCAP protocol is not involved + and the local functions are used. */ #define PCAP_SRC_IF_STRING "rpcap://" /*! - \} + \} */ @@ -185,137 +185,137 @@ extern "C" { /*! - \addtogroup remote_open_flags - \{ + \addtogroup remote_open_flags + \{ */ /*! - \brief Defines if the adapter has to go in promiscuous mode. + \brief Defines if the adapter has to go in promiscuous mode. - It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise. - Note that even if this parameter is false, the interface could well be in promiscuous - mode for some other reason (for example because another capture process with - promiscuous mode enabled is currently using that interface). - On on Linux systems with 2.2 or later kernels (that have the "any" device), this - flag does not work on the "any" device; if an argument of "any" is supplied, - the 'promisc' flag is ignored. + It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise. + Note that even if this parameter is false, the interface could well be in promiscuous + mode for some other reason (for example because another capture process with + promiscuous mode enabled is currently using that interface). + On on Linux systems with 2.2 or later kernels (that have the "any" device), this + flag does not work on the "any" device; if an argument of "any" is supplied, + the 'promisc' flag is ignored. */ -#define PCAP_OPENFLAG_PROMISCUOUS 1 +#define PCAP_OPENFLAG_PROMISCUOUS 1 /*! - \brief Defines if the data trasfer (in case of a remote - capture) has to be done with UDP protocol. + \brief Defines if the data trasfer (in case of a remote + capture) has to be done with UDP protocol. - If it is '1' if you want a UDP data connection, '0' if you want - a TCP data connection; control connection is always TCP-based. - A UDP connection is much lighter, but it does not guarantee that all - the captured packets arrive to the client workstation. Moreover, - it could be harmful in case of network congestion. - This flag is meaningless if the source is not a remote interface. - In that case, it is simply ignored. + If it is '1' if you want a UDP data connection, '0' if you want + a TCP data connection; control connection is always TCP-based. + A UDP connection is much lighter, but it does not guarantee that all + the captured packets arrive to the client workstation. Moreover, + it could be harmful in case of network congestion. + This flag is meaningless if the source is not a remote interface. + In that case, it is simply ignored. */ -#define PCAP_OPENFLAG_DATATX_UDP 2 +#define PCAP_OPENFLAG_DATATX_UDP 2 /*! - \brief Defines if the remote probe will capture its own generated traffic. + \brief Defines if the remote probe will capture its own generated traffic. - In case the remote probe uses the same interface to capture traffic and to send - data back to the caller, the captured traffic includes the RPCAP traffic as well. - If this flag is turned on, the RPCAP traffic is excluded from the capture, so that - the trace returned back to the collector is does not include this traffic. + In case the remote probe uses the same interface to capture traffic and to send + data back to the caller, the captured traffic includes the RPCAP traffic as well. + If this flag is turned on, the RPCAP traffic is excluded from the capture, so that + the trace returned back to the collector is does not include this traffic. */ -#define PCAP_OPENFLAG_NOCAPTURE_RPCAP 4 +#define PCAP_OPENFLAG_NOCAPTURE_RPCAP 4 /*! - \brief Defines if the local adapter will capture its own generated traffic. + \brief Defines if the local adapter will capture its own generated traffic. - This flag tells the underlying capture driver to drop the packets that were sent by itself. - This is usefult when building applications like bridges, that should ignore the traffic - they just sent. + This flag tells the underlying capture driver to drop the packets that were sent by itself. + This is usefult when building applications like bridges, that should ignore the traffic + they just sent. */ -#define PCAP_OPENFLAG_NOCAPTURE_LOCAL 8 +#define PCAP_OPENFLAG_NOCAPTURE_LOCAL 8 /*! - \brief This flag configures the adapter for maximum responsiveness. + \brief This flag configures the adapter for maximum responsiveness. - In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before - copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, - i.e. better performance, which is good for applications like sniffers. If the user sets the - PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application - is ready to receive them. This is suggested for real time applications (like, for example, a bridge) - that need the best responsiveness.*/ -#define PCAP_OPENFLAG_MAX_RESPONSIVENESS 16 + In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before + copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, + i.e. better performance, which is good for applications like sniffers. If the user sets the + PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application + is ready to receive them. This is suggested for real time applications (like, for example, a bridge) + that need the best responsiveness.*/ +#define PCAP_OPENFLAG_MAX_RESPONSIVENESS 16 /*! - \} + \} */ /*! - \addtogroup remote_samp_methods - \{ + \addtogroup remote_samp_methods + \{ */ /*! - \brief No sampling has to be done on the current capture. + \brief No sampling has to be done on the current capture. - In this case, no sampling algorithms are applied to the current capture. + In this case, no sampling algorithms are applied to the current capture. */ -#define PCAP_SAMP_NOSAMP 0 +#define PCAP_SAMP_NOSAMP 0 /*! - \brief It defines that only 1 out of N packets must be returned to the user. + \brief It defines that only 1 out of N packets must be returned to the user. - In this case, the 'value' field of the 'pcap_samp' structure indicates the - number of packets (minus 1) that must be discarded before one packet got accepted. - In other words, if 'value = 10', the first packet is returned to the caller, while - the following 9 are discarded. + In this case, the 'value' field of the 'pcap_samp' structure indicates the + number of packets (minus 1) that must be discarded before one packet got accepted. + In other words, if 'value = 10', the first packet is returned to the caller, while + the following 9 are discarded. */ -#define PCAP_SAMP_1_EVERY_N 1 +#define PCAP_SAMP_1_EVERY_N 1 /*! - \brief It defines that we have to return 1 packet every N milliseconds. + \brief It defines that we have to return 1 packet every N milliseconds. - In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting - time' in milliseconds before one packet got accepted. - In other words, if 'value = 10', the first packet is returned to the caller; the next - returned one will be the first packet that arrives when 10ms have elapsed. + In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting + time' in milliseconds before one packet got accepted. + In other words, if 'value = 10', the first packet is returned to the caller; the next + returned one will be the first packet that arrives when 10ms have elapsed. */ #define PCAP_SAMP_FIRST_AFTER_N_MS 2 /*! - \} + \} */ /*! - \addtogroup remote_auth_methods - \{ + \addtogroup remote_auth_methods + \{ */ /*! - \brief It defines the NULL authentication. + \brief It defines the NULL authentication. - This value has to be used within the 'type' member of the pcap_rmtauth structure. - The 'NULL' authentication has to be equal to 'zero', so that old applications - can just put every field of struct pcap_rmtauth to zero, and it does work. + This value has to be used within the 'type' member of the pcap_rmtauth structure. + The 'NULL' authentication has to be equal to 'zero', so that old applications + can just put every field of struct pcap_rmtauth to zero, and it does work. */ #define RPCAP_RMTAUTH_NULL 0 /*! - \brief It defines the username/password authentication. + \brief It defines the username/password authentication. - With this type of authentication, the RPCAP protocol will use the username/ - password provided to authenticate the user on the remote machine. If the - authentication is successful (and the user has the right to open network devices) - the RPCAP connection will continue; otherwise it will be dropped. + With this type of authentication, the RPCAP protocol will use the username/ + password provided to authenticate the user on the remote machine. If the + authentication is successful (and the user has the right to open network devices) + the RPCAP connection will continue; otherwise it will be dropped. - This value has to be used within the 'type' member of the pcap_rmtauth structure. + This value has to be used within the 'type' member of the pcap_rmtauth structure. */ #define RPCAP_RMTAUTH_PWD 1 /*! - \} + \} */ @@ -323,73 +323,73 @@ extern "C" { /*! - \brief This structure keeps the information needed to autheticate - the user on a remote machine. - - The remote machine can either grant or refuse the access according - to the information provided. - In case the NULL authentication is required, both 'username' and - 'password' can be NULL pointers. - - This structure is meaningless if the source is not a remote interface; - in that case, the functions which requires such a structure can accept - a NULL pointer as well. + \brief This structure keeps the information needed to autheticate + the user on a remote machine. + + The remote machine can either grant or refuse the access according + to the information provided. + In case the NULL authentication is required, both 'username' and + 'password' can be NULL pointers. + + This structure is meaningless if the source is not a remote interface; + in that case, the functions which requires such a structure can accept + a NULL pointer as well. */ struct pcap_rmtauth { - /*! - \brief Type of the authentication required. + /*! + \brief Type of the authentication required. - In order to provide maximum flexibility, we can support different types - of authentication based on the value of this 'type' variable. The currently - supported authentication methods are defined into the - \link remote_auth_methods Remote Authentication Methods Section\endlink. + In order to provide maximum flexibility, we can support different types + of authentication based on the value of this 'type' variable. The currently + supported authentication methods are defined into the + \link remote_auth_methods Remote Authentication Methods Section\endlink. - */ - int type; - /*! - \brief Zero-terminated string containing the username that has to be - used on the remote machine for authentication. - - This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication - and it can be NULL. - */ - char *username; - /*! - \brief Zero-terminated string containing the password that has to be - used on the remote machine for authentication. - - This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication - and it can be NULL. - */ - char *password; + */ + int type; + /*! + \brief Zero-terminated string containing the username that has to be + used on the remote machine for authentication. + + This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication + and it can be NULL. + */ + char *username; + /*! + \brief Zero-terminated string containing the password that has to be + used on the remote machine for authentication. + + This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication + and it can be NULL. + */ + char *password; }; /*! - \brief This structure defines the information related to sampling. + \brief This structure defines the information related to sampling. - In case the sampling is requested, the capturing device should read - only a subset of the packets coming from the source. The returned packets depend - on the sampling parameters. + In case the sampling is requested, the capturing device should read + only a subset of the packets coming from the source. The returned packets depend + on the sampling parameters. - \warning The sampling process is applied after the filtering process. - In other words, packets are filtered first, then the sampling process selects a - subset of the 'filtered' packets and it returns them to the caller. + \warning The sampling process is applied after the filtering process. + In other words, packets are filtered first, then the sampling process selects a + subset of the 'filtered' packets and it returns them to the caller. */ struct pcap_samp { - /*! - Method used for sampling. Currently, the supported methods are listed in the - \link remote_samp_methods Sampling Methods Section\endlink. - */ - int method; + /*! + Method used for sampling. Currently, the supported methods are listed in the + \link remote_samp_methods Sampling Methods Section\endlink. + */ + int method; - /*! - This value depends on the sampling method defined. For its meaning, please check - at the \link remote_samp_methods Sampling Methods Section\endlink. - */ - int value; + /*! + This value depends on the sampling method defined. For its meaning, please check + at the \link remote_samp_methods Sampling Methods Section\endlink. + */ + int value; }; @@ -400,7 +400,7 @@ struct pcap_samp /*! - \} + \} */ // end of public documentation @@ -410,8 +410,8 @@ struct pcap_samp /** \name New WinPcap functions - This section lists the new functions that are able to help considerably in writing - WinPcap programs because of their easiness of use. + This section lists the new functions that are able to help considerably in writing + WinPcap programs because of their easiness of use. */ //\{ pcap_t *pcap_open(const char *source, int snaplen, int flags, int read_timeout, struct pcap_rmtauth *auth, char *errbuf); @@ -427,7 +427,7 @@ struct pcap_samp *pcap_setsampling(pcap_t *p); /** \name Remote Capture functions */ -//\{ +//\{ SOCKET pcap_remoteact_accept(const char *address, const char *port, const char *hostlist, char *connectinghost, struct pcap_rmtauth *auth, char *errbuf); int pcap_remoteact_list(char *hostlist, char sep, int size, char *errbuf); int pcap_remoteact_close(const char *host, char *errbuf); diff --git a/bsp/simulator/pcap/pcap_netif.c b/bsp/simulator/pcap/pcap_netif.c index d6572c3045..0aef477185 100644 --- a/bsp/simulator/pcap/pcap_netif.c +++ b/bsp/simulator/pcap/pcap_netif.c @@ -1,11 +1,7 @@ /* - * File : pcap_netif.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -37,12 +33,12 @@ struct pcap_netif { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; pcap_t *tap; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct pcap_netif pcap_netif_device; static struct rt_semaphore sem_lock; @@ -61,7 +57,7 @@ static void pcap_thread_entry(void* parameter) /* Open the adapter */ if ((tap = pcap_open_live(netif->name, - 65536, // portion of the packet to capture. + 65536, // portion of the packet to capture. 1, // promiscuous mode (nonzero means promiscuous) 1, // read timeout, 0 blocked, -1 no timeout errbuf )) == NULL) @@ -88,7 +84,7 @@ static void pcap_thread_entry(void* parameter) p = pbuf_alloc(PBUF_LINK, header->len, PBUF_RAM); pbuf_take(p, pkt_data, header->len); - + /* send to packet mailbox */ rt_mb_send_wait(packet_mb, (rt_uint32_t)p, RT_WAITING_FOREVER); /* notify eth rx thread to receive packet */ @@ -134,7 +130,7 @@ static rt_err_t pcap_netif_init(rt_device_t dev) { rt_kprintf("Select (%s) as network interface\n", d->description); packet_mb = rt_mb_create("pcap", 64, RT_IPC_FLAG_FIFO); - tid = rt_thread_create("pcap", pcap_thread_entry, d, + tid = rt_thread_create("pcap", pcap_thread_entry, d, 2048, RT_THREAD_PRIORITY_MAX - 1, 10); if (tid != RT_NULL) { @@ -151,7 +147,7 @@ static rt_err_t pcap_netif_init(rt_device_t dev) static rt_err_t pcap_netif_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t pcap_netif_close(rt_device_t dev) @@ -161,42 +157,42 @@ static rt_err_t pcap_netif_close(rt_device_t dev) tap = NETIF_PCAP(dev); pcap_close(tap); - return RT_EOK; + return RT_EOK; } static rt_size_t pcap_netif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t pcap_netif_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t pcap_netif_control(rt_device_t dev, int cmd, void *args) { - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, pcap_netif_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) rt_memcpy(args, pcap_netif_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p) { - struct pbuf *q; - rt_uint8_t *ptr; + struct pbuf *q; + rt_uint8_t *ptr; rt_uint8_t buf[2048]; rt_err_t result = RT_EOK; pcap_t *tap; @@ -204,18 +200,18 @@ rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p) tap = NETIF_PCAP(dev); - /* lock EMAC device */ - rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + /* lock EMAC device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); - /* copy data to tx buffer */ - q = p; - ptr = (rt_uint8_t*)buf; - while (q) - { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } + /* copy data to tx buffer */ + q = p; + ptr = (rt_uint8_t*)buf; + while (q) + { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + q = q->next; + } rt_enter_critical(); res = pcap_sendpacket(tap, buf, p->tot_len); @@ -227,15 +223,15 @@ rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p) result = -RT_ERROR; } - /* unlock EMAC device */ - rt_sem_release(&sem_lock); + /* unlock EMAC device */ + rt_sem_release(&sem_lock); return result; } struct pbuf *pcap_netif_rx(rt_device_t dev) { - struct pbuf* p = RT_NULL; + struct pbuf* p = RT_NULL; rt_mb_recv(packet_mb, (rt_uint32_t*)&p, 0); @@ -244,28 +240,28 @@ struct pbuf *pcap_netif_rx(rt_device_t dev) void pcap_netif_hw_init(void) { - rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); - pcap_netif_device.dev_addr[0] = 0x00; - pcap_netif_device.dev_addr[1] = 0x60; - pcap_netif_device.dev_addr[2] = 0x37; - /* set mac address: (only for test) */ - pcap_netif_device.dev_addr[3] = 0x12; - pcap_netif_device.dev_addr[4] = 0x34; - pcap_netif_device.dev_addr[5] = 0x56; + pcap_netif_device.dev_addr[0] = 0x00; + pcap_netif_device.dev_addr[1] = 0x60; + pcap_netif_device.dev_addr[2] = 0x37; + /* set mac address: (only for test) */ + pcap_netif_device.dev_addr[3] = 0x12; + pcap_netif_device.dev_addr[4] = 0x34; + pcap_netif_device.dev_addr[5] = 0x56; - pcap_netif_device.parent.parent.init = pcap_netif_init; - pcap_netif_device.parent.parent.open = pcap_netif_open; - pcap_netif_device.parent.parent.close = pcap_netif_close; - pcap_netif_device.parent.parent.read = pcap_netif_read; - pcap_netif_device.parent.parent.write = pcap_netif_write; - pcap_netif_device.parent.parent.control = pcap_netif_control; - pcap_netif_device.parent.parent.user_data = RT_NULL; + pcap_netif_device.parent.parent.init = pcap_netif_init; + pcap_netif_device.parent.parent.open = pcap_netif_open; + pcap_netif_device.parent.parent.close = pcap_netif_close; + pcap_netif_device.parent.parent.read = pcap_netif_read; + pcap_netif_device.parent.parent.write = pcap_netif_write; + pcap_netif_device.parent.parent.control = pcap_netif_control; + pcap_netif_device.parent.parent.user_data = RT_NULL; - pcap_netif_device.parent.eth_rx = pcap_netif_rx; - pcap_netif_device.parent.eth_tx = pcap_netif_tx; + pcap_netif_device.parent.eth_rx = pcap_netif_rx; + pcap_netif_device.parent.eth_tx = pcap_netif_tx; - eth_device_init(&(pcap_netif_device.parent), "e0"); + eth_device_init(&(pcap_netif_device.parent), "e0"); } #include diff --git a/bsp/simulator/rtconfig_project.h b/bsp/simulator/rtconfig_project.h index 2ff5c8d3a4..098255741e 100644 --- a/bsp/simulator/rtconfig_project.h +++ b/bsp/simulator/rtconfig_project.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + #ifndef RTCONFIG_PROJECT_H__ #define RTCONFIG_PROJECT_H__ @@ -10,7 +19,7 @@ #define _INC_TIME_INL //dfs_elm.c time.h conflicts with wtime.inl /* disable some warning in MSC */ -#pragma warning(disable:4273) /* to ignore: warning C4273: inconsistent dll linkage */ +#pragma warning(disable:4273) /* to ignore: warning C4273: inconsistent dll linkage */ #pragma warning(disable:4312) /* to ignore: warning C4312: 'type cast' : conversion from 'rt_uint32_t' to 'rt_uint32_t *' */ #pragma warning(disable:4311) /* to ignore: warning C4311: 'type cast' : pointer truncation from 'short *__w64 ' to 'long' */ #pragma warning(disable:4996) /* to ignore: warning C4996: The POSIX name for this item is deprecated. */ diff --git a/bsp/stm32/stm32f072-st-nucleo/applications/main.c b/bsp/stm32/stm32f072-st-nucleo/applications/main.c index 81b03091e1..486ed61283 100644 --- a/bsp/stm32/stm32f072-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f072-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.c b/bsp/stm32/stm32f072-st-nucleo/board/board.c index 8adbcd7bdd..5f06e3253d 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f072-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-12-21 zylx first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; @@ -25,7 +25,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.h b/bsp/stm32/stm32f072-st-nucleo/board/board.h index bfd0371048..51a9f80edd 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f072-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f091-st-nucleo/applications/main.c b/bsp/stm32/stm32f091-st-nucleo/applications/main.c index 421f897bc4..9783d01e55 100644 --- a/bsp/stm32/stm32f091-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f091-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.c b/bsp/stm32/stm32f091-st-nucleo/board/board.c index db5c101a9d..ec74fe9af0 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f091-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-12-21 zylx first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14 |RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE; @@ -38,7 +38,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.h b/bsp/stm32/stm32f091-st-nucleo/board/board.h index 7a78136471..a9ba91377d 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f091-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h index 78bf24d251..b9964e0154 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c index 6d75fd13ce..be493624c1 100644 --- a/bsp/stm32/stm32f103-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c index bb35832bfa..de585efe32 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.c +++ b/bsp/stm32/stm32f103-atk-nano/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h index a33ef3cd5e..498459073e 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.h +++ b/bsp/stm32/stm32f103-atk-nano/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h index 0ca9acb3ea..3eb4fd7c0d 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c index 43f726525b..7892489436 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c index 140fb13c73..55c2b62023 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c index 17bfd29f27..2dc4c9cabf 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h index 68ac34f5f7..80c80984bf 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c index c0b077e600..420785bc9e 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h index 06ee47cca2..f51d21c6fa 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c index a56e1bc35f..d56fb039d4 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-blue-pill/applications/main.c b/bsp/stm32/stm32f103-blue-pill/applications/main.c index f1de7cf454..9be4cd59b1 100644 --- a/bsp/stm32/stm32f103-blue-pill/applications/main.c +++ b/bsp/stm32/stm32f103-blue-pill/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-blue-pill/board/board.c b/bsp/stm32/stm32f103-blue-pill/board/board.c index af6fb56470..22f1cc14f7 100644 --- a/bsp/stm32/stm32f103-blue-pill/board/board.c +++ b/bsp/stm32/stm32f103-blue-pill/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-03-08 obito0 first version */ - + #include "board.h" void SystemClock_Config(void) diff --git a/bsp/stm32/stm32f103-blue-pill/board/board.h b/bsp/stm32/stm32f103-blue-pill/board/board.h index fc435ee029..1be364929a 100644 --- a/bsp/stm32/stm32f103-blue-pill/board/board.h +++ b/bsp/stm32/stm32f103-blue-pill/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c index 7b7f00c8ee..0ec4930664 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c +++ b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c index 038725b78d..695510d1ac 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c +++ b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.c b/bsp/stm32/stm32f103-dofly-M3S/board/board.c index 7b6a3ea947..d32a5096b6 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/board.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-11-06 SummerGift first version * 2019-04-09 WillianChan add stm32f103-dofly-M3S BSP */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -29,7 +29,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.h b/bsp/stm32/stm32f103-dofly-M3S/board/board.h index 62f9030426..8662bff0f5 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/board.h +++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c index 5ffa50ba1d..13d235b694 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h index 5f83366ea0..0f0183422a 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c index 060c6d59b4..e22efac3c9 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c index 18dbaac95c..dc4e9cbb7e 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c +++ b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c index 9f1ba0ddab..8493439409 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h index ae6f2c67e8..8d8cc4643a 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c index 5f0f0db8ed..7ddaa5ee96 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-5 SummerGift first version */ - + #include #include #include diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c index 080a22ff49..abbc74be30 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include #include "board.h" @@ -17,7 +17,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h index 968ac8e2e5..7aa3c0f703 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h index 5f83366ea0..0f0183422a 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c index bf5f3e10a7..55baa2c263 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c index 96b2034f24..519080ae05 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c index 68348d2bac..378d8f8274 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c index 70f60f3f8b..bf9e60aae9 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c index 66a0c7f737..55faf0d89f 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" /** @@ -19,7 +19,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h index 7f0ae67d48..cdb13091cd 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c index d0ab2cc6ed..096b4df406 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c index 0598b6af0d..779d731980 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h index fe3ea19e77..239f0afdd6 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c index 0de060a35a..f18b6318bb 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,6 +21,6 @@ int esp_02_device_init() rt_pin_write(ESP8266_CH_PD_Pin,PIN_HIGH) ; rt_pin_write(ESP8266_RST,PIN_HIGH) ; - return RT_EOK ; + return RT_EOK ; } INIT_DEVICE_EXPORT(esp_02_device_init); diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h index 5f83366ea0..0f0183422a 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c index be8978c63d..ae0660b29a 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c index a0174bbb0c..59d139a8ac 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c index 6d75fd13ce..be493624c1 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c +++ b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/board.c b/bsp/stm32/stm32f103-onenet-nbiot/board/board.c index 258dd08e9d..5e045816b2 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/board/board.c +++ b/bsp/stm32/stm32f103-onenet-nbiot/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include "board.h" /** @@ -16,32 +16,32 @@ */ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } } diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/board.h b/bsp/stm32/stm32f103-onenet-nbiot/board/board.h index 070ccbbb45..162925a4f3 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/board/board.h +++ b/bsp/stm32/stm32f103-onenet-nbiot/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-yf-ufun/applications/main.c b/bsp/stm32/stm32f103-yf-ufun/applications/main.c index 737c362b23..ffe4955e19 100644 --- a/bsp/stm32/stm32f103-yf-ufun/applications/main.c +++ b/bsp/stm32/stm32f103-yf-ufun/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.c b/bsp/stm32/stm32f103-yf-ufun/board/board.c index 4df20fbd48..5271b59c71 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/board.c +++ b/bsp/stm32/stm32f103-yf-ufun/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 SummerGift first version */ - + #include "board.h" void SystemClock_Config(void) @@ -15,7 +15,7 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -28,7 +28,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.h b/bsp/stm32/stm32f103-yf-ufun/board/board.h index 8c0aa1d769..738f37080a 100644 --- a/bsp/stm32/stm32f103-yf-ufun/board/board.h +++ b/bsp/stm32/stm32f103-yf-ufun/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f107-uc-eval/applications/main.c b/bsp/stm32/stm32f107-uc-eval/applications/main.c index 11587e49d0..9dca242b10 100644 --- a/bsp/stm32/stm32f107-uc-eval/applications/main.c +++ b/bsp/stm32/stm32f107-uc-eval/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.c b/bsp/stm32/stm32f107-uc-eval/board/board.c index a63b070167..f053579c2f 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/board.c +++ b/bsp/stm32/stm32f107-uc-eval/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.h b/bsp/stm32/stm32f107-uc-eval/board/board.h index 98df6d51ff..44a96208c6 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/board.h +++ b/bsp/stm32/stm32f107-uc-eval/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/main.c b/bsp/stm32/stm32f401-st-nucleo/applications/main.c index 86c4508d12..48009f1c78 100644 --- a/bsp/stm32/stm32f401-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f401-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.c b/bsp/stm32/stm32f401-st-nucleo/board/board.c index 942d080c5b..9c33cdbba5 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f401-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -34,7 +34,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.h b/bsp/stm32/stm32f401-st-nucleo/board/board.h index 4c6f84d170..82647a83a4 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f401-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c index 453681a90a..47358c8a61 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c +++ b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c index ef1f24cbb5..190ca080cf 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h index 5b30f605d9..844f5e35e6 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h +++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c index e3ae33205f..2fc9307caf 100644 --- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c index c2c90a5e86..02a3a3d53f 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -37,7 +37,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h index 70a4c0ed19..6d80e38f78 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c index 2b60a6d2cc..dba9ec5e29 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,11 +26,11 @@ static struct rt_memheap system_heap; static SRAM_HandleTypeDef hsram; static int rt_hw_sram_init(void) -{ +{ int result = RT_EOK; FSMC_NORSRAM_TimingTypeDef Timing = {0}; - + /** Perform the SRAM2 memory initialization sequence */ hsram.Instance = FSMC_NORSRAM_DEVICE; @@ -57,7 +57,7 @@ static int rt_hw_sram_init(void) hsram.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; hsram.Init.PageSize = FSMC_PAGE_SIZE_NONE; - + /* Timing */ Timing.AddressSetupTime = 0; Timing.AddressHoldTime = 0; @@ -81,7 +81,7 @@ static int rt_hw_sram_init(void) rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE); #endif } - + return result; } INIT_BOARD_EXPORT(rt_hw_sram_init); @@ -153,7 +153,7 @@ static int sram_test(void) LOG_D("SRAM test success!"); } - return RT_EOK; + return RT_EOK; } MSH_CMD_EXPORT(sram_test, sram test); #endif /* FINSH_USING_MSH */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c index 838216ffaa..ec5c61f1b0 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c index 0a9c36fd42..bc7e8b676e 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c index 4705cc0112..b92344fa43 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h index b40082267a..6238e611b1 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-st-discovery/applications/main.c b/bsp/stm32/stm32f407-st-discovery/applications/main.c index c7ffc240cb..2651a75073 100644 --- a/bsp/stm32/stm32f407-st-discovery/applications/main.c +++ b/bsp/stm32/stm32f407-st-discovery/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.c b/bsp/stm32/stm32f407-st-discovery/board/board.c index 8a3dbd9937..5fff5426fe 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/board.c +++ b/bsp/stm32/stm32f407-st-discovery/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -33,7 +33,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.h b/bsp/stm32/stm32f407-st-discovery/board/board.h index 7ba6c79dee..539e3abf45 100644 --- a/bsp/stm32/stm32f407-st-discovery/board/board.h +++ b/bsp/stm32/stm32f407-st-discovery/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f410-st-nucleo/applications/main.c b/bsp/stm32/stm32f410-st-nucleo/applications/main.c index 1305c03138..05ab0e2504 100644 --- a/bsp/stm32/stm32f410-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f410-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f410-st-nucleo/board/board.c b/bsp/stm32/stm32f410-st-nucleo/board/board.c index dffc7ffba0..3e64df40d7 100644 --- a/bsp/stm32/stm32f410-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f410-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f410-st-nucleo/board/board.h b/bsp/stm32/stm32f410-st-nucleo/board/board.h index b9c9f8427f..72bd8a017c 100644 --- a/bsp/stm32/stm32f410-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f410-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-atk-nano/applications/main.c b/bsp/stm32/stm32f411-atk-nano/applications/main.c index 943b08cf15..df457f4760 100644 --- a/bsp/stm32/stm32f411-atk-nano/applications/main.c +++ b/bsp/stm32/stm32f411-atk-nano/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-atk-nano/board/board.c b/bsp/stm32/stm32f411-atk-nano/board/board.c index 2ca06e13bf..08158c2f96 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/board.c +++ b/bsp/stm32/stm32f411-atk-nano/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -34,7 +34,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f411-atk-nano/board/board.h b/bsp/stm32/stm32f411-atk-nano/board/board.h index 452aa7420c..2cbe75f5d9 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/board.h +++ b/bsp/stm32/stm32f411-atk-nano/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c index 43f726525b..7892489436 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/main.c b/bsp/stm32/stm32f411-st-nucleo/applications/main.c index b29630d930..0e109663ae 100644 --- a/bsp/stm32/stm32f411-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f411-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.c b/bsp/stm32/stm32f411-st-nucleo/board/board.c index e9e6ffb5e7..1d83386719 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f411-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.h b/bsp/stm32/stm32f411-st-nucleo/board/board.h index e05c785128..062038ffdb 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f411-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c index 729ae11bd6..be6a8af867 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c +++ b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/board.c b/bsp/stm32/stm32f411-weact-MiniF4/board/board.c index a19a49af8e..7f27135a6b 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/board/board.c +++ b/bsp/stm32/stm32f411-weact-MiniF4/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/board.h b/bsp/stm32/stm32f411-weact-MiniF4/board/board.h index e05c785128..062038ffdb 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/board/board.h +++ b/bsp/stm32/stm32f411-weact-MiniF4/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h b/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h index fe616d31cf..517d94f3ba 100644 --- a/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/main.c b/bsp/stm32/stm32f412-st-nucleo/applications/main.c index 317bc60514..2cf35c5bc6 100644 --- a/bsp/stm32/stm32f412-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f412-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.c b/bsp/stm32/stm32f412-st-nucleo/board/board.c index 504407b161..b8f8168dfa 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f412-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.h b/bsp/stm32/stm32f412-st-nucleo/board/board.h index 3e2d7384c8..5c463d04e8 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f412-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f413-st-nucleo/applications/main.c b/bsp/stm32/stm32f413-st-nucleo/applications/main.c index 18b64457a9..799dc6797d 100644 --- a/bsp/stm32/stm32f413-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f413-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.c b/bsp/stm32/stm32f413-st-nucleo/board/board.c index dffc5bba40..b36f973530 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f413-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,11 +20,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -40,7 +40,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.h b/bsp/stm32/stm32f413-st-nucleo/board/board.h index cd5e86661c..634003f596 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f413-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f427-robomaster-a/applications/main.c b/bsp/stm32/stm32f427-robomaster-a/applications/main.c index 7c21823832..6cef3cbb34 100644 --- a/bsp/stm32/stm32f427-robomaster-a/applications/main.c +++ b/bsp/stm32/stm32f427-robomaster-a/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.c b/bsp/stm32/stm32f427-robomaster-a/board/board.c index a0901feba9..780e089fcd 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/board.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,11 +19,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -37,13 +37,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.h b/bsp/stm32/stm32f427-robomaster-a/board/board.h index 4c74f95682..a0ea5ca4bd 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/board.h +++ b/bsp/stm32/stm32f427-robomaster-a/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c index b46537d311..6a79c83523 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/applications/main.c b/bsp/stm32/stm32f429-armfly-v6/applications/main.c index 70c2a3b0f7..21b7c14ec0 100644 --- a/bsp/stm32/stm32f429-armfly-v6/applications/main.c +++ b/bsp/stm32/stm32f429-armfly-v6/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,10 +18,10 @@ int main(void) int count = 1; HC574_SetPin(LED1,0); - HC574_SetPin(LED2,0); + HC574_SetPin(LED2,0); HC574_SetPin(LED3,0); HC574_SetPin(LED4,0); - + while (count++) { HC574_SetPin(LED1,1); @@ -29,6 +29,6 @@ int main(void) HC574_SetPin(LED1,0); rt_thread_mdelay(500); } - + return RT_EOK; } diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.c b/bsp/stm32/stm32f429-armfly-v6/board/board.c index f314b7c45a..2d37e631e3 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/board.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,12 +17,12 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /**Configure the main internal regulator output voltage + + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -39,13 +39,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -53,7 +53,7 @@ void SystemClock_Config(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.h b/bsp/stm32/stm32f429-armfly-v6/board/board.h index f0ea803bb0..c0d30df246 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/board.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c index 44a4a622c5..89fa42af5f 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,84 +17,84 @@ #include #include "drv_ext_io.h" -#define HC574_PORT *(volatile rt_uint32_t *)0x64001000 +#define HC574_PORT *(volatile rt_uint32_t *)0x64001000 volatile rt_uint32_t HC574_state = 0; void HC574_SetPin(rt_uint32_t _pin, uint8_t _value) { - if (_value == 0) - { - HC574_state &= (~_pin); - } - else - { - HC574_state |= _pin; - } - - HC574_PORT = HC574_state; + if (_value == 0) + { + HC574_state &= (~_pin); + } + else + { + HC574_state |= _pin; + } + + HC574_PORT = HC574_state; } rt_uint8_t HC574_GetPin(rt_uint32_t _pin) { - if (HC574_state & _pin) - { - return 1; - } - else - { - return 0; - } + if (HC574_state & _pin) + { + return 1; + } + else + { + return 0; + } } static void HC574_Config_FMC(void) { FMC_NORSRAM_TimingTypeDef timing = {0}; SRAM_HandleTypeDef sram2 = {0}; - - /* - For LCD compatibility£¬select 3-0-6-1-0-0 - 3-0-5-1-0-0 : RD high level 75ns£¬low level 50ns. Read 8 channels of data into memory in 1us. - 1-0-1-1-0-0 : RD high level 75ns£¬low level 12ns£¬trailing edge 12ns. - */ - /* FMC_Bank1_NORSRAM2 configuration */ - timing.AddressSetupTime = 3; - timing.AddressHoldTime = 0; - timing.DataSetupTime = 6; - timing.BusTurnAroundDuration = 1; - timing.CLKDivision = 0; - timing.DataLatency = 0; - timing.AccessMode = FMC_ACCESS_MODE_A; - /* - LCD configured as follow: - - Data/Address MUX = Disable - - Memory Type = SRAM - - Data Width = 32bit - - Write Operation = Enable - - Extended Mode = Enable - - Asynchronous Wait = Disable - */ + /* + For LCD compatibility，select 3-0-6-1-0-0 + 3-0-5-1-0-0 : RD high level 75ns，low level 50ns. Read 8 channels of data into memory in 1us. + 1-0-1-1-0-0 : RD high level 75ns，low level 12ns，trailing edge 12ns. + */ + /* FMC_Bank1_NORSRAM2 configuration */ + timing.AddressSetupTime = 3; + timing.AddressHoldTime = 0; + timing.DataSetupTime = 6; + timing.BusTurnAroundDuration = 1; + timing.CLKDivision = 0; + timing.DataLatency = 0; + timing.AccessMode = FMC_ACCESS_MODE_A; + + /* + LCD configured as follow: + - Data/Address MUX = Disable + - Memory Type = SRAM + - Data Width = 32bit + - Write Operation = Enable + - Extended Mode = Enable + - Asynchronous Wait = Disable + */ sram2.Instance = FMC_NORSRAM_DEVICE; sram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE; - sram2.Init.NSBank = FMC_NORSRAM_BANK2; - sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; - sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; - sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32; - sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; - sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; - sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE; - sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; - sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; - sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; - sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; - sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; - sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; + sram2.Init.NSBank = FMC_NORSRAM_BANK2; + sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; + sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32; + sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; + sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE; + sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; + sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; + sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; sram2.Init.PageSize = FMC_PAGE_SIZE_1024; - if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK) + if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK) { LOG_E("extend IO init failed!"); } @@ -106,12 +106,12 @@ static void HC574_Config_FMC(void) static int stm32_ext_io_init(void) { - HC574_Config_FMC(); - /* Set the chip select to high level */ - HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 ); + HC574_Config_FMC(); + /* Set the chip select to high level */ + HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 ); /* Change IO state */ - HC574_PORT = HC574_state; - + HC574_PORT = HC574_state; + return RT_EOK; } INIT_BOARD_EXPORT(stm32_ext_io_init); diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h index 09740d3571..3f336dd7ab 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,64 +13,64 @@ #include "rtthread.h" /* - armfly STM32-V6 Development board Extend IO - D0 - GPRS_RERM_ON - D1 - GPRS_RESET - D2 - NRF24L01_CE - D3 - NRF905_TX_EN - D4 - NRF905_TRX_CE/VS1053_XDCS - D5 - NRF905_PWR_UP - D6 - ESP8266_G0 - D7 - ESP8266_G2 - - D8 - LED1 - D9 - LED2 - D10 - LED3 - D11 - LED4 - D12 - TP_NRST - D13 - AD7606_OS0 - D14 - AD7606_OS1 - D15 - AD7606_OS2 - - GPIO can output 5V - D16 - Y50_0 - D17 - Y50_1 - D18 - Y50_2 - D19 - Y50_3 - D20 - Y50_4 - D21 - Y50_5 - D22 - Y50_6 - D23 - Y50_7 + armfly STM32-V6 Development board Extend IO + D0 - GPRS_RERM_ON + D1 - GPRS_RESET + D2 - NRF24L01_CE + D3 - NRF905_TX_EN + D4 - NRF905_TRX_CE/VS1053_XDCS + D5 - NRF905_PWR_UP + D6 - ESP8266_G0 + D7 - ESP8266_G2 - GPIO can output 3.3V - D24 - AD7606_RESET - D25 - AD7606_RAGE - D26 - Y33_2 - D27 - Y33_3 - D28 - Y33_4 - D29 - Y33_5 - D30 - Y33_6 - D31 - Y33_7 + D8 - LED1 + D9 - LED2 + D10 - LED3 + D11 - LED4 + D12 - TP_NRST + D13 - AD7606_OS0 + D14 - AD7606_OS1 + D15 - AD7606_OS2 + + GPIO can output 5V + D16 - Y50_0 + D17 - Y50_1 + D18 - Y50_2 + D19 - Y50_3 + D20 - Y50_4 + D21 - Y50_5 + D22 - Y50_6 + D23 - Y50_7 + + GPIO can output 3.3V + D24 - AD7606_RESET + D25 - AD7606_RAGE + D26 - Y33_2 + D27 - Y33_3 + D28 - Y33_4 + D29 - Y33_5 + D30 - Y33_6 + D31 - Y33_7 */ #ifndef GPIO_Pin_0 - #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ - #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ - #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ - #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ - #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ - #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ - #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ - #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ - #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ - #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ - #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ - #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ - #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ - #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ - #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ - #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#endif + #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ + #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ + #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ + #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ + #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ + #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ + #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ + #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ + #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ + #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ + #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ + #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ + #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ + #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ + #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ + #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#endif #define GPIO_Pin_16 ((uint32_t)0x00010000) /* Pin 0 selected */ #define GPIO_Pin_17 ((uint32_t)0x00020000) /* Pin 1 selected */ @@ -90,42 +90,42 @@ #define GPIO_Pin_31 ((uint32_t)0x80000000) /* Pin 15 selected */ /* Rename the macro for the sake of memory */ -#define GPRS_TERM_ON GPIO_Pin_0 -#define GPRS_RESET GPIO_Pin_1 -#define NRF24L01_CE GPIO_Pin_2 -#define NRF905_TX_EN GPIO_Pin_3 -#define NRF905_TRX_CE GPIO_Pin_4 +#define GPRS_TERM_ON GPIO_Pin_0 +#define GPRS_RESET GPIO_Pin_1 +#define NRF24L01_CE GPIO_Pin_2 +#define NRF905_TX_EN GPIO_Pin_3 +#define NRF905_TRX_CE GPIO_Pin_4 #define VS1053_XDCS GPIO_Pin_4 -#define NRF905_PWR_UP GPIO_Pin_5 -#define ESP8266_G0 GPIO_Pin_6 -#define ESP8266_G2 GPIO_Pin_7 - -#define LED1 GPIO_Pin_8 -#define LED2 GPIO_Pin_9 -#define LED3 GPIO_Pin_10 -#define LED4 GPIO_Pin_11 -#define TP_NRST GPIO_Pin_12 -#define AD7606_OS0 GPIO_Pin_13 -#define AD7606_OS1 GPIO_Pin_14 -#define AD7606_OS2 GPIO_Pin_15 - -#define Y50_0 GPIO_Pin_16 -#define Y50_1 GPIO_Pin_17 -#define Y50_2 GPIO_Pin_18 -#define Y50_3 GPIO_Pin_19 -#define Y50_4 GPIO_Pin_20 -#define Y50_5 GPIO_Pin_21 -#define Y50_6 GPIO_Pin_22 -#define Y50_7 GPIO_Pin_23 +#define NRF905_PWR_UP GPIO_Pin_5 +#define ESP8266_G0 GPIO_Pin_6 +#define ESP8266_G2 GPIO_Pin_7 -#define AD7606_RESET GPIO_Pin_24 -#define AD7606_RANGE GPIO_Pin_25 -#define Y33_2 GPIO_Pin_26 -#define Y33_3 GPIO_Pin_27 -#define Y33_4 GPIO_Pin_28 -#define Y33_5 GPIO_Pin_29 -#define Y33_6 GPIO_Pin_30 -#define Y33_7 GPIO_Pin_31 +#define LED1 GPIO_Pin_8 +#define LED2 GPIO_Pin_9 +#define LED3 GPIO_Pin_10 +#define LED4 GPIO_Pin_11 +#define TP_NRST GPIO_Pin_12 +#define AD7606_OS0 GPIO_Pin_13 +#define AD7606_OS1 GPIO_Pin_14 +#define AD7606_OS2 GPIO_Pin_15 + +#define Y50_0 GPIO_Pin_16 +#define Y50_1 GPIO_Pin_17 +#define Y50_2 GPIO_Pin_18 +#define Y50_3 GPIO_Pin_19 +#define Y50_4 GPIO_Pin_20 +#define Y50_5 GPIO_Pin_21 +#define Y50_6 GPIO_Pin_22 +#define Y50_7 GPIO_Pin_23 + +#define AD7606_RESET GPIO_Pin_24 +#define AD7606_RANGE GPIO_Pin_25 +#define Y33_2 GPIO_Pin_26 +#define Y33_3 GPIO_Pin_27 +#define Y33_4 GPIO_Pin_28 +#define Y33_5 GPIO_Pin_29 +#define Y33_6 GPIO_Pin_30 +#define Y33_7 GPIO_Pin_31 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value); rt_uint8_t HC574_GetPin(rt_uint32_t _pin); diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h index 31e2b9a392..0fda729291 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c index 36296b486a..6d97b5a979 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c index b46537d311..6a79c83523 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h index 1e57acb19f..9b5a363b6f 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c index e8fd133824..ac58f66259 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c index 487ddf44f6..6d19a46edb 100644 --- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c index c13619f753..36d2ff17d3 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,11 +18,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -39,13 +39,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.h b/bsp/stm32/stm32f429-atk-apollo/board/board.h index 9173f50c46..077b0af713 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/board.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c index ce1021fb60..889c5b0dee 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -86,7 +86,7 @@ void SAIB_config_set(struct rt_audio_configure config) SAIB_samplerate_set(config.samplerate); SAIB_samplebits_set(config.samplebits); } - + static void SAIB_config_init() { _sai_b.hsai.Instance = SAI1_Block_B; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h index 8aeede498c..0cc55f7aa9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,10 +8,10 @@ * 2019-07-28 Ernest the first version */ -#ifndef __DRV_MIC_H_ -#define __DRV_MIC_H_ +#ifndef __DRV_MIC_H_ +#define __DRV_MIC_H_ -#include +#include #include #endif diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c index 4a51ef6347..f564cc1b84 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ #define DBG_LVL DBG_INFO #include -#define CODEC_I2C_NAME ("i2c1") +#define CODEC_I2C_NAME ("i2c1") #define TX_DMA_FIFO_SIZE (2048) @@ -49,7 +49,7 @@ void SAIA_samplerate_set(rt_uint32_t freq) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; int i; - + /* check frequence */ for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++) { @@ -60,12 +60,12 @@ void SAIA_samplerate_set(rt_uint32_t freq) LOG_E("Can not support this frequence: %d.", freq); return; } - + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S; PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1]; PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2]; PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1; - + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S); diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h index 216481444f..28a1ea210d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-07-28 Ernest the first version + * 2019-07-28 Ernest the first version */ -#ifndef __DRV_SOUND_H_ -#define __DRV_SOUND_H_ +#ifndef __DRV_SOUND_H_ +#define __DRV_SOUND_H_ -#include +#include #include -#include +#include #define AUDIO_FREQUENCY_048K ((rt_uint32_t) 48000) #define AUDIO_FREQUENCY_044K ((rt_uint32_t) 44100) diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c index 5c7b8084c4..0f650538f9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -763,8 +763,8 @@ rt_err_t wm8978_init(struct rt_i2c_bus_device *dev) wm8978_interface_cfg(dev, I2S_FOMAT_SELECT, 16); wm8978_mic_enabled(dev, 0); - - return RT_EOK; + + return RT_EOK; } void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h index d385255f9c..fe476ec0bb 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c index 666d053b25..826f8c7ded 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,8 +16,8 @@ #include #define ETH_RESET_IO 7 //PHY RESET PIN -#define I2C_BUS_NAME "i2c1" -#define PCF8574_ADDR 0x20 +#define I2C_BUS_NAME "i2c1" +#define PCF8574_ADDR 0x20 /* pcf8574 hardware init */ pcf8574_device_t pcf8574_hw_init(char * dev_name, int addr) diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c index 10d0655a3a..fe2595fa4b 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h index ff948cb61e..85697210fa 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c index 26a9b2d2a8..7e35a36c86 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c index 1078b64286..64e40b75c8 100644 --- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c index ec47ab0d3a..5ca583d599 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.h b/bsp/stm32/stm32f429-fire-challenger/board/board.h index ab9e1733e9..c51f6a93cc 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/board.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h index a587e207ce..995136cd54 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h index 2660f3931b..8d297ec915 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c index 298dd14e29..8eaf6dcd5a 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c index d7b740ae47..01111ab4d3 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h index 72d7c8d06d..1e5978871b 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c index 5a1a4a2585..94a550cf37 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c index 277a754ae6..2660e6ef7c 100644 --- a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c +++ b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/applications/main.c b/bsp/stm32/stm32f429-st-disco/applications/main.c index 8e6e8caef1..992f2b5d74 100644 --- a/bsp/stm32/stm32f429-st-disco/applications/main.c +++ b/bsp/stm32/stm32f429-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/board/board.c b/bsp/stm32/stm32f429-st-disco/board/board.c index 0abc70267a..542681ae0b 100644 --- a/bsp/stm32/stm32f429-st-disco/board/board.c +++ b/bsp/stm32/stm32f429-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -48,7 +48,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /*##-2- LTDC Clock Configuration ###########################################*/ + /*##-2- LTDC Clock Configuration ###########################################*/ /* LCD clock configuration */ /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 MHz */ @@ -58,5 +58,5 @@ void SystemClock_Config(void) PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; PeriphClkInitStruct.PLLSAI.PLLSAIR = 4; PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); } diff --git a/bsp/stm32/stm32f429-st-disco/board/board.h b/bsp/stm32/stm32f429-st-disco/board/board.h index 69e3eb1fac..ce8f2cc591 100644 --- a/bsp/stm32/stm32f429-st-disco/board/board.h +++ b/bsp/stm32/stm32f429-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h index 46ecb322c4..ac75718bc7 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0; &nor_flash0, \ } -#define ONCHIP_FLASH_PART_TABLE +#define ONCHIP_FLASH_PART_TABLE #define QSPI_FLASH_PART_TABLE \ {FAL_PART_MAGIC_WROD, "qspiflash", FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0}, @@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, -#define QSPI_FLASH_PART_TABLE +#define QSPI_FLASH_PART_TABLE #else diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c index 3829193b5c..eaab59c78d 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c +++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c @@ -25,28 +25,28 @@ #include "stm32f4xx_hal.h" #include "ili9341.h" -/** - * @brief LCD Control pin - */ +/** + * @brief LCD Control pin + */ #define LCD_NCS_PIN GPIO_PIN_2 #define LCD_NCS_GPIO_PORT GPIOC #define LCD_NCS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define LCD_NCS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() -/** - * @brief LCD Command/data pin +/** + * @brief LCD Command/data pin */ #define LCD_WRX_PIN GPIO_PIN_13 #define LCD_WRX_GPIO_PORT GPIOD #define LCD_WRX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define LCD_WRX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() - + #define LCD_RDX_PIN GPIO_PIN_12 #define LCD_RDX_GPIO_PORT GPIOD #define LCD_RDX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() #define LCD_RDX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() -/* Maximum Timeout values for flags waiting loops */ +/* Maximum Timeout values for flags waiting loops */ #define SPIx_TIMEOUT_MAX ((uint32_t)0x1000) /* Chip Select macro definition */ @@ -73,8 +73,8 @@ static void SPIx_Init(void) { /* SPI configuration -----------------------------------------------------*/ SpiHandle.Instance = SPI5; - /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz) - */ + /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz) + */ SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; /* On STM32F429I-Discovery, LCD ID cannot be read then keep a common configuration */ @@ -90,9 +90,9 @@ static void SPIx_Init(void) SpiHandle.Init.NSS = SPI_NSS_SOFT; SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; SpiHandle.Init.Mode = SPI_MODE_MASTER; - + HAL_SPI_Init(&SpiHandle); - } + } } /** @@ -101,11 +101,11 @@ static void SPIx_Init(void) static void LCD_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStructure; - + if(Is_LCD_IO_Initialized == 0) { - Is_LCD_IO_Initialized = 1; - + Is_LCD_IO_Initialized = 1; + /* Configure NCS in Output Push-Pull mode */ LCD_WRX_GPIO_CLK_ENABLE(); GPIO_InitStructure.Pin = LCD_WRX_PIN; @@ -113,28 +113,28 @@ static void LCD_GPIO_Init(void) GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Speed = GPIO_SPEED_FAST; HAL_GPIO_Init(LCD_WRX_GPIO_PORT, &GPIO_InitStructure); - + LCD_RDX_GPIO_CLK_ENABLE(); GPIO_InitStructure.Pin = LCD_RDX_PIN; GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Speed = GPIO_SPEED_FAST; HAL_GPIO_Init(LCD_RDX_GPIO_PORT, &GPIO_InitStructure); - + /* Configure the LCD Control pins ----------------------------------------*/ LCD_NCS_GPIO_CLK_ENABLE(); - + /* Configure NCS in Output Push-Pull mode */ GPIO_InitStructure.Pin = LCD_NCS_PIN; GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Speed = GPIO_SPEED_FAST; HAL_GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - + /* Set or Reset the control line */ LCD_CS_LOW(); LCD_CS_HIGH(); - + SPIx_Init(); } } @@ -148,12 +148,12 @@ static void ili9341_write_data(uint16_t data) { /* Set WRX to send data */ LCD_WRX_HIGH(); - - /* Reset LCD control line(/CS) and Send data */ + + /* Reset LCD control line(/CS) and Send data */ LCD_CS_LOW(); - - HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX); - + + HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX); + /* Deselect: Chip Select high */ LCD_CS_HIGH(); } @@ -167,12 +167,12 @@ static void ili9341_write_register(uint8_t reg) { /* Reset WRX to send command */ LCD_WRX_LOW(); - + /* Reset LCD control line(/CS) and Send command */ LCD_CS_LOW(); - + HAL_SPI_Transmit(&SpiHandle, (uint8_t*) ®, 1, SPIx_TIMEOUT_MAX); - + /* Deselect: Chip Select high */ LCD_CS_HIGH(); } @@ -186,7 +186,7 @@ int ili9341_hw_init(void) { /* Initialize ILI9341 low level bus layer ----------------------------------*/ LCD_GPIO_Init(); - + /* Configure LCD */ ili9341_write_register(0xCA); ili9341_write_data(0xC3); @@ -242,7 +242,7 @@ int ili9341_hw_init(void) ili9341_write_data(0xA7); ili9341_write_data(0x27); ili9341_write_data(0x04); - + /* Colomn address set */ ili9341_write_register(LCD_COLUMN_ADDR); ili9341_write_data(0x00); @@ -259,13 +259,13 @@ int ili9341_hw_init(void) ili9341_write_data(0x01); ili9341_write_data(0x00); ili9341_write_data(0x06); - + ili9341_write_register(LCD_GRAM); rt_thread_mdelay(20); - + ili9341_write_register(LCD_GAMMA); ili9341_write_data(0x01); - + ili9341_write_register(LCD_PGAMMA); ili9341_write_data(0x0F); ili9341_write_data(0x29); @@ -298,14 +298,14 @@ int ili9341_hw_init(void) ili9341_write_data(0x28); ili9341_write_data(0x2F); ili9341_write_data(0x0F); - + ili9341_write_register(LCD_SLEEP_OUT); rt_thread_mdelay(20); ili9341_write_register(LCD_DISPLAY_ON); /* GRAM start writing */ ili9341_write_register(LCD_GRAM); - - return 0; + + return 0; } INIT_DEVICE_EXPORT(ili9341_hw_init); diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h index b4c59e6ffa..895683be5c 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h @@ -26,16 +26,16 @@ #ifdef __cplusplus extern "C" { -#endif +#endif -/** - * @brief ILI9341 chip IDs - */ +/** + * @brief ILI9341 chip IDs + */ #define ILI9341_ID 0x9341 -/** - * @brief ILI9341 Registers +/** + * @brief ILI9341 Registers */ /* Level 1 Commands */ @@ -57,32 +57,32 @@ #define LCD_GAMMA 0x26 /* Gamma register */ #define LCD_DISPLAY_OFF 0x28 /* Display off register */ #define LCD_DISPLAY_ON 0x29 /* Display on register */ -#define LCD_COLUMN_ADDR 0x2A /* Colomn address register */ -#define LCD_PAGE_ADDR 0x2B /* Page address register */ -#define LCD_GRAM 0x2C /* GRAM register */ -#define LCD_RGBSET 0x2D /* Color SET */ -#define LCD_RAMRD 0x2E /* Memory Read */ -#define LCD_PLTAR 0x30 /* Partial Area */ -#define LCD_VSCRDEF 0x33 /* Vertical Scrolling Definition */ -#define LCD_TEOFF 0x34 /* Tearing Effect Line OFF */ -#define LCD_TEON 0x35 /* Tearing Effect Line ON */ +#define LCD_COLUMN_ADDR 0x2A /* Colomn address register */ +#define LCD_PAGE_ADDR 0x2B /* Page address register */ +#define LCD_GRAM 0x2C /* GRAM register */ +#define LCD_RGBSET 0x2D /* Color SET */ +#define LCD_RAMRD 0x2E /* Memory Read */ +#define LCD_PLTAR 0x30 /* Partial Area */ +#define LCD_VSCRDEF 0x33 /* Vertical Scrolling Definition */ +#define LCD_TEOFF 0x34 /* Tearing Effect Line OFF */ +#define LCD_TEON 0x35 /* Tearing Effect Line ON */ #define LCD_MAC 0x36 /* Memory Access Control register*/ -#define LCD_VSCRSADD 0x37 /* Vertical Scrolling Start Address */ -#define LCD_IDMOFF 0x38 /* Idle Mode OFF */ -#define LCD_IDMON 0x39 /* Idle Mode ON */ +#define LCD_VSCRSADD 0x37 /* Vertical Scrolling Start Address */ +#define LCD_IDMOFF 0x38 /* Idle Mode OFF */ +#define LCD_IDMON 0x39 /* Idle Mode ON */ #define LCD_PIXEL_FORMAT 0x3A /* Pixel Format register */ -#define LCD_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */ -#define LCD_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */ -#define LCD_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */ -#define LCD_GET_SCANLINE 0x45 /* Get Scanline */ +#define LCD_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */ +#define LCD_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */ +#define LCD_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */ +#define LCD_GET_SCANLINE 0x45 /* Get Scanline */ #define LCD_WDB 0x51 /* Write Brightness Display register */ -#define LCD_RDDISBV 0x52 /* Read Display Brightness */ +#define LCD_RDDISBV 0x52 /* Read Display Brightness */ #define LCD_WCD 0x53 /* Write Control Display register*/ -#define LCD_RDCTRLD 0x54 /* Read CTRL Display */ -#define LCD_WRCABC 0x55 /* Write Content Adaptive Brightness Control */ -#define LCD_RDCABC 0x56 /* Read Content Adaptive Brightness Control */ -#define LCD_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */ -#define LCD_READ_CABC 0x5F /* Read CABC Minimum Brightness */ +#define LCD_RDCTRLD 0x54 /* Read CTRL Display */ +#define LCD_WRCABC 0x55 /* Write Content Adaptive Brightness Control */ +#define LCD_RDCABC 0x56 /* Read Content Adaptive Brightness Control */ +#define LCD_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */ +#define LCD_READ_CABC 0x5F /* Read CABC Minimum Brightness */ #define LCD_READ_ID1 0xDA /* Read ID1 */ #define LCD_READ_ID2 0xDB /* Read ID2 */ #define LCD_READ_ID3 0xDC /* Read ID3 */ @@ -129,13 +129,13 @@ /* Size of read registers */ #define LCD_READ_ID4_SIZE 3 /* Size of Read ID4 */ - + /** @defgroup ILI9341_Exported_Functions * @{ - */ + */ int ili9341_hw_init(void); - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h index 6f8112cc1b..21801def62 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h index 77c80f58ff..5a9f83e7d6 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c index 8559b69f98..d70e444ef4 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c +++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -154,7 +154,7 @@ int32_t touch_get_state(struct touch_state *state) res = touch_read(STMPE811_TSC_CTRL, &val); if (res < 0) return -1; state->pressed = (val & (1 << 7)) ? 1 : 0; - + if (state->pressed) { val = STMPE811_TSC_DATA; @@ -218,7 +218,7 @@ static int rt_hw_touch_init(void) /* register touch device to RT-Thread */ rt_device_register(&touch, "touch", RT_DEVICE_FLAG_RDWR); - + return RT_EOK; } INIT_BOARD_EXPORT(rt_hw_touch_init); diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h index 68c8f92b7f..a7b6328f17 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h +++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f446-st-nucleo/applications/main.c b/bsp/stm32/stm32f446-st-nucleo/applications/main.c index 0f283769a9..897c6eec1c 100644 --- a/bsp/stm32/stm32f446-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f446-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.c b/bsp/stm32/stm32f446-st-nucleo/board/board.c index aba3df89e1..a2500ee68a 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f446-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -35,13 +35,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.h b/bsp/stm32/stm32f446-st-nucleo/board/board.h index 1800e44079..8cb4438f8b 100644 --- a/bsp/stm32/stm32f446-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f446-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c index 277a754ae6..2660e6ef7c 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c +++ b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/applications/main.c b/bsp/stm32/stm32f469-st-disco/applications/main.c index 8feca19928..759572d376 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/main.c +++ b/bsp/stm32/stm32f469-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/board.c b/bsp/stm32/stm32f469-st-disco/board/board.c index 8c4c361dcc..fefb07fafd 100644 --- a/bsp/stm32/stm32f469-st-disco/board/board.c +++ b/bsp/stm32/stm32f469-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -36,13 +36,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f469-st-disco/board/board.h b/bsp/stm32/stm32f469-st-disco/board/board.h index 0880c1f384..607aa3877d 100644 --- a/bsp/stm32/stm32f469-st-disco/board/board.h +++ b/bsp/stm32/stm32f469-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c index 84202f84c8..8fde3a56ae 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-05-23 WillianChan first version */ - + #include #ifdef BSP_USING_LCD_OTM8009A extern DSI_HandleTypeDef hdsi; @@ -93,9 +93,9 @@ const rt_uint8_t RDS49[] = {0xF5, 0x06}; const rt_uint8_t RDS50[] = {0x00, 0xB1}; const rt_uint8_t RDS51[] = {0xC6, 0x06}; -void otm8009a_reset(void) +void otm8009a_reset(void) { - rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT); + rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT); rt_pin_write(GET_PIN(H, 7), PIN_LOW); rt_thread_delay(rt_tick_from_millisecond(20)); rt_pin_write(GET_PIN(H, 7), PIN_HIGH); @@ -116,7 +116,7 @@ static void otm8009a_write_cmd(uint8_t *p, uint32_t num) static void otm8009a_delay(uint32_t d) { - rt_thread_delay(rt_tick_from_millisecond(d)); + rt_thread_delay(rt_tick_from_millisecond(d)); } static void otm8009a_config(rt_uint32_t pixel_format) @@ -127,11 +127,11 @@ static void otm8009a_config(rt_uint32_t pixel_format) otm8009a_write_cmd((rt_uint8_t *)RDL02, 2); otm8009a_write_cmd((rt_uint8_t *)RDS02, 0); otm8009a_write_cmd((rt_uint8_t *)RDS03, 0); - otm8009a_delay(10); + otm8009a_delay(10); otm8009a_write_cmd((rt_uint8_t *)RDS04, 0); otm8009a_write_cmd((rt_uint8_t *)RDS05, 0); - otm8009a_delay(10); + otm8009a_delay(10); otm8009a_write_cmd((rt_uint8_t *)RDS06, 0); otm8009a_write_cmd((rt_uint8_t *)RDS07, 0); @@ -215,8 +215,8 @@ static void otm8009a_config(rt_uint32_t pixel_format) otm8009a_write_cmd((rt_uint8_t *)RDS01, 0); otm8009a_write_cmd((rt_uint8_t *)RDL04, 16); otm8009a_write_cmd((rt_uint8_t *)RDS36, 0); - otm8009a_delay(120); - + otm8009a_delay(120); + switch (pixel_format) { case RTGRAPHIC_PIXEL_FORMAT_RGB565: @@ -248,7 +248,7 @@ void stm32_mipi_lcd_init(void) void stm32_mipi_lcd_config(rt_uint32_t pixel_format) { - otm8009a_config(pixel_format); + otm8009a_config(pixel_format); } void stm32_mipi_display_on(void) diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c index f5fe27d6e1..ff1b11e34c 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-11-27 zylx first version * 2019-04-11 ZYH port from stm32f7serial */ - + #include #include #include @@ -64,7 +64,7 @@ void n25qxxa_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxxa_enter_qspi_mode, RT_NULL); - + /* init n25qxx */ if (RT_NULL == rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi10")) { diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c index cfe6f59e1e..9fd2d11fd4 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ static void _sdcard_mount(void) { rt_device_t device; - + device = rt_device_find("sd0"); if (device == NULL) { @@ -56,7 +56,7 @@ static void _sdcard_unmount(void) rt_thread_mdelay(200); dfs_unmount("/"); LOG_I("Unmount \"/\""); - + mmcsd_wait_cd_changed(0); stm32_mmcsd_change(); mmcsd_wait_cd_changed(RT_WAITING_FOREVER); @@ -65,7 +65,7 @@ static void _sdcard_unmount(void) static void sd_mount(void *parameter) { rt_uint8_t re_sd_check_pin = 1; - + while (1) { rt_thread_mdelay(200); @@ -73,7 +73,7 @@ static void sd_mount(void *parameter) { _sdcard_mount(); } - + if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0) { _sdcard_unmount(); @@ -84,7 +84,7 @@ static void sd_mount(void *parameter) int stm32_sdcard_mount(void) { rt_thread_t tid; - + rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP); tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h index 46ecb322c4..ac75718bc7 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0; &nor_flash0, \ } -#define ONCHIP_FLASH_PART_TABLE +#define ONCHIP_FLASH_PART_TABLE #define QSPI_FLASH_PART_TABLE \ {FAL_PART_MAGIC_WROD, "qspiflash", FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0}, @@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0; {FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \ {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, -#define QSPI_FLASH_PART_TABLE +#define QSPI_FLASH_PART_TABLE #else diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h index d5ee2b13b4..b23a970538 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,19 +7,19 @@ * Date Author Notes * 2018-07-28 liu2guang the first version for STM32F469NI-Discovery. */ - -#ifndef __DRV_LCD_H_ -#define __DRV_LCD_H_ -#include +#ifndef __DRV_LCD_H_ +#define __DRV_LCD_H_ + +#include #include -#include +#include #define LCD_WIDTH (800U) #define LCD_HEIGHT (480U) #define LCD_HSYNC (1U) -#define LCD_HBP (15U) +#define LCD_HBP (15U) #define LCD_HFP (16U) #define LCD_VSYNC (2U) #define LCD_VBP (34U) diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c index f90b468463..5b311a391a 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h index 14d44f7115..7b33d36362 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c index 1ff29544ff..53437f34ef 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-02-08 Zhangyihong the first version */ - + #include "drv_touch.h" #include #ifdef BSP_USING_TOUCH @@ -105,7 +105,7 @@ static void touch_thread_entry(void *parameter) { continue; } - + while(touch->ops->read_point(&msg) == RT_EOK) { switch (msg.event) diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h index a8fea21d54..21bea39f83 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-02-08 Zhangyihong the first version */ - + #ifndef __DRV_TOUCH_H__ #define __DRV_TOUCH_H__ diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c index a7e9275441..e85e793573 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -109,7 +109,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) { return RT_ERROR; } - + if (point_num == 0) { if (s_tp_down) @@ -121,7 +121,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) msg->event = TOUCH_EVENT_NONE; return RT_ERROR; } - + ret = ft_read(ft_i2c_bus, 0x03, point, 6); if (ret < 0) { @@ -130,7 +130,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) msg->y = (point[0]&0x0F) << 8 | point[1]; msg->x = (point[2]&0x0F) << 8 | point[3]; - + if (s_tp_down) { msg->event = TOUCH_EVENT_MOVE; @@ -138,7 +138,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) } msg->event = TOUCH_EVENT_DOWN; s_tp_down = 1; - + return RT_EOK; } diff --git a/bsp/stm32/stm32f746-st-disco/applications/main.c b/bsp/stm32/stm32f746-st-disco/applications/main.c index 669d889e58..0024ce1c0a 100644 --- a/bsp/stm32/stm32f746-st-disco/applications/main.c +++ b/bsp/stm32/stm32f746-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/board.c b/bsp/stm32/stm32f746-st-disco/board/board.c index bf92d115e7..da2564d515 100644 --- a/bsp/stm32/stm32f746-st-disco/board/board.c +++ b/bsp/stm32/stm32f746-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -42,13 +42,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f746-st-disco/board/board.h b/bsp/stm32/stm32f746-st-disco/board/board.h index 98e3799e00..b0c120fb41 100644 --- a/bsp/stm32/stm32f746-st-disco/board/board.h +++ b/bsp/stm32/stm32f746-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c index ca7641f866..4e37f4ec2f 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2019-01-26 jinsheng first version */ - + #include #include #include @@ -63,7 +63,7 @@ void n25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxx_enter_qspi_mode, RT_NULL); - + /* init n25q128 */ if (RT_NULL == rt_sfud_flash_probe("n25q128", "qspi10")) { diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h index c886dab45d..d7ce293475 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h index f534e50522..8ea00b0ed4 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c index 3d5f75c7f0..5825f775cc 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c index 0797f9326c..66e8dfefab 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h index 4c49e0f217..91bb91b01b 100644 --- a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/applications/main.c b/bsp/stm32/stm32f767-atk-apollo/applications/main.c index 7d7440f05c..71e6132ea2 100644 --- a/bsp/stm32/stm32f767-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32f767-atk-apollo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.c b/bsp/stm32/stm32f767-atk-apollo/board/board.c index d9959f9301..726b7783b7 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/board.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,15 +16,15 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -41,13 +41,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.h b/bsp/stm32/stm32f767-atk-apollo/board/board.h index 3d986024ae..e91271055e 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/board.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c index 5cabc9d4d2..72e589aea4 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init W25Q256 */ if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10")) { diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h index 891beb2010..5ddddaa2cd 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h index ca894bb045..156ba2e2cf 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c index d00e6c06e0..18bed5f8e4 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c index 0a9c36fd42..bc7e8b676e 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h index ff948cb61e..85697210fa 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/main.c b/bsp/stm32/stm32f767-fire-challenger/applications/main.c index 9ed6529712..4cf67f2e9e 100644 --- a/bsp/stm32/stm32f767-fire-challenger/applications/main.c +++ b/bsp/stm32/stm32f767-fire-challenger/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.c b/bsp/stm32/stm32f767-fire-challenger/board/board.c index f5b0c783c7..de621405e1 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/board.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,11 +16,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -34,13 +34,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.h b/bsp/stm32/stm32f767-fire-challenger/board/board.h index 1beb8c5f87..e9a1277849 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/board.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c index 36ecb754e9..a3091fd2eb 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init w25q128 */ if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) { diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h index 891beb2010..5ddddaa2cd 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h index 2660f3931b..8d297ec915 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c index 298dd14e29..8eaf6dcd5a 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c index 615ad6e06e..f1a7b8c27f 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h index 0d9c7e6918..7f9485aa4a 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-st-nucleo/applications/main.c b/bsp/stm32/stm32f767-st-nucleo/applications/main.c index ed3fc2c341..a0967c1326 100644 --- a/bsp/stm32/stm32f767-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32f767-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,5 +30,5 @@ int main(void) rt_thread_mdelay(500); } - return RT_EOK; + return RT_EOK; } diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.c b/bsp/stm32/stm32f767-st-nucleo/board/board.c index 0c63bfe489..4e00f26886 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/board.c +++ b/bsp/stm32/stm32f767-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,14 +21,14 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; @@ -42,13 +42,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Activate the Over-Drive mode + /**Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.h b/bsp/stm32/stm32f767-st-nucleo/board/board.h index 1d1e1d1106..1d82defe0d 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f767-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c index 8a833eec2a..79b8fecc16 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,6 +16,6 @@ void phy_reset(void) * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin, * so no additional reset is required. */ - + return ; } diff --git a/bsp/stm32/stm32f769-st-disco/applications/main.c b/bsp/stm32/stm32f769-st-disco/applications/main.c index 14a2f68f81..d61afe14c3 100644 --- a/bsp/stm32/stm32f769-st-disco/applications/main.c +++ b/bsp/stm32/stm32f769-st-disco/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f769-st-disco/board/board.c b/bsp/stm32/stm32f769-st-disco/board/board.c index 97bbbe3076..55126435b1 100644 --- a/bsp/stm32/stm32f769-st-disco/board/board.c +++ b/bsp/stm32/stm32f769-st-disco/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -42,13 +42,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Activate the Over-Drive mode + /** Activate the Over-Drive mode */ if (HAL_PWREx_EnableOverDrive() != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32f769-st-disco/board/board.h b/bsp/stm32/stm32f769-st-disco/board/board.h index 85c900e4c8..813dd5b27e 100644 --- a/bsp/stm32/stm32f769-st-disco/board/board.h +++ b/bsp/stm32/stm32f769-st-disco/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c index ca76f6e337..0a4f3f5216 100644 --- a/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,6 +16,6 @@ void phy_reset(void) * The PHY reset pin of DISCO-F769NI is connected to the MCU reset pin, * so no additional reset is required. */ - + return ; } diff --git a/bsp/stm32/stm32g070-st-nucleo/applications/main.c b/bsp/stm32/stm32g070-st-nucleo/applications/main.c index 8541bd3b9f..5f22fcae65 100644 --- a/bsp/stm32/stm32g070-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g070-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.c b/bsp/stm32/stm32g070-st-nucleo/board/board.c index 0c907528d0..101f483d27 100644 --- a/bsp/stm32/stm32g070-st-nucleo/board/board.c +++ b/bsp/stm32/stm32g070-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.h b/bsp/stm32/stm32g070-st-nucleo/board/board.h index f0345a1293..d36387892b 100644 --- a/bsp/stm32/stm32g070-st-nucleo/board/board.h +++ b/bsp/stm32/stm32g070-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h index ee65e188d9..277b98ba70 100644 --- a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g071-st-nucleo/applications/main.c b/bsp/stm32/stm32g071-st-nucleo/applications/main.c index 8541bd3b9f..5f22fcae65 100644 --- a/bsp/stm32/stm32g071-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g071-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.c b/bsp/stm32/stm32g071-st-nucleo/board/board.c index 5d634db15e..28d4e56e46 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/board.c +++ b/bsp/stm32/stm32g071-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,10 +16,10 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -36,7 +36,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1; @@ -48,7 +48,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the peripherals clocks + /**Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.h b/bsp/stm32/stm32g071-st-nucleo/board/board.h index f0345a1293..d36387892b 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/board.h +++ b/bsp/stm32/stm32g071-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h index ee65e188d9..277b98ba70 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g431-st-nucleo/applications/main.c b/bsp/stm32/stm32g431-st-nucleo/applications/main.c index aad9acb9b9..fa4fd35a6e 100644 --- a/bsp/stm32/stm32g431-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32g431-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.c b/bsp/stm32/stm32g431-st-nucleo/board/board.c index f025a3e234..7aeb088632 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/board.c +++ b/bsp/stm32/stm32g431-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,10 +17,10 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -36,7 +36,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -49,7 +49,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the peripherals clocks + /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.h b/bsp/stm32/stm32g431-st-nucleo/board/board.h index 9b91078b0f..6fd0c97890 100644 --- a/bsp/stm32/stm32g431-st-nucleo/board/board.h +++ b/bsp/stm32/stm32g431-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/applications/main.c b/bsp/stm32/stm32h743-atk-apollo/applications/main.c index 19a43a12e6..376d3c78ff 100644 --- a/bsp/stm32/stm32h743-atk-apollo/applications/main.c +++ b/bsp/stm32/stm32h743-atk-apollo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,9 +18,9 @@ int main(void) { int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + while (count++) { rt_pin_write(LED0_PIN, PIN_HIGH); diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.c b/bsp/stm32/stm32h743-atk-apollo/board/board.c index 0ae3016460..a96ed203a7 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/board.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,22 +16,22 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Supply configuration update enable + /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Macro to configure the PLL clock source + /** Macro to configure the PLL clock source */ __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -52,7 +52,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.h b/bsp/stm32/stm32h743-atk-apollo/board/board.h index ffb9772ee7..c9ec7a30d9 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/board.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ extern "C" { #endif -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000) #endif diff --git a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c index 5f4d8b1b80..929d317afa 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -55,7 +55,7 @@ int mpu_init(void) /* Enable CACHE */ SCB_EnableICache(); SCB_EnableDCache(); - + return 0; } diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c index 8a57c37e01..cc170ff945 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h index af519987dd..d40ffc6926 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c index 0ed9345156..95e5784654 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ struct rt_i2c_bus_device *i2c_bus = RT_NULL; #define JPEG_LINE_SIZE 1 * 1024 static pcf8574_device_t pcf_dev = RT_NULL; - + static rt_uint32_t *jpeg_data_buf = RT_NULL; static rt_uint32_t JPEG_LINE0_BUF[JPEG_LINE_SIZE]; static rt_uint32_t JPEG_LINE1_BUF[JPEG_LINE_SIZE]; @@ -454,7 +454,7 @@ rt_uint8_t ov2640_set_image_window_size(rt_uint16_t offx, rt_uint16_t offy, rt_u temp|=(offy>>4)&0X70; temp|=(hsize>>5)&0X08; temp|=(offx>>8)&0X07; - write_reg(i2c_bus, 0X55,temp); + write_reg(i2c_bus, 0X55,temp); write_reg(i2c_bus, 0X57,(hsize>>2)&0X80); write_reg(i2c_bus, 0XE0,0X00); return 0; @@ -550,36 +550,36 @@ int ov2640_pwdn_set(rt_uint8_t sta) return -1; } pcf8574_pin_write(pcf_dev, DCMI_PWDN_IO, sta); - + return 0; } void sw_ov2640_mode(void) -{ +{ GPIO_InitTypeDef GPIO_Initure = {0}; - + ov2640_pwdn_set(0); - - GPIO_Initure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; - GPIO_Initure.Mode = GPIO_MODE_AF_PP; - GPIO_Initure.Pull = GPIO_PULLUP; - GPIO_Initure.Speed = GPIO_SPEED_HIGH; - GPIO_Initure.Alternate = GPIO_AF13_DCMI; - HAL_GPIO_Init(GPIOC,&GPIO_Initure); -} + + GPIO_Initure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; + GPIO_Initure.Mode = GPIO_MODE_AF_PP; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Alternate = GPIO_AF13_DCMI; + HAL_GPIO_Init(GPIOC,&GPIO_Initure); +} void sw_sdcard_mode(void) { GPIO_InitTypeDef GPIO_Initure = {0}; - - ov2640_pwdn_set(1); /* OV2640 Power Down */ - GPIO_Initure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; - GPIO_Initure.Mode = GPIO_MODE_AF_PP; + ov2640_pwdn_set(1); /* OV2640 Power Down */ + + GPIO_Initure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11; + GPIO_Initure.Mode = GPIO_MODE_AF_PP; GPIO_Initure.Pull = GPIO_PULLUP; - GPIO_Initure.Speed = GPIO_SPEED_HIGH; - GPIO_Initure.Alternate = GPIO_AF12_SDMMC1; - HAL_GPIO_Init(GPIOC, &GPIO_Initure); + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_Initure); } int rt_ov2640_init(void) @@ -587,7 +587,7 @@ int rt_ov2640_init(void) rt_uint16_t i = 0; rt_err_t result = RT_EOK; rt_device_t dcmi_dev = RT_NULL; - + sw_ov2640_mode(); pcf_dev = pcf8574_init("i2c1", RT_NULL); if (pcf_dev == RT_NULL) @@ -595,17 +595,17 @@ int rt_ov2640_init(void) LOG_E("can't find pcf8574, please check it"); return -RT_ERROR; } - + ov2640_pwdn_set(0); - rt_thread_delay(20); - + rt_thread_delay(20); + /* ov2640 hard reset */ rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT); rt_pin_write(RESET_PIN, PIN_LOW); rt_thread_delay(20); rt_pin_write(RESET_PIN, PIN_HIGH); rt_thread_delay(20); - + i2c_bus = rt_i2c_bus_device_find(I2C_NAME); if (i2c_bus == RT_NULL) { @@ -687,7 +687,7 @@ int camera_sample(int argc, char **argv) rt_kprintf("camera_sample file.jpg\n"); return -1; } - + sw_ov2640_mode(); DCMI_Start(); diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h index 4ff948b0c6..e85e559421 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c index 5cabc9d4d2..72e589aea4 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init W25Q256 */ if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10")) { diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c index 07776296f0..a2789227a6 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h index 63f193e848..276064ddad 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h index 64c244f095..ca0c7a01b9 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h index ca894bb045..156ba2e2cf 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h index 5784f79036..50804561eb 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-st-nucleo/applications/main.c b/bsp/stm32/stm32h743-st-nucleo/applications/main.c index 2a4d35d4d8..9a8ac51bb5 100644 --- a/bsp/stm32/stm32h743-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32h743-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.c b/bsp/stm32/stm32h743-st-nucleo/board/board.c index dc2e79d04f..b5a5a4245d 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/board.c +++ b/bsp/stm32/stm32h743-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.h b/bsp/stm32/stm32h743-st-nucleo/board/board.h index 72d84ff29d..32eb25f147 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/board.h +++ b/bsp/stm32/stm32h743-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h747-st-discovery/applications/main.c b/bsp/stm32/stm32h747-st-discovery/applications/main.c index 9840fc6618..3904f7b3bc 100644 --- a/bsp/stm32/stm32h747-st-discovery/applications/main.c +++ b/bsp/stm32/stm32h747-st-discovery/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.c b/bsp/stm32/stm32h747-st-discovery/board/board.c index a7af6b13f8..73f2013e66 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/board.c +++ b/bsp/stm32/stm32h747-st-discovery/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.h b/bsp/stm32/stm32h747-st-discovery/board/board.h index c3441d01b1..85196a7664 100644 --- a/bsp/stm32/stm32h747-st-discovery/board/board.h +++ b/bsp/stm32/stm32h747-st-discovery/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c index 73691fa783..b19e338dc5 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c +++ b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c index 7783d407a8..6426138e1e 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,18 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Supply configuration update enable + /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Macro to configure the PLL clock source + /** Macro to configure the PLL clock source */ __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -50,7 +50,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h index a0455aec76..b41ed17e43 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l010-st-nucleo/applications/main.c b/bsp/stm32/stm32l010-st-nucleo/applications/main.c index 8541bd3b9f..5f22fcae65 100644 --- a/bsp/stm32/stm32l010-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l010-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.c b/bsp/stm32/stm32l010-st-nucleo/board/board.c index 858d59660f..62621eed0a 100644 --- a/bsp/stm32/stm32l010-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l010-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -56,11 +56,11 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.h b/bsp/stm32/stm32l010-st-nucleo/board/board.h index 9ca68af470..67e4ad5ec0 100644 --- a/bsp/stm32/stm32l010-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l010-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l053-st-nucleo/applications/main.c b/bsp/stm32/stm32l053-st-nucleo/applications/main.c index 8541bd3b9f..5f22fcae65 100644 --- a/bsp/stm32/stm32l053-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l053-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.c b/bsp/stm32/stm32l053-st-nucleo/board/board.c index 858d59660f..62621eed0a 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l053-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,11 +17,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -35,7 +35,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -56,11 +56,11 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.h b/bsp/stm32/stm32l053-st-nucleo/board/board.h index 016e4ec4e3..f88ee51946 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l053-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l412-st-nucleo/applications/main.c b/bsp/stm32/stm32l412-st-nucleo/applications/main.c index 2511e7a3bc..b22a9d1ba3 100644 --- a/bsp/stm32/stm32l412-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l412-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.c b/bsp/stm32/stm32l412-st-nucleo/board/board.c index 70a17da702..1ac2bc2df9 100644 --- a/bsp/stm32/stm32l412-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l412-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,13 +17,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -41,7 +41,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -62,22 +62,22 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - /**Enable MSI Auto calibration + /**Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.h b/bsp/stm32/stm32l412-st-nucleo/board/board.h index e88c9168b4..1f1519158f 100644 --- a/bsp/stm32/stm32l412-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l412-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l431-BearPi/applications/main.c b/bsp/stm32/stm32l431-BearPi/applications/main.c index 8bda11b8cd..9222b842fc 100644 --- a/bsp/stm32/stm32l431-BearPi/applications/main.c +++ b/bsp/stm32/stm32l431-BearPi/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l431-BearPi/board/board.c b/bsp/stm32/stm32l431-BearPi/board/board.c index 368ab74da1..b1a9d3d860 100644 --- a/bsp/stm32/stm32l431-BearPi/board/board.c +++ b/bsp/stm32/stm32l431-BearPi/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,13 +16,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE |RCC_OSCILLATORTYPE_MSI; @@ -43,7 +43,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -65,22 +65,22 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - /**Enable MSI Auto calibration + /**Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); diff --git a/bsp/stm32/stm32l431-BearPi/board/board.h b/bsp/stm32/stm32l431-BearPi/board/board.h index 3b3a77e103..77db7fce6e 100644 --- a/bsp/stm32/stm32l431-BearPi/board/board.h +++ b/bsp/stm32/stm32l431-BearPi/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l432-st-nucleo/applications/main.c b/bsp/stm32/stm32l432-st-nucleo/applications/main.c index e1755ec81e..336347c11e 100644 --- a/bsp/stm32/stm32l432-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l432-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.c b/bsp/stm32/stm32l432-st-nucleo/board/board.c index 79f7c0344f..93000dc18c 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l432-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,13 +17,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -42,7 +42,7 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -63,22 +63,22 @@ void SystemClock_Config(void) _Error_Handler(__FILE__, __LINE__); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); } - /**Configure the Systick interrupt time + /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /**Configure the Systick + /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - /**Enable MSI Auto calibration + /**Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.h b/bsp/stm32/stm32l432-st-nucleo/board/board.h index 3b3a77e103..77db7fce6e 100644 --- a/bsp/stm32/stm32l432-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l432-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l433-st-nucleo/applications/main.c b/bsp/stm32/stm32l433-st-nucleo/applications/main.c index 43c2522c51..056bad6689 100644 --- a/bsp/stm32/stm32l433-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l433-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l433-st-nucleo/board/board.c b/bsp/stm32/stm32l433-st-nucleo/board/board.c index 0cf319801f..284b759c59 100644 --- a/bsp/stm32/stm32l433-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l433-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,11 +20,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -42,7 +42,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -65,13 +65,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { Error_Handler(); } - /** Enable MSI Auto calibration + /** Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); } diff --git a/bsp/stm32/stm32l433-st-nucleo/board/board.h b/bsp/stm32/stm32l433-st-nucleo/board/board.h index 3b3a77e103..77db7fce6e 100644 --- a/bsp/stm32/stm32l433-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l433-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l452-st-nucleo/applications/main.c b/bsp/stm32/stm32l452-st-nucleo/applications/main.c index aad9acb9b9..fa4fd35a6e 100644 --- a/bsp/stm32/stm32l452-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l452-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.c b/bsp/stm32/stm32l452-st-nucleo/board/board.c index 5ab9da967a..d6c090b6b8 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l452-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -36,7 +36,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -55,7 +55,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.h b/bsp/stm32/stm32l452-st-nucleo/board/board.h index 1ea1e6be9c..0c9006dc40 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l452-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h index db782a5991..09c420dae9 100644 --- a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,9 +20,9 @@ extern const struct fal_flash_dev stm32_onchip_flash; /* ========================= Device Configuration ========================== */ #ifdef BSP_USING_ON_CHIP_FLASH -#define ONCHIP_FLASH_DEV &stm32_onchip_flash, +#define ONCHIP_FLASH_DEV &stm32_onchip_flash, #else -#define ONCHIP_FLASH_DEV +#define ONCHIP_FLASH_DEV #endif /* BSP_USING_ON_CHIP_FLASH */ /* flash device table */ diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c b/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c index 3283560274..a89c5e0b9c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,30 +18,30 @@ static int lcd_sample(void) { - /* ÇåÆÁ */ + /* æ¸…å± */ lcd_clear(WHITE); - /* ÏÔʾ RT-Thread logo */ + /* 显示 RT-Thread logo */ lcd_show_image(0, 0, 240, 69, image_rttlogo); - - /* ÉèÖñ³¾°É«ºÍÇ°¾°É« */ + + /* 设置背景色和å‰æ™¯è‰² */ lcd_set_color(WHITE, BLACK); - /* ÔÚ LCD ÉÏÏÔʾ×Ö·û */ + /* 在 LCD 上显示字符 */ lcd_show_string(10, 69, 16, "Hello, RT-Thread!"); lcd_show_string(10, 69+16, 24, "RT-Thread"); lcd_show_string(10, 69+16+24, 32, "RT-Thread"); - - /* ÔÚ LCD ÉÏ»­Ïß */ + + /* 在 LCD 上画线 */ lcd_draw_line(0, 69+16+24+32, 240, 69+16+24+32); - - /* ÔÚ LCD ÉÏ»­Ò»¸öͬÐÄÔ² */ + + /* 在 LCD 上画一个åŒå¿ƒåœ† */ lcd_draw_point(120, 194); for (int i = 0; i < 46; i += 4) { lcd_draw_circle(120, 194, i); } - + return RT_EOK; } INIT_APP_EXPORT(lcd_sample); diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c index 97e08a7d42..dfad8c68c1 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c +++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c index e97c6784ae..d711d2c3d6 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -22,11 +22,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -44,7 +44,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -76,7 +76,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h index ee516b50db..a1029a3e99 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c index fe115eb593..5d9844c6bd 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h index 472c844fca..ac758960f8 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c index c4ea570dd7..ac604875f0 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c index bccf9c62db..b19d584d3d 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h index 4dc76631c7..d573b0dee5 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c index 65bdcd85f9..f80ca3a4b2 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -955,7 +955,7 @@ rt_err_t lcd_show_qrcode(rt_uint16_t x, rt_uint16_t y, rt_uint8_t version, rt_ui { enlargement_factor = enlargement; } - + /* malloc memory for quick display of qrcode */ qrcode_buf = rt_malloc(qrcode.size * 2 * enlargement_factor * enlargement_factor); if (qrcode_buf == RT_NULL) diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h index ca4c28595f..394305012e 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-08-14 flybreak the first version - * 2018-09-18 balanceTWK add sleep mode function + * 2018-09-18 balanceTWK add sleep mode function */ #ifndef __DRV_LCD_H__ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h index d73d3c4d62..a326936b7b 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h @@ -1,5 +1,5 @@ #ifndef __DRV_LCD_FONT_H__ -#define __DRV_LCD_FONT_H__ +#define __DRV_LCD_FONT_H__ #include /* DejaVu Sans Mono */ /* diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c index aef2226239..f866d2741c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include @@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - + /* init w25q128 */ if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) { diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c index 92ec9d539b..c7f561e0b7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -46,10 +46,10 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) DMA2_Channel4->CCR &= ~0x00000001; DMA2->IFCR = DMA_ISR_GIF1 << 4; - + DMA2_CSELR->CSELR &= ~(0xf << (3 * 4)); // channel 4 - DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); - + DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); + DMA2_Channel4->CCR = DMA_MEMORY_TO_PERIPH | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \ DMA_PDATAALIGN_WORD | DMA_MDATAALIGN_WORD | DMA_NORMAL | DMA_PRIORITY_MEDIUM; DMA2_Channel4->CNDTR = BufferSize; @@ -57,7 +57,7 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) DMA2_Channel4->CMAR = (uint32_t)src; DMA2_Channel4->CCR |= 0x00000001; - + // HAL_DMA_Start(&SDTxDMAHandler, (uint32_t)src, (uint32_t)dst, BufferSize); } @@ -73,9 +73,9 @@ void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize) DMA2_Channel4->CCR &= ~0x00000001; DMA2->IFCR = DMA_ISR_GIF1 << 4; - + DMA2_CSELR->CSELR &= ~(0xf << (3 * 4)); // channel 4 - DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); + DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); DMA2_Channel4->CCR = DMA_PERIPH_TO_MEMORY | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \ DMA_PDATAALIGN_WORD | DMA_MDATAALIGN_WORD | DMA_NORMAL | DMA_PRIORITY_MEDIUM; @@ -130,7 +130,7 @@ void SD_LowLevel_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c index 91ebb73e1e..5655b27237 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * + * */ #include diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h index a6d43e21ba..25ed2c3ff7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c index 3f1e4776b4..fc9a1c7ada 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c index 76272c8de2..bf4babd15f 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c index d253cc179e..fac1209a63 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c index fc5d4759e9..7f0986e0d7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -200,7 +200,7 @@ static int read_cfg(void *buff, int len) { return 0; } - + return len; } diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h index 35a0fc8956..ee8477d9be 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c index 6c56cbcf6f..431a18008c 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h index 461c5f0e8d..e940dd99e2 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-st-discovery/applications/main.c b/bsp/stm32/stm32l475-st-discovery/applications/main.c index 2c4ca35a6b..bddb8abe63 100644 --- a/bsp/stm32/stm32l475-st-discovery/applications/main.c +++ b/bsp/stm32/stm32l475-st-discovery/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.c b/bsp/stm32/stm32l475-st-discovery/board/board.c index bdd1307a91..cd2f9a5989 100644 --- a/bsp/stm32/stm32l475-st-discovery/board/board.c +++ b/bsp/stm32/stm32l475-st-discovery/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -32,7 +32,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -51,7 +51,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.h b/bsp/stm32/stm32l475-st-discovery/board/board.h index e49d71c68c..2b5f830eb9 100644 --- a/bsp/stm32/stm32l475-st-discovery/board/board.h +++ b/bsp/stm32/stm32l475-st-discovery/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/main.c b/bsp/stm32/stm32l476-st-nucleo/applications/main.c index e92ed8da71..b22a8b8e8d 100644 --- a/bsp/stm32/stm32l476-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l476-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.c b/bsp/stm32/stm32l476-st-nucleo/board/board.c index 88600d4b4f..0d279e679a 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.h b/bsp/stm32/stm32l476-st-nucleo/board/board.h index b59fe1b3b6..c0b6a905ff 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l476-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/applications/main.c b/bsp/stm32/stm32l496-ali-developer/applications/main.c index d4926deb07..86d1cf72dd 100644 --- a/bsp/stm32/stm32l496-ali-developer/applications/main.c +++ b/bsp/stm32/stm32l496-ali-developer/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.c b/bsp/stm32/stm32l496-ali-developer/board/board.c index f9413f8f98..a0886582d4 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/board.c +++ b/bsp/stm32/stm32l496-ali-developer/board/board.c @@ -20,11 +20,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure LSE Drive Capability + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE |RCC_OSCILLATORTYPE_MSI; @@ -44,7 +44,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -77,7 +77,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.h b/bsp/stm32/stm32l496-ali-developer/board/board.h index 78cc07314b..6d99022522 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/board.h +++ b/bsp/stm32/stm32l496-ali-developer/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c index e37a67f4a1..be6c2a5744 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c +++ b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-27 zylx first version */ - + #include #include #include diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h index d7a1db25e9..a0598e9d83 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c index 8a2c1cade7..6abc52c3ba 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-st-nucleo/applications/main.c b/bsp/stm32/stm32l496-st-nucleo/applications/main.c index 20931cb3af..efe91875b9 100644 --- a/bsp/stm32/stm32l496-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l496-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.c b/bsp/stm32/stm32l496-st-nucleo/board/board.c index 370b558be0..29f27a354f 100644 --- a/bsp/stm32/stm32l496-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l496-st-nucleo/board/board.c @@ -22,11 +22,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure LSE Drive Capability + /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -44,7 +44,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -71,13 +71,13 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { Error_Handler(); } - /** Enable MSI Auto calibration + /** Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); } diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.h b/bsp/stm32/stm32l496-st-nucleo/board/board.h index b215ae9ee8..f9edac21da 100644 --- a/bsp/stm32/stm32l496-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l496-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c index df59d02ff9..2dbb2b2c81 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,12 +19,12 @@ /* defined the LED3 pin: PB14 */ #define LED3_PIN GET_PIN(B, 14) -#define LED_RUN_PIN LED3_PIN +#define LED_RUN_PIN LED3_PIN int main(void) { int count = 1; - + rt_pin_mode(LED_RUN_PIN, PIN_MODE_OUTPUT); while (count++) diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c index 7ab82ccd58..4b1fccdb4e 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,13 +16,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -38,7 +38,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h index 095f503423..b90222c6e3 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-5 SummerGift first version - * 2019-04-09 jhb + * 2019-04-09 jhb */ #ifndef __BOARD_H__ diff --git a/bsp/stm32/stm32l4r9-st-eval/applications/main.c b/bsp/stm32/stm32l4r9-st-eval/applications/main.c index ee74c2edd2..c53f70fb97 100644 --- a/bsp/stm32/stm32l4r9-st-eval/applications/main.c +++ b/bsp/stm32/stm32l4r9-st-eval/applications/main.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version - * 2019-04-09 jhb + * 2019-04-09 jhb */ #include diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c index af69f12729..cf4231f00c 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,13 +16,13 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage + /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; @@ -37,7 +37,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -63,5 +63,5 @@ void SystemClock_Config(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); - } + } } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.h b/bsp/stm32/stm32l4r9-st-eval/board/board.h index f9f8adbcf8..7d85022bb4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-11-5 SummerGift first version - * 2019-04-09 jhb + * 2019-04-09 jhb */ #ifndef __BOARD_H__ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c index 8e926d7e2d..e00616eaac 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -706,17 +706,17 @@ void line() lcd = (struct drv_lcd_dsi_device *)rt_device_find("lcd_dsi"); rt_uint8_t *ptr = lcd->lcd_info.framebuffer; - /* red */ - for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + /* red */ + for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + - } MSH_CMD_EXPORT(line, line); diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c index f77fa05aee..416e6863a7 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c index 314b1d707f..dc24066f51 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c index 726be84e0d..0d3904444f 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -119,7 +119,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) { return RT_ERROR; } - + if (point_num == 0) { if (s_tp_down) @@ -131,7 +131,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) msg->event = TOUCH_EVENT_NONE; return RT_ERROR; } - + ret = ft_read(ft_i2c_bus, 0x03, point, 6); if (ret < 0) { @@ -147,7 +147,7 @@ static rt_err_t ft_read_point(touch_msg_t msg) } msg->event = TOUCH_EVENT_DOWN; s_tp_down = 1; - + return RT_EOK; } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h index 0e0cfae502..b70dd3eb25 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h index fbc56b4a44..4d602fc344 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h index a5d89f1d80..f02a735dc4 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-discovery/.config b/bsp/stm32/stm32mp157a-st-discovery/.config index 5715750c67..47f0965c66 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/.config +++ b/bsp/stm32/stm32mp157a-st-discovery/.config @@ -55,6 +55,8 @@ CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y # @@ -154,7 +156,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -260,8 +262,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -275,6 +275,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set # # security packages @@ -302,6 +305,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_TJPGD is not set # CONFIG_PKG_USING_HELIX is not set # CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -313,9 +317,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set @@ -323,6 +330,18 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set # CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages @@ -341,6 +360,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -355,11 +376,20 @@ CONFIG_RT_USING_PIN=y # Micrium: Micrium software products porting for RT-Thread # # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set # CONFIG_PKG_USING_UC_CRC is not set # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -368,6 +398,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -416,6 +447,26 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_DM9051 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set # # miscellaneous packages @@ -425,6 +476,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -446,19 +498,22 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32MP1=y @@ -479,6 +534,7 @@ CONFIG_BSP_USING_STLINK_TO_USART=y # CONFIG_BSP_USING_RS485 is not set # CONFIG_BSP_USING_GBE is not set # CONFIG_BSP_USING_SDMMC is not set +# CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_AUDIO is not set # diff --git a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c index d8f61de87e..85d9d3ba89 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c +++ b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,19 +15,19 @@ /* defined the LD7 pin: PH7 */ #define LED7_PIN GET_PIN(H, 7) -int main(void) +int main(void) { int count = 1; /* set LD7 pin mode to output */ rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT); - + while (count++) { rt_pin_write(LED7_PIN, PIN_HIGH); - rt_thread_mdelay(500); + rt_thread_mdelay(500); rt_pin_write(LED7_PIN, PIN_LOW); rt_thread_mdelay(500); } - + return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.c b/bsp/stm32/stm32mp157a-st-discovery/board/board.c index cb44c09515..92180ecaa8 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/board.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2006-2018, RT-Thread Development Team +* Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,13 +20,13 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); - - /**Initializes the CPU, AHB and APB busses clocks + + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE @@ -39,7 +39,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = 0x10; /* Default reset value */ - + /**PLL1 Config */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -53,7 +53,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL; RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + /**PLL2 Config */ RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; @@ -67,7 +67,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL; RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + /**PLL3 Config */ RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; @@ -82,7 +82,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL; RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + /**PLL4 Config */ RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON; @@ -97,7 +97,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER; RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -119,12 +119,12 @@ void SystemClock_Config(void) RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2; RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2; RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2; - + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { Error_Handler(); } - + /**Set the HSE division factor for RTC clock */ __HAL_RCC_RTC_HSEDIV(24); @@ -137,7 +137,7 @@ void SystemClock_Config(void) */ void PeriphCommonClock_Config(void) { RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + /** Initializes the common periph clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER; @@ -149,11 +149,11 @@ void PeriphCommonClock_Config(void) { extern void rt_hw_systick_init(void); extern int rt_hw_usart_init(void); -void rt_hw_board_init() +void rt_hw_board_init() { /* HAL_Init() function is called at the beginning of the program */ HAL_Init(); - + /* enable interrupt */ __set_PRIMASK(0); /* Configure the system clock */ @@ -163,29 +163,29 @@ void rt_hw_board_init() } /* disable interrupt */ __set_PRIMASK(1); - + rt_hw_systick_init(); - + /* Heap initialization */ #if defined(RT_USING_HEAP) rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif - + /* Pin driver initialization is open by default */ #ifdef RT_USING_PIN rt_hw_pin_init(); #endif - + /* USART driver initialization is open by default */ #ifdef RT_USING_SERIAL rt_hw_usart_init(); #endif - + /* Set the shell console output device */ #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - + /* Board underlying hardware initialization */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.h b/bsp/stm32/stm32mp157a-st-discovery/board/board.h index 2472d96400..0b60c68af4 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/board.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,12 +22,12 @@ extern "C" { #endif -#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) +#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) #define STM32_FLASH_SIZE (192 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) - + #define STM32_SRAM_SIZE (64) -#define STM32_SRAM_END (0x10030000 + 64 * 1024) +#define STM32_SRAM_END (0x10030000 + 64 * 1024) #if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c index 315f6320d5..2e045b016b 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include #include -#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC) +#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC) #define BUFSZ 1024 #define SOUND_DEVICE_NAME "sound0" static rt_device_t snd_dev; @@ -217,7 +217,7 @@ int wavrecord_sample(int argc, char **argv) caps.main_type = AUDIO_TYPE_INPUT; caps.sub_type = AUDIO_DSP_PARAM; caps.udata.config.samplerate = RECORD_SAMPLERATE; - caps.udata.config.channels = RECORD_CHANNEL; + caps.udata.config.channels = RECORD_CHANNEL; caps.udata.config.samplebits = 16; rt_device_control(mic_dev, AUDIO_CTL_CONFIGURE, &caps); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c index e0ae5f1b5e..47ac5b0de2 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ /* CS42L51 address */ #define CHIP_ADDRESS 0x4A /* reset pin, active low */ -#define CS42L51_RESET_PIN GET_PIN(G, 9) +#define CS42L51_RESET_PIN GET_PIN(G, 9) static uint16_t CS42L51_Device = OUT_HEADPHONE; static struct rt_i2c_bus_device *audio_dev = RT_NULL; @@ -31,12 +31,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8 struct rt_i2c_msg msg[2] = {0, 0}; RT_ASSERT(bus != RT_NULL); - + msg[0].addr = CHIP_ADDRESS; /* Slave address */ msg[0].flags = RT_I2C_WR; /* Write flag */ msg[0].buf = ® /* Slave register address */ msg[0].len = 1; /* Number of bytes sent */ - + msg[1].addr = CHIP_ADDRESS; msg[1].flags = RT_I2C_RD; msg[1].len = len; @@ -57,8 +57,8 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint struct rt_i2c_msg msgs; RT_ASSERT(bus != RT_NULL); - - buf[0] = reg; + + buf[0] = reg; buf[1] = data; msgs.addr = CHIP_ADDRESS; @@ -119,10 +119,10 @@ static void cs42l51_lowlevel_init(void) /* Power off the cs42l51 */ rt_pin_write(CS42L51_RESET_PIN, PIN_LOW); - /* wait until power supplies are stable */ + /* wait until power supplies are stable */ rt_thread_mdelay(10); - /* Power on the cs42l51 */ + /* Power on the cs42l51 */ rt_pin_write(CS42L51_RESET_PIN, PIN_HIGH); /* Wait at least 500ns after reset */ @@ -150,12 +150,12 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu static uint8_t init_flag = 0; rt_uint8_t temp = 0; rt_uint8_t value = 0; - + /* check if codec is already initialized */ if (init_flag == 0) { audio_dev = rt_i2c_bus_device_find(bus_name); - + if (audio_dev == RT_NULL) { LOG_E("%s bus not found\n", bus_name); @@ -172,7 +172,7 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F); read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E)); - + init_flag = 1; } else @@ -187,7 +187,7 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu /* Power control : Enter standby (PDN = 1) */ read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp); - write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); + write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); } /* Mic Power and Speed Control : Auto detect on, Speed mode SSM, tri state off, MCLK divide by 2 off */ read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp); @@ -204,9 +204,9 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu write_reg(audio_dev, CS42L51_DAC_OUT_CTL, 0xC3); /* DAC control : Signal processing to DAC, Freeze off, De-emphasis off, Analog output auto mute off, DAC soft ramp */ write_reg(audio_dev, CS42L51_DAC_CTL, 0x42); - /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */ + /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */ write_reg(audio_dev, CS42L51_ALC_PGA_CTL, 0xC0); - /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */ + /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */ write_reg(audio_dev, CS42L51_ALC_PGB_CTL, 0xC0); /* ADCA Attenuator : 0dB */ write_reg(audio_dev, CS42L51_ADCA_ATT, 0x00); @@ -229,12 +229,12 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu /* AOUTA volume control : AOUTA volume */ write_reg(audio_dev, CS42L51_AOUTA_VOL, value); /* AOUTB volume control : AOUTB volume */ - write_reg(audio_dev, CS42L51_AOUTB_VOL, value); + write_reg(audio_dev, CS42L51_AOUTB_VOL, value); } - + CS42L51_Device = device; - - return RT_EOK; + + return RT_EOK; } /** @@ -271,7 +271,7 @@ static void cs42l51_deinit(void) } /** - * @brief Verify that we have a CS42L51. + * @brief Verify that we have a CS42L51. * @retval 0 if correct communication, else wrong communication */ @@ -283,20 +283,20 @@ static uint32_t cs42l51_read_id(void) read_reg(audio_dev, CS42L51_CHIP_REV_ID, 1, &temp); if ((temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) && - (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) + (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) { - LOG_E("device id : 0x%02x", temp); - return RT_ERROR; + LOG_E("device id : 0x%02x", temp); + return RT_ERROR; } - - LOG_D("device id : 0x%02x", temp); - + + LOG_D("device id : 0x%02x", temp); + return RT_EOK; } /** * @brief Start the audio Codec play feature. - * @note For this codec no Play options are required. + * @note For this codec no Play options are required. * @retval 0 if correct communication, else wrong communication */ static uint32_t cs42l51_play(void) @@ -316,7 +316,7 @@ static uint32_t cs42l51_play(void) write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F)); break; } - + case IN_LINE1: { /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN1A to PGAA, ADCB invert off, ADCA invert off, ADCB mute off, ADCA mute off */ @@ -326,7 +326,7 @@ static uint32_t cs42l51_play(void) write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F)); break; } - + case IN_MIC1: { /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN3A to PreAmp to PGAA, ADCB invert off, ADCA invert off, ADCB mute on, ADCA mute off */ @@ -339,7 +339,7 @@ static uint32_t cs42l51_play(void) write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF9)); break; } - + case IN_MIC2: { /* Power control 1 : PDN_PGAB, PDN_ADCB disable. */ @@ -350,7 +350,7 @@ static uint32_t cs42l51_play(void) write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF5)); break; } - + default: LOG_D("error audio play mode!"); break; @@ -365,11 +365,11 @@ static uint32_t cs42l51_play(void) /** * @brief Pause playing on the audio codec. - * @param audio_dev: Device address on communication Bus. + * @param audio_dev: Device address on communication Bus. * @retval 0 if correct communication, else wrong communication */ static uint32_t cs42l51_pause(void) -{ +{ /* Pause the audio file playing */ /* Mute the output first */ @@ -379,7 +379,7 @@ static uint32_t cs42l51_pause(void) /** * @brief Resume playing on the audio codec. - * @param audio_dev: Device address on communication Bus. + * @param audio_dev: Device address on communication Bus. * @retval 0 if correct communication, else wrong communication */ static uint32_t cs42l51_resume(void) @@ -423,7 +423,7 @@ static uint32_t cs42l51_set_frequency(uint32_t AudioFreq) } /** - * @brief Set higher or lower the codec volume level. + * @brief Set higher or lower the codec volume level. * @param Volume: output volume level (from 0 (-100dB) to 100 (0dB)). * @retval 0 if correct communication, else wrong communication */ @@ -440,23 +440,23 @@ static uint32_t cs42l51_set_volume(uint8_t Volume) } /** - * @brief get higher or lower the codec volume level. + * @brief get higher or lower the codec volume level. * @retval value if correct communication */ static uint32_t cs42l51_get_volume(void) { rt_uint8_t temp = 0; - + /* AOUTA volume control : AOUTA volume */ read_reg(audio_dev, CS42L51_AOUTA_VOL, 1, &temp); temp = VOLUME_INVERT(temp); - + return temp; } /** -* @brief Enable or disable the mute feature on the audio codec. +* @brief Enable or disable the mute feature on the audio codec. * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the * mute mode. * @retval 0 if correct communication, else wrong communication @@ -464,7 +464,7 @@ static uint32_t cs42l51_get_volume(void) static uint32_t cs42l51_set_mute(uint32_t cmd) { rt_uint8_t temp = 0; - + /* Read DAC output control register */ read_reg(audio_dev, 0x08, 1, &temp); @@ -484,10 +484,10 @@ static uint32_t cs42l51_set_mute(uint32_t cmd) } /** - * @brief Switch dynamically (while audio file is played) the output target + * @brief Switch dynamically (while audio file is played) the output target * (speaker, headphone, etc). * @note This function is currently not used (only headphone output device). - * @param Output: specifies the audio output device target. + * @param Output: specifies the audio output device target. * @retval 0 if correct communication, else wrong communication */ static uint32_t cs42l51_set_output_mode(uint8_t Output) @@ -496,7 +496,7 @@ static uint32_t cs42l51_set_output_mode(uint8_t Output) } /** - * @brief Reset CS42L51 registers. + * @brief Reset CS42L51 registers. * @retval 0 if correct communication, else wrong communication */ static uint32_t cs42l51_reset(void) @@ -508,8 +508,8 @@ static uint32_t cs42l51_reset(void) return RT_EOK; } -/* Audio codec driver structure initialization */ -AUDIO_DrvTypeDef cs42l51_drv = +/* Audio codec driver structure initialization */ +AUDIO_DrvTypeDef cs42l51_drv = { cs42l51_init, cs42l51_deinit, @@ -518,12 +518,12 @@ AUDIO_DrvTypeDef cs42l51_drv = cs42l51_play, cs42l51_pause, cs42l51_resume, - cs42l51_stop, - - cs42l51_set_frequency, + cs42l51_stop, + + cs42l51_set_frequency, cs42l51_set_volume, cs42l51_get_volume, - cs42l51_set_mute, + cs42l51_set_mute, cs42l51_set_output_mode, cs42l51_reset, }; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h index b3d7f78dca..4447418a24 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes @@ -13,7 +13,7 @@ #ifdef __cplusplus extern "C" { #endif - + typedef struct { rt_err_t (*init)(uint16_t , const char *, uint8_t); @@ -34,137 +34,137 @@ typedef struct extern AUDIO_DrvTypeDef cs42l51_drv; /* CS42L51 register space */ -#define CS42L51_CHIP_ID 0x1B -#define CS42L51_CHIP_REV_A 0x00 -#define CS42L51_CHIP_REV_B 0x01 +#define CS42L51_CHIP_ID 0x1B +#define CS42L51_CHIP_REV_A 0x00 +#define CS42L51_CHIP_REV_B 0x01 -#define CS42L51_CHIP_REV_ID 0x01 -#define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b)) +#define CS42L51_CHIP_REV_ID 0x01 +#define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b)) -#define CS42L51_POWER_CTL1 0x02 -#define CS42L51_POWER_CTL1_PDN_DACB (1<<6) -#define CS42L51_POWER_CTL1_PDN_DACA (1<<5) -#define CS42L51_POWER_CTL1_PDN_PGAB (1<<4) -#define CS42L51_POWER_CTL1_PDN_PGAA (1<<3) -#define CS42L51_POWER_CTL1_PDN_ADCB (1<<2) -#define CS42L51_POWER_CTL1_PDN_ADCA (1<<1) -#define CS42L51_POWER_CTL1_PDN (1<<0) +#define CS42L51_POWER_CTL1 0x02 +#define CS42L51_POWER_CTL1_PDN_DACB (1<<6) +#define CS42L51_POWER_CTL1_PDN_DACA (1<<5) +#define CS42L51_POWER_CTL1_PDN_PGAB (1<<4) +#define CS42L51_POWER_CTL1_PDN_PGAA (1<<3) +#define CS42L51_POWER_CTL1_PDN_ADCB (1<<2) +#define CS42L51_POWER_CTL1_PDN_ADCA (1<<1) +#define CS42L51_POWER_CTL1_PDN (1<<0) -#define CS42L51_MIC_POWER_CTL 0x03 -#define CS42L51_MIC_POWER_CTL_AUTO (1<<7) -#define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) -#define CS42L51_QSM_MODE 3 -#define CS42L51_HSM_MODE 2 -#define CS42L51_SSM_MODE 1 -#define CS42L51_DSM_MODE 0 -#define CS42L51_MIC_POWER_CTL_3ST_SP (1<<4) -#define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3) -#define CS42L51_MIC_POWER_CTL_PDN_MICA (1<<2) -#define CS42L51_MIC_POWER_CTL_PDN_BIAS (1<<1) -#define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0) +#define CS42L51_MIC_POWER_CTL 0x03 +#define CS42L51_MIC_POWER_CTL_AUTO (1<<7) +#define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) +#define CS42L51_QSM_MODE 3 +#define CS42L51_HSM_MODE 2 +#define CS42L51_SSM_MODE 1 +#define CS42L51_DSM_MODE 0 +#define CS42L51_MIC_POWER_CTL_3ST_SP (1<<4) +#define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3) +#define CS42L51_MIC_POWER_CTL_PDN_MICA (1<<2) +#define CS42L51_MIC_POWER_CTL_PDN_BIAS (1<<1) +#define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0) -#define CS42L51_INTF_CTL 0x04 -#define CS42L51_INTF_CTL_LOOPBACK (1<<7) -#define CS42L51_INTF_CTL_MASTER (1<<6) -#define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) -#define CS42L51_DAC_DIF_LJ24 0x00 -#define CS42L51_DAC_DIF_I2S 0x01 -#define CS42L51_DAC_DIF_RJ24 0x02 -#define CS42L51_DAC_DIF_RJ20 0x03 -#define CS42L51_DAC_DIF_RJ18 0x04 -#define CS42L51_DAC_DIF_RJ16 0x05 -#define CS42L51_INTF_CTL_ADC_I2S (1<<2) -#define CS42L51_INTF_CTL_DIGMIX (1<<1) -#define CS42L51_INTF_CTL_MICMIX (1<<0) +#define CS42L51_INTF_CTL 0x04 +#define CS42L51_INTF_CTL_LOOPBACK (1<<7) +#define CS42L51_INTF_CTL_MASTER (1<<6) +#define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) +#define CS42L51_DAC_DIF_LJ24 0x00 +#define CS42L51_DAC_DIF_I2S 0x01 +#define CS42L51_DAC_DIF_RJ24 0x02 +#define CS42L51_DAC_DIF_RJ20 0x03 +#define CS42L51_DAC_DIF_RJ18 0x04 +#define CS42L51_DAC_DIF_RJ16 0x05 +#define CS42L51_INTF_CTL_ADC_I2S (1<<2) +#define CS42L51_INTF_CTL_DIGMIX (1<<1) +#define CS42L51_INTF_CTL_MICMIX (1<<0) -#define CS42L51_MIC_CTL 0x05 -#define CS42L51_MIC_CTL_ADC_SNGVOL (1<<7) -#define CS42L51_MIC_CTL_ADCD_DBOOST (1<<6) -#define CS42L51_MIC_CTL_ADCA_DBOOST (1<<5) -#define CS42L51_MIC_CTL_MICBIAS_SEL (1<<4) -#define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) -#define CS42L51_MIC_CTL_MICB_BOOST (1<<1) -#define CS42L51_MIC_CTL_MICA_BOOST (1<<0) +#define CS42L51_MIC_CTL 0x05 +#define CS42L51_MIC_CTL_ADC_SNGVOL (1<<7) +#define CS42L51_MIC_CTL_ADCD_DBOOST (1<<6) +#define CS42L51_MIC_CTL_ADCA_DBOOST (1<<5) +#define CS42L51_MIC_CTL_MICBIAS_SEL (1<<4) +#define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) +#define CS42L51_MIC_CTL_MICB_BOOST (1<<1) +#define CS42L51_MIC_CTL_MICA_BOOST (1<<0) -#define CS42L51_ADC_CTL 0x06 -#define CS42L51_ADC_CTL_ADCB_HPFEN (1<<7) -#define CS42L51_ADC_CTL_ADCB_HPFRZ (1<<6) -#define CS42L51_ADC_CTL_ADCA_HPFEN (1<<5) -#define CS42L51_ADC_CTL_ADCA_HPFRZ (1<<4) -#define CS42L51_ADC_CTL_SOFTB (1<<3) -#define CS42L51_ADC_CTL_ZCROSSB (1<<2) -#define CS42L51_ADC_CTL_SOFTA (1<<1) -#define CS42L51_ADC_CTL_ZCROSSA (1<<0) +#define CS42L51_ADC_CTL 0x06 +#define CS42L51_ADC_CTL_ADCB_HPFEN (1<<7) +#define CS42L51_ADC_CTL_ADCB_HPFRZ (1<<6) +#define CS42L51_ADC_CTL_ADCA_HPFEN (1<<5) +#define CS42L51_ADC_CTL_ADCA_HPFRZ (1<<4) +#define CS42L51_ADC_CTL_SOFTB (1<<3) +#define CS42L51_ADC_CTL_ZCROSSB (1<<2) +#define CS42L51_ADC_CTL_SOFTA (1<<1) +#define CS42L51_ADC_CTL_ZCROSSA (1<<0) -#define CS42L51_ADC_INPUT 0x07 -#define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) -#define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) -#define CS42L51_ADC_INPUT_INV_ADCB (1<<3) -#define CS42L51_ADC_INPUT_INV_ADCA (1<<2) -#define CS42L51_ADC_INPUT_ADCB_MUTE (1<<1) -#define CS42L51_ADC_INPUT_ADCA_MUTE (1<<0) +#define CS42L51_ADC_INPUT 0x07 +#define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) +#define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) +#define CS42L51_ADC_INPUT_INV_ADCB (1<<3) +#define CS42L51_ADC_INPUT_INV_ADCA (1<<2) +#define CS42L51_ADC_INPUT_ADCB_MUTE (1<<1) +#define CS42L51_ADC_INPUT_ADCA_MUTE (1<<0) -#define CS42L51_DAC_OUT_CTL 0x08 -#define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5) -#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL (1<<4) -#define CS42L51_DAC_OUT_CTL_INV_PCMB (1<<3) -#define CS42L51_DAC_OUT_CTL_INV_PCMA (1<<2) -#define CS42L51_DAC_OUT_CTL_DACB_MUTE (1<<1) -#define CS42L51_DAC_OUT_CTL_DACA_MUTE (1<<0) +#define CS42L51_DAC_OUT_CTL 0x08 +#define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5) +#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL (1<<4) +#define CS42L51_DAC_OUT_CTL_INV_PCMB (1<<3) +#define CS42L51_DAC_OUT_CTL_INV_PCMA (1<<2) +#define CS42L51_DAC_OUT_CTL_DACB_MUTE (1<<1) +#define CS42L51_DAC_OUT_CTL_DACA_MUTE (1<<0) -#define CS42L51_DAC_CTL 0x09 -#define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6) -#define CS42L51_DAC_CTL_FREEZE (1<<5) -#define CS42L51_DAC_CTL_DEEMPH (1<<3) -#define CS42L51_DAC_CTL_AMUTE (1<<2) -#define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0) +#define CS42L51_DAC_CTL 0x09 +#define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6) +#define CS42L51_DAC_CTL_FREEZE (1<<5) +#define CS42L51_DAC_CTL_DEEMPH (1<<3) +#define CS42L51_DAC_CTL_AMUTE (1<<2) +#define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0) -#define CS42L51_ALC_PGA_CTL 0x0A -#define CS42L51_ALC_PGB_CTL 0x0B -#define CS42L51_ALC_PGX_ALCX_SRDIS (1<<7) -#define CS42L51_ALC_PGX_ALCX_ZCDIS (1<<6) -#define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0) +#define CS42L51_ALC_PGA_CTL 0x0A +#define CS42L51_ALC_PGB_CTL 0x0B +#define CS42L51_ALC_PGX_ALCX_SRDIS (1<<7) +#define CS42L51_ALC_PGX_ALCX_ZCDIS (1<<6) +#define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0) -#define CS42L51_ADCA_ATT 0x0C -#define CS42L51_ADCB_ATT 0x0D +#define CS42L51_ADCA_ATT 0x0C +#define CS42L51_ADCB_ATT 0x0D -#define CS42L51_ADCA_VOL 0x0E -#define CS42L51_ADCB_VOL 0x0F -#define CS42L51_PCMA_VOL 0x10 -#define CS42L51_PCMB_VOL 0x11 -#define CS42L51_MIX_MUTE_ADCMIX (1<<7) -#define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0) +#define CS42L51_ADCA_VOL 0x0E +#define CS42L51_ADCB_VOL 0x0F +#define CS42L51_PCMA_VOL 0x10 +#define CS42L51_PCMB_VOL 0x11 +#define CS42L51_MIX_MUTE_ADCMIX (1<<7) +#define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0) -#define CS42L51_BEEP_FREQ 0x12 -#define CS42L51_BEEP_VOL 0x13 -#define CS42L51_BEEP_CONF 0x14 +#define CS42L51_BEEP_FREQ 0x12 +#define CS42L51_BEEP_VOL 0x13 +#define CS42L51_BEEP_CONF 0x14 -#define CS42L51_TONE_CTL 0x15 -#define CS42L51_TONE_CTL_TREB(x) (((x)&0xf)<<4) -#define CS42L51_TONE_CTL_BASS(x) (((x)&0xf)<<0) +#define CS42L51_TONE_CTL 0x15 +#define CS42L51_TONE_CTL_TREB(x) (((x)&0xf)<<4) +#define CS42L51_TONE_CTL_BASS(x) (((x)&0xf)<<0) -#define CS42L51_AOUTA_VOL 0x16 -#define CS42L51_AOUTB_VOL 0x17 -#define CS42L51_PCM_MIXER 0x18 -#define CS42L51_LIMIT_THRES_DIS 0x19 -#define CS42L51_LIMIT_REL 0x1A -#define CS42L51_LIMIT_ATT 0x1B -#define CS42L51_ALC_EN 0x1C -#define CS42L51_ALC_REL 0x1D -#define CS42L51_ALC_THRES 0x1E -#define CS42L51_NOISE_CONF 0x1F +#define CS42L51_AOUTA_VOL 0x16 +#define CS42L51_AOUTB_VOL 0x17 +#define CS42L51_PCM_MIXER 0x18 +#define CS42L51_LIMIT_THRES_DIS 0x19 +#define CS42L51_LIMIT_REL 0x1A +#define CS42L51_LIMIT_ATT 0x1B +#define CS42L51_ALC_EN 0x1C +#define CS42L51_ALC_REL 0x1D +#define CS42L51_ALC_THRES 0x1E +#define CS42L51_NOISE_CONF 0x1F -#define CS42L51_STATUS 0x20 -#define CS42L51_STATUS_SP_CLKERR (1<<6) -#define CS42L51_STATUS_SPEA_OVFL (1<<5) -#define CS42L51_STATUS_SPEB_OVFL (1<<4) -#define CS42L51_STATUS_PCMA_OVFL (1<<3) -#define CS42L51_STATUS_PCMB_OVFL (1<<2) -#define CS42L51_STATUS_ADCA_OVFL (1<<1) -#define CS42L51_STATUS_ADCB_OVFL (1<<0) +#define CS42L51_STATUS 0x20 +#define CS42L51_STATUS_SP_CLKERR (1<<6) +#define CS42L51_STATUS_SPEA_OVFL (1<<5) +#define CS42L51_STATUS_SPEB_OVFL (1<<4) +#define CS42L51_STATUS_PCMA_OVFL (1<<3) +#define CS42L51_STATUS_PCMB_OVFL (1<<2) +#define CS42L51_STATUS_ADCA_OVFL (1<<1) +#define CS42L51_STATUS_ADCB_OVFL (1<<0) -#define CS42L51_CHARGE_FREQ 0x21 -#define CS42L51_FIRSTREG 0x01 +#define CS42L51_CHARGE_FREQ 0x21 +#define CS42L51_FIRSTREG 0x01 enum play_type { NONE, @@ -181,12 +181,12 @@ enum play_type { * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using * 32 regs */ -#define CS42L51_LASTREG 0x20 -#define CS42L51_NUMREGS (CS42L51_LASTREG - CS42L51_FIRSTREG + 1) +#define CS42L51_LASTREG 0x20 +#define CS42L51_NUMREGS (CS42L51_LASTREG - CS42L51_FIRSTREG + 1) #define VOLUME_CONVERT(Volume) ((Volume >= 100) ? 0 : ((uint8_t)(((Volume * 2) + 56)))) #define VOLUME_INVERT(Volume) (((Volume) == 0U) ? 100U : ((uint8_t)(((Volume) - 56U) / 2U))) - + /* MUTE commands */ #define AUDIO_MUTE_ON 1 #define AUDIO_MUTE_OFF 0 diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c index 20e98d4826..45b0afe762 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -79,21 +79,21 @@ void SAIB_Init(void) hsai_BlockB2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; hsai_BlockB2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; hsai_BlockB2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - + hsai_BlockB2.SlotInit.FirstBitOffset = 0; hsai_BlockB2.SlotInit.SlotSize = SAI_SLOTSIZE_32B; hsai_BlockB2.SlotInit.SlotNumber = 2; hsai_BlockB2.SlotInit.SlotActive = SAI_SLOTACTIVE_0|SAI_SLOTACTIVE_1; - + /* DeInit SAI PDM input */ HAL_SAI_DeInit(&hsai_BlockB2); - + /* Init SAI PDM input */ if(HAL_OK != HAL_SAI_Init(&hsai_BlockB2)) { Error_Handler(); } - + /* Enable SAI to generate clock used by audio driver */ __HAL_SAI_ENABLE(&hsai_BlockB2); } @@ -299,7 +299,7 @@ static rt_err_t mic_init(struct rt_audio_device *audio) { struct mic_device *mic_dev; RT_ASSERT(audio != RT_NULL); - + mic_dev = (struct mic_device *)audio->parent.user_data; SAIB_Init(); /* set default params */ @@ -312,7 +312,7 @@ static rt_err_t mic_start(struct rt_audio_device *audio, int stream) { struct mic_device *mic_dev; RT_ASSERT(audio != RT_NULL); - + mic_dev = (struct mic_device *)audio->parent.user_data; if (stream == AUDIO_STREAM_RECORD) { @@ -324,7 +324,7 @@ static rt_err_t mic_start(struct rt_audio_device *audio, int stream) } /* supply clk */ HAL_SAI_Transmit(&hsai_BlockA2, (uint8_t *)&zero_frame[0], 2, 0); - + cs42l51_drv.play(); } @@ -358,7 +358,7 @@ int rt_hw_mic_init(void) { rt_err_t result = RT_EOK; struct rt_device *device; - + rt_memset(MIC_RX_FIFO, 0, RX_FIFO_SIZE); mic_dev.rx_fifo = MIC_RX_FIFO; @@ -373,15 +373,15 @@ int rt_hw_mic_init(void) /* register sound device */ mic_dev.audio.ops = &mic_ops; result = rt_audio_register(&mic_dev.audio, "mic0", RT_DEVICE_FLAG_RDONLY, &mic_dev); - + if (result != RT_EOK) { - device = &(mic_dev.audio.parent); + device = &(mic_dev.audio.parent); rt_device_unregister(device); LOG_E("mic device init error!"); return RT_ERROR; } - + return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c index 5d94bfc399..6a057fa72f 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) /* Peripheral clock enable */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; @@ -72,7 +72,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_SAI2_CLK_ENABLE(); - /**SAI2_A_Block_A GPIO Configuration + /**SAI2_A_Block_A GPIO Configuration PE0 ------> SAI2_MCLK_A PI7 ------> SAI2_FS_A PI5 ------> SAI2_SCK_A @@ -106,7 +106,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) hdma_sai2_a.Init.Mode = DMA_CIRCULAR; hdma_sai2_a.Init.Priority = DMA_PRIORITY_HIGH; hdma_sai2_a.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - + HAL_DMA_DeInit(&hdma_sai2_a); if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK) { @@ -117,13 +117,13 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0); HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); } - + if(hsai->Instance==SAI2_Block_B) { /* Peripheral clock enable */ if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2; PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q; @@ -135,9 +135,9 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) } __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_SAI2_CLK_ENABLE(); - - /**SAI2_B_Block_B GPIO Configuration - PF11 ------> SAI2_SD_B + + /**SAI2_B_Block_B GPIO Configuration + PF11 ------> SAI2_SD_B */ GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -148,7 +148,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_RCC_DMAMUX_CLK_ENABLE(); __HAL_RCC_DMA2_CLK_ENABLE(); - + /* Peripheral DMA init*/ hdma_sai2_b.Instance = DMA2_Stream4; hdma_sai2_b.Init.Request = DMA_REQUEST_SAI2_B; @@ -163,7 +163,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) hdma_sai2_b.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; hdma_sai2_b.Init.MemBurst = DMA_MBURST_SINGLE; hdma_sai2_b.Init.PeriphBurst = DMA_PBURST_SINGLE; - __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); + __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); HAL_DMA_DeInit(&hdma_sai2_b); if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK) { @@ -172,7 +172,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b); __HAL_DMA_ENABLE(&hdma_sai2_b); HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 2, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); + HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); } } @@ -182,14 +182,14 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) if(hsai->Instance==SAI2_Block_A) { - /* Peripheral clock disable */ + /* Peripheral clock disable */ __HAL_RCC_SAI2_CLK_DISABLE(); - /**SAI2_A_Block_A GPIO Configuration + /**SAI2_A_Block_A GPIO Configuration PE0 ------> SAI2_MCLK_A PI7 ------> SAI2_FS_A PI5 ------> SAI2_SCK_A - PI6 ------> SAI2_SD_A + PI6 ------> SAI2_SD_A */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0); @@ -198,14 +198,14 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) HAL_DMA_DeInit(hsai->hdmarx); HAL_DMA_DeInit(hsai->hdmatx); } - + if(hsai->Instance==SAI2_Block_B) { /* Peripheral clock disable */ __HAL_RCC_SAI2_CLK_DISABLE(); - /**SAI2_B_Block_B GPIO Configuration - PF11 ------> SAI2_SD_B + /**SAI2_B_Block_B GPIO Configuration + PF11 ------> SAI2_SD_B */ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_11); @@ -241,12 +241,12 @@ static void rt_hw_sai2a_init(void) hsai_BlockA2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; hsai_BlockA2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; hsai_BlockA2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - + hsai_BlockA2.SlotInit.FirstBitOffset = 0; hsai_BlockA2.SlotInit.SlotSize = SAI_SLOTSIZE_32B; hsai_BlockA2.SlotInit.SlotNumber = 2; hsai_BlockA2.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; - + if(HAL_OK != HAL_SAI_Init(&hsai_BlockA2)) { Error_Handler(); @@ -383,7 +383,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap return result; } - + static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) { rt_err_t result = RT_EOK; @@ -403,9 +403,9 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c rt_uint8_t volume = caps->udata.value; cs42l51_drv.set_volume(volume); - + snd_dev->volume = volume; - + LOG_D("set volume %d", volume); break; } @@ -483,16 +483,16 @@ static rt_err_t sound_init(struct rt_audio_device *audio) RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; - cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40); - + cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40); + if (cs42l51_drv.read_id() != RT_EOK) { LOG_E("can't find low level audio device!"); return RT_ERROR; } - + rt_hw_sai2a_init(); - + /* set default params */ SAIA_Frequency_Set(snd_dev->replay_config.samplerate); SAIA_Channels_Set(snd_dev->replay_config.channels); @@ -510,10 +510,10 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream) if (stream == AUDIO_STREAM_REPLAY) { LOG_D("open sound device"); - + cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 60); /* set work mode */ cs42l51_drv.play(); - + if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK) { return RT_ERROR; @@ -589,12 +589,12 @@ int rt_hw_sound_init(void) result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); if (result != RT_EOK) { - device = &(snd_dev.audio.parent); + device = &(snd_dev.audio.parent); rt_device_unregister(device); LOG_E("sound device init error!"); return RT_ERROR; } - + return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c index e3eb609559..439e6352cc 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -77,7 +77,7 @@ static void hw_crc_sample(uint8_t *temp, int size) { struct rt_hwcrypto_ctx *ctx; rt_uint32_t result = 0; - + struct hwcrypto_crc_cfg cfg = { .last_val = 0xFFFFFFFF, @@ -92,9 +92,9 @@ static void hw_crc_sample(uint8_t *temp, int size) result = rt_hwcrypto_crc_update(ctx, temp, size); - rt_kprintf("crc result: %x \n", result); + rt_kprintf("crc result: %x \n", result); - rt_hwcrypto_crc_destroy(ctx); + rt_hwcrypto_crc_destroy(ctx); } #endif @@ -103,19 +103,19 @@ static void hw_hash_sample() { struct rt_hwcrypto_ctx *ctx = RT_NULL; const uint8_t hash_input[] = "RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS)."; - + static uint8_t sha1_output[20]; - static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, + static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, 0x02, 0x1b, 0xa8, 0xbc, 0xa2, 0x2e, 0xa5, 0xb0, 0x62, 0x1b, 0xdf, 0x7f, 0xec}; - + static uint8_t md5_output[16]; - static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, + static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, 0x4c, 0xd6, 0x7d, 0x28, 0xfc, 0xf6, 0xc3, 0xac, 0x8b}; - + static uint8_t sha224_output[28]; - static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, + static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, 0x9f, 0x82, 0x78, 0x7a, 0x46, 0x91, 0xb0, 0xe9, 0x64, 0x89, 0xe6, 0xc3, 0x6b, 0x7e, 0xcf, 0xca, 0x11, 0x42, @@ -130,7 +130,7 @@ static void hw_hash_sample() rt_kprintf("======================== Hash Test start ========================\n"); rt_kprintf("Hash Test string: \n"); dump_hex(hash_input, sizeof(hash_input)); - + /* sh1 test*/ rt_kprintf("\n============ SHA1 Test Start ============\n"); ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA1); @@ -147,7 +147,7 @@ static void hw_hash_sample() rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); /* get sha1 result */ rt_hwcrypto_hash_finish(ctx, sha1_output, rt_strlen((char const *)sha1_output)); - + rt_kprintf("Actual sha1 result:\n"); dump_hex(sha1_output, sizeof(sha1_output)); @@ -162,7 +162,7 @@ static void hw_hash_sample() /* deinit hash*/ rt_hwcrypto_hash_destroy(ctx); rt_kprintf("============ SHA1 Test Over ============\n"); - + /* md5 test*/ rt_kprintf("\n============ MD5 Test Start ============\n"); ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_MD5); @@ -179,7 +179,7 @@ static void hw_hash_sample() rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); /* get md5 result */ rt_hwcrypto_hash_finish(ctx, md5_output, rt_strlen((char const *)md5_output)); - + rt_kprintf("Actual md5 result:\n"); dump_hex(md5_output, sizeof(md5_output)); @@ -194,7 +194,7 @@ static void hw_hash_sample() /* deinit hash*/ rt_hwcrypto_hash_destroy(ctx); rt_kprintf("============ MD5 Test Over ============\n"); - + /* sha224 test */ rt_kprintf("\n============ SHA224 Test Start ============\n"); ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA224); @@ -211,7 +211,7 @@ static void hw_hash_sample() rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input)); /* get sha224 result */ rt_hwcrypto_hash_finish(ctx, sha224_output, rt_strlen((char const *)sha224_output)); - + rt_kprintf("Actual sha224 result:\n"); dump_hex(sha224_output, sizeof(sha224_output)); @@ -234,7 +234,7 @@ static void hw_hash_sample() rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA256); return ; } - + rt_kprintf("Create sha256 type success!\n"); rt_kprintf("Except sha256 result:\n"); dump_hex(sha256_except, sizeof(sha256_except)); @@ -246,7 +246,7 @@ static void hw_hash_sample() rt_kprintf("Actual sha256 result\n"); dump_hex(sha256_output, sizeof(sha256_output)); - + if(rt_memcmp(sha256_output, sha256_except, sizeof(sha256_except)/sizeof(sha256_except[0])) != 0) { rt_kprintf("Hash type sha256 Test error, The actual result is not equal to the except result\n"); @@ -258,7 +258,7 @@ static void hw_hash_sample() /* destory */ rt_hwcrypto_hash_destroy(ctx); rt_kprintf("============ SHA256 Test Over ============\n"); - rt_kprintf("======================== Hash Test over! ========================\n"); + rt_kprintf("======================== Hash Test over! ========================\n"); } #endif @@ -286,29 +286,29 @@ static void hw_cryp_sample() rt_uint8_t buf_in[32]; rt_uint8_t buf_out[32]; int i; - + /* Populating test data */ for (i = 0; i < sizeof(buf_in); i++) { buf_in[i] = i; } - + /* dump primitive data */ rt_kprintf("key : \n"); dump_hex(cryp_key, sizeof(cryp_key)); rt_kprintf("primitive data : \n"); dump_hex(buf_in, sizeof(buf_in)); - + rt_memset(buf_out, 0, sizeof(buf_out)); - + /* encrypt */ hw_aes_cbc(buf_in, buf_out, HWCRYPTO_MODE_ENCRYPT); /* dump encrypt data */ rt_kprintf("AES-enc : \n"); dump_hex(buf_out, sizeof(buf_out)); - + rt_memset(buf_in, 0, sizeof(buf_in)); - + /* decrypt */ hw_aes_cbc(buf_out, buf_in, HWCRYPTO_MODE_DECRYPT); @@ -323,7 +323,7 @@ static int crypto(int argc, char **argv) int result = RT_EOK; static rt_device_t device = RT_NULL; char *result_str; - + if (argc > 1) { if (!strcmp(argv[1], "probe")) @@ -362,7 +362,7 @@ static int crypto(int argc, char **argv) { rt_kprintf("rng - generate digital\n"); } - + #else rt_kprintf("please enable RNG first!\n"); #endif @@ -370,7 +370,7 @@ static int crypto(int argc, char **argv) else if (!strcmp(argv[1], "crc")) { #if defined (BSP_USING_CRC) - int size = 0, i = 0; + int size = 0, i = 0; if (argc > 3) { size = argc - 2; @@ -381,7 +381,7 @@ static int crypto(int argc, char **argv) { data[i] = strtol(argv[2 + i], NULL, 0); } - hw_crc_sample(data, size); + hw_crc_sample(data, size); rt_free(data); } else @@ -402,31 +402,31 @@ static int crypto(int argc, char **argv) #if defined (BSP_USING_HASH) if (argc == 3) { - hw_hash_sample(); + hw_hash_sample(); } else { - rt_kprintf("crypto hash sample - hash use sample\n"); + rt_kprintf("crypto hash sample - hash use sample\n"); } #else - rt_kprintf("please enable CRC first!\n"); -#endif + rt_kprintf("please enable CRC first!\n"); +#endif } else if (!strcmp(argv[1], "cryp")) { #if defined (BSP_USING_CRYP) if (argc == 3) { - hw_cryp_sample(); + hw_cryp_sample(); } else { - rt_kprintf("crypto cryp sample - encrypt and decrypt data sample\n"); + rt_kprintf("crypto cryp sample - encrypt and decrypt data sample\n"); } #else - rt_kprintf("please enable CRYP first!\n"); -#endif - } + rt_kprintf("please enable CRYP first!\n"); +#endif + } else { rt_kprintf("Unknown command. Please enter 'crypto' for help\n"); @@ -443,7 +443,7 @@ static int crypto(int argc, char **argv) rt_kprintf("crypto cryp sample - encrypt and decrypt data\n"); result = -RT_ERROR; } - + return result; } MSH_CMD_EXPORT(crypto, crypto function); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c index b2fbc3561b..229c3e585e 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -156,7 +156,7 @@ static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_v return -RT_ETIMEOUT; } } - + return RT_EOK; } @@ -165,7 +165,7 @@ static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr) uint16_t reg_value = 0; uint32_t status = 0; volatile uint32_t tickstart = 0; - + /* Take care not to alter MDC clock configuration */ status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR; /* Set up a read operation */ @@ -238,10 +238,10 @@ static void HAL_ETH_MspInit(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH; PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4; @@ -250,10 +250,10 @@ static void HAL_ETH_MspInit(void) Error_Handler(); } } - + /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Enable GPIO clocks */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); @@ -263,12 +263,12 @@ static void HAL_ETH_MspInit(void) /* Select RGMII interface mode */ HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII); - + /* Enable Ethernet MAC clock */ __HAL_RCC_ETH1MAC_CLK_ENABLE(); __HAL_RCC_ETH1TX_CLK_ENABLE(); __HAL_RCC_ETH1RX_CLK_ENABLE(); - + /**ETH1 GPIO Configuration PA1 ------> ETH1_RX_CLK PA7 ------> ETH1_RX_CTL @@ -303,12 +303,12 @@ static void HAL_ETH_MspInit(void) HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); /* ETH interrupt Init */ HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00); HAL_NVIC_EnableIRQ(ETH1_IRQn); - + /* Configure PHY_RST (PG0) */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; @@ -326,11 +326,11 @@ static void HAL_ETH_MspInit(void) static rt_err_t rt_stm32_eth_init(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); - + rt_uint32_t status, i; volatile rt_uint32_t tickstart = 0; rt_uint8_t *macAddr = &stm32_eth_device.dev_addr[0]; - + /* Initialize TX descriptor index */ txIndex = 0; /* Initialize RX descriptor index */ @@ -372,30 +372,30 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) ETH->MACA2HR = 0; ETH->MACA3LR = 0; ETH->MACA3HR = 0; - + /* Initialize hash table */ ETH->MACHT0R = 0; ETH->MACHT1R = 0; - + /* Configure the receive filter */ ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC; - + /* Disable flow control */ ETH->MACQ0TXFCR = 0; ETH->MACRXFCR = 0; - + /* Enable the first RX queue */ ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1); - + /* Configure DMA operating mode */ ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0); - + /* Configure system bus mode */ ETH->DMASBMR |= ETH_DMASBMR_AAL; - + /* The DMA takes the descriptor table as contiguous */ ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0); - + /* Configure TX features */ ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1); @@ -427,12 +427,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) rxDmaDesc[i].rdes2 = 0; rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; } - + /* Set Transmit Descriptor List Address Register */ ETH->DMAC0TXDLAR = (uint32_t) &txDmaDesc[0]; /* Length of the transmit descriptor ring */ ETH->DMAC0TXRLR = ETH_TXBUFNB - 1; - + /* Set Receive Descriptor List Address Register */ ETH->DMAC0RXDLAR = (uint32_t) &rxDmaDesc[0]; /* Length of the receive descriptor ring */ @@ -441,24 +441,24 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) /* Prevent interrupts from being generated when the transmit statistic * counters reach half their maximum value */ ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM; - + /* Prevent interrupts from being generated when the receive statistic * counters reach half their maximum value */ ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM; - + /* Disable MAC interrupts */ ETH->MACIER = 0; - + /* Enable the desired DMA interrupts */ ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; - + /* Enable MAC transmission and reception */ ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE; - + /* Enable DMA transmission and reception */ ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST; ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR; - + /* Reset PHY transceiver */ phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR, RTL8211F_BMCR_RESET); status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR); @@ -474,9 +474,9 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) else { status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR); - } + } } - + /* The PHY will generate interrupts when link status changes are detected */ phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_INER, RTL8211F_INER_AN_COMPLETE | RTL8211F_INER_LINK_STATUS); @@ -515,11 +515,11 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) { case NIOCTL_GADDR: /* get mac address */ - if (args) + if (args) { rt_memcpy(args, stm32_eth_device.dev_addr, 6); } - else + else { return -RT_ERROR; } @@ -536,7 +536,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) { uint32_t framelen = 0; struct pbuf *q = RT_NULL; - + /* Copy user data to the transmit buffer */ for (q = p; q != NULL; q = q->next) { @@ -546,12 +546,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) LOG_D("buffer not valid"); return ERR_USE; } - + level = rt_hw_interrupt_disable(); rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len); framelen += q->len; rt_hw_interrupt_enable(level); - + /* Check the frame length */ if (framelen > ETH_TX_BUF_SIZE - 1) { @@ -559,7 +559,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) return ERR_USE; } } - + #ifdef ETH_TX_DUMP rt_kprintf("Tx dump, len= %d\r\n", framelen); dump_hex(txBuffer[txIndex], framelen); @@ -579,7 +579,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) ETH->DMAC0SR = ETH_DMAC0SR_TBU; /* Instruct the DMA to poll the transmit descriptor list */ ETH->DMAC0TXDTPR = 0; - + if (++txIndex > ETH_TXBUFNB - 1) { txIndex = 0; @@ -595,7 +595,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) struct pbuf *p = RT_NULL, *q = RT_NULL; /* The current buffer is available for reading */ - if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) + if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) { /* FD and LD flags should be set */ if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD)) @@ -617,7 +617,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len); framelen += q->len; rt_hw_interrupt_enable(level); - + if (framelen > framelength) { LOG_E("frame len is too long!"); @@ -632,7 +632,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) LOG_D("the received packet contains an error!"); return RT_NULL; } - + } else { @@ -645,7 +645,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex]; /* Give the ownership of the descriptor back to the DMA */ rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; - + #ifdef ETH_RX_DUMP rt_kprintf("Rx dump, len= %d\r\n", framelen); dump_hex(rxBuffer[rxIndex], framelen); @@ -660,14 +660,14 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) /* Instruct the DMA to poll the receive descriptor list */ ETH->DMAC0RXDTPR = 0; } - + return p; } void ETH1_IRQHandler(void) { rt_uint32_t status = 0; - + /* enter interrupt */ rt_interrupt_enter(); /* Read DMA status register */ @@ -683,7 +683,7 @@ void ETH1_IRQHandler(void) { /* Disable RIE interrupt */ ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE; - + rt_event_send(&rx_event, status); } /* ETH DMA Error */ @@ -694,7 +694,7 @@ void ETH1_IRQHandler(void) } /* Clear the interrupt flags */ ETH->DMAC0SR = ETH_DMAC0SR_NIS; - + /* leave interrupt */ rt_interrupt_leave(); @@ -704,19 +704,19 @@ static void phy_linkchange() { rt_uint32_t status = 0; - /* Read status register to acknowledge the interrupt */ + /* Read status register to acknowledge the interrupt */ status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_INSR); - + if (status & (RTL8211F_BMSR_LINK_STATUS | RTL8211F_INSR_AN_COMPLETE)) { - status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR); - status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR); + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR); + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR); if (status & RTL8211F_BMSR_LINK_STATUS) { - LOG_D("link up"); + LOG_D("link up"); - status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR); + status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR); switch (status & RTL8211F_PHYSR_SPEED) { case RTL8211F_PHYSR_SPEED_10MBPS: @@ -725,25 +725,25 @@ static void phy_linkchange() stm32_eth_device.eth_speed |= PHY_10M; } break; - + case RTL8211F_PHYSR_SPEED_100MBPS: { LOG_D("speed: 100M"); stm32_eth_device.eth_speed |= PHY_100M; } break; - + case RTL8211F_PHYSR_SPEED_1000MBPS: { LOG_D("speed: 1000M"); stm32_eth_device.eth_speed |= PHY_1000M; } break; - + /* Unknown speed */ default: rt_kprintf("Invalid speed."); - break; + break; } stm32_eth_device.eth_mode = (status & RTL8211F_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX ; @@ -812,9 +812,9 @@ static void phy_monitor_thread_entry(void *parameter) eth_device_ready(&(stm32_eth_device.parent)); } } - + /* enable DMA interrupts */ - ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; + ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; } } } @@ -823,7 +823,7 @@ static void phy_monitor_thread_entry(void *parameter) static int rt_hw_stm32_eth_init(void) { rt_err_t state = RT_EOK; - + /* OUI 00-80-E1 STMICROELECTRONICS. */ stm32_eth_device.dev_addr[0] = 0x00; stm32_eth_device.dev_addr[1] = 0x80; @@ -845,7 +845,7 @@ static int rt_hw_stm32_eth_init(void) stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO); - + /* register eth device */ state = eth_device_init(&(stm32_eth_device.parent), "e0"); if (RT_EOK == state) diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h index 40d7db8353..a85651be72 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c index d3d118fd9f..caaf002aa9 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ static int exti_sample(void) rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP); rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL); rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE); - + return RT_EOK; } INIT_DEVICE_EXPORT(exti_sample); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c index 82f66e9916..0e479b6ae6 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,9 +28,9 @@ void LPTIM1_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_LPTIM_IRQHandler(&hlptim1); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -41,9 +41,9 @@ void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) { HAL_GPIO_TogglePin(GPIOH, GPIO_PIN_7); } - + /* All level of ITs can interrupt */ - __set_BASEPRI(0U); + __set_BASEPRI(0U); lptim_stop(); rt_kprintf("system returns to normal!\n"); @@ -53,12 +53,12 @@ static int lptim_control(uint8_t pre_value) { if(pre_value > 7) { - pre_value = 7; + pre_value = 7; } hlptim1.Instance->CFGR &= ~(7 << 9); /* clear PRESC[2:0] */ hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0] */ rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value); - + return RT_EOK; } @@ -70,9 +70,9 @@ int lptim_start(void) LOG_D("lptim1 start counting failed!\n"); return -RT_ERROR; } - + LOG_D("lptim1 start counting success!\n"); - + return RT_EOK; } @@ -83,16 +83,16 @@ int lptim_stop(void) LOG_D("lptim1 stop failed!\n"); return -RT_ERROR; } - - LOG_D("lptim1 stop counting success!\n"); - + + LOG_D("lptim1 stop counting success!\n"); + return RT_EOK; } int lptim_init(void) { rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT); - + hlptim1.Instance = LPTIM1; hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8; @@ -110,7 +110,7 @@ int lptim_init(void) return -RT_ERROR; } LOG_D("lptim init success!\n"); - + return RT_EOK; } INIT_DEVICE_EXPORT(lptim_init); @@ -120,7 +120,7 @@ static int lptim_sample(int argc, char *argv[]) if (argc > 1) { if (!strcmp(argv[1], "start")) - { + { lptim_start(); return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c index c5f26596cc..2915d7dcb2 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,12 +29,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8 struct rt_i2c_msg msg[2] = {0, 0}; RT_ASSERT(bus != RT_NULL); - + msg[0].addr = STPMU1_I2C_ADDRESS; /* Slave address */ msg[0].flags = RT_I2C_WR; /* Write flag */ msg[0].buf = ® /* Slave register address */ msg[0].len = 1; /* Number of bytes sent */ - + msg[1].addr = STPMU1_I2C_ADDRESS; msg[1].flags = RT_I2C_RD; msg[1].len = len; @@ -55,7 +55,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint struct rt_i2c_msg msgs; RT_ASSERT(bus != RT_NULL); - + buf[0] = reg; //cmd buf[1] = data; @@ -85,7 +85,7 @@ static rt_err_t stpmu1_read_reg(uint8_t register_id) { Error_Handler(); } - + return result; } @@ -93,7 +93,7 @@ static void stpmu1_write_reg(uint8_t register_id, uint8_t value) { uint32_t status = RT_EOK; uint8_t readval = 0; - + status = write_reg(pmic_dev, register_id, (rt_uint8_t)value); /* Check the communication status */ @@ -120,7 +120,7 @@ static uint32_t BSP_PMIC_MspInit(void) __HAL_RCC_GPIOA_CLK_ENABLE(); GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = 0 ; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -619,7 +619,7 @@ static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t miliv uint8_t i; for ( i = 0 ; i < regul->voltage_table_size ; i++) { - if ( regul->voltage_table[i] == milivolts ) + if ( regul->voltage_table[i] == milivolts ) { LOG_D("idx:%d for %dmV\n\r", (int)i, (int)milivolts); return i; @@ -716,7 +716,7 @@ void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn) LOG_I(" Interrupt received\n\r"); } -void STPMU1_INTn_Callback(PMIC_IRQn IRQn) +void STPMU1_INTn_Callback(PMIC_IRQn IRQn) { BSP_PMIC_INTn_Callback(IRQn); } @@ -846,15 +846,15 @@ static rt_err_t rt_hw_pmic_init_register(void) static rt_err_t rt_hw_pmic_init(const char *bus_name) { PMIC_IRQn irq; - + pmic_dev = rt_i2c_bus_device_find(bus_name); - + if (pmic_dev == RT_NULL) { LOG_E("%s bus not found\n", bus_name); return -RT_ERROR; } - + if (stpmu1_read_reg(VERSION_STATUS_REG) != PMIC_VERSION_ID) { return -RT_EIO; @@ -863,7 +863,7 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name) STPMU1_Enable_Interrupt(IT_PONKEY_R); STPMU1_Enable_Interrupt(IT_PONKEY_F); /* enable all irqs */ - for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) + for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) { STPMU1_Enable_Interrupt(irq); } @@ -874,18 +874,18 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name) static rt_err_t rt_hw_pmic_deinit(void) { BSP_PMIC_MspDeInit(); - + return RT_EOK; } static int pmic_init(void) { rt_err_t result = RT_EOK; - + if (IS_ENGINEERING_BOOT_MODE()) { BSP_PMIC_MspInit(); - + result = rt_hw_pmic_init(I2C_NAME); if(result != RT_EOK) { @@ -893,16 +893,16 @@ static int pmic_init(void) rt_hw_pmic_deinit(); return RT_ERROR; } - + rt_hw_pmic_init_register(); - + __HAL_RCC_VREF_CLK_ENABLE(); HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE); HAL_SYSCFG_EnableVREFBUF(); } LOG_I("stpmic init success!"); - + return RT_EOK; } INIT_PREV_EXPORT(pmic_init); @@ -910,12 +910,12 @@ INIT_PREV_EXPORT(pmic_init); static int i2c_sample(int argc, char *argv[]) { rt_uint8_t id = 0; - + if (argc > 1) { if (!rt_strcmp(argv[1], "read")) - { - rt_kprintf("i2c read pmic version id\n"); + { + rt_kprintf("i2c read pmic version id\n"); id = stpmu1_read_reg(VERSION_STATUS_REG); rt_kprintf("version id : 0x%02x\n", id); return RT_EOK; @@ -930,7 +930,7 @@ _exit: rt_kprintf("Usage:\n"); rt_kprintf("i2c_sample read - read pmic verison id\n"); } - + return RT_ERROR; } MSH_CMD_EXPORT(i2c_sample, i2c sample); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h index b24ccaeaf3..72c4af3a49 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -98,7 +98,7 @@ typedef struct { /* Those define should reflect NVM_USER section * For ES Eval Configuration this is specified as - * 0xF7, + * 0xF7, 0x92, 0xC0, 0x02, @@ -146,12 +146,12 @@ typedef struct { * */ -#define OTP_VINOK_HYST ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) // nvm_vinok_hyst -#define OTP_VINOK ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) // nvm_vinok -#define OTP_LDO4_FORCED ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) // Otp_ldo4_forced -#define OTP_LONGKEYPRESSED ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2) // nvm_longkeypress -#define OTP_AUTOTURNON ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1) // nvm_autoturnon -#define OTP_CC_KEEPOFF ((NVM_SECTOR3_REGISTER_0 & 0x01)) // nvm_cc_keepoff +#define OTP_VINOK_HYST ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) // nvm_vinok_hyst +#define OTP_VINOK ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) // nvm_vinok +#define OTP_LDO4_FORCED ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) // Otp_ldo4_forced +#define OTP_LONGKEYPRESSED ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2) // nvm_longkeypress +#define OTP_AUTOTURNON ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1) // nvm_autoturnon +#define OTP_CC_KEEPOFF ((NVM_SECTOR3_REGISTER_0 & 0x01)) // nvm_cc_keepoff /* * nvm_rank_buck4: @@ -176,10 +176,10 @@ typedef struct { 11: rank3 * */ -#define OTP_RANK_BUCK4 ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) // nvm_rank_buck4 -#define OTP_RANK_BUCK3 ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) // nvm_rank_buck3 -#define OTP_RANK_BUCK2 ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) // nvm_rank_buck2 -#define OTP_RANK_BUCK1 ((NVM_SECTOR3_REGISTER_1 & 0x03)) // nvm_rank_buck1 +#define OTP_RANK_BUCK4 ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) // nvm_rank_buck4 +#define OTP_RANK_BUCK3 ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) // nvm_rank_buck3 +#define OTP_RANK_BUCK2 ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) // nvm_rank_buck2 +#define OTP_RANK_BUCK1 ((NVM_SECTOR3_REGISTER_1 & 0x03)) // nvm_rank_buck1 /* @@ -205,10 +205,10 @@ typedef struct { 11: rank3 * */ -#define OTP_RANK_LDO4 ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) // nvm_rank_ldo4 -#define OTP_RANK_LDO3 ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) // nvm_rank_ldo3 -#define OTP_RANK_LDO2 ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) // nvm_rank_ldo2 -#define OTP_RANK_LDO1 ((NVM_SECTOR3_REGISTER_2 & 0x03)) // nvm_rank_ldo1 +#define OTP_RANK_LDO4 ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) // nvm_rank_ldo4 +#define OTP_RANK_LDO3 ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) // nvm_rank_ldo3 +#define OTP_RANK_LDO2 ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) // nvm_rank_ldo2 +#define OTP_RANK_LDO1 ((NVM_SECTOR3_REGISTER_2 & 0x03)) // nvm_rank_ldo1 /* * nvm_clamp_output_buck: Clamp output value to 1.3V max @@ -238,11 +238,11 @@ nvm_rank_ldo5: 11: rank3 * */ -#define OTP_CLAMP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) // nvm_clamp_output_buck4 -#define OTP_BYPASS_MODE_LDO3 ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) // nvm_bypass_mode_ldo3 -#define OTP_RANK_VREFDDR ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) // nvm_rank_vrefddr -#define OTP_RANK_LDO6 ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) // nvm_rank_ldo6 -#define OTP_RANK_LDO5 ((NVM_SECTOR3_REGISTER_3 & 0x03)) // nvm_rank_ldo5 +#define OTP_CLAMP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) // nvm_clamp_output_buck4 +#define OTP_BYPASS_MODE_LDO3 ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) // nvm_bypass_mode_ldo3 +#define OTP_RANK_VREFDDR ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) // nvm_rank_vrefddr +#define OTP_RANK_LDO6 ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) // nvm_rank_ldo6 +#define OTP_RANK_LDO5 ((NVM_SECTOR3_REGISTER_3 & 0x03)) // nvm_rank_ldo5 /* * nvm_output_buck4: Buck4 default output selection @@ -267,31 +267,31 @@ nvm_rank_ldo5: 11: 1.25V * */ -#define OTP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) // nvm_output_buck4 -#define OTP_OUTPUT_BUCK3 ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) // nvm_output_buck3 -#define OTP_OUTPUT_BUCK2 ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) // nvm_output_buck2 -#define OTP_OUTPUT_BUCK1 ((NVM_SECTOR3_REGISTER_4 & 0x03)) // nvm_output_buck1 +#define OTP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) // nvm_output_buck4 +#define OTP_OUTPUT_BUCK3 ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) // nvm_output_buck3 +#define OTP_OUTPUT_BUCK2 ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) // nvm_output_buck2 +#define OTP_OUTPUT_BUCK1 ((NVM_SECTOR3_REGISTER_4 & 0x03)) // nvm_output_buck1 /* - * [7] OTP_SWOFF_BY_BOOST_OVP: + * [7] OTP_SWOFF_BY_BOOST_OVP: 0 -> SWOUT will not turnoff bu boost OVP 1 -> SWOUT will be turnoff by BOOST OVP - [6] reserved + [6] reserved - [5:4] nvm_output_ldo3: LDO3 default output selection + [5:4] nvm_output_ldo3: LDO3 default output selection 00: 1.8V 01: 2.5V 10: 3.3V 11: output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog) - [3:2] nvm_output_ldo2: LDO2 default output selection + [3:2] nvm_output_ldo2: LDO2 default output selection 00: 1.8V 01: 2.5V 10: 2.9V 11: 3.3V - [1:0] nvm_output_ldo1: LDO1 default output selection + [1:0] nvm_output_ldo1: LDO1 default output selection 00: 1.8V 01: 2.5V 10: 2.9V @@ -299,21 +299,21 @@ nvm_rank_ldo5: * */ -#define OTP_SWOFF_BY_BOOST_OVP ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) // OTP_SWOFF_BY_BOOST_OVP -#define OTP_OUTPUT_LDO3 ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) // nvm_output_ldo3 -#define OTP_OUTPUT_LDO2 ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) // nvm_output_ldo2 -#define OTP_OUTPUT_LDO1 ((NVM_SECTOR3_REGISTER_5 & 0x03)) // nvm_output_ldo1 +#define OTP_SWOFF_BY_BOOST_OVP ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) // OTP_SWOFF_BY_BOOST_OVP +#define OTP_OUTPUT_LDO3 ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) // nvm_output_ldo3 +#define OTP_OUTPUT_LDO2 ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) // nvm_output_ldo2 +#define OTP_OUTPUT_LDO1 ((NVM_SECTOR3_REGISTER_5 & 0x03)) // nvm_output_ldo1 /* - * [7:4] reserved + * [7:4] reserved * - [3:2] nvm_output_ldo6: LDO6 default output selection + [3:2] nvm_output_ldo6: LDO6 default output selection 00: 1.0V 01: 1.2V 10: 1.8V 11: 3.3V - [1:0] nvm_output_ldo5: LDO5 default output selection + [1:0] nvm_output_ldo5: LDO5 default output selection 00: 1.8V 01: 2.5V 10: 2.9V @@ -321,8 +321,8 @@ nvm_rank_ldo5: * */ -#define OTP_OUTPUT_LDO6 ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) // nvm_output_ldo6 -#define OTP_OUTPUT_LDO5 ((NVM_SECTOR3_REGISTER_6 & 0x03)) // nvm_output_ldo5 +#define OTP_OUTPUT_LDO6 ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) // nvm_output_ldo6 +#define OTP_OUTPUT_LDO5 ((NVM_SECTOR3_REGISTER_6 & 0x03)) // nvm_output_ldo5 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define BIT(_x) (1<<(_x)) @@ -417,7 +417,7 @@ nvm_rank_ldo5: #define LDO_BUCK_PULL_DOWN_MASK 0x03 -/* Main PMIC Control Register +/* Main PMIC Control Register * MAIN_CONTROL_REG * Address : 0x10 * */ @@ -427,7 +427,7 @@ nvm_rank_ldo5: #define RESTART_REQUEST_ENABLED BIT(1) #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) -/* Main PMIC PADS Control Register +/* Main PMIC PADS Control Register * PADS_PULL_REG * Address : 0x11 * */ @@ -438,7 +438,7 @@ nvm_rank_ldo5: #define PONKEY_PU_ACTIVE BIT(0) -/* Main PMIC VINLOW Control Register +/* Main PMIC VINLOW Control Register * VIN_CONTROL_REGC DMSC * Address : 0x15 * */ @@ -452,7 +452,7 @@ nvm_rank_ldo5: #define VINLOW_CTRL_REG_MASK 0xFF -/* USB Control Register +/* USB Control Register * Address : 0x40 * */ #define BOOST_OVP_DISABLED BIT(7) diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c index 3aac57603d..a98b280f1b 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c index 8c6f45ad91..442bc14d9c 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ static int rcc_sample(int argc, char *argv[]) if (argc > 1) { if (!strcmp(argv[1], "enable")) - { + { enable_clock(); return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c index 44eba3be91..78475ec7e8 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ static rt_err_t rs485_output(rt_device_t dev, void * buffer) static rt_err_t rs485_input(rt_device_t dev, rt_size_t size) { rt_sem_release(&rx_sem); - + return RT_EOK; } @@ -38,13 +38,13 @@ int rs485_send_data(char *tbuf, rt_uint16_t t_len) { /* change rs485 mode */ RS485_OUT; - + /* send data */ rt_device_write(serial, 0, tbuf, t_len); - + /* change rs485 mode */ RS485_IN; - + return RT_EOK; } @@ -59,10 +59,10 @@ static void rs485_thread_entry(void *parameter) { rt_sem_take(&rx_sem, RT_WAITING_FOREVER); } - + /* The data read through the serial port output dislocation */ ch = ch + 1; - + /* send char */ rs485_send_data(&ch, 1); } @@ -77,20 +77,20 @@ static int rs485_init(void) { rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME); return RT_ERROR; - } + } rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); /* set receive data callback function */ rt_device_set_rx_indicate(serial, rs485_input); - + /* set the send completion callback function */ rt_device_set_tx_complete(serial, rs485_output); - + rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT); - + RS485_IN; - + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); /* create rs485 thread */ rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10); @@ -103,8 +103,8 @@ static int rs485_init(void) { return RT_ERROR; } - - return RT_EOK; + + return RT_EOK; } INIT_DEVICE_EXPORT(rs485_init); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h index 01edf84ae8..0d9767ac04 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ extern "C" { #define RS485_SEND_MODE 0 #define RS485_RECV_MODE 1 - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c index 45de04328f..df1ca92691 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -60,7 +60,7 @@ __attribute__((at(SDCARD_ADDR))) static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; #elif defined ( __GNUC__ ) static rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection"))); #elif defined(__ICCARM__) -#pragma location = SDCARD_ADDR +#pragma location = SDCARD_ADDR __no_init static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; #endif @@ -151,7 +151,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) { return; } - + cmd->resp[0] = hw_sdio->resp1; cmd->resp[1] = hw_sdio->resp2; cmd->resp[2] = hw_sdio->resp3; @@ -167,22 +167,22 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) { cmd->err = -RT_ERROR; } - + if (status & SDMMC_STA_CTIMEOUT) { cmd->err = -RT_ETIMEOUT; } - + if (status & SDMMC_STA_DCRCFAIL) { data->err = -RT_ERROR; } - + if (status & SDMMC_STA_DTIMEOUT) { data->err = -RT_ETIMEOUT; } - + if (cmd->err == RT_EOK) { LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); @@ -205,7 +205,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) data ? data->blksize : 0 ); } - + } else { @@ -226,7 +226,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) struct rt_mmcsd_data *data = cmd->data; struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; rt_uint32_t reg_cmd; - + sdio->pkg = pkg; LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n", @@ -254,9 +254,9 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) reg_cmd |= SDMMC_RESPONSE_LONG; else reg_cmd |= SDMMC_RESPONSE_SHORT; - + hw_sdio->mask |= SDIO_MASKR_ALL; - + /* data pre configuration */ if (data != RT_NULL) { @@ -292,7 +292,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) /* close irq, keep sdio irq */ hw_sdio->mask = hw_sdio->mask & SDMMC_IT_SDIOIT ? SDMMC_IT_SDIOIT : 0x00; - + /* data post configuration */ if (data != RT_NULL) { @@ -316,7 +316,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r struct rt_mmcsd_data *data; RTHW_SDIO_LOCK(sdio); - + if (req->cmd != RT_NULL) { rt_memset(&pkg, 0, sizeof(pkg)); @@ -346,7 +346,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r } RTHW_SDIO_UNLOCK(sdio); - + mmcsd_req_complete(sdio->host); } @@ -392,7 +392,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg * ); RTHW_SDIO_LOCK(sdio); - + clk_src = SDIO_CLOCK_FREQ; if (clk > 0) @@ -425,7 +425,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg * if (io_cfg->power_mode == MMCSD_POWER_ON) hw_sdio->power |= SDMMC_POWER_PWRCTRL; - + RTHW_SDIO_UNLOCK(sdio); } @@ -513,7 +513,7 @@ err: { rt_free(sdio); } - + return RT_NULL; } @@ -522,7 +522,7 @@ void SDMMC1_IRQHandler(void) rt_interrupt_enter(); /* Process All SDIO Interrupt Sources */ rthw_sdio_irq_process(host1); - + rt_interrupt_leave(); } @@ -577,7 +577,7 @@ int rt_hw_sdio_init(void) return RT_NULL; } #endif - + #ifdef BSP_USING_SDIO2 MX_RTC_Init(); LBEE5KL1DX_init(); @@ -591,7 +591,7 @@ int rt_hw_sdio_init(void) { LOG_E("host2 create fail"); return RT_NULL; - } + } #endif return RT_EOK; } @@ -601,7 +601,7 @@ INIT_DEVICE_EXPORT(rt_hw_sdio_init); int mnt_init(void) { rt_device_t sd = RT_NULL; - + rt_thread_delay(RT_TICK_PER_SECOND); sd = rt_device_find("sd0"); @@ -610,7 +610,7 @@ int mnt_init(void) rt_kprintf("can't find sd0 device!\n"); return RT_ERROR; } - + if (dfs_mount("sd0", "/", "elm", 0, 0) != 0) { rt_kprintf("file system mount failed!\n"); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h index da70bf1257..9383e812e4 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -90,7 +90,7 @@ struct stm32_sdio volatile rt_uint32_t idmalar; volatile rt_uint32_t idmabar; volatile rt_uint32_t reserved2[5]; - volatile rt_uint32_t fifo; + volatile rt_uint32_t fifo; volatile rt_uint32_t reserved3[220]; volatile rt_uint32_t verr; volatile rt_uint32_t ipidr; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c index 4e9910aa95..77bde7d7b7 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,15 +22,15 @@ #define LED5_PIN GET_PIN(A, 14) static rt_uint8_t feed_flag = 0; -static WWDG_HandleTypeDef hwwdg1; +static WWDG_HandleTypeDef hwwdg1; void WWDG1_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_WWDG_IRQHandler(&hwwdg1); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -50,18 +50,18 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) static void wwdg_init() { rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT); - + hwwdg1.Instance = WWDG1; hwwdg1.Init.Prescaler = WWDG_PRESCALER_8; hwwdg1.Init.Window = 0X5F; hwwdg1.Init.Counter = 0x7F; hwwdg1.Init.EWIMode = WWDG_EWI_ENABLE; - + if (HAL_WWDG_Init(&hwwdg1) != HAL_OK) { Error_Handler(); } - + feed_flag = 1; } @@ -69,10 +69,10 @@ static void wwdg_control(uint8_t pre_value) { if(pre_value > 7) { - pre_value = 7; + pre_value = 7; } hwwdg1.Instance->CFR &= ~(7 << 11); /* clear WDGTB[2:0] */ - hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */ + hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */ } static void wwdg_stop(void) @@ -85,7 +85,7 @@ static int wwdg_sample(int argc, char *argv[]) if (argc > 1) { if (!strcmp(argv[1], "run")) - { + { wwdg_init(); } else if (!strcmp(argv[1], "set")) @@ -93,7 +93,7 @@ static int wwdg_sample(int argc, char *argv[]) if (argc > 2) { wwdg_control(atoi(argv[2])); - } + } } else if (!strcmp(argv[1], "stop")) { diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c index 1a4c91ac24..36a441d62f 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,15 +28,15 @@ static int rt_spi_device_init(void) cfg.max_hz = 1 *1000 *1000; spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME); - + if (RT_NULL == spi_dev) { rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME); return RT_ERROR; } - + rt_spi_configure(spi_dev, &cfg); - + return RT_EOK; } INIT_APP_EXPORT(rt_spi_device_init); @@ -44,22 +44,22 @@ INIT_APP_EXPORT(rt_spi_device_init); /* spi5 loopback mode test case */ static int spi_sample(int argc, char **argv) { - rt_uint8_t t_buf[8], r_buf[8]; - int i = 0; + rt_uint8_t t_buf[8], r_buf[8]; + int i = 0; static struct rt_spi_message msg1; - + if (argc != 9) { rt_kprintf("Usage:\n"); rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n"); return -RT_ERROR; } - + for (i = 0; i < 8; i++) { t_buf[i] = atoi(argv[i+1]); } - + msg1.send_buf = &t_buf; msg1.recv_buf = &r_buf; msg1.length = sizeof(t_buf); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c index fdbc721c8d..0f4df63bd3 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,11 +26,11 @@ static rt_adc_device_t adc_dev = RT_NULL; static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { rt_uint32_t value = 0 , vol = 0; - + /* read adc value */ value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); rt_kprintf("the value is :%d \n", value); - + vol = value * REFER_VOLTAGE / CONVERT_BITS; rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); @@ -55,21 +55,21 @@ static int hwtimer_stop(void) rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME); return ret; } - + /* close adc channel */ ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); - + return ret; } static int hwtimer_start(void) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_hwtimerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - + rt_hwtimer_mode_t mode; - + hw_dev = rt_device_find(HWTIMER_DEV_NAME); if (hw_dev == RT_NULL) { @@ -84,7 +84,7 @@ static int hwtimer_start(void) rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); return RT_ERROR; } - + /* Open the device in read/write mode */ ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) @@ -118,10 +118,10 @@ static int hwtimer_start(void) rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); - + /* enable adc channel */ ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); - + return ret; } @@ -130,8 +130,8 @@ static int tim_sample(int argc, char *argv[]) if (argc > 1) { if (!rt_strcmp(argv[1], "start")) - { - rt_kprintf("tim14 will start\n"); + { + rt_kprintf("tim14 will start\n"); hwtimer_start(); return RT_EOK; } @@ -152,7 +152,7 @@ _exit: rt_kprintf("tim_sample start - start TIM14 \n"); rt_kprintf("tim_sample stop - stop TIM14 \n"); } - + return RT_ERROR; } MSH_CMD_EXPORT(tim_sample, tim sample); diff --git a/bsp/stm32/stm32mp157a-st-ev1/.config b/bsp/stm32/stm32mp157a-st-ev1/.config index 8886fca66a..bd24db0d5a 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/.config +++ b/bsp/stm32/stm32mp157a-st-ev1/.config @@ -55,6 +55,8 @@ CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y # @@ -123,6 +125,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -151,9 +154,9 @@ CONFIG_RT_USING_PIN=y # # POSIX layer and C standard library # -CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_USING_TIME=y # # Network @@ -199,12 +202,15 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -231,6 +237,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -243,7 +250,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -255,8 +262,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -265,6 +270,14 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set # # security packages @@ -273,6 +286,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -289,6 +303,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -300,13 +317,31 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set # CONFIG_PKG_USING_NR_MICRO_SHELL is not set # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages @@ -318,18 +353,43 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -338,6 +398,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -367,6 +428,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -374,6 +436,37 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set # # miscellaneous packages @@ -383,6 +476,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -403,13 +497,23 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32MP1=y @@ -422,28 +526,45 @@ CONFIG_SOC_STM32MP157A=y # Onboard Peripheral Drivers # CONFIG_BSP_USING_STLINK_TO_USART=y +# CONFIG_BSP_USING_EXTI is not set # CONFIG_BSP_USING_PMIC is not set +# CONFIG_BSP_USING_PWR is not set # CONFIG_BSP_USING_NAND is not set +# CONFIG_BSP_USING_QSPI_FLASH is not set # CONFIG_BSP_USING_OPENAMP is not set +# CONFIG_BSP_USING_GBE is not set +# CONFIG_BSP_USING_SDMMC is not set +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_DCMI is not set +# CONFIG_BSP_USING_MFX is not set +# CONFIG_BSP_USING_RS485 is not set # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_WWDG is not set +# CONFIG_BSP_USING_DMA is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_SPDIFRX is not set +# CONFIG_BSP_USING_DFSDM is not set CONFIG_BSP_USING_UART=y # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_UART3_RX_USING_DMA is not set CONFIG_BSP_USING_UART4=y # CONFIG_BSP_UART4_RX_USING_DMA is not set # CONFIG_BSP_UART4_TX_USING_DMA is not set # CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_LPTIM is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_FDCAN is not set # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_HASH is not set +# CONFIG_BSP_USING_CRYP is not set # CONFIG_BSP_USING_UDID is not set # diff --git a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c index b38732f066..6e70b83927 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c +++ b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,19 +15,19 @@ /* defined the LD4 pin: PD8 */ #define LED4_PIN GET_PIN(D, 8) -int main(void) +int main(void) { int count = 1; /* set LD8 pin mode to output */ rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); - + while (count++) { rt_pin_write(LED4_PIN, PIN_HIGH); - rt_thread_mdelay(500); + rt_thread_mdelay(500); rt_pin_write(LED4_PIN, PIN_LOW); rt_thread_mdelay(500); } - + return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.c b/bsp/stm32/stm32mp157a-st-ev1/board/board.c index 362250de22..52475b9240 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/board.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2006-2018, RT-Thread Development Team +* Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,13 +21,13 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - + /**Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); - - /**Initializes the CPU, AHB and APB busses clocks + + /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -36,7 +36,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = 16; RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1; - + /**PLL1 Config */ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -50,7 +50,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL; RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + /**PLL2 Config */ RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; @@ -64,7 +64,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL; RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + /**PLL3 Config */ RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; @@ -79,7 +79,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL; RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + /**PLL4 Config */ RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON; @@ -94,7 +94,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER; RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; - + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -116,16 +116,16 @@ void SystemClock_Config(void) RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2; RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2; RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2; - + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { Error_Handler(); } - + /**Set the HSE division factor for RTC clock */ __HAL_RCC_RTC_HSEDIV(24); - + /* Configure the peripherals common clocks */ if(IS_ENGINEERING_BOOT_MODE()) { @@ -140,7 +140,7 @@ void SystemClock_Config(void) */ void PeriphCommonClock_Config(void) { RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + /** Initializes the common periph clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER; @@ -152,11 +152,11 @@ void PeriphCommonClock_Config(void) { extern void rt_hw_systick_init(void); extern int rt_hw_usart_init(void); -void rt_hw_board_init() +void rt_hw_board_init() { /* HAL_Init() function is called at the beginning of the program */ HAL_Init(); - + /* enable interrupt */ __set_PRIMASK(0); /* Configure the system clock */ @@ -166,29 +166,29 @@ void rt_hw_board_init() } /* disable interrupt */ __set_PRIMASK(1); - + rt_hw_systick_init(); - + /* Heap initialization */ #if defined(RT_USING_HEAP) rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif - + /* Pin driver initialization is open by default */ #ifdef RT_USING_PIN rt_hw_pin_init(); #endif - + /* USART driver initialization is open by default */ #ifdef RT_USING_SERIAL rt_hw_usart_init(); #endif - + /* Set the shell console output device */ #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - + /* Board underlying hardware initialization */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.h b/bsp/stm32/stm32mp157a-st-ev1/board/board.h index 334eea4f5c..0406e49952 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/board.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,13 +22,13 @@ extern "C" { #endif -#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) +#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) #define STM32_FLASH_SIZE (192 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) #define STM32_SRAM_SIZE (64) -#define STM32_SRAM_END (0x10030000 + 64 * 1024) +#define STM32_SRAM_END (0x10030000 + 64 * 1024) #if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c index 12651efa1a..cee0c38d79 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ static VIRT_UART_HandleTypeDef huart0; static rt_uint8_t rx_buffer[MAX_BUFFER_SIZE]; static rt_uint8_t tx_buffer[MAX_BUFFER_SIZE]; - + struct rthw_openamp { struct rt_device parent; @@ -36,41 +36,41 @@ struct rthw_openamp }; static struct rthw_openamp dev_openamp; -void IPCC_RX1_IRQHandler(void) +void IPCC_RX1_IRQHandler(void) { rt_interrupt_enter(); - + HAL_IPCC_RX_IRQHandler(&hipcc); - + rt_interrupt_leave(); } void IPCC_TX1_IRQHandler(void) { rt_interrupt_enter(); - + HAL_IPCC_TX_IRQHandler(&hipcc); - + rt_interrupt_leave(); } -void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) -{ +void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) +{ rt_uint16_t rx_size = 0, i = 0; rt_size_t count, size, offset; rt_uint8_t *buf = RT_NULL; - + struct rthw_openamp *device; device = (struct rthw_openamp *)rt_device_find("openamp"); RT_ASSERT(device != RT_NULL); - - buf = device->serial.rbuf; + + buf = device->serial.rbuf; count = device->serial.rbuf_count; size = device->serial.rbuf_size; offset = device->serial.rbuf_start + count; - + rt_sem_take(&device->sema, RT_WAITING_FOREVER); - + rx_size = (huart->RxXferSize < MAX_BUFFER_SIZE) ? huart->RxXferSize : MAX_BUFFER_SIZE - 1; if (count < size) @@ -79,7 +79,7 @@ void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) { offset -= size; } - + for (i = 0; i < rx_size; i++) { buf[offset++] = huart->pRxBuffPtr[i]; @@ -88,16 +88,16 @@ void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) } device->serial.rbuf_count = count; - + rt_sem_release(&device->sema); } - + static rt_err_t _init(struct rt_device *dev) { struct rthw_openamp *device; device = (struct rthw_openamp *)dev; RT_ASSERT(device != RT_NULL); - + device->serial.rbuf_start = 0; device->serial.rbuf_count = 0; device->serial.tbuf_start = 0; @@ -106,79 +106,79 @@ static rt_err_t _init(struct rt_device *dev) device->serial.tbuf_size = MAX_BUFFER_SIZE; device->serial.rbuf = rx_buffer; device->serial.tbuf = tx_buffer; - + if (rt_sem_init(&device->sema, "openamplock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) { return RT_ERROR; } - + return RT_EOK; } static rt_size_t _read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size) { rt_size_t count, rbsize, offset; - rt_uint8_t *buf = RT_NULL; + rt_uint8_t *buf = RT_NULL; rt_uint8_t *pBuffer = RT_NULL; rt_uint16_t i = 0; - + struct rthw_openamp *device; device = (struct rthw_openamp *)dev; RT_ASSERT(device != RT_NULL); - + pBuffer = (unsigned char*)buffer; count = device->serial.rbuf_count; buf = device->serial.rbuf; - + if (count == 0) { return -RT_ERROR; } - + rt_sem_take(&device->sema, RT_WAITING_FOREVER); - + if (count >= size) { count = size; - } + } offset = device->serial.rbuf_start; rbsize = device->serial.rbuf_size; - + for (i = 0; i < count; i++) { *pBuffer++ = buf[offset++]; if (offset > rbsize) { - offset = 0; + offset = 0; } } device->serial.rbuf_start = offset; device->serial.rbuf_count -= count; - + rt_sem_release(&device->sema); - + return count; } - + static rt_size_t _write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size) { rt_err_t result = VIRT_UART_OK; - + struct rthw_openamp *device; device = (struct rthw_openamp *)dev; RT_ASSERT(device != RT_NULL); - + rt_sem_take(&device->sema, RT_WAITING_FOREVER); - result = VIRT_UART_Transmit(&huart0, (uint8_t *)buffer, size); + result = VIRT_UART_Transmit(&huart0, (uint8_t *)buffer, size); rt_sem_release(&device->sema); - + if (result != VIRT_UART_OK) { return -RT_ERROR; } - + return size; } @@ -206,7 +206,7 @@ static rt_err_t rt_hw_openamp_register(struct rthw_openamp *openamp, const char } static int openamp_init(void) -{ +{ extern int MX_OPENAMP_Init(int RPMsgRole, rpmsg_ns_bind_cb ns_bind_cb); /* IPCC init */ @@ -217,25 +217,25 @@ static int openamp_init(void) } /* openamp slave device */ MX_OPENAMP_Init(RPMSG_REMOTE, NULL); - - if (VIRT_UART_Init(&huart0) != VIRT_UART_OK) + + if (VIRT_UART_Init(&huart0) != VIRT_UART_OK) { return RT_ERROR; } - if (VIRT_UART_RegisterCallback(&huart0, VIRT_UART_RXCPLT_CB_ID, VIRT_UART0_RxCpltCallback) != VIRT_UART_OK) + if (VIRT_UART_RegisterCallback(&huart0, VIRT_UART_RXCPLT_CB_ID, VIRT_UART0_RxCpltCallback) != VIRT_UART_OK) { return RT_ERROR; } - - return RT_EOK; + + return RT_EOK; } int rt_hw_openamp_init(void) { openamp_init(); - + rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL); - + if (RT_CONSOLE_DEVICE_NAME == "openamp") { rt_console_set_device(RT_CONSOLE_DEVICE_NAME); @@ -245,27 +245,27 @@ int rt_hw_openamp_init(void) } INIT_PREV_EXPORT(rt_hw_openamp_init); -static void openamp_thread_entry(void *parameter) +static void openamp_thread_entry(void *parameter) { rt_size_t size = 0; struct rthw_openamp *device = RT_NULL; - + device = (struct rthw_openamp *)rt_device_find("openamp"); RT_ASSERT(device != RT_NULL); - - for (;;) + + for (;;) { OPENAMP_check_for_message(); size = device->serial.rbuf_count; if (size > 0) { - if (device->parent.rx_indicate != RT_NULL) + if (device->parent.rx_indicate != RT_NULL) { device->parent.rx_indicate(&device->parent, size); } } - + rt_thread_mdelay(1); } } @@ -273,22 +273,22 @@ static void openamp_thread_entry(void *parameter) static int creat_openamp_thread(void) { rt_thread_t tid = RT_NULL; - - tid = rt_thread_create("OpenAMP", - openamp_thread_entry, - RT_NULL, - OPENAMP_THREAD_STACK_SIZE, - OPENAMP_THREAD_PRIORITY, + + tid = rt_thread_create("OpenAMP", + openamp_thread_entry, + RT_NULL, + OPENAMP_THREAD_STACK_SIZE, + OPENAMP_THREAD_PRIORITY, OPENAMP_THREAD_TIMESLICE); - - if (tid == RT_NULL) + + if (tid == RT_NULL) { LOG_E("openamp thread create failed!"); return RT_ERROR; - } - + } + rt_thread_startup(tid); - + return RT_EOK; } INIT_APP_EXPORT(creat_openamp_thread); @@ -298,7 +298,7 @@ INIT_APP_EXPORT(creat_openamp_thread); static int console(int argc, char **argv) { rt_err_t result = RT_EOK; - + if (argc > 1) { if (!strcmp(argv[1], "set")) diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h index df1533b38b..20538a999d 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/OpenAMP/drv_openamp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,22 +18,22 @@ extern "C" { struct rt_openamp { - rt_uint8_t *rbuf; - rt_uint8_t *tbuf; - volatile rt_uint16_t rbuf_size; + rt_uint8_t *rbuf; + rt_uint8_t *tbuf; + volatile rt_uint16_t rbuf_size; volatile rt_uint16_t tbuf_size; volatile rt_uint16_t rbuf_start; volatile rt_uint16_t rbuf_count; volatile rt_uint16_t tbuf_start; volatile rt_uint16_t tbuf_count; }; - + #define OPENAMP_THREAD_STACK_SIZE 512 #define OPENAMP_THREAD_PRIORITY 5 #define OPENAMP_THREAD_TIMESLICE 10 #define MAX_BUFFER_SIZE 256 - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c index 23cc195046..4a269bf936 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/dma_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -83,9 +83,9 @@ static int uart_dma_sample(int argc, char *argv[]) } rt_mq_init(&rx_mq, "rx_mq", - msg_pool, - sizeof(struct rx_msg), - sizeof(msg_pool), + msg_pool, + sizeof(struct rx_msg), + sizeof(msg_pool), RT_IPC_FLAG_FIFO); ret = rt_device_open(serial, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_RX); @@ -94,14 +94,14 @@ static int uart_dma_sample(int argc, char *argv[]) rt_kprintf("serial device open fail!.\n"); return -RT_ERROR; } - + ret = rt_device_set_rx_indicate(serial, uart_input); if (ret != RT_EOK) { rt_kprintf("set rx indicate fail!.\n"); return -RT_ERROR; } - + rt_device_write(serial, 0, str, (sizeof(str) - 1)); rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c index def5dfd461..1accaced7c 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -110,7 +110,7 @@ void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /* enter interrupt */ rt_interrupt_enter(); - jpeg_data_process(); + jpeg_data_process(); __HAL_DCMI_ENABLE_IT(&dcmi,DCMI_IT_FRAME); /* leave interrupt */ rt_interrupt_leave(); @@ -127,7 +127,7 @@ void DMA1_Stream3_IRQHandler(void) __HAL_DMA_CLEAR_FLAG(&hdma_dcmi, DMA_FLAG_TCIF3_7); rt_hw_camera_rx_callback(); } - + /* leave interrupt */ rt_interrupt_leave(); } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h index 39fe3bdd26..d83c739a83 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dcmi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c index 38678dbdce..61600fbd00 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -67,7 +67,7 @@ void DMA2_Stream2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_DMA_IRQHandler(&hdma_dfsdm1_flt1); /* leave interrupt */ @@ -78,9 +78,9 @@ void DMA2_Stream1_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_DMA_IRQHandler(&hdma_dfsdm1_flt0); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -122,15 +122,15 @@ static int rt_hw_dfsdm_init(void) hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS; hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING ; /* left */ hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL; - hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; - hdfsdm1_channel1.Init.Awd.Oversampling = 10; + hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; + hdfsdm1_channel1.Init.Awd.Oversampling = 10; hdfsdm1_channel1.Init.Offset = 0; hdfsdm1_channel1.Init.RightBitShift = 2; if(HAL_OK != HAL_DFSDM_ChannelInit(&hdfsdm1_channel1)) { return RT_ERROR; } - + /* DATAIN1_RIGHT */ __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(&hdfsdm1_channel0); hdfsdm1_channel0.Instance = DFSDM1_Channel0; @@ -138,7 +138,7 @@ static int rt_hw_dfsdm_init(void) hdfsdm1_channel0.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM; hdfsdm1_channel0.Init.OutputClock.Divider = 74; /* 209/74 = 2.82MHZ*/ hdfsdm1_channel0.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS; - hdfsdm1_channel0.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; + hdfsdm1_channel0.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; hdfsdm1_channel0.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS; hdfsdm1_channel0.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_FALLING; /* right */ hdfsdm1_channel0.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL; @@ -159,7 +159,7 @@ static int rt_hw_dfsdm_init(void) hdfsdm1_filter0.Init.RegularParam.DmaMode = ENABLE; hdfsdm1_filter0.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; hdfsdm1_filter0.Init.InjectedParam.ScanMode = DISABLE; - hdfsdm1_filter0.Init.InjectedParam.DmaMode = DISABLE; + hdfsdm1_filter0.Init.InjectedParam.DmaMode = DISABLE; hdfsdm1_filter0.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC3_ORDER; hdfsdm1_filter0.Init.FilterParam.Oversampling = 64; /* 209 / ( 74 * 64) = 44.1KHZ*/ hdfsdm1_filter0.Init.FilterParam.IntOversampling = 1; @@ -174,9 +174,9 @@ static int rt_hw_dfsdm_init(void) hdfsdm1_filter1.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER; hdfsdm1_filter1.Init.RegularParam.FastMode = ENABLE; hdfsdm1_filter1.Init.RegularParam.DmaMode = ENABLE; - hdfsdm1_filter1.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; - hdfsdm1_filter1.Init.InjectedParam.ScanMode = DISABLE; - hdfsdm1_filter1.Init.InjectedParam.DmaMode = DISABLE; + hdfsdm1_filter1.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; + hdfsdm1_filter1.Init.InjectedParam.ScanMode = DISABLE; + hdfsdm1_filter1.Init.InjectedParam.DmaMode = DISABLE; hdfsdm1_filter1.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC3_ORDER; hdfsdm1_filter1.Init.FilterParam.Oversampling = 64; /* 209 / ( 74 * 64) = 44.1KHZ*/ hdfsdm1_filter1.Init.FilterParam.IntOversampling = 1; @@ -221,7 +221,7 @@ static rt_err_t rt_hw_dfsdm_open(void) static rt_err_t _init(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); - + rt_hw_dfsdm_init(); return RT_EOK; @@ -230,7 +230,7 @@ static rt_err_t _init(rt_device_t dev) static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag) { RT_ASSERT(dev != RT_NULL); - + rt_hw_dfsdm_open(); return RT_EOK; @@ -239,10 +239,10 @@ static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t _close(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); - + HAL_DFSDM_FilterRegularStop_DMA(&hdfsdm1_filter0); HAL_DFSDM_FilterRegularStop_DMA(&hdfsdm1_filter1); - + return RT_EOK; } @@ -252,7 +252,7 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si rt_uint32_t i = 0; rt_int16_t *p = RT_NULL; p = (rt_int16_t *)buffer; - + if (!pos) { for (i = 0; i < 512; i++) @@ -267,7 +267,7 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si { p[2*i] = (int16_t)SaturaLH((FILTER0_FIFO[i] >> 8), -32768, 32767); p[(2*i)+1] = (int16_t)SaturaLH((FILTER1_FIFO[i] >> 8), -32768, 32767); - } + } } return size; @@ -276,7 +276,7 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si static rt_size_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { RT_ASSERT(dev != RT_NULL); - + return RT_EOK; } @@ -299,9 +299,9 @@ int dfsdm_init(void) dfsdm_dev.user_data = RT_NULL; rt_device_register(&dfsdm_dev, "dfsdm1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - + LOG_I("dfsdm1 init success!"); - + return RT_EOK; } INIT_DEVICE_EXPORT(dfsdm_init); @@ -314,38 +314,38 @@ static int dfsdm_sample(int argc, char **argv) rt_kprintf("dfsdm_sample\n"); return -1; } - - static struct rt_device *dfsdm_dev = RT_NULL; - static struct rt_device *sound_dev = RT_NULL; + + static struct rt_device *dfsdm_dev = RT_NULL; + static struct rt_device *sound_dev = RT_NULL; rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE; rt_uint16_t tickstart = 0; - + extern SAI_HandleTypeDef hsai_BlockA2; - + dfsdm_dev = rt_device_find("dfsdm1"); if (dfsdm_dev == RT_NULL) { rt_kprintf("no dfsdm device!"); return RT_ERROR; } - + sound_dev = rt_device_find("decoder"); if (sound_dev == RT_NULL) { rt_kprintf("no decoder device!"); - return RT_ERROR; + return RT_ERROR; } /* open dfsdm device */ rt_device_open(dfsdm_dev, RT_DEVICE_OFLAG_RDWR); /* open sound device */ rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY); - + rt_device_control(sound_dev, SET_PLAY_TYPE, &play_type); rt_device_control(sound_dev, START_PLAY, RT_NULL); - + rt_memset(PLAY_BUF, 0, PALY_SIZE); - + tickstart = rt_tick_get(); if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, (uint8_t *)PLAY_BUF, PALY_SIZE) != HAL_OK) { @@ -353,7 +353,7 @@ static int dfsdm_sample(int argc, char **argv) return RT_ERROR; } rt_kprintf("dfsdm audio record test begin!\n"); - + while (1) { if ((rt_tick_get() - tickstart) > 0x1000) @@ -375,9 +375,9 @@ static int dfsdm_sample(int argc, char **argv) DmaRightRecBuffCplt = 0; } } - + rt_kprintf("dfsdm audio record test end!\n"); - + return RT_EOK; } MSH_CMD_EXPORT(dfsdm_sample, dfsdm audiorecord test); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h index bf40fbf2f8..7b73c85638 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_dfsdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,7 +18,7 @@ extern "C" { #endif #define SaturaLH(N, L, H) (((N)<(L))?(L):(((N)>(H))?(H):(N))) - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c index 54af52e5e0..3e1913bb94 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -172,7 +172,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) { return; } - + cmd->resp[0] = hw_sdio->resp1; cmd->resp[1] = hw_sdio->resp2; cmd->resp[2] = hw_sdio->resp3; @@ -188,22 +188,22 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) { cmd->err = -RT_ERROR; } - + if (status & SDMMC_STA_CTIMEOUT) { cmd->err = -RT_ETIMEOUT; } - + if (status & SDMMC_STA_DCRCFAIL) { data->err = -RT_ERROR; } - + if (status & SDMMC_STA_DTIMEOUT) { data->err = -RT_ETIMEOUT; } - + if (cmd->err == RT_EOK) { LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); @@ -226,7 +226,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) data ? data->blksize : 0 ); } - + } else { @@ -247,7 +247,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) struct rt_mmcsd_data *data = cmd->data; struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio; rt_uint32_t reg_cmd; - + sdio->pkg = pkg; LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n", @@ -282,7 +282,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) reg_cmd |= SDMMC_RESPONSE_SHORT; } hw_sdio->mask |= SDIO_MASKR_ALL; - + /* data pre configuration */ if (data != RT_NULL) { @@ -324,7 +324,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) #if defined(EMMC_RX_DUMP) rt_kprintf("\nEMMC Rx:\n"); dump_hex(cache_buf, data->blks * data->blksize); -#endif +#endif rt_memcpy(data->buf, cache_buf, data->blks * data->blksize); } } @@ -343,7 +343,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r struct rt_mmcsd_data *data; RTHW_SDIO_LOCK(sdio); - + if (req->cmd != RT_NULL) { rt_memset(&pkg, 0, sizeof(pkg)); @@ -361,7 +361,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r #if defined(EMMC_TX_DUMP) rt_kprintf("\nEMMC Tx:\n"); dump_hex(cache_buf, data->blks * data->blksize); -#endif +#endif rt_memcpy(cache_buf, data->buf, size); } } @@ -377,7 +377,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r } RTHW_SDIO_UNLOCK(sdio); - + mmcsd_req_complete(sdio->host); } @@ -423,7 +423,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg * ); RTHW_SDIO_LOCK(sdio); - + clk_src = EMMC_CLOCK_FREQ; if (clk > 0) @@ -451,12 +451,12 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg * { temp |= SDMMC_BUS_WIDE_1B; } - + hw_sdio->clkcr = temp; if (io_cfg->power_mode == MMCSD_POWER_ON) hw_sdio->power |= SDMMC_POWER_PWRCTRL; - + RTHW_SDIO_UNLOCK(sdio); } @@ -529,7 +529,7 @@ err: { rt_free(sdio); } - + return RT_NULL; } @@ -538,14 +538,14 @@ void SDMMC2_IRQHandler(void) rt_interrupt_enter(); /* Process All SDIO Interrupt Sources */ rthw_sdio_irq_process(host); - + rt_interrupt_leave(); } int rt_hw_sdio_init(void) { struct stm32_sdio_des sdio_des; - + hsd.Instance = SDMMC2; HAL_SD_MspInit(&hsd); @@ -563,20 +563,20 @@ INIT_DEVICE_EXPORT(rt_hw_sdio_init); int mnt_init(void) { rt_device_t sd = RT_NULL; - + #if defined(EMMC_RX_DUMP) || defined(EMMC_TX_DUMP) rt_thread_delay(3000); #else rt_thread_delay(RT_TICK_PER_SECOND); #endif - + sd = rt_device_find("sd0"); if (sd == RT_NULL) { rt_kprintf("can't find emmc device!\n"); return RT_ERROR; } - + if (dfs_mount("sd0", "/", "elm", 0, 0) != 0) { rt_kprintf("file system mount failed!\n"); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h index bd385cbb14..7f3e8c1dc8 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_emmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -76,7 +76,7 @@ struct stm32_sdio volatile rt_uint32_t idmalar; volatile rt_uint32_t idmabar; volatile rt_uint32_t reserved2[5]; - volatile rt_uint32_t fifo; + volatile rt_uint32_t fifo; volatile rt_uint32_t reserved3[220]; volatile rt_uint32_t verr; volatile rt_uint32_t ipidr; diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c index d3d118fd9f..caaf002aa9 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_exti.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ static int exti_sample(void) rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP); rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL); rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE); - + return RT_EOK; } INIT_DEVICE_EXPORT(exti_sample); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c index 78c18e8594..494d8e399f 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h index ab4280d360..764a69105f 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_fdcan.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c index 195345c19d..34a8ae0593 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,9 +28,9 @@ void LPTIM1_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_LPTIM_IRQHandler(&hlptim1); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -41,10 +41,10 @@ void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) { HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_9); } - + #if defined(BSP_USING_PWR) /* All level of ITs can interrupt */ - __set_BASEPRI(0U); + __set_BASEPRI(0U); lptim_stop(); rt_kprintf("system returns to normal!\n"); @@ -55,12 +55,12 @@ static int lptim_control(uint8_t pre_value) { if(pre_value > 7) { - pre_value = 7; + pre_value = 7; } hlptim1.Instance->CFGR &= ~(7 << 9); /* clear PRESC[2:0] */ hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0] */ rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value); - + return RT_EOK; } @@ -72,9 +72,9 @@ int lptim_start(void) LOG_D("lptim1 start counting failed!\n"); return -RT_ERROR; } - + LOG_D("lptim1 start counting success!\n"); - + return RT_EOK; } @@ -85,16 +85,16 @@ int lptim_stop(void) LOG_D("lptim1 stop failed!\n"); return -RT_ERROR; } - - LOG_D("lptim1 stop counting success!\n"); - + + LOG_D("lptim1 stop counting success!\n"); + return RT_EOK; } int lptim_init(void) { rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT); - + hlptim1.Instance = LPTIM1; hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8; @@ -112,7 +112,7 @@ int lptim_init(void) return -RT_ERROR; } LOG_D("lptim init success!\n"); - + return RT_EOK; } INIT_DEVICE_EXPORT(lptim_init); @@ -122,7 +122,7 @@ static int lptim_sample(int argc, char *argv[]) if (argc > 1) { if (!strcmp(argv[1], "start")) - { + { lptim_start(); return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c index 071f833a10..c92145f378 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,7 +20,7 @@ struct st_mfx { - struct rt_device dev; + struct rt_device dev; struct rt_i2c_bus_device *i2c_bus; rt_uint8_t id; rt_uint16_t type; @@ -31,7 +31,7 @@ static IO_DrvTypeDef *IoDrv = NULL; static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint16_t len, rt_uint8_t *buf) { struct rt_i2c_msg msg[2] = {0, 0}; - + RT_ASSERT(bus != RT_NULL); msg[0].addr = CHIP_ADDRESS; @@ -134,11 +134,11 @@ RT_WEAK void MFX_IO_Delay(rt_uint32_t Delay) rt_thread_delay(Delay); } -RT_WEAK void MFX_IO_Wakeup(void) +RT_WEAK void MFX_IO_Wakeup(void) { } -RT_WEAK void MFX_IO_EnableWakeupPin(void) +RT_WEAK void MFX_IO_EnableWakeupPin(void) { } @@ -172,7 +172,7 @@ void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear) /** * @brief Configures the IO pin(s) according to IO mode structure value. - * @param IoPin: IO pin(s) to be configured. + * @param IoPin: IO pin(s) to be configured. * This parameter can be one of the following values: * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23. * @param IoMode: IO pin mode to configure @@ -182,7 +182,7 @@ void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear) * @arg IO_MODE_IT_RISING_EDGE * @arg IO_MODE_IT_FALLING_EDGE * @arg IO_MODE_IT_LOW_LEVEL - * @arg IO_MODE_IT_HIGH_LEVEL + * @arg IO_MODE_IT_HIGH_LEVEL * @arg IO_MODE_ANALOG * @arg IO_MODE_OFF * @arg IO_MODE_INPUT_PU, @@ -201,20 +201,20 @@ void BSP_IO_ITClearPin(rt_uint32_t IO_Pins_To_Clear) * @arg IO_MODE_IT_FALLING_EDGE_PD * @arg IO_MODE_IT_LOW_LEVEL_PD * @arg IO_MODE_IT_HIGH_LEVEL_PD - * @retval RT_EOK if all initializations are OK. Other value if error. + * @retval RT_EOK if all initializations are OK. Other value if error. */ rt_uint8_t rt_mfx_pin_mode(rt_uint32_t IoPin, IO_ModeTypedef IoMode) { /* Configure the selected IO pin(s) mode */ IoDrv->Config(0, IoPin, IoMode); - return RT_EOK; + return RT_EOK; } /** * @brief Sets the IRQ_OUT pin polarity and type * @param IoIrqOutPinPolarity: High/Low - * @param IoIrqOutPinType: OpenDrain/PushPull + * @param IoIrqOutPinType: OpenDrain/PushPull * @retval OK */ rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOutPinType) @@ -231,9 +231,9 @@ rt_uint8_t rt_mfx_config_irq(rt_uint8_t IoIrqOutPinPolarity, rt_uint8_t IoIrqOut /** * @brief Sets the selected pins state. - * @param IoPin: Selected pins to write. - * This parameter can be any combination of the IO pins. - * @param PinState: New pins state to write + * @param IoPin: Selected pins to write. + * This parameter can be any combination of the IO pins. + * @param PinState: New pins state to write * @retval None */ void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState) @@ -244,9 +244,9 @@ void rt_mfx_pin_write(rt_uint32_t IoPin, rt_base_t PinState) /** * @brief Gets the selected pins current state. - * @param IoPin: Selected pins to read. - * This parameter can be any combination of the IO pins. - * @retval The current pins state + * @param IoPin: Selected pins to read. + * This parameter can be any combination of the IO pins. + * @retval The current pins state */ rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin) { @@ -255,9 +255,9 @@ rt_uint32_t rt_mfx_pin_read(rt_uint32_t IoPin) /** * @brief Toggles the selected pins state. - * @param IoPin: Selected pins to toggle. - * This parameter can be any combination of the IO pins. - * @note This function is only used to toggle one pin in the same time + * @param IoPin: Selected pins to toggle. + * This parameter can be any combination of the IO pins. + * @note This function is only used to toggle one pin in the same time * @retval None */ void rt_mfx_pin_toggle(rt_uint32_t IoPin) @@ -270,7 +270,7 @@ void rt_mfx_pin_toggle(rt_uint32_t IoPin) else { IoDrv->WritePin(0, IoPin, 1); /* Set */ - } + } } int rt_mfx_init(void) @@ -285,13 +285,13 @@ int rt_mfx_init(void) /* Initialize MFX */ IoDrv->Init(0); IoDrv->Start(0, IO_PIN_ALL); - + LOG_I("mfx init success, id: 0x%x", rt_mfx.id); - + return RT_EOK; } LOG_I("mfx init error, id: 0x%x", rt_mfx.id); - + return RT_ERROR; } INIT_DEVICE_EXPORT(rt_mfx_init); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h index a0cf46777c..9816c8c335 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_mfx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c index 84e93e2926..f92dd09afb 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,8 +21,8 @@ #define NAND_RB_PIN GET_PIN(D, 6) -static rt_uint32_t ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE]; -static rt_uint32_t ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE]; +static rt_uint32_t ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE]; +static rt_uint32_t ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE]; struct rthw_fmc { rt_uint32_t id; @@ -193,11 +193,11 @@ static rt_uint8_t rt_hw_nand_ecc_check(rt_uint32_t generatedEcc, rt_uint32_t rea syndrome = (generatedEcc ^ readEcc) & ECC_MASK28; - if (syndrome == 0) + if (syndrome == 0) { return (RT_EOK); /* No errors in data. */ } - + eccPn = syndrome & ECC_MASK; /* Get 14 odd parity bits. */ eccP = (syndrome >> 1) & ECC_MASK; /* Get 14 even parity bits. */ @@ -255,13 +255,13 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, rt_uint32_t index, i, tickstart, eccnum; rt_err_t result; rt_uint8_t *p = RT_NULL; - + page = page + device->block_start * device->pages_per_block; if (page / device->pages_per_block > device->block_end) { return -RT_EIO; } - + rt_mutex_take(&_device.lock, RT_WAITING_FOREVER); if (data && data_len) { @@ -272,9 +272,9 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, NAND_DATA_AREA = (rt_uint8_t)(page >> 8); NAND_DATA_AREA = (rt_uint8_t)(page >> 16); NAND_CMD_AREA = NAND_AREA_TRUE1; - + rt_hw_nand_delay(10); - + /* not an integer multiple of NAND ECC SECTOR SIZE, no ECC checks*/ if (data_len % NAND_ECC_SECTOR_SIZE) { @@ -285,16 +285,16 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, } else { - eccnum = data_len/NAND_ECC_SECTOR_SIZE; + eccnum = data_len/NAND_ECC_SECTOR_SIZE; p = data; for (index = 0; index < 4; index++) { - FMC_Bank3_R->PCR |= 1<<6; /* enable ecc */ - - for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++) + FMC_Bank3_R->PCR |= 1<<6; /* enable ecc */ + + for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++) { *data++ = NAND_ADDR_AREA; - } + } /* Get tick */ tickstart = rt_tick_get(); /* Wait until FIFO is empty */ @@ -307,25 +307,25 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, goto _exit; } } - ecc_hdbuf[index] = FMC_Bank3_R->HECCR; /* read hardware ecc */ - FMC_Bank3_R->PCR &= ~(1<<6); /* disable ecc */ + ecc_hdbuf[index] = FMC_Bank3_R->HECCR; /* read hardware ecc */ + FMC_Bank3_R->PCR &= ~(1<<6); /* disable ecc */ } i = device->page_size + 0x10; - + rt_hw_nand_delay(10); - + NAND_CMD_AREA = 0x05; NAND_DATA_AREA = (rt_uint8_t)i; NAND_DATA_AREA = (rt_uint8_t)(i>>8); NAND_CMD_AREA = 0xE0; - + rt_hw_nand_delay(10); - - data =(rt_uint8_t*)&ecc_rdbuf[0]; + + data =(rt_uint8_t*)&ecc_rdbuf[0]; for (i = 0; i < 4*eccnum; i++) { *data++ = NAND_ADDR_AREA; - } + } /* check ecc */ for(i = 0; i< eccnum; i++) { @@ -336,10 +336,10 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, { goto _exit; } - } + } } } - } + } if (spare && spare_len) { NAND_CMD_AREA = NAND_AREA_A; @@ -356,7 +356,7 @@ static rt_err_t _read_page(struct rt_mtd_nand_device *device, *spare++ = NAND_ADDR_AREA; } } - + if (rt_hw_nand_wait_ready() != RT_EOK) { result = RT_ETIMEOUT; @@ -400,11 +400,11 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device, NAND_DATA_AREA = (rt_uint8_t)(page & 0xFF); NAND_DATA_AREA = (rt_uint8_t)(page >> 8); NAND_DATA_AREA = (rt_uint8_t)(page >> 16); - + rt_hw_nand_delay(10); - + if (data_len % NAND_ECC_SECTOR_SIZE) - { + { /* read nand flash */ for (i = 0; i < data_len; i++) { @@ -413,15 +413,15 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device, } else { - eccnum = data_len/NAND_ECC_SECTOR_SIZE; + eccnum = data_len/NAND_ECC_SECTOR_SIZE; for (index = 0; index < eccnum; index++) { - FMC_Bank3_R->PCR |= 1<<6; /* enable ecc */ - - for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++) + FMC_Bank3_R->PCR |= 1<<6; /* enable ecc */ + + for (i = 0; i < NAND_ECC_SECTOR_SIZE; i++) { NAND_ADDR_AREA = *data++; - } + } /* Get tick */ tickstart = rt_tick_get(); /* Wait until FIFO is empty */ @@ -434,26 +434,26 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device, goto _exit; } } - ecc_hdbuf[index] = FMC_Bank3_R->HECCR; /* read hardware ecc */ - FMC_Bank3_R->PCR &= ~(1<<6); /* disable ecc */ + ecc_hdbuf[index] = FMC_Bank3_R->HECCR; /* read hardware ecc */ + FMC_Bank3_R->PCR &= ~(1<<6); /* disable ecc */ } - + i = device->page_size + 0x10; rt_hw_nand_delay(10); NAND_CMD_AREA = 0x85; NAND_DATA_AREA = (rt_uint8_t)i; NAND_DATA_AREA = (rt_uint8_t)(i>>8); rt_hw_nand_delay(10); - + data = (uint8_t*)&ecc_hdbuf[0]; - for (index = 0; index < eccnum; index++) - { - for (i = 0; i < 4; i++) + for (index = 0; index < eccnum; index++) + { + for (i = 0; i < 4; i++) { NAND_ADDR_AREA = *data++; } - } + } } } NAND_CMD_AREA = NAND_WRITE_TURE1; @@ -462,7 +462,7 @@ static rt_err_t _write_page(struct rt_mtd_nand_device *device, result = -RT_EIO; goto _exit; } - + if (spare && spare_len) { NAND_CMD_AREA = NAND_WRITE0; diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h index 609a5e2aae..094635ebfb 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c index 30eb0e4ad7..da4d602a67 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -39,10 +39,10 @@ __no_init static rt_int32_t JPEG_DATA_BUF[JPEG_BUF_SIZE]; #if defined(__CC_ARM) || defined(__CLANG_ARM) __attribute__((at(0x2FFDC000))) static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]; #elif defined(__GNUC__) -static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE] __attribute__((section(".Dcmi1Section"))); +static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE] __attribute__((section(".Dcmi1Section"))); #elif defined(__ICCARM__) #pragma location = 0x2FFDC000 -__no_init static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]; +__no_init static rt_int32_t JPEG_LINE_BUF[2][JPEG_LINE_SIZE]; #endif volatile rt_uint32_t jpeg_data_len = 0; diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h index d005150482..d2daa32bd6 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_ov5640.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,9 +16,9 @@ extern "C" { #endif -/** - * @brief OV5640 ID - */ +/** + * @brief OV5640 ID + */ #define OV5640_ID 0x5640U /* JPEG picture size table */ @@ -40,611 +40,611 @@ static const unsigned short jpeg_picture_size[][2] = /* camera light mode */ static const unsigned char OV5640_LIGHTMODE_TBL[5][7]= -{ - 0x04,0X00,0X04,0X00,0X04,0X00,0X00, /* Auto */ - 0x06,0X1C,0X04,0X00,0X04,0XF3,0X01, /* Sunny */ - 0x05,0X48,0X04,0X00,0X07,0XCF,0X01, /* Office */ - 0x06,0X48,0X04,0X00,0X04,0XD3,0X01, /* Cloudy */ - 0x04,0X10,0X04,0X00,0X08,0X40,0X01, /* Home */ -}; +{ + 0x04,0X00,0X04,0X00,0X04,0X00,0X00, /* Auto */ + 0x06,0X1C,0X04,0X00,0X04,0XF3,0X01, /* Sunny */ + 0x05,0X48,0X04,0X00,0X07,0XCF,0X01, /* Office */ + 0x06,0X48,0X04,0X00,0X04,0XD3,0X01, /* Cloudy */ + 0x04,0X10,0X04,0X00,0X08,0X40,0X01, /* Home */ +}; /* Table of color saturation setting parameters */ static const unsigned char OV5640_SATURATION_TBL[7][6]= -{ - 0X0C,0x30,0X3D,0X3E,0X3D,0X01, /* -3 */ - 0X10,0x3D,0X4D,0X4E,0X4D,0X01, /* -2 */ - 0X15,0x52,0X66,0X68,0X66,0X02, /* -1 */ - 0X1A,0x66,0X80,0X82,0X80,0X02, /* 0 */ - 0X1F,0x7A,0X9A,0X9C,0X9A,0X02, /* 1 */ - 0X24,0x8F,0XB3,0XB6,0XB3,0X03, /* 2 */ - 0X2B,0xAB,0XD6,0XDA,0XD6,0X04, /* 3 */ +{ + 0X0C,0x30,0X3D,0X3E,0X3D,0X01, /* -3 */ + 0X10,0x3D,0X4D,0X4E,0X4D,0X01, /* -2 */ + 0X15,0x52,0X66,0X68,0X66,0X02, /* -1 */ + 0X1A,0x66,0X80,0X82,0X80,0X02, /* 0 */ + 0X1F,0x7A,0X9A,0X9C,0X9A,0X02, /* 1 */ + 0X24,0x8F,0XB3,0XB6,0XB3,0X03, /* 2 */ + 0X2B,0xAB,0XD6,0XDA,0XD6,0X04, /* 3 */ }; static const unsigned short OV5640_jpeg_reg_tbl[][2]= { - 0x4300, 0x30, // YUV 422, YUYV - 0x501f, 0x00, // YUV 422 - // Input clock = 24Mhz - 0x3035, 0x21, // PLL - 0x3036, 0x69, // PLL - 0x3c07, 0x07, // lightmeter 1 threshold[7:0] - 0x3820, 0x46, // flip - 0x3821, 0x20, // mirror - 0x3814, 0x11, // timing X inc - 0x3815, 0x11, // timing Y inc - 0x3800, 0x00, // HS - 0x3801, 0x00, // HS - 0x3802, 0x00, // VS - 0x3803, 0x00, // VS - 0x3804, 0x0a, // HW (HE) - 0x3805, 0x3f, // HW (HE) - 0x3806, 0x07, // VH (VE) - 0x3807, 0x9f, // VH (VE) - - 0x3808, 0x02, // DVPHO - 0x3809, 0x80, // DVPHO - 0x380a, 0x01, // DVPVO - 0x380b, 0xe0, // DVPVO + 0x4300, 0x30, // YUV 422, YUYV + 0x501f, 0x00, // YUV 422 + // Input clock = 24Mhz + 0x3035, 0x21, // PLL + 0x3036, 0x69, // PLL + 0x3c07, 0x07, // lightmeter 1 threshold[7:0] + 0x3820, 0x46, // flip + 0x3821, 0x20, // mirror + 0x3814, 0x11, // timing X inc + 0x3815, 0x11, // timing Y inc + 0x3800, 0x00, // HS + 0x3801, 0x00, // HS + 0x3802, 0x00, // VS + 0x3803, 0x00, // VS + 0x3804, 0x0a, // HW (HE) + 0x3805, 0x3f, // HW (HE) + 0x3806, 0x07, // VH (VE) + 0x3807, 0x9f, // VH (VE) - 0x380c, 0x0b, // HTS // - 0x380d, 0x1c, // HTS - 0x380e, 0x07, // VTS // - 0x380f, 0xb0, // VTS - 0x3813, 0x04, // timing V offset 04 - 0x3618, 0x04, - 0x3612, 0x2b, - 0x3709, 0x12, - 0x370c, 0x00, - - 0x4004, 0x06, // BLC line number - 0x3002, 0x00, // enable JFIFO, SFIFO, JPG - 0x3006, 0xff, // enable clock of JPEG2x, JPEG - 0x4713, 0x03, // JPEG mode 3 - 0x4407, 0x01, // Quantization sacle - 0x460b, 0x35, - 0x460c, 0x22, - 0x4837, 0x16, // MIPI global timing - 0x3824, 0x02, // PCLK manual divider - 0x5001, 0xA3, // SDE on, Scaling on, CMX on, AWB on - 0x3503, 0x00, // AEC/AGC on + 0x3808, 0x02, // DVPHO + 0x3809, 0x80, // DVPHO + 0x380a, 0x01, // DVPVO + 0x380b, 0xe0, // DVPVO + + 0x380c, 0x0b, // HTS // + 0x380d, 0x1c, // HTS + 0x380e, 0x07, // VTS // + 0x380f, 0xb0, // VTS + 0x3813, 0x04, // timing V offset 04 + 0x3618, 0x04, + 0x3612, 0x2b, + 0x3709, 0x12, + 0x370c, 0x00, + + 0x4004, 0x06, // BLC line number + 0x3002, 0x00, // enable JFIFO, SFIFO, JPG + 0x3006, 0xff, // enable clock of JPEG2x, JPEG + 0x4713, 0x03, // JPEG mode 3 + 0x4407, 0x01, // Quantization sacle + 0x460b, 0x35, + 0x460c, 0x22, + 0x4837, 0x16, // MIPI global timing + 0x3824, 0x02, // PCLK manual divider + 0x5001, 0xA3, // SDE on, Scaling on, CMX on, AWB on + 0x3503, 0x00, // AEC/AGC on }; /* RGB565 configuration, 15 frames */ static const unsigned short ov5640_rgb565_reg_tbl[][2]= { - 0x4300, 0X6F, - 0X501F, 0x01, - // 1280x800, 15fps - // input clock 24Mhz, PCLK 42Mhz - 0x3035, 0x41, // PLL - 0x3036, 0x69, // PLL - 0x3c07, 0x07, // lightmeter 1 threshold[7:0] - 0x3820, 0x46, // flip - 0x3821, 0x00, // mirror - 0x3814, 0x31, // timing X inc - 0x3815, 0x31, // timing Y inc - 0x3800, 0x00, // HS - 0x3801, 0x00, // HS - 0x3802, 0x00, // VS - 0x3803, 0x00, // VS - 0x3804, 0x0a, // HW (HE) - 0x3805, 0x3f, // HW (HE) - 0x3806, 0x06, // VH (VE) - 0x3807, 0xa9, // VH (VE) - 0x3808, 0x05, // DVPHO - 0x3809, 0x00, // DVPHO - 0x380a, 0x02, // DVPVO - 0x380b, 0xd0, // DVPVO - 0x380c, 0x05, // HTS - 0x380d, 0xF8, // HTS - 0x380e, 0x03, // VTS - 0x380f, 0x84, // VTS - 0x3813, 0x04, // timing V offset - 0x3618, 0x00, - 0x3612, 0x29, - 0x3709, 0x52, - 0x370c, 0x03, - 0x3a02, 0x02, // 60Hz max exposure - 0x3a03, 0xe0, // 60Hz max exposure - - 0x3a14, 0x02, // 50Hz max exposure - 0x3a15, 0xe0, // 50Hz max exposure - 0x4004, 0x02, // BLC line number - 0x3002, 0x1c, // reset JFIFO, SFIFO, JPG - 0x3006, 0xc3, // disable clock of JPEG2x, JPEG - 0x4713, 0x03, // JPEG mode 3 - 0x4407, 0x04, // Quantization scale - 0x460b, 0x37, - 0x460c, 0x20, - 0x4837, 0x16, // MIPI global timing - 0x3824, 0x04, // PCLK manual divider - 0x5001, 0xA3, // SDE on, scale on, UV average off, color matrix on, AWB on - 0x3503, 0x00, // AEC/AGC on -}; + 0x4300, 0X6F, + 0X501F, 0x01, + // 1280x800, 15fps + // input clock 24Mhz, PCLK 42Mhz + 0x3035, 0x41, // PLL + 0x3036, 0x69, // PLL + 0x3c07, 0x07, // lightmeter 1 threshold[7:0] + 0x3820, 0x46, // flip + 0x3821, 0x00, // mirror + 0x3814, 0x31, // timing X inc + 0x3815, 0x31, // timing Y inc + 0x3800, 0x00, // HS + 0x3801, 0x00, // HS + 0x3802, 0x00, // VS + 0x3803, 0x00, // VS + 0x3804, 0x0a, // HW (HE) + 0x3805, 0x3f, // HW (HE) + 0x3806, 0x06, // VH (VE) + 0x3807, 0xa9, // VH (VE) + 0x3808, 0x05, // DVPHO + 0x3809, 0x00, // DVPHO + 0x380a, 0x02, // DVPVO + 0x380b, 0xd0, // DVPVO + 0x380c, 0x05, // HTS + 0x380d, 0xF8, // HTS + 0x380e, 0x03, // VTS + 0x380f, 0x84, // VTS + 0x3813, 0x04, // timing V offset + 0x3618, 0x00, + 0x3612, 0x29, + 0x3709, 0x52, + 0x370c, 0x03, + 0x3a02, 0x02, // 60Hz max exposure + 0x3a03, 0xe0, // 60Hz max exposure + + 0x3a14, 0x02, // 50Hz max exposure + 0x3a15, 0xe0, // 50Hz max exposure + 0x4004, 0x02, // BLC line number + 0x3002, 0x1c, // reset JFIFO, SFIFO, JPG + 0x3006, 0xc3, // disable clock of JPEG2x, JPEG + 0x4713, 0x03, // JPEG mode 3 + 0x4407, 0x04, // Quantization scale + 0x460b, 0x37, + 0x460c, 0x20, + 0x4837, 0x16, // MIPI global timing + 0x3824, 0x04, // PCLK manual divider + 0x5001, 0xA3, // SDE on, scale on, UV average off, color matrix on, AWB on + 0x3503, 0x00, // AEC/AGC on +}; static const unsigned short RGB565_Init[][2]= -{ - /* 24MHz input clock, 24MHz PCLK */ - 0x3008, 0x42, // software power down, bit[6] - 0x3103, 0x03, // system clock from PLL, bit[1] - 0x3017, 0xff, // FREX, Vsync, HREF, PCLK, D[9:6] output enable - 0x3018, 0xff, // D[5:0], GPIO[1:0] output enable - 0x3034, 0x1a, // MIPI 10-bit - 0x3037, 0x13, // PLL root divider, bit[4], PLL pre-divider, bit[3:0] - 0x3108, 0x01, // PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] +{ + /* 24MHz input clock, 24MHz PCLK */ + 0x3008, 0x42, // software power down, bit[6] + 0x3103, 0x03, // system clock from PLL, bit[1] + 0x3017, 0xff, // FREX, Vsync, HREF, PCLK, D[9:6] output enable + 0x3018, 0xff, // D[5:0], GPIO[1:0] output enable + 0x3034, 0x1a, // MIPI 10-bit + 0x3037, 0x13, // PLL root divider, bit[4], PLL pre-divider, bit[3:0] + 0x3108, 0x01, // PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] - // SCLK root divider, bit[1:0] - 0x3630, 0x36, - 0x3631, 0x0e, - 0x3632, 0xe2, - 0x3633, 0x12, - 0x3621, 0xe0, - 0x3704, 0xa0, - 0x3703, 0x5a, - 0x3715, 0x78, - 0x3717, 0x01, - 0x370b, 0x60, - 0x3705, 0x1a, - 0x3905, 0x02, - 0x3906, 0x10, - 0x3901, 0x0a, - 0x3731, 0x12, - 0x3600, 0x08, // VCM control - 0x3601, 0x33, // VCM control - 0x302d, 0x60, // system control - 0x3620, 0x52, - 0x371b, 0x20, - 0x471c, 0x50, - 0x3a13, 0x43, // pre-gain = 1.047x - 0x3a18, 0x00, // gain ceiling - 0x3a19, 0xf8, // gain ceiling = 15.5x - 0x3635, 0x13, - 0x3636, 0x03, - 0x3634, 0x40, - 0x3622, 0x01, - // 50/60Hz detection 50/60Hz - 0x3c01, 0x34, // Band auto, bit[7] - 0x3c04, 0x28, // threshold low sum - 0x3c05, 0x98, // threshold high sum - 0x3c06, 0x00, // light meter 1 threshold[15:8] - 0x3c07, 0x08, // light meter 1 threshold[7:0] - 0x3c08, 0x00, // light meter 2 threshold[15:8] - 0x3c09, 0x1c, // light meter 2 threshold[7:0] - 0x3c0a, 0x9c, // sample number[15:8] - 0x3c0b, 0x40, // sample number[7:0] - 0x3810, 0x00, // Timing Hoffset[11:8] - 0x3811, 0x10, // Timing Hoffset[7:0] - 0x3812, 0x00, // Timing Voffset[10:8] - 0x3708, 0x64, - 0x4001, 0x02, // BLC start from line 2 - 0x4005, 0x1a, // BLC always update - 0x3000, 0x00, // enable blocks - 0x3004, 0xff, // enable clocks - 0x300e, 0x58, // MIPI power down, DVP enable - 0x302e, 0x00, - 0x4300, 0x30, // YUV 422, YUYV - 0x501f, 0x00, // YUV 422 - 0x440e, 0x00, - 0x5000, 0xa7, // Lenc on, raw gamma on, BPC on, WPC on, CIP on - // AEC target - 0x3a0f, 0x30, // stable range in high - 0x3a10, 0x28, // stable range in low - 0x3a1b, 0x30, // stable range out high - 0x3a1e, 0x26, // stable range out low - 0x3a11, 0x60, // fast zone high - 0x3a1f, 0x14, // fast zone low - // Lens correction - 0x5800, 0x23, - 0x5801, 0x14, - 0x5802, 0x0f, - 0x5803, 0x0f, - 0x5804, 0x12, - 0x5805, 0x26, - 0x5806, 0x0c, - 0x5807, 0x08, - 0x5808, 0x05, - 0x5809, 0x05, - 0x580a, 0x08, + // SCLK root divider, bit[1:0] + 0x3630, 0x36, + 0x3631, 0x0e, + 0x3632, 0xe2, + 0x3633, 0x12, + 0x3621, 0xe0, + 0x3704, 0xa0, + 0x3703, 0x5a, + 0x3715, 0x78, + 0x3717, 0x01, + 0x370b, 0x60, + 0x3705, 0x1a, + 0x3905, 0x02, + 0x3906, 0x10, + 0x3901, 0x0a, + 0x3731, 0x12, + 0x3600, 0x08, // VCM control + 0x3601, 0x33, // VCM control + 0x302d, 0x60, // system control + 0x3620, 0x52, + 0x371b, 0x20, + 0x471c, 0x50, + 0x3a13, 0x43, // pre-gain = 1.047x + 0x3a18, 0x00, // gain ceiling + 0x3a19, 0xf8, // gain ceiling = 15.5x + 0x3635, 0x13, + 0x3636, 0x03, + 0x3634, 0x40, + 0x3622, 0x01, + // 50/60Hz detection 50/60Hz + 0x3c01, 0x34, // Band auto, bit[7] + 0x3c04, 0x28, // threshold low sum + 0x3c05, 0x98, // threshold high sum + 0x3c06, 0x00, // light meter 1 threshold[15:8] + 0x3c07, 0x08, // light meter 1 threshold[7:0] + 0x3c08, 0x00, // light meter 2 threshold[15:8] + 0x3c09, 0x1c, // light meter 2 threshold[7:0] + 0x3c0a, 0x9c, // sample number[15:8] + 0x3c0b, 0x40, // sample number[7:0] + 0x3810, 0x00, // Timing Hoffset[11:8] + 0x3811, 0x10, // Timing Hoffset[7:0] + 0x3812, 0x00, // Timing Voffset[10:8] + 0x3708, 0x64, + 0x4001, 0x02, // BLC start from line 2 + 0x4005, 0x1a, // BLC always update + 0x3000, 0x00, // enable blocks + 0x3004, 0xff, // enable clocks + 0x300e, 0x58, // MIPI power down, DVP enable + 0x302e, 0x00, + 0x4300, 0x30, // YUV 422, YUYV + 0x501f, 0x00, // YUV 422 + 0x440e, 0x00, + 0x5000, 0xa7, // Lenc on, raw gamma on, BPC on, WPC on, CIP on + // AEC target + 0x3a0f, 0x30, // stable range in high + 0x3a10, 0x28, // stable range in low + 0x3a1b, 0x30, // stable range out high + 0x3a1e, 0x26, // stable range out low + 0x3a11, 0x60, // fast zone high + 0x3a1f, 0x14, // fast zone low + // Lens correction + 0x5800, 0x23, + 0x5801, 0x14, + 0x5802, 0x0f, + 0x5803, 0x0f, + 0x5804, 0x12, + 0x5805, 0x26, + 0x5806, 0x0c, + 0x5807, 0x08, + 0x5808, 0x05, + 0x5809, 0x05, + 0x580a, 0x08, - 0x580b, 0x0d, - 0x580c, 0x08, - 0x580d, 0x03, - 0x580e, 0x00, - 0x580f, 0x00, - 0x5810, 0x03, - 0x5811, 0x09, - 0x5812, 0x07, - 0x5813, 0x03, - 0x5814, 0x00, - 0x5815, 0x01, - 0x5816, 0x03, - 0x5817, 0x08, - 0x5818, 0x0d, - 0x5819, 0x08, - 0x581a, 0x05, - 0x581b, 0x06, - 0x581c, 0x08, - 0x581d, 0x0e, - 0x581e, 0x29, - 0x581f, 0x17, - 0x5820, 0x11, - 0x5821, 0x11, - 0x5822, 0x15, - 0x5823, 0x28, - 0x5824, 0x46, - 0x5825, 0x26, - 0x5826, 0x08, - 0x5827, 0x26, - 0x5828, 0x64, - 0x5829, 0x26, - 0x582a, 0x24, - 0x582b, 0x22, - 0x582c, 0x24, - 0x582d, 0x24, - 0x582e, 0x06, - 0x582f, 0x22, - 0x5830, 0x40, - 0x5831, 0x42, - 0x5832, 0x24, - 0x5833, 0x26, - 0x5834, 0x24, - 0x5835, 0x22, - 0x5836, 0x22, - 0x5837, 0x26, - 0x5838, 0x44, - 0x5839, 0x24, - 0x583a, 0x26, - 0x583b, 0x28, - 0x583c, 0x42, - 0x583d, 0xce, // lenc BR offset - // AWB - 0x5180, 0xff, // AWB B block - 0x5181, 0xf2, // AWB control - 0x5182, 0x00, // [7:4] max local counter, [3:0] max fast counter - 0x5183, 0x14, // AWB advanced - 0x5184, 0x25, - 0x5185, 0x24, - 0x5186, 0x09, - 0x5187, 0x09, - 0x5188, 0x09, - 0x5189, 0x75, - 0x518a, 0x54, - 0x518b, 0xe0, - 0x518c, 0xb2, - 0x518d, 0x42, - 0x518e, 0x3d, - 0x518f, 0x56, - 0x5190, 0x46, - 0x5191, 0xf8, // AWB top limit - 0x5192, 0x04, // AWB bottom limit - 0x5193, 0x70, // red limit - 0x5194, 0xf0, // green limit - 0x5195, 0xf0, // blue limit - 0x5196, 0x03, // AWB control - 0x5197, 0x01, // local limit - 0x5198, 0x04, - 0x5199, 0x12, - 0x519a, 0x04, - 0x519b, 0x00, - 0x519c, 0x06, - 0x519d, 0x82, - 0x519e, 0x38, // AWB control - // Gamma - 0x5480, 0x01, // Gamma bias plus on, bit[0] - 0x5481, 0x08, - 0x5482, 0x14, - 0x5483, 0x28, - 0x5484, 0x51, - 0x5485, 0x65, - 0x5486, 0x71, - 0x5487, 0x7d, - 0x5488, 0x87, - 0x5489, 0x91, - 0x548a, 0x9a, - 0x548b, 0xaa, - 0x548c, 0xb8, - 0x548d, 0xcd, - 0x548e, 0xdd, - 0x548f, 0xea, - 0x5490, 0x1d, - // color matrix - 0x5381, 0x1e, // CMX1 for Y - 0x5382, 0x5b, // CMX2 for Y - 0x5383, 0x08, // CMX3 for Y - 0x5384, 0x0a, // CMX4 for U - 0x5385, 0x7e, // CMX5 for U - 0x5386, 0x88, // CMX6 for U - 0x5387, 0x7c, // CMX7 for V - 0x5388, 0x6c, // CMX8 for V - 0x5389, 0x10, // CMX9 for V - 0x538a, 0x01, // sign[9] - 0x538b, 0x98, // sign[8:1] - // UV adjust UV - 0x5580, 0x06, // saturation on, bit[1] - 0x5583, 0x40, - 0x5584, 0x10, - 0x5589, 0x10, - 0x558a, 0x00, - 0x558b, 0xf8, - 0x501d, 0x40, // enable manual offset of contrast - // CIP - 0x5300, 0x08, // CIP sharpen MT threshold 1 - 0x5301, 0x30, // CIP sharpen MT threshold 2 - 0x5302, 0x10, // CIP sharpen MT offset 1 - 0x5303, 0x00, // CIP sharpen MT offset 2 - 0x5304, 0x08, // CIP DNS threshold 1 - 0x5305, 0x30, // CIP DNS threshold 2 - 0x5306, 0x08, // CIP DNS offset 1 - 0x5307, 0x16, // CIP DNS offset 2 - 0x5309, 0x08, // CIP sharpen TH threshold 1 - 0x530a, 0x30, // CIP sharpen TH threshold 2 - 0x530b, 0x04, // CIP sharpen TH offset 1 - 0x530c, 0x06, // CIP sharpen TH offset 2 - 0x5025, 0x00, - 0x3008, 0x02, // wake up from standby, bit[6] + 0x580b, 0x0d, + 0x580c, 0x08, + 0x580d, 0x03, + 0x580e, 0x00, + 0x580f, 0x00, + 0x5810, 0x03, + 0x5811, 0x09, + 0x5812, 0x07, + 0x5813, 0x03, + 0x5814, 0x00, + 0x5815, 0x01, + 0x5816, 0x03, + 0x5817, 0x08, + 0x5818, 0x0d, + 0x5819, 0x08, + 0x581a, 0x05, + 0x581b, 0x06, + 0x581c, 0x08, + 0x581d, 0x0e, + 0x581e, 0x29, + 0x581f, 0x17, + 0x5820, 0x11, + 0x5821, 0x11, + 0x5822, 0x15, + 0x5823, 0x28, + 0x5824, 0x46, + 0x5825, 0x26, + 0x5826, 0x08, + 0x5827, 0x26, + 0x5828, 0x64, + 0x5829, 0x26, + 0x582a, 0x24, + 0x582b, 0x22, + 0x582c, 0x24, + 0x582d, 0x24, + 0x582e, 0x06, + 0x582f, 0x22, + 0x5830, 0x40, + 0x5831, 0x42, + 0x5832, 0x24, + 0x5833, 0x26, + 0x5834, 0x24, + 0x5835, 0x22, + 0x5836, 0x22, + 0x5837, 0x26, + 0x5838, 0x44, + 0x5839, 0x24, + 0x583a, 0x26, + 0x583b, 0x28, + 0x583c, 0x42, + 0x583d, 0xce, // lenc BR offset + // AWB + 0x5180, 0xff, // AWB B block + 0x5181, 0xf2, // AWB control + 0x5182, 0x00, // [7:4] max local counter, [3:0] max fast counter + 0x5183, 0x14, // AWB advanced + 0x5184, 0x25, + 0x5185, 0x24, + 0x5186, 0x09, + 0x5187, 0x09, + 0x5188, 0x09, + 0x5189, 0x75, + 0x518a, 0x54, + 0x518b, 0xe0, + 0x518c, 0xb2, + 0x518d, 0x42, + 0x518e, 0x3d, + 0x518f, 0x56, + 0x5190, 0x46, + 0x5191, 0xf8, // AWB top limit + 0x5192, 0x04, // AWB bottom limit + 0x5193, 0x70, // red limit + 0x5194, 0xf0, // green limit + 0x5195, 0xf0, // blue limit + 0x5196, 0x03, // AWB control + 0x5197, 0x01, // local limit + 0x5198, 0x04, + 0x5199, 0x12, + 0x519a, 0x04, + 0x519b, 0x00, + 0x519c, 0x06, + 0x519d, 0x82, + 0x519e, 0x38, // AWB control + // Gamma + 0x5480, 0x01, // Gamma bias plus on, bit[0] + 0x5481, 0x08, + 0x5482, 0x14, + 0x5483, 0x28, + 0x5484, 0x51, + 0x5485, 0x65, + 0x5486, 0x71, + 0x5487, 0x7d, + 0x5488, 0x87, + 0x5489, 0x91, + 0x548a, 0x9a, + 0x548b, 0xaa, + 0x548c, 0xb8, + 0x548d, 0xcd, + 0x548e, 0xdd, + 0x548f, 0xea, + 0x5490, 0x1d, + // color matrix + 0x5381, 0x1e, // CMX1 for Y + 0x5382, 0x5b, // CMX2 for Y + 0x5383, 0x08, // CMX3 for Y + 0x5384, 0x0a, // CMX4 for U + 0x5385, 0x7e, // CMX5 for U + 0x5386, 0x88, // CMX6 for U + 0x5387, 0x7c, // CMX7 for V + 0x5388, 0x6c, // CMX8 for V + 0x5389, 0x10, // CMX9 for V + 0x538a, 0x01, // sign[9] + 0x538b, 0x98, // sign[8:1] + // UV adjust UV + 0x5580, 0x06, // saturation on, bit[1] + 0x5583, 0x40, + 0x5584, 0x10, + 0x5589, 0x10, + 0x558a, 0x00, + 0x558b, 0xf8, + 0x501d, 0x40, // enable manual offset of contrast + // CIP + 0x5300, 0x08, // CIP sharpen MT threshold 1 + 0x5301, 0x30, // CIP sharpen MT threshold 2 + 0x5302, 0x10, // CIP sharpen MT offset 1 + 0x5303, 0x00, // CIP sharpen MT offset 2 + 0x5304, 0x08, // CIP DNS threshold 1 + 0x5305, 0x30, // CIP DNS threshold 2 + 0x5306, 0x08, // CIP DNS offset 1 + 0x5307, 0x16, // CIP DNS offset 2 + 0x5309, 0x08, // CIP sharpen TH threshold 1 + 0x530a, 0x30, // CIP sharpen TH threshold 2 + 0x530b, 0x04, // CIP sharpen TH offset 1 + 0x530c, 0x06, // CIP sharpen TH offset 2 + 0x5025, 0x00, + 0x3008, 0x02, // wake up from standby, bit[6] - 0x4740, 0X21, //VSYNC -}; + 0x4740, 0X21, //VSYNC +}; -/* Autofocus initialization configuration */ +/* Autofocus initialization configuration */ const unsigned char OV5640_AF_Config[] = { - 0x02, 0x0f, 0xd6, 0x02, 0x0a, 0x39, 0xc2, 0x01, 0x22, 0x22, 0x00, 0x02, 0x0f, 0xb2, 0xe5, 0x1f, //0x8000, - 0x70, 0x72, 0xf5, 0x1e, 0xd2, 0x35, 0xff, 0xef, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xe4, 0xf6, 0x08, //0x8010, - 0xf6, 0x0f, 0xbf, 0x34, 0xf2, 0x90, 0x0e, 0x93, 0xe4, 0x93, 0xff, 0xe5, 0x4b, 0xc3, 0x9f, 0x50, //0x8020, - 0x04, 0x7f, 0x05, 0x80, 0x02, 0x7f, 0xfb, 0x78, 0xbd, 0xa6, 0x07, 0x12, 0x0f, 0x04, 0x40, 0x04, //0x8030, - 0x7f, 0x03, 0x80, 0x02, 0x7f, 0x30, 0x78, 0xbc, 0xa6, 0x07, 0xe6, 0x18, 0xf6, 0x08, 0xe6, 0x78, //0x8040, - 0xb9, 0xf6, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xbf, 0x76, 0x33, 0xe4, 0x08, 0xf6, 0x78, //0x8050, - 0xb8, 0x76, 0x01, 0x75, 0x4a, 0x02, 0x78, 0xb6, 0xf6, 0x08, 0xf6, 0x74, 0xff, 0x78, 0xc1, 0xf6, //0x8060, - 0x08, 0xf6, 0x75, 0x1f, 0x01, 0x78, 0xbc, 0xe6, 0x75, 0xf0, 0x05, 0xa4, 0xf5, 0x4b, 0x12, 0x0a, //0x8070, - 0xff, 0xc2, 0x37, 0x22, 0x78, 0xb8, 0xe6, 0xd3, 0x94, 0x00, 0x40, 0x02, 0x16, 0x22, 0xe5, 0x1f, //0x8080, - 0xb4, 0x05, 0x23, 0xe4, 0xf5, 0x1f, 0xc2, 0x01, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x78, //0x8090, - 0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0xa2, 0x37, 0xe4, 0x33, 0xf5, 0x3c, 0x90, 0x30, 0x28, 0xf0, //0x80a0, - 0x75, 0x1e, 0x10, 0xd2, 0x35, 0x22, 0xe5, 0x4b, 0x75, 0xf0, 0x05, 0x84, 0x78, 0xbc, 0xf6, 0x90, //0x80b0, - 0x0e, 0x8c, 0xe4, 0x93, 0xff, 0x25, 0xe0, 0x24, 0x0a, 0xf8, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x78, //0x80c0, - 0xbc, 0xe6, 0x25, 0xe0, 0x24, 0x4e, 0xf8, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0xef, 0x12, 0x0f, 0x0b, //0x80d0, - 0xd3, 0x78, 0xb7, 0x96, 0xee, 0x18, 0x96, 0x40, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xb9, 0xf6, 0x78, //0x80e0, - 0xb6, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x8c, 0xe4, 0x93, 0x12, 0x0f, 0x0b, 0xc3, 0x78, //0x80f0, - 0xc2, 0x96, 0xee, 0x18, 0x96, 0x50, 0x0d, 0x78, 0xbc, 0xe6, 0x78, 0xba, 0xf6, 0x78, 0xc1, 0xa6, //0x8100, - 0x06, 0x08, 0xa6, 0x07, 0x78, 0xb6, 0xe6, 0xfe, 0x08, 0xe6, 0xc3, 0x78, 0xc2, 0x96, 0xff, 0xee, //0x8110, - 0x18, 0x96, 0x78, 0xc3, 0xf6, 0x08, 0xa6, 0x07, 0x90, 0x0e, 0x95, 0xe4, 0x18, 0x12, 0x0e, 0xe9, //0x8120, - 0x40, 0x02, 0xd2, 0x37, 0x78, 0xbc, 0xe6, 0x08, 0x26, 0x08, 0xf6, 0xe5, 0x1f, 0x64, 0x01, 0x70, //0x8130, - 0x4a, 0xe6, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xdf, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, 0x39, 0x12, //0x8140, - 0x0f, 0x02, 0x40, 0x04, 0x7f, 0xfe, 0x80, 0x02, 0x7f, 0x02, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, //0x8150, - 0xe6, 0x24, 0x03, 0x78, 0xbf, 0xf6, 0x78, 0xb9, 0xe6, 0x24, 0xfd, 0x78, 0xc0, 0xf6, 0x12, 0x0f, //0x8160, - 0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8170, - 0x07, 0x75, 0x1f, 0x02, 0x78, 0xb8, 0x76, 0x01, 0x02, 0x02, 0x4a, 0xe5, 0x1f, 0x64, 0x02, 0x60, //0x8180, - 0x03, 0x02, 0x02, 0x2a, 0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x08, //0x8190, - 0x12, 0x0e, 0xda, 0x50, 0x03, 0x02, 0x02, 0x28, 0x12, 0x0f, 0x02, 0x40, 0x04, 0x7f, 0xff, 0x80, //0x81a0, - 0x02, 0x7f, 0x01, 0x78, 0xbd, 0xa6, 0x07, 0x78, 0xb9, 0xe6, 0x04, 0x78, 0xbf, 0xf6, 0x78, 0xb9, //0x81b0, - 0xe6, 0x14, 0x78, 0xc0, 0xf6, 0x18, 0x12, 0x0f, 0x04, 0x40, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, //0x81c0, - 0x00, 0x78, 0xbf, 0xa6, 0x07, 0xd3, 0x08, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x40, 0x04, 0xe6, 0xff, //0x81d0, - 0x80, 0x02, 0x7f, 0x00, 0x78, 0xc0, 0xa6, 0x07, 0xc3, 0x18, 0xe6, 0x64, 0x80, 0x94, 0xb3, 0x50, //0x81e0, - 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xbf, 0xa6, 0x07, 0xc3, 0x08, 0xe6, 0x64, 0x80, //0x81f0, - 0x94, 0xb3, 0x50, 0x04, 0xe6, 0xff, 0x80, 0x02, 0x7f, 0x33, 0x78, 0xc0, 0xa6, 0x07, 0x12, 0x0f, //0x8200, - 0x02, 0x40, 0x06, 0x78, 0xc0, 0xe6, 0xff, 0x80, 0x04, 0x78, 0xbf, 0xe6, 0xff, 0x78, 0xbe, 0xa6, //0x8210, - 0x07, 0x75, 0x1f, 0x03, 0x78, 0xb8, 0x76, 0x01, 0x80, 0x20, 0xe5, 0x1f, 0x64, 0x03, 0x70, 0x26, //0x8220, - 0x78, 0xbe, 0xe6, 0xff, 0xc3, 0x78, 0xc0, 0x12, 0x0e, 0xe0, 0x40, 0x05, 0x12, 0x0e, 0xda, 0x40, //0x8230, - 0x09, 0x78, 0xb9, 0xe6, 0x78, 0xbe, 0xf6, 0x75, 0x1f, 0x04, 0x78, 0xbe, 0xe6, 0x75, 0xf0, 0x05, //0x8240, - 0xa4, 0xf5, 0x4b, 0x02, 0x0a, 0xff, 0xe5, 0x1f, 0xb4, 0x04, 0x10, 0x90, 0x0e, 0x94, 0xe4, 0x78, //0x8250, - 0xc3, 0x12, 0x0e, 0xe9, 0x40, 0x02, 0xd2, 0x37, 0x75, 0x1f, 0x05, 0x22, 0x30, 0x01, 0x03, 0x02, //0x8260, - 0x04, 0xc0, 0x30, 0x02, 0x03, 0x02, 0x04, 0xc0, 0x90, 0x51, 0xa5, 0xe0, 0x78, 0x93, 0xf6, 0xa3, //0x8270, - 0xe0, 0x08, 0xf6, 0xa3, 0xe0, 0x08, 0xf6, 0xe5, 0x1f, 0x70, 0x3c, 0x75, 0x1e, 0x20, 0xd2, 0x35, //0x8280, - 0x12, 0x0c, 0x7a, 0x78, 0x7e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xa6, 0x09, 0x18, 0x76, //0x8290, - 0x01, 0x12, 0x0c, 0x5b, 0x78, 0x4e, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8b, 0xe6, 0x78, 0x6e, //0x82a0, - 0xf6, 0x75, 0x1f, 0x01, 0x78, 0x93, 0xe6, 0x78, 0x90, 0xf6, 0x78, 0x94, 0xe6, 0x78, 0x91, 0xf6, //0x82b0, - 0x78, 0x95, 0xe6, 0x78, 0x92, 0xf6, 0x22, 0x79, 0x90, 0xe7, 0xd3, 0x78, 0x93, 0x96, 0x40, 0x05, //0x82c0, - 0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x93, 0xe7, 0x78, 0x90, 0x96, 0xff, 0x78, 0x88, 0x76, //0x82d0, - 0x00, 0x08, 0xa6, 0x07, 0x79, 0x91, 0xe7, 0xd3, 0x78, 0x94, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, //0x82e0, - 0x80, 0x08, 0xc3, 0x79, 0x94, 0xe7, 0x78, 0x91, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x79, 0x92, 0xe7, //0x82f0, - 0xd3, 0x78, 0x95, 0x96, 0x40, 0x05, 0xe7, 0x96, 0xff, 0x80, 0x08, 0xc3, 0x79, 0x95, 0xe7, 0x78, //0x8300, - 0x92, 0x96, 0xff, 0x12, 0x0c, 0x8e, 0x12, 0x0c, 0x5b, 0x78, 0x8a, 0xe6, 0x25, 0xe0, 0x24, 0x4e, //0x8310, - 0xf8, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x78, 0x8a, 0xe6, 0x24, 0x6e, 0xf8, 0xa6, 0x09, 0x78, 0x8a, //0x8320, - 0xe6, 0x24, 0x01, 0xff, 0xe4, 0x33, 0xfe, 0xd3, 0xef, 0x94, 0x0f, 0xee, 0x64, 0x80, 0x94, 0x80, //0x8330, - 0x40, 0x04, 0x7f, 0x00, 0x80, 0x05, 0x78, 0x8a, 0xe6, 0x04, 0xff, 0x78, 0x8a, 0xa6, 0x07, 0xe5, //0x8340, - 0x1f, 0xb4, 0x01, 0x0a, 0xe6, 0x60, 0x03, 0x02, 0x04, 0xc0, 0x75, 0x1f, 0x02, 0x22, 0x12, 0x0c, //0x8350, - 0x7a, 0x78, 0x80, 0xa6, 0x06, 0x08, 0xa6, 0x07, 0x12, 0x0c, 0x7a, 0x78, 0x82, 0xa6, 0x06, 0x08, //0x8360, - 0xa6, 0x07, 0x78, 0x6e, 0xe6, 0x78, 0x8c, 0xf6, 0x78, 0x6e, 0xe6, 0x78, 0x8d, 0xf6, 0x7f, 0x01, //0x8370, - 0xef, 0x25, 0xe0, 0x24, 0x4f, 0xf9, 0xc3, 0x78, 0x81, 0xe6, 0x97, 0x18, 0xe6, 0x19, 0x97, 0x50, //0x8380, - 0x0a, 0x12, 0x0c, 0x82, 0x78, 0x80, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0x74, 0x6e, 0x2f, 0xf9, 0x78, //0x8390, - 0x8c, 0xe6, 0xc3, 0x97, 0x50, 0x08, 0x74, 0x6e, 0x2f, 0xf8, 0xe6, 0x78, 0x8c, 0xf6, 0xef, 0x25, //0x83a0, - 0xe0, 0x24, 0x4f, 0xf9, 0xd3, 0x78, 0x83, 0xe6, 0x97, 0x18, 0xe6, 0x19, 0x97, 0x40, 0x0a, 0x12, //0x83b0, - 0x0c, 0x82, 0x78, 0x82, 0xa6, 0x04, 0x08, 0xa6, 0x05, 0x74, 0x6e, 0x2f, 0xf9, 0x78, 0x8d, 0xe6, //0x83c0, - 0xd3, 0x97, 0x40, 0x08, 0x74, 0x6e, 0x2f, 0xf8, 0xe6, 0x78, 0x8d, 0xf6, 0x0f, 0xef, 0x64, 0x10, //0x83d0, - 0x70, 0x9e, 0xc3, 0x79, 0x81, 0xe7, 0x78, 0x83, 0x96, 0xff, 0x19, 0xe7, 0x18, 0x96, 0x78, 0x84, //0x83e0, - 0xf6, 0x08, 0xa6, 0x07, 0xc3, 0x79, 0x8c, 0xe7, 0x78, 0x8d, 0x96, 0x08, 0xf6, 0xd3, 0x79, 0x81, //0x83f0, - 0xe7, 0x78, 0x7f, 0x96, 0x19, 0xe7, 0x18, 0x96, 0x40, 0x05, 0x09, 0xe7, 0x08, 0x80, 0x06, 0xc3, //0x8400, - 0x79, 0x7f, 0xe7, 0x78, 0x81, 0x96, 0xff, 0x19, 0xe7, 0x18, 0x96, 0xfe, 0x78, 0x86, 0xa6, 0x06, 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//0x8940, - 0x12, 0x0d, 0x0d, 0x75, 0x1e, 0x70, 0xd2, 0x35, 0x02, 0x0a, 0x1d, 0x02, 0x0a, 0x04, 0x85, 0x40, //0x8950, - 0x4a, 0x85, 0x3c, 0x4b, 0x12, 0x0a, 0xff, 0x02, 0x0a, 0x1d, 0x85, 0x4a, 0x40, 0x85, 0x4b, 0x3c, //0x8960, - 0x02, 0x0a, 0x1d, 0xe4, 0xf5, 0x22, 0xf5, 0x23, 0x85, 0x40, 0x31, 0x85, 0x3f, 0x30, 0x85, 0x3e, //0x8970, - 0x2f, 0x85, 0x3d, 0x2e, 0x12, 0x0f, 0x46, 0x80, 0x1f, 0x75, 0x22, 0x00, 0x75, 0x23, 0x01, 0x74, //0x8980, - 0xff, 0xf5, 0x2d, 0xf5, 0x2c, 0xf5, 0x2b, 0xf5, 0x2a, 0x12, 0x0f, 0x46, 0x85, 0x2d, 0x40, 0x85, //0x8990, - 0x2c, 0x3f, 0x85, 0x2b, 0x3e, 0x85, 0x2a, 0x3d, 0xe4, 0xf5, 0x3c, 0x80, 0x70, 0x12, 0x0f, 0x16, //0x89a0, - 0x80, 0x6b, 0x85, 0x3d, 0x45, 0x85, 0x3e, 0x46, 0xe5, 0x47, 0xc3, 0x13, 0xff, 0xe5, 0x45, 0xc3, //0x89b0, - 0x9f, 0x50, 0x02, 0x8f, 0x45, 0xe5, 0x48, 0xc3, 0x13, 0xff, 0xe5, 0x46, 0xc3, 0x9f, 0x50, 0x02, //0x89c0, - 0x8f, 0x46, 0xe5, 0x47, 0xc3, 0x13, 0xff, 0xfd, 0xe5, 0x45, 0x2d, 0xfd, 0xe4, 0x33, 0xfc, 0xe5, //0x89d0, - 0x44, 0x12, 0x0f, 0x90, 0x40, 0x05, 0xe5, 0x44, 0x9f, 0xf5, 0x45, 0xe5, 0x48, 0xc3, 0x13, 0xff, //0x89e0, - 0xfd, 0xe5, 0x46, 0x2d, 0xfd, 0xe4, 0x33, 0xfc, 0xe5, 0x43, 0x12, 0x0f, 0x90, 0x40, 0x05, 0xe5, //0x89f0, - 0x43, 0x9f, 0xf5, 0x46, 0x12, 0x06, 0xd7, 0x80, 0x14, 0x85, 0x40, 0x48, 0x85, 0x3f, 0x47, 0x85, //0x8a00, - 0x3e, 0x46, 0x85, 0x3d, 0x45, 0x80, 0x06, 0x02, 0x06, 0xd7, 0x12, 0x0d, 0x7e, 0x90, 0x30, 0x24, //0x8a10, - 0xe5, 0x3d, 0xf0, 0xa3, 0xe5, 0x3e, 0xf0, 0xa3, 0xe5, 0x3f, 0xf0, 0xa3, 0xe5, 0x40, 0xf0, 0xa3, //0x8a20, - 0xe5, 0x3c, 0xf0, 0x90, 0x30, 0x23, 0xe4, 0xf0, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0xc0, //0x8a30, - 0xd0, 0x90, 0x3f, 0x0c, 0xe0, 0xf5, 0x32, 0xe5, 0x32, 0x30, 0xe3, 0x74, 0x30, 0x36, 0x66, 0x90, //0x8a40, - 0x60, 0x19, 0xe0, 0xf5, 0x0a, 0xa3, 0xe0, 0xf5, 0x0b, 0x90, 0x60, 0x1d, 0xe0, 0xf5, 0x14, 0xa3, //0x8a50, - 0xe0, 0xf5, 0x15, 0x90, 0x60, 0x21, 0xe0, 0xf5, 0x0c, 0xa3, 0xe0, 0xf5, 0x0d, 0x90, 0x60, 0x29, //0x8a60, - 0xe0, 0xf5, 0x0e, 0xa3, 0xe0, 0xf5, 0x0f, 0x90, 0x60, 0x31, 0xe0, 0xf5, 0x10, 0xa3, 0xe0, 0xf5, //0x8a70, - 0x11, 0x90, 0x60, 0x39, 0xe0, 0xf5, 0x12, 0xa3, 0xe0, 0xf5, 0x13, 0x30, 0x01, 0x06, 0x30, 0x33, //0x8a80, - 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x09, 0x30, 0x02, 0x06, 0x30, 0x33, 0x03, 0xd3, 0x80, 0x01, //0x8a90, - 0xc3, 0x92, 0x0a, 0x30, 0x33, 0x0c, 0x30, 0x03, 0x09, 0x20, 0x02, 0x06, 0x20, 0x01, 0x03, 0xd3, //0x8aa0, - 0x80, 0x01, 0xc3, 0x92, 0x0b, 0x90, 0x30, 0x01, 0xe0, 0x44, 0x40, 0xf0, 0xe0, 0x54, 0xbf, 0xf0, //0x8ab0, - 0xe5, 0x32, 0x30, 0xe1, 0x14, 0x30, 0x34, 0x11, 0x90, 0x30, 0x22, 0xe0, 0xf5, 0x08, 0xe4, 0xf0, //0x8ac0, - 0x30, 0x00, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x08, 0xe5, 0x32, 0x30, 0xe5, 0x12, 0x90, 0x56, //0x8ad0, - 0xa1, 0xe0, 0xf5, 0x09, 0x30, 0x31, 0x09, 0x30, 0x05, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x92, 0x0d, //0x8ae0, - 0x90, 0x3f, 0x0c, 0xe5, 0x32, 0xf0, 0xd0, 0xd0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, //0x8af0, - 0x0e, 0x7e, 0xe4, 0x93, 0xfe, 0x74, 0x01, 0x93, 0xff, 0xc3, 0x90, 0x0e, 0x7c, 0x74, 0x01, 0x93, //0x8b00, - 0x9f, 0xff, 0xe4, 0x93, 0x9e, 0xfe, 0xe4, 0x8f, 0x3b, 0x8e, 0x3a, 0xf5, 0x39, 0xf5, 0x38, 0xab, //0x8b10, - 0x3b, 0xaa, 0x3a, 0xa9, 0x39, 0xa8, 0x38, 0xaf, 0x4b, 0xfc, 0xfd, 0xfe, 0x12, 0x05, 0x28, 0x12, //0x8b20, - 0x0d, 0xe1, 0xe4, 0x7b, 0xff, 0xfa, 0xf9, 0xf8, 0x12, 0x05, 0xb3, 0x12, 0x0d, 0xe1, 0x90, 0x0e, //0x8b30, - 0x69, 0xe4, 0x12, 0x0d, 0xf6, 0x12, 0x0d, 0xe1, 0xe4, 0x85, 0x4a, 0x37, 0xf5, 0x36, 0xf5, 0x35, //0x8b40, - 0xf5, 0x34, 0xaf, 0x37, 0xae, 0x36, 0xad, 0x35, 0xac, 0x34, 0xa3, 0x12, 0x0d, 0xf6, 0x8f, 0x37, //0x8b50, - 0x8e, 0x36, 0x8d, 0x35, 0x8c, 0x34, 0xe5, 0x3b, 0x45, 0x37, 0xf5, 0x3b, 0xe5, 0x3a, 0x45, 0x36, //0x8b60, - 0xf5, 0x3a, 0xe5, 0x39, 0x45, 0x35, 0xf5, 0x39, 0xe5, 0x38, 0x45, 0x34, 0xf5, 0x38, 0xe4, 0xf5, //0x8b70, - 0x22, 0xf5, 0x23, 0x85, 0x3b, 0x31, 0x85, 0x3a, 0x30, 0x85, 0x39, 0x2f, 0x85, 0x38, 0x2e, 0x02, //0x8b80, - 0x0f, 0x46, 0xe0, 0xa3, 0xe0, 0x75, 0xf0, 0x02, 0xa4, 0xff, 0xae, 0xf0, 0xc3, 0x08, 0xe6, 0x9f, //0x8b90, - 0xf6, 0x18, 0xe6, 0x9e, 0xf6, 0x22, 0xff, 0xe5, 0xf0, 0x34, 0x60, 0x8f, 0x82, 0xf5, 0x83, 0xec, //0x8ba0, - 0xf0, 0x22, 0x78, 0x52, 0x7e, 0x00, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x02, 0x04, 0xc1, 0xe4, 0xfc, //0x8bb0, - 0xfd, 0x12, 0x06, 0x99, 0x78, 0x5c, 0xe6, 0xc3, 0x13, 0xfe, 0x08, 0xe6, 0x13, 0x22, 0x78, 0x52, //0x8bc0, - 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0xe4, 0xfc, 0xfd, 0x22, 0xe7, 0xc4, 0xf8, 0x54, 0xf0, 0xc8, 0x68, //0x8bd0, - 0xf7, 0x09, 0xe7, 0xc4, 0x54, 0x0f, 0x48, 0xf7, 0x22, 0xe6, 0xfc, 0xed, 0x75, 0xf0, 0x04, 0xa4, //0x8be0, - 0x22, 0x12, 0x06, 0x7c, 0x8f, 0x48, 0x8e, 0x47, 0x8d, 0x46, 0x8c, 0x45, 0x22, 0xe0, 0xfe, 0xa3, //0x8bf0, - 0xe0, 0xfd, 0xee, 0xf6, 0xed, 0x08, 0xf6, 0x22, 0x13, 0xff, 0xc3, 0xe6, 0x9f, 0xff, 0x18, 0xe6, //0x8c00, - 0x9e, 0xfe, 0x22, 0xe6, 0xc3, 0x13, 0xf7, 0x08, 0xe6, 0x13, 0x09, 0xf7, 0x22, 0xad, 0x39, 0xac, //0x8c10, - 0x38, 0xfa, 0xf9, 0xf8, 0x12, 0x05, 0x28, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0xab, //0x8c20, - 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//0x8d80, + 0xe5, 0x3d, 0x34, 0x28, 0xf5, 0x34, 0xe5, 0x37, 0xff, 0xe4, 0xfe, 0xfd, 0xfc, 0x78, 0x18, 0x12, //0x8d90, + 0x06, 0x69, 0x8f, 0x40, 0x8e, 0x3f, 0x8d, 0x3e, 0x8c, 0x3d, 0xe5, 0x37, 0x54, 0xa0, 0xff, 0xe5, //0x8da0, + 0x36, 0xfe, 0xe4, 0xfd, 0xfc, 0x78, 0x07, 0x12, 0x06, 0x56, 0x78, 0x10, 0x12, 0x0f, 0x9a, 0xe4, //0x8db0, + 0xff, 0xfe, 0xe5, 0x35, 0xfd, 0xe4, 0xfc, 0x78, 0x0e, 0x12, 0x06, 0x56, 0x12, 0x0f, 0x9d, 0xe4, //0x8dc0, + 0xff, 0xfe, 0xfd, 0xe5, 0x34, 0xfc, 0x78, 0x18, 0x12, 0x06, 0x56, 0x78, 0x08, 0x12, 0x0f, 0x9a, //0x8dd0, + 0x22, 0x8f, 0x3b, 0x8e, 0x3a, 0x8d, 0x39, 0x8c, 0x38, 0x22, 0x12, 0x06, 0x7c, 0x8f, 0x31, 0x8e, //0x8de0, + 0x30, 0x8d, 0x2f, 0x8c, 0x2e, 0x22, 0x93, 0xf9, 0xf8, 0x02, 0x06, 0x69, 0x00, 0x00, 0x00, 0x00, //0x8df0, + 0x12, 0x01, 0x17, 0x08, 0x31, 0x15, 0x53, 0x54, 0x44, 0x20, 0x20, 0x20, 0x20, 0x20, 0x13, 0x01, //0x8e00, + 0x10, 0x01, 0x56, 0x40, 0x1a, 0x30, 0x29, 0x7e, 0x00, 0x30, 0x04, 0x20, 0xdf, 0x30, 0x05, 0x40, //0x8e10, + 0xbf, 0x50, 0x03, 0x00, 0xfd, 0x50, 0x27, 0x01, 0xfe, 0x60, 0x00, 0x11, 0x00, 0x3f, 0x05, 0x30, //0x8e20, + 0x00, 0x3f, 0x06, 0x22, 0x00, 0x3f, 0x01, 0x2a, 0x00, 0x3f, 0x02, 0x00, 0x00, 0x36, 0x06, 0x07, //0x8e30, + 0x00, 0x3f, 0x0b, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x01, 0x40, 0xbf, 0x30, 0x01, 0x00, //0x8e40, + 0xbf, 0x30, 0x29, 0x70, 0x00, 0x3a, 0x00, 0x00, 0xff, 0x3a, 0x00, 0x00, 0xff, 0x36, 0x03, 0x36, //0x8e50, + 0x02, 0x41, 0x44, 0x58, 0x20, 0x18, 0x10, 0x0a, 0x04, 0x04, 0x00, 0x03, 0xff, 0x64, 0x00, 0x00, //0x8e60, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x06, 0x06, 0x00, 0x03, 0x51, 0x00, 0x7a, //0x8e70, + 0x50, 0x3c, 0x28, 0x1e, 0x10, 0x10, 0x50, 0x2d, 0x28, 0x16, 0x10, 0x10, 0x02, 0x00, 0x10, 0x0c, //0x8e80, + 0x10, 0x04, 0x0c, 0x6e, 0x06, 0x05, 0x00, 0xa5, 0x5a, 0x00, 0xae, 0x35, 0xaf, 0x36, 0xe4, 0xfd, //0x8e90, + 0xed, 0xc3, 0x95, 0x37, 0x50, 0x33, 0x12, 0x0f, 0xe2, 0xe4, 0x93, 0xf5, 0x38, 0x74, 0x01, 0x93, //0x8ea0, + 0xf5, 0x39, 0x45, 0x38, 0x60, 0x23, 0x85, 0x39, 0x82, 0x85, 0x38, 0x83, 0xe0, 0xfc, 0x12, 0x0f, //0x8eb0, + 0xe2, 0x74, 0x03, 0x93, 0x52, 0x04, 0x12, 0x0f, 0xe2, 0x74, 0x02, 0x93, 0x42, 0x04, 0x85, 0x39, //0x8ec0, + 0x82, 0x85, 0x38, 0x83, 0xec, 0xf0, 0x0d, 0x80, 0xc7, 0x22, 0x78, 0xbe, 0xe6, 0xd3, 0x08, 0xff, //0x8ed0, + 0xe6, 0x64, 0x80, 0xf8, 0xef, 0x64, 0x80, 0x98, 0x22, 0x93, 0xff, 0x7e, 0x00, 0xe6, 0xfc, 0x08, //0x8ee0, + 0xe6, 0xfd, 0x12, 0x04, 0xc1, 0x78, 0xc1, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0xd3, 0xef, 0x9d, 0xee, //0x8ef0, + 0x9c, 0x22, 0x78, 0xbd, 0xd3, 0xe6, 0x64, 0x80, 0x94, 0x80, 0x22, 0x25, 0xe0, 0x24, 0x0a, 0xf8, //0x8f00, + 0xe6, 0xfe, 0x08, 0xe6, 0xff, 0x22, 0xe5, 0x3c, 0xd3, 0x94, 0x00, 0x40, 0x0b, 0x90, 0x0e, 0x88, //0x8f10, + 0x12, 0x0b, 0xf1, 0x90, 0x0e, 0x86, 0x80, 0x09, 0x90, 0x0e, 0x82, 0x12, 0x0b, 0xf1, 0x90, 0x0e, //0x8f20, + 0x80, 0xe4, 0x93, 0xf5, 0x44, 0xa3, 0xe4, 0x93, 0xf5, 0x43, 0xd2, 0x06, 0x30, 0x06, 0x03, 0xd3, //0x8f30, + 0x80, 0x01, 0xc3, 0x92, 0x0e, 0x22, 0xa2, 0xaf, 0x92, 0x32, 0xc2, 0xaf, 0xe5, 0x23, 0x45, 0x22, //0x8f40, + 0x90, 0x0e, 0x5d, 0x60, 0x0e, 0x12, 0x0f, 0xcb, 0xe0, 0xf5, 0x2c, 0x12, 0x0f, 0xc8, 0xe0, 0xf5, //0x8f50, + 0x2d, 0x80, 0x0c, 0x12, 0x0f, 0xcb, 0xe5, 0x30, 0xf0, 0x12, 0x0f, 0xc8, 0xe5, 0x31, 0xf0, 0xa2, //0x8f60, + 0x32, 0x92, 0xaf, 0x22, 0xd2, 0x01, 0xc2, 0x02, 0xe4, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, //0x8f70, + 0x33, 0xd2, 0x36, 0xd2, 0x01, 0xc2, 0x02, 0xf5, 0x1f, 0xf5, 0x1e, 0xd2, 0x35, 0xd2, 0x33, 0x22, //0x8f80, + 0xfb, 0xd3, 0xed, 0x9b, 0x74, 0x80, 0xf8, 0x6c, 0x98, 0x22, 0x12, 0x06, 0x69, 0xe5, 0x40, 0x2f, //0x8f90, + 0xf5, 0x40, 0xe5, 0x3f, 0x3e, 0xf5, 0x3f, 0xe5, 0x3e, 0x3d, 0xf5, 0x3e, 0xe5, 0x3d, 0x3c, 0xf5, //0x8fa0, + 0x3d, 0x22, 0xc0, 0xe0, 0xc0, 0x83, 0xc0, 0x82, 0x90, 0x3f, 0x0d, 0xe0, 0xf5, 0x33, 0xe5, 0x33, //0x8fb0, + 0xf0, 0xd0, 0x82, 0xd0, 0x83, 0xd0, 0xe0, 0x32, 0x90, 0x0e, 0x5f, 0xe4, 0x93, 0xfe, 0x74, 0x01, //0x8fc0, + 0x93, 0xf5, 0x82, 0x8e, 0x83, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8, 0xfd, 0x75, 0x81, 0xcd, 0x02, //0x8fd0, + 0x0c, 0x98, 0x8f, 0x82, 0x8e, 0x83, 0x75, 0xf0, 0x04, 0xed, 0x02, 0x06, 0xa5, //0x8fe0 +}; #ifdef __cplusplus } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c index 174fd3bdac..3d4e2f18b8 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,12 +29,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8 struct rt_i2c_msg msg[2] = {0, 0}; RT_ASSERT(bus != RT_NULL); - + msg[0].addr = STPMU1_I2C_ADDRESS; /* Slave address */ msg[0].flags = RT_I2C_WR; /* Write flag */ msg[0].buf = ® /* Slave register address */ msg[0].len = 1; /* Number of bytes sent */ - + msg[1].addr = STPMU1_I2C_ADDRESS; msg[1].flags = RT_I2C_RD; msg[1].len = len; @@ -55,7 +55,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint struct rt_i2c_msg msgs; RT_ASSERT(bus != RT_NULL); - + buf[0] = reg; //cmd buf[1] = data; @@ -85,7 +85,7 @@ static rt_err_t stpmu1_read_reg(uint8_t register_id) { Error_Handler(); } - + return result; } @@ -93,7 +93,7 @@ static void stpmu1_write_reg(uint8_t register_id, uint8_t value) { uint32_t status = RT_EOK; uint8_t readval = 0; - + status = write_reg(pmic_dev, register_id, (rt_uint8_t)value); /* Check the communication status */ @@ -120,7 +120,7 @@ static uint32_t BSP_PMIC_MspInit(void) __HAL_RCC_GPIOA_CLK_ENABLE(); GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Alternate = 0 ; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -619,7 +619,7 @@ static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t miliv uint8_t i; for ( i = 0 ; i < regul->voltage_table_size ; i++) { - if ( regul->voltage_table[i] == milivolts ) + if ( regul->voltage_table[i] == milivolts ) { LOG_D("idx:%d for %dmV\n\r", (int)i, (int)milivolts); return i; @@ -716,7 +716,7 @@ void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn) LOG_I(" Interrupt received\n\r"); } -void STPMU1_INTn_Callback(PMIC_IRQn IRQn) +void STPMU1_INTn_Callback(PMIC_IRQn IRQn) { BSP_PMIC_INTn_Callback(IRQn); } @@ -846,15 +846,15 @@ static rt_err_t rt_hw_pmic_init_register(void) static rt_err_t rt_hw_pmic_init(const char *bus_name) { PMIC_IRQn irq; - + pmic_dev = rt_i2c_bus_device_find(bus_name); - + if (pmic_dev == RT_NULL) { LOG_E("%s bus not found\n", bus_name); return -RT_ERROR; } - + if (stpmu1_read_reg(VERSION_STATUS_REG) != PMIC_VERSION_ID) { return -RT_EIO; @@ -863,7 +863,7 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name) STPMU1_Enable_Interrupt(IT_PONKEY_R); STPMU1_Enable_Interrupt(IT_PONKEY_F); /* enable all irqs */ - for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) + for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) { STPMU1_Enable_Interrupt(irq); } @@ -874,18 +874,18 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name) static rt_err_t rt_hw_pmic_deinit(void) { BSP_PMIC_MspDeInit(); - + return RT_EOK; } static int pmic_init(void) { rt_err_t result = RT_EOK; - + if (IS_ENGINEERING_BOOT_MODE()) { BSP_PMIC_MspInit(); - + result = rt_hw_pmic_init(I2C_NAME); if(result != RT_EOK) { @@ -893,12 +893,12 @@ static int pmic_init(void) rt_hw_pmic_deinit(); return RT_ERROR; } - + rt_hw_pmic_init_register(); } - + LOG_I("stpmic init success!"); - + return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h index b24ccaeaf3..72c4af3a49 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pmic.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -98,7 +98,7 @@ typedef struct { /* Those define should reflect NVM_USER section * For ES Eval Configuration this is specified as - * 0xF7, + * 0xF7, 0x92, 0xC0, 0x02, @@ -146,12 +146,12 @@ typedef struct { * */ -#define OTP_VINOK_HYST ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) // nvm_vinok_hyst -#define OTP_VINOK ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) // nvm_vinok -#define OTP_LDO4_FORCED ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) // Otp_ldo4_forced -#define OTP_LONGKEYPRESSED ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2) // nvm_longkeypress -#define OTP_AUTOTURNON ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1) // nvm_autoturnon -#define OTP_CC_KEEPOFF ((NVM_SECTOR3_REGISTER_0 & 0x01)) // nvm_cc_keepoff +#define OTP_VINOK_HYST ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) // nvm_vinok_hyst +#define OTP_VINOK ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) // nvm_vinok +#define OTP_LDO4_FORCED ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) // Otp_ldo4_forced +#define OTP_LONGKEYPRESSED ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2) // nvm_longkeypress +#define OTP_AUTOTURNON ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1) // nvm_autoturnon +#define OTP_CC_KEEPOFF ((NVM_SECTOR3_REGISTER_0 & 0x01)) // nvm_cc_keepoff /* * nvm_rank_buck4: @@ -176,10 +176,10 @@ typedef struct { 11: rank3 * */ -#define OTP_RANK_BUCK4 ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) // nvm_rank_buck4 -#define OTP_RANK_BUCK3 ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) // nvm_rank_buck3 -#define OTP_RANK_BUCK2 ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) // nvm_rank_buck2 -#define OTP_RANK_BUCK1 ((NVM_SECTOR3_REGISTER_1 & 0x03)) // nvm_rank_buck1 +#define OTP_RANK_BUCK4 ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) // nvm_rank_buck4 +#define OTP_RANK_BUCK3 ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) // nvm_rank_buck3 +#define OTP_RANK_BUCK2 ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) // nvm_rank_buck2 +#define OTP_RANK_BUCK1 ((NVM_SECTOR3_REGISTER_1 & 0x03)) // nvm_rank_buck1 /* @@ -205,10 +205,10 @@ typedef struct { 11: rank3 * */ -#define OTP_RANK_LDO4 ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) // nvm_rank_ldo4 -#define OTP_RANK_LDO3 ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) // nvm_rank_ldo3 -#define OTP_RANK_LDO2 ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) // nvm_rank_ldo2 -#define OTP_RANK_LDO1 ((NVM_SECTOR3_REGISTER_2 & 0x03)) // nvm_rank_ldo1 +#define OTP_RANK_LDO4 ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) // nvm_rank_ldo4 +#define OTP_RANK_LDO3 ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) // nvm_rank_ldo3 +#define OTP_RANK_LDO2 ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) // nvm_rank_ldo2 +#define OTP_RANK_LDO1 ((NVM_SECTOR3_REGISTER_2 & 0x03)) // nvm_rank_ldo1 /* * nvm_clamp_output_buck: Clamp output value to 1.3V max @@ -238,11 +238,11 @@ nvm_rank_ldo5: 11: rank3 * */ -#define OTP_CLAMP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) // nvm_clamp_output_buck4 -#define OTP_BYPASS_MODE_LDO3 ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) // nvm_bypass_mode_ldo3 -#define OTP_RANK_VREFDDR ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) // nvm_rank_vrefddr -#define OTP_RANK_LDO6 ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) // nvm_rank_ldo6 -#define OTP_RANK_LDO5 ((NVM_SECTOR3_REGISTER_3 & 0x03)) // nvm_rank_ldo5 +#define OTP_CLAMP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) // nvm_clamp_output_buck4 +#define OTP_BYPASS_MODE_LDO3 ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) // nvm_bypass_mode_ldo3 +#define OTP_RANK_VREFDDR ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) // nvm_rank_vrefddr +#define OTP_RANK_LDO6 ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) // nvm_rank_ldo6 +#define OTP_RANK_LDO5 ((NVM_SECTOR3_REGISTER_3 & 0x03)) // nvm_rank_ldo5 /* * nvm_output_buck4: Buck4 default output selection @@ -267,31 +267,31 @@ nvm_rank_ldo5: 11: 1.25V * */ -#define OTP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) // nvm_output_buck4 -#define OTP_OUTPUT_BUCK3 ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) // nvm_output_buck3 -#define OTP_OUTPUT_BUCK2 ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) // nvm_output_buck2 -#define OTP_OUTPUT_BUCK1 ((NVM_SECTOR3_REGISTER_4 & 0x03)) // nvm_output_buck1 +#define OTP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) // nvm_output_buck4 +#define OTP_OUTPUT_BUCK3 ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) // nvm_output_buck3 +#define OTP_OUTPUT_BUCK2 ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) // nvm_output_buck2 +#define OTP_OUTPUT_BUCK1 ((NVM_SECTOR3_REGISTER_4 & 0x03)) // nvm_output_buck1 /* - * [7] OTP_SWOFF_BY_BOOST_OVP: + * [7] OTP_SWOFF_BY_BOOST_OVP: 0 -> SWOUT will not turnoff bu boost OVP 1 -> SWOUT will be turnoff by BOOST OVP - [6] reserved + [6] reserved - [5:4] nvm_output_ldo3: LDO3 default output selection + [5:4] nvm_output_ldo3: LDO3 default output selection 00: 1.8V 01: 2.5V 10: 3.3V 11: output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog) - [3:2] nvm_output_ldo2: LDO2 default output selection + [3:2] nvm_output_ldo2: LDO2 default output selection 00: 1.8V 01: 2.5V 10: 2.9V 11: 3.3V - [1:0] nvm_output_ldo1: LDO1 default output selection + [1:0] nvm_output_ldo1: LDO1 default output selection 00: 1.8V 01: 2.5V 10: 2.9V @@ -299,21 +299,21 @@ nvm_rank_ldo5: * */ -#define OTP_SWOFF_BY_BOOST_OVP ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) // OTP_SWOFF_BY_BOOST_OVP -#define OTP_OUTPUT_LDO3 ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) // nvm_output_ldo3 -#define OTP_OUTPUT_LDO2 ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) // nvm_output_ldo2 -#define OTP_OUTPUT_LDO1 ((NVM_SECTOR3_REGISTER_5 & 0x03)) // nvm_output_ldo1 +#define OTP_SWOFF_BY_BOOST_OVP ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) // OTP_SWOFF_BY_BOOST_OVP +#define OTP_OUTPUT_LDO3 ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) // nvm_output_ldo3 +#define OTP_OUTPUT_LDO2 ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) // nvm_output_ldo2 +#define OTP_OUTPUT_LDO1 ((NVM_SECTOR3_REGISTER_5 & 0x03)) // nvm_output_ldo1 /* - * [7:4] reserved + * [7:4] reserved * - [3:2] nvm_output_ldo6: LDO6 default output selection + [3:2] nvm_output_ldo6: LDO6 default output selection 00: 1.0V 01: 1.2V 10: 1.8V 11: 3.3V - [1:0] nvm_output_ldo5: LDO5 default output selection + [1:0] nvm_output_ldo5: LDO5 default output selection 00: 1.8V 01: 2.5V 10: 2.9V @@ -321,8 +321,8 @@ nvm_rank_ldo5: * */ -#define OTP_OUTPUT_LDO6 ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) // nvm_output_ldo6 -#define OTP_OUTPUT_LDO5 ((NVM_SECTOR3_REGISTER_6 & 0x03)) // nvm_output_ldo5 +#define OTP_OUTPUT_LDO6 ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) // nvm_output_ldo6 +#define OTP_OUTPUT_LDO5 ((NVM_SECTOR3_REGISTER_6 & 0x03)) // nvm_output_ldo5 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define BIT(_x) (1<<(_x)) @@ -417,7 +417,7 @@ nvm_rank_ldo5: #define LDO_BUCK_PULL_DOWN_MASK 0x03 -/* Main PMIC Control Register +/* Main PMIC Control Register * MAIN_CONTROL_REG * Address : 0x10 * */ @@ -427,7 +427,7 @@ nvm_rank_ldo5: #define RESTART_REQUEST_ENABLED BIT(1) #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) -/* Main PMIC PADS Control Register +/* Main PMIC PADS Control Register * PADS_PULL_REG * Address : 0x11 * */ @@ -438,7 +438,7 @@ nvm_rank_ldo5: #define PONKEY_PU_ACTIVE BIT(0) -/* Main PMIC VINLOW Control Register +/* Main PMIC VINLOW Control Register * VIN_CONTROL_REGC DMSC * Address : 0x15 * */ @@ -452,7 +452,7 @@ nvm_rank_ldo5: #define VINLOW_CTRL_REG_MASK 0xFF -/* USB Control Register +/* USB Control Register * Address : 0x40 * */ #define BOOST_OVP_DISABLED BIT(7) diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c index 3aac57603d..a98b280f1b 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_pwr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c index 70fa977359..7f716c1dae 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_qspi_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2020-07-07 thread-liu first version */ - + #include #include #include @@ -29,7 +29,7 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(hqspi->Instance==QUADSPI) { /* USER CODE BEGIN QUADSPI_MspInit 0 */ @@ -45,16 +45,16 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PF6 ------> QUADSPI_BK1_IO3 PF7 ------> QUADSPI_BK1_IO2 PF8 ------> QUADSPI_BK1_IO0 PF9 ------> QUADSPI_BK1_IO1 PF10 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -62,14 +62,14 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -104,14 +104,14 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; GPIO_InitStruct.Alternate = GPIO_AF11_QUADSPI; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - + /* USER CODE BEGIN QUADSPI_MspInit 1 */ /* USER CODE END QUADSPI_MspInit 1 */ @@ -133,8 +133,8 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PC0 ------> QUADSPI_BK2_NCS PF10 ------> QUADSPI_CLK PB6 ------> QUADSPI_BK1_NCS @@ -145,10 +145,10 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) PF6 ------> QUADSPI_BK1_IO3 PH2 ------> QUADSPI_BK2_IO0 PF8 ------> QUADSPI_BK1_IO0 - PF9 ------> QUADSPI_BK1_IO1 + PF9 ------> QUADSPI_BK1_IO1 */ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); - + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); @@ -156,7 +156,7 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) HAL_GPIO_DeInit(GPIOH, GPIO_PIN_3|GPIO_PIN_2); HAL_GPIO_DeInit(GPIOG, GPIO_PIN_7|GPIO_PIN_10); - + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ /* USER CODE END QUADSPI_MspDeInit 1 */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c index 44eba3be91..78475ec7e8 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ static rt_err_t rs485_output(rt_device_t dev, void * buffer) static rt_err_t rs485_input(rt_device_t dev, rt_size_t size) { rt_sem_release(&rx_sem); - + return RT_EOK; } @@ -38,13 +38,13 @@ int rs485_send_data(char *tbuf, rt_uint16_t t_len) { /* change rs485 mode */ RS485_OUT; - + /* send data */ rt_device_write(serial, 0, tbuf, t_len); - + /* change rs485 mode */ RS485_IN; - + return RT_EOK; } @@ -59,10 +59,10 @@ static void rs485_thread_entry(void *parameter) { rt_sem_take(&rx_sem, RT_WAITING_FOREVER); } - + /* The data read through the serial port output dislocation */ ch = ch + 1; - + /* send char */ rs485_send_data(&ch, 1); } @@ -77,20 +77,20 @@ static int rs485_init(void) { rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME); return RT_ERROR; - } + } rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); /* set receive data callback function */ rt_device_set_rx_indicate(serial, rs485_input); - + /* set the send completion callback function */ rt_device_set_tx_complete(serial, rs485_output); - + rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT); - + RS485_IN; - + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); /* create rs485 thread */ rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10); @@ -103,8 +103,8 @@ static int rs485_init(void) { return RT_ERROR; } - - return RT_EOK; + + return RT_EOK; } INIT_DEVICE_EXPORT(rs485_init); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h index 01edf84ae8..0d9767ac04 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_rs485.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ extern "C" { #define RS485_SEND_MODE 0 #define RS485_RECV_MODE 1 - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c index 3ef28f4e85..bb6e92584f 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sdcard.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ struct stm32_sd struct rt_semaphore sd_lock; volatile rt_uint8_t write_flage; volatile rt_uint8_t read_flage; - volatile rt_base_t level; + volatile rt_base_t level; }; static struct stm32_sd sd_device; @@ -47,7 +47,7 @@ __attribute__((at(SDCARD_ADDR))) static rt_uint32_t cache_buf[SDIO_BUFF_SIZE]; #elif defined ( __GNUC__ ) static rt_uint32_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection"))); #elif defined(__ICCARM__) -#pragma location = SDCARD_ADDR +#pragma location = SDCARD_ADDR __no_init static rt_uint32_t cache_buf[SDIO_BUFF_SIZE]; #endif @@ -79,7 +79,7 @@ static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) static rt_err_t rt_hw_sd_is_detected(void) { - return rt_pin_read(DETECT_PIN); + return rt_pin_read(DETECT_PIN); } static rt_err_t rt_hw_sd_init(void) @@ -94,46 +94,46 @@ static rt_err_t rt_hw_sd_init(void) LOG_E("can't find sd card!"); return RT_ERROR; } - + SDCARD_Handler.Instance = SDMMC1; HAL_SD_DeInit(&SDCARD_Handler); - + /* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock - else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV]. + else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV]. SDMMC Kernel Clock = 99MHz, SDMMC Clock frequency = 50MHz */ - + SDCARD_Handler.Init.ClockDiv = 1; - SDCARD_Handler.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; - SDCARD_Handler.Init.ClockEdge = SDMMC_CLOCK_EDGE_FALLING; - SDCARD_Handler.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - SDCARD_Handler.Init.BusWide = SDMMC_BUS_WIDE_4B; - + SDCARD_Handler.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + SDCARD_Handler.Init.ClockEdge = SDMMC_CLOCK_EDGE_FALLING; + SDCARD_Handler.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + SDCARD_Handler.Init.BusWide = SDMMC_BUS_WIDE_4B; + if (HAL_SD_Init(&SDCARD_Handler) != RT_EOK) { LOG_E("sd device init error!"); - return RT_ERROR; + return RT_ERROR; } if (HAL_SD_ConfigWideBusOperation(&SDCARD_Handler, SDMMC_BUS_WIDE_4B) != RT_EOK) { LOG_E("sd bus config error!"); - return RT_ERROR; + return RT_ERROR; } if (HAL_SD_GetCardInfo(&SDCARD_Handler, &SDCardInfo) != RT_EOK) { LOG_E("sd get card info error!"); - return RT_ERROR; + return RT_ERROR; } - + rt_thread_mdelay(100); - + if(HAL_SD_GetCardState(&SDCARD_Handler) != HAL_SD_CARD_TRANSFER) { LOG_E("sd get card state error!"); - return RT_ERROR; + return RT_ERROR; } - + return RT_EOK; } @@ -145,7 +145,7 @@ static void rt_hw_sd_deinit(void) static rt_err_t sdcard_wait_ok(void) { rt_uint32_t tick_start = 0; - + tick_start = rt_tick_get(); while ((rt_tick_get() - tick_start) < SD_TIMEOUT) { @@ -166,19 +166,19 @@ void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) else { rt_pin_write(LDO_PIN, PIN_LOW); - } + } } static rt_err_t rt_sdcard_init(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); struct stm32_sd *sd = (struct stm32_sd *)dev; - + if (rt_sem_init(&sd->sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) { LOG_E("init sd lock semaphore failed\n"); } - + return RT_EOK; } @@ -207,24 +207,24 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer, { RT_ASSERT(dev != RT_NULL); struct stm32_sd *sd = (struct stm32_sd *)dev; - + rt_uint8_t ret = RT_EOK; volatile uint32_t tickstart = 0; sd->read_flage = 0; - + rt_memset(cache_buf, 0x00, BLOCKSIZE * count); - + ret = sdcard_wait_ok(); if (ret != RT_EOK) { LOG_D("sdmmc busy!"); return 0; } - + rt_sem_take(&sd->sd_lock, RT_WAITING_FOREVER); ret = HAL_SD_ReadBlocks_DMA(&SDCARD_Handler, (rt_uint8_t *)cache_buf, (uint32_t)sector, count); rt_sem_release(&sd->sd_lock); - + /* Wait that writing process is completed or a timeout occurs */ tickstart = rt_tick_get(); if (ret == HAL_OK) @@ -247,7 +247,7 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer, { sd->level=rt_hw_interrupt_disable(); rt_memcpy((rt_uint8_t *)(buffer), cache_buf, BLOCKSIZE * count); - rt_hw_interrupt_enable(sd->level); + rt_hw_interrupt_enable(sd->level); #if defined(SDMMC_RX_DUMP) rt_kprintf("\nsd rx: \n"); dump_hex(cache_buf, BLOCKSIZE * count); @@ -257,7 +257,7 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t sector, void *buffer, } } } - + return 0; } @@ -275,14 +275,14 @@ static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *b struct stm32_sd *sd = (struct stm32_sd *)dev; rt_uint32_t i = 0; rt_uint8_t ret = RT_EOK; - + for (i = 0; i < count; i++) { sd->level = rt_hw_interrupt_disable(); rt_memset(cache_buf, 0x00, BLOCKSIZE); rt_memcpy(cache_buf, (rt_uint32_t *)((uintptr_t)buffer + BLOCKSIZE * i), BLOCKSIZE); rt_hw_interrupt_enable(sd->level); - + #if defined(SDMMC_TX_DUMP) rt_kprintf("\nsd tx: \n"); dump_hex(cache_buf, BLOCKSIZE); @@ -303,14 +303,14 @@ static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t sector, const void *b rt_completion_wait(&tx_comp,RT_WAITING_FOREVER); } - + return count; } static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) { RT_ASSERT(dev != RT_NULL); - + if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) { struct rt_device_blk_geometry *geometry; @@ -372,9 +372,9 @@ int rt_hw_sdcard_init(void) sd_device.sdcard.user_data = &SDCardInfo; rt_device_register(&sd_device.sdcard, "sd_card", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - + LOG_I("sd card init success!"); - + return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_sdcard_init); @@ -383,7 +383,7 @@ INIT_DEVICE_EXPORT(rt_hw_sdcard_init); int mnt_init(void) { rt_device_t sd_dev = RT_NULL; - + LOG_I("init sd card file system."); #if defined(SDMMC_RX_DUMP) || defined(SDMMC_TX_DUMP) rt_thread_delay(3000); @@ -396,7 +396,7 @@ int mnt_init(void) LOG_E("can't find sd deivce name!"); return RT_ERROR; } - + if (dfs_mount("sd_card", "/", "elm", 0, 0) != 0) { rt_kprintf("file system mount failed!\n"); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c index 14efc094e5..4aee045825 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_sound.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ struct sound_device { struct rt_audio_device audio; struct rt_audio_configure replay_config; - rt_device_t decoder; + rt_device_t decoder; rt_uint8_t *tx_fifo; rt_uint8_t volume; }; @@ -70,7 +70,7 @@ static void rt_hw_sai2a_init(void) hsai_BlockA2.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; hsai_BlockA2.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; hsai_BlockA2.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - + hsai_BlockA2.SlotInit.FirstBitOffset = 0; hsai_BlockA2.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE; hsai_BlockA2.SlotInit.SlotNumber = 2; @@ -218,7 +218,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap return result; } - + static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) { rt_err_t result = RT_EOK; @@ -238,9 +238,9 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c rt_uint8_t volume = caps->udata.value; rt_device_control(snd_dev->decoder, SET_VOLUME, &volume); - + snd_dev->volume = volume; - + LOG_D("set volume %d", volume); break; } @@ -315,16 +315,16 @@ static rt_err_t sound_init(struct rt_audio_device *audio) rt_err_t result = RT_EOK; struct sound_device *snd_dev; rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE; - + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; - + rt_hw_sai2a_init(); - + /* set default params */ SAIA_Frequency_Set(snd_dev->replay_config.samplerate); SAIA_Channels_Set(snd_dev->replay_config.channels); - + /* set audio play type */ rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type); /* open lowlevel audio device */ @@ -337,7 +337,7 @@ static rt_err_t sound_init(struct rt_audio_device *audio) LOG_E("can't find low level audio device!"); return RT_ERROR; } - + return result; } @@ -345,17 +345,17 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream) { struct sound_device *snd_dev; rt_uint16_t play_type = OUTPUT_DEVICE_HEADPHONE; - + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; - + if (stream == AUDIO_STREAM_REPLAY) { LOG_D("open sound device"); - + rt_device_control(snd_dev->decoder, SET_PLAY_TYPE, &play_type); rt_device_control(snd_dev->decoder, START_PLAY, RT_NULL); - + if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK) { return RT_ERROR; @@ -368,7 +368,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream) static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) { RT_ASSERT(audio != RT_NULL); - + if (stream == AUDIO_STREAM_REPLAY) { HAL_SAI_DMAStop(&hsai_BlockA2); @@ -385,7 +385,7 @@ static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf RT_ASSERT(audio != RT_NULL); device = (struct sound_device *)audio->parent.user_data; - + info->buffer = device->tx_fifo; info->total_size = TX_FIFO_SIZE; info->block_size = TX_FIFO_SIZE / 2; @@ -407,7 +407,7 @@ int rt_hw_sound_init(void) { rt_err_t result = RT_EOK; struct rt_device *device = RT_NULL; - + rt_memset(AUDIO_TX_FIFO, 0, TX_FIFO_SIZE); snd_dev.tx_fifo = AUDIO_TX_FIFO; @@ -416,7 +416,7 @@ int rt_hw_sound_init(void) snd_dev.replay_config.channels = 2; snd_dev.replay_config.samplebits = 16; snd_dev.volume = 55; - + /* find lowlevel decoder device*/ snd_dev.decoder = rt_device_find("decoder"); if (snd_dev.decoder == RT_NULL) @@ -424,19 +424,19 @@ int rt_hw_sound_init(void) LOG_E("cant't find lowlevel decoder deivce!"); return RT_ERROR; } - + /* register sound device */ snd_dev.audio.ops = &snd_ops; result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev); /* check sound device register success or not */ if (result != RT_EOK) { - device = &(snd_dev.audio.parent); + device = &(snd_dev.audio.parent); rt_device_unregister(device); LOG_E("sound device init error!"); return RT_ERROR; } - + return RT_EOK; } @@ -485,7 +485,7 @@ int wavplay_sample(int argc, char **argv) #define BUFSZ 1024 #define SOUND_DEVICE_NAME "sound0" static rt_device_t sound_dev; - + int fd = -1; uint8_t *buffer = NULL; struct wav_info *info = NULL; @@ -528,9 +528,9 @@ static rt_device_t sound_dev; rt_device_open(sound_dev, RT_DEVICE_OFLAG_WRONLY); - caps.main_type = AUDIO_TYPE_OUTPUT; + caps.main_type = AUDIO_TYPE_OUTPUT; caps.sub_type = AUDIO_DSP_PARAM; - caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec; + caps.udata.config.samplerate = info->fmt_block.wav_format.SamplesPerSec; caps.udata.config.channels = info->fmt_block.wav_format.Channels; caps.udata.config.samplebits = 16; rt_device_control(sound_dev, AUDIO_CTL_CONFIGURE, &caps); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c index 6230b49a4f..7d0e665f64 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_spdifrx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ struct stm32_spdifrx { - struct rt_device dev; + struct rt_device dev; SPDIFRX_HandleTypeDef spdifrx; SAI_HandleTypeDef sai4; volatile rt_uint8_t complate; @@ -46,7 +46,7 @@ static void sai4a_init(SAI_HandleTypeDef* sai) sai->Init.DataSize = SAI_DATASIZE_24; sai->Init.FirstBit = SAI_FIRSTBIT_MSB; sai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; - + sai->FrameInit.FrameLength = 64; sai->FrameInit.ActiveFrameLength = 32; sai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; @@ -57,7 +57,7 @@ static void sai4a_init(SAI_HandleTypeDef* sai) sai->SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE; sai->SlotInit.SlotNumber = 4; sai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - + if (HAL_SAI_Init(sai) != HAL_OK) { Error_Handler(); @@ -65,12 +65,12 @@ static void sai4a_init(SAI_HandleTypeDef* sai) } void DMA1_Stream7_IRQHandler(void) -{ +{ /* enter interrupt */ rt_interrupt_enter(); - + HAL_DMA_IRQHandler(&hdma_spdifrx_rx); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -79,9 +79,9 @@ void DMA1_Stream2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_DMA_IRQHandler(&hdma_sai4_a); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -95,10 +95,10 @@ static rt_err_t _init(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev; - + device->spdifrx.Instance = SPDIFRX; - HAL_SPDIFRX_DeInit(&device->spdifrx); - + HAL_SPDIFRX_DeInit(&device->spdifrx); + device->spdifrx.Init.InputSelection = SPDIFRX_INPUT_IN1; device->spdifrx.Init.Retries = SPDIFRX_MAXRETRIES_15; device->spdifrx.Init.WaitForActivity = SPDIFRX_WAITFORACTIVITY_ON; @@ -106,53 +106,53 @@ static rt_err_t _init(rt_device_t dev) device->spdifrx.Init.DataFormat = SPDIFRX_DATAFORMAT_MSB; device->spdifrx.Init.StereoMode = SPDIFRX_STEREOMODE_ENABLE; device->spdifrx.Init.PreambleTypeMask = SPDIFRX_PREAMBLETYPEMASK_ON; - device->spdifrx.Init.ChannelStatusMask = SPDIFRX_CHANNELSTATUS_ON; - + device->spdifrx.Init.ChannelStatusMask = SPDIFRX_CHANNELSTATUS_ON; + if (HAL_SPDIFRX_Init(&device->spdifrx) != HAL_OK) { return RT_ERROR; } - + sai4a_init(&device->sai4); - + rt_spdifrx.complate = RESET; - + return RT_EOK; } static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag) { RT_ASSERT(dev != RT_NULL); - + return RT_EOK; } static rt_err_t _close(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); - + return RT_EOK; } static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) { rt_uint32_t tickstart = 0; - + RT_ASSERT(dev != RT_NULL); struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev; rt_err_t result = RT_EOK; - + result = HAL_SPDIFRX_ReceiveDataFlow_DMA(&device->spdifrx, (uint32_t *)buffer, size); if (result != HAL_OK) { return 0; } - + if(device->spdifrx.ErrorCode != HAL_SPDIFRX_ERROR_NONE) { return 0; } - + tickstart = rt_tick_get(); while (rt_spdifrx.complate == RESET) { @@ -161,9 +161,9 @@ static rt_size_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t si return 0; } } - + rt_spdifrx.complate = RESET; - + return size; } @@ -173,13 +173,13 @@ static rt_size_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_si struct stm32_spdifrx *device = (struct stm32_spdifrx *)dev; rt_err_t result = RT_EOK; - + result = HAL_SAI_Transmit_DMA(&device->sai4, (rt_uint8_t *)buffer, size); if (result != HAL_OK) { return RT_ERROR; } - + return RT_EOK; } @@ -203,10 +203,10 @@ int spdifrx_init(void) rt_device_register(&rt_spdifrx.dev, "spdifrx", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); rt_device_init(&rt_spdifrx.dev); - + LOG_I("spdifrx init success!"); - - return RT_EOK; + + return RT_EOK; } INIT_DEVICE_EXPORT(spdifrx_init); @@ -247,8 +247,8 @@ static int spdifrx_sample(int argc, char **argv) rt_kprintf("spdifrx_sample\n"); return -1; } - - /* 16 bit Data Buffer for Transmission */ + + /* 16 bit Data Buffer for Transmission */ static rt_uint16_t tx_buffer[64] = { 0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C, 0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768, 0x696A, 0x6B6C, 0x6D6E, 0x6F70, @@ -258,11 +258,11 @@ static int spdifrx_sample(int argc, char **argv) 0x6162, 0x6364, 0x6566, 0x6768, 0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374, 0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80, 0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C, 0x8D8E, 0x8F90}; - + static rt_uint32_t *rx_buffer = NULL; rt_uint8_t size = 64; struct rt_device *dev = RT_NULL; - + dev = rt_device_find("spdifrx"); if (dev == RT_NULL) { @@ -270,31 +270,31 @@ static int spdifrx_sample(int argc, char **argv) } rt_device_open(dev, RT_DEVICE_OFLAG_RDWR); - + rt_kprintf("spdifrx test tx data : \n"); dump_hex((rt_uint8_t *)tx_buffer, size); - + rx_buffer = (rt_uint32_t *)rt_malloc(size); - + rt_device_write(dev, 0, tx_buffer, size); rt_device_read(dev, 0, rx_buffer, size); - - /* Compare the received data with the expected one */ + + /* Compare the received data with the expected one */ while (size--) { if (((rx_buffer[size] & 0x00ffff00) >> 8) != (tx_buffer[size])) { rt_kprintf("spdirex loopback mode test failed!\n"); - + return RT_ERROR; } } - + rt_kprintf("spdifrx rx : \n"); dump_hex((rt_uint8_t *)rx_buffer, size); - + rt_kprintf("spdirex loopback mode test success!\n"); - + return RT_EOK; } MSH_CMD_EXPORT(spdifrx_sample, spdifrx loopback test); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c index b162d76b0f..cea18205fd 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ struct wm8994_dev { - struct rt_device dev; + struct rt_device dev; struct rt_i2c_bus_device *i2c_bus; rt_uint16_t id; rt_uint16_t type; @@ -34,12 +34,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uint { struct rt_i2c_msg msg[2] = {0, 0}; static rt_uint8_t i2c_reg[2] = {0, 0}; - + RT_ASSERT(bus != RT_NULL); - + i2c_reg[0] = ((uint16_t)(reg >> 8) & 0xFF); i2c_reg[1] = ((uint16_t)(reg) & 0xFF); - + msg[0].addr = CHIP_ADDRESS; msg[0].flags = RT_I2C_WR; msg[0].buf = i2c_reg; @@ -68,7 +68,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint16_t reg, rt_uin buf[0] = ((uint16_t)(reg >> 8) & 0xFF); buf[1] = ((uint16_t)(reg) & 0xFF); - + buf[2] = ((uint16_t)(data >> 8) & 0xFF); buf[3] = ((uint16_t)(data) & 0xFF); @@ -247,14 +247,14 @@ static rt_err_t wm8994_set_input_mode(struct rt_i2c_bus_device *bus, rt_uint16_t /* Actually, no other input devices supported */ break; } - + return RT_EOK; } static rt_err_t _wm8994_init(struct wm8994_dev *dev) { RT_ASSERT(dev != RT_NULL); - + /* wm8994 Errata Work-Arounds */ write_reg(dev->i2c_bus, 0x0102, 0x0003); write_reg(dev->i2c_bus, 0x0817, 0x0000); @@ -275,7 +275,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev) write_reg(dev->i2c_bus, 0x0001, 0x0003); } rt_thread_mdelay(50); - + if ((dev->type & 0x000F) != 0 ) { /* Path Configurations for output */ @@ -297,7 +297,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev) /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */ write_reg(dev->i2c_bus, 0x0300, 0x4010); } - + /* slave mode */ write_reg(dev->i2c_bus, 0x0302, 0x0000); @@ -308,7 +308,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev) write_reg(dev->i2c_bus, 0x0200, 0x0001); /* Audio output selected */ - if ((dev->type & 0x000F) != 0 ) + if ((dev->type & 0x000F) != 0 ) { if (dev->type & OUTPUT_DEVICE_HEADPHONE) { @@ -409,7 +409,7 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev) } /* Audio input selected */ - if ((dev->type & 0x01F0) != 0 ) + if ((dev->type & 0x01F0) != 0 ) { if ((dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (dev->type & INPUT_DEVICE_DIGITAL_MICROPHONE_2)) { @@ -449,17 +449,17 @@ static rt_err_t _wm8994_init(struct wm8994_dev *dev) write_reg(dev->i2c_bus, 0x0410, 0x1800); } } - + /* Return communication control value */ return RT_EOK; - + } static rt_err_t _read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id) { rt_uint8_t read_value[2]; - - read_reg(bus, 0x0000, 2, read_value); + + read_reg(bus, 0x0000, 2, read_value); *id = ((uint16_t)(read_value[0] << 8) & 0xFF00); *id |= ((uint16_t)(read_value[1])& 0x00FF); @@ -468,9 +468,9 @@ static rt_err_t _read_id(struct rt_i2c_bus_device *bus, rt_uint16_t *id) LOG_E("error id: 0x%04x", *id); return RT_ERROR; } - + LOG_I("wm8994 init success, id: %04x", *id); - + return RT_EOK; } @@ -493,7 +493,7 @@ static rt_err_t _set_mute(struct rt_i2c_bus_device *bus, uint32_t cmd) /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */ write_reg(bus, 0x422, 0x0010); } - + return RT_EOK; } @@ -507,7 +507,7 @@ static rt_err_t _play(struct rt_i2c_bus_device *bus) static rt_err_t _set_volume(struct rt_i2c_bus_device *bus, rt_uint16_t type, rt_uint8_t volume) { rt_uint8_t convertedvol = VOLUME_CONVERT(volume); - + if (type & 0x000F) { /* Output volume */ @@ -575,9 +575,9 @@ static rt_err_t _set_volume(struct rt_i2c_bus_device *bus, rt_uint16_t type, rt_ static rt_err_t _get_volume(struct rt_i2c_bus_device *bus, rt_uint32_t *value) { rt_uint8_t read_value[2]; - + read_reg(bus, 0x001C, 2, read_value); - + *value = ((uint16_t)(read_value[0] << 8) & 0xFF00); *value |= ((uint16_t)(read_value[1])& 0x00FF); @@ -618,11 +618,11 @@ static rt_err_t _set_frequency(struct rt_i2c_bus_device *bus, rt_uint32_t freq) case AUDIO_FREQUENCY_44K: write_reg(bus, 0x210, 0x0073); - break; + break; default: write_reg(bus, 0x210, 0x0083); - break; + break; } return RT_EOK; @@ -641,36 +641,36 @@ static rt_err_t rt_wm8994_init(rt_device_t dev) RT_ASSERT(dev != RT_NULL); rt_err_t result = RT_EOK; static rt_uint16_t old_type = DEVICE_NONE; - + struct wm8994_dev *device = (struct wm8994_dev *)dev; - + if (old_type == device->type) { return RT_EOK; } - + old_type = device->type; - + device->i2c_bus = rt_i2c_bus_device_find(I2C_NAME); if (device->i2c_bus == RT_NULL) { LOG_E("can't find %c deivce", I2C_NAME); return RT_ERROR; } - + result = _wm8994_init(device); /* set volume */ _set_volume(device->i2c_bus, device->type, VOLUME_CONVERT(100)); /* set frequency */ _set_frequency(device->i2c_bus, AUDIO_FREQUENCY_44K); - + return result; } static rt_err_t rt_wm8994_open(rt_device_t dev, rt_uint16_t oflag) { RT_ASSERT(dev != RT_NULL); - + return RT_EOK; } @@ -678,7 +678,7 @@ static rt_err_t rt_wm8994_close(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); struct wm8994_dev *device = (struct wm8994_dev *)dev; - + _set_mute(device->i2c_bus, AUDIO_MUTE_ON); /* Mute the AIF1 Timeslot 0 DAC1 path */ @@ -721,19 +721,19 @@ static rt_err_t rt_wm8994_control(rt_device_t dev, int cmd, void *args) case GET_ID: result = _read_id(device->i2c_bus, (rt_uint16_t*)args); break; - + case SET_FREQUENCE: result = _set_frequency(device->i2c_bus, (*(rt_uint32_t *)args)); break; - + case SET_VOLUME: result = _set_volume(device->i2c_bus, device->type, (*(rt_uint8_t*)args)); break; - + case GET_VOLUME: result = _get_volume(device->i2c_bus, (rt_uint32_t *)args); break; - + case SET_MUTE: result = _set_mute(device->i2c_bus, (*(rt_uint32_t*)args)); break; @@ -741,23 +741,23 @@ static rt_err_t rt_wm8994_control(rt_device_t dev, int cmd, void *args) case SET_RESET: result = _reset(device->i2c_bus); break; - + case START_PLAY: result = _play(device->i2c_bus); break; - + case SET_PLAY_TYPE: device->type = 0; device->type = *(rt_uint32_t *)args; rt_wm8994_init(dev); break; - + default: LOG_D("not support cmd"); break; } - - return result; + + return result; } int wm8994_init(void) @@ -772,9 +772,9 @@ int wm8994_init(void) rt_wm8994.dev.user_data = RT_NULL; rt_device_register(&rt_wm8994.dev, "decoder", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); - + LOG_I("lowlevel decoder device init success!"); - + return RT_EOK; } INIT_DEVICE_EXPORT(wm8994_init); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h index 872e02b162..73921ffaa1 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wm8994.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,7 +16,7 @@ #ifdef __cplusplus extern "C" { #endif - + enum{ GET_ID, SET_FREQUENCE, @@ -65,7 +65,7 @@ enum{ #define AUDIO_FREQUENCY_22K ((uint32_t)22050) #define AUDIO_FREQUENCY_16K ((uint32_t)16000) #define AUDIO_FREQUENCY_11K ((uint32_t)11025) -#define AUDIO_FREQUENCY_8K ((uint32_t)8000) +#define AUDIO_FREQUENCY_8K ((uint32_t)8000) #define VOLUME_CONVERT(Volume) (((Volume) > 100)? 100:((uint8_t)(((Volume) * 63) / 100))) #define VOLUME_IN_CONVERT(Volume) (((Volume) >= 100)? 239:((uint8_t)(((Volume) * 240) / 100))) diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c index 4e9910aa95..77bde7d7b7 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,15 +22,15 @@ #define LED5_PIN GET_PIN(A, 14) static rt_uint8_t feed_flag = 0; -static WWDG_HandleTypeDef hwwdg1; +static WWDG_HandleTypeDef hwwdg1; void WWDG1_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + HAL_WWDG_IRQHandler(&hwwdg1); - + /* leave interrupt */ rt_interrupt_leave(); } @@ -50,18 +50,18 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) static void wwdg_init() { rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT); - + hwwdg1.Instance = WWDG1; hwwdg1.Init.Prescaler = WWDG_PRESCALER_8; hwwdg1.Init.Window = 0X5F; hwwdg1.Init.Counter = 0x7F; hwwdg1.Init.EWIMode = WWDG_EWI_ENABLE; - + if (HAL_WWDG_Init(&hwwdg1) != HAL_OK) { Error_Handler(); } - + feed_flag = 1; } @@ -69,10 +69,10 @@ static void wwdg_control(uint8_t pre_value) { if(pre_value > 7) { - pre_value = 7; + pre_value = 7; } hwwdg1.Instance->CFR &= ~(7 << 11); /* clear WDGTB[2:0] */ - hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */ + hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */ } static void wwdg_stop(void) @@ -85,7 +85,7 @@ static int wwdg_sample(int argc, char *argv[]) if (argc > 1) { if (!strcmp(argv[1], "run")) - { + { wwdg_init(); } else if (!strcmp(argv[1], "set")) @@ -93,7 +93,7 @@ static int wwdg_sample(int argc, char *argv[]) if (argc > 2) { wwdg_control(atoi(argv[2])); - } + } } else if (!strcmp(argv[1], "stop")) { diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c index 42aec448f8..670a00e35e 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -146,7 +146,7 @@ static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_v return RT_ETIMEOUT; } } - + return RT_EOK; } @@ -155,7 +155,7 @@ static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr) uint16_t reg_value = 0; uint32_t status = 0; volatile uint32_t tickstart = 0; - + /* Take care not to alter MDC clock configuration */ status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR; /* Set up a read operation */ @@ -228,10 +228,10 @@ static void HAL_ETH_MspInit(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - + if(IS_ENGINEERING_BOOT_MODE()) { - /** Initializes the peripherals clock + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH; PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4; @@ -240,10 +240,10 @@ static void HAL_ETH_MspInit(void) Error_Handler(); } } - + /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Enable GPIO clocks */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); @@ -254,21 +254,21 @@ static void HAL_ETH_MspInit(void) /* Select RGMII interface mode */ HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII); - + /* Enable Ethernet MAC clock */ __HAL_RCC_ETH1MAC_CLK_ENABLE(); __HAL_RCC_ETH1TX_CLK_ENABLE(); __HAL_RCC_ETH1RX_CLK_ENABLE(); - + /**ETH1 GPIO Configuration PA1 ------> ETH1_RX_CLK - PA2 ------> ETH1_MDIO + PA2 ------> ETH1_MDIO PA7 ------> ETH1_RX_CTL PB0 ------> ETH1_RXD2 - PB1 ------> ETH1_RXD3 - PB11 ------> ETH1_TX_CTL + PB1 ------> ETH1_RXD3 + PB11 ------> ETH1_TX_CTL PC1 ------> ETH1_MDC - PC2 ------> ETH1_TXD2 + PC2 ------> ETH1_TXD2 PC4 ------> ETH1_RXD0 PC5 ------> ETH1_RXD1 PE2 ------> ETH1_TXD3 @@ -294,12 +294,12 @@ static void HAL_ETH_MspInit(void) HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); /* ETH interrupt Init */ HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00); HAL_NVIC_EnableIRQ(ETH1_IRQn); - + /* Configure PHY_RST (PD10) */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; @@ -317,12 +317,12 @@ static void HAL_ETH_MspInit(void) static rt_err_t rt_stm32_eth_init(rt_device_t dev) { RT_ASSERT(dev != RT_NULL); - + rt_uint32_t status; int i = 0 ; volatile uint32_t tickstart = 0; uint8_t *macAddr = &stm32_eth_device.dev_addr[0]; - + /* Initialize RX/TX descriptor index */ rxIndex = txIndex = 0; @@ -362,30 +362,30 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) ETH->MACA2HR = 0; ETH->MACA3LR = 0; ETH->MACA3HR = 0; - + /* Initialize hash table */ ETH->MACHT0R = 0; ETH->MACHT1R = 0; - + /* Configure the receive filter */ ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC; - + /* Disable flow control */ ETH->MACQ0TXFCR = 0; ETH->MACRXFCR = 0; - + /* Enable the first RX queue */ ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1); - + /* Configure DMA operating mode */ ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0); - + /* Configure system bus mode */ ETH->DMASBMR |= ETH_DMASBMR_AAL; - + /* The DMA takes the descriptor table as contiguous */ ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0); - + /* Configure TX features */ ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1); @@ -417,12 +417,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) rxDmaDesc[i].rdes2 = 0; rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V; } - + /* Set Transmit Descriptor List Address Register */ ETH->DMAC0TXDLAR = (uint32_t)&txDmaDesc[0]; /* Length of the transmit descriptor ring */ ETH->DMAC0TXRLR = ETH_TXBUFNB - 1; - + /* Set Receive Descriptor List Address Register */ ETH->DMAC0RXDLAR = (uint32_t)&rxDmaDesc[0]; /* Length of the receive descriptor ring */ @@ -431,24 +431,24 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) /* Prevent interrupts from being generated when the transmit statistic * counters reach half their maximum value */ ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM; - + /* Prevent interrupts from being generated when the receive statistic * counters reach half their maximum value */ ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM; - + /* Disable MAC interrupts */ ETH->MACIER = 0; - + /* Enable the desired DMA interrupts */ ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; - + /* Enable MAC transmission and reception */ ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE; - + /* Enable DMA transmission and reception */ ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST; ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR; - + /* Reset PHY transceiver */ phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR, RTL8211E_BMCR_RESET); status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR); @@ -464,9 +464,9 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) else { status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMCR); - } + } } - + /* The PHY will generate interrupts when link status changes are detected */ phy_write_reg(RTL8211E_PHY_ADDR, RTL8211E_INER, RTL8211E_INER_AN_COMPLETE | RTL8211E_INER_LINK_STATUS); @@ -505,11 +505,11 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args) { case NIOCTL_GADDR: /* get mac address */ - if (args) + if (args) { rt_memcpy(args, stm32_eth_device.dev_addr, 6); } - else + else { return -RT_ERROR; } @@ -526,7 +526,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) { uint32_t framelen = 0; struct pbuf *q = RT_NULL; - + /* Copy user data to the transmit buffer */ for (q = p; q != NULL; q = q->next) { @@ -536,12 +536,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) LOG_D("buffer not valid"); return ERR_USE; } - + level = rt_hw_interrupt_disable(); rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len); framelen += q->len; rt_hw_interrupt_enable(level); - + /* Check the frame length */ if (framelen > ETH_TX_BUF_SIZE - 1) { @@ -549,12 +549,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) return ERR_USE; } } - + #ifdef ETH_TX_DUMP rt_kprintf("Tx dump, len= %d\r\n", framelen); dump_hex(txBuffer[txIndex], framelen); #endif - + /* Set the start address of the buffer */ txDmaDesc[txIndex].tdes0 = (uint32_t)txBuffer[txIndex]; /* Write the number of bytes to send */ @@ -569,7 +569,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p) ETH->DMAC0SR = ETH_DMAC0SR_TBU; /* Instruct the DMA to poll the transmit descriptor list */ ETH->DMAC0TXDTPR = 0; - + if (++txIndex > ETH_TXBUFNB - 1) { txIndex = 0; @@ -585,7 +585,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) struct pbuf *p = RT_NULL, *q = RT_NULL; /* The current buffer is available for reading */ - if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) + if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) { /* FD and LD flags should be set */ if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD)) @@ -594,7 +594,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) if(!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_ES)) { /* Retrieve the length of the frame */ - framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL; + framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL; /* check the frame length */ framelength = (framelength > ETH_RX_BUF_SIZE) ? ETH_RX_BUF_SIZE : framelength; p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM); @@ -606,7 +606,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len); framelen += q->len; rt_hw_interrupt_enable(level); - + if (framelen > framelength) { LOG_E("frame len is too long!"); @@ -621,7 +621,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) LOG_D("the received packet contains an error!"); return RT_NULL; } - + } else { @@ -648,14 +648,14 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) /* Instruct the DMA to poll the receive descriptor list */ ETH->DMAC0RXDTPR = 0; } - + return p; } void ETH1_IRQHandler(void) { rt_uint32_t status = 0; - + /* enter interrupt */ rt_interrupt_enter(); /* Read DMA status register */ @@ -671,7 +671,7 @@ void ETH1_IRQHandler(void) { /* Disable RIE interrupt */ ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE; - + rt_event_send(&rx_event, status); } /* ETH DMA Error */ @@ -682,7 +682,7 @@ void ETH1_IRQHandler(void) } /* Clear the interrupt flags */ ETH->DMAC0SR = ETH_DMAC0SR_NIS; - + /* leave interrupt */ rt_interrupt_leave(); } @@ -693,18 +693,18 @@ static void phy_linkchange() /* Read status register to acknowledge the interrupt */ status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_INSR); - + if (status & (RTL8211E_INSR_AN_COMPLETE | RTL8211E_INSR_LINK_STATUS)) { status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR); status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_BMSR); - + if (status & RTL8211E_BMSR_LINK_STATUS) { - LOG_D("link up"); - + LOG_D("link up"); + status = phy_read_reg(RTL8211E_PHY_ADDR, RTL8211E_PHYSR); - + switch (status & RTL8211E_PHYSR_SPEED) { case RTL8211E_PHYSR_SPEED_10MBPS: @@ -713,25 +713,25 @@ static void phy_linkchange() stm32_eth_device.eth_speed |= PHY_10M; break; } - + case RTL8211E_PHYSR_SPEED_100MBPS: { LOG_D("speed: 100M"); stm32_eth_device.eth_speed |= PHY_100M; break; } - + case RTL8211E_PHYSR_SPEED_1000MBPS: { LOG_D("speed: 1000M"); stm32_eth_device.eth_speed |= PHY_1000M; break; } - + /* Unknown speed */ default: rt_kprintf("Invalid speed."); - break; + break; } stm32_eth_device.eth_mode = (status & RTL8211E_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX; @@ -762,7 +762,7 @@ static void eth_phy_isr(void *args) static void phy_monitor_thread_entry(void *parameter) { rt_uint32_t status = 0; - + phy_linkchange(); #ifdef PHY_USING_INTERRUPT_MODE /* configuration intterrupt pin */ @@ -800,9 +800,9 @@ static void phy_monitor_thread_entry(void *parameter) eth_device_ready(&(stm32_eth_device.parent)); } } - + /* enable DMA interrupts */ - ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; + ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; } } } @@ -811,7 +811,7 @@ static void phy_monitor_thread_entry(void *parameter) static int rt_hw_stm32_eth_init(void) { rt_err_t state = RT_EOK; - + /* OUI 00-80-E1 STMICROELECTRONICS. */ stm32_eth_device.dev_addr[0] = 0x00; stm32_eth_device.dev_addr[1] = 0x80; @@ -831,9 +831,9 @@ static int rt_hw_stm32_eth_init(void) stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; - + rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO); - + /* register eth device */ state = eth_device_init(&(stm32_eth_device.parent), "e0"); if (RT_EOK == state) diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h index 9529d778a0..08612249ed 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/eth/drv_eth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -368,7 +368,7 @@ enum { #define RTL8211E_INSR_FALSE_CARRIER 0x0100 #define RTL8211E_INSR_JABBER 0x0001 -/* Link Down Power Saving register */ +/* Link Down Power Saving register */ #define RTL8211E_LDPSR_POWER_SAVE_MODE 0x0001 /* Extension Page Select register */ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c index ca31b0aa47..075476294b 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/spi_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -29,15 +29,15 @@ static int rt_spi_device_init(void) cfg.max_hz = 1 *1000 *1000; spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME); - + if (RT_NULL == spi_dev) { rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME); return RT_ERROR; } - + rt_spi_configure(spi_dev, &cfg); - + return RT_EOK; } INIT_APP_EXPORT(rt_spi_device_init); @@ -45,22 +45,22 @@ INIT_APP_EXPORT(rt_spi_device_init); /* spi5 loopback mode test case */ static int spi_sample(int argc, char **argv) { - rt_uint8_t t_buf[8], r_buf[8]; - int i = 0; + rt_uint8_t t_buf[8], r_buf[8]; + int i = 0; static struct rt_spi_message msg1; - + if (argc != 9) { rt_kprintf("Usage:\n"); rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n"); return -RT_ERROR; } - + for (i = 0; i < 8; i++) { t_buf[i] = atoi(argv[i+1]); } - + msg1.send_buf = &t_buf; msg1.recv_buf = &r_buf; msg1.length = sizeof(t_buf); diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c index fdbc721c8d..0f4df63bd3 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,11 +26,11 @@ static rt_adc_device_t adc_dev = RT_NULL; static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { rt_uint32_t value = 0 , vol = 0; - + /* read adc value */ value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); rt_kprintf("the value is :%d \n", value); - + vol = value * REFER_VOLTAGE / CONVERT_BITS; rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); @@ -55,21 +55,21 @@ static int hwtimer_stop(void) rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME); return ret; } - + /* close adc channel */ ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); - + return ret; } static int hwtimer_start(void) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_hwtimerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - + rt_hwtimer_mode_t mode; - + hw_dev = rt_device_find(HWTIMER_DEV_NAME); if (hw_dev == RT_NULL) { @@ -84,7 +84,7 @@ static int hwtimer_start(void) rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); return RT_ERROR; } - + /* Open the device in read/write mode */ ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) @@ -118,10 +118,10 @@ static int hwtimer_start(void) rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); - + /* enable adc channel */ ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); - + return ret; } @@ -130,8 +130,8 @@ static int tim_sample(int argc, char *argv[]) if (argc > 1) { if (!rt_strcmp(argv[1], "start")) - { - rt_kprintf("tim14 will start\n"); + { + rt_kprintf("tim14 will start\n"); hwtimer_start(); return RT_EOK; } @@ -152,7 +152,7 @@ _exit: rt_kprintf("tim_sample start - start TIM14 \n"); rt_kprintf("tim_sample stop - stop TIM14 \n"); } - + return RT_ERROR; } MSH_CMD_EXPORT(tim_sample, tim sample); diff --git a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c index ce87056796..f6e244c12c 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c @@ -1,10 +1,10 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2020-09-29 Dozingfiretruck first version */ diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/board.c b/bsp/stm32/stm32wb55-st-nucleo/board/board.c index 1fa13eb975..13796c442c 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/board.c +++ b/bsp/stm32/stm32wb55-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/board.h b/bsp/stm32/stm32wb55-st-nucleo/board/board.h index d77bf172ba..366ef99b50 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/board.h +++ b/bsp/stm32/stm32wb55-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h index 3cf64a01de..e3c93996e7 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h @@ -1,10 +1,10 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2020-09-29 Dozingfiretruck first version */ diff --git a/bsp/stm32/stm32wl55-st-nucleo/applications/main.c b/bsp/stm32/stm32wl55-st-nucleo/applications/main.c index ecd955ef8e..57385ad74c 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32wl55-st-nucleo/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h index 3fe6b19b9a..07da513450 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h +++ b/bsp/stm32/stm32wl55-st-nucleo/board/CubeMX_Config/Inc/stm32wlxx_nucleo.h @@ -28,7 +28,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wlxx_nucleo_errno.h" #include "stm32wlxx_nucleo_conf.h" - + #if (USE_BSP_COM_FEATURE > 0) #if (USE_COM_LOG > 0) #ifndef __GNUC__ @@ -36,7 +36,7 @@ #endif #endif #endif - + /** @addtogroup BSP * @{ */ @@ -52,7 +52,7 @@ /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types * @{ */ -typedef enum +typedef enum { LED1 = 0, LED2 = 1, @@ -63,15 +63,15 @@ typedef enum LED_RED = LED3 }Led_TypeDef; -typedef enum -{ +typedef enum +{ BUTTON_SW1 = 0, BUTTON_SW2 = 1, BUTTON_SW3 = 2, }Button_TypeDef; -typedef enum -{ +typedef enum +{ BUTTON_MODE_GPIO = 0, BUTTON_MODE_EXTI = 1 }ButtonMode_TypeDef; @@ -129,18 +129,18 @@ typedef struct #endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */ #endif /* (USE_BSP_COM_FEATURE > 0) */ -typedef enum +typedef enum { ABSENT = 0, PRESENT = 1, }Presence_TypeDef; /** * @} - */ + */ /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants * @{ - */ + */ /** * @brief STM32WLXX NUCLEO BSP Driver version number @@ -148,15 +148,15 @@ typedef enum #define __STM32WLXX_NUCLEO_BSP_VERSION_MAIN (0x00U) /*!< [31:24] main version */ #define __STM32WLXX_NUCLEO_BSP_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32WLXX_NUCLEO_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32WLXX_NUCLEO_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WLXX_NUCLEO_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WLXX_NUCLEO_BSP_VERSION ((__STM32WLXX_NUCLEO_BSP_VERSION_MAIN << 24)\ |(__STM32WLXX_NUCLEO_BSP_VERSION_SUB1 << 16)\ |(__STM32WLXX_NUCLEO_BSP_VERSION_SUB2 << 8 )\ |(__STM32WLXX_NUCLEO_BSP_VERSION_RC)) -/** - * @brief Define for STM32WLXX_NUCLEO board - */ +/** + * @brief Define for STM32WLXX_NUCLEO board + */ #if !defined (USE_STM32WLXX_NUCLEO) #define USE_STM32WLXX_NUCLEO #endif @@ -185,11 +185,11 @@ typedef enum #define LEDx_GPIO_CLK_DISABLE(__INDEX__) __HAL_RCC_GPIOB_CLK_ENABLE() /* All Led on same port */ /** * @} - */ - + */ + /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_BUTTON LOW LEVEL BUTTON Constants * @{ - */ + */ #define BUTTONn 3 /** @@ -239,11 +239,11 @@ typedef enum /** * @} */ - + #if (USE_BSP_COM_FEATURE > 0) /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_COM LOW LEVEL COM Port Constants * @{ - */ + */ #define COM1_UART LPUART1 #define COM1_CLK_ENABLE() __HAL_RCC_LPUART1_CLK_ENABLE() #define COM1_CLK_DISABLE() __HAL_RCC_LPUART1_CLK_DISABLE() @@ -315,7 +315,7 @@ void BSP_PB_IRQHandler(Button_TypeDef Button); #if (USE_BSP_COM_FEATURE > 0) /** @defgroup STM32WLXX_NUCLEO_LOW_LEVEL_COM_Functions LOW LEVEL COM Port Functions * @{ - */ + */ int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init); int32_t BSP_COM_DeInit(COM_TypeDef COM); #if (USE_COM_LOG > 0) diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/board.c b/bsp/stm32/stm32wl55-st-nucleo/board/board.c index d99a819d39..994aedfce4 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/board.c +++ b/bsp/stm32/stm32wl55-st-nucleo/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,11 +15,11 @@ void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; RCC_OscInitStruct.HSICalibrationValue = 70; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -32,8 +32,8 @@ void SystemClock_Config(void) { Error_Handler(); } - - /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK3); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/board.h b/bsp/stm32/stm32wl55-st-nucleo/board/board.h index e8268b970a..c6ba5988ff 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/board.h +++ b/bsp/stm32/stm32wl55-st-nucleo/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tm4c123bsp/applications/main.c b/bsp/tm4c123bsp/applications/main.c index 3d5b70bcb9..d19bc78525 100644 --- a/bsp/tm4c123bsp/applications/main.c +++ b/bsp/tm4c123bsp/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,6 @@ int main(void) rt_pin_write(2, PIN_LOW); rt_thread_mdelay(500); } - + return RT_EOK; } diff --git a/bsp/tm4c123bsp/board/board.c b/bsp/tm4c123bsp/board/board.c index 5e4b8baa58..4f75212b08 100644 --- a/bsp/tm4c123bsp/board/board.c +++ b/bsp/tm4c123bsp/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tm4c123bsp/board/board.h b/bsp/tm4c123bsp/board/board.h index cd1647ec15..f12ba9c5b5 100644 --- a/bsp/tm4c123bsp/board/board.h +++ b/bsp/tm4c123bsp/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -49,4 +49,4 @@ #endif /*__BOARD_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/board/tm4c123_config.c b/bsp/tm4c123bsp/board/tm4c123_config.c index 781f2a504e..cc03988adf 100644 --- a/bsp/tm4c123bsp/board/tm4c123_config.c +++ b/bsp/tm4c123bsp/board/tm4c123_config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -85,4 +85,4 @@ void spi_hw_config(void) } #endif /* RT_USING_SPI */ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/board/tm4c123_config.h b/bsp/tm4c123bsp/board/tm4c123_config.h index 38128bc60f..0153babcfa 100644 --- a/bsp/tm4c123bsp/board/tm4c123_config.h +++ b/bsp/tm4c123bsp/board/tm4c123_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h index cfeb256020..bdb9d7e9bc 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h +++ b/bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -49,4 +49,4 @@ extern "C" { #endif /*__ADC_CONFIG_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h index e44eb372e4..5b32fa9e67 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h +++ b/bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -90,7 +90,7 @@ extern "C" { #ifdef BSP_USING_PWM6 #ifndef PWM6_CONFIG #define PWM6_CONFIG \ - { \ + { \ .name = "pwm6", \ .channel = 0 , \ .counterMode = PWM_GEN_MODE_UP_DOWN , \ @@ -117,4 +117,4 @@ extern "C" { #endif /*__PWM_CONFIG_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h index 7da0b7852f..23518523a7 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h +++ b/bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -63,4 +63,4 @@ extern "C" { #endif /*__SPI_CONFIG_H__ */ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h index b8fd375d07..f226ce8dab 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h +++ b/bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -73,4 +73,4 @@ extern "C" { #endif /* __UART_CONFIG_H__ */ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c index daf8e7b8ca..331b599f2f 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -156,4 +156,4 @@ INIT_APP_EXPORT(tm4c123_adc_init); #endif /*RT_UING_ADC*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h index a552e5f047..d739a2efb3 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,4 +28,4 @@ struct tm4c123_adc_config #endif /*__DRV_ADC_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c index 410a456849..b55da5bd40 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -165,4 +165,4 @@ INIT_BOARD_EXPORT(rt_hw_pin_init); #endif /*RT_USING_PIN*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h index 5205367e8b..dd40475cda 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,4 +36,4 @@ extern int rt_hw_pin_init(void); #endif /*__DRV_GPIO_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_log.h b/bsp/tm4c123bsp/libraries/Drivers/drv_log.h index ea5e648429..0b6d8d8f12 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_log.h +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c index dbd69fdb4e..d365899a4d 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -322,4 +322,4 @@ int rt_hw_pwm_init(void) #endif /* RT_USING_PWM */ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h index 29ce1899bd..906680fe3d 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,4 +33,4 @@ int rt_hw_pwm_init(void); #endif /*__DRV_PWM_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c index d604c21993..deee0b49bb 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -306,4 +306,4 @@ INIT_BOARD_EXPORT(rt_hw_spi_init); #endif /* defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */ #endif /*RT_USING_SPI*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h index bc4e5a4e24..33b28146bc 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -46,4 +46,4 @@ struct tm4c123_spi_device #endif /*__DRV_SPI_H__ */ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c index 9679baf293..41b133fd6e 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -235,4 +235,4 @@ int rt_hw_usart_init(void) #endif /* RT_USING_SERIAL */ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h index 44f8615008..aabd753500 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -43,4 +43,4 @@ extern int rt_hw_usart_init(void); #endif /*__DRV_UART_H__*/ -/************************** end of file ******************/ \ No newline at end of file +/************************** end of file ******************/ diff --git a/bsp/tm4c129x/applications/application.c b/bsp/tm4c129x/applications/application.c index 671511c36d..e199702e8a 100644 --- a/bsp/tm4c129x/applications/application.c +++ b/bsp/tm4c129x/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/tm4c129x/applications/board.c b/bsp/tm4c129x/applications/board.c index 382cf28cf8..26ada2f8f8 100644 --- a/bsp/tm4c129x/applications/board.c +++ b/bsp/tm4c129x/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -72,10 +68,10 @@ void rt_hw_board_init() int rt_hw_cpu_init(void) { MAP_IntMasterDisable(); - IntRegister(FAULT_HARD, HardFault_Handler); + IntRegister(FAULT_HARD, HardFault_Handler); IntRegister(FAULT_PENDSV, PendSV_Handler); IntRegister(FAULT_SYSTICK, SysTick_Handler); - + // Enable lazy stacking for interrupt handlers. This allows floating-point // instructions to be used within interrupt handlers, but at the expense of // extra stack usage. @@ -91,7 +87,7 @@ int rt_hw_cpu_init(void) MAP_SysTickDisable(); MAP_SysTickPeriodSet(SystemCoreClock/ RT_TICK_PER_SECOND - 1); MAP_SysTickIntEnable(); - MAP_SysTickEnable(); + MAP_SysTickEnable(); return 0; } diff --git a/bsp/tm4c129x/applications/board.h b/bsp/tm4c129x/applications/board.h index 20b038db30..ea1f7d4de4 100644 --- a/bsp/tm4c129x/applications/board.h +++ b/bsp/tm4c129x/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c index 9545620d8d..12d9f88f3e 100644 --- a/bsp/tm4c129x/drivers/drv_eth.c +++ b/bsp/tm4c129x/drivers/drv_eth.c @@ -1,11 +1,7 @@ /* - * File : drv_eth.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -246,7 +242,7 @@ volatile uint32_t g_ui32AbnormalInts; ((uint32_t)(ptr) < 0x20070000)) -typedef struct +typedef struct { /* inherit from ethernet device */ struct eth_device parent; @@ -254,7 +250,7 @@ typedef struct /* for rx_thread async get pbuf */ rt_mailbox_t rx_pbuf_mb; } net_device; -typedef net_device* net_device_t; +typedef net_device* net_device_t; static char rx_pbuf_mb_pool[8*4]; static struct rt_mailbox eth_rx_pbuf_mb; @@ -570,7 +566,7 @@ tivaif_transmit(net_device_t dev, struct pbuf *p) /* Get our state data from the netif structure we were passed. */ //pIF = (tStellarisIF *)psNetif->state; pIF = dev->dma_if; - + /* Make sure that the transmit descriptors are not all in use */ pDesc = &(pIF->pTxDescList->pDescriptors[pIF->pTxDescList->ui32Write]); if(pDesc->pBuf) @@ -955,7 +951,7 @@ tivaif_process_phy_interrupt(net_device_t dev) */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - /* + /* * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register */ EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); @@ -1170,38 +1166,38 @@ void lwIPEthernetIntHandler(void) } -// OUI:00-12-37 (hex) Texas Instruments, only for test +// OUI:00-12-37 (hex) Texas Instruments, only for test static int tiva_eth_mac_addr_init(void) { - int retVal =0; + int retVal =0; uint32_t ulUser[2]; uint8_t mac_addr[6]; - + MAP_FlashUserGet(&ulUser[0], &ulUser[1]); if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff)) { rt_kprintf("Fail to get mac address from eeprom.\n"); rt_kprintf("Using default mac address\n"); - // OUI:00-12-37 (hex) Texas Instruments, only for test - // Configure the hardware MAC address + // OUI:00-12-37 (hex) Texas Instruments, only for test + // Configure the hardware MAC address ulUser[0] = 0x00371200; ulUser[1] = 0x00563412; - //FlashUserSet(ulUser0, ulUser1); + //FlashUserSet(ulUser0, ulUser1); retVal =-1; } - - + + //Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC //address needed to program the hardware registers, then program the MAC //address into the Ethernet Controller registers. - + mac_addr[0] = ((ulUser[0] >> 0) & 0xff); mac_addr[1] = ((ulUser[0] >> 8) & 0xff); mac_addr[2] = ((ulUser[0] >> 16) & 0xff); mac_addr[3] = ((ulUser[1] >> 0) & 0xff); mac_addr[4] = ((ulUser[1] >> 8) & 0xff); mac_addr[5] = ((ulUser[1] >> 16) & 0xff); - + // // Program the hardware with its MAC address (for filtering). // @@ -1219,7 +1215,7 @@ static int tiva_eth_mac_addr_init(void) MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4); - + // // Enable the ethernet peripheral. // @@ -1288,7 +1284,7 @@ static int tiva_eth_mac_addr_init(void) EMAC_MODE_TX_STORE_FORWARD | EMAC_MODE_TX_THRESHOLD_64_BYTES | EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); - + EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler); } @@ -1297,7 +1293,7 @@ static rt_err_t eth_dev_init(rt_device_t device) { net_device_t net_dev = (net_device_t)device; struct netif *psNetif = (net_dev->parent.netif); - + LWIP_ASSERT("psNetif != NULL", (psNetif != NULL)); #if LWIP_NETIF_HOSTNAME @@ -1311,7 +1307,7 @@ static rt_err_t eth_dev_init(rt_device_t device) * of bits per second. */ //NETIF_INIT_SNMP(psNetif, snmp_ifType_ethernet_csmacd, 1000000); - + net_dev->dma_if = &g_StellarisIFData; /* Remember our MAC address. */ @@ -1329,9 +1325,9 @@ static rt_err_t eth_dev_control(rt_device_t dev, int cmd, void *args) { case NIOCTL_GADDR: /* get mac address */ - if(args) + if(args) MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args); - else + else return -RT_ERROR; break; @@ -1379,7 +1375,7 @@ static struct pbuf* eth_dev_rx(rt_device_t dev) rt_uint32_t temp =0; net_device_t net_dev = (net_device_t)dev; result = rt_mb_recv(net_dev->rx_pbuf_mb, (rt_ubase_t *)&temp, RT_WAITING_NO); - + return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL; } @@ -1388,7 +1384,7 @@ int rt_hw_tiva_eth_init(void) rt_err_t result; /* Clock GPIO and etc */ - tiva_eth_lowlevel_init(); + tiva_eth_lowlevel_init(); tiva_eth_mac_addr_init(); /* init rt-thread device interface */ @@ -1400,14 +1396,14 @@ int rt_hw_tiva_eth_init(void) eth_dev->parent.parent.control = eth_dev_control; eth_dev->parent.eth_rx = eth_dev_rx; eth_dev->parent.eth_tx = eth_dev_tx; - + result = rt_mb_init(ð_rx_pbuf_mb, "epbuf", &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4, RT_IPC_FLAG_FIFO); RT_ASSERT(result == RT_EOK); eth_dev->rx_pbuf_mb = ð_rx_pbuf_mb; - - + + result = eth_device_init(&(eth_dev->parent), "e0"); return result; } @@ -1433,13 +1429,13 @@ void PHY_Write(uint8_t addr , uint16_t data) } FINSH_FUNCTION_EXPORT(PHY_Write, (add, data)); -void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, +void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, uint8_t addr3, uint8_t addr4, uint8_t addr5) { uint32_t ulUser[2]; ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0; ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3; - + MAP_FlashUserSet(ulUser[0], ulUser[1]); MAP_FlashUserSave(); rt_kprintf("Save to EEPROM. please reboot."); diff --git a/bsp/tm4c129x/drivers/drv_eth.h b/bsp/tm4c129x/drivers/drv_eth.h index 54431405fe..2fa81e4f04 100644 --- a/bsp/tm4c129x/drivers/drv_eth.h +++ b/bsp/tm4c129x/drivers/drv_eth.h @@ -1,17 +1,13 @@ /* - * File : drv_eth.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2014-07-25 ArdaFu Port to TM4C129X */ - + #ifndef __TIVA_ETH_H__ #define __TIVA_ETH_H__ diff --git a/bsp/tm4c129x/drivers/drv_uart.c b/bsp/tm4c129x/drivers/drv_uart.c index ef95144af1..d1b26f3002 100644 --- a/bsp/tm4c129x/drivers/drv_uart.c +++ b/bsp/tm4c129x/drivers/drv_uart.c @@ -1,11 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,75 +30,75 @@ typedef struct hw_uart_device #define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data)) static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - uint32_t config = 0; - hw_uart_t* uart; +{ + uint32_t config = 0; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); - MAP_UARTDisable(uart->hw_base); - // build UART Configuration parameter structure + MAP_UARTDisable(uart->hw_base); + // build UART Configuration parameter structure switch(cfg->data_bits) - { - case DATA_BITS_9: - // enable 9bit address mode and set DATA_BIT_8 - MAP_UART9BitEnable(uart->hw_base); - case DATA_BITS_8: - config |= UART_CONFIG_WLEN_8; - break; - case DATA_BITS_7: - config |= UART_CONFIG_WLEN_7; - break; - case DATA_BITS_6: - config |= UART_CONFIG_WLEN_6; - break; - case DATA_BITS_5: - config |= UART_CONFIG_WLEN_5; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->parity) - { - case PARITY_ODD: - config |= UART_CONFIG_PAR_ODD; - break; - case PARITY_EVEN: - config |= UART_CONFIG_PAR_EVEN; - break; - case PARITY_NONE: - config |= UART_CONFIG_PAR_NONE; - break; - default: - RT_ASSERT(0); - break; - } - switch(cfg->stop_bits) - { - case STOP_BITS_1: - config |= UART_CONFIG_STOP_ONE; - break; - case STOP_BITS_2: - config |= UART_CONFIG_STOP_TWO; - break; - default: - RT_ASSERT(0); - break; - } - - // Initialize UART0 peripheral with given to corresponding parameter - MAP_UARTConfigSetExpClk(uart->hw_base, SystemCoreClock, cfg->baud_rate, config); - MAP_UARTFIFOEnable(uart->hw_base); + { + case DATA_BITS_9: + // enable 9bit address mode and set DATA_BIT_8 + MAP_UART9BitEnable(uart->hw_base); + case DATA_BITS_8: + config |= UART_CONFIG_WLEN_8; + break; + case DATA_BITS_7: + config |= UART_CONFIG_WLEN_7; + break; + case DATA_BITS_6: + config |= UART_CONFIG_WLEN_6; + break; + case DATA_BITS_5: + config |= UART_CONFIG_WLEN_5; + break; + default: + RT_ASSERT(0); + break; + } + switch(cfg->parity) + { + case PARITY_ODD: + config |= UART_CONFIG_PAR_ODD; + break; + case PARITY_EVEN: + config |= UART_CONFIG_PAR_EVEN; + break; + case PARITY_NONE: + config |= UART_CONFIG_PAR_NONE; + break; + default: + RT_ASSERT(0); + break; + } + switch(cfg->stop_bits) + { + case STOP_BITS_1: + config |= UART_CONFIG_STOP_ONE; + break; + case STOP_BITS_2: + config |= UART_CONFIG_STOP_TWO; + break; + default: + RT_ASSERT(0); + break; + } - // Enable the UART. - MAP_UARTEnable(uart->hw_base); + // Initialize UART0 peripheral with given to corresponding parameter + MAP_UARTConfigSetExpClk(uart->hw_base, SystemCoreClock, cfg->baud_rate, config); + MAP_UARTFIFOEnable(uart->hw_base); + + // Enable the UART. + MAP_UARTEnable(uart->hw_base); return RT_EOK; } static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg) { - hw_uart_t* uart; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); @@ -123,21 +119,21 @@ static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg) static int hw_putc(struct rt_serial_device *serial, char c) { - hw_uart_t* uart; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); - + MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c)); return 1; } static int hw_getc(struct rt_serial_device *serial) { - hw_uart_t* uart; + hw_uart_t* uart; RT_ASSERT(serial != RT_NULL); uart = mUartGetHwPtr(serial); - - return MAP_UARTCharGetNonBlocking(uart->hw_base); + + return MAP_UARTCharGetNonBlocking(uart->hw_base); } static const struct rt_uart_ops hw_uart_ops = @@ -158,7 +154,7 @@ hw_uart_t uart0 = void UART0_IRQHandler(void) { - uint32_t intsrc; + uint32_t intsrc; hw_uart_t *uart = &uart0; /* enter interrupt */ @@ -173,7 +169,7 @@ void UART0_IRQHandler(void) MAP_UARTIntClear(uart->hw_base, intsrc); rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); } - + /* leave interrupt */ rt_interrupt_leave(); } @@ -191,7 +187,7 @@ int rt_hw_uart_init(void) config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; - + #ifdef RT_USING_UART0 uart = &uart0; serial0.ops = &hw_uart_ops; @@ -200,7 +196,7 @@ int rt_hw_uart_init(void) MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); MAP_GPIOPinConfigure(GPIO_PA0_U0RX); MAP_GPIOPinConfigure(GPIO_PA1_U0TX); - + MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); @@ -208,15 +204,15 @@ int rt_hw_uart_init(void) //IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01)); /* Enable Interrupt for UART channel */ - UARTIntRegister(uart->hw_base, UART0_IRQHandler); - MAP_IntEnable(INT_UART0); - MAP_UARTEnable(uart->hw_base); + UARTIntRegister(uart->hw_base, UART0_IRQHandler); + MAP_IntEnable(INT_UART0); + MAP_UARTEnable(uart->hw_base); /* register UART0 device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif - return 0; + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/tm4c129x/drivers/drv_uart.h b/bsp/tm4c129x/drivers/drv_uart.h index 312c6da6b3..cd0bf1e0e3 100644 --- a/bsp/tm4c129x/drivers/drv_uart.h +++ b/bsp/tm4c129x/drivers/drv_uart.h @@ -1,11 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/components/dfs/src/dfs_file.c b/components/dfs/src/dfs_file.c index aa6494457a..802311b54e 100644 --- a/components/dfs/src/dfs_file.c +++ b/components/dfs/src/dfs_file.c @@ -615,6 +615,7 @@ void cat(const char *filename) } } while (length > 0); + rt_kprintf("\n"); dfs_file_close(&fd); } diff --git a/components/drivers/include/drivers/pin.h b/components/drivers/include/drivers/pin.h index 5ba1e6c8ea..38e5abea2a 100644 --- a/components/drivers/include/drivers/pin.h +++ b/components/drivers/include/drivers/pin.h @@ -13,7 +13,6 @@ #define PIN_H__ #include -#include #ifdef __cplusplus extern "C" { @@ -68,8 +67,6 @@ struct rt_pin_ops void (*pin_mode)(struct rt_device *device, rt_base_t pin, rt_base_t mode); void (*pin_write)(struct rt_device *device, rt_base_t pin, rt_base_t value); int (*pin_read)(struct rt_device *device, rt_base_t pin); - - /* TODO: add GPIO interrupt */ rt_err_t (*pin_attach_irq)(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args); rt_err_t (*pin_detach_irq)(struct rt_device *device, rt_int32_t pin); @@ -79,8 +76,6 @@ struct rt_pin_ops int rt_device_pin_register(const char *name, const struct rt_pin_ops *ops, void *user_data); -/* Get pin number by name,such as PA.0,P0.12 */ -rt_base_t rt_pin_get(const char *name); void rt_pin_mode(rt_base_t pin, rt_base_t mode); void rt_pin_write(rt_base_t pin, rt_base_t value); int rt_pin_read(rt_base_t pin); @@ -88,6 +83,8 @@ rt_err_t rt_pin_attach_irq(rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args); rt_err_t rt_pin_detach_irq(rt_int32_t pin); rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint32_t enabled); +/* Get pin number by name,such as PA.0,P0.12 */ +rt_base_t rt_pin_get(const char *name); #ifdef __cplusplus } diff --git a/components/drivers/include/drivers/sensor.h b/components/drivers/include/drivers/sensor.h new file mode 100644 index 0000000000..d071893eed --- /dev/null +++ b/components/drivers/include/drivers/sensor.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-31 flybreak first version + */ + +#ifndef __SENSOR_H__ +#define __SENSOR_H__ + +#include +#include "pin.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef RT_USING_RTC +#define rt_sensor_get_ts() time(RT_NULL) /* API for the sensor to get the timestamp */ +#else +#define rt_sensor_get_ts() rt_tick_get() /* API for the sensor to get the timestamp */ +#endif + +#define RT_PIN_NONE 0xFFFF /* RT PIN NONE */ +#define RT_DEVICE_FLAG_FIFO_RX 0x200 /* Flag to use when the sensor is open by fifo mode */ + +#define RT_SENSOR_MODULE_MAX (3) /* The maximum number of members of a sensor module */ + +/* Sensor types */ + +#define RT_SENSOR_CLASS_NONE (0) +#define RT_SENSOR_CLASS_ACCE (1) /* Accelerometer */ +#define RT_SENSOR_CLASS_GYRO (2) /* Gyroscope */ +#define RT_SENSOR_CLASS_MAG (3) /* Magnetometer */ +#define RT_SENSOR_CLASS_TEMP (4) /* Temperature */ +#define RT_SENSOR_CLASS_HUMI (5) /* Relative Humidity */ +#define RT_SENSOR_CLASS_BARO (6) /* Barometer */ +#define RT_SENSOR_CLASS_LIGHT (7) /* Ambient light */ +#define RT_SENSOR_CLASS_PROXIMITY (8) /* Proximity */ +#define RT_SENSOR_CLASS_HR (9) /* Heart Rate */ +#define RT_SENSOR_CLASS_TVOC (10) /* TVOC Level */ +#define RT_SENSOR_CLASS_NOISE (11) /* Noise Loudness */ +#define RT_SENSOR_CLASS_STEP (12) /* Step sensor */ +#define RT_SENSOR_CLASS_FORCE (13) /* Force sensor */ +#define RT_SENSOR_CLASS_DUST (14) /* Dust sensor */ +#define RT_SENSOR_CLASS_ECO2 (15) /* eCO2 sensor */ +#define RT_SENSOR_CLASS_GNSS (16) /* GPS/GNSS sensor */ +#define RT_SENSOR_CLASS_TOF (17) /* TOF sensor */ + +/* Sensor vendor types */ + +#define RT_SENSOR_VENDOR_UNKNOWN (0) +#define RT_SENSOR_VENDOR_STM (1) /* STMicroelectronics */ +#define RT_SENSOR_VENDOR_BOSCH (2) /* Bosch */ +#define RT_SENSOR_VENDOR_INVENSENSE (3) /* Invensense */ +#define RT_SENSOR_VENDOR_SEMTECH (4) /* Semtech */ +#define RT_SENSOR_VENDOR_GOERTEK (5) /* Goertek */ +#define RT_SENSOR_VENDOR_MIRAMEMS (6) /* MiraMEMS */ +#define RT_SENSOR_VENDOR_DALLAS (7) /* Dallas */ +#define RT_SENSOR_VENDOR_ASAIR (8) /* Aosong */ +#define RT_SENSOR_VENDOR_SHARP (9) /* Sharp */ +#define RT_SENSOR_VENDOR_SENSIRION (10) /* Sensirion */ +#define RT_SENSOR_VENDOR_TI (11) /* Texas Instruments */ +#define RT_SENSOR_VENDOR_PLANTOWER (12) /* Plantower */ +#define RT_SENSOR_VENDOR_AMS (13) /* ams AG */ +#define RT_SENSOR_VENDOR_MAXIM (14) /* Maxim Integrated */ + + +/* Sensor unit types */ + +#define RT_SENSOR_UNIT_NONE (0) +#define RT_SENSOR_UNIT_MG (1) /* Accelerometer unit: mG */ +#define RT_SENSOR_UNIT_MDPS (2) /* Gyroscope unit: mdps */ +#define RT_SENSOR_UNIT_MGAUSS (3) /* Magnetometer unit: mGauss */ +#define RT_SENSOR_UNIT_LUX (4) /* Ambient light unit: lux */ +#define RT_SENSOR_UNIT_CM (5) /* Distance unit: cm */ +#define RT_SENSOR_UNIT_PA (6) /* Barometer unit: pa */ +#define RT_SENSOR_UNIT_PERMILLAGE (7) /* Relative Humidity unit: permillage */ +#define RT_SENSOR_UNIT_DCELSIUS (8) /* Temperature unit: dCelsius */ +#define RT_SENSOR_UNIT_HZ (9) /* Frequency unit: HZ */ +#define RT_SENSOR_UNIT_ONE (10) /* Dimensionless quantity unit: 1 */ +#define RT_SENSOR_UNIT_BPM (11) /* Heart rate unit: bpm */ +#define RT_SENSOR_UNIT_MM (12) /* Distance unit: mm */ +#define RT_SENSOR_UNIT_MN (13) /* Force unit: mN */ +#define RT_SENSOR_UNIT_PPM (14) /* Concentration unit: ppm */ +#define RT_SENSOR_UNIT_PPB (15) /* Concentration unit: ppb */ +#define RT_SENSOR_UNIT_DMS (16) /* Coordinates unit: DMS */ +#define RT_SENSOR_UNIT_DD (17) /* Coordinates unit: DD */ + +/* Sensor communication interface types */ + +#define RT_SENSOR_INTF_I2C (1 << 0) +#define RT_SENSOR_INTF_SPI (1 << 1) +#define RT_SENSOR_INTF_UART (1 << 2) +#define RT_SENSOR_INTF_ONEWIRE (1 << 3) + +/* Sensor power mode types */ + +#define RT_SENSOR_POWER_NONE (0) +#define RT_SENSOR_POWER_DOWN (1) /* power down mode */ +#define RT_SENSOR_POWER_NORMAL (2) /* normal-power mode */ +#define RT_SENSOR_POWER_LOW (3) /* low-power mode */ +#define RT_SENSOR_POWER_HIGH (4) /* high-power mode */ + +/* Sensor work mode types */ + +#define RT_SENSOR_MODE_NONE (0) +#define RT_SENSOR_MODE_POLLING (1) /* One shot only read a data */ +#define RT_SENSOR_MODE_INT (2) /* TODO: One shot interrupt only read a data */ +#define RT_SENSOR_MODE_FIFO (3) /* TODO: One shot interrupt read all fifo data */ + +/* Sensor control cmd types */ + +#define RT_SENSOR_CTRL_GET_ID (0) /* Get device id */ +#define RT_SENSOR_CTRL_GET_INFO (1) /* Get sensor info */ +#define RT_SENSOR_CTRL_SET_RANGE (2) /* Set the measure range of sensor. unit is info of sensor */ +#define RT_SENSOR_CTRL_SET_ODR (3) /* Set output date rate. unit is HZ */ +#define RT_SENSOR_CTRL_SET_MODE (4) /* Set sensor's work mode. ex. RT_SENSOR_MODE_POLLING,RT_SENSOR_MODE_INT */ +#define RT_SENSOR_CTRL_SET_POWER (5) /* Set power mode. args type of sensor power mode. ex. RT_SENSOR_POWER_DOWN,RT_SENSOR_POWER_NORMAL */ +#define RT_SENSOR_CTRL_SELF_TEST (6) /* Take a self test */ + +#define RT_SENSOR_CTRL_USER_CMD_START 0x100 /* User commands should be greater than 0x100 */ + +struct rt_sensor_info +{ + rt_uint8_t type; /* The sensor type */ + rt_uint8_t vendor; /* Vendor of sensors */ + const char *model; /* model name of sensor */ + rt_uint8_t unit; /* unit of measurement */ + rt_uint8_t intf_type; /* Communication interface type */ + rt_int32_t range_max; /* maximum range of this sensor's value. unit is 'unit' */ + rt_int32_t range_min; /* minimum range of this sensor's value. unit is 'unit' */ + rt_uint32_t period_min; /* Minimum measurement period,unit:ms. zero = not a constant rate */ + rt_uint8_t fifo_max; +}; + +struct rt_sensor_intf +{ + char *dev_name; /* The name of the communication device */ + rt_uint8_t type; /* Communication interface type */ + void *user_data; /* Private data for the sensor. ex. i2c addr,spi cs,control I/O */ +}; + +struct rt_sensor_config +{ + struct rt_sensor_intf intf; /* sensor interface config */ + struct rt_device_pin_mode irq_pin; /* Interrupt pin, The purpose of this pin is to notification read data */ + rt_uint8_t mode; /* sensor work mode */ + rt_uint8_t power; /* sensor power mode */ + rt_uint16_t odr; /* sensor out data rate */ + rt_int32_t range; /* sensor range of measurement */ +}; + +typedef struct rt_sensor_device *rt_sensor_t; + +struct rt_sensor_device +{ + struct rt_device parent; /* The standard device */ + + struct rt_sensor_info info; /* The sensor info data */ + struct rt_sensor_config config; /* The sensor config data */ + + void *data_buf; /* The buf of the data received */ + rt_size_t data_len; /* The size of the data received */ + + const struct rt_sensor_ops *ops; /* The sensor ops */ + + struct rt_sensor_module *module; /* The sensor module */ + + rt_err_t (*irq_handle)(rt_sensor_t sensor); /* Called when an interrupt is generated, registered by the driver */ +}; + +struct rt_sensor_module +{ + rt_mutex_t lock; /* The module lock */ + + rt_sensor_t sen[RT_SENSOR_MODULE_MAX]; /* The module contains a list of sensors */ + rt_uint8_t sen_num; /* Number of sensors contained in the module */ +}; + +/* 3-axis Data Type */ +struct sensor_3_axis +{ + rt_int32_t x; + rt_int32_t y; + rt_int32_t z; +}; + +struct coordinates +{ + double longitude; + double latitude; +}; + +struct rt_sensor_data +{ + rt_uint32_t timestamp; /* The timestamp when the data was received */ + rt_uint8_t type; /* The sensor type of the data */ + union + { + struct sensor_3_axis acce; /* Accelerometer. unit: mG */ + struct sensor_3_axis gyro; /* Gyroscope. unit: mdps */ + struct sensor_3_axis mag; /* Magnetometer. unit: mGauss */ + struct coordinates coord; /* Coordinates unit: degrees */ + rt_int32_t temp; /* Temperature. unit: dCelsius */ + rt_int32_t humi; /* Relative humidity. unit: permillage */ + rt_int32_t baro; /* Pressure. unit: pascal (Pa) */ + rt_int32_t light; /* Light. unit: lux */ + rt_int32_t proximity; /* Distance. unit: centimeters */ + rt_int32_t hr; /* Heart rate. unit: bpm */ + rt_int32_t tvoc; /* TVOC. unit: permillage */ + rt_int32_t noise; /* Noise Loudness. unit: HZ */ + rt_uint32_t step; /* Step sensor. unit: 1 */ + rt_int32_t force; /* Force sensor. unit: mN */ + rt_uint32_t dust; /* Dust sensor. unit: ug/m3 */ + rt_uint32_t eco2; /* eCO2 sensor. unit: ppm */ + } data; +}; + +struct rt_sensor_ops +{ + rt_size_t (*fetch_data)(struct rt_sensor_device *sensor, void *buf, rt_size_t len); + rt_err_t (*control)(struct rt_sensor_device *sensor, int cmd, void *arg); +}; + +int rt_hw_sensor_register(rt_sensor_t sensor, + const char *name, + rt_uint32_t flag, + void *data); + +#ifdef __cplusplus +} +#endif + +#endif /* __SENSOR_H__ */ diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 82868e5aef..fbd3c9e7b2 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -78,70 +78,76 @@ extern "C" { #include "drivers/mmcsd_core.h" #include "drivers/sd.h" #include "drivers/sdio.h" -#endif +#endif /* RT_USING_SDIO */ + #ifdef RT_USING_WDT #include "drivers/watchdog.h" -#endif +#endif /* RT_USING_WDT */ #ifdef RT_USING_PIN #include "drivers/pin.h" -#endif +#endif /* RT_USING_PIN */ + +#ifdef RT_USING_SENSOR +#include "drivers/sensor.h" +#endif /* RT_USING_SENSOR */ #ifdef RT_USING_CAN #include "drivers/can.h" -#endif +#endif /* RT_USING_CAN */ #ifdef RT_USING_HWTIMER #include "drivers/hwtimer.h" -#endif +#endif /* RT_USING_HWTIMER */ #ifdef RT_USING_AUDIO #include "drivers/audio.h" -#endif +#endif /* RT_USING_AUDIO */ #ifdef RT_USING_CPUTIME #include "drivers/cputime.h" -#endif +#endif /* RT_USING_CPUTIME */ #ifdef RT_USING_ADC #include "drivers/adc.h" -#endif +#endif /* RT_USING_ADC */ #ifdef RT_USING_DAC #include "drivers/dac.h" -#endif +#endif /* RT_USING_DAC */ #ifdef RT_USING_PWM #include "drivers/rt_drv_pwm.h" -#endif +#endif /* RT_USING_PWM */ #ifdef RT_USING_PM #include "drivers/pm.h" -#endif +#endif /* RT_USING_PM */ #ifdef RT_USING_WIFI #include "drivers/wlan.h" -#endif +#endif /* RT_USING_WIFI */ #ifdef MTD_USING_NOR #include "drivers/mtdnor.h" -#endif +#endif /* MTD_USING_NOR */ + #ifdef MTD_USING_NAND #include "drivers/mtdnand.h" -#endif +#endif /* MTD_USING_NAND */ #ifdef RT_USING_HWCRYPTO #include "drivers/crypto.h" -#endif +#endif /* RT_USING_HWCRYPTO */ #ifdef RT_USING_PULSE_ENCODER #include "drivers/pulse_encoder.h" -#endif +#endif /* RT_USING_PULSE_ENCODER */ #ifdef RT_USING_INPUT_CAPTURE #include "drivers/rt_inputcapture.h" -#endif +#endif /* RT_USING_INPUT_CAPTURE */ #ifdef __cplusplus } diff --git a/components/drivers/sensors/sensor.c b/components/drivers/sensors/sensor.c index ccc1fca34e..6d584e568e 100644 --- a/components/drivers/sensors/sensor.c +++ b/components/drivers/sensors/sensor.c @@ -121,12 +121,30 @@ static rt_err_t rt_sensor_irq_init(rt_sensor_t sensor) return 0; } +// local rt_sensor_ops + +static rt_size_t local_fetch_data(struct rt_sensor_device *sensor, void *buf, rt_size_t len) +{ + LOG_D("Undefined fetch_data"); + return 0; +} +static rt_err_t local_control(struct rt_sensor_device *sensor, int cmd, void *arg) +{ + LOG_D("Undefined control"); + return RT_ERROR; +} +static struct rt_sensor_ops local_ops = { + .fetch_data = local_fetch_data, + .control = local_control +}; + /* RT-Thread Device Interface */ static rt_err_t rt_sensor_open(rt_device_t dev, rt_uint16_t oflag) { rt_sensor_t sensor = (rt_sensor_t)dev; RT_ASSERT(dev != RT_NULL); rt_err_t res = RT_EOK; + rt_err_t (*local_ctrl)(struct rt_sensor_device *sensor, int cmd, void *arg) = local_control; if (sensor->module) { @@ -144,37 +162,36 @@ static rt_err_t rt_sensor_open(rt_device_t dev, rt_uint16_t oflag) goto __exit; } } + if (sensor->ops->control != RT_NULL) + { + local_ctrl = sensor->ops->control; + } + sensor->config.mode = RT_SENSOR_MODE_POLLING; if (oflag & RT_DEVICE_FLAG_RDONLY && dev->flag & RT_DEVICE_FLAG_RDONLY) { - if (sensor->ops->control != RT_NULL) - { - /* If polling mode is supported, configure it to polling mode */ - sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_MODE, (void *)RT_SENSOR_MODE_POLLING); - } - sensor->config.mode = RT_SENSOR_MODE_POLLING; + /* If polling mode is supported, configure it to polling mode */ + local_ctrl(sensor, RT_SENSOR_CTRL_SET_MODE, (void *)RT_SENSOR_MODE_POLLING); } else if (oflag & RT_DEVICE_FLAG_INT_RX && dev->flag & RT_DEVICE_FLAG_INT_RX) { - if (sensor->ops->control != RT_NULL) + /* If interrupt mode is supported, configure it to interrupt mode */ + if (local_ctrl(sensor, RT_SENSOR_CTRL_SET_MODE, (void *)RT_SENSOR_MODE_INT) == RT_EOK) { - /* If interrupt mode is supported, configure it to interrupt mode */ - sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_MODE, (void *)RT_SENSOR_MODE_INT); + /* Initialization sensor interrupt */ + rt_sensor_irq_init(sensor); + sensor->config.mode = RT_SENSOR_MODE_INT; } - /* Initialization sensor interrupt */ - rt_sensor_irq_init(sensor); - sensor->config.mode = RT_SENSOR_MODE_INT; } else if (oflag & RT_DEVICE_FLAG_FIFO_RX && dev->flag & RT_DEVICE_FLAG_FIFO_RX) { - if (sensor->ops->control != RT_NULL) + /* If fifo mode is supported, configure it to fifo mode */ + if (local_ctrl(sensor, RT_SENSOR_CTRL_SET_MODE, (void *)RT_SENSOR_MODE_FIFO) == RT_EOK) { - /* If fifo mode is supported, configure it to fifo mode */ - sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_MODE, (void *)RT_SENSOR_MODE_FIFO); + /* Initialization sensor interrupt */ + rt_sensor_irq_init(sensor); + sensor->config.mode = RT_SENSOR_MODE_FIFO; } - /* Initialization sensor interrupt */ - rt_sensor_irq_init(sensor); - sensor->config.mode = RT_SENSOR_MODE_FIFO; } else { @@ -183,7 +200,7 @@ static rt_err_t rt_sensor_open(rt_device_t dev, rt_uint16_t oflag) } /* Configure power mode to normal mode */ - if (sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_POWER, (void *)RT_SENSOR_POWER_NORMAL) == RT_EOK) + if (local_ctrl(sensor, RT_SENSOR_CTRL_SET_POWER, (void *)RT_SENSOR_POWER_NORMAL) == RT_EOK) { sensor->config.power = RT_SENSOR_POWER_NORMAL; } @@ -202,6 +219,7 @@ static rt_err_t rt_sensor_close(rt_device_t dev) { rt_sensor_t sensor = (rt_sensor_t)dev; int i; + rt_err_t (*local_ctrl)(struct rt_sensor_device * sensor, int cmd, void *arg) = local_control; RT_ASSERT(dev != RT_NULL); @@ -209,9 +227,13 @@ static rt_err_t rt_sensor_close(rt_device_t dev) { rt_mutex_take(sensor->module->lock, RT_WAITING_FOREVER); } + if (sensor->ops->control != RT_NULL) + { + local_ctrl = sensor->ops->control; + } /* Configure power mode to power down mode */ - if (sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_POWER, (void *)RT_SENSOR_POWER_DOWN) == RT_EOK) + if (local_ctrl(sensor, RT_SENSOR_CTRL_SET_POWER, (void *)RT_SENSOR_POWER_DOWN) == RT_EOK) { sensor->config.power = RT_SENSOR_POWER_DOWN; } @@ -234,10 +256,13 @@ static rt_err_t rt_sensor_close(rt_device_t dev) } } } - /* Sensor disable interrupt */ - if (sensor->config.irq_pin.pin != RT_PIN_NONE) + if (sensor->config.mode != RT_SENSOR_MODE_POLLING) { - rt_pin_irq_enable(sensor->config.irq_pin.pin, RT_FALSE); + /* Sensor disable interrupt */ + if (sensor->config.irq_pin.pin != RT_PIN_NONE) + { + rt_pin_irq_enable(sensor->config.irq_pin.pin, RT_FALSE); + } } __exit: @@ -282,7 +307,10 @@ static rt_size_t rt_sensor_read(rt_device_t dev, rt_off_t pos, void *buf, rt_siz else { /* If the buffer is empty read the data */ - result = sensor->ops->fetch_data(sensor, buf, len); + if (sensor->ops->fetch_data != RT_NULL) + { + result = sensor->ops->fetch_data(sensor, buf, len); + } } if (sensor->module) @@ -298,18 +326,23 @@ static rt_err_t rt_sensor_control(rt_device_t dev, int cmd, void *args) rt_sensor_t sensor = (rt_sensor_t)dev; rt_err_t result = RT_EOK; RT_ASSERT(dev != RT_NULL); + rt_err_t (*local_ctrl)(struct rt_sensor_device * sensor, int cmd, void *arg) = local_control; if (sensor->module) { rt_mutex_take(sensor->module->lock, RT_WAITING_FOREVER); } + if (sensor->ops->control != RT_NULL) + { + local_ctrl = sensor->ops->control; + } switch (cmd) { case RT_SENSOR_CTRL_GET_ID: if (args) { - result = sensor->ops->control(sensor, RT_SENSOR_CTRL_GET_ID, args); + result = local_ctrl(sensor, RT_SENSOR_CTRL_GET_ID, args); } break; case RT_SENSOR_CTRL_GET_INFO: @@ -319,19 +352,17 @@ static rt_err_t rt_sensor_control(rt_device_t dev, int cmd, void *args) } break; case RT_SENSOR_CTRL_SET_RANGE: - /* Configuration measurement range */ - result = sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_RANGE, args); + result = local_ctrl(sensor, RT_SENSOR_CTRL_SET_RANGE, args); if (result == RT_EOK) { sensor->config.range = (rt_int32_t)args; LOG_D("set range %d", sensor->config.range); - } + } break; case RT_SENSOR_CTRL_SET_ODR: - /* Configuration data output rate */ - result = sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_ODR, args); + result = local_ctrl(sensor, RT_SENSOR_CTRL_SET_ODR, args); if (result == RT_EOK) { sensor->config.odr = (rt_uint32_t)args & 0xFFFF; @@ -339,9 +370,8 @@ static rt_err_t rt_sensor_control(rt_device_t dev, int cmd, void *args) } break; case RT_SENSOR_CTRL_SET_POWER: - /* Configuration sensor power mode */ - result = sensor->ops->control(sensor, RT_SENSOR_CTRL_SET_POWER, args); + result = local_ctrl(sensor, RT_SENSOR_CTRL_SET_POWER, args); if (result == RT_EOK) { sensor->config.power = (rt_uint32_t)args & 0xFF; @@ -349,16 +379,15 @@ static rt_err_t rt_sensor_control(rt_device_t dev, int cmd, void *args) } break; case RT_SENSOR_CTRL_SELF_TEST: - /* Device self-test */ - result = sensor->ops->control(sensor, RT_SENSOR_CTRL_SELF_TEST, args); + result = local_ctrl(sensor, RT_SENSOR_CTRL_SELF_TEST, args); break; default: if (cmd > RT_SENSOR_CTRL_USER_CMD_START) { /* Custom commands */ - result = sensor->ops->control(sensor, cmd, args); + result = local_ctrl(sensor, cmd, args); } else { @@ -387,6 +416,7 @@ const static struct rt_device_ops rt_sensor_ops = }; #endif + /* * sensor register */ @@ -401,6 +431,11 @@ int rt_hw_sensor_register(rt_sensor_t sensor, char *sensor_name = RT_NULL, *device_name = RT_NULL; + if (sensor->ops == RT_NULL) + { + sensor->ops = &local_ops; + } + /* Add a type name for the sensor device */ sensor_name = sensor_name_str[sensor->info.type]; device_name = (char *)rt_calloc(1, rt_strlen(sensor_name) + 1 + rt_strlen(name)); @@ -444,12 +479,12 @@ int rt_hw_sensor_register(rt_sensor_t sensor, result = rt_device_register(device, device_name, flag | RT_DEVICE_FLAG_STANDALONE); if (result != RT_EOK) { + LOG_E("rt_sensor[%s] register err code: %d", device_name, result); rt_free(device_name); - LOG_E("rt_sensor register err code: %d", result); return result; } rt_free(device_name); - LOG_I("rt_sensor init success"); + LOG_I("rt_sensor[%s] init success", device_name); return RT_EOK; } diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index f54d4e8799..761ee49b4c 100755 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -8,231 +8,7 @@ * 2019-01-31 flybreak first version */ -#ifndef __SENSOR_H__ -#define __SENSOR_H__ #include #include -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef RT_USING_RTC -#define rt_sensor_get_ts() time(RT_NULL) /* API for the sensor to get the timestamp */ -#else -#define rt_sensor_get_ts() rt_tick_get() /* API for the sensor to get the timestamp */ -#endif - -#define RT_PIN_NONE 0xFFFF /* RT PIN NONE */ -#define RT_DEVICE_FLAG_FIFO_RX 0x200 /* Flag to use when the sensor is open by fifo mode */ - -#define RT_SENSOR_MODULE_MAX (3) /* The maximum number of members of a sensor module */ - -/* Sensor types */ - -#define RT_SENSOR_CLASS_NONE (0) -#define RT_SENSOR_CLASS_ACCE (1) /* Accelerometer */ -#define RT_SENSOR_CLASS_GYRO (2) /* Gyroscope */ -#define RT_SENSOR_CLASS_MAG (3) /* Magnetometer */ -#define RT_SENSOR_CLASS_TEMP (4) /* Temperature */ -#define RT_SENSOR_CLASS_HUMI (5) /* Relative Humidity */ -#define RT_SENSOR_CLASS_BARO (6) /* Barometer */ -#define RT_SENSOR_CLASS_LIGHT (7) /* Ambient light */ -#define RT_SENSOR_CLASS_PROXIMITY (8) /* Proximity */ -#define RT_SENSOR_CLASS_HR (9) /* Heart Rate */ -#define RT_SENSOR_CLASS_TVOC (10) /* TVOC Level */ -#define RT_SENSOR_CLASS_NOISE (11) /* Noise Loudness */ -#define RT_SENSOR_CLASS_STEP (12) /* Step sensor */ -#define RT_SENSOR_CLASS_FORCE (13) /* Force sensor */ -#define RT_SENSOR_CLASS_DUST (14) /* Dust sensor */ -#define RT_SENSOR_CLASS_ECO2 (15) /* eCO2 sensor */ -#define RT_SENSOR_CLASS_GNSS (16) /* GPS/GNSS sensor */ -#define RT_SENSOR_CLASS_TOF (17) /* TOF sensor */ - -/* Sensor vendor types */ - -#define RT_SENSOR_VENDOR_UNKNOWN (0) -#define RT_SENSOR_VENDOR_STM (1) /* STMicroelectronics */ -#define RT_SENSOR_VENDOR_BOSCH (2) /* Bosch */ -#define RT_SENSOR_VENDOR_INVENSENSE (3) /* Invensense */ -#define RT_SENSOR_VENDOR_SEMTECH (4) /* Semtech */ -#define RT_SENSOR_VENDOR_GOERTEK (5) /* Goertek */ -#define RT_SENSOR_VENDOR_MIRAMEMS (6) /* MiraMEMS */ -#define RT_SENSOR_VENDOR_DALLAS (7) /* Dallas */ -#define RT_SENSOR_VENDOR_ASAIR (8) /* Aosong */ -#define RT_SENSOR_VENDOR_SHARP (9) /* Sharp */ -#define RT_SENSOR_VENDOR_SENSIRION (10) /* Sensirion */ -#define RT_SENSOR_VENDOR_TI (11) /* Texas Instruments */ -#define RT_SENSOR_VENDOR_PLANTOWER (12) /* Plantower */ -#define RT_SENSOR_VENDOR_AMS (13) /* ams AG */ -#define RT_SENSOR_VENDOR_MAXIM (14) /* Maxim Integrated */ - - -/* Sensor unit types */ - -#define RT_SENSOR_UNIT_NONE (0) -#define RT_SENSOR_UNIT_MG (1) /* Accelerometer unit: mG */ -#define RT_SENSOR_UNIT_MDPS (2) /* Gyroscope unit: mdps */ -#define RT_SENSOR_UNIT_MGAUSS (3) /* Magnetometer unit: mGauss */ -#define RT_SENSOR_UNIT_LUX (4) /* Ambient light unit: lux */ -#define RT_SENSOR_UNIT_CM (5) /* Distance unit: cm */ -#define RT_SENSOR_UNIT_PA (6) /* Barometer unit: pa */ -#define RT_SENSOR_UNIT_PERMILLAGE (7) /* Relative Humidity unit: permillage */ -#define RT_SENSOR_UNIT_DCELSIUS (8) /* Temperature unit: dCelsius */ -#define RT_SENSOR_UNIT_HZ (9) /* Frequency unit: HZ */ -#define RT_SENSOR_UNIT_ONE (10) /* Dimensionless quantity unit: 1 */ -#define RT_SENSOR_UNIT_BPM (11) /* Heart rate unit: bpm */ -#define RT_SENSOR_UNIT_MM (12) /* Distance unit: mm */ -#define RT_SENSOR_UNIT_MN (13) /* Force unit: mN */ -#define RT_SENSOR_UNIT_PPM (14) /* Concentration unit: ppm */ -#define RT_SENSOR_UNIT_PPB (15) /* Concentration unit: ppb */ -#define RT_SENSOR_UNIT_DMS (16) /* Coordinates unit: DMS */ -#define RT_SENSOR_UNIT_DD (17) /* Coordinates unit: DD */ - -/* Sensor communication interface types */ - -#define RT_SENSOR_INTF_I2C (1 << 0) -#define RT_SENSOR_INTF_SPI (1 << 1) -#define RT_SENSOR_INTF_UART (1 << 2) -#define RT_SENSOR_INTF_ONEWIRE (1 << 3) - -/* Sensor power mode types */ - -#define RT_SENSOR_POWER_NONE (0) -#define RT_SENSOR_POWER_DOWN (1) /* power down mode */ -#define RT_SENSOR_POWER_NORMAL (2) /* normal-power mode */ -#define RT_SENSOR_POWER_LOW (3) /* low-power mode */ -#define RT_SENSOR_POWER_HIGH (4) /* high-power mode */ - -/* Sensor work mode types */ - -#define RT_SENSOR_MODE_NONE (0) -#define RT_SENSOR_MODE_POLLING (1) /* One shot only read a data */ -#define RT_SENSOR_MODE_INT (2) /* TODO: One shot interrupt only read a data */ -#define RT_SENSOR_MODE_FIFO (3) /* TODO: One shot interrupt read all fifo data */ - -/* Sensor control cmd types */ - -#define RT_SENSOR_CTRL_GET_ID (0) /* Get device id */ -#define RT_SENSOR_CTRL_GET_INFO (1) /* Get sensor info */ -#define RT_SENSOR_CTRL_SET_RANGE (2) /* Set the measure range of sensor. unit is info of sensor */ -#define RT_SENSOR_CTRL_SET_ODR (3) /* Set output date rate. unit is HZ */ -#define RT_SENSOR_CTRL_SET_MODE (4) /* Set sensor's work mode. ex. RT_SENSOR_MODE_POLLING,RT_SENSOR_MODE_INT */ -#define RT_SENSOR_CTRL_SET_POWER (5) /* Set power mode. args type of sensor power mode. ex. RT_SENSOR_POWER_DOWN,RT_SENSOR_POWER_NORMAL */ -#define RT_SENSOR_CTRL_SELF_TEST (6) /* Take a self test */ - -#define RT_SENSOR_CTRL_USER_CMD_START 0x100 /* User commands should be greater than 0x100 */ - -struct rt_sensor_info -{ - rt_uint8_t type; /* The sensor type */ - rt_uint8_t vendor; /* Vendor of sensors */ - const char *model; /* model name of sensor */ - rt_uint8_t unit; /* unit of measurement */ - rt_uint8_t intf_type; /* Communication interface type */ - rt_int32_t range_max; /* maximum range of this sensor's value. unit is 'unit' */ - rt_int32_t range_min; /* minimum range of this sensor's value. unit is 'unit' */ - rt_uint32_t period_min; /* Minimum measurement period,unit:ms. zero = not a constant rate */ - rt_uint8_t fifo_max; -}; - -struct rt_sensor_intf -{ - char *dev_name; /* The name of the communication device */ - rt_uint8_t type; /* Communication interface type */ - void *user_data; /* Private data for the sensor. ex. i2c addr,spi cs,control I/O */ -}; - -struct rt_sensor_config -{ - struct rt_sensor_intf intf; /* sensor interface config */ - struct rt_device_pin_mode irq_pin; /* Interrupt pin, The purpose of this pin is to notification read data */ - rt_uint8_t mode; /* sensor work mode */ - rt_uint8_t power; /* sensor power mode */ - rt_uint16_t odr; /* sensor out data rate */ - rt_int32_t range; /* sensor range of measurement */ -}; - -typedef struct rt_sensor_device *rt_sensor_t; - -struct rt_sensor_device -{ - struct rt_device parent; /* The standard device */ - - struct rt_sensor_info info; /* The sensor info data */ - struct rt_sensor_config config; /* The sensor config data */ - - void *data_buf; /* The buf of the data received */ - rt_size_t data_len; /* The size of the data received */ - - const struct rt_sensor_ops *ops; /* The sensor ops */ - - struct rt_sensor_module *module; /* The sensor module */ - - rt_err_t (*irq_handle)(rt_sensor_t sensor); /* Called when an interrupt is generated, registered by the driver */ -}; - -struct rt_sensor_module -{ - rt_mutex_t lock; /* The module lock */ - - rt_sensor_t sen[RT_SENSOR_MODULE_MAX]; /* The module contains a list of sensors */ - rt_uint8_t sen_num; /* Number of sensors contained in the module */ -}; - -/* 3-axis Data Type */ -struct sensor_3_axis -{ - rt_int32_t x; - rt_int32_t y; - rt_int32_t z; -}; - -struct coordinates -{ - double longitude; - double latitude; -}; - -struct rt_sensor_data -{ - rt_uint32_t timestamp; /* The timestamp when the data was received */ - rt_uint8_t type; /* The sensor type of the data */ - union - { - struct sensor_3_axis acce; /* Accelerometer. unit: mG */ - struct sensor_3_axis gyro; /* Gyroscope. unit: mdps */ - struct sensor_3_axis mag; /* Magnetometer. unit: mGauss */ - struct coordinates coord; /* Coordinates unit: degrees */ - rt_int32_t temp; /* Temperature. unit: dCelsius */ - rt_int32_t humi; /* Relative humidity. unit: permillage */ - rt_int32_t baro; /* Pressure. unit: pascal (Pa) */ - rt_int32_t light; /* Light. unit: lux */ - rt_int32_t proximity; /* Distance. unit: centimeters */ - rt_int32_t hr; /* Heart rate. unit: bpm */ - rt_int32_t tvoc; /* TVOC. unit: permillage */ - rt_int32_t noise; /* Noise Loudness. unit: HZ */ - rt_uint32_t step; /* Step sensor. unit: 1 */ - rt_int32_t force; /* Force sensor. unit: mN */ - rt_uint32_t dust; /* Dust sensor. unit: ug/m3 */ - rt_uint32_t eco2; /* eCO2 sensor. unit: ppm */ - } data; -}; - -struct rt_sensor_ops -{ - rt_size_t (*fetch_data)(struct rt_sensor_device *sensor, void *buf, rt_size_t len); - rt_err_t (*control)(struct rt_sensor_device *sensor, int cmd, void *arg); -}; - -int rt_hw_sensor_register(rt_sensor_t sensor, - const char *name, - rt_uint32_t flag, - void *data); - -#ifdef __cplusplus -} -#endif - -#endif /* __SENSOR_H__ */ diff --git a/components/drivers/sensors/sensor_cmd.c b/components/drivers/sensors/sensor_cmd.c index 5c2d22640c..0f0ab66d63 100755 --- a/components/drivers/sensors/sensor_cmd.c +++ b/components/drivers/sensors/sensor_cmd.c @@ -231,6 +231,7 @@ static void sensor_polling(int argc, char **argv) struct rt_sensor_data data; rt_size_t res, i; rt_int32_t delay; + rt_err_t result; dev = rt_device_find(argv[1]); if (dev == RT_NULL) @@ -244,9 +245,10 @@ static void sensor_polling(int argc, char **argv) sensor = (rt_sensor_t)dev; delay = sensor->info.period_min > 100 ? sensor->info.period_min : 100; - if (rt_device_open(dev, RT_DEVICE_FLAG_RDWR) != RT_EOK) + result = rt_device_open(dev, RT_DEVICE_FLAG_RDONLY); + if (result != RT_EOK) { - LOG_E("open device failed!"); + LOG_E("open device failed! error code : %d", result); return; } rt_device_control(dev, RT_SENSOR_CTRL_SET_ODR, (void *)100); @@ -451,7 +453,7 @@ static void sensor(int argc, char **argv) dev = rt_device_find(argv[2]); if (dev == RT_NULL) { - LOG_E("Can't find device:%s", argv[1]); + LOG_E("Can't find device:%s", argv[2]); return; } if (rt_device_open(dev, RT_DEVICE_FLAG_RDWR) != RT_EOK) diff --git a/components/libc/compilers/common/time.c b/components/libc/compilers/common/time.c index 0bad6bdf8e..083ae9be6c 100644 --- a/components/libc/compilers/common/time.c +++ b/components/libc/compilers/common/time.c @@ -16,6 +16,7 @@ * 2012-12-08 Bernard fix the issue of _timevalue.tv_usec initialization, * which found by Rob * 2021-02-12 Meco Man move all of the functions located in to this file + * 2021-03-15 Meco Man fixed bug: https://club.rt-thread.org/ask/question/423650.html */ #include @@ -152,13 +153,14 @@ char* asctime_r(const struct tm *t, char *buf) num2str(buf + 20, (t->tm_year + 1900) / 100); num2str(buf + 22, (t->tm_year + 1900) % 100); buf[24] = '\n'; + buf[25] = '\0'; return buf; } RTM_EXPORT(asctime_r); char* asctime(const struct tm *timeptr) { - static char buf[25]; + static char buf[26]; return asctime_r(timeptr, buf); } RTM_EXPORT(asctime); diff --git a/include/rtdef.h b/include/rtdef.h index 38686492b1..b936a33455 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -198,7 +198,7 @@ typedef rt_base_t rt_off_t; /**< Type for offset */ #define RT_UNUSED __attribute__((unused)) #define RT_USED __attribute__((used, protect)) #define PRAGMA(x) _Pragma(#x) - #define ALIGN(n) __attribute__((aligned(n))) + #define ALIGN(n) __attribute__((__align(n))) #define RT_WEAK __attribute__((weak)) #define rt_inline static inline #define RTT_API