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Merge pull request #18 from RT-Thread/master

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This commit is contained in:
Meco Jianting Man authored and GitHub committed 2021-02-18 01:30:19 -06:00
2 parents e19873db6d 6420c27791
commit 8ea33c2101
61 files changed
+4070 -565
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bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_ertc.h
+3
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@@ -11,6 +11,9 @@
#ifndef __AT32F4xx_ERTC_H
#define __AT32F4xx_ERTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f4xx.h"
bsp/at32/Libraries/rt_drivers/SConscript
+6
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@@ -43,9 +43,15 @@ if GetDepend('BSP_USING_SRAM'):
if GetDepend('BSP_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
src += ['drv_flash.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_CAN']):
src += ['drv_can.c']
if GetDepend(['BSP_USING_SDIO']):
src += ['drv_sdio.c']
bsp/at32/Libraries/rt_drivers/drv_can.c
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bsp/at32/Libraries/rt_drivers/drv_can.h
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@@ -0,0 +1,58 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-09 shelton the first version
*/
#ifndef __DRV_CAN_H__
#define __DRV_CAN_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <board.h>
#include <rtdevice.h>
#include <rtthread.h>
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
struct at32_baud_rate_tab
{
rt_uint32_t baud_rate;
rt_uint32_t sjw;
rt_uint32_t bs1;
rt_uint32_t bs2;
rt_uint32_t psc;
};
struct CAN_Handler
{
CAN_Type *Instance;
CAN_InitType CanInit;
CAN_FilterInitType FilterConfig;
};
/* at32 can device */
struct at32_can
{
char *name;
struct CAN_Handler CanConfig;
struct rt_can_device device; /* inherit from can device */
};
int rt_hw_can_init(void);
#ifdef __cplusplus
}
#endif
#endif /*__DRV_CAN_H__ */
/************************** end of file ******************/
bsp/at32/Libraries/rt_drivers/drv_flash.c
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bsp/at32/Libraries/rt_drivers/drv_flash.h
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@@ -0,0 +1,30 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-09 shelton the first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#ifdef __cplusplus
extern "C" {
#endif
int at32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int at32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int at32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */
bsp/at32/at32f403a-start/README.md
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@@ -46,8 +46,10 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| PWM | 支持 | TMR1/2 |
| HWTIMER | 支持 | TMR3/4/5 |
| SDIO | 支持 | SDIO1 |
| CAN | 支持 | CAN1/2 |
| WDT | 支持 | |
| RTC | 支持 | |
| FLASH | 支持 | |
### IO在板级支持包中的映射情况
@@ -88,6 +90,10 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| PC3 | ADC1/2_IN13 |
| PC4 | ADC1/2_IN14 |
| PC5 | ADC1/2_IN15 |
| PA11 | CAN1_RX |
| PA12 | CAN1_TX |
| PB5 | CAN2_RX |
| PB6 | CAN2_TX |
## 使用说明
bsp/at32/at32f403a-start/board/Kconfig
+17
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@@ -24,6 +24,10 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
menuconfig BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
@@ -151,6 +155,19 @@ menu "On-chip Peripheral Drivers"
default n
endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
if BSP_USING_CAN
config BSP_USING_CAN1
bool "using CAN1"
default n
config BSP_USING_CAN2
bool "using CAN2"
default n
endif
menuconfig BSP_USING_SDIO
bool "Enable SDIO"
default n
bsp/at32/at32f403a-start/board/board.h
+7
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@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2020-01-15 shelton first version
* 2021-02-09 shelton add flash macros
*/
#ifndef __BOARD_H__
@@ -18,6 +19,12 @@
extern "C" {
#endif
/* Just only support for AT32F40xxG */
#define AT32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define FLASH_PAGE_SIZE (2 * 1024)
#define AT32_FLASH_SIZE (1024 * 1024)
#define AT32_FLASH_END_ADDRESS ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <96>, Default: 96*/
#define AT32_SRAM_SIZE 96
#define AT32_SRAM_END (0x20000000 + AT32_SRAM_SIZE * 1024)
bsp/at32/at32f403a-start/board/msp/at32_msp.c
+43 -2
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@@ -2,8 +2,8 @@
******************************************************************************
* @file at32_msp.c
* @author Artery Technology
* @version V1.0.0
* @date 2020-01-10
* @version V1.0.1
* @date 2021-02-09
* @brief Msp source file
******************************************************************************
* @attention
@@ -256,3 +256,44 @@ void at32_msp_hwtmr_init(void *Instance)
#endif
}
#endif
#ifdef BSP_USING_CAN
void at32_msp_can_init(void *Instance)
{
GPIO_InitType GPIO_InitStruct;
CAN_Type *CANx = (CAN_Type *)Instance;
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
#ifdef BSP_USING_CAN1
if(CAN1 == CANx)
{
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_11;
GPIO_Init(GPIOA, &GPIO_InitStruct);
}
#endif
#ifdef BSP_USING_CAN2
if(CAN2 == CANx)
{
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOB, ENABLE);
GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_6;
GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_5;
GPIO_Init(GPIOB, &GPIO_InitStruct);
}
#endif
}
#endif /* BSP_USING_CAN */
bsp/at32/at32f403a-start/board/msp/at32_msp.h
+3 -2
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@@ -2,8 +2,8 @@
******************************************************************************
* @file at32_msp.h
* @author Artery Technology
* @version V1.0.0
* @date 2020-01-10
* @version V1.0.1
* @date 2021-02-09
* @brief Msp header file
******************************************************************************
* @attention
@@ -29,5 +29,6 @@ void at32_msp_i2c_init(void *Instance);
void at32_msp_sdio_init(void *Instance);
void at32_msp_adc_init(void *Instance);
void at32_msp_hwtmr_init(void *Instance);
void at32_msp_can_init(void *Instance);
#endif /* __AT32_MSP_H__ */
bsp/at32/at32f407-start/README.md
+6
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@@ -46,8 +46,10 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| PWM | 支持 | TMR1/2 |
| HWTIMER | 支持 | TMR3/4/5 |
| SDIO | 支持 | SDIO1 |
| CAN | 支持 | CAN1/2 |
| WDT | 支持 | |
| RTC | 支持 | |
| FLASH | 支持 | |
| ETH | 支持 | |
### IO在板级支持包中的映射情况
@@ -89,6 +91,10 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| PC3 | ADC1/2_IN13 |
| PC4 | ADC1/2_IN14 |
| PC5 | ADC1/2_IN15 |
| PA11 | CAN1_RX |
| PA12 | CAN1_TX |
| PB5 | CAN2_RX |
| PB6 | CAN2_TX |
| PB11 | ETH_RMII_TX_EN |
| PB12 | ETH_RMII_TX0 |
| PB13 | ETH_RMII_TX1 |
bsp/at32/at32f407-start/board/Kconfig
+17
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@@ -24,6 +24,10 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_ETH
bool "Enable Ethernet"
default n
@@ -157,6 +161,19 @@ menu "On-chip Peripheral Drivers"
default n
endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
if BSP_USING_CAN
config BSP_USING_CAN1
bool "using CAN1"
default n
config BSP_USING_CAN2
bool "using CAN2"
default n
endif
menuconfig BSP_USING_SDIO
bool "Enable SDIO"
default n
bsp/at32/at32f407-start/board/board.h
+7
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@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2020-01-15 shelton first version
* 2021-02-09 shelton add flash macros
*/
#ifndef __BOARD_H__
@@ -18,6 +19,12 @@
extern "C" {
#endif
/* Just only support for AT32F40xxG */
#define AT32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define FLASH_PAGE_SIZE (2 * 1024)
#define AT32_FLASH_SIZE (1024 * 1024)
#define AT32_FLASH_END_ADDRESS ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <96>, Default: 96*/
#define AT32_SRAM_SIZE 96
#define AT32_SRAM_END (0x20000000 + AT32_SRAM_SIZE * 1024)
bsp/at32/at32f407-start/board/msp/at32_msp.c
+43 -2
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@@ -2,8 +2,8 @@
******************************************************************************
* @file at32_msp.c
* @author Artery Technology
* @version V1.0.0
* @date 2020-01-10
* @version V1.0.1
* @date 2021-02-09
* @brief Msp source file
******************************************************************************
* @attention
@@ -256,3 +256,44 @@ void at32_msp_hwtmr_init(void *Instance)
#endif
}
#endif
#ifdef BSP_USING_CAN
void at32_msp_can_init(void *Instance)
{
GPIO_InitType GPIO_InitStruct;
CAN_Type *CANx = (CAN_Type *)Instance;
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
#ifdef BSP_USING_CAN1
if(CAN1 == CANx)
{
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_11;
GPIO_Init(GPIOA, &GPIO_InitStruct);
}
#endif
#ifdef BSP_USING_CAN2
if(CAN2 == CANx)
{
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOB, ENABLE);
GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_6;
GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_5;
GPIO_Init(GPIOB, &GPIO_InitStruct);
}
#endif
}
#endif /* BSP_USING_CAN */
bsp/at32/at32f407-start/board/msp/at32_msp.h
+3 -2
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@@ -2,8 +2,8 @@
******************************************************************************
* @file at32_msp.h
* @author Artery Technology
* @version V1.0.0
* @date 2020-01-10
* @version V1.0.1
* @date 2021-02-09
* @brief Msp header file
******************************************************************************
* @attention
@@ -29,5 +29,6 @@ void at32_msp_i2c_init(void *Instance);
void at32_msp_sdio_init(void *Instance);
void at32_msp_adc_init(void *Instance);
void at32_msp_hwtmr_init(void *Instance);
void at32_msp_can_init(void *Instance);
#endif /* __AT32_MSP_H__ */
bsp/ls1bdev/Kconfig
+18 -2
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@@ -16,7 +16,6 @@ config PKGS_DIR
default "packages"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/libcpu/mips/common/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_LS1B
@@ -25,16 +24,33 @@ config SOC_LS1B
select RT_USING_USER_MAIN
default y
config RT_MEM_SIZE
int "Memory Size (MByte)"
default 256
config RT_OSC_CLK
int "Oscillator Clock (Hz)"
default 25000000
if RT_USING_SERIAL
config RT_USING_UART0
bool "Using RT_USING_UART0"
default y
default n
config RT_USING_UART1
bool "Using RT_USING_UART1"
default n
config RT_USING_UART2
bool "Using RT_USING_UART2"
default n
config RT_USING_UART3
bool "Using RT_USING_UART3"
default n
config RT_USING_UART4
bool "Using RT_USING_UART4"
default n
config RT_USING_UART5
bool "Using RT_USING_UART5"
default y
config RT_UART_RX_BUFFER_SIZE
int "The rx buffer size"
bsp/ls1bdev/drivers/board.c
+2 -2
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@@ -19,7 +19,7 @@
#include <mips_fpu.h>
#include "board.h"
#include "uart.h"
#include "drv_uart.h"
#include "ls1b.h"
#ifdef RT_USING_RTGUI
@@ -84,6 +84,6 @@ void rt_hw_board_init(void)
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
rt_kprintf("current sr: 0x%08x\n", read_c0_status());
}
/*@}*/
bsp/ls1bdev/drivers/board.h
+1 -1
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@@ -19,7 +19,7 @@
void rt_hw_board_init(void);
/* 64M SDRAM */
#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
#define RT_HW_HEAP_END (0x80000000 + RT_MEM_SIZE * 1024 * 1024)
#define CPU_HZ (125 * 1000000)
#endif
bsp/ls1bdev/drivers/drv_uart.c
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bsp/ls1bdev/drivers/drv_uart.h
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@@ -0,0 +1,100 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-08 zhuangwei the first version
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include "ls1b.h"
#include <rthw.h>
#define DEV_CLK 252000000 // 252MHz
#define UART_BAUDRATE 115200
#define UART0_BASE 0xBFE40000
//#define UART0_1_BASE 0xBFE41000
#define UART1_BASE 0xBFE44000
#define UART2_BASE 0xBFE48000
#define UART3_BASE 0xBFE4C000
#define UART4_BASE 0xBFE4C400
#define UART5_BASE 0xBFE4C500
#define UART6_BASE 0xBFE4C600
#define UART7_BASE 0xBFE4C700
#define UART8_BASE 0xBFE4C800
#define UART9_BASE 0xBFE4C900
#define UART10_BASE 0xBFE4Ca00
#define UART11_BASE 0xBFE4Cb00
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT HWREG8(UART0_BASE + 0x00)
#define UART0_IER HWREG8(UART0_BASE + 0x01)
#define UART0_IIR HWREG8(UART0_BASE + 0x02)
#define UART0_FCR HWREG8(UART0_BASE + 0x02)
#define UART0_LCR HWREG8(UART0_BASE + 0x03)
#define UART0_MCR HWREG8(UART0_BASE + 0x04)
#define UART0_LSR HWREG8(UART0_BASE + 0x05)
#define UART0_MSR HWREG8(UART0_BASE + 0x06)
#define UART0_LSB HWREG8(UART0_BASE + 0x00)
#define UART0_MSB HWREG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT HWREG8(UART1_BASE + 0x00)
#define UART1_IER HWREG8(UART1_BASE + 0x01)
#define UART1_IIR HWREG8(UART1_BASE + 0x02)
#define UART1_FCR HWREG8(UART1_BASE + 0x02)
#define UART1_LCR HWREG8(UART1_BASE + 0x03)
#define UART1_MCR HWREG8(UART1_BASE + 0x04)
#define UART1_LSR HWREG8(UART1_BASE + 0x05)
#define UART1_MSR HWREG8(UART1_BASE + 0x06)
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_uart_init(void);
#endif
bsp/ls1bdev/drivers/uart.c
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bsp/ls1bdev/drivers/uart.h
-99
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@@ -1,99 +0,0 @@
/*
* File : uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version for LS1B
*/
#ifndef __UART_H__
#define __UART_H__
#include "ls1b.h"
#include <rthw.h>
#define UART0_BASE 0xBFE40000
#define UART0_1_BASE 0xBFE41000
#define UART0_2_BASE 0xBFE42000
#define UART0_3_BASE 0xBFE43000
#define UART1_BASE 0xBFE44000
#define UART1_1_BASE 0xBFE45000
#define UART1_2_BASE 0xBFE46000
#define UART1_3_BASE 0xBFE47000
#define UART2_BASE 0xBFE48000
#define UART3_BASE 0xBFE4C000
#define UART4_BASE 0xBFE6C000
#define UART5_BASE 0xBFE7C000
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT HWREG8(UART0_BASE + 0x00)
#define UART0_IER HWREG8(UART0_BASE + 0x01)
#define UART0_IIR HWREG8(UART0_BASE + 0x02)
#define UART0_FCR HWREG8(UART0_BASE + 0x02)
#define UART0_LCR HWREG8(UART0_BASE + 0x03)
#define UART0_MCR HWREG8(UART0_BASE + 0x04)
#define UART0_LSR HWREG8(UART0_BASE + 0x05)
#define UART0_MSR HWREG8(UART0_BASE + 0x06)
#define UART0_LSB HWREG8(UART0_BASE + 0x00)
#define UART0_MSB HWREG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT HWREG8(UART1_BASE + 0x00)
#define UART1_IER HWREG8(UART1_BASE + 0x01)
#define UART1_IIR HWREG8(UART1_BASE + 0x02)
#define UART1_FCR HWREG8(UART1_BASE + 0x02)
#define UART1_LCR HWREG8(UART1_BASE + 0x03)
#define UART1_MCR HWREG8(UART1_BASE + 0x04)
#define UART1_LSR HWREG8(UART1_BASE + 0x05)
#define UART1_MSR HWREG8(UART1_BASE + 0x06)
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_uart_init(void);
#endif
bsp/ls1bdev/libraries/SConscript
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/ls1bdev/libraries/ls1b_clock.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
#include "rtconfig.h"
#include "ls1b_regs.h"
#include "ls1b_public.h"
// 晶振的频率
#define AHB_CLK (RT_OSC_CLK)
#define APB_CLK (AHB_CLK)
#define DIV_DC_EN (0x1 << 31)
#define DIV_DC (0x1f << 26)
#define DIV_CPU_EN (0x1 << 25)
#define DIV_CPU (0x1f << 20)
#define DIV_DDR_EN (0x1 << 19)
#define DIV_DDR (0x1f << 14)
#define DIV_DC_SHIFT 26
#define DIV_CPU_SHIFT 20
#define DIV_DDR_SHIFT 14
/*
* 获取PLL频率
* @ret PLL频率
*/
unsigned long clk_get_pll_rate(void)
{
unsigned int ctrl;
unsigned long pll_rate = 0;
ctrl = reg_read_32((volatile unsigned int *)LS1B_START_FREQ);
pll_rate = (12 + (ctrl & 0x3f)) * APB_CLK / 2
+ ((ctrl >> 8) & 0x3ff) * APB_CLK / 1024 / 2;
return pll_rate;
}
/*
* 获取CPU频率
* @ret CPU频率
*/
unsigned long clk_get_cpu_rate(void)
{
unsigned long pll_rate, cpu_rate;
unsigned int ctrl;
pll_rate = clk_get_pll_rate();
ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT);
return cpu_rate;
}
/*
* 获取DDR频率
* @ret DDR频率
*/
unsigned long clk_get_ddr_rate(void)
{
unsigned long pll_rate, ddr_rate;
unsigned int ctrl;
pll_rate = clk_get_pll_rate();
ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
ddr_rate = pll_rate / ((ctrl & DIV_DDR) >> DIV_DDR_SHIFT);
return ddr_rate;
}
/*
* 获取APB频率
* @ret APB频率
*/
unsigned long clk_get_apb_rate(void)
{
return clk_get_ddr_rate() / 2;
}
/*
* 获取DC频率
* @ret DC频率
*/
unsigned long clk_get_dc_rate(void)
{
unsigned long pll_rate, dc_rate;
unsigned int ctrl;
pll_rate = clk_get_pll_rate();
ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
dc_rate = pll_rate ;
return dc_rate;
}
bsp/ls1bdev/libraries/ls1b_clock.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
#ifndef __LOONGSON_CLOCK_H
#define __LOONGSON_CLOCK_H
/*
* 获取PLL频率
* @ret PLL频率
*/
unsigned long clk_get_pll_rate(void);
/*
* 获取CPU频率
* @ret CPU频率
*/
unsigned long clk_get_cpu_rate(void);
/*
* 获取DDR频率
* @ret DDR频率
*/
unsigned long clk_get_ddr_rate(void);
/*
* 获取APB频率
* @ret APB频率
*/
unsigned long clk_get_apb_rate(void);
/*
* 获取DC频率
* @ret DC频率
*/
unsigned long clk_get_dc_rate(void);
#endif
bsp/ls1bdev/libraries/ls1b_gpio.c
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bsp/ls1bdev/libraries/ls1b_gpio.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
#ifndef __LOONGSON_GPIO_H
#define __LOONGSON_GPIO_H
// 龙芯1c的gpio是按照0,1,2,3,4...这样的顺序编号的，
// 但在操作寄存器的时候，又是按照每32个一组来分的
// 这里利用这个特性，将每组的32个gpio叫做一个"port"，每个gpio在每组中的索引叫"pin"
// port = gpio / 32
// pin = gpio % 32
// 例如GPIO50，port=1,pin=18
#define GPIO_GET_PORT(gpio) ((gpio) / 32)
#define GPIO_GET_PIN(gpio) ((gpio) % 32)
// gpio的工作模式--输入、输出
typedef enum{
gpio_mode_output = 0, // 输出
gpio_mode_input = 1 // 输入
}gpio_mode_t;
// gpio高低电平值
typedef enum{
gpio_level_low = 0, // 低电平
gpio_level_high = 1 // 高电平
}gpio_level_t;
typedef enum {
// 上升沿触发
IRQ_TYPE_EDGE_RISING = 0x00000001,
// 下降沿触发
IRQ_TYPE_EDGE_FALLING = 0x00000002,
IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
// 高电平触发
IRQ_TYPE_LEVEL_HIGH = 0x00000004,
// 低电平触发
IRQ_TYPE_LEVEL_LOW = 0x00000008,
IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
}gpio_irq_type_t;
/*
* 获取指定gpio的CFG寄存器
* @gpio gpio编号
* @ret CFG寄存器
*/
volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio);
/*
* gpio初始化
* @gpio gpio引脚，取值范围[0, 127]
* @mode gpio的工作模式(输入、输出)
*
* 例: 将gpio50初始化为输出
* gpio_init(50, gpio_mode_output);
*/
void gpio_init(unsigned int gpio, gpio_mode_t mode);
/*
* 在指定gpio输出高电平或低电平
* @gpio gpio引脚，取值范围[0, 127]
* @level 电平值
*
* 例: 在gpio50上输出低电平
* gpio_set(50, gpio_level_low);
*/
void gpio_set(unsigned int gpio, gpio_level_t level);
/*
* 读取指定gpio引脚的值
* @gpio gpio引脚，取值范围[0,127]
*
* 例: 读取gpio50引脚上的值
* gpio_level_t level;
* level = gpio_get(50);
*/
unsigned int gpio_get(unsigned int gpio);
/**
* 设置中断类型
* @gpio gpio引脚
* @type 触发中断的条件。高电平触发、低电平触发、上升沿触发 or 下降沿触发
*/
void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type);
#endif
bsp/ls1bdev/libraries/ls1b_pin.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 引脚功能(普通gpio，pwm，复用等)相关接口
#include "ls1b_public.h"
#include "ls1b_regs.h"
#include "ls1b_gpio.h"
#include "ls1b_pin.h"
/*
* 把指定pin设置为指定用途(普通gpio，非gpio)
* @gpio gpio引脚编号
* @purpose 用途
*/
void pin_set_purpose(unsigned int gpio, pin_purpose_t purpose)
{
volatile unsigned int *gpio_cfgx; // GPIO_CFGx寄存器
unsigned int pin = GPIO_GET_PIN(gpio);
gpio_cfgx = gpio_get_cfg_reg(gpio);
if (PIN_PURPOSE_GPIO == purpose) // 引脚用作普通gpio
{
reg_set_one_bit(gpio_cfgx, pin);
}
else // 引脚用作其它功能(非gpio)
{
reg_clr_one_bit(gpio_cfgx, pin);
}
return ;
}
/*
* 设置指定pin为第n复用
* @gpio gpio编号
* @remap 第n复用
*/
void pin_set_remap(unsigned int gpio, pin_remap_t remap)
{
volatile unsigned int *reg = NULL; // 复用寄存器
unsigned int port = GPIO_GET_PORT(gpio);
unsigned int pin = GPIO_GET_PIN(gpio);
int i;
/*指定全部pin复用为0*/
for (i = 0; i <= 4; i++)
{
reg = (volatile unsigned int *)((LS1B_CBUS_FIRST0) + ((port) * 0x04) + ((i) * 0x10));
// 置0
reg_clr_one_bit(reg, pin);
}
if (remap == PIN_REMAP_DEFAULT) return;
switch (port)
{
case 0:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST0;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND0;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD0;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH0;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH0;
break;
}
break;
case 1:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST1;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND1;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD1;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH1;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH1;
break;
}
break;
case 2:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST2;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND2;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD2;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH2;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH2;
break;
}
break;
case 3:
switch (remap)
{
case PIN_REMAP_FIRST:
reg = (volatile unsigned int *)LS1B_CBUS_FIRST3;
break;
case PIN_REMAP_SECOND:
reg = (volatile unsigned int *)LS1B_CBUS_SECOND3;
break;
case PIN_REMAP_THIRD:
reg = (volatile unsigned int *)LS1B_CBUS_THIRD3;
break;
case PIN_REMAP_FOURTH:
reg = (volatile unsigned int *)LS1B_CBUS_FOURTH3;
break;
case PIN_REMAP_FIFTH:
reg = (volatile unsigned int *)LS1B_CBUS_FIFTH3;
break;
}
break;
default:
return ;
}
// 置1
reg_set_one_bit(reg, pin);
return ;
}
bsp/ls1bdev/libraries/ls1b_pin.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
// 引脚功能(普通gpio，pwm，复用等)相关接口
#ifndef __LOONGSON_PIN_H
#define __LOONGSON_PIN_H
// 引脚用途
typedef enum
{
PIN_PURPOSE_GPIO = 0, // 引脚用作普通gpio
PIN_PURPOSE_OTHER, // 引脚用作其它功能(非gpio)
}pin_purpose_t;
// 引脚复用
typedef enum
{
PIN_REMAP_FIRST = 0, // 第一复用
PIN_REMAP_SECOND, // 第二复用
PIN_REMAP_THIRD, // 第三复用
PIN_REMAP_FOURTH, // 第四复用
PIN_REMAP_FIFTH, // 第五复用
PIN_REMAP_DEFAULT, //缺省复用
}pin_remap_t;
/*
* 把指定pin设置为指定用途(普通gpio，非gpio)
* @gpio gpio引脚编号
* @purpose 用途
*/
void pin_set_purpose(unsigned int gpio, pin_purpose_t purpose);
/*
* 设置指定pin为第n复用
* @gpio gpio编号
* @remap 第n复用
*/
void pin_set_remap(unsigned int gpio, pin_remap_t remap);
#endif
bsp/ls1bdev/libraries/ls1b_public.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 一些常用的、共用的接口
/*
* 将指定寄存器的指定位置1
* @reg 寄存器地址
* @bit 需要置1的那一bit
*/
void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit)
{
unsigned int temp, mask;
mask = 1 << bit;
temp = *reg;
temp |= mask;
*reg = temp;
return ;
}
/*
* 将指定寄存器的指定位清零
* @reg 寄存器地址
* @bit 需要清零的那一bit
*/
void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit)
{
unsigned int temp, mask;
mask = 1 << bit;
temp = *reg;
temp &= ~mask;
*reg = temp;
return ;
}
/*
* 获取指定寄存器的指定位的值
* @reg 寄存器地址
* @bit 需要读取值的那一bit
* @ret 指定位的值
*/
unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit)
{
unsigned int temp;
temp = *reg;
temp = (temp >> bit) & 1;
return temp;
}
/*
* 向寄存器中写入8bit(一个字节)数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_8(unsigned char data, volatile unsigned char *addr)
{
*addr = data;
}
/*
* 从寄存器读出8bit(一个字节)数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned char reg_read_8(volatile unsigned char *addr)
{
return (*addr);
}
/*
* 向寄存器中写一个32bit的数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_32(unsigned int data, volatile unsigned int *addr)
{
*addr = data;
}
/*
* 从寄存器读出一个32bit数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned int reg_read_32(volatile unsigned int *addr)
{
return (*addr);
}
/**
* ffs - find first bit set
* @x: the word to search
*
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
int ls1b_ffs(int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
/*
* fls - find last (most-significant) bit set
* @x: the word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
int ls1b_fls(int x)
{
int r = 32;
if (!x)
return 0;
if (!(x & 0xffff0000u))
{
x <<= 16;
r -= 16;
}
if (!(x & 0xff000000u))
{
x <<= 8;
r -= 8;
}
if (!(x & 0xf0000000u))
{
x <<= 4;
r -= 4;
}
if (!(x & 0xc0000000u))
{
x <<= 2;
r -= 2;
}
if (!(x & 0x80000000u))
{
x <<= 1;
r -= 1;
}
return r;
}
bsp/ls1bdev/libraries/ls1b_public.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
*/
// 一些常用的、共用的接口
#ifndef __LOONGSON_PUBLIC_H
#define __LOONGSON_PUBLIC_H
#include <stdio.h>
// pmon提供的打印函数，见main()函数
struct callvectors {
int (*open) (char *, int, int);
int (*close) (int);
int (*read) (int, void *, int);
int (*write) (int, void *, int);
long long (*lseek) (int, long long, int);
int (*printf) (const char *, ...);
void (*cacheflush) (void);
char *(*gets) (char *);
};
#define myprintf (*callvec->printf)
#define mygets (*callvec->gets)
extern struct callvectors *callvec;
#define MIN(a, b) ((a) > (b) ? (b) : (a))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
typedef enum
{
FALSE=0,
TRUE=1
}BOOL;
/*
* 将指定寄存器的指定位置1
* @reg 寄存器地址
* @bit 需要置1的那一bit
*/
void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit);
/*
* 将指定寄存器的指定位清零
* @reg 寄存器地址
* @bit 需要清零的那一bit
*/
void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit);
/*
* 获取指定寄存器的指定位的值
* @reg 寄存器地址
* @bit 需要读取值的那一bit
* @ret 指定位的值
*/
unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit);
/*
* 向寄存器中写入8bit(一个字节)数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_8(unsigned char data, volatile unsigned char *addr);
/*
* 从寄存器读出8bit(一个字节)数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned char reg_read_8(volatile unsigned char *addr);
/*
* 向寄存器中写一个32bit的数据
* @data 待写入的数据
* @addr 寄存器地址
*/
void reg_write_32(unsigned int data, volatile unsigned int *addr);
/*
* 从寄存器读出一个32bit数据
* @addr 寄存器地址
* @ret 读出的数据
*/
unsigned int reg_read_32(volatile unsigned int *addr);
/**
* ffs - find first bit set
* @x: the word to search
*/
int ls1b_ffs(int x);
/*
* fls - find last (most-significant) bit set
* @x: the word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
int ls1b_fls(int x);
#endif
bsp/ls1bdev/libraries/ls1b_regs.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-09-06 勤为本 first version
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 龙芯1b外设寄存器
#ifndef __LOONGSON_LS1B_REGS_H
#define __LOONGSON_LS1B_REGS_H
// 时钟相关寄存器地址
#define LS1B_START_FREQ (0xbfe78030)
#define LS1B_CLK_DIV_PARAM (0xbfe78034)
// gpio相关寄存器地址
#define LS1B_GPIO_CFG0 (0xbfd010c0)
#define LS1B_GPIO_EN0 (0xbfd010d0)
#define LS1B_GPIO_IN0 (0xbfd010e0)
#define LS1B_GPIO_OUT0 (0xbfd010f0)
#define LS1B_GPIO_CFG1 (0xbfd010c4)
#define LS1B_GPIO_EN1 (0xbfd010d4)
#define LS1B_GPIO_IN1 (0xbfd010e4)
#define LS1B_GPIO_OUT1 (0xbfd010f4)
// 复用相关寄存器
#define LS1B_CBUS_FIRST0 (0xbfd011c0)
#define LS1B_CBUS_SECOND0 (0xbfd011d0)
#define LS1B_CBUS_THIRD0 (0xbfd011e0)
#define LS1B_CBUS_FOURTH0 (0xbfd011f0)
#define LS1B_CBUS_FIFTH0 (0xbfd01200)
#define LS1B_CBUS_FIRST1 (0xbfd011c4)
#define LS1B_CBUS_SECOND1 (0xbfd011d4)
#define LS1B_CBUS_THIRD1 (0xbfd011e4)
#define LS1B_CBUS_FOURTH1 (0xbfd011f4)
#define LS1B_CBUS_FIFTH1 (0xbfd01204)
#define LS1B_CBUS_FIRST2 (0xbfd011c8)
#define LS1B_CBUS_SECOND2 (0xbfd011d8)
#define LS1B_CBUS_THIRD2 (0xbfd011e8)
#define LS1B_CBUS_FOURTH2 (0xbfd011f8)
#define LS1B_CBUS_FIFTH2 (0xbfd01208)
#define LS1B_CBUS_FIRST3 (0xbfd011cc)
#define LS1B_CBUS_SECOND3 (0xbfd011dc)
#define LS1B_CBUS_THIRD3 (0xbfd011ec)
#define LS1B_CBUS_FOURTH3 (0xbfd011fc)
#define LS1B_CBUS_FIFTH3 (0xbfd0120c)
// PWM寄存器偏移
#define LS1B_PWM_CNTR (0x0)
#define LS1B_PWM_HRC (0x4)
#define LS1B_PWM_LRC (0x8)
#define LS1B_PWM_CTRL (0xC)
// PWM基地址
#define LS1B_REG_BASE_PWM0 (0xbfe5c000)
#define LS1B_REG_BASE_PWM1 (0xbfe5c010)
#define LS1B_REG_BASE_PWM2 (0xbfe5c020)
#define LS1B_REG_BASE_PWM3 (0xbfe5c030)
//CAN基地址
#define LS1B_REG_BASE_CAN0 (0xbfe50000)
#define LS1B_REG_BASE_CAN1 (0xbfe54000)
// 中断配置寄存器
#define LS1B_INT0_SR (0xbfd01040)
#define LS1B_INT0_EN (0xbfd01044)
#define LS1B_INT0_SET (0xbfd01048)
#define LS1B_INT0_CLR (0xbfd0104c)
#define LS1B_INT0_POL (0xbfd01050)
#define LS1B_INT0_EDGE (0xbfd01054)
#define LS1B_INT1_SR (0xbfd01058)
#define LS1B_INT1_EN (0xbfd0105c)
#define LS1B_INT1_SET (0xbfd01060)
#define LS1B_INT1_CLR (0xbfd01064)
#define LS1B_INT1_POL (0xbfd01068)
#define LS1B_INT1_EDGE (0xbfd0106c)
#define LS1B_INT2_SR (0xbfd01070)
#define LS1B_INT2_EN (0xbfd01074)
#define LS1B_INT2_SET (0xbfd01078)
#define LS1B_INT2_CLR (0xbfd0107c)
#define LS1B_INT2_POL (0xbfd01080)
#define LS1B_INT2_EDGE (0xbfd01084)
#define LS1B_INT3_SR (0xbfd01088)
#define LS1B_INT3_EN (0xbfd0108c)
#define LS1B_INT3_SET (0xbfd01090)
#define LS1B_INT3_CLR (0xbfd01094)
#define LS1B_INT3_POL (0xbfd01098)
#define LS1B_INT3_EDGE (0xbfd0109c)
#define LS1B_INT4_SR (0xbfd010a0)
#define LS1B_INT4_EN (0xbfd010a4)
#define LS1B_INT4_SET (0xbfd010a8)
#define LS1B_INT4_CLR (0xbfd010ac)
#define LS1B_INT4_POL (0xbfd010b0)
#define LS1B_INT4_EDGE (0xbfd010b4)
// I2C寄存器
#define LS1B_I2C0_BASE (0xbfe58000)
#define LS1B_I2C1_BASE (0xbfe68000)
#define LS1B_I2C2_BASE (0xbfe70000)
// SPI寄存器
#define LS1B_SPI0_BASE (0xbfe80000)
#define LS1B_SPI1_BASE (0xbfec0000)
// 串口寄存器
#define LS1B_UART00_BASE (0xbfe40000)
#define LS1B_UART01_BASE (0xbfe41000)
#define LS1B_UART1_BASE (0xbfe44000)
#define LS1B_UART2_BASE (0xbfe48000)
#define LS1B_UART3_BASE (0xbfe4c000)
#define LS1B_UART4_BASE (0xbfe6c000)
#define LS1B_UART5_BASE (0xbfe7c000)
#define LS1B_UART6_BASE (0xbfe41000)
#define LS1B_UART7_BASE (0xbfe42000)
#define LS1B_UART8_BASE (0xbfe43000)
#define LS1B_UART9_BASE (0xbfe45000)
#define LS1B_UART10_BASE (0xbfe46000)
#define LS1B_UART11_BASE (0xbfe47000)
//RTC寄存器
#define LS1B_RTC_BASE (0xbfe64024)
#endif
bsp/ls1bdev/libraries/ls1b_uart.c
+251
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bsp/ls1bdev/libraries/ls1b_uart.h
+181
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@@ -0,0 +1,181 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
*/
// 串口相关头文件
#ifndef __LOONGSON_UART_H
#define __LOONGSON_UART_H
#include "ls1b_public.h"
// 串口各寄存器相对基地址的偏移
#define LS1B_UART_DAT_OFFSET (0)
#define LS1B_UART_IER_OFFSET (1)
#define LS1B_UART_IIR_OFFSET (2)
#define LS1B_UART_FCR_OFFSET (2)
#define LS1B_UART_LCR_OFFSET (3)
#define LS1B_UART_MCR_OFFSET (4)
#define LS1B_UART_LSR_OFFSET (5)
#define LS1B_UART_MSR_OFFSET (6)
#define LS1B_UART_LSB_OFFSET (0) // 分频锁存器1
#define LS1B_UART_MSB_OFFSET (1) // 分频锁存器2
/* interrupt enable register */
#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
#define IER_IME 0x8 /* Modem状态中断使能 */
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
// 线路控制寄存器
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
// 串口模块编号
typedef enum
{
LS1B_UART00 = 0, // 全功能串口UART0可以分为两个四线串口UART00和UART01
LS1B_UART01,
LS1B_UART1,
LS1B_UART2,
LS1B_UART3,
LS1B_UART4,
LS1B_UART5,
LS1B_UART6,
LS1B_UART7,
LS1B_UART8,
LS1B_UART9,
LS1B_UART10,
LS1B_UART11
}ls1b_uart_t;
// 串口信息
typedef struct
{
ls1b_uart_t UARTx; // 串口模块编号
unsigned int baudrate; // 波特率
BOOL rx_enable; // 是否需要使用串口接收数据(使能接收中断)，发送默认使能
}ls1b_uart_info_t;
/*
* 获取指定串口模块的基地址
* @UARTx 串口编号
* @ret 基地址
*/
void *uart_get_base(ls1b_uart_t UARTx);
/*
* 初始化指定的串口模块
* @uart_info_p 串口模块信息
*/
void uart_init(ls1b_uart_info_t *uart_info_p);
/*
* 初始化串口2
*/
void uart2_init(void);
/*
* 在串口2上打印字符串
* @str 待打印的字符串
*/
void uart2_print(const char *str);
/*
* 在调试串口打印字符串
* @str 待打印的字符串
*/
void uart_debug_print(const char *str);
/*
* 在调试串口打印一个字符
* @ch 待打印的字符
*/
void uart_debug_putc(unsigned char ch);
/*
* 发送一个字节
* @uartx 串口号
* @ch 待发送的字符串
*/
void uart_putc(ls1b_uart_t uartx, unsigned char ch);
/*
* 打印一个字符串到指定串口
* @uartx 串口号
* @str 待打印的字符串
*/
void uart_print(ls1b_uart_t uartx, const char *str);
#endif
bsp/ls1bdev/rtconfig.h
+7 -11
View File
@@ -10,15 +10,12 @@
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_DEBUG
/* Inter-Thread communication */
@@ -40,8 +37,8 @@
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40002
#define RT_CONSOLE_DEVICE_NAME "uart5"
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
@@ -114,9 +111,6 @@
/* Utilities */
/* RT-Thread MIPS CPU */
/* RT-Thread online packages */
/* IoT - internet of things */
@@ -157,7 +151,9 @@
/* samples: kernel and components samples */
#define SOC_LS1B
#define RT_USING_UART0
#define RT_MEM_SIZE 256
#define RT_OSC_CLK 25000000
#define RT_USING_UART5
#define RT_UART_RX_BUFFER_SIZE 64
#endif
bsp/ls1bdev/rtconfig.py
+1 -1
View File
@@ -36,7 +36,7 @@ OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -mips32r2'
DEVICE = ' -mips32 -msoft-float -mfp32'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'
bsp/maxim/MAX32660_EVSYS/.config
+3 -2
View File
@@ -122,7 +122,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_PIN is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
@@ -478,9 +478,10 @@ CONFIG_SOC_MAXIM=y
#
# On-chip Peripheral Drivers
#
# CONFIG_BSP_USING_GPIO is not set
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART0 is not set
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
bsp/maxim/MAX32660_EVSYS/README.md
+2 -2
View File
@@ -72,10 +72,10 @@ MAX32660-EVSYS开发板常用 **板载资源** 如下：
| **片上外设** | **支持情况** | **备注** |
| :----------- | :----------: | :-------------------: |
| GPIO | | |
| GPIO | 支持 | |
| UART | 支持 | UART0, UART1(console) |
| PWM | | |
| SPI | | |
| SPI | 支持 | SPI0, SPI1 |
| RTC | | |
| I2S | | |
| I2C | | |
bsp/maxim/MAX32660_EVSYS/applications/application.c
+6 -8
View File
@@ -11,22 +11,20 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "gpio.h"
const gpio_cfg_t led_pin[] =
{
{PORT_0, PIN_13, GPIO_FUNC_OUT, GPIO_PAD_NONE},
};
#define GPIO_LED_PIN 13
int main(void)
{
int count = 1;
GPIO_Config(&led_pin[0]);
GPIO_OutSet(&led_pin[0]);
rt_pin_mode(GPIO_LED_PIN, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(GPIO_LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(GPIO_LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
GPIO_OutToggle(&led_pin[0]);
}
return RT_EOK;
}
bsp/maxim/MAX32660_EVSYS/board/Kconfig
+19
View File
@@ -43,6 +43,25 @@ menu "On-chip Peripheral Drivers"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_SPI
bool "Enable SPI"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 bus [MISO P0.4;MOSI P0.5;SCL P0.6;SS P0.7]"
default y
config BSP_USING_SPI1
bool "Enable SPI1 bus [MISO P0.0;MOSI P0.1;SCL P0.2;SS P0.3]"
default n
if BSP_USING_SPI1
config BSP_USING_SPI1A
bool "Use SPI1A. [MISO P0.10;MOSI P0.11;SCL P0.12;SS P0.13]"
default n
endif
endif
config BSP_USING_ON_CHIP_FLASH
select PKG_USING_FAL
bool "Enable on-chip FLASH"
bsp/maxim/MAX32660_EVSYS/board/board.h
+4
View File
@@ -14,6 +14,10 @@
#include <rtthread.h>
#include <rthw.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#define MCU_FLASH_START_ADRESS ((uint32_t)0x0)
#define MCU_FLASH_SIZE_KB (256)
#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADRESS + MCU_FLASH_SIZE*1024))
bsp/maxim/MAX32660_EVSYS/project.uvoptx
+89 -45
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File diff suppressed because it is too large. Load diff
bsp/maxim/MAX32660_EVSYS/project.uvprojx
+11 -1
View File
@@ -338,7 +338,7 @@
<MiscControls></MiscControls>
<Define>TARGET=32660, TARGET_REV=0x4131, __RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Include;..\libraries\MAX32660PeriphDriver\CMSIS\Core\Include;..\libraries\MAX32660PeriphDriver\Include</IncludePath>
<IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Include;..\libraries\MAX32660PeriphDriver\CMSIS\Core\Include;..\libraries\MAX32660PeriphDriver\Include</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -422,6 +422,11 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
@@ -477,6 +482,11 @@
<FileType>2</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\ARM\startup_max32660.s</FilePath>
</File>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_uart.c</FileName>
<FileType>1</FileType>
bsp/maxim/MAX32660_EVSYS/rtconfig.h
+2
View File
@@ -79,6 +79,7 @@
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
@@ -159,6 +160,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
bsp/maxim/libraries/HAL_Drivers/drv_gpio.c
+208
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File diff suppressed because it is too large. Load diff
bsp/maxim/libraries/HAL_Drivers/drv_gpio.h
+21
View File
@@ -0,0 +1,21 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-11 supperthomas first version
*
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <board.h>
#include <rtdevice.h>
int rt_hw_pin_init(void);
#endif /* __DRV_GPIO_H__ */
bsp/maxim/libraries/HAL_Drivers/drv_spi.c
+169
View File
@@ -0,0 +1,169 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-14 supperthomas first version
*/
#include <stdint.h>
#include <string.h>
#include "board.h"
#include "drv_spi.h"
#define DBG_LEVEL DBG_LOG
#include <rtdbg.h>
#define LOG_TAG "drv.spi"
#ifdef BSP_USING_SPI
#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2)
static struct mcu_drv_spi_config spi_config[] =
{
#ifdef BSP_USING_SPI0
MCU_SPI0_CONFIG,
#endif
#ifdef BSP_USING_SPI1
MCU_SPI1_CONFIG,
#endif
};
static struct mcu_drv_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
/**
* @brief This function config spi bus
* @param device
* @param configuration
* @retval RT_EOK / RT_ERROR
*/
static rt_err_t spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct mcu_drv_spi *tmp_spi;
tmp_spi = rt_container_of(device->bus, struct mcu_drv_spi, spi_bus);
int mode;
///init
switch (configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0/* RT_SPI_CPOL:0 , RT_SPI_CPHA:0 */:
case RT_SPI_MODE_1/* RT_SPI_CPOL:0 , RT_SPI_CPHA:1 */:
case RT_SPI_MODE_2/* RT_SPI_CPOL:1 , RT_SPI_CPHA:0 */:
case RT_SPI_MODE_3/* RT_SPI_CPOL:1 , RT_SPI_CPHA:1 */:
mode = configuration->mode & RT_SPI_MODE_3;
break;
default:
LOG_E("spi_configure mode error %x\n", configuration->mode);
return RT_ERROR;
}
tmp_spi->spixfer_req.width = SPI17Y_WIDTH_1;
tmp_spi->spixfer_req.bits = configuration->data_width;
tmp_spi->spixfer_req.ssel = 0;
tmp_spi->spixfer_req.deass = 1;
tmp_spi->spixfer_req.tx_num = 0;
tmp_spi->spixfer_req.rx_num = 0;
tmp_spi->spixfer_req.callback = NULL;
LOG_D("spi init mode:%d, rate:%d", mode, configuration->max_hz);
if (SPI_Init(tmp_spi->spi_instance, mode, configuration->max_hz) != 0)
{
LOG_E("Error configuring SPI\n");
while (1) {}
}
//init
return RT_EOK;
}
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
int ret = 0;
struct mcu_drv_spi *tmp_spi;
tmp_spi = rt_container_of(device->bus, struct mcu_drv_spi, spi_bus);
tmp_spi->spixfer_req.tx_data = message->send_buf;
tmp_spi->spixfer_req.rx_data = message->recv_buf;
tmp_spi->spixfer_req.len = message->length;
ret = SPI_MasterTrans(tmp_spi->spi_instance, &tmp_spi->spixfer_req);
if (ret == E_NO_ERROR)
{
return message->length;
}
else
{
LOG_E("spixfer faild, ret %d", ret);
return 0;
}
}
/* spi bus callback function */
static const struct rt_spi_ops nrfx_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer,
};
/*spi bus init*/
static int rt_hw_spi_bus_init(void)
{
rt_err_t result = RT_ERROR;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].spi_instance = spi_config[i].spi_instance;
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; //SPI INSTANCE
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &nrfx_spi_ops);
RT_ASSERT(result == RT_EOK);
}
return result;
}
int rt_hw_spi_init(void)
{
return rt_hw_spi_bus_init();
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t cs_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
RT_ASSERT(cs_pin != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
/* initialize the cs pin */
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d", device_name, bus_name, result);
result = RT_ERROR;
}
/* TODO: SET THE GPIO */
RT_ASSERT(result == RT_EOK);
return result;
}
#endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 */
#endif /*BSP_USING_SPI*/
bsp/maxim/libraries/HAL_Drivers/drv_spi.h
+67
View File
@@ -0,0 +1,67 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-14 supperthomas first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "spi.h"
#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
/**
* @brief Attach the spi device to SPI bus, this function must be used after initialization.
* @param bus_name spi bus name "spi0"/"spi1"/"spi2"
* @param device_name spi device name "spi0x"/"spi1x"/"spi2x"
* @param ss_pin spi ss pin number
* @retval RT_ERROR / RT_EOK
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t ss_pin);
//SPI bus config
#ifdef BSP_USING_SPI0
#define MCU_SPI0_CONFIG \
{ \
.bus_name = "spi0", \
.spi_instance = SPI0A, \
}
#endif
#ifdef BSP_USING_SPI1
#ifdef BSP_USING_SPI1A //The SPI1A is conflit with UART1 TX RX P0.10 P0.11
#define MCU_SPI1_CONFIG \
{ \
.bus_name = "spi1", \
.spi_instance = SPI1A \
}
#else
#define MCU_SPI1_CONFIG \
{ \
.bus_name = "spi1", \
.spi_instance = SPI1B \
}
#endif
#endif
struct mcu_drv_spi_config
{
char *bus_name;
spi_type spi_instance;
};
struct mcu_drv_spi
{
spi_type spi_instance;
spi_req_t spixfer_req;
struct rt_spi_configuration *cfg;
struct rt_spi_bus spi_bus;
};
#endif /*__DRV_SPI_H_*/
bsp/maxim/libraries/MAX32660PeriphDriver/SConscript
+3
View File
@@ -30,6 +30,9 @@ if GetDepend(['RT_USING_I2C']):
if GetDepend(['RT_USING_SPI']):
src += ['Source/spi.c']
src += ['Source/spi17y.c']
src += ['Source/spimss.c']
if GetDepend(['RT_USING_RTC']):
src += ['Source/rtc.c']
bsp/nrf5x/README.md
+51 -1
View File
@@ -132,4 +132,54 @@ nrf5x
下面提供一种擦写softdevice的方法。在keil中选择softdevice Erase的FLASH算法，这个时候就烧写之前可以擦除之前的softdevice。
![image-20201017194935643](docs/images/softdevice_erase.png)
![image-20201017194935643](docs/images/softdevice_erase.png)
### 2.如果在使用softdevice的时候，连上手机时候出现一些hardfault
如下所示：
```
psr: 0x8100000f
r00: 0x00000000
r01: 0x200034e6
r02: 0x00000000
r03: 0x200034dc
r04: 0x200034dc
r05: 0x00000000
r06: 0x200034e6
r07: 0xdeadbeef
r08: 0xdeadbeef
r09: 0xdeadbeef
r10: 0xdeadbeef
r11: 0xdeadbeef
r12: 0x00000000
lr: 0x000369af
pc: 0x00036972
hard fault on handler
```
这个hardfault发生在SOFTDEVICE内部，由于代码不开源，这边尝试了修改如下函数，可以不触发hardfault。
```
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
;MRS r0, PRIMASK
;CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
;MSR PRIMASK, r0
BX LR
ENDP
```
bsp/nrf5x/nrf52832/board/board.h
+1 -2
View File
@@ -21,8 +21,7 @@ extern int __bss_end__;
#define HEAP_BEGIN ((void *)&__bss_end__)
#endif
#define HEAP_SIZE 16*1024
#define HEAP_END (HEAP_BEGIN + HEAP_SIZE)
#define HEAP_END (MCU_SRAM_END_ADDRESS)
void rt_hw_board_init(void);
bsp/nrf5x/nrf52840/board/Kconfig
+2 -2
View File
@@ -314,8 +314,8 @@ menu "On-chip Peripheral Drivers"
endif
config BSP_USING_SPI
bool "Enable SPI"
select RT_USING_PIN
default y
select RT_USING_SPI
default n
if BSP_USING_SPI
config NRFX_SPI_ENABLED
bsp/nrf5x/nrf52840/board/board.c
-3
View File
@@ -53,9 +53,6 @@ void SysTick_Configuration(void)
void rt_hw_board_init(void)
{
rt_hw_interrupt_enable(0);
// sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
/* Activate deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
SysTick_Configuration();
bsp/nrf5x/nrf52840/board/board.h
+2 -2
View File
@@ -21,8 +21,8 @@ extern int __bss_end__;
#define HEAP_BEGIN ((void *)&__bss_end__)
#endif
#define HEAP_SIZE 16*1024
#define HEAP_END (HEAP_BEGIN + HEAP_SIZE)
#define HEAP_END (MCU_SRAM_END_ADDRESS)
void rt_hw_board_init(void);
components/libc/compilers/armlibc/syscalls.c
+5 -19
View File
@@ -258,23 +258,9 @@ void _ttywrch(int ch)
RT_WEAK void _sys_exit(int return_code)
{
rt_thread_t self = rt_thread_self();
#ifdef RT_USING_MODULE
if (dlmodule_self())
{
dlmodule_exit(return_code);
}
#endif
if (self != RT_NULL)
{
rt_kprintf("thread:%-8.*s exit:%d!\n", RT_NAME_MAX, self->name, return_code);
rt_thread_suspend(self);
rt_schedule();
}
while(1); /* noreturn */
extern void __rt_libc_exit(int status);
__rt_libc_exit(return_code);
while(1);
}
/**
@@ -320,8 +306,8 @@ int remove(const char *filename)
#else
int system(const char *string)
{
RT_ASSERT(0);
for (;;);
extern int __rt_libc_system(const char *string);
return __rt_libc_system(string);
}
#endif
components/libc/compilers/common/SConscript
+4 -4
View File
@@ -8,13 +8,13 @@ group = []
CPPPATH = [cwd]
if GetDepend('RT_USING_LIBC'):
src += Glob('*.c')
src += Glob('*.c')
else:
if GetDepend('RT_LIBC_USING_TIME') and not GetDepend('RT_USING_MINILIBC'):
src += ['time.c']
if GetDepend('RT_LIBC_USING_TIME') and not GetDepend('RT_USING_MINILIBC'):
src += ['time.c']
if GetDepend('RT_USING_POSIX') == False:
SrcRemove(src, ['unistd.c'])
SrcRemove(src, ['unistd.c'])
if rtconfig.CROSS_TOOL == 'keil':
CPPDEFINES = ['__CLK_TCK=RT_TICK_PER_SECOND']
components/libc/compilers/common/stdlib.c
+49
View File
@@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-15 Meco Man first version
*/
#include <rtthread.h>
#include <stdlib.h>
void __rt_libc_exit(int status)
{
rt_thread_t self = rt_thread_self();
#ifdef RT_USING_MODULE
if (dlmodule_self())
{
dlmodule_exit(status);
}
#endif
if (self != RT_NULL)
{
if(status == EXIT_FAILURE) /* abort() */
{
rt_kprintf("thread:%s abort!\n", self->name);
}
else /* exit() */
{
rt_kprintf("thread:%s exit:%d!\n", self->name, status);
}
rt_thread_suspend(self);
rt_schedule();
}
}
void __rt_libc_abort(void)
{
__rt_libc_exit(EXIT_FAILURE);
}
int __rt_libc_system(const char *string)
{
/* TODO */
return 0;
}
components/libc/compilers/dlib/syscalls.c
+6 -34
View File
@@ -11,42 +11,14 @@
void exit (int status)
{
rt_thread_t self = rt_thread_self();
#ifdef RT_USING_MODULE
if (dlmodule_self())
{
dlmodule_exit(status);
}
#endif
if (self != RT_NULL)
{
rt_kprintf("thread:%-8.*s exit:%d!\n", RT_NAME_MAX, self->name, status);
rt_thread_suspend(self);
rt_schedule();
}
while(1); /* noreturn */
extern void __rt_libc_exit(int status);
__rt_libc_exit(status);
while(1);
}
void abort(void)
{
rt_thread_t self = rt_thread_self();
#ifdef RT_USING_MODULE
if (dlmodule_self())
{
dlmodule_exit(-1);
}
#endif
if (self != RT_NULL)
{
rt_kprintf("thread:%-8.*s abort!\n", RT_NAME_MAX, self->name);
rt_thread_suspend(self);
rt_schedule();
}
while(1); /* noreturn */
extern void __rt_libc_abort(void);
__rt_libc_abort();
while(1);
}
components/libc/compilers/newlib/machine/time.h
+12
View File
@@ -0,0 +1,12 @@
#ifndef _MACHTIME_H_
#define _MACHTIME_H_
#include <rtconfig.h>
#define _CLOCKS_PER_SEC_ RT_TICK_PER_SECOND
#ifdef __SPU__
#include <sys/_timespec.h>
int nanosleep (const struct timespec *, struct timespec *);
#endif
#endif /* _MACHTIME_H_ */
components/libc/compilers/newlib/syscalls.c
+8 -36
View File
@@ -286,30 +286,16 @@ _free_r (struct _reent *ptr, void *addr)
void
exit (int status)
{
rt_thread_t self = rt_thread_self();
#ifdef RT_USING_MODULE
if (dlmodule_self())
{
dlmodule_exit(status);
}
#endif
if (self != RT_NULL)
{
rt_kprintf("thread:%-8.*s exit:%d!\n", RT_NAME_MAX, self->name, status);
rt_thread_suspend(self);
rt_schedule();
}
while(1); /* noreturn */
extern void __rt_libc_exit(int status);
__rt_libc_exit(status);
while(1);
}
void
_system(const char *s)
{
/* not support this call */
return;
extern int __rt_libc_system(const char *string);
__rt_libc_system(s);
}
void __libc_init_array(void)
@@ -319,23 +305,9 @@ void __libc_init_array(void)
void abort(void)
{
rt_thread_t self = rt_thread_self();
#ifdef RT_USING_MODULE
if (dlmodule_self())
{
dlmodule_exit(-1);
}
#endif
if (self != RT_NULL)
{
rt_kprintf("thread:%-8.*s abort!\n", RT_NAME_MAX, self->name);
rt_thread_suspend(self);
rt_schedule();
}
while(1); /* noreturn */
extern void __rt_libc_abort(void);
__rt_libc_abort();
while(1);
}
uid_t getuid(void)