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BernardXiong committed 2015-05-18 18:16:59 +08:00
2 parents 8de629c0b0 0d1ee90f28
commit 7d73fb8bdb
59 files changed
+19088 -5261
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bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h
+90 -21
View File
@@ -1,12 +1,12 @@
/****************************************************************************************************//**
* @file CMEM7.h
* @file cmem7.h
*
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
* CMEM7 from <unknown Vendor>.
* cmem7 from <unknown Vendor>.
*
* @version V1.0
* @date 5. June 2014
* @date 5. January 2015
*
* @note Generated with SVDConv V2.75
* from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0,
@@ -18,7 +18,7 @@
* @{
*/
/** @addtogroup CMEM7
/** @addtogroup cmem7
* @{
*/
@@ -46,7 +46,7 @@ typedef enum {
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* ---------------------- CMEM7 Specific Interrupt Numbers ---------------------- */
/* ---------------------- cmem7 Specific Interrupt Numbers ---------------------- */
ETH_INT_IRQn = 0, /*!< 0 ETH_INT */
USB_INT_IRQn = 1, /*!< 1 USB_INT */
DMA_INT_IRQn = 2, /*!< 2 DMA_INT */
@@ -105,7 +105,7 @@ typedef enum {
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
#include "system_cmem7.h" /*!< CMEM7 System */
#include "system_cmem7.h" /*!< cmem7 System */
/* ================================================================================ */
@@ -789,17 +789,17 @@ typedef struct { /*!< RTC Structure
struct {
__IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */
__IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt, write 1 clear 0 */
__IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt, write 1 clear 0 */
} INT_STATUS_b; /*!< BitSize */
};
__IO uint32_t SECOND; /*!< current seconds of system time */
union {
__IO uint16_t MICROSECOND; /*!< current micro seconds of system time */
__IO uint16_t MILLSECOND; /*!< current millseconds of system time */
struct {
__IO uint16_t MS : 10; /*!< micro seconds */
} MICROSECOND_b; /*!< BitSize */
} MILLSECOND_b; /*!< BitSize */
};
} RTC_Type;
@@ -2884,9 +2884,35 @@ typedef struct { /*!< ETH Structure
are used to index the content */
} VLAN_TAG_b; /*!< BitSize */
};
__I uint32_t RESERVED0[8];
__I uint32_t RESERVED0[2];
__IO uint32_t RWUFFR; /*!< Remote Wake-Up Frame Filter Register */
union {
__IO uint32_t PMTCSR; /*!< PMT Control and Status Register */
struct {
__IO uint32_t PWRDWN : 1; /*!< Power Down */
__IO uint32_t MGKPKTEN : 1; /*!< Magic Packet Enable */
__IO uint32_t RWKPKTEN : 1; /*!< Remote Wake-Up Frame Enable */
uint32_t : 2;
__IO uint32_t MGKPRCVD : 1; /*!< the power management event is generated because of the reception
of a magic packet */
__IO uint32_t RWKPRCVD : 1; /*!< When set, this bit indicates the power management event is generated
because of the reception of a remote wake-up frame */
uint32_t : 2;
__IO uint32_t GLBLUCAST : 1; /*!< When set, enables any unicast packet filtered by the MAC (DAF)address
recognition to be a remote wake-up frame. */
uint32_t : 14;
__IO uint32_t RWKPTR : 3; /*!< Remote Wake-up FIFO Pointer */
uint32_t : 4;
__IO uint32_t RWKFILTRST : 1; /*!< Remote Wake-Up Frame Filter Register Pointer Reset. */
} PMTCSR_b; /*!< BitSize */
};
__I uint32_t RESERVED1[2];
__IO uint32_t MACISR; /*!< Interrupt Status Register */
__IO uint32_t MACIMR; /*!< Interrupt Mask Register */
__IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */
__I uint16_t RESERVED1;
__I uint16_t RESERVED2;
__IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */
union {
@@ -2901,10 +2927,51 @@ typedef struct { /*!< ETH Structure
} ADDR1_HIGH_b; /*!< BitSize */
};
__IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */
__I uint32_t RESERVED2[47];
__IO uint32_t MMC_RX_MASK; /*!< MMC Receive interrupt mask */
__IO uint32_t MMC_TX_MASK; /*!< MMC Transmit Interrupt Mask */
__I uint32_t RESERVED3[955];
__I uint32_t RESERVED3[44];
union {
__IO uint32_t MMCCR; /*!< MMC Control Register */
struct {
__IO uint32_t CNTRST : 1; /*!< Counters Reset */
__IO uint32_t CNTSTOPRO : 1; /*!< Counter Stop Rollover */
__IO uint32_t RSTONRD : 1; /*!< Reset on Read */
__IO uint32_t CNTFREEZ : 1; /*!< MMC Counter Freeze */
__IO uint32_t CNTPRST : 1; /*!< Counters Preset */
__IO uint32_t CNTPRSTLVL : 1; /*!< Counters Preset */
uint32_t : 2;
__IO uint32_t UCDBC : 1; /*!< Update MMC Counters for Dropped Broadcast Frames */
} MMCCR_b; /*!< BitSize */
};
__IO uint32_t MMCRIR; /*!< MMC Receive Interrupt Register */
__IO uint32_t MMCTIR; /*!< MMC Transmit Interrupt Register */
__IO uint32_t MMCRIMR; /*!< MMC Receive interrupt mask */
__IO uint32_t MMCTIMR; /*!< MMC Transmit Interrupt Mask */
__I uint32_t RESERVED4[59];
__IO uint32_t MMCIRCOIM; /*!< MMC IPC Receive Checksum Offload Interrupt Mask */
__I uint32_t RESERVED5[319];
union {
__IO uint32_t PTPTSCR; /*!< Timestamp Control Register */
struct {
__IO uint32_t TSENA : 1; /*!< Timestamp Enable */
__IO uint32_t TSCFUPDT : 1; /*!< Timestamp Fine or Coarse Update */
__IO uint32_t TSINIT : 1; /*!< Timestamp Initialize */
__IO uint32_t TSUPDT : 1; /*!< Timestamp Update */
__IO uint32_t TSTRIG : 1; /*!< Timestamp Interrupt Trigger Enable */
__IO uint32_t TSADDREG : 1; /*!< Addend Reg Update */
} PTPTSCR_b; /*!< BitSize */
};
__IO uint32_t PTPSSIR; /*!< Sub-Second Increment Register */
__IO uint32_t PTPTSHR; /*!< System Time Seconds Register */
__IO uint32_t PTPTSLR; /*!< System Time Nanoseconds Register */
__IO uint32_t PTPTSHUR; /*!< System Time Seconds Update Register */
__IO uint32_t PTPTSLUR; /*!< System Time Nanoseconds Update Register */
__IO uint32_t PTPTSAR; /*!< Timestamp Addend Register */
__IO uint32_t PTPTTHR; /*!< Target Time Seconds Register */
__IO uint32_t PTPTTLR; /*!< Target Time Nanoseconds Register */
__I uint32_t RESERVED6[567];
union {
__IO uint32_t BUS_MODE; /*!< Flow Control Register */
@@ -3019,7 +3086,7 @@ typedef struct { /*!< ETH Structure
__IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */
} INT_EN_b; /*!< BitSize */
};
__I uint32_t RESERVED4[3];
__I uint32_t RESERVED7[3];
union {
__IO uint32_t AHB_STATUS; /*!< AHB Status Register */
@@ -3029,7 +3096,7 @@ typedef struct { /*!< ETH Structure
in the non-idle state */
} AHB_STATUS_b; /*!< BitSize */
};
__I uint32_t RESERVED5[6];
__I uint32_t RESERVED8[6];
__I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */
__I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */
__I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */
@@ -7227,7 +7294,7 @@ typedef struct { /*!< GLOBAL_CTRL Structure
struct {
__IO uint32_t SECOND : 1; /*!< 1s interrupt enable */
__IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt enable */
__IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt enable */
} RTC_INT_EN_b; /*!< BitSize */
};
__I uint32_t RESERVED1;
@@ -7315,7 +7382,9 @@ typedef struct { /*!< DDRC Structure
__IO uint32_t MODE : 6; /*!< DDRC Mode */
uint32_t : 2;
__IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */
uint32_t : 7;
uint32_t : 3;
__IO uint32_t ADEC : 1; /*!< address decoder mapping */
uint32_t : 3;
__IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */
uint32_t : 6;
__IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */
@@ -7933,7 +8002,7 @@ typedef struct { /*!< SOFT_RESET Structure
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group CMEM7 */
/** @} */ /* End of group cmem7 */
/** @} */ /* End of group (null) */
#ifdef __cplusplus
@@ -7941,5 +8010,5 @@ typedef struct { /*!< SOFT_RESET Structure
#endif
#endif /* CMEM7_H */
#endif /* cmem7_H */
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h
+8 -1
View File
@@ -45,6 +45,11 @@
#define _USB
#define _WDG
//#define _MARVELL
//#define _IP1826D
#define _M7NORFLASH
#define _ME_6095_F
#define USE_FULL_ASSERT 1
#ifdef USE_FULL_ASSERT
@@ -71,7 +76,9 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
/**
* System clock frequency, unit is Hz.
*/
#define SYSTEM_CLOCK_FREQ 200000000
#define SYSTEM_CLOCK_FREQ 300000000
//250000000
//300000000
/**
* @brief usecond delay
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h
+50 -15
View File
@@ -86,7 +86,6 @@
/**
* @}
*/
/**
* @brief EFUSE receive filter structure
*/
@@ -105,15 +104,15 @@ typedef struct
*/
typedef struct
{
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
BOOL ETH_RxEn; /*!< Rx enable */
BOOL ETH_TxEn; /*!< Tx enable */
BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */
BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */
uint8_t ETH_MacAddr[6]; /*!< MAC address */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
} ETH_InitTypeDef;
/**
@@ -173,14 +172,14 @@ typedef struct {
uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
uint32_t : 5;
uint32_t TTSE : 1; /*!< timestamp available while last segment */
uint32_t LS : 1; /*!< last segment flag */
uint32_t FS : 1; /*!< first segment flag */
uint32_t LS : 1; /*!< [OUT] last segment flag */
uint32_t FS : 1; /*!< [OUT] first segment flag */
uint32_t : 1;
uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
uint32_t : 2;
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
uint32_t FL : 14; /*!< frame length while last segment */
uint32_t FL : 14; /*!< [OUT] frame length while last segment */
uint32_t : 2;
} RX0_b;
} RX_0;
@@ -216,7 +215,13 @@ uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
* @retval None
*/
void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/**
* @brief Fills each ETH_InitStruct member with its default value.
* @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void ETH_StructInit(ETH_InitTypeDef* init);
/**
* @brief Ethernet initialization
* @note This function should be called at first before any other interfaces.
@@ -231,21 +236,21 @@ BOOL ETH_Init(ETH_InitTypeDef *init);
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void ETH_EnableInt(uint32_t Int, BOOL enable);
void ETH_ITConfig(uint32_t Int, BOOL enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL ETH_GetIntStatus(uint32_t Int);
BOOL ETH_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @retval None
*/
void ETH_ClearInt(uint32_t Int);
void ETH_ClearITPendingBit(uint32_t Int);
/**
* @brief Get ethernte MAC address
@@ -299,7 +304,7 @@ ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
/**
* @brief Check if a transmission descriptor is free or not
* @param desc A pointer of a transmission descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval BOOL True if the transmission descriptor is free, or flase.
*/
BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
@@ -309,11 +314,26 @@ BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
* After users prepared data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param desc A pointer of a transmission descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
/**
* @brief Set buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @param[in] bufAddr buffer address to be sent
* @retval None
*/
void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific TX descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
/**
* @brief Set ethernet receive descriptor ring
* @note Make sure that memory occupied by descriptors should be in physical
@@ -359,7 +379,7 @@ ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
/**
* @brief Check if a receive descriptor is free or not
* @param desc A pointer of a receive descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval BOOL True if the receive descriptor is free, or flase.
*/
BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
@@ -369,11 +389,26 @@ BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
* After users handled data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param desc A pointer of a transmission descriptor
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
/**
* @brief Set buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @param[in] bufAddr buffer address to be received
* @retval None
*/
void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
#ifdef __cplusplus
}
#endif
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h
+8
View File
@@ -202,6 +202,14 @@ void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
*/
void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
void flash_WaitInWritting(void) ;
void flash_WaitReadFifoNotEmpty(void);
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ;
#ifdef __cplusplus
}
#endif
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h
+11
View File
@@ -140,6 +140,17 @@ void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLev
*/
void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask);
void GPIO_clrBits(uint32_t mask);
uint32_t GPIO_getBits(uint32_t mask);
#ifdef __cplusplus
}
#endif
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h
+10
View File
@@ -102,6 +102,16 @@
#include "cmem7_wdg.h"
#endif
#ifdef _MARVELL
#include <marvel_98dx242.h>
#include <s24g_i2c.h>
#endif
#ifdef _IP1826D
#include <ip1826d_v00.h>
#endif
#ifdef __cplusplus
}
#endif
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h
+41 -1
View File
@@ -87,9 +87,11 @@ typedef struct
* @{
*/
#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000)
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
@@ -197,6 +199,20 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
*/
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
/**
* @brief Convert the mapping destination address to source address
* @param[in] to address to be mapped to
* @retval uint32_t address to be mapped from
*/
uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
/**
* @brief Convert the mapping source address to destination address
* @param[in] from address to be mapped from
* @retval uint32_t address to be mapped to
*/
uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
/**
* @brief Set NMI irq number, it should be one of @ref IRQn_Type.
* @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
@@ -228,6 +244,30 @@ void GLB_SetNmiIrqNum(uint32_t irq);
*/
void GLB_SelectSysClkSource(uint8_t source);
/**
* @brief Simulate instruction 'STRB' or 'STRH' with 'BFI'
* @Note In M7, you have to write a register in 32-bit alignment,
* not in 8-bit or 16-bit.
* @param[in] addr register address to be written
* @param[in] value value to be written
* @param[in] lsb LSB in register to be written
* @param[in] len bit length to be written
* @retval None
*/
//#define aaaa(len) __asm("LDR len, 11")
#define CMEM7_BFI(addr, value, lsb, len) \
do { \
unsigned long tmp; \
unsigned long tmp1 = (unsigned long)addr; \
\
__asm("LDR tmp, [tmp1]\n" \
"BFI tmp, "#value", "#lsb", "#len" \n" \
"STR tmp, [tmp1]\n"); \
} while (0)
#ifdef __cplusplus
}
#endif
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h
+8 -8
View File
@@ -38,34 +38,34 @@
* @{
*/
#define RTC_Int_Second ((uint32_t)0x00000001)
#define RTC_Int_Microsecond ((uint32_t)0x00000002)
#define RTC_Int_Millsecond ((uint32_t)0x00000002)
#define RTC_Int_All ((uint32_t)0x00000003)
#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
/**
* @}
*/
/**
* @brief Enable or disable RTC interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None
*/
void RTC_EnableInt(uint32_t Int, BOOL Enable);
void RTC_ITConfig(uint32_t Int, BOOL Enable);
/**
* @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval BOOL The bit indicates if specific interrupts are set or not
*/
BOOL RTC_GetIntStatus(uint32_t Int);
BOOL RTC_GetITStatus(uint32_t Int);
/**
* @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval None
*/
void RTC_ClearInt(uint32_t Int);
void RTC_ClearITPendingBit(uint32_t Int);
/**
* @brief Get seconds since power up
@@ -75,11 +75,11 @@ void RTC_ClearInt(uint32_t Int);
uint32_t RTC_GetSecond(void);
/**
* @brief Get current micro-seconds
* @brief Get current millseconds
* @param None
* @retval uint32_t Current micro-seconds
* @retval uint32_t Current millseconds
*/
uint16_t RTC_GetMicroSecond(void);
uint16_t RTC_GetMillSecond(void);
#ifdef __cplusplus
}
bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h
+13 -6
View File
@@ -56,14 +56,21 @@
* @}
*/
/**
* @brief Deinitializes the Watchdog peripheral registers to their default reset values.
* @param[in] None
* @retval None
*/
void WDG_DeInit(void);
/**
* @brief Watchdog initialization
* @note This function should be called at first before any other interfaces.
* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
* @param[in] ResetMicroSecond MicroSeconds lasts before global reset
* @param[in] ResetMillSecond MillSeconds lasts before global reset
* @retval None
*/
void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond);
void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
/**
* @brief Enable or disable watchdog interrupt.
@@ -71,28 +78,28 @@ void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond);
* @param[in] Enable The bit indicates if the specific interrupt are enable or not
* @retval None
*/
void WDG_EnableInt(uint8_t Int, BOOL Enable);
void WDG_ITConfig(uint8_t Int, BOOL Enable);
/**
* @brief Check the specific interrupt are set or not
* @param None
* @retval BOOL The bit indicates if the specific interrupt are set or not
*/
BOOL WDG_GetIntStatus(void);
BOOL WDG_GetITStatus(void);
/**
* @brief Clear the specific interrupt
* @param None
* @retval None
*/
void WDG_ClearInt(void);
void WDG_ClearITPendingBit(void);
/**
* @brief Enable or disable watchdog.
* @param[in] Enable The bit indicates if watchdog is enable or not
* @retval None
*/
void WDG_Enable(BOOL Enable);
void WDG_Cmd(BOOL Enable);
#ifdef __cplusplus
bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c
+100 -37
View File
File diff suppressed because it is too large. Load diff
bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c
+6 -3
View File
@@ -108,7 +108,8 @@ static uint8_t flash_ReadInnerStatusHigh() {
return (uint8_t)NOR_FLASH->DATA;
}
static void flash_WaitInWritting() {
//static void flash_WaitInWritting() {
void flash_WaitInWritting(void) {
FLASH_INNER_STATUS s;
while (NOR_FLASH->STATUS_b.BUSY);
@@ -173,7 +174,8 @@ static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
NOR_FLASH->TRIGGER_b.OP_START = TRUE;
}
static void flash_WaitReadFifoNotEmpty() {
//static void flash_WaitReadFifoNotEmpty() {
void flash_WaitReadFifoNotEmpty(void) {
while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
if (wait) {
(*wait)();
@@ -181,7 +183,8 @@ static void flash_WaitReadFifoNotEmpty() {
}
}
static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
//static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
uint16_t count = 0;
while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c
+75
View File
@@ -179,3 +179,78 @@ void GPIO_EnablePwm(uint8_t Channel, BOOL Enable) {
}
}
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask)
{
static uint32_t g_GPIO_OUT_UNMASK;
static uint32_t g_GPIO_OUT_DATA;
static uint32_t g_GPIO_OE;
g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
g_GPIO_OUT_DATA = GPIO->GPIO_OUT_DATA ;
g_GPIO_OE = GPIO->GPIO_OE ;
g_GPIO_OUT_UNMASK |=mask;
g_GPIO_OE |=mask;
g_GPIO_OUT_DATA |=mask;
GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
GPIO->GPIO_OUT_DATA =g_GPIO_OUT_DATA ;
GPIO->GPIO_OE =g_GPIO_OE ;
}
void GPIO_clrBits(uint32_t mask)
{
static uint32_t g_GPIO_OUT_UNMASK;
static uint32_t g_GPIO_OUT_DATA;
static uint32_t g_GPIO_OE;
g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
g_GPIO_OUT_DATA = GPIO->GPIO_OUT_DATA ;
g_GPIO_OE = GPIO->GPIO_OE ;
g_GPIO_OUT_UNMASK |=mask;
g_GPIO_OE |=mask;
g_GPIO_OUT_DATA &=(~ mask);
GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
GPIO->GPIO_OUT_DATA =g_GPIO_OUT_DATA ;
GPIO->GPIO_OE =g_GPIO_OE ;
}
uint32_t GPIO_getBits(uint32_t mask)
{
static uint32_t g_GPIO_OUT_UNMASK;
//static uint32_t g_GPIO_OUT_DATA;
static uint32_t g_GPIO_OE;
uint32_t get_delay = 0;
uint32_t saved_mask;
saved_mask=mask;
g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
g_GPIO_OE = GPIO->GPIO_OE ;
g_GPIO_OUT_UNMASK &=(~mask);
g_GPIO_OE &=(~mask);
GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
GPIO->GPIO_OE =g_GPIO_OE ;
for(get_delay=0;get_delay<100;get_delay++)
{
}
//get_delay=(GPIO->GPIO_IN)&saved_mask;
if(((GPIO->GPIO_IN)&saved_mask)==saved_mask)
{
return(1);
}
else
{
return(0);
}
}
/**
xjf 20150324
**/
bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c
+45 -1
View File
@@ -92,8 +92,20 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState)
}
}
#define DEF_IBUS_OFFSET 0x1FFE0000
#define DEF_EXT_ADDR 0x08020000
static BOOL isMappingOn() {
/* If default values aren't changed */
if ((GLOBAL_CTRL->IBUSOFF == DEF_IBUS_OFFSET) &&
(GLOBAL_CTRL->EXTADDR == DEF_EXT_ADDR)) {
return FALSE;
}
return TRUE;
}
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
int n;
volatile int n;
GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
GLOBAL_CTRL->EXTADDR = to;
@@ -104,6 +116,38 @@ void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
for (n = 0; n < 100; n++);
}
/*
* ------------------------------------------------------------------
* | 0 - 0x20000 | --> 0x20000000 | -> 0x40000000 | -> 0xFFFFFFFF |
* | code SRAM | map to region | data SRAM | map from region |
* ------------------------------------------------------------------
*/
#define MAPPING_FROM_REGION_START 0x40000000
#define MAPPING_TO_REGION_END 0x20000000
uint32_t GLB_ConvertToMappingFromAddr(uint32_t to) {
if (!isMappingOn()) {
return to;
}
if ((to > MAPPING_TO_REGION_END) || (to < GLOBAL_CTRL->EXTADDR)) {
return to;
}
return (to + GLOBAL_CTRL->IBUSOFF);
}
uint32_t GLB_ConvertToMappingToAddr(uint32_t from) {
if (!isMappingOn()) {
return from;
}
if (from < MAPPING_FROM_REGION_START) {
return from;
}
return (from - GLOBAL_CTRL->IBUSOFF);
}
void GLB_SetNmiIrqNum(uint32_t irq) {
GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
}
bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c
+5 -5
View File
@@ -28,7 +28,7 @@
#define SECONDS_IN_A_DAY (86400)
void RTC_EnableInt(uint32_t Int, BOOL Enable) {
void RTC_ITConfig(uint32_t Int, BOOL Enable) {
assert_param(IS_RTC_INT(Int));
if (Enable) {
@@ -38,7 +38,7 @@ void RTC_EnableInt(uint32_t Int, BOOL Enable) {
}
}
BOOL RTC_GetIntStatus(uint32_t Int) {
BOOL RTC_GetITStatus(uint32_t Int) {
assert_param(IS_RTC_INT(Int));
if (0 != (RTC->INT_STATUS & Int)) {
@@ -48,7 +48,7 @@ BOOL RTC_GetIntStatus(uint32_t Int) {
return FALSE;
}
void RTC_ClearInt(uint32_t Int) {
void RTC_ClearITPendingBit(uint32_t Int) {
assert_param(IS_RTC_INT(Int));
RTC->INT_STATUS = Int;
@@ -58,6 +58,6 @@ uint32_t RTC_GetSecond() {
return RTC->SECOND;
}
uint16_t RTC_GetMicroSecond() {
return RTC->MICROSECOND_b.MS;
uint16_t RTC_GetMillSecond() {
return RTC->MILLSECOND_b.MS;
}
bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c
+11 -6
View File
@@ -30,29 +30,34 @@ static uint32_t wdg_GetClock() {
return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1));
}
void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond) {
void WDG_DeInit(void){
SOFT_RESET->SOFTRST_b.WDT_n = 0;
SOFT_RESET->SOFTRST_b.WDT_n = 1;
}
void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond) {
assert_param(IS_WDG_TRIGGER_MODE(trigger));
WDG->INT_CTRL_b.TRIGGER_MODE = trigger;
WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMicroSecond / 1000;
WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMillSecond / 1000;
}
void WDG_EnableInt(uint8_t Int, BOOL Enable) {
void WDG_ITConfig(uint8_t Int, BOOL Enable) {
assert_param(IS_WDG_INT(Int));
WDG->CTRL_b.INT_LEN = Int;
WDG->INT_CTRL_b.MASK = !Enable;
}
BOOL WDG_GetIntStatus() {
BOOL WDG_GetITStatus() {
return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE;
}
void WDG_ClearInt() {
void WDG_ClearITPendingBit() {
WDG->INT_STA_b.STA = 1;
}
void WDG_Enable(BOOL Enable) {
void WDG_Cmd(BOOL Enable) {
WDG->CTRL_b.EN = Enable;
}
bsp/CME_M7/drivers/emac.c
+17 -17
View File
@@ -205,14 +205,14 @@ static rt_err_t rt_cme_eth_init(rt_device_t dev)
RxDescChainInit();
TxDescChainInit();
ETH_EnableInt(ETH_INT_BUS_FATAL_ERROR, TRUE);
ETH_ITConfig(ETH_INT_BUS_FATAL_ERROR, TRUE);
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_EnableInt(ETH_INT_RX_STOP, TRUE);
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_ITConfig(ETH_INT_RX_STOP, TRUE);
ETH_StartRx();
ETH_EnableInt(ETH_INT_TX_COMPLETE_FRAME, TRUE);
ETH_ITConfig(ETH_INT_TX_COMPLETE_FRAME, TRUE);
ETH_StartTx();
return RT_EOK;
@@ -318,8 +318,8 @@ struct pbuf *rt_cme_eth_rx(rt_device_t dev)
desc = ETH_AcquireFreeRxDesc();
if(desc == RT_NULL)
{
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE);
ETH_ResumeRx();
goto _exit;
}
@@ -414,28 +414,28 @@ void ETH_IRQHandler(void)
/* enter interrupt */
rt_interrupt_enter();
if (ETH_GetIntStatus(ETH_INT_TX_COMPLETE_FRAME))
if (ETH_GetITStatus(ETH_INT_TX_COMPLETE_FRAME))
{
rt_sem_release(&cme_eth_device.tx_buf_free);
ETH_ClearInt(ETH_INT_TX_COMPLETE_FRAME);
ETH_ClearITPendingBit(ETH_INT_TX_COMPLETE_FRAME);
}
if (ETH_GetIntStatus(ETH_INT_RX_STOP))
if (ETH_GetITStatus(ETH_INT_RX_STOP))
{
CME_ETH_PRINTF("ETH_INT_RX_STOP\n");
ETH_ClearInt(ETH_INT_RX_STOP);
ETH_ClearITPendingBit(ETH_INT_RX_STOP);
}
if ((ETH_GetIntStatus(ETH_INT_RX_BUF_UNAVAI)) ||
(ETH_GetIntStatus(ETH_INT_RX_COMPLETE_FRAME)))
if ((ETH_GetITStatus(ETH_INT_RX_BUF_UNAVAI)) ||
(ETH_GetITStatus(ETH_INT_RX_COMPLETE_FRAME)))
{
/* a frame has been received */
eth_device_ready(&(cme_eth_device.parent));
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, FALSE);
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, FALSE);
ETH_ClearInt(ETH_INT_RX_BUF_UNAVAI);
ETH_ClearInt(ETH_INT_RX_COMPLETE_FRAME);
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, FALSE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, FALSE);
ETH_ClearITPendingBit(ETH_INT_RX_BUF_UNAVAI);
ETH_ClearITPendingBit(ETH_INT_RX_COMPLETE_FRAME);
}
/* leave interrupt */
bsp/CME_M7/project.uvopt
+956 -888
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bsp/CME_M7/project.uvproj
+285 -292
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bsp/CME_M7/rtconfig.py
+1 -1
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@@ -24,7 +24,7 @@ if os.getenv('RTT_EXEC_PATH'):
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd())
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
BUILD = 'debug'
bsp/asm9260t/project.uvproj
+930
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bsp/frdm-k64f/project.uvproj
+74 -60
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bsp/lm4f232/project.uvproj
+322 -322
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bsp/lpc176x/project.uvproj
+327 -198
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bsp/lpc178x/project.uvproj
+241 -175
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bsp/lpc2478/project.uvproj
+220 -144
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bsp/lpc408x/project.uvproj
+1031
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bsp/mb9bf506r/project.uvproj
+241 -165
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bsp/mb9bf568r/project.uvproj
+682
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bsp/mini2440/project.Uv2
+431
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bsp/nrf51822/project.uvproj
+646
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bsp/sam7x/project.uvproj
+312 -175
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bsp/stm32f0x/project.uvproj
+454 -188
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bsp/stm32f107/project.uvopt
+4 -1624
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bsp/stm32f107/project.uvproj
+536 -350
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bsp/stm32f10x/applications/canapp.c
+145
View File
@@ -0,0 +1,145 @@
/*
* File : canapp.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-05-14 aubrcool@qq.com first version
*/
#ifdef RT_USING_CAN
#include <board.h>
#include <rtthread.h>
#include <rtdevice.h>
struct can_app_struct
{
const char* name;
struct rt_event event;
struct rt_can_filter_config * filter;
rt_uint8_t eventopt;
};
static struct can_app_struct can_data[2];
static rt_err_t can1ind(rt_device_t dev, void* args, rt_int32_t hdr, rt_size_t size)
{
rt_event_t pevent = (rt_event_t)args;
rt_event_send(pevent, 1 << (hdr));
return RT_EOK;
}
static rt_err_t can2ind(rt_device_t dev, void* args, rt_int32_t hdr, rt_size_t size)
{
rt_event_t pevent = (rt_event_t)args;
rt_event_send(pevent, 1 << (hdr));
return RT_EOK;
}
struct rt_can_filter_item filter1item[4] =
{
RT_CAN_FILTER_STD_INIT(1,can1ind,&can_data[0].event),
RT_CAN_FILTER_STD_INIT(2,can1ind,&can_data[0].event),
RT_CAN_STD_RMT_FILTER_INIT(3,can1ind,&can_data[0].event),
RT_CAN_STD_RMT_DATA_FILTER_INIT(4,can1ind,&can_data[0].event),
};
struct rt_can_filter_item filter2item[4] =
{
RT_CAN_FILTER_STD_INIT(1,can2ind,&can_data[1].event),
RT_CAN_FILTER_STD_INIT(2,can2ind,&can_data[1].event),
RT_CAN_STD_RMT_FILTER_INIT(3,can2ind,&can_data[1].event),
RT_CAN_STD_RMT_DATA_FILTER_INIT(4,can2ind,&can_data[1].event),
};
struct rt_can_filter_config filter1 =
{
.count = 4,
.actived = 1,
.items = filter1item,
};
struct rt_can_filter_config filter2 =
{
.count = 4,
.actived = 1,
.items = filter2item,
};
static struct can_app_struct can_data[2] = {
{
.name = "bxcan1",
.filter = &filter1,
.eventopt = RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
},
{
.name = "bxcan2",
.filter = &filter2,
.eventopt = RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR,
},
};
void rt_can_thread_entry(void* parameter)
{
struct rt_can_msg msg;
struct can_app_struct* canpara = (struct can_app_struct*) parameter;
rt_device_t candev;
rt_uint32_t e;
candev = rt_device_find(canpara->name);
RT_ASSERT(candev);
rt_event_init(&canpara->event, canpara->name, RT_IPC_FLAG_FIFO);
rt_device_open(candev, (RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX));
rt_device_control(candev,RT_CAN_CMD_SET_FILTER,canpara->filter);
while(1) {
if (
rt_event_recv(&canpara->event,
((1 << canpara->filter->items[0].hdr) |
(1 << canpara->filter->items[1].hdr) |
(1 << canpara->filter->items[2].hdr) |
(1 << canpara->filter->items[3].hdr)),
canpara->eventopt,
RT_WAITING_FOREVER, &e) != RT_EOK
) {
continue;
}
if(e & (1 << canpara->filter->items[0].hdr)) {
msg.hdr = canpara->filter->items[0].hdr;
while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) {
rt_device_write(candev, 0, &msg, sizeof(msg));
}
}
if(e & (1 << canpara->filter->items[1].hdr)) {
msg.hdr = canpara->filter->items[1].hdr;
while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) {
rt_device_write(candev, 0, &msg, sizeof(msg));
}
}
if(e & (1 << canpara->filter->items[2].hdr)) {
msg.hdr = canpara->filter->items[2].hdr;
while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) {
rt_device_write(candev, 0, &msg, sizeof(msg));
}
}
if(e & (1 << canpara->filter->items[3].hdr)) {
msg.hdr = canpara->filter->items[3].hdr;
while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) {
rt_device_write(candev, 0, &msg, sizeof(msg));
}
}
}
}
int rt_can_app_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("canapp1",
rt_can_thread_entry, &can_data[0],
512, RT_THREAD_PRIORITY_MAX /3 - 1, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
tid = rt_thread_create("canapp2",
rt_can_thread_entry, &can_data[1],
512, RT_THREAD_PRIORITY_MAX /3 - 1, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;
}
INIT_APP_EXPORT(rt_can_app_init);
#endif /*RT_USING_CAN*/
bsp/stm32f10x/drivers/bxcan.c
+1412
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File diff suppressed because it is too large. Load diff
bsp/stm32f10x/drivers/bxcan.h
+17
View File
@@ -0,0 +1,17 @@
/*
* File : bxcan.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-05-14 aubrcool@qq.com first version
*/
#ifndef BXCAN_H_
#define BXCAN_H_
#endif /*BXCAN_H_*/
bsp/stm32f10x/project.Uv2
+72 -73
View File
@@ -3,84 +3,83 @@
Target (RT-Thread STM32), 0x0004 // Tools: 'ARM-ADS'
Group (STM32_StdPeriph)
Group (Applications)
Group (Drivers)
Group (STM32_StdPeriph)
Group (Kernel)
Group (CORTEX-M3)
Group (DeviceDrivers)
Group (finsh)
Group (Components)
File 1,1,<applications\application.c><application.c>
File 1,1,<applications\startup.c><startup.c>
File 2,1,<drivers\board.c><board.c>
File 2,1,<drivers\stm32f10x_it.c><stm32f10x_it.c>
File 2,1,<drivers\led.c><led.c>
File 2,1,<drivers\usart.c><usart.c>
File 3,1,<Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c><system_stm32f10x.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c><stm32f10x_crc.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c><stm32f10x_pwr.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c><stm32f10x_exti.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c><stm32f10x_bkp.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c><stm32f10x_i2c.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c><stm32f10x_adc.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c><stm32f10x_dac.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c><stm32f10x_rtc.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c><stm32f10x_fsmc.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c><stm32f10x_tim.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c><stm32f10x_spi.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c><stm32f10x_flash.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c><stm32f10x_sdio.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c><stm32f10x_usart.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c><stm32f10x_dma.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c><stm32f10x_can.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c><stm32f10x_cec.c>
File 3,1,<Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c>
File 3,2,<Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s><startup_stm32f10x_hd.s>
File 4,1,<..\..\src\clock.c><clock.c>
File 4,1,<..\..\src\device.c><device.c>
File 4,1,<..\..\src\idle.c><idle.c>
File 4,1,<..\..\src\ipc.c><ipc.c>
File 4,1,<..\..\src\irq.c><irq.c>
File 4,1,<..\..\src\kservice.c><kservice.c>
File 4,1,<..\..\src\mem.c><mem.c>
File 4,1,<..\..\src\mempool.c><mempool.c>
File 4,1,<..\..\src\object.c><object.c>
File 4,1,<..\..\src\scheduler.c><scheduler.c>
File 4,1,<..\..\src\thread.c><thread.c>
File 4,1,<..\..\src\timer.c><timer.c>
File 5,1,<..\..\libcpu\arm\cortex-m3\cpuport.c><cpuport.c>
File 5,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S><context_rvds.S>
File 5,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
File 5,1,<..\..\libcpu\arm\common\div0.c><div0.c>
File 5,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
File 6,1,<..\..\components\drivers\serial\serial.c><serial.c>
File 6,1,<..\..\components\drivers\src\completion.c><completion.c>
File 6,1,<..\..\components\drivers\src\dataqueue.c><dataqueue.c>
File 6,1,<..\..\components\drivers\src\pipe.c><pipe.c>
File 6,1,<..\..\components\drivers\src\ringbuffer.c><ringbuffer.c>
File 7,1,<..\..\components\finsh\cmd.c><cmd.c>
File 7,1,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c>
File 7,1,<..\..\components\finsh\finsh_error.c><finsh_error.c>
File 7,1,<..\..\components\finsh\finsh_heap.c><finsh_heap.c>
File 7,1,<..\..\components\finsh\finsh_init.c><finsh_init.c>
File 7,1,<..\..\components\finsh\finsh_node.c><finsh_node.c>
File 7,1,<..\..\components\finsh\finsh_ops.c><finsh_ops.c>
File 7,1,<..\..\components\finsh\finsh_parser.c><finsh_parser.c>
File 7,1,<..\..\components\finsh\finsh_token.c><finsh_token.c>
File 7,1,<..\..\components\finsh\finsh_var.c><finsh_var.c>
File 7,1,<..\..\components\finsh\finsh_vm.c><finsh_vm.c>
File 7,1,<..\..\components\finsh\msh.c><msh.c>
File 7,1,<..\..\components\finsh\msh_cmd.c><msh_cmd.c>
File 7,1,<..\..\components\finsh\shell.c><shell.c>
File 7,1,<..\..\components\finsh\symbol.c><symbol.c>
File 8,1,<..\..\components\init\components.c><components.c>
File 1,1,<Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c><system_stm32f10x.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c><stm32f10x_crc.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c><stm32f10x_rcc.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c><stm32f10x_wwdg.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c><stm32f10x_pwr.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c><stm32f10x_exti.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c><stm32f10x_bkp.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c><stm32f10x_i2c.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c><stm32f10x_adc.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c><stm32f10x_dac.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c><stm32f10x_rtc.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c><stm32f10x_fsmc.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c><stm32f10x_tim.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c><stm32f10x_iwdg.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c><stm32f10x_spi.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c><stm32f10x_flash.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c><stm32f10x_sdio.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c><stm32f10x_gpio.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c><stm32f10x_usart.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c><stm32f10x_dma.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c><stm32f10x_can.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c><stm32f10x_cec.c>
File 1,1,<Libraries/STM32F10x_StdPeriph_Driver/src/misc.c><misc.c>
File 1,2,<Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s><startup_stm32f10x_hd.s>
File 2,1,<applications/application.c><application.c>
File 2,1,<applications/startup.c><startup.c>
File 3,1,<drivers/board.c><board.c>
File 3,1,<drivers/stm32f10x_it.c><stm32f10x_it.c>
File 3,1,<drivers/led.c><led.c>
File 3,1,<drivers/usart.c><usart.c>
File 4,1,<../../src/clock.c><clock.c>
File 4,1,<../../src/components.c><components.c>
File 4,1,<../../src/device.c><device.c>
File 4,1,<../../src/idle.c><idle.c>
File 4,1,<../../src/ipc.c><ipc.c>
File 4,1,<../../src/irq.c><irq.c>
File 4,1,<../../src/kservice.c><kservice.c>
File 4,1,<../../src/mem.c><mem.c>
File 4,1,<../../src/mempool.c><mempool.c>
File 4,1,<../../src/object.c><object.c>
File 4,1,<../../src/scheduler.c><scheduler.c>
File 4,1,<../../src/thread.c><thread.c>
File 4,1,<../../src/timer.c><timer.c>
File 5,1,<../../libcpu/arm/cortex-m3/cpuport.c><cpuport.c>
File 5,2,<../../libcpu/arm/cortex-m3/context_rvds.S><context_rvds.S>
File 5,1,<../../libcpu/arm/common/backtrace.c><backtrace.c>
File 5,1,<../../libcpu/arm/common/div0.c><div0.c>
File 5,1,<../../libcpu/arm/common/showmem.c><showmem.c>
File 6,1,<../../components/drivers/serial/serial.c><serial.c>
File 6,1,<../../components/drivers/src/completion.c><completion.c>
File 6,1,<../../components/drivers/src/dataqueue.c><dataqueue.c>
File 6,1,<../../components/drivers/src/pipe.c><pipe.c>
File 6,1,<../../components/drivers/src/portal.c><portal.c>
File 6,1,<../../components/drivers/src/ringbuffer.c><ringbuffer.c>
File 6,1,<../../components/drivers/src/workqueue.c><workqueue.c>
File 7,1,<../../components/finsh/shell.c><shell.c>
File 7,1,<../../components/finsh/symbol.c><symbol.c>
File 7,1,<../../components/finsh/cmd.c><cmd.c>
File 7,1,<../../components/finsh/finsh_compiler.c><finsh_compiler.c>
File 7,1,<../../components/finsh/finsh_error.c><finsh_error.c>
File 7,1,<../../components/finsh/finsh_heap.c><finsh_heap.c>
File 7,1,<../../components/finsh/finsh_init.c><finsh_init.c>
File 7,1,<../../components/finsh/finsh_node.c><finsh_node.c>
File 7,1,<../../components/finsh/finsh_ops.c><finsh_ops.c>
File 7,1,<../../components/finsh/finsh_parser.c><finsh_parser.c>
File 7,1,<../../components/finsh/finsh_var.c><finsh_var.c>
File 7,1,<../../components/finsh/finsh_vm.c><finsh_vm.c>
File 7,1,<../../components/finsh/finsh_token.c><finsh_token.c>
@@ -143,7 +142,7 @@ Options 1,0,0 // Target 'RT-Thread STM32'
ADSCMISC ()
ADSCDEFN (STM32F10X_HD, USE_STDPERIPH_DRIVER)
ADSCUDEF ()
ADSCINCD (Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\include;drivers;..\..\components\CMSIS\Include;.;applications;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\libcpu\arm\common;..\..\components\init;..\..\components\finsh;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x)
ADSCINCD (../../libcpu/arm/cortex-m3;../../components/drivers/include;Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x;../../libcpu/arm/common;.;applications;../../include;../../components/finsh;../../components/CMSIS/Include;drivers;Libraries/STM32F10x_StdPeriph_Driver/inc)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
@@ -164,7 +163,7 @@ Options 1,0,0 // Target 'RT-Thread STM32'
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC ( --keep __fsym_* --keep __vsym_* --keep __rt_init* )
ADSLDMC ( --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) )
ADSLDIF ()
ADSLDDW ()
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE)
bsp/stm32f20x/project.uvproj
+349 -342
View File
File diff suppressed because it is too large. Load diff
bsp/stm32f40x/applications/application.c
+1 -1
View File
@@ -20,7 +20,7 @@
#include <lwip/sys.h>
#include <lwip/api.h>
#include <netif/ethernetif.h>
#include "stm32_eth.h"
#include "stm32f4xx_eth.h"
#endif
#ifdef RT_USING_GDB
bsp/stm32f40x/drivers/SConscript
+17 -1
View File
@@ -3,9 +3,25 @@ Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
src = Glob('*.c')
# add the general drivers.
src = Split("""
board.c
stm32f4xx_it.c
usart.c
""")
# add Ethernet drivers.
if GetDepend('RT_USING_LWIP'):
src += ['stm32f4xx_eth.c']
# add gpio drivers.
if GetDepend('RT_USING_PIN'):
src += ['gpio.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/stm32f40x/drivers/stm32f4xx_eth.c
+4038
View File
File diff suppressed because it is too large. Load diff
bsp/stm32f40x/drivers/stm32f4xx_eth.h
+1874
View File
File diff suppressed because it is too large. Load diff
bsp/stm32f40x/project.uvproj
+92 -85
View File
File diff suppressed because it is too large. Load diff
bsp/stm32f40x/project.uvprojx
+57 -7
View File
@@ -365,7 +365,7 @@
<MiscControls></MiscControls>
<Define>USE_STDPERIPH_DRIVER</Define>
<Undefine></Undefine>
<IncludePath>.;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries\CMSIS\Include;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\STM32F4xx_StdPeriph_Driver\inc;applications;drivers</IncludePath>
<IncludePath>.;..\..\components\drivers\include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries\CMSIS\Include;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\STM32F4xx_StdPeriph_Driver\inc;applications;drivers</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -398,7 +398,7 @@
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc> --keep __fsym_* --keep __vsym_* </Misc>
<Misc> --keep *.o(FSymTab) --keep *.o(VSymTab) </Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
@@ -428,11 +428,6 @@
<FileType>1</FileType>
<FilePath>drivers\board.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\serial.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_it.c</FileName>
<FileType>1</FileType>
@@ -443,6 +438,11 @@
<FileType>1</FileType>
<FilePath>drivers\usart.c</FilePath>
</File>
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\gpio.c</FilePath>
</File>
</Files>
</Group>
<Group>
@@ -623,6 +623,11 @@
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\components.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
@@ -710,6 +715,51 @@
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\serial\serial.c</FilePath>
</File>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\completion.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\pipe.c</FilePath>
</File>
<File>
<FileName>portal.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\portal.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>finsh</GroupName>
<Files>
bsp/tm4c129x/project.uvproj
+1210
View File
File diff suppressed because it is too large. Load diff
components/drivers/can/SConscript
+8
View File
@@ -0,0 +1,8 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd + '/../include']
group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_CAN'], CPPPATH = CPPPATH)
Return('group')
components/drivers/can/can.c
+907
View File
File diff suppressed because it is too large. Load diff
components/drivers/can/readme-zh.txt
+132
View File
@@ -0,0 +1,132 @@
说明:
本驱动完成了can控制器硬件抽象
一 CAN Driver 注册
Can driver注册需要填充以下几个数据结构：
1、struct can_configure
{
rt_uint32_t baud_rate;
rt_uint32_t msgboxsz;
rt_uint32_t sndboxnumber;
rt_uint32_t mode :8;
rt_uint32_t privmode :8;
rt_uint32_t reserved :16;
#ifdef RT_CAN_USING_LED
const struct rt_can_led* rcvled;
const struct rt_can_led* sndled;
const struct rt_can_led* errled;
#endif /*RT_CAN_USING_LED*/
rt_uint32_t ticks;
#ifdef RT_CAN_USING_HDR
rt_uint32_t maxhdr;
#endif
};
struct can_configure 为can驱动的基本配置信息:
baud_rate :
enum CANBAUD
{
CAN1MBaud=0, // 1 MBit/sec
CAN800kBaud, // 800 kBit/sec
CAN500kBaud, // 500 kBit/sec
CAN250kBaud, // 250 kBit/sec
CAN125kBaud, // 125 kBit/sec
CAN100kBaud, // 100 kBit/sec
CAN50kBaud, // 50 kBit/sec
CAN20kBaud, // 20 kBit/sec
CAN10kBaud // 10 kBit/sec
};
配置Can的波特率。
msgboxsz : Can接收邮箱缓冲数量，本驱动在软件层开辟msgboxsz个接收邮箱。
sndboxnumber : can 发送通道数量，该配置为Can控制器实际的发送通道数量。
mode ：
#define RT_CAN_MODE_NORMAL 0 正常模式
#define RT_CAN_MODE_LISEN 1 只听模式
#define RT_CAN_MODE_LOOPBACK 2 自发自收模式
#define RT_CAN_MODE_LOOPBACKANLISEN 3 自发自收只听模式
配置Can 的工作状态。
privmode :
#define RT_CAN_MODE_PRIV 0x01 处于优先级模式，高优先级的消息优先发送。
#define RT_CAN_MODE_NOPRIV 0x00
配置Can driver的优先级模式。
#ifdef RT_CAN_USING_LED
const struct rt_can_led* rcvled;
const struct rt_can_led* sndled;
const struct rt_can_led* errled;
#endif /*RT_CAN_USING_LED*/
配置can led信息, 当前can驱动的led使用了 pin驱动，
开启RT_CAN_USING_LED时要确保当前系统已实现pin驱动。
rt_uint32_t ticks : 配置Can driver timer周期。
#ifdef RT_CAN_USING_HDR
rt_uint32_t maxhdr;
#endif
如果使用硬件过滤，则开启RT_CAN_USING_HDR, maxhdr 为Can控制器过滤表的数量。
2、struct rt_can_ops
{
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno);
int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno);
};
struct rt_can_ops 为要实现的特定的can控制器操作。
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
configure根据配置信息初始化Can控制器工作模式。
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
control 当前接受以下cmd参数：
#define RT_CAN_CMD_SET_FILTER 0x13
#define RT_CAN_CMD_SET_BAUD 0x14
#define RT_CAN_CMD_SET_MODE 0x15
#define RT_CAN_CMD_SET_PRIV 0x16
#define RT_CAN_CMD_GET_STATUS 0x17
#define RT_CAN_CMD_SET_STATUS_IND 0x18
int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno);
sendmsg向Can控制器发送数，boxno为发送通道号。
int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno);
recvmsg从Can控制器接收数据，boxno为接收通道号。
struct rt_can_device
{
struct rt_device parent;
const struct rt_can_ops *ops;
struct can_configure config;
struct rt_can_status status;
rt_uint32_t timerinitflag;
struct rt_timer timer;
struct rt_can_status_ind_type status_indicate;
#ifdef RT_CAN_USING_HDR
struct rt_can_hdr* hdr;
#endif
void *can_rx;
void *can_tx;
};
填充完成后，便可调用rt_hw_can_register完成can驱动的注册。
二、 CAN Driver 的添加：
要添加一个新的Can驱动，至少要完成以下接口。
1、struct rt_can_ops
{
rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg);
rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno);
int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno);
};
2、 rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg);
接口的
#define RT_CAN_CMD_SET_FILTER 0x13
#define RT_CAN_CMD_SET_BAUD 0x14
#define RT_CAN_CMD_SET_MODE 0x15
#define RT_CAN_CMD_SET_PRIV 0x16
#define RT_CAN_CMD_GET_STATUS 0x17
#define RT_CAN_CMD_SET_STATUS_IND 0x18
若干命令。
3、can口中断，要完接收，发送结束，以及错误中断。
#define RT_CAN_EVENT_RX_IND 0x01 /* Rx indication */
#define RT_CAN_EVENT_TX_DONE 0x02 /* Tx complete */
#define RT_CAN_EVENT_TX_FAIL 0x03 /* Tx complete */
#define RT_CAN_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */
#define RT_CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */
中断产生后，调用rt_hw_can_isr(struct rt_can_device *can, int event)
进入相应的操作，其中接收发送中断的event，最低8位为上面的事件，16到24位为通信通道号。
一个作为一个例子，参见bsp/stm32f10x/driver下的bxcan.c 。
三、CAN Driver的使用：
一个使用的例子，参数bsp/stm32f10x/applications下的canapp.c
四、当前Can驱动，没有实现轮模式，采用中断模式，bxcan驱动工作在loopback模式下的时候不能读数据。
五、当前Can驱动，在stm32f105上测试，暂无问题。
components/drivers/include/drivers/can.h
+293
View File
File diff suppressed because it is too large. Load diff
components/drivers/include/rtdevice.h
+4
View File
@@ -366,6 +366,10 @@ rt_inline void rt_work_init(struct rt_work* work, void (*work_func)(struct rt_wo
#include "drivers/pin.h"
#endif
#ifdef RT_USING_CAN
#include "drivers/can.h"
#endif
#ifdef __cplusplus
}
#endif
components/drivers/spi/spi_flash_w25qxx.c
+5 -2
View File
@@ -13,6 +13,7 @@
* 2012-05-06 aozima can page write.
* 2012-08-23 aozima add flash lock.
* 2012-08-24 aozima fixed write status register BUG.
* 2015-05-13 bernard add GD25Q flash ID.
*/
#include <stdint.h>
@@ -28,8 +29,10 @@
#define PAGE_SIZE 4096
/* JEDEC Manufacturer¡¯s ID */
/* JEDEC Manufacturer��s ID */
#define MF_ID (0xEF)
#define GD_ID (0xC8)
/* JEDEC Device ID: Memory type and Capacity */
#define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */
#define MTC_W25Q16_DW (0x6015) /* W25Q16DW */
@@ -297,7 +300,7 @@ rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_nam
flash_unlock(&spi_flash_device);
if(id_recv[0] != MF_ID)
if(id_recv[0] != MF_ID && id_recv[0] != GD_ID)
{
FLASH_TRACE("Manufacturers ID error!\r\n");
FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
components/net/lwip/apps/ftpd.c
+229 -35
View File
File diff suppressed because it is too large. Load diff
components/net/lwip_dhcpd/dhcp_server.c
+16 -5
View File
@@ -376,13 +376,24 @@ static void dhcpd_thread_entry(void *parameter)
void dhcpd_start(char* netif_name)
{
rt_thread_t thread;
struct netif *netif = RT_NULL;
struct netif *netif = netif_list;
/* find ethernet interface. */
netif = netif_find(netif_name);
if (netif == RT_NULL)
if(strlen(netif_name) > sizeof(netif->name))
{
DEBUG_PRINTF("Not found network interface:%s\n", netif_name);
rt_kprintf("network interface name too long!\r\n");
return;
}
while(netif != RT_NULL)
{
if(strncmp(netif_name, netif->name, sizeof(netif->name)) == 0)
break;
netif = netif->next;
if( netif == RT_NULL )
{
rt_kprintf("network interface: %s not found!\r\n", netif_name);
return;
}
}
thread = rt_thread_create("dhcpd",
libcpu/arm/am335x/mmu.c
+1 -1
View File
@@ -15,7 +15,7 @@
#include <rtthread.h>
#include "am33xx.h"
#define DESC_SEC (0x2|(1<<4))
#define DESC_SEC (0x2)
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
libcpu/arm/cortex-m0/context_rvds.S
+2 -2
View File
@@ -183,13 +183,11 @@ rt_hw_context_switch_to PROC
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
NOP
; restore MSP
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
; enable interrupts at processor level
@@ -216,4 +214,6 @@ HardFault_Handler PROC
POP {pc}
ENDP
ALIGN 4
END
libcpu/arm/cortex-m3/context_rvds.S
+3 -3
View File
@@ -177,7 +177,6 @@ rt_hw_context_switch_to PROC
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
NOP
ENDP
IMPORT rt_hw_hard_fault_exception
@@ -203,5 +202,6 @@ HardFault_Handler PROC
BX lr
ENDP
NOP
END
ALIGN 4
END
libcpu/arm/cortex-m4/context_rvds.S
+2 -1
View File
@@ -218,7 +218,6 @@ rt_hw_context_switch_to PROC
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
NOP
ENDP
IMPORT rt_hw_hard_fault_exception
@@ -235,4 +234,6 @@ HardFault_Handler PROC
BX lr
ENDP
ALIGN 4
END
tools/buildbot.py
+11
View File
@@ -19,6 +19,17 @@ elif sys.argv[1] == 'clean':
command = ' -c'
elif sys.argv[1] == 'project':
command = ' --target=mdk -s'
projects = os.listdir(BSP_ROOT)
for item in projects:
project_dir = os.path.join(BSP_ROOT, item)
if os.path.isfile(os.path.join(project_dir, 'template.uvproj')):
print ('prepare MDK project file on ' + project_dir)
os.system('scons --directory=' + project_dir + command)
sys.exit(0)
else:
usage()
sys.exit(0)